(0h2)) \n when _T_581 : \n node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_584 = and(_T_582, _T_583) \n node _T_585 = eq(io.in.a.bits.source, UInt<1>(0h1)) \n node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_587 = or(_T_585, _T_586) \n node _T_588 = and(_T_584, _T_587) \n node _T_589 = or(UInt<1>(0h0), _T_588) \n node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_591 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_592 = and(_T_590, _T_591) \n node _T_593 = or(UInt<1>(0h0), _T_592) \n node _T_594 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_595 = cvt(_T_594) \n node _T_596 = and(_T_595, asSInt(UInt<14>(0h2000))) \n node _T_597 = asSInt(_T_596) \n node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) \n node _T_599 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_600 = cvt(_T_599) \n node _T_601 = and(_T_600, asSInt(UInt<13>(0h1000))) \n node _T_602 = asSInt(_T_601) \n node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) \n node _T_604 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_605 = cvt(_T_604) \n node _T_606 = and(_T_605, asSInt(UInt<18>(0h2f000))) \n node _T_607 = asSInt(_T_606) \n node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) \n node _T_609 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_610 = cvt(_T_609) \n node _T_611 = and(_T_610, asSInt(UInt<17>(0h10000))) \n node _T_612 = asSInt(_T_611) \n node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) \n node _T_614 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_615 = cvt(_T_614) \n node _T_616 = and(_T_615, asSInt(UInt<27>(0h4000000))) \n node _T_617 = asSInt(_T_616) \n node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0))) \n node _T_619 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_620 = cvt(_T_619) \n node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000))) \n node _T_622 = asSInt(_T_621) \n node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0))) \n node _T_624 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_625 = cvt(_T_624) \n node _T_626 = and(_T_625, asSInt(UInt<19>(0h40000))) \n node _T_627 = asSInt(_T_626) \n node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) \n node _T_629 = or(_T_598, _T_603) \n node _T_630 = or(_T_629, _T_608) \n node _T_631 = or(_T_630, _T_613) \n node _T_632 = or(_T_631, _T_618) \n node _T_633 = or(_T_632, _T_623) \n node _T_634 = or(_T_633, _T_628) \n node _T_635 = and(_T_593, _T_634) \n node _T_636 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_637 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_638 = cvt(_T_637) \n node _T_639 = and(_T_638, asSInt(UInt<17>(0h10000))) \n node _T_640 = asSInt(_T_639) \n node _T_641 = eq(_T_640, asSInt(UInt<1>(0h0))) \n node _T_642 = and(_T_636, _T_641) \n node _T_643 = or(UInt<1>(0h0), _T_635) \n node _T_644 = or(_T_643, _T_642) \n node _T_645 = and(_T_589, _T_644) \n node _T_646 = asUInt(reset) \n node _T_647 = eq(_T_646, UInt<1>(0h0)) \n when _T_647 : \n node _T_648 = eq(_T_645, UInt<1>(0h0)) \n when _T_648 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_645, UInt<1>(0h1), \"\") : assert_36 \n node _T_649 = asUInt(reset) \n node _T_650 = eq(_T_649, UInt<1>(0h0)) \n when _T_650 : \n node _T_651 = eq(source_ok, UInt<1>(0h0)) \n when _T_651 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_652 = asUInt(reset) \n node _T_653 = eq(_T_652, UInt<1>(0h0)) \n when _T_653 : \n node _T_654 = eq(is_aligned, UInt<1>(0h0)) \n when _T_654 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_655 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_656 = asUInt(reset) \n node _T_657 = eq(_T_656, UInt<1>(0h0)) \n when _T_657 : \n node _T_658 = eq(_T_655, UInt<1>(0h0)) \n when _T_658 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_655, UInt<1>(0h1), \"\") : assert_39 \n node _T_659 = eq(io.in.a.bits.mask, mask) \n node _T_660 = asUInt(reset) \n node _T_661 = eq(_T_660, UInt<1>(0h0)) \n when _T_661 : \n node _T_662 = eq(_T_659, UInt<1>(0h0)) \n when _T_662 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_659, UInt<1>(0h1), \"\") : assert_40 \n node _T_663 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_663 : \n node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_665 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_666 = and(_T_664, _T_665) \n node _T_667 = eq(io.in.a.bits.source, UInt<1>(0h1)) \n node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_669 = or(_T_667, _T_668) \n node _T_670 = and(_T_666, _T_669) \n node _T_671 = or(UInt<1>(0h0), _T_670) \n node _T_672 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_673 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_674 = and(_T_672, _T_673) \n node _T_675 = or(UInt<1>(0h0), _T_674) \n node _T_676 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_677 = cvt(_T_676) \n node _T_678 = and(_T_677, asSInt(UInt<14>(0h2000))) \n node _T_679 = asSInt(_T_678) \n node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0))) \n node _T_681 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_682 = cvt(_T_681) \n node _T_683 = and(_T_682, asSInt(UInt<13>(0h1000))) \n node _T_684 = asSInt(_T_683) \n node _T_685 = eq(_T_684, asSInt(UInt<1>(0h0))) \n node _T_686 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_687 = cvt(_T_686) \n node _T_688 = and(_T_687, asSInt(UInt<18>(0h2f000))) \n node _T_689 = asSInt(_T_688) \n node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) \n node _T_691 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_692 = cvt(_T_691) \n node _T_693 = and(_T_692, asSInt(UInt<17>(0h10000))) \n node _T_694 = asSInt(_T_693) \n node _T_695 = eq(_T_694, asSInt(UInt<1>(0h0))) \n node _T_696 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_697 = cvt(_T_696) \n node _T_698 = and(_T_697, asSInt(UInt<27>(0h4000000))) \n node _T_699 = asSInt(_T_698) \n node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) \n node _T_701 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_702 = cvt(_T_701) \n node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000))) \n node _T_704 = asSInt(_T_703) \n node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0))) \n node _T_706 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_707 = cvt(_T_706) \n node _T_708 = and(_T_707, asSInt(UInt<19>(0h40000))) \n node _T_709 = asSInt(_T_708) \n node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) \n node _T_711 = or(_T_680, _T_685) \n node _T_712 = or(_T_711, _T_690) \n node _T_713 = or(_T_712, _T_695) \n node _T_714 = or(_T_713, _T_700) \n node _T_715 = or(_T_714, _T_705) \n node _T_716 = or(_T_715, _T_710) \n node _T_717 = and(_T_675, _T_716) \n node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_720 = cvt(_T_719) \n node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) \n node _T_722 = asSInt(_T_721) \n node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) \n node _T_724 = and(_T_718, _T_723) \n node _T_725 = or(UInt<1>(0h0), _T_717) \n node _T_726 = or(_T_725, _T_724) \n node _T_727 = and(_T_671, _T_726) \n node _T_728 = asUInt(reset) \n node _T_729 = eq(_T_728, UInt<1>(0h0)) \n when _T_729 : \n node _T_730 = eq(_T_727, UInt<1>(0h0)) \n when _T_730 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_727, UInt<1>(0h1), \"\") : assert_41 \n node _T_731 = asUInt(reset) \n node _T_732 = eq(_T_731, UInt<1>(0h0)) \n when _T_732 : \n node _T_733 = eq(source_ok, UInt<1>(0h0)) \n when _T_733 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_734 = asUInt(reset) \n node _T_735 = eq(_T_734, UInt<1>(0h0)) \n when _T_735 : \n node _T_736 = eq(is_aligned, UInt<1>(0h0)) \n when _T_736 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_737 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_738 = asUInt(reset) \n node _T_739 = eq(_T_738, UInt<1>(0h0)) \n when _T_739 : \n node _T_740 = eq(_T_737, UInt<1>(0h0)) \n when _T_740 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_737, UInt<1>(0h1), \"\") : assert_44 \n node _T_741 = eq(io.in.a.bits.mask, mask) \n node _T_742 = asUInt(reset) \n node _T_743 = eq(_T_742, UInt<1>(0h0)) \n when _T_743 : \n node _T_744 = eq(_T_741, UInt<1>(0h0)) \n when _T_744 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_741, UInt<1>(0h1), \"\") : assert_45 \n node _T_745 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_745 : \n node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_748 = and(_T_746, _T_747) \n node _T_749 = eq(io.in.a.bits.source, UInt<1>(0h1)) \n node _T_750 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_751 = or(_T_749, _T_750) \n node _T_752 = and(_T_748, _T_751) \n node _T_753 = or(UInt<1>(0h0), _T_752) \n node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_756 = and(_T_754, _T_755) \n node _T_757 = or(UInt<1>(0h0), _T_756) \n node _T_758 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_759 = cvt(_T_758) \n node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000))) \n node _T_761 = asSInt(_T_760) \n node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0))) \n node _T_763 = and(_T_757, _T_762) \n node _T_764 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_765 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_766 = cvt(_T_765) \n node _T_767 = and(_T_766, asSInt(UInt<14>(0h2000))) \n node _T_768 = asSInt(_T_767) \n node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) \n node _T_770 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_771 = cvt(_T_770) \n node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) \n node _T_773 = asSInt(_T_772) \n node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) \n node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_776 = cvt(_T_775) \n node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) \n node _T_778 = asSInt(_T_777) \n node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) \n node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_781 = cvt(_T_780) \n node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) \n node _T_783 = asSInt(_T_782) \n node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) \n node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_786 = cvt(_T_785) \n node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) \n node _T_788 = asSInt(_T_787) \n node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) \n node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_791 = cvt(_T_790) \n node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) \n node _T_793 = asSInt(_T_792) \n node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) \n node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_796 = cvt(_T_795) \n node _T_797 = and(_T_796, asSInt(UInt<19>(0h40000))) \n node _T_798 = asSInt(_T_797) \n node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) \n node _T_800 = or(_T_769, _T_774) \n node _T_801 = or(_T_800, _T_779) \n node _T_802 = or(_T_801, _T_784) \n node _T_803 = or(_T_802, _T_789) \n node _T_804 = or(_T_803, _T_794) \n node _T_805 = or(_T_804, _T_799) \n node _T_806 = and(_T_764, _T_805) \n node _T_807 = or(UInt<1>(0h0), _T_763) \n node _T_808 = or(_T_807, _T_806) \n node _T_809 = and(_T_753, _T_808) \n node _T_810 = asUInt(reset) \n node _T_811 = eq(_T_810, UInt<1>(0h0)) \n when _T_811 : \n node _T_812 = eq(_T_809, UInt<1>(0h0)) \n when _T_812 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_809, UInt<1>(0h1), \"\") : assert_46 \n node _T_813 = asUInt(reset) \n node _T_814 = eq(_T_813, UInt<1>(0h0)) \n when _T_814 : \n node _T_815 = eq(source_ok, UInt<1>(0h0)) \n when _T_815 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_816 = asUInt(reset) \n node _T_817 = eq(_T_816, UInt<1>(0h0)) \n when _T_817 : \n node _T_818 = eq(is_aligned, UInt<1>(0h0)) \n when _T_818 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_819 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_820 = asUInt(reset) \n node _T_821 = eq(_T_820, UInt<1>(0h0)) \n when _T_821 : \n node _T_822 = eq(_T_819, UInt<1>(0h0)) \n when _T_822 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_819, UInt<1>(0h1), \"\") : assert_49 \n node _T_823 = eq(io.in.a.bits.mask, mask) \n node _T_824 = asUInt(reset) \n node _T_825 = eq(_T_824, UInt<1>(0h0)) \n when _T_825 : \n node _T_826 = eq(_T_823, UInt<1>(0h0)) \n when _T_826 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_823, UInt<1>(0h1), \"\") : assert_50 \n node _T_827 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_828 = asUInt(reset) \n node _T_829 = eq(_T_828, UInt<1>(0h0)) \n when _T_829 : \n node _T_830 = eq(_T_827, UInt<1>(0h0)) \n when _T_830 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_827, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_831 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_832 = asUInt(reset) \n node _T_833 = eq(_T_832, UInt<1>(0h0)) \n when _T_833 : \n node _T_834 = eq(_T_831, UInt<1>(0h0)) \n when _T_834 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_831, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h1)) \n node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE_1 : UInt<1>[2] \n connect _source_ok_WIRE_1[0], _source_ok_T_2 \n connect _source_ok_WIRE_1[1], _source_ok_T_3 \n node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_835 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_835 : \n node _T_836 = asUInt(reset) \n node _T_837 = eq(_T_836, UInt<1>(0h0)) \n when _T_837 : \n node _T_838 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_838 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_839 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_840 = asUInt(reset) \n node _T_841 = eq(_T_840, UInt<1>(0h0)) \n when _T_841 : \n node _T_842 = eq(_T_839, UInt<1>(0h0)) \n when _T_842 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_839, UInt<1>(0h1), \"\") : assert_54 \n node _T_843 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_844 = asUInt(reset) \n node _T_845 = eq(_T_844, UInt<1>(0h0)) \n when _T_845 : \n node _T_846 = eq(_T_843, UInt<1>(0h0)) \n when _T_846 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_843, UInt<1>(0h1), \"\") : assert_55 \n node _T_847 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_848 = asUInt(reset) \n node _T_849 = eq(_T_848, UInt<1>(0h0)) \n when _T_849 : \n node _T_850 = eq(_T_847, UInt<1>(0h0)) \n when _T_850 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_847, UInt<1>(0h1), \"\") : assert_56 \n node _T_851 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_852 = asUInt(reset) \n node _T_853 = eq(_T_852, UInt<1>(0h0)) \n when _T_853 : \n node _T_854 = eq(_T_851, UInt<1>(0h0)) \n when _T_854 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_851, UInt<1>(0h1), \"\") : assert_57 \n node _T_855 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_855 : \n node _T_856 = asUInt(reset) \n node _T_857 = eq(_T_856, UInt<1>(0h0)) \n when _T_857 : \n node _T_858 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_858 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_859 = asUInt(reset) \n node _T_860 = eq(_T_859, UInt<1>(0h0)) \n when _T_860 : \n node _T_861 = eq(sink_ok, UInt<1>(0h0)) \n when _T_861 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_862 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_863 = asUInt(reset) \n node _T_864 = eq(_T_863, UInt<1>(0h0)) \n when _T_864 : \n node _T_865 = eq(_T_862, UInt<1>(0h0)) \n when _T_865 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_862, UInt<1>(0h1), \"\") : assert_60 \n node _T_866 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_867 = asUInt(reset) \n node _T_868 = eq(_T_867, UInt<1>(0h0)) \n when _T_868 : \n node _T_869 = eq(_T_866, UInt<1>(0h0)) \n when _T_869 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_866, UInt<1>(0h1), \"\") : assert_61 \n node _T_870 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_871 = asUInt(reset) \n node _T_872 = eq(_T_871, UInt<1>(0h0)) \n when _T_872 : \n node _T_873 = eq(_T_870, UInt<1>(0h0)) \n when _T_873 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_870, UInt<1>(0h1), \"\") : assert_62 \n node _T_874 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_875 = asUInt(reset) \n node _T_876 = eq(_T_875, UInt<1>(0h0)) \n when _T_876 : \n node _T_877 = eq(_T_874, UInt<1>(0h0)) \n when _T_877 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_874, UInt<1>(0h1), \"\") : assert_63 \n node _T_878 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_879 = or(UInt<1>(0h1), _T_878) \n node _T_880 = asUInt(reset) \n node _T_881 = eq(_T_880, UInt<1>(0h0)) \n when _T_881 : \n node _T_882 = eq(_T_879, UInt<1>(0h0)) \n when _T_882 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_879, UInt<1>(0h1), \"\") : assert_64 \n node _T_883 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_883 : \n node _T_884 = asUInt(reset) \n node _T_885 = eq(_T_884, UInt<1>(0h0)) \n when _T_885 : \n node _T_886 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_886 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_887 = asUInt(reset) \n node _T_888 = eq(_T_887, UInt<1>(0h0)) \n when _T_888 : \n node _T_889 = eq(sink_ok, UInt<1>(0h0)) \n when _T_889 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_890 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_891 = asUInt(reset) \n node _T_892 = eq(_T_891, UInt<1>(0h0)) \n when _T_892 : \n node _T_893 = eq(_T_890, UInt<1>(0h0)) \n when _T_893 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_890, UInt<1>(0h1), \"\") : assert_67 \n node _T_894 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_895 = asUInt(reset) \n node _T_896 = eq(_T_895, UInt<1>(0h0)) \n when _T_896 : \n node _T_897 = eq(_T_894, UInt<1>(0h0)) \n when _T_897 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_894, UInt<1>(0h1), \"\") : assert_68 \n node _T_898 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_899 = asUInt(reset) \n node _T_900 = eq(_T_899, UInt<1>(0h0)) \n when _T_900 : \n node _T_901 = eq(_T_898, UInt<1>(0h0)) \n when _T_901 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_898, UInt<1>(0h1), \"\") : assert_69 \n node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_903 = or(_T_902, io.in.d.bits.corrupt) \n node _T_904 = asUInt(reset) \n node _T_905 = eq(_T_904, UInt<1>(0h0)) \n when _T_905 : \n node _T_906 = eq(_T_903, UInt<1>(0h0)) \n when _T_906 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_903, UInt<1>(0h1), \"\") : assert_70 \n node _T_907 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_908 = or(UInt<1>(0h1), _T_907) \n node _T_909 = asUInt(reset) \n node _T_910 = eq(_T_909, UInt<1>(0h0)) \n when _T_910 : \n node _T_911 = eq(_T_908, UInt<1>(0h0)) \n when _T_911 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_908, UInt<1>(0h1), \"\") : assert_71 \n node _T_912 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_912 : \n node _T_913 = asUInt(reset) \n node _T_914 = eq(_T_913, UInt<1>(0h0)) \n when _T_914 : \n node _T_915 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_915 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_916 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_917 = asUInt(reset) \n node _T_918 = eq(_T_917, UInt<1>(0h0)) \n when _T_918 : \n node _T_919 = eq(_T_916, UInt<1>(0h0)) \n when _T_919 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_916, UInt<1>(0h1), \"\") : assert_73 \n node _T_920 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_921 = asUInt(reset) \n node _T_922 = eq(_T_921, UInt<1>(0h0)) \n when _T_922 : \n node _T_923 = eq(_T_920, UInt<1>(0h0)) \n when _T_923 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_920, UInt<1>(0h1), \"\") : assert_74 \n node _T_924 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_925 = or(UInt<1>(0h1), _T_924) \n node _T_926 = asUInt(reset) \n node _T_927 = eq(_T_926, UInt<1>(0h0)) \n when _T_927 : \n node _T_928 = eq(_T_925, UInt<1>(0h0)) \n when _T_928 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_925, UInt<1>(0h1), \"\") : assert_75 \n node _T_929 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_929 : \n node _T_930 = asUInt(reset) \n node _T_931 = eq(_T_930, UInt<1>(0h0)) \n when _T_931 : \n node _T_932 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_932 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_934 = asUInt(reset) \n node _T_935 = eq(_T_934, UInt<1>(0h0)) \n when _T_935 : \n node _T_936 = eq(_T_933, UInt<1>(0h0)) \n when _T_936 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_933, UInt<1>(0h1), \"\") : assert_77 \n node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_938 = or(_T_937, io.in.d.bits.corrupt) \n node _T_939 = asUInt(reset) \n node _T_940 = eq(_T_939, UInt<1>(0h0)) \n when _T_940 : \n node _T_941 = eq(_T_938, UInt<1>(0h0)) \n when _T_941 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_938, UInt<1>(0h1), \"\") : assert_78 \n node _T_942 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_943 = or(UInt<1>(0h1), _T_942) \n node _T_944 = asUInt(reset) \n node _T_945 = eq(_T_944, UInt<1>(0h0)) \n when _T_945 : \n node _T_946 = eq(_T_943, UInt<1>(0h0)) \n when _T_946 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_943, UInt<1>(0h1), \"\") : assert_79 \n node _T_947 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_947 : \n node _T_948 = asUInt(reset) \n node _T_949 = eq(_T_948, UInt<1>(0h0)) \n when _T_949 : \n node _T_950 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_950 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_951 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_952 = asUInt(reset) \n node _T_953 = eq(_T_952, UInt<1>(0h0)) \n when _T_953 : \n node _T_954 = eq(_T_951, UInt<1>(0h0)) \n when _T_954 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_951, UInt<1>(0h1), \"\") : assert_81 \n node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_956 = asUInt(reset) \n node _T_957 = eq(_T_956, UInt<1>(0h0)) \n when _T_957 : \n node _T_958 = eq(_T_955, UInt<1>(0h0)) \n when _T_958 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_955, UInt<1>(0h1), \"\") : assert_82 \n node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_960 = or(UInt<1>(0h1), _T_959) \n node _T_961 = asUInt(reset) \n node _T_962 = eq(_T_961, UInt<1>(0h0)) \n when _T_962 : \n node _T_963 = eq(_T_960, UInt<1>(0h0)) \n when _T_963 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_960, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_964 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_965 = asUInt(reset) \n node _T_966 = eq(_T_965, UInt<1>(0h0)) \n when _T_966 : \n node _T_967 = eq(_T_964, UInt<1>(0h0)) \n when _T_967 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_964, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_968 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_969 = asUInt(reset) \n node _T_970 = eq(_T_969, UInt<1>(0h0)) \n when _T_970 : \n node _T_971 = eq(_T_968, UInt<1>(0h0)) \n when _T_971 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_968, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_972 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_973 = asUInt(reset) \n node _T_974 = eq(_T_973, UInt<1>(0h0)) \n when _T_974 : \n node _T_975 = eq(_T_972, UInt<1>(0h0)) \n when _T_975 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_972, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_976 = eq(a_first, UInt<1>(0h0)) \n node _T_977 = and(io.in.a.valid, _T_976) \n when _T_977 : \n node _T_978 = eq(io.in.a.bits.opcode, opcode) \n node _T_979 = asUInt(reset) \n node _T_980 = eq(_T_979, UInt<1>(0h0)) \n when _T_980 : \n node _T_981 = eq(_T_978, UInt<1>(0h0)) \n when _T_981 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_978, UInt<1>(0h1), \"\") : assert_87 \n node _T_982 = eq(io.in.a.bits.param, param) \n node _T_983 = asUInt(reset) \n node _T_984 = eq(_T_983, UInt<1>(0h0)) \n when _T_984 : \n node _T_985 = eq(_T_982, UInt<1>(0h0)) \n when _T_985 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_982, UInt<1>(0h1), \"\") : assert_88 \n node _T_986 = eq(io.in.a.bits.size, size) \n node _T_987 = asUInt(reset) \n node _T_988 = eq(_T_987, UInt<1>(0h0)) \n when _T_988 : \n node _T_989 = eq(_T_986, UInt<1>(0h0)) \n when _T_989 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_986, UInt<1>(0h1), \"\") : assert_89 \n node _T_990 = eq(io.in.a.bits.source, source) \n node _T_991 = asUInt(reset) \n node _T_992 = eq(_T_991, UInt<1>(0h0)) \n when _T_992 : \n node _T_993 = eq(_T_990, UInt<1>(0h0)) \n when _T_993 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_990, UInt<1>(0h1), \"\") : assert_90 \n node _T_994 = eq(io.in.a.bits.address, address) \n node _T_995 = asUInt(reset) \n node _T_996 = eq(_T_995, UInt<1>(0h0)) \n when _T_996 : \n node _T_997 = eq(_T_994, UInt<1>(0h0)) \n when _T_997 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_994, UInt<1>(0h1), \"\") : assert_91 \n node _T_998 = and(io.in.a.ready, io.in.a.valid) \n node _T_999 = and(_T_998, a_first) \n when _T_999 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1000 = eq(d_first, UInt<1>(0h0)) \n node _T_1001 = and(io.in.d.valid, _T_1000) \n when _T_1001 : \n node _T_1002 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1003 = asUInt(reset) \n node _T_1004 = eq(_T_1003, UInt<1>(0h0)) \n when _T_1004 : \n node _T_1005 = eq(_T_1002, UInt<1>(0h0)) \n when _T_1005 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1002, UInt<1>(0h1), \"\") : assert_92 \n node _T_1006 = eq(io.in.d.bits.param, param_1) \n node _T_1007 = asUInt(reset) \n node _T_1008 = eq(_T_1007, UInt<1>(0h0)) \n when _T_1008 : \n node _T_1009 = eq(_T_1006, UInt<1>(0h0)) \n when _T_1009 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1006, UInt<1>(0h1), \"\") : assert_93 \n node _T_1010 = eq(io.in.d.bits.size, size_1) \n node _T_1011 = asUInt(reset) \n node _T_1012 = eq(_T_1011, UInt<1>(0h0)) \n when _T_1012 : \n node _T_1013 = eq(_T_1010, UInt<1>(0h0)) \n when _T_1013 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1010, UInt<1>(0h1), \"\") : assert_94 \n node _T_1014 = eq(io.in.d.bits.source, source_1) \n node _T_1015 = asUInt(reset) \n node _T_1016 = eq(_T_1015, UInt<1>(0h0)) \n when _T_1016 : \n node _T_1017 = eq(_T_1014, UInt<1>(0h0)) \n when _T_1017 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1014, UInt<1>(0h1), \"\") : assert_95 \n node _T_1018 = eq(io.in.d.bits.sink, sink) \n node _T_1019 = asUInt(reset) \n node _T_1020 = eq(_T_1019, UInt<1>(0h0)) \n when _T_1020 : \n node _T_1021 = eq(_T_1018, UInt<1>(0h0)) \n when _T_1021 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1018, UInt<1>(0h1), \"\") : assert_96 \n node _T_1022 = eq(io.in.d.bits.denied, denied) \n node _T_1023 = asUInt(reset) \n node _T_1024 = eq(_T_1023, UInt<1>(0h0)) \n when _T_1024 : \n node _T_1025 = eq(_T_1022, UInt<1>(0h0)) \n when _T_1025 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1022, UInt<1>(0h1), \"\") : assert_97 \n node _T_1026 = and(io.in.d.ready, io.in.d.valid) \n node _T_1027 = and(_T_1026, d_first) \n when _T_1027 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0) \n regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<2> \n connect a_set, UInt<2>(0h0) \n wire a_set_wo_ready : UInt<2> \n connect a_set_wo_ready, UInt<2>(0h0) \n wire a_opcodes_set : UInt<8> \n connect a_opcodes_set, UInt<8>(0h0) \n wire a_sizes_set : UInt<16> \n connect a_sizes_set, UInt<16>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<8> \n connect a_size_lookup, UInt<8>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<5> \n connect a_sizes_set_interm, UInt<5>(0h0) \n node _T_1028 = and(io.in.a.valid, a_first_1) \n node _T_1029 = and(_T_1028, UInt<1>(0h1)) \n when _T_1029 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1030 = and(io.in.a.ready, io.in.a.valid) \n node _T_1031 = and(_T_1030, a_first_1) \n node _T_1032 = and(_T_1031, UInt<1>(0h1)) \n when _T_1032 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1033 = dshr(inflight, io.in.a.bits.source) \n node _T_1034 = bits(_T_1033, 0, 0) \n node _T_1035 = eq(_T_1034, UInt<1>(0h0)) \n node _T_1036 = asUInt(reset) \n node _T_1037 = eq(_T_1036, UInt<1>(0h0)) \n when _T_1037 : \n node _T_1038 = eq(_T_1035, UInt<1>(0h0)) \n when _T_1038 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1035, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<2> \n connect d_clr, UInt<2>(0h0) \n wire d_clr_wo_ready : UInt<2> \n connect d_clr_wo_ready, UInt<2>(0h0) \n wire d_opcodes_clr : UInt<8> \n connect d_opcodes_clr, UInt<8>(0h0) \n wire d_sizes_clr : UInt<16> \n connect d_sizes_clr, UInt<16>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1039 = and(io.in.d.valid, d_first_1) \n node _T_1040 = and(_T_1039, UInt<1>(0h1)) \n node _T_1041 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1042 = and(_T_1040, _T_1041) \n when _T_1042 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1043 = and(io.in.d.ready, io.in.d.valid) \n node _T_1044 = and(_T_1043, d_first_1) \n node _T_1045 = and(_T_1044, UInt<1>(0h1)) \n node _T_1046 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1047 = and(_T_1045, _T_1046) \n when _T_1047 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1048 = and(io.in.d.valid, d_first_1) \n node _T_1049 = and(_T_1048, UInt<1>(0h1)) \n node _T_1050 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1051 = and(_T_1049, _T_1050) \n when _T_1051 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1052 = dshr(inflight, io.in.d.bits.source) \n node _T_1053 = bits(_T_1052, 0, 0) \n node _T_1054 = or(_T_1053, same_cycle_resp) \n node _T_1055 = asUInt(reset) \n node _T_1056 = eq(_T_1055, UInt<1>(0h0)) \n when _T_1056 : \n node _T_1057 = eq(_T_1054, UInt<1>(0h0)) \n when _T_1057 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1054, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1058 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1059 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1060 = or(_T_1058, _T_1059) \n node _T_1061 = asUInt(reset) \n node _T_1062 = eq(_T_1061, UInt<1>(0h0)) \n when _T_1062 : \n node _T_1063 = eq(_T_1060, UInt<1>(0h0)) \n when _T_1063 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1060, UInt<1>(0h1), \"\") : assert_100 \n node _T_1064 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1065 = asUInt(reset) \n node _T_1066 = eq(_T_1065, UInt<1>(0h0)) \n when _T_1066 : \n node _T_1067 = eq(_T_1064, UInt<1>(0h0)) \n when _T_1067 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1064, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1068 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1069 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1070 = or(_T_1068, _T_1069) \n node _T_1071 = asUInt(reset) \n node _T_1072 = eq(_T_1071, UInt<1>(0h0)) \n when _T_1072 : \n node _T_1073 = eq(_T_1070, UInt<1>(0h0)) \n when _T_1073 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1070, UInt<1>(0h1), \"\") : assert_102 \n node _T_1074 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1075 = asUInt(reset) \n node _T_1076 = eq(_T_1075, UInt<1>(0h0)) \n when _T_1076 : \n node _T_1077 = eq(_T_1074, UInt<1>(0h0)) \n when _T_1077 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1074, UInt<1>(0h1), \"\") : assert_103 \n node _T_1078 = and(io.in.d.valid, d_first_1) \n node _T_1079 = and(_T_1078, a_first_1) \n node _T_1080 = and(_T_1079, io.in.a.valid) \n node _T_1081 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1082 = and(_T_1080, _T_1081) \n node _T_1083 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1084 = and(_T_1082, _T_1083) \n when _T_1084 : \n node _T_1085 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1086 = or(_T_1085, io.in.a.ready) \n node _T_1087 = asUInt(reset) \n node _T_1088 = eq(_T_1087, UInt<1>(0h0)) \n when _T_1088 : \n node _T_1089 = eq(_T_1086, UInt<1>(0h0)) \n when _T_1089 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1086, UInt<1>(0h1), \"\") : assert_104 \n node _T_1090 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_1091 = orr(a_set_wo_ready) \n node _T_1092 = eq(_T_1091, UInt<1>(0h0)) \n node _T_1093 = or(_T_1090, _T_1092) \n node _T_1094 = asUInt(reset) \n node _T_1095 = eq(_T_1094, UInt<1>(0h0)) \n when _T_1095 : \n node _T_1096 = eq(_T_1093, UInt<1>(0h0)) \n when _T_1096 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1093, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_64 \n node _T_1097 = orr(inflight) \n node _T_1098 = eq(_T_1097, UInt<1>(0h0)) \n node _T_1099 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1100 = or(_T_1098, _T_1099) \n node _T_1101 = lt(watchdog, plusarg_reader.out) \n node _T_1102 = or(_T_1100, _T_1101) \n node _T_1103 = asUInt(reset) \n node _T_1104 = eq(_T_1103, UInt<1>(0h0)) \n when _T_1104 : \n node _T_1105 = eq(_T_1102, UInt<1>(0h0)) \n when _T_1105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1102, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1106 = and(io.in.a.ready, io.in.a.valid) \n node _T_1107 = and(io.in.d.ready, io.in.d.valid) \n node _T_1108 = or(_T_1106, _T_1107) \n when _T_1108 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0) \n regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<2> \n connect c_set, UInt<2>(0h0) \n wire c_set_wo_ready : UInt<2> \n connect c_set_wo_ready, UInt<2>(0h0) \n wire c_opcodes_set : UInt<8> \n connect c_opcodes_set, UInt<8>(0h0) \n wire c_sizes_set : UInt<16> \n connect c_sizes_set, UInt<16>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<8> \n connect c_size_lookup, UInt<8>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<5> \n connect c_sizes_set_interm, UInt<5>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_1109 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<1>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_1110 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_1111 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_1112 = and(_T_1110, _T_1111) \n node _T_1113 = and(_T_1109, _T_1112) \n when _T_1113 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<1>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1114 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_1115 = and(_T_1114, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<1>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1116 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1117 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1118 = and(_T_1116, _T_1117) \n node _T_1119 = and(_T_1115, _T_1118) \n when _T_1119 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<32>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<1>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1120 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_1121 = bits(_T_1120, 0, 0) \n node _T_1122 = eq(_T_1121, UInt<1>(0h0)) \n node _T_1123 = asUInt(reset) \n node _T_1124 = eq(_T_1123, UInt<1>(0h0)) \n when _T_1124 : \n node _T_1125 = eq(_T_1122, UInt<1>(0h0)) \n when _T_1125 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1122, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<2> \n connect d_clr_1, UInt<2>(0h0) \n wire d_clr_wo_ready_1 : UInt<2> \n connect d_clr_wo_ready_1, UInt<2>(0h0) \n wire d_opcodes_clr_1 : UInt<8> \n connect d_opcodes_clr_1, UInt<8>(0h0) \n wire d_sizes_clr_1 : UInt<16> \n connect d_sizes_clr_1, UInt<16>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1126 = and(io.in.d.valid, d_first_2) \n node _T_1127 = and(_T_1126, UInt<1>(0h1)) \n node _T_1128 = and(_T_1127, d_release_ack_1) \n when _T_1128 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1129 = and(io.in.d.ready, io.in.d.valid) \n node _T_1130 = and(_T_1129, d_first_2) \n node _T_1131 = and(_T_1130, UInt<1>(0h1)) \n node _T_1132 = and(_T_1131, d_release_ack_1) \n when _T_1132 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1133 = and(io.in.d.valid, d_first_2) \n node _T_1134 = and(_T_1133, UInt<1>(0h1)) \n node _T_1135 = and(_T_1134, d_release_ack_1) \n when _T_1135 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1136 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1137 = bits(_T_1136, 0, 0) \n node _T_1138 = or(_T_1137, same_cycle_resp_1) \n node _T_1139 = asUInt(reset) \n node _T_1140 = eq(_T_1139, UInt<1>(0h0)) \n when _T_1140 : \n node _T_1141 = eq(_T_1138, UInt<1>(0h0)) \n when _T_1141 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1138, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<32>(0h0) \n connect _WIRE_16.bits.address, UInt<32>(0h0) \n connect _WIRE_16.bits.source, UInt<1>(0h0) \n connect _WIRE_16.bits.size, UInt<4>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1142 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_1143 = asUInt(reset) \n node _T_1144 = eq(_T_1143, UInt<1>(0h0)) \n when _T_1144 : \n node _T_1145 = eq(_T_1142, UInt<1>(0h0)) \n when _T_1145 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1142, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_1146 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1147 = asUInt(reset) \n node _T_1148 = eq(_T_1147, UInt<1>(0h0)) \n when _T_1148 : \n node _T_1149 = eq(_T_1146, UInt<1>(0h0)) \n when _T_1149 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1146, UInt<1>(0h1), \"\") : assert_110 \n node _T_1150 = and(io.in.d.valid, d_first_2) \n node _T_1151 = and(_T_1150, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<32>(0h0) \n connect _WIRE_18.bits.address, UInt<32>(0h0) \n connect _WIRE_18.bits.source, UInt<1>(0h0) \n connect _WIRE_18.bits.size, UInt<4>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1152 = and(_T_1151, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<32>(0h0) \n connect _WIRE_20.bits.address, UInt<32>(0h0) \n connect _WIRE_20.bits.source, UInt<1>(0h0) \n connect _WIRE_20.bits.size, UInt<4>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1153 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_1154 = and(_T_1152, _T_1153) \n node _T_1155 = and(_T_1154, d_release_ack_1) \n node _T_1156 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_1157 = and(_T_1155, _T_1156) \n when _T_1157 : \n node _T_1158 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<32>(0h0) \n connect _WIRE_22.bits.address, UInt<32>(0h0) \n connect _WIRE_22.bits.source, UInt<1>(0h0) \n connect _WIRE_22.bits.size, UInt<4>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1159 = or(_T_1158, _WIRE_23.ready) \n node _T_1160 = asUInt(reset) \n node _T_1161 = eq(_T_1160, UInt<1>(0h0)) \n when _T_1161 : \n node _T_1162 = eq(_T_1159, UInt<1>(0h0)) \n when _T_1162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1159, UInt<1>(0h1), \"\") : assert_111 \n node _T_1163 = orr(c_set_wo_ready) \n when _T_1163 : \n node _T_1164 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_1165 = asUInt(reset) \n node _T_1166 = eq(_T_1165, UInt<1>(0h0)) \n when _T_1166 : \n node _T_1167 = eq(_T_1164, UInt<1>(0h0)) \n when _T_1167 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_1164, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_65 \n node _T_1168 = orr(inflight_1) \n node _T_1169 = eq(_T_1168, UInt<1>(0h0)) \n node _T_1170 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_1171 = or(_T_1169, _T_1170) \n node _T_1172 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_1173 = or(_T_1171, _T_1172) \n node _T_1174 = asUInt(reset) \n node _T_1175 = eq(_T_1174, UInt<1>(0h0)) \n when _T_1175 : \n node _T_1176 = eq(_T_1173, UInt<1>(0h0)) \n when _T_1176 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_1173, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<1>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1177 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_1178 = and(io.in.d.ready, io.in.d.valid) \n node _T_1179 = or(_T_1177, _T_1178) \n when _T_1179 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_32(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [9:0] c_first_beats1_decode = 10'h0;\t// @[Edges.scala:220:59]\n wire [9:0] c_first_beats1 = 10'h0;\t// @[Edges.scala:221:14]\n wire [9:0] _c_first_count_T = 10'h0;\t// @[Edges.scala:234:27]\n wire [9:0] c_first_count = 10'h0;\t// @[Edges.scala:234:25]\n wire [9:0] _c_first_counter_T = 10'h0;\t// @[Edges.scala:236:21]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [9:0] c_first_counter1 = 10'h3FF;\t// @[Edges.scala:230:28]\n wire [10:0] _c_first_counter1_T = 11'h7FF;\t// @[Edges.scala:230:28]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_T = 4'h0;\t// @[Monitor.scala:767:79]\n wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_T = 4'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [19:0] _c_sizes_set_T_1 = 20'h0;\t// @[Monitor.scala:768:52]\n wire [18:0] _c_opcodes_set_T_1 = 19'h0;\t// @[Monitor.scala:767:54]\n wire [4:0] _c_sizes_set_interm_T_1 = 5'h1;\t// @[Monitor.scala:766:59]\n wire [4:0] c_sizes_set_interm = 5'h0;\t// @[Monitor.scala:755:40]\n wire [4:0] _c_sizes_set_interm_T = 5'h0;\t// @[Monitor.scala:766:51]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [1:0] _c_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [15:0] c_sizes_set = 16'h0;\t// @[Monitor.scala:741:34]\n wire [7:0] c_opcodes_set = 8'h0;\t// @[Monitor.scala:740:34]\n wire [1:0] c_set = 2'h0;\t// @[Monitor.scala:738:34]\n wire [1:0] c_set_wo_ready = 2'h0;\t// @[Monitor.scala:739:34]\n wire [11:0] _c_first_beats1_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _c_first_beats1_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_sizes_clr_T = 4'h8;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_sizes_clr_T_6 = 4'h8;\t// @[Monitor.scala:791:48]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire _source_ok_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_1 = ~io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1 = _source_ok_T_1;\t// @[Parameters.scala:1138:31]\n wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0];\t// @[OneHot.scala:64:49]\n wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1;\t// @[OneHot.scala:65:{12,27}]\n wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]);\t// @[Misc.scala:206:21]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_1_2 = mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire _source_ok_WIRE_1_0 = _source_ok_T_2;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_3 = ~io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_1 = _source_ok_T_3;\t// @[Parameters.scala:1138:31]\n wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1106 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1106;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1106;\t// @[Decoupled.scala:51:35]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [9:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 10'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 10'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 10'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [9:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1179 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1179;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1179;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1179;\t// @[Decoupled.scala:51:35]\n wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [9:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 10'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 10'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 10'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [9:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [7:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [15:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [9:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 10'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 10'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2];\t// @[package.scala:243:46]\n wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [9:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 10'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 10'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [1:0] a_set;\t// @[Monitor.scala:626:34]\n wire [1:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [7:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [15:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [3:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [3:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [3:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [3:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF};\t// @[Monitor.scala:637:{44,97}]\n wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [7:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :641:65]\n wire [3:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65]\n wire [3:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_2;\t// @[Monitor.scala:641:65, :681:99]\n wire [3:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65, :750:67]\n wire [3:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_2;\t// @[Monitor.scala:641:65, :791:99]\n wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF;\t// @[Monitor.scala:641:{40,91}]\n wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[7:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [4:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [1:0] _GEN_4 = 2'h1 << _GEN_3;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_4;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0;\t// @[OneHot.scala:58:35]\n wire _T_1032 = _T_1106 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1032 ? _a_set_T : 2'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1032 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1032 ? _a_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1032 ? _a_opcodes_set_T_1[7:0] : 8'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :660:77]\n wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :660:{52,77}]\n assign a_sizes_set = _T_1032 ? _a_sizes_set_T_1[15:0] : 16'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [1:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [1:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [7:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [15:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_5;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_5;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1078 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [1:0] _GEN_7 = 2'h1 << _GEN_6;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1078 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0;\t// @[OneHot.scala:58:35]\n wire _T_1047 = _T_1179 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1047 ? _d_clr_T : 2'h0;\t// @[OneHot.scala:58:35]\n wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1047 ? _d_opcodes_clr_T_5[7:0] : 8'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1047 ? _d_sizes_clr_T_5[15:0] : 16'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [1:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [1:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [7:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [15:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2];\t// @[package.scala:243:46]\n wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [9:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 10'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 10'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [7:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF};\t// @[Monitor.scala:749:{44,97}]\n wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF;\t// @[Monitor.scala:750:{42,93}]\n wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[7:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [1:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [1:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [7:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [15:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1150 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1150 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0;\t// @[OneHot.scala:58:35]\n wire _T_1132 = _T_1179 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1132 ? _d_clr_T_1 : 2'h0;\t// @[OneHot.scala:58:35]\n wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1132 ? _d_opcodes_clr_T_11[7:0] : 8'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1132 ? _d_sizes_clr_T_11[15:0] : 16'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :795:113]\n wire [1:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":35467,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_23 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<4>, q : UInt<4>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n node _output_T_2 = asAsyncReset(reset) \n node _output_T_3 = bits(io.d, 1, 1) \n inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 \n connect output_chain_1.clock, clock\n\n connect output_chain_1.reset, _output_T_2\n\n connect output_chain_1.io.d, _output_T_3 \n wire output_1 : UInt<1> \n connect output_1, output_chain_1.io.q \n node _output_T_4 = asAsyncReset(reset) \n node _output_T_5 = bits(io.d, 2, 2) \n inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 \n connect output_chain_2.clock, clock\n\n connect output_chain_2.reset, _output_T_4\n\n connect output_chain_2.io.d, _output_T_5 \n wire output_2 : UInt<1> \n connect output_2, output_chain_2.io.q \n node _output_T_6 = asAsyncReset(reset) \n node _output_T_7 = bits(io.d, 3, 3) \n inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 \n connect output_chain_3.clock, clock\n\n connect output_chain_3.reset, _output_T_6\n\n connect output_chain_3.io.d, _output_T_7 \n wire output_3 : UInt<1> \n connect output_3, output_chain_3.io.q \n node io_q_lo = cat(output_1, output_0) \n node io_q_hi = cat(output_3, output_2) \n node _io_q_T = cat(io_q_hi, io_q_lo) \n connect io.q, _io_q_T"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w4_d3_i0_23(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input [3:0] io_d,\t// @[ShiftReg.scala:36:14]\n output [3:0] io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire [3:0] io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_2 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_4 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_6 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire [3:0] _io_q_T;\t// @[SynchronizerReg.scala:90:14]\n wire [3:0] io_q_0;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T_1 = io_d_0[0];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire _output_T_3 = io_d_0[1];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_1;\t// @[ShiftReg.scala:48:24]\n wire _output_T_5 = io_d_0[2];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_2;\t// @[ShiftReg.scala:48:24]\n wire _output_T_7 = io_d_0[3];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_3;\t// @[ShiftReg.scala:48:24]\n wire [1:0] io_q_lo = {output_1, output_0};\t// @[SynchronizerReg.scala:90:14]\n wire [1:0] io_q_hi = {output_3, output_2};\t// @[SynchronizerReg.scala:90:14]\n assign _io_q_T = {io_q_hi, io_q_lo};\t// @[SynchronizerReg.scala:90:14]\n assign io_q_0 = _io_q_T;\t// @[SynchronizerReg.scala:80:7, :90:14]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 output_chain_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_2),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_3),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_1)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 output_chain_2 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_4),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_5),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_2)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 output_chain_3 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_6),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_7),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_3)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35468,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 4) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 3, 0) \n node _T_4 = shr(io.in.a.bits.source, 4) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<4>(0h9)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_1 \n node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_20 : \n node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_23 = and(_T_21, _T_22) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) \n node _T_24 = shr(io.in.a.bits.source, 4) \n node _T_25 = eq(_T_24, UInt<1>(0h0)) \n node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_27 = and(_T_25, _T_26) \n node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = and(_T_23, _T_29) \n node _T_31 = or(UInt<1>(0h0), _T_30) \n node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_34 = cvt(_T_33) \n node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) \n node _T_36 = asSInt(_T_35) \n node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) \n node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_39 = cvt(_T_38) \n node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000))) \n node _T_41 = asSInt(_T_40) \n node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) \n node _T_43 = or(_T_37, _T_42) \n node _T_44 = and(_T_32, _T_43) \n node _T_45 = or(UInt<1>(0h0), _T_44) \n node _T_46 = and(_T_31, _T_45) \n node _T_47 = asUInt(reset) \n node _T_48 = eq(_T_47, UInt<1>(0h0)) \n when _T_48 : \n node _T_49 = eq(_T_46, UInt<1>(0h0)) \n when _T_49 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_46, UInt<1>(0h1), \"\") : assert_2 \n node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_52 = and(_T_50, _T_51) \n node _T_53 = or(UInt<1>(0h0), _T_52) \n node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_55 = cvt(_T_54) \n node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000))) \n node _T_57 = asSInt(_T_56) \n node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) \n node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_60 = cvt(_T_59) \n node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000))) \n node _T_62 = asSInt(_T_61) \n node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) \n node _T_64 = or(_T_58, _T_63) \n node _T_65 = and(_T_53, _T_64) \n node _T_66 = or(UInt<1>(0h0), _T_65) \n node _T_67 = and(UInt<1>(0h0), _T_66) \n node _T_68 = asUInt(reset) \n node _T_69 = eq(_T_68, UInt<1>(0h0)) \n when _T_69 : \n node _T_70 = eq(_T_67, UInt<1>(0h0)) \n when _T_70 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_67, UInt<1>(0h1), \"\") : assert_3 \n node _T_71 = asUInt(reset) \n node _T_72 = eq(_T_71, UInt<1>(0h0)) \n when _T_72 : \n node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_73 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_5 \n node _T_78 = asUInt(reset) \n node _T_79 = eq(_T_78, UInt<1>(0h0)) \n when _T_79 : \n node _T_80 = eq(is_aligned, UInt<1>(0h0)) \n when _T_80 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_82 = asUInt(reset) \n node _T_83 = eq(_T_82, UInt<1>(0h0)) \n when _T_83 : \n node _T_84 = eq(_T_81, UInt<1>(0h0)) \n when _T_84 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_81, UInt<1>(0h1), \"\") : assert_7 \n node _T_85 = not(io.in.a.bits.mask) \n node _T_86 = eq(_T_85, UInt<1>(0h0)) \n node _T_87 = asUInt(reset) \n node _T_88 = eq(_T_87, UInt<1>(0h0)) \n when _T_88 : \n node _T_89 = eq(_T_86, UInt<1>(0h0)) \n when _T_89 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_86, UInt<1>(0h1), \"\") : assert_8 \n node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_91 = asUInt(reset) \n node _T_92 = eq(_T_91, UInt<1>(0h0)) \n when _T_92 : \n node _T_93 = eq(_T_90, UInt<1>(0h0)) \n when _T_93 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_90, UInt<1>(0h1), \"\") : assert_9 \n node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_94 : \n node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_97 = and(_T_95, _T_96) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) \n node _T_98 = shr(io.in.a.bits.source, 4) \n node _T_99 = eq(_T_98, UInt<1>(0h0)) \n node _T_100 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_101 = and(_T_99, _T_100) \n node _T_102 = leq(uncommonBits_2, UInt<4>(0h9)) \n node _T_103 = and(_T_101, _T_102) \n node _T_104 = and(_T_97, _T_103) \n node _T_105 = or(UInt<1>(0h0), _T_104) \n node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_108 = cvt(_T_107) \n node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000))) \n node _T_110 = asSInt(_T_109) \n node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) \n node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_113 = cvt(_T_112) \n node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000))) \n node _T_115 = asSInt(_T_114) \n node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) \n node _T_117 = or(_T_111, _T_116) \n node _T_118 = and(_T_106, _T_117) \n node _T_119 = or(UInt<1>(0h0), _T_118) \n node _T_120 = and(_T_105, _T_119) \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_T_120, UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_120, UInt<1>(0h1), \"\") : assert_10 \n node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_126 = and(_T_124, _T_125) \n node _T_127 = or(UInt<1>(0h0), _T_126) \n node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_129 = cvt(_T_128) \n node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000))) \n node _T_131 = asSInt(_T_130) \n node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0))) \n node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_134 = cvt(_T_133) \n node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000))) \n node _T_136 = asSInt(_T_135) \n node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0))) \n node _T_138 = or(_T_132, _T_137) \n node _T_139 = and(_T_127, _T_138) \n node _T_140 = or(UInt<1>(0h0), _T_139) \n node _T_141 = and(UInt<1>(0h0), _T_140) \n node _T_142 = asUInt(reset) \n node _T_143 = eq(_T_142, UInt<1>(0h0)) \n when _T_143 : \n node _T_144 = eq(_T_141, UInt<1>(0h0)) \n when _T_144 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_141, UInt<1>(0h1), \"\") : assert_11 \n node _T_145 = asUInt(reset) \n node _T_146 = eq(_T_145, UInt<1>(0h0)) \n when _T_146 : \n node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_147 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_149 = asUInt(reset) \n node _T_150 = eq(_T_149, UInt<1>(0h0)) \n when _T_150 : \n node _T_151 = eq(_T_148, UInt<1>(0h0)) \n when _T_151 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_148, UInt<1>(0h1), \"\") : assert_13 \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(is_aligned, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_156 = asUInt(reset) \n node _T_157 = eq(_T_156, UInt<1>(0h0)) \n when _T_157 : \n node _T_158 = eq(_T_155, UInt<1>(0h0)) \n when _T_158 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_155, UInt<1>(0h1), \"\") : assert_15 \n node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_16 \n node _T_163 = not(io.in.a.bits.mask) \n node _T_164 = eq(_T_163, UInt<1>(0h0)) \n node _T_165 = asUInt(reset) \n node _T_166 = eq(_T_165, UInt<1>(0h0)) \n when _T_166 : \n node _T_167 = eq(_T_164, UInt<1>(0h0)) \n when _T_167 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_164, UInt<1>(0h1), \"\") : assert_17 \n node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_169 = asUInt(reset) \n node _T_170 = eq(_T_169, UInt<1>(0h0)) \n when _T_170 : \n node _T_171 = eq(_T_168, UInt<1>(0h0)) \n when _T_171 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_168, UInt<1>(0h1), \"\") : assert_18 \n node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_172 : \n node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_175 = and(_T_173, _T_174) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) \n node _T_176 = shr(io.in.a.bits.source, 4) \n node _T_177 = eq(_T_176, UInt<1>(0h0)) \n node _T_178 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_179 = and(_T_177, _T_178) \n node _T_180 = leq(uncommonBits_3, UInt<4>(0h9)) \n node _T_181 = and(_T_179, _T_180) \n node _T_182 = and(_T_175, _T_181) \n node _T_183 = or(UInt<1>(0h0), _T_182) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_19 \n node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_189 = and(_T_187, _T_188) \n node _T_190 = or(UInt<1>(0h0), _T_189) \n node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_192 = cvt(_T_191) \n node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000))) \n node _T_194 = asSInt(_T_193) \n node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) \n node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_197 = cvt(_T_196) \n node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000))) \n node _T_199 = asSInt(_T_198) \n node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) \n node _T_201 = or(_T_195, _T_200) \n node _T_202 = and(_T_190, _T_201) \n node _T_203 = or(UInt<1>(0h0), _T_202) \n node _T_204 = asUInt(reset) \n node _T_205 = eq(_T_204, UInt<1>(0h0)) \n when _T_205 : \n node _T_206 = eq(_T_203, UInt<1>(0h0)) \n when _T_206 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_203, UInt<1>(0h1), \"\") : assert_20 \n node _T_207 = asUInt(reset) \n node _T_208 = eq(_T_207, UInt<1>(0h0)) \n when _T_208 : \n node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_209 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_210 = asUInt(reset) \n node _T_211 = eq(_T_210, UInt<1>(0h0)) \n when _T_211 : \n node _T_212 = eq(is_aligned, UInt<1>(0h0)) \n when _T_212 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_214 = asUInt(reset) \n node _T_215 = eq(_T_214, UInt<1>(0h0)) \n when _T_215 : \n node _T_216 = eq(_T_213, UInt<1>(0h0)) \n when _T_216 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_213, UInt<1>(0h1), \"\") : assert_23 \n node _T_217 = eq(io.in.a.bits.mask, mask) \n node _T_218 = asUInt(reset) \n node _T_219 = eq(_T_218, UInt<1>(0h0)) \n when _T_219 : \n node _T_220 = eq(_T_217, UInt<1>(0h0)) \n when _T_220 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_217, UInt<1>(0h1), \"\") : assert_24 \n node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_T_221, UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_221, UInt<1>(0h1), \"\") : assert_25 \n node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_225 : \n node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_228 = and(_T_226, _T_227) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) \n node _T_229 = shr(io.in.a.bits.source, 4) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n node _T_231 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_232 = and(_T_230, _T_231) \n node _T_233 = leq(uncommonBits_4, UInt<4>(0h9)) \n node _T_234 = and(_T_232, _T_233) \n node _T_235 = and(_T_228, _T_234) \n node _T_236 = or(UInt<1>(0h0), _T_235) \n node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_239 = and(_T_237, _T_238) \n node _T_240 = or(UInt<1>(0h0), _T_239) \n node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_242 = cvt(_T_241) \n node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) \n node _T_244 = asSInt(_T_243) \n node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) \n node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_247 = cvt(_T_246) \n node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) \n node _T_249 = asSInt(_T_248) \n node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) \n node _T_251 = or(_T_245, _T_250) \n node _T_252 = and(_T_240, _T_251) \n node _T_253 = or(UInt<1>(0h0), _T_252) \n node _T_254 = and(_T_236, _T_253) \n node _T_255 = asUInt(reset) \n node _T_256 = eq(_T_255, UInt<1>(0h0)) \n when _T_256 : \n node _T_257 = eq(_T_254, UInt<1>(0h0)) \n when _T_257 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_254, UInt<1>(0h1), \"\") : assert_26 \n node _T_258 = asUInt(reset) \n node _T_259 = eq(_T_258, UInt<1>(0h0)) \n when _T_259 : \n node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_260 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_261 = asUInt(reset) \n node _T_262 = eq(_T_261, UInt<1>(0h0)) \n when _T_262 : \n node _T_263 = eq(is_aligned, UInt<1>(0h0)) \n when _T_263 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_265 = asUInt(reset) \n node _T_266 = eq(_T_265, UInt<1>(0h0)) \n when _T_266 : \n node _T_267 = eq(_T_264, UInt<1>(0h0)) \n when _T_267 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_264, UInt<1>(0h1), \"\") : assert_29 \n node _T_268 = eq(io.in.a.bits.mask, mask) \n node _T_269 = asUInt(reset) \n node _T_270 = eq(_T_269, UInt<1>(0h0)) \n when _T_270 : \n node _T_271 = eq(_T_268, UInt<1>(0h0)) \n when _T_271 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_268, UInt<1>(0h1), \"\") : assert_30 \n node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_272 : \n node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_275 = and(_T_273, _T_274) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) \n node _T_276 = shr(io.in.a.bits.source, 4) \n node _T_277 = eq(_T_276, UInt<1>(0h0)) \n node _T_278 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_279 = and(_T_277, _T_278) \n node _T_280 = leq(uncommonBits_5, UInt<4>(0h9)) \n node _T_281 = and(_T_279, _T_280) \n node _T_282 = and(_T_275, _T_281) \n node _T_283 = or(UInt<1>(0h0), _T_282) \n node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_286 = and(_T_284, _T_285) \n node _T_287 = or(UInt<1>(0h0), _T_286) \n node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_289 = cvt(_T_288) \n node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000))) \n node _T_291 = asSInt(_T_290) \n node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) \n node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_294 = cvt(_T_293) \n node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000))) \n node _T_296 = asSInt(_T_295) \n node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) \n node _T_298 = or(_T_292, _T_297) \n node _T_299 = and(_T_287, _T_298) \n node _T_300 = or(UInt<1>(0h0), _T_299) \n node _T_301 = and(_T_283, _T_300) \n node _T_302 = asUInt(reset) \n node _T_303 = eq(_T_302, UInt<1>(0h0)) \n when _T_303 : \n node _T_304 = eq(_T_301, UInt<1>(0h0)) \n when _T_304 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_301, UInt<1>(0h1), \"\") : assert_31 \n node _T_305 = asUInt(reset) \n node _T_306 = eq(_T_305, UInt<1>(0h0)) \n when _T_306 : \n node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_307 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_308 = asUInt(reset) \n node _T_309 = eq(_T_308, UInt<1>(0h0)) \n when _T_309 : \n node _T_310 = eq(is_aligned, UInt<1>(0h0)) \n when _T_310 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_312 = asUInt(reset) \n node _T_313 = eq(_T_312, UInt<1>(0h0)) \n when _T_313 : \n node _T_314 = eq(_T_311, UInt<1>(0h0)) \n when _T_314 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_311, UInt<1>(0h1), \"\") : assert_34 \n node _T_315 = not(mask) \n node _T_316 = and(io.in.a.bits.mask, _T_315) \n node _T_317 = eq(_T_316, UInt<1>(0h0)) \n node _T_318 = asUInt(reset) \n node _T_319 = eq(_T_318, UInt<1>(0h0)) \n when _T_319 : \n node _T_320 = eq(_T_317, UInt<1>(0h0)) \n when _T_320 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_317, UInt<1>(0h1), \"\") : assert_35 \n node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_321 : \n node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_324 = and(_T_322, _T_323) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) \n node _T_325 = shr(io.in.a.bits.source, 4) \n node _T_326 = eq(_T_325, UInt<1>(0h0)) \n node _T_327 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_328 = and(_T_326, _T_327) \n node _T_329 = leq(uncommonBits_6, UInt<4>(0h9)) \n node _T_330 = and(_T_328, _T_329) \n node _T_331 = and(_T_324, _T_330) \n node _T_332 = or(UInt<1>(0h0), _T_331) \n node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_335 = cvt(_T_334) \n node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000))) \n node _T_337 = asSInt(_T_336) \n node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) \n node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_340 = cvt(_T_339) \n node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000))) \n node _T_342 = asSInt(_T_341) \n node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) \n node _T_344 = or(_T_338, _T_343) \n node _T_345 = and(_T_333, _T_344) \n node _T_346 = or(UInt<1>(0h0), _T_345) \n node _T_347 = and(_T_332, _T_346) \n node _T_348 = asUInt(reset) \n node _T_349 = eq(_T_348, UInt<1>(0h0)) \n when _T_349 : \n node _T_350 = eq(_T_347, UInt<1>(0h0)) \n when _T_350 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_347, UInt<1>(0h1), \"\") : assert_36 \n node _T_351 = asUInt(reset) \n node _T_352 = eq(_T_351, UInt<1>(0h0)) \n when _T_352 : \n node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_353 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_354 = asUInt(reset) \n node _T_355 = eq(_T_354, UInt<1>(0h0)) \n when _T_355 : \n node _T_356 = eq(is_aligned, UInt<1>(0h0)) \n when _T_356 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_358 = asUInt(reset) \n node _T_359 = eq(_T_358, UInt<1>(0h0)) \n when _T_359 : \n node _T_360 = eq(_T_357, UInt<1>(0h0)) \n when _T_360 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_357, UInt<1>(0h1), \"\") : assert_39 \n node _T_361 = eq(io.in.a.bits.mask, mask) \n node _T_362 = asUInt(reset) \n node _T_363 = eq(_T_362, UInt<1>(0h0)) \n when _T_363 : \n node _T_364 = eq(_T_361, UInt<1>(0h0)) \n when _T_364 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_361, UInt<1>(0h1), \"\") : assert_40 \n node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_365 : \n node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_368 = and(_T_366, _T_367) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) \n node _T_369 = shr(io.in.a.bits.source, 4) \n node _T_370 = eq(_T_369, UInt<1>(0h0)) \n node _T_371 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_372 = and(_T_370, _T_371) \n node _T_373 = leq(uncommonBits_7, UInt<4>(0h9)) \n node _T_374 = and(_T_372, _T_373) \n node _T_375 = and(_T_368, _T_374) \n node _T_376 = or(UInt<1>(0h0), _T_375) \n node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_379 = cvt(_T_378) \n node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000))) \n node _T_381 = asSInt(_T_380) \n node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) \n node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_384 = cvt(_T_383) \n node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000))) \n node _T_386 = asSInt(_T_385) \n node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0))) \n node _T_388 = or(_T_382, _T_387) \n node _T_389 = and(_T_377, _T_388) \n node _T_390 = or(UInt<1>(0h0), _T_389) \n node _T_391 = and(_T_376, _T_390) \n node _T_392 = asUInt(reset) \n node _T_393 = eq(_T_392, UInt<1>(0h0)) \n when _T_393 : \n node _T_394 = eq(_T_391, UInt<1>(0h0)) \n when _T_394 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_391, UInt<1>(0h1), \"\") : assert_41 \n node _T_395 = asUInt(reset) \n node _T_396 = eq(_T_395, UInt<1>(0h0)) \n when _T_396 : \n node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_397 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(is_aligned, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_402 = asUInt(reset) \n node _T_403 = eq(_T_402, UInt<1>(0h0)) \n when _T_403 : \n node _T_404 = eq(_T_401, UInt<1>(0h0)) \n when _T_404 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_401, UInt<1>(0h1), \"\") : assert_44 \n node _T_405 = eq(io.in.a.bits.mask, mask) \n node _T_406 = asUInt(reset) \n node _T_407 = eq(_T_406, UInt<1>(0h0)) \n when _T_407 : \n node _T_408 = eq(_T_405, UInt<1>(0h0)) \n when _T_408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_405, UInt<1>(0h1), \"\") : assert_45 \n node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_409 : \n node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_412 = and(_T_410, _T_411) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) \n node _T_413 = shr(io.in.a.bits.source, 4) \n node _T_414 = eq(_T_413, UInt<1>(0h0)) \n node _T_415 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_416 = and(_T_414, _T_415) \n node _T_417 = leq(uncommonBits_8, UInt<4>(0h9)) \n node _T_418 = and(_T_416, _T_417) \n node _T_419 = and(_T_412, _T_418) \n node _T_420 = or(UInt<1>(0h0), _T_419) \n node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_423 = cvt(_T_422) \n node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000))) \n node _T_425 = asSInt(_T_424) \n node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0))) \n node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_428 = cvt(_T_427) \n node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000))) \n node _T_430 = asSInt(_T_429) \n node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) \n node _T_432 = or(_T_426, _T_431) \n node _T_433 = and(_T_421, _T_432) \n node _T_434 = or(UInt<1>(0h0), _T_433) \n node _T_435 = and(_T_420, _T_434) \n node _T_436 = asUInt(reset) \n node _T_437 = eq(_T_436, UInt<1>(0h0)) \n when _T_437 : \n node _T_438 = eq(_T_435, UInt<1>(0h0)) \n when _T_438 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_435, UInt<1>(0h1), \"\") : assert_46 \n node _T_439 = asUInt(reset) \n node _T_440 = eq(_T_439, UInt<1>(0h0)) \n when _T_440 : \n node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_441 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_442 = asUInt(reset) \n node _T_443 = eq(_T_442, UInt<1>(0h0)) \n when _T_443 : \n node _T_444 = eq(is_aligned, UInt<1>(0h0)) \n when _T_444 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_446 = asUInt(reset) \n node _T_447 = eq(_T_446, UInt<1>(0h0)) \n when _T_447 : \n node _T_448 = eq(_T_445, UInt<1>(0h0)) \n when _T_448 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_445, UInt<1>(0h1), \"\") : assert_49 \n node _T_449 = eq(io.in.a.bits.mask, mask) \n node _T_450 = asUInt(reset) \n node _T_451 = eq(_T_450, UInt<1>(0h0)) \n when _T_451 : \n node _T_452 = eq(_T_449, UInt<1>(0h0)) \n when _T_452 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_449, UInt<1>(0h1), \"\") : assert_50 \n node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_454 = asUInt(reset) \n node _T_455 = eq(_T_454, UInt<1>(0h0)) \n when _T_455 : \n node _T_456 = eq(_T_453, UInt<1>(0h0)) \n when _T_456 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_453, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_458 = asUInt(reset) \n node _T_459 = eq(_T_458, UInt<1>(0h0)) \n when _T_459 : \n node _T_460 = eq(_T_457, UInt<1>(0h0)) \n when _T_460 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_457, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) \n node _source_ok_T_6 = shr(io.in.d.bits.source, 4) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_11 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_461 : \n node _T_462 = asUInt(reset) \n node _T_463 = eq(_T_462, UInt<1>(0h0)) \n when _T_463 : \n node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_464 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_466 = asUInt(reset) \n node _T_467 = eq(_T_466, UInt<1>(0h0)) \n when _T_467 : \n node _T_468 = eq(_T_465, UInt<1>(0h0)) \n when _T_468 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_465, UInt<1>(0h1), \"\") : assert_54 \n node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_470 = asUInt(reset) \n node _T_471 = eq(_T_470, UInt<1>(0h0)) \n when _T_471 : \n node _T_472 = eq(_T_469, UInt<1>(0h0)) \n when _T_472 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_469, UInt<1>(0h1), \"\") : assert_55 \n node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_474 = asUInt(reset) \n node _T_475 = eq(_T_474, UInt<1>(0h0)) \n when _T_475 : \n node _T_476 = eq(_T_473, UInt<1>(0h0)) \n when _T_476 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_473, UInt<1>(0h1), \"\") : assert_56 \n node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_478 = asUInt(reset) \n node _T_479 = eq(_T_478, UInt<1>(0h0)) \n when _T_479 : \n node _T_480 = eq(_T_477, UInt<1>(0h0)) \n when _T_480 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_477, UInt<1>(0h1), \"\") : assert_57 \n node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_481 : \n node _T_482 = asUInt(reset) \n node _T_483 = eq(_T_482, UInt<1>(0h0)) \n when _T_483 : \n node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_484 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_485 = asUInt(reset) \n node _T_486 = eq(_T_485, UInt<1>(0h0)) \n when _T_486 : \n node _T_487 = eq(sink_ok, UInt<1>(0h0)) \n when _T_487 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_489 = asUInt(reset) \n node _T_490 = eq(_T_489, UInt<1>(0h0)) \n when _T_490 : \n node _T_491 = eq(_T_488, UInt<1>(0h0)) \n when _T_491 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_488, UInt<1>(0h1), \"\") : assert_60 \n node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_493 = asUInt(reset) \n node _T_494 = eq(_T_493, UInt<1>(0h0)) \n when _T_494 : \n node _T_495 = eq(_T_492, UInt<1>(0h0)) \n when _T_495 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_492, UInt<1>(0h1), \"\") : assert_61 \n node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_497 = asUInt(reset) \n node _T_498 = eq(_T_497, UInt<1>(0h0)) \n when _T_498 : \n node _T_499 = eq(_T_496, UInt<1>(0h0)) \n when _T_499 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_496, UInt<1>(0h1), \"\") : assert_62 \n node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_501 = asUInt(reset) \n node _T_502 = eq(_T_501, UInt<1>(0h0)) \n when _T_502 : \n node _T_503 = eq(_T_500, UInt<1>(0h0)) \n when _T_503 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_500, UInt<1>(0h1), \"\") : assert_63 \n node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_505 = or(UInt<1>(0h1), _T_504) \n node _T_506 = asUInt(reset) \n node _T_507 = eq(_T_506, UInt<1>(0h0)) \n when _T_507 : \n node _T_508 = eq(_T_505, UInt<1>(0h0)) \n when _T_508 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_505, UInt<1>(0h1), \"\") : assert_64 \n node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_509 : \n node _T_510 = asUInt(reset) \n node _T_511 = eq(_T_510, UInt<1>(0h0)) \n when _T_511 : \n node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_513 = asUInt(reset) \n node _T_514 = eq(_T_513, UInt<1>(0h0)) \n when _T_514 : \n node _T_515 = eq(sink_ok, UInt<1>(0h0)) \n when _T_515 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_517 = asUInt(reset) \n node _T_518 = eq(_T_517, UInt<1>(0h0)) \n when _T_518 : \n node _T_519 = eq(_T_516, UInt<1>(0h0)) \n when _T_519 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_516, UInt<1>(0h1), \"\") : assert_67 \n node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_521 = asUInt(reset) \n node _T_522 = eq(_T_521, UInt<1>(0h0)) \n when _T_522 : \n node _T_523 = eq(_T_520, UInt<1>(0h0)) \n when _T_523 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_520, UInt<1>(0h1), \"\") : assert_68 \n node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_525 = asUInt(reset) \n node _T_526 = eq(_T_525, UInt<1>(0h0)) \n when _T_526 : \n node _T_527 = eq(_T_524, UInt<1>(0h0)) \n when _T_527 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_524, UInt<1>(0h1), \"\") : assert_69 \n node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_529 = or(_T_528, io.in.d.bits.corrupt) \n node _T_530 = asUInt(reset) \n node _T_531 = eq(_T_530, UInt<1>(0h0)) \n when _T_531 : \n node _T_532 = eq(_T_529, UInt<1>(0h0)) \n when _T_532 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_529, UInt<1>(0h1), \"\") : assert_70 \n node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_534 = or(UInt<1>(0h1), _T_533) \n node _T_535 = asUInt(reset) \n node _T_536 = eq(_T_535, UInt<1>(0h0)) \n when _T_536 : \n node _T_537 = eq(_T_534, UInt<1>(0h0)) \n when _T_537 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_534, UInt<1>(0h1), \"\") : assert_71 \n node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_538 : \n node _T_539 = asUInt(reset) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n when _T_540 : \n node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_541 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_543 = asUInt(reset) \n node _T_544 = eq(_T_543, UInt<1>(0h0)) \n when _T_544 : \n node _T_545 = eq(_T_542, UInt<1>(0h0)) \n when _T_545 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_542, UInt<1>(0h1), \"\") : assert_73 \n node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_547 = asUInt(reset) \n node _T_548 = eq(_T_547, UInt<1>(0h0)) \n when _T_548 : \n node _T_549 = eq(_T_546, UInt<1>(0h0)) \n when _T_549 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_546, UInt<1>(0h1), \"\") : assert_74 \n node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_551 = or(UInt<1>(0h1), _T_550) \n node _T_552 = asUInt(reset) \n node _T_553 = eq(_T_552, UInt<1>(0h0)) \n when _T_553 : \n node _T_554 = eq(_T_551, UInt<1>(0h0)) \n when _T_554 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_551, UInt<1>(0h1), \"\") : assert_75 \n node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_555 : \n node _T_556 = asUInt(reset) \n node _T_557 = eq(_T_556, UInt<1>(0h0)) \n when _T_557 : \n node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_558 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_560 = asUInt(reset) \n node _T_561 = eq(_T_560, UInt<1>(0h0)) \n when _T_561 : \n node _T_562 = eq(_T_559, UInt<1>(0h0)) \n when _T_562 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_559, UInt<1>(0h1), \"\") : assert_77 \n node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_564 = or(_T_563, io.in.d.bits.corrupt) \n node _T_565 = asUInt(reset) \n node _T_566 = eq(_T_565, UInt<1>(0h0)) \n when _T_566 : \n node _T_567 = eq(_T_564, UInt<1>(0h0)) \n when _T_567 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_564, UInt<1>(0h1), \"\") : assert_78 \n node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_569 = or(UInt<1>(0h1), _T_568) \n node _T_570 = asUInt(reset) \n node _T_571 = eq(_T_570, UInt<1>(0h0)) \n when _T_571 : \n node _T_572 = eq(_T_569, UInt<1>(0h0)) \n when _T_572 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_569, UInt<1>(0h1), \"\") : assert_79 \n node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_573 : \n node _T_574 = asUInt(reset) \n node _T_575 = eq(_T_574, UInt<1>(0h0)) \n when _T_575 : \n node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_576 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_578 = asUInt(reset) \n node _T_579 = eq(_T_578, UInt<1>(0h0)) \n when _T_579 : \n node _T_580 = eq(_T_577, UInt<1>(0h0)) \n when _T_580 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_577, UInt<1>(0h1), \"\") : assert_81 \n node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_582 = asUInt(reset) \n node _T_583 = eq(_T_582, UInt<1>(0h0)) \n when _T_583 : \n node _T_584 = eq(_T_581, UInt<1>(0h0)) \n when _T_584 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_581, UInt<1>(0h1), \"\") : assert_82 \n node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_586 = or(UInt<1>(0h1), _T_585) \n node _T_587 = asUInt(reset) \n node _T_588 = eq(_T_587, UInt<1>(0h0)) \n when _T_588 : \n node _T_589 = eq(_T_586, UInt<1>(0h0)) \n when _T_589 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_586, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<4>(0h0) \n connect _WIRE.bits.size, UInt<3>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_591 = asUInt(reset) \n node _T_592 = eq(_T_591, UInt<1>(0h0)) \n when _T_592 : \n node _T_593 = eq(_T_590, UInt<1>(0h0)) \n when _T_593 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_590, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<4>(0h0) \n connect _WIRE_2.bits.size, UInt<3>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_595 = asUInt(reset) \n node _T_596 = eq(_T_595, UInt<1>(0h0)) \n when _T_596 : \n node _T_597 = eq(_T_594, UInt<1>(0h0)) \n when _T_597 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_594, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_599 = asUInt(reset) \n node _T_600 = eq(_T_599, UInt<1>(0h0)) \n when _T_600 : \n node _T_601 = eq(_T_598, UInt<1>(0h0)) \n when _T_601 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_598, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_602 = eq(a_first, UInt<1>(0h0)) \n node _T_603 = and(io.in.a.valid, _T_602) \n when _T_603 : \n node _T_604 = eq(io.in.a.bits.opcode, opcode) \n node _T_605 = asUInt(reset) \n node _T_606 = eq(_T_605, UInt<1>(0h0)) \n when _T_606 : \n node _T_607 = eq(_T_604, UInt<1>(0h0)) \n when _T_607 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_604, UInt<1>(0h1), \"\") : assert_87 \n node _T_608 = eq(io.in.a.bits.param, param) \n node _T_609 = asUInt(reset) \n node _T_610 = eq(_T_609, UInt<1>(0h0)) \n when _T_610 : \n node _T_611 = eq(_T_608, UInt<1>(0h0)) \n when _T_611 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_608, UInt<1>(0h1), \"\") : assert_88 \n node _T_612 = eq(io.in.a.bits.size, size) \n node _T_613 = asUInt(reset) \n node _T_614 = eq(_T_613, UInt<1>(0h0)) \n when _T_614 : \n node _T_615 = eq(_T_612, UInt<1>(0h0)) \n when _T_615 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_612, UInt<1>(0h1), \"\") : assert_89 \n node _T_616 = eq(io.in.a.bits.source, source) \n node _T_617 = asUInt(reset) \n node _T_618 = eq(_T_617, UInt<1>(0h0)) \n when _T_618 : \n node _T_619 = eq(_T_616, UInt<1>(0h0)) \n when _T_619 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_616, UInt<1>(0h1), \"\") : assert_90 \n node _T_620 = eq(io.in.a.bits.address, address) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_91 \n node _T_624 = and(io.in.a.ready, io.in.a.valid) \n node _T_625 = and(_T_624, a_first) \n when _T_625 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_626 = eq(d_first, UInt<1>(0h0)) \n node _T_627 = and(io.in.d.valid, _T_626) \n when _T_627 : \n node _T_628 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_629 = asUInt(reset) \n node _T_630 = eq(_T_629, UInt<1>(0h0)) \n when _T_630 : \n node _T_631 = eq(_T_628, UInt<1>(0h0)) \n when _T_631 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_628, UInt<1>(0h1), \"\") : assert_92 \n node _T_632 = eq(io.in.d.bits.param, param_1) \n node _T_633 = asUInt(reset) \n node _T_634 = eq(_T_633, UInt<1>(0h0)) \n when _T_634 : \n node _T_635 = eq(_T_632, UInt<1>(0h0)) \n when _T_635 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_632, UInt<1>(0h1), \"\") : assert_93 \n node _T_636 = eq(io.in.d.bits.size, size_1) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_94 \n node _T_640 = eq(io.in.d.bits.source, source_1) \n node _T_641 = asUInt(reset) \n node _T_642 = eq(_T_641, UInt<1>(0h0)) \n when _T_642 : \n node _T_643 = eq(_T_640, UInt<1>(0h0)) \n when _T_643 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_640, UInt<1>(0h1), \"\") : assert_95 \n node _T_644 = eq(io.in.d.bits.sink, sink) \n node _T_645 = asUInt(reset) \n node _T_646 = eq(_T_645, UInt<1>(0h0)) \n when _T_646 : \n node _T_647 = eq(_T_644, UInt<1>(0h0)) \n when _T_647 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_644, UInt<1>(0h1), \"\") : assert_96 \n node _T_648 = eq(io.in.d.bits.denied, denied) \n node _T_649 = asUInt(reset) \n node _T_650 = eq(_T_649, UInt<1>(0h0)) \n when _T_650 : \n node _T_651 = eq(_T_648, UInt<1>(0h0)) \n when _T_651 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_648, UInt<1>(0h1), \"\") : assert_97 \n node _T_652 = and(io.in.d.ready, io.in.d.valid) \n node _T_653 = and(_T_652, d_first) \n when _T_653 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) \n regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) \n regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<10> \n connect a_set, UInt<10>(0h0) \n wire a_set_wo_ready : UInt<10> \n connect a_set_wo_ready, UInt<10>(0h0) \n wire a_opcodes_set : UInt<40> \n connect a_opcodes_set, UInt<40>(0h0) \n wire a_sizes_set : UInt<40> \n connect a_sizes_set, UInt<40>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<4> \n connect a_sizes_set_interm, UInt<4>(0h0) \n node _T_654 = and(io.in.a.valid, a_first_1) \n node _T_655 = and(_T_654, UInt<1>(0h1)) \n when _T_655 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_656 = and(io.in.a.ready, io.in.a.valid) \n node _T_657 = and(_T_656, a_first_1) \n node _T_658 = and(_T_657, UInt<1>(0h1)) \n when _T_658 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_659 = dshr(inflight, io.in.a.bits.source) \n node _T_660 = bits(_T_659, 0, 0) \n node _T_661 = eq(_T_660, UInt<1>(0h0)) \n node _T_662 = asUInt(reset) \n node _T_663 = eq(_T_662, UInt<1>(0h0)) \n when _T_663 : \n node _T_664 = eq(_T_661, UInt<1>(0h0)) \n when _T_664 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_661, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<10> \n connect d_clr, UInt<10>(0h0) \n wire d_clr_wo_ready : UInt<10> \n connect d_clr_wo_ready, UInt<10>(0h0) \n wire d_opcodes_clr : UInt<40> \n connect d_opcodes_clr, UInt<40>(0h0) \n wire d_sizes_clr : UInt<40> \n connect d_sizes_clr, UInt<40>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_665 = and(io.in.d.valid, d_first_1) \n node _T_666 = and(_T_665, UInt<1>(0h1)) \n node _T_667 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_668 = and(_T_666, _T_667) \n when _T_668 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_669 = and(io.in.d.ready, io.in.d.valid) \n node _T_670 = and(_T_669, d_first_1) \n node _T_671 = and(_T_670, UInt<1>(0h1)) \n node _T_672 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_673 = and(_T_671, _T_672) \n when _T_673 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_674 = and(io.in.d.valid, d_first_1) \n node _T_675 = and(_T_674, UInt<1>(0h1)) \n node _T_676 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_677 = and(_T_675, _T_676) \n when _T_677 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_678 = dshr(inflight, io.in.d.bits.source) \n node _T_679 = bits(_T_678, 0, 0) \n node _T_680 = or(_T_679, same_cycle_resp) \n node _T_681 = asUInt(reset) \n node _T_682 = eq(_T_681, UInt<1>(0h0)) \n when _T_682 : \n node _T_683 = eq(_T_680, UInt<1>(0h0)) \n when _T_683 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_680, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_686 = or(_T_684, _T_685) \n node _T_687 = asUInt(reset) \n node _T_688 = eq(_T_687, UInt<1>(0h0)) \n when _T_688 : \n node _T_689 = eq(_T_686, UInt<1>(0h0)) \n when _T_689 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_686, UInt<1>(0h1), \"\") : assert_100 \n node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_691 = asUInt(reset) \n node _T_692 = eq(_T_691, UInt<1>(0h0)) \n when _T_692 : \n node _T_693 = eq(_T_690, UInt<1>(0h0)) \n when _T_693 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_690, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_696 = or(_T_694, _T_695) \n node _T_697 = asUInt(reset) \n node _T_698 = eq(_T_697, UInt<1>(0h0)) \n when _T_698 : \n node _T_699 = eq(_T_696, UInt<1>(0h0)) \n when _T_699 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_696, UInt<1>(0h1), \"\") : assert_102 \n node _T_700 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_701 = asUInt(reset) \n node _T_702 = eq(_T_701, UInt<1>(0h0)) \n when _T_702 : \n node _T_703 = eq(_T_700, UInt<1>(0h0)) \n when _T_703 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_700, UInt<1>(0h1), \"\") : assert_103 \n node _T_704 = and(io.in.d.valid, d_first_1) \n node _T_705 = and(_T_704, a_first_1) \n node _T_706 = and(_T_705, io.in.a.valid) \n node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_708 = and(_T_706, _T_707) \n node _T_709 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_710 = and(_T_708, _T_709) \n when _T_710 : \n node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_712 = or(_T_711, io.in.a.ready) \n node _T_713 = asUInt(reset) \n node _T_714 = eq(_T_713, UInt<1>(0h0)) \n when _T_714 : \n node _T_715 = eq(_T_712, UInt<1>(0h0)) \n when _T_715 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_712, UInt<1>(0h1), \"\") : assert_104 \n node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_717 = orr(a_set_wo_ready) \n node _T_718 = eq(_T_717, UInt<1>(0h0)) \n node _T_719 = or(_T_716, _T_718) \n node _T_720 = asUInt(reset) \n node _T_721 = eq(_T_720, UInt<1>(0h0)) \n when _T_721 : \n node _T_722 = eq(_T_719, UInt<1>(0h0)) \n when _T_722 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_719, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_86 \n node _T_723 = orr(inflight) \n node _T_724 = eq(_T_723, UInt<1>(0h0)) \n node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_726 = or(_T_724, _T_725) \n node _T_727 = lt(watchdog, plusarg_reader.out) \n node _T_728 = or(_T_726, _T_727) \n node _T_729 = asUInt(reset) \n node _T_730 = eq(_T_729, UInt<1>(0h0)) \n when _T_730 : \n node _T_731 = eq(_T_728, UInt<1>(0h0)) \n when _T_731 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_728, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_732 = and(io.in.a.ready, io.in.a.valid) \n node _T_733 = and(io.in.d.ready, io.in.d.valid) \n node _T_734 = or(_T_732, _T_733) \n when _T_734 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) \n regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) \n regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<10> \n connect c_set, UInt<10>(0h0) \n wire c_set_wo_ready : UInt<10> \n connect c_set_wo_ready, UInt<10>(0h0) \n wire c_opcodes_set : UInt<40> \n connect c_opcodes_set, UInt<40>(0h0) \n wire c_sizes_set : UInt<40> \n connect c_sizes_set, UInt<40>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<4> \n connect c_sizes_set_interm, UInt<4>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<4>(0h0) \n connect _WIRE_6.bits.size, UInt<3>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_735 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<4>(0h0) \n connect _WIRE_8.bits.size, UInt<3>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_738 = and(_T_736, _T_737) \n node _T_739 = and(_T_735, _T_738) \n when _T_739 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<4>(0h0) \n connect _WIRE_10.bits.size, UInt<3>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_741 = and(_T_740, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<4>(0h0) \n connect _WIRE_12.bits.size, UInt<3>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_744 = and(_T_742, _T_743) \n node _T_745 = and(_T_741, _T_744) \n when _T_745 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<4>(0h0) \n connect _WIRE_14.bits.size, UInt<3>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_746 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_747 = bits(_T_746, 0, 0) \n node _T_748 = eq(_T_747, UInt<1>(0h0)) \n node _T_749 = asUInt(reset) \n node _T_750 = eq(_T_749, UInt<1>(0h0)) \n when _T_750 : \n node _T_751 = eq(_T_748, UInt<1>(0h0)) \n when _T_751 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_748, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<10> \n connect d_clr_1, UInt<10>(0h0) \n wire d_clr_wo_ready_1 : UInt<10> \n connect d_clr_wo_ready_1, UInt<10>(0h0) \n wire d_opcodes_clr_1 : UInt<40> \n connect d_opcodes_clr_1, UInt<40>(0h0) \n wire d_sizes_clr_1 : UInt<40> \n connect d_sizes_clr_1, UInt<40>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_752 = and(io.in.d.valid, d_first_2) \n node _T_753 = and(_T_752, UInt<1>(0h1)) \n node _T_754 = and(_T_753, d_release_ack_1) \n when _T_754 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_755 = and(io.in.d.ready, io.in.d.valid) \n node _T_756 = and(_T_755, d_first_2) \n node _T_757 = and(_T_756, UInt<1>(0h1)) \n node _T_758 = and(_T_757, d_release_ack_1) \n when _T_758 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_759 = and(io.in.d.valid, d_first_2) \n node _T_760 = and(_T_759, UInt<1>(0h1)) \n node _T_761 = and(_T_760, d_release_ack_1) \n when _T_761 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_762 = dshr(inflight_1, io.in.d.bits.source) \n node _T_763 = bits(_T_762, 0, 0) \n node _T_764 = or(_T_763, same_cycle_resp_1) \n node _T_765 = asUInt(reset) \n node _T_766 = eq(_T_765, UInt<1>(0h0)) \n when _T_766 : \n node _T_767 = eq(_T_764, UInt<1>(0h0)) \n when _T_767 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_764, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<32>(0h0) \n connect _WIRE_16.bits.source, UInt<4>(0h0) \n connect _WIRE_16.bits.size, UInt<3>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_769 = asUInt(reset) \n node _T_770 = eq(_T_769, UInt<1>(0h0)) \n when _T_770 : \n node _T_771 = eq(_T_768, UInt<1>(0h0)) \n when _T_771 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_768, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_772 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_773 = asUInt(reset) \n node _T_774 = eq(_T_773, UInt<1>(0h0)) \n when _T_774 : \n node _T_775 = eq(_T_772, UInt<1>(0h0)) \n when _T_775 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_772, UInt<1>(0h1), \"\") : assert_110 \n node _T_776 = and(io.in.d.valid, d_first_2) \n node _T_777 = and(_T_776, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<32>(0h0) \n connect _WIRE_18.bits.source, UInt<4>(0h0) \n connect _WIRE_18.bits.size, UInt<3>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_778 = and(_T_777, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<32>(0h0) \n connect _WIRE_20.bits.source, UInt<4>(0h0) \n connect _WIRE_20.bits.size, UInt<3>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_780 = and(_T_778, _T_779) \n node _T_781 = and(_T_780, d_release_ack_1) \n node _T_782 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_783 = and(_T_781, _T_782) \n when _T_783 : \n node _T_784 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<32>(0h0) \n connect _WIRE_22.bits.source, UInt<4>(0h0) \n connect _WIRE_22.bits.size, UInt<3>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_785 = or(_T_784, _WIRE_23.ready) \n node _T_786 = asUInt(reset) \n node _T_787 = eq(_T_786, UInt<1>(0h0)) \n when _T_787 : \n node _T_788 = eq(_T_785, UInt<1>(0h0)) \n when _T_788 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_785, UInt<1>(0h1), \"\") : assert_111 \n node _T_789 = orr(c_set_wo_ready) \n when _T_789 : \n node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_791 = asUInt(reset) \n node _T_792 = eq(_T_791, UInt<1>(0h0)) \n when _T_792 : \n node _T_793 = eq(_T_790, UInt<1>(0h0)) \n when _T_793 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_790, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_87 \n node _T_794 = orr(inflight_1) \n node _T_795 = eq(_T_794, UInt<1>(0h0)) \n node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_797 = or(_T_795, _T_796) \n node _T_798 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_799 = or(_T_797, _T_798) \n node _T_800 = asUInt(reset) \n node _T_801 = eq(_T_800, UInt<1>(0h0)) \n when _T_801 : \n node _T_802 = eq(_T_799, UInt<1>(0h0)) \n when _T_802 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_799, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<4>(0h0) \n connect _WIRE_24.bits.size, UInt<3>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_804 = and(io.in.d.ready, io.in.d.valid) \n node _T_805 = or(_T_803, _T_804) \n when _T_805 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_43(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [130:0] _c_opcodes_set_T_1 = 131'h0;\t// @[Monitor.scala:767:54]\n wire [130:0] _c_sizes_set_T_1 = 131'h0;\t// @[Monitor.scala:768:52]\n wire [6:0] _c_opcodes_set_T = 7'h0;\t// @[Monitor.scala:767:79]\n wire [6:0] _c_sizes_set_T = 7'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [15:0] _c_set_wo_ready_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [15:0] _c_set_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [39:0] c_opcodes_set = 40'h0;\t// @[Monitor.scala:740:34]\n wire [39:0] c_sizes_set = 40'h0;\t// @[Monitor.scala:741:34]\n wire [9:0] c_set = 10'h0;\t// @[Monitor.scala:738:34]\n wire [9:0] c_set_wo_ready = 10'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [3:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_732;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_732;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [3:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_805;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_805;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_805;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [3:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [9:0] inflight;\t// @[Monitor.scala:614:27]\n reg [39:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [39:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [9:0] a_set;\t// @[Monitor.scala:626:34]\n wire [9:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [39:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [39:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [6:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [6:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [6:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [6:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [6:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [6:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [6:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [6:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire _T_658 = _T_732 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [6:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [6:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [9:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [9:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [39:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [39:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_704 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire _T_673 = _T_805 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [9:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [9:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [9:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [9:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [39:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [39:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [9:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [9:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [39:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [39:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_776 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire _T_758 = _T_805 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [9:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":35469,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Tile_158 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} \n\n\n inst tile_0_0 of PE_414 \n connect tile_0_0.clock, clock\n\n connect tile_0_0.reset, reset\n\n connect tile_0_0.io.in_a, io.in_a[0] \n connect tile_0_0.io.in_b, io.in_b[0] \n connect tile_0_0.io.in_d, io.in_d[0] \n connect tile_0_0.io.in_control.shift, io.in_control[0].shift \n connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate \n connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow \n connect tile_0_0.io.in_valid, io.in_valid[0] \n connect tile_0_0.io.in_id, io.in_id[0] \n connect tile_0_0.io.in_last, io.in_last[0] \n connect io.out_c[0], tile_0_0.io.out_c \n connect io.out_control[0], tile_0_0.io.out_control \n connect io.out_id[0], tile_0_0.io.out_id \n connect io.out_last[0], tile_0_0.io.out_last \n connect io.out_valid[0], tile_0_0.io.out_valid \n connect io.out_b[0], tile_0_0.io.out_b \n connect io.bad_dataflow, tile_0_0.io.bad_dataflow \n connect io.out_a[0], tile_0_0.io.out_a"},"response":{"kind":"string","value":"module Tile_158(\t// @[Tile.scala:16:7]\n input clock,\t// @[Tile.scala:16:7]\n input reset,\t// @[Tile.scala:16:7]\n input [7:0] io_in_a_0,\t// @[Tile.scala:17:14]\n input [19:0] io_in_b_0,\t// @[Tile.scala:17:14]\n input [19:0] io_in_d_0,\t// @[Tile.scala:17:14]\n input io_in_control_0_dataflow,\t// @[Tile.scala:17:14]\n input io_in_control_0_propagate,\t// @[Tile.scala:17:14]\n input [4:0] io_in_control_0_shift,\t// @[Tile.scala:17:14]\n input [2:0] io_in_id_0,\t// @[Tile.scala:17:14]\n input io_in_last_0,\t// @[Tile.scala:17:14]\n output [7:0] io_out_a_0,\t// @[Tile.scala:17:14]\n output [19:0] io_out_c_0,\t// @[Tile.scala:17:14]\n output [19:0] io_out_b_0,\t// @[Tile.scala:17:14]\n output io_out_control_0_dataflow,\t// @[Tile.scala:17:14]\n output io_out_control_0_propagate,\t// @[Tile.scala:17:14]\n output [4:0] io_out_control_0_shift,\t// @[Tile.scala:17:14]\n output [2:0] io_out_id_0,\t// @[Tile.scala:17:14]\n output io_out_last_0,\t// @[Tile.scala:17:14]\n input io_in_valid_0,\t// @[Tile.scala:17:14]\n output io_out_valid_0\t// @[Tile.scala:17:14]\n);\n\n wire [7:0] io_in_a_0_0 = io_in_a_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_in_b_0_0 = io_in_b_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_in_d_0_0 = io_in_d_0;\t// @[Tile.scala:16:7]\n wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow;\t// @[Tile.scala:16:7]\n wire io_in_control_0_propagate_0 = io_in_control_0_propagate;\t// @[Tile.scala:16:7]\n wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift;\t// @[Tile.scala:16:7]\n wire [2:0] io_in_id_0_0 = io_in_id_0;\t// @[Tile.scala:16:7]\n wire io_in_last_0_0 = io_in_last_0;\t// @[Tile.scala:16:7]\n wire io_in_valid_0_0 = io_in_valid_0;\t// @[Tile.scala:16:7]\n wire io_bad_dataflow = 1'h0;\t// @[Tile.scala:16:7, :17:14, :42:44]\n wire [7:0] io_out_a_0_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_out_c_0_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_out_b_0_0;\t// @[Tile.scala:16:7]\n wire io_out_control_0_dataflow_0;\t// @[Tile.scala:16:7]\n wire io_out_control_0_propagate_0;\t// @[Tile.scala:16:7]\n wire [4:0] io_out_control_0_shift_0;\t// @[Tile.scala:16:7]\n wire [2:0] io_out_id_0_0;\t// @[Tile.scala:16:7]\n wire io_out_last_0_0;\t// @[Tile.scala:16:7]\n wire io_out_valid_0_0;\t// @[Tile.scala:16:7]\n PE_414 tile_0_0 (\t// @[Tile.scala:42:44]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0_0),\t// @[Tile.scala:16:7]\n .io_in_b (io_in_b_0_0),\t// @[Tile.scala:16:7]\n .io_in_d (io_in_d_0_0),\t// @[Tile.scala:16:7]\n .io_out_a (io_out_a_0_0),\n .io_out_b (io_out_b_0_0),\n .io_out_c (io_out_c_0_0),\n .io_in_control_dataflow (io_in_control_0_dataflow_0),\t// @[Tile.scala:16:7]\n .io_in_control_propagate (io_in_control_0_propagate_0),\t// @[Tile.scala:16:7]\n .io_in_control_shift (io_in_control_0_shift_0),\t// @[Tile.scala:16:7]\n .io_out_control_dataflow (io_out_control_0_dataflow_0),\n .io_out_control_propagate (io_out_control_0_propagate_0),\n .io_out_control_shift (io_out_control_0_shift_0),\n .io_in_id (io_in_id_0_0),\t// @[Tile.scala:16:7]\n .io_out_id (io_out_id_0_0),\n .io_in_last (io_in_last_0_0),\t// @[Tile.scala:16:7]\n .io_out_last (io_out_last_0_0),\n .io_in_valid (io_in_valid_0_0),\t// @[Tile.scala:16:7]\n .io_out_valid (io_out_valid_0_0)\n );\t// @[Tile.scala:42:44]\n assign io_out_a_0 = io_out_a_0_0;\t// @[Tile.scala:16:7]\n assign io_out_c_0 = io_out_c_0_0;\t// @[Tile.scala:16:7]\n assign io_out_b_0 = io_out_b_0_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_dataflow = io_out_control_0_dataflow_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_propagate = io_out_control_0_propagate_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_shift = io_out_control_0_shift_0;\t// @[Tile.scala:16:7]\n assign io_out_id_0 = io_out_id_0_0;\t// @[Tile.scala:16:7]\n assign io_out_last_0 = io_out_last_0_0;\t// @[Tile.scala:16:7]\n assign io_out_valid_0 = io_out_valid_0_0;\t// @[Tile.scala:16:7]\nendmodule"}}},{"rowIdx":35470,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Tile_56 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} \n\n\n inst tile_0_0 of PE_312 \n connect tile_0_0.clock, clock\n\n connect tile_0_0.reset, reset\n\n connect tile_0_0.io.in_a, io.in_a[0] \n connect tile_0_0.io.in_b, io.in_b[0] \n connect tile_0_0.io.in_d, io.in_d[0] \n connect tile_0_0.io.in_control.shift, io.in_control[0].shift \n connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate \n connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow \n connect tile_0_0.io.in_valid, io.in_valid[0] \n connect tile_0_0.io.in_id, io.in_id[0] \n connect tile_0_0.io.in_last, io.in_last[0] \n connect io.out_c[0], tile_0_0.io.out_c \n connect io.out_control[0], tile_0_0.io.out_control \n connect io.out_id[0], tile_0_0.io.out_id \n connect io.out_last[0], tile_0_0.io.out_last \n connect io.out_valid[0], tile_0_0.io.out_valid \n connect io.out_b[0], tile_0_0.io.out_b \n connect io.bad_dataflow, tile_0_0.io.bad_dataflow \n connect io.out_a[0], tile_0_0.io.out_a"},"response":{"kind":"string","value":"module Tile_56(\t// @[Tile.scala:16:7]\n input clock,\t// @[Tile.scala:16:7]\n input reset,\t// @[Tile.scala:16:7]\n input [7:0] io_in_a_0,\t// @[Tile.scala:17:14]\n input [19:0] io_in_b_0,\t// @[Tile.scala:17:14]\n input [19:0] io_in_d_0,\t// @[Tile.scala:17:14]\n input io_in_control_0_dataflow,\t// @[Tile.scala:17:14]\n input io_in_control_0_propagate,\t// @[Tile.scala:17:14]\n input [4:0] io_in_control_0_shift,\t// @[Tile.scala:17:14]\n input [2:0] io_in_id_0,\t// @[Tile.scala:17:14]\n input io_in_last_0,\t// @[Tile.scala:17:14]\n output [7:0] io_out_a_0,\t// @[Tile.scala:17:14]\n output [19:0] io_out_c_0,\t// @[Tile.scala:17:14]\n output [19:0] io_out_b_0,\t// @[Tile.scala:17:14]\n output io_out_control_0_dataflow,\t// @[Tile.scala:17:14]\n output io_out_control_0_propagate,\t// @[Tile.scala:17:14]\n output [4:0] io_out_control_0_shift,\t// @[Tile.scala:17:14]\n output [2:0] io_out_id_0,\t// @[Tile.scala:17:14]\n output io_out_last_0,\t// @[Tile.scala:17:14]\n input io_in_valid_0,\t// @[Tile.scala:17:14]\n output io_out_valid_0\t// @[Tile.scala:17:14]\n);\n\n wire [7:0] io_in_a_0_0 = io_in_a_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_in_b_0_0 = io_in_b_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_in_d_0_0 = io_in_d_0;\t// @[Tile.scala:16:7]\n wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow;\t// @[Tile.scala:16:7]\n wire io_in_control_0_propagate_0 = io_in_control_0_propagate;\t// @[Tile.scala:16:7]\n wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift;\t// @[Tile.scala:16:7]\n wire [2:0] io_in_id_0_0 = io_in_id_0;\t// @[Tile.scala:16:7]\n wire io_in_last_0_0 = io_in_last_0;\t// @[Tile.scala:16:7]\n wire io_in_valid_0_0 = io_in_valid_0;\t// @[Tile.scala:16:7]\n wire io_bad_dataflow = 1'h0;\t// @[Tile.scala:16:7, :17:14, :42:44]\n wire [7:0] io_out_a_0_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_out_c_0_0;\t// @[Tile.scala:16:7]\n wire [19:0] io_out_b_0_0;\t// @[Tile.scala:16:7]\n wire io_out_control_0_dataflow_0;\t// @[Tile.scala:16:7]\n wire io_out_control_0_propagate_0;\t// @[Tile.scala:16:7]\n wire [4:0] io_out_control_0_shift_0;\t// @[Tile.scala:16:7]\n wire [2:0] io_out_id_0_0;\t// @[Tile.scala:16:7]\n wire io_out_last_0_0;\t// @[Tile.scala:16:7]\n wire io_out_valid_0_0;\t// @[Tile.scala:16:7]\n PE_312 tile_0_0 (\t// @[Tile.scala:42:44]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0_0),\t// @[Tile.scala:16:7]\n .io_in_b (io_in_b_0_0),\t// @[Tile.scala:16:7]\n .io_in_d (io_in_d_0_0),\t// @[Tile.scala:16:7]\n .io_out_a (io_out_a_0_0),\n .io_out_b (io_out_b_0_0),\n .io_out_c (io_out_c_0_0),\n .io_in_control_dataflow (io_in_control_0_dataflow_0),\t// @[Tile.scala:16:7]\n .io_in_control_propagate (io_in_control_0_propagate_0),\t// @[Tile.scala:16:7]\n .io_in_control_shift (io_in_control_0_shift_0),\t// @[Tile.scala:16:7]\n .io_out_control_dataflow (io_out_control_0_dataflow_0),\n .io_out_control_propagate (io_out_control_0_propagate_0),\n .io_out_control_shift (io_out_control_0_shift_0),\n .io_in_id (io_in_id_0_0),\t// @[Tile.scala:16:7]\n .io_out_id (io_out_id_0_0),\n .io_in_last (io_in_last_0_0),\t// @[Tile.scala:16:7]\n .io_out_last (io_out_last_0_0),\n .io_in_valid (io_in_valid_0_0),\t// @[Tile.scala:16:7]\n .io_out_valid (io_out_valid_0_0)\n );\t// @[Tile.scala:42:44]\n assign io_out_a_0 = io_out_a_0_0;\t// @[Tile.scala:16:7]\n assign io_out_c_0 = io_out_c_0_0;\t// @[Tile.scala:16:7]\n assign io_out_b_0 = io_out_b_0_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_dataflow = io_out_control_0_dataflow_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_propagate = io_out_control_0_propagate_0;\t// @[Tile.scala:16:7]\n assign io_out_control_0_shift = io_out_control_0_shift_0;\t// @[Tile.scala:16:7]\n assign io_out_id_0 = io_out_id_0_0;\t// @[Tile.scala:16:7]\n assign io_out_last_0 = io_out_last_0_0;\t// @[Tile.scala:16:7]\n assign io_out_valid_0 = io_out_valid_0_0;\t// @[Tile.scala:16:7]\nendmodule"}}},{"rowIdx":35471,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLNoC_1_router_10ClockSinkDomain : \n output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip clock_in : { clock : Clock, reset : Reset}} \n output clock : Clock \n output reset : Reset \n\n\n wire childClock : Clock \n wire childReset : Reset \n node _childClock_T = asClock(UInt<1>(0h0)) \n connect childClock, _childClock_T \n invalidate childReset \n inst routers of Router_39 \n connect routers.clock, childClock\n\n connect routers.reset, childReset\n\n wire clockNodeIn : { clock : Clock, reset : Reset} \n invalidate clockNodeIn.reset \n invalidate clockNodeIn.clock \n connect clockNodeIn, auto.clock_in \n connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0 \n connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1 \n connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2 \n connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free \n connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return \n connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit \n connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free \n connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return \n connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit \n connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free \n connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return \n connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit \n connect auto.routers_debug_out, routers.auto.debug_out \n connect childClock, clockNodeIn.clock \n connect childReset, clockNodeIn.reset \n connect clock, clockNodeIn.clock \n connect reset, clockNodeIn.reset"},"response":{"kind":"string","value":"module TLNoC_1_router_10ClockSinkDomain(\t// @[ClockDomain.scala:14:9]\n output [2:0] auto_routers_debug_out_va_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_debug_out_va_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_debug_out_va_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_debug_out_sa_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_debug_out_sa_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_debug_out_sa_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_2_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_2_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_2_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_2_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_2_vc_free,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_routers_source_nodes_out_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_source_nodes_out_0_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_2_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_2_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_2_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_2_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_2_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_routers_dest_nodes_in_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_routers_dest_nodes_in_0_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_clock,\t// @[LazyModuleImp.scala:107:25]\n input auto_clock_in_reset\t// @[LazyModuleImp.scala:107:25]\n);\n\n Router_39 routers (\t// @[NoC.scala:67:22]\n .clock (auto_clock_in_clock),\n .reset (auto_clock_in_reset),\n .auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),\n .auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),\n .auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),\n .auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),\n .auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),\n .auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),\n .auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),\n .auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),\n .auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),\n .auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),\n .auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),\n .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),\n .auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),\n .auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),\n .auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),\n .auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),\n .auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),\n .auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),\n .auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),\n .auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),\n .auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),\n .auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),\n .auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),\n .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),\n .auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),\n .auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),\n .auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),\n .auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),\n .auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),\n .auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),\n .auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),\n .auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),\n .auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),\n .auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),\n .auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),\n .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),\n .auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),\n .auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),\n .auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),\n .auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),\n .auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),\n .auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),\n .auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),\n .auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),\n .auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),\n .auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),\n .auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),\n .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),\n .auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),\n .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),\n .auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),\n .auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),\n .auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),\n .auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),\n .auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),\n .auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),\n .auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),\n .auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),\n .auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),\n .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),\n .auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),\n .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),\n .auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),\n .auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),\n .auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),\n .auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),\n .auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),\n .auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),\n .auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),\n .auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),\n .auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),\n .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),\n .auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),\n .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),\n .auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),\n .auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),\n .auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),\n .auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)\n );\t// @[NoC.scala:67:22]\nendmodule"}}},{"rowIdx":35472,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e5_s11_5 : \n output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<23>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} \n\n\n node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) \n node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) \n node _sigSum_T = bits(io.mulAddResult, 22, 22) \n node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) \n node _sigSum_T_2 = tail(_sigSum_T_1, 1) \n node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) \n node _sigSum_T_4 = bits(io.mulAddResult, 21, 0) \n node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) \n node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) \n node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) \n node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) \n node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) \n node CDom_sExp = asSInt(_CDom_sExp_T_2) \n node _CDom_absSigSum_T = bits(sigSum, 35, 12) \n node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) \n node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 12, 11) \n node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) \n node _CDom_absSigSum_T_4 = bits(sigSum, 33, 13) \n node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) \n node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) \n node _CDom_absSigSumExtra_T = bits(sigSum, 11, 1) \n node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) \n node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) \n node _CDom_absSigSumExtra_T_3 = bits(sigSum, 12, 1) \n node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) \n node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) \n node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) \n node CDom_mainSig = bits(_CDom_mainSig_T, 23, 8) \n node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 10, 0) \n node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 0) \n wire CDom_reduced4SigExtra_reducedVec : UInt<1>[3] \n node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) \n node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) \n connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 \n node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) \n node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) \n connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 \n node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 10, 8) \n node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) \n connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 \n node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) \n node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec[0]) \n node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) \n node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) \n node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<5>(0h10)), _CDom_reduced4SigExtra_T_4) \n node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 2, 1) \n node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 0, 0) \n node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_5, 1, 1) \n node _CDom_reduced4SigExtra_T_8 = cat(_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7) \n node _CDom_reduced4SigExtra_T_9 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_8) \n node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_9) \n node _CDom_sig_T = shr(CDom_mainSig, 3) \n node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) \n node _CDom_sig_T_2 = orr(_CDom_sig_T_1) \n node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) \n node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) \n node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) \n node notCDom_signSigSum = bits(sigSum, 25, 25) \n node _notCDom_absSigSum_T = bits(sigSum, 24, 0) \n node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) \n node _notCDom_absSigSum_T_2 = bits(sigSum, 24, 0) \n node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) \n node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) \n node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) \n wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[13] \n node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) \n node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) \n node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) \n node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) \n node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) \n node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) \n node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) \n node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) \n node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) \n node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) \n node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) \n node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) \n node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 \n node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 24, 24) \n node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) \n connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 \n node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) \n node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) \n node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) \n node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) \n node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) \n node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) \n node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) \n node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) \n node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) \n node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) \n node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) \n node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) \n node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) \n node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) \n node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) \n node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) \n node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) \n node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) \n node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) \n node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) \n node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) \n node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) \n node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) \n node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) \n node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) \n node _notCDom_normDistReduced2_T_13 = mux(_notCDom_normDistReduced2_T_1, UInt<4>(0hb), UInt<4>(0hc)) \n node _notCDom_normDistReduced2_T_14 = mux(_notCDom_normDistReduced2_T_2, UInt<4>(0ha), _notCDom_normDistReduced2_T_13) \n node _notCDom_normDistReduced2_T_15 = mux(_notCDom_normDistReduced2_T_3, UInt<4>(0h9), _notCDom_normDistReduced2_T_14) \n node _notCDom_normDistReduced2_T_16 = mux(_notCDom_normDistReduced2_T_4, UInt<4>(0h8), _notCDom_normDistReduced2_T_15) \n node _notCDom_normDistReduced2_T_17 = mux(_notCDom_normDistReduced2_T_5, UInt<3>(0h7), _notCDom_normDistReduced2_T_16) \n node _notCDom_normDistReduced2_T_18 = mux(_notCDom_normDistReduced2_T_6, UInt<3>(0h6), _notCDom_normDistReduced2_T_17) \n node _notCDom_normDistReduced2_T_19 = mux(_notCDom_normDistReduced2_T_7, UInt<3>(0h5), _notCDom_normDistReduced2_T_18) \n node _notCDom_normDistReduced2_T_20 = mux(_notCDom_normDistReduced2_T_8, UInt<3>(0h4), _notCDom_normDistReduced2_T_19) \n node _notCDom_normDistReduced2_T_21 = mux(_notCDom_normDistReduced2_T_9, UInt<2>(0h3), _notCDom_normDistReduced2_T_20) \n node _notCDom_normDistReduced2_T_22 = mux(_notCDom_normDistReduced2_T_10, UInt<2>(0h2), _notCDom_normDistReduced2_T_21) \n node _notCDom_normDistReduced2_T_23 = mux(_notCDom_normDistReduced2_T_11, UInt<1>(0h1), _notCDom_normDistReduced2_T_22) \n node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_12, UInt<1>(0h0), _notCDom_normDistReduced2_T_23) \n node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) \n node _notCDom_sExp_T = cvt(notCDom_nearNormDist) \n node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) \n node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) \n node notCDom_sExp = asSInt(_notCDom_sExp_T_2) \n node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) \n node notCDom_mainSig = bits(_notCDom_mainSig_T, 25, 10) \n node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 5, 0) \n node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 1) \n wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[4] \n node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) \n node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) \n connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) \n node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) \n connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) \n node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) \n connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 \n node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 6, 6) \n node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) \n connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 \n node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_reducedVec[1], notCDom_reduced4SigExtra_reducedVec[0]) \n node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_reducedVec[3], notCDom_reduced4SigExtra_reducedVec[2]) \n node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) \n node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) \n node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) \n node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _notCDom_reduced4SigExtra_T_4) \n node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 3, 1) \n node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 1, 0) \n node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 0, 0) \n node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_6, 1, 1) \n node _notCDom_reduced4SigExtra_T_9 = cat(_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8) \n node _notCDom_reduced4SigExtra_T_10 = bits(_notCDom_reduced4SigExtra_T_5, 2, 2) \n node _notCDom_reduced4SigExtra_T_11 = cat(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10) \n node _notCDom_reduced4SigExtra_T_12 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_11) \n node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_12) \n node _notCDom_sig_T = shr(notCDom_mainSig, 3) \n node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) \n node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) \n node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) \n node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) \n node _notCDom_completeCancellation_T = bits(notCDom_sig, 13, 12) \n node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) \n node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) \n node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) \n node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) \n node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) \n node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) \n node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) \n node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) \n node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) \n node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) \n node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) \n node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) \n node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) \n node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) \n node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) \n node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) \n node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) \n connect io.invalidExc, _io_invalidExc_T_9 \n node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) \n connect io.rawOut.isNaN, _io_rawOut_isNaN_T \n connect io.rawOut.isInf, notNaN_isInfOut \n node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) \n node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) \n node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) \n connect io.rawOut.isZero, _io_rawOut_isZero_T_2 \n node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) \n node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) \n node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) \n node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) \n node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) \n node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) \n node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) \n node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) \n node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) \n node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) \n node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) \n node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) \n node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) \n node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) \n node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) \n node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) \n node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) \n node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) \n connect io.rawOut.sign, _io_rawOut_sign_T_17 \n node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) \n connect io.rawOut.sExp, _io_rawOut_sExp_T \n node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) \n connect io.rawOut.sig, _io_rawOut_sig_T"},"response":{"kind":"string","value":"module MulAddRecFNToRaw_postMul_e5_s11_5(\t// @[MulAddRecFN.scala:169:7]\n input io_fromPreMul_isSigNaNAny,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isNaNAOrB,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isInfA,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isZeroA,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isInfB,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isZeroB,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_signProd,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isNaNC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isInfC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_isZeroC,\t// @[MulAddRecFN.scala:172:16]\n input [6:0] io_fromPreMul_sExpSum,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_doSubMags,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_CIsDominant,\t// @[MulAddRecFN.scala:172:16]\n input [3:0] io_fromPreMul_CDom_CAlignDist,\t// @[MulAddRecFN.scala:172:16]\n input [12:0] io_fromPreMul_highAlignedSigC,\t// @[MulAddRecFN.scala:172:16]\n input io_fromPreMul_bit0AlignedSigC,\t// @[MulAddRecFN.scala:172:16]\n input [22:0] io_mulAddResult,\t// @[MulAddRecFN.scala:172:16]\n input [2:0] io_roundingMode,\t// @[MulAddRecFN.scala:172:16]\n output io_invalidExc,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isNaN,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isInf,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_isZero,\t// @[MulAddRecFN.scala:172:16]\n output io_rawOut_sign,\t// @[MulAddRecFN.scala:172:16]\n output [6:0] io_rawOut_sExp,\t// @[MulAddRecFN.scala:172:16]\n output [13:0] io_rawOut_sig\t// @[MulAddRecFN.scala:172:16]\n);\n\n wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC;\t// @[MulAddRecFN.scala:169:7]\n wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant;\t// @[MulAddRecFN.scala:169:7]\n wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist;\t// @[MulAddRecFN.scala:169:7]\n wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC;\t// @[MulAddRecFN.scala:169:7]\n wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC;\t// @[MulAddRecFN.scala:169:7]\n wire [22:0] io_mulAddResult_0 = io_mulAddResult;\t// @[MulAddRecFN.scala:169:7]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[MulAddRecFN.scala:169:7]\n wire _io_invalidExc_T_9;\t// @[MulAddRecFN.scala:273:57]\n wire _io_rawOut_isNaN_T;\t// @[MulAddRecFN.scala:278:48]\n wire notNaN_isInfOut;\t// @[MulAddRecFN.scala:265:44]\n wire _io_rawOut_isZero_T_2;\t// @[MulAddRecFN.scala:282:25]\n wire _io_rawOut_sign_T_17;\t// @[MulAddRecFN.scala:290:50]\n wire [6:0] _io_rawOut_sExp_T;\t// @[MulAddRecFN.scala:293:26]\n wire [13:0] _io_rawOut_sig_T;\t// @[MulAddRecFN.scala:294:25]\n wire io_rawOut_isNaN_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_isInf_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_isZero_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_rawOut_sign_0;\t// @[MulAddRecFN.scala:169:7]\n wire [6:0] io_rawOut_sExp_0;\t// @[MulAddRecFN.scala:169:7]\n wire [13:0] io_rawOut_sig_0;\t// @[MulAddRecFN.scala:169:7]\n wire io_invalidExc_0;\t// @[MulAddRecFN.scala:169:7]\n wire roundingMode_min = io_roundingMode_0 == 3'h2;\t// @[MulAddRecFN.scala:169:7, :186:45]\n wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0;\t// @[MulAddRecFN.scala:169:7, :190:42]\n wire _sigSum_T = io_mulAddResult_0[22];\t// @[MulAddRecFN.scala:169:7, :192:32]\n wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1;\t// @[MulAddRecFN.scala:169:7, :193:47]\n wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0];\t// @[MulAddRecFN.scala:193:47]\n wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0;\t// @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]\n wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0];\t// @[MulAddRecFN.scala:169:7, :196:28]\n wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4};\t// @[MulAddRecFN.scala:192:{12,16}, :196:28]\n wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0};\t// @[MulAddRecFN.scala:169:7, :192:12]\n wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0};\t// @[MulAddRecFN.scala:169:7, :203:69]\n wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0};\t// @[MulAddRecFN.scala:169:7, :203:43]\n wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T};\t// @[MulAddRecFN.scala:203:{43,69}]\n wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0];\t// @[MulAddRecFN.scala:203:43]\n wire [6:0] CDom_sExp = _CDom_sExp_T_2;\t// @[MulAddRecFN.scala:203:43]\n wire [23:0] _CDom_absSigSum_T = sigSum[35:12];\t// @[MulAddRecFN.scala:192:12, :206:20]\n wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T;\t// @[MulAddRecFN.scala:206:{13,20}]\n wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11];\t// @[MulAddRecFN.scala:169:7, :209:46]\n wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2};\t// @[MulAddRecFN.scala:207:22, :209:46]\n wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13];\t// @[MulAddRecFN.scala:192:12, :210:23]\n wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4};\t// @[MulAddRecFN.scala:207:22, :209:71, :210:23]\n wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5;\t// @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]\n wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1];\t// @[MulAddRecFN.scala:192:12, :215:21]\n wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T;\t// @[MulAddRecFN.scala:215:{14,21}]\n wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1;\t// @[MulAddRecFN.scala:215:{14,36}]\n wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1];\t// @[MulAddRecFN.scala:192:12, :216:19]\n wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3;\t// @[MulAddRecFN.scala:216:{19,37}]\n wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4;\t// @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]\n wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0;\t// @[MulAddRecFN.scala:169:7, :205:12, :219:24]\n wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8];\t// @[MulAddRecFN.scala:219:{24,56}]\n wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0];\t// @[MulAddRecFN.scala:205:12, :222:36]\n wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T;\t// @[MulAddRecFN.scala:222:{36,53}]\n wire _CDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:120:54]\n wire _CDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:123:57]\n wire CDom_reduced4SigExtra_reducedVec_0;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_1;\t// @[primitives.scala:118:30]\n wire CDom_reduced4SigExtra_reducedVec_2;\t// @[primitives.scala:118:30]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4];\t// @[primitives.scala:120:33]\n assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T;\t// @[primitives.scala:120:{33,54}]\n assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:118:30, :120:54]\n wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8];\t// @[primitives.scala:123:15]\n assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T;\t// @[primitives.scala:123:{15,57}]\n assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:118:30, :123:57]\n wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1};\t// @[primitives.scala:118:30, :124:20]\n wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0};\t// @[primitives.scala:118:30, :124:20]\n wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2];\t// @[MulAddRecFN.scala:169:7, :223:51]\n wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3;\t// @[primitives.scala:52:21]\n wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4);\t// @[primitives.scala:52:21, :76:56]\n wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1];\t// @[primitives.scala:76:56, :78:22]\n wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0];\t// @[primitives.scala:77:20, :78:22]\n wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1];\t// @[primitives.scala:77:20, :78:22]\n wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7};\t// @[primitives.scala:77:20]\n wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8};\t// @[primitives.scala:77:20, :124:20]\n wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_9;\t// @[MulAddRecFN.scala:222:72, :223:73]\n wire [12:0] _CDom_sig_T = CDom_mainSig[15:3];\t// @[MulAddRecFN.scala:219:56, :225:25]\n wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0];\t// @[MulAddRecFN.scala:219:56, :226:25]\n wire _CDom_sig_T_2 = |_CDom_sig_T_1;\t// @[MulAddRecFN.scala:226:{25,32}]\n wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra;\t// @[MulAddRecFN.scala:223:73, :226:{32,36}]\n wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra;\t// @[MulAddRecFN.scala:214:12, :226:{36,61}]\n wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4};\t// @[MulAddRecFN.scala:225:{12,25}, :226:61]\n wire notCDom_signSigSum = sigSum[25];\t// @[MulAddRecFN.scala:192:12, :232:36]\n wire [24:0] _notCDom_absSigSum_T = sigSum[24:0];\t// @[MulAddRecFN.scala:192:12, :235:20]\n wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0];\t// @[MulAddRecFN.scala:192:12, :235:20, :236:19]\n wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T;\t// @[MulAddRecFN.scala:235:{13,20}]\n wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0};\t// @[MulAddRecFN.scala:169:7, :236:{19,41}]\n wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0];\t// @[MulAddRecFN.scala:236:41]\n wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4;\t// @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]\n wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1;\t// @[primitives.scala:106:57]\n wire notCDom_reduced2AbsSigSum_reducedVec_0;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_1;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_2;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_3;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_4;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_5;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_6;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_7;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_8;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_9;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_10;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_11;\t// @[primitives.scala:101:30]\n wire notCDom_reduced2AbsSigSum_reducedVec_12;\t// @[primitives.scala:101:30]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24];\t// @[primitives.scala:106:15]\n assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T;\t// @[primitives.scala:106:{15,57}]\n assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1;\t// @[primitives.scala:101:30, :106:57]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3};\t// @[primitives.scala:101:30, :107:20]\n wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo};\t// @[primitives.scala:107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7};\t// @[primitives.scala:101:30, :107:20]\n wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11};\t// @[primitives.scala:101:30, :107:20]\n wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo};\t// @[primitives.scala:107:20]\n wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo};\t// @[primitives.scala:107:20]\n wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo};\t// @[primitives.scala:107:20]\n wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11];\t// @[primitives.scala:91:52, :107:20]\n wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12];\t// @[primitives.scala:91:52, :107:20]\n wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21;\t// @[Mux.scala:50:70]\n wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22;\t// @[Mux.scala:50:70]\n wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23;\t// @[Mux.scala:50:70]\n wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0};\t// @[Mux.scala:50:70]\n wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist};\t// @[MulAddRecFN.scala:240:56, :241:76]\n wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T};\t// @[MulAddRecFN.scala:203:43, :241:{46,76}]\n wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0];\t// @[MulAddRecFN.scala:241:46]\n wire [6:0] notCDom_sExp = _notCDom_sExp_T_2;\t// @[MulAddRecFN.scala:241:46]\n wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist;\t// @[MulAddRecFN.scala:234:12, :240:56, :243:27]\n wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10];\t// @[MulAddRecFN.scala:243:{27,50}]\n wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0];\t// @[primitives.scala:107:20]\n wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0};\t// @[MulAddRecFN.scala:247:{39,55}]\n wire _notCDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:106:57]\n wire notCDom_reduced4SigExtra_reducedVec_0;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_1;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_2;\t// @[primitives.scala:101:30]\n wire notCDom_reduced4SigExtra_reducedVec_3;\t// @[primitives.scala:101:30]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4];\t// @[primitives.scala:103:33]\n assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T;\t// @[primitives.scala:103:{33,54}]\n assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1;\t// @[primitives.scala:101:30, :103:54]\n wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6];\t// @[primitives.scala:106:15]\n assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T;\t// @[primitives.scala:106:{15,57}]\n assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1;\t// @[primitives.scala:101:30, :106:57]\n wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0};\t// @[primitives.scala:101:30, :107:20]\n wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2};\t// @[primitives.scala:101:30, :107:20]\n wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo};\t// @[primitives.scala:107:20]\n wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1];\t// @[Mux.scala:50:70]\n wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3;\t// @[primitives.scala:52:21]\n wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4);\t// @[primitives.scala:52:21, :76:56]\n wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1];\t// @[primitives.scala:76:56, :78:22]\n wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0];\t// @[primitives.scala:77:20, :78:22]\n wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0];\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1];\t// @[primitives.scala:77:20]\n wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8};\t// @[primitives.scala:77:20]\n wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2];\t// @[primitives.scala:77:20, :78:22]\n wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10};\t// @[primitives.scala:77:20]\n wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11};\t// @[primitives.scala:77:20, :107:20]\n wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_12;\t// @[MulAddRecFN.scala:247:78, :249:11]\n wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3];\t// @[MulAddRecFN.scala:243:50, :251:28]\n wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0];\t// @[MulAddRecFN.scala:243:50, :252:28]\n wire _notCDom_sig_T_2 = |_notCDom_sig_T_1;\t// @[MulAddRecFN.scala:252:{28,35}]\n wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra;\t// @[MulAddRecFN.scala:249:11, :252:{35,39}]\n wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3};\t// @[MulAddRecFN.scala:251:{12,28}, :252:39]\n wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12];\t// @[MulAddRecFN.scala:251:12, :255:21]\n wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0;\t// @[primitives.scala:103:54]\n wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum;\t// @[MulAddRecFN.scala:169:7, :232:36, :259:36]\n wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T;\t// @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36]\n wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0;\t// @[MulAddRecFN.scala:169:7, :264:49]\n wire notNaN_isInfProd;\t// @[MulAddRecFN.scala:264:49]\n assign notNaN_isInfProd = _GEN_0;\t// @[MulAddRecFN.scala:264:49]\n wire _io_invalidExc_T_5;\t// @[MulAddRecFN.scala:275:36]\n assign _io_invalidExc_T_5 = _GEN_0;\t// @[MulAddRecFN.scala:264:49, :275:36]\n assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0;\t// @[MulAddRecFN.scala:169:7, :264:49, :265:44]\n assign io_rawOut_isInf_0 = notNaN_isInfOut;\t// @[MulAddRecFN.scala:169:7, :265:44]\n wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0;\t// @[MulAddRecFN.scala:169:7, :267:32]\n wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0;\t// @[MulAddRecFN.scala:169:7, :267:{32,58}]\n wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0;\t// @[MulAddRecFN.scala:169:7, :272:31]\n wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T;\t// @[MulAddRecFN.scala:169:7, :271:35, :272:31]\n wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0;\t// @[MulAddRecFN.scala:169:7, :273:32]\n wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2;\t// @[MulAddRecFN.scala:271:35, :272:57, :273:32]\n wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0;\t// @[MulAddRecFN.scala:169:7, :274:10]\n wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5;\t// @[MulAddRecFN.scala:274:{10,36}, :275:36]\n wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0;\t// @[MulAddRecFN.scala:169:7, :274:36, :275:61]\n wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0;\t// @[MulAddRecFN.scala:169:7, :275:61, :276:35]\n assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8;\t// @[MulAddRecFN.scala:272:57, :273:57, :276:35]\n assign io_invalidExc_0 = _io_invalidExc_T_9;\t// @[MulAddRecFN.scala:169:7, :273:57]\n assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0;\t// @[MulAddRecFN.scala:169:7, :278:48]\n assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T;\t// @[MulAddRecFN.scala:169:7, :278:48]\n wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0;\t// @[MulAddRecFN.scala:169:7, :283:14]\n wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation;\t// @[MulAddRecFN.scala:255:50, :283:{14,42}]\n assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1;\t// @[MulAddRecFN.scala:267:58, :282:25, :283:42]\n assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2;\t// @[MulAddRecFN.scala:169:7, :282:25]\n wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0;\t// @[MulAddRecFN.scala:169:7, :264:49, :285:27]\n wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC;\t// @[MulAddRecFN.scala:169:7, :190:42, :286:31]\n wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1;\t// @[MulAddRecFN.scala:285:{27,54}, :286:31]\n wire _io_rawOut_sign_T_3 = ~roundingMode_min;\t// @[MulAddRecFN.scala:186:45, :287:29]\n wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3;\t// @[MulAddRecFN.scala:267:58, :287:{26,29}]\n wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0;\t// @[MulAddRecFN.scala:169:7, :287:{26,48}]\n wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC;\t// @[MulAddRecFN.scala:190:42, :287:48, :288:36]\n wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6;\t// @[MulAddRecFN.scala:285:54, :286:43, :288:36]\n wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min;\t// @[MulAddRecFN.scala:186:45, :267:58, :289:26]\n wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC;\t// @[MulAddRecFN.scala:169:7, :190:42, :290:37]\n wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9;\t// @[MulAddRecFN.scala:289:{26,46}, :290:37]\n wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10;\t// @[MulAddRecFN.scala:286:43, :288:48, :289:46]\n wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut;\t// @[MulAddRecFN.scala:265:44, :291:10]\n wire _io_rawOut_sign_T_13 = ~notNaN_addZeros;\t// @[MulAddRecFN.scala:267:58, :291:31]\n wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13;\t// @[MulAddRecFN.scala:291:{10,28,31}]\n wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign;\t// @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]\n wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15;\t// @[MulAddRecFN.scala:291:{28,49}, :292:17]\n assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16;\t// @[MulAddRecFN.scala:288:48, :290:50, :291:49]\n assign io_rawOut_sign_0 = _io_rawOut_sign_T_17;\t// @[MulAddRecFN.scala:169:7, :290:50]\n assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp;\t// @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]\n assign io_rawOut_sExp_0 = _io_rawOut_sExp_T;\t// @[MulAddRecFN.scala:169:7, :293:26]\n assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig;\t// @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]\n assign io_rawOut_sig_0 = _io_rawOut_sig_T;\t// @[MulAddRecFN.scala:169:7, :294:25]\n assign io_invalidExc = io_invalidExc_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isNaN = io_rawOut_isNaN_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isInf = io_rawOut_isInf_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_isZero = io_rawOut_isZero_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sign = io_rawOut_sign_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sExp = io_rawOut_sExp_0;\t// @[MulAddRecFN.scala:169:7]\n assign io_rawOut_sig = io_rawOut_sig_0;\t// @[MulAddRecFN.scala:169:7]\nendmodule"}}},{"rowIdx":35473,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 2) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) \n node _source_ok_T_6 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) \n node _source_ok_T_12 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) \n node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) \n node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) \n node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) \n node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) \n node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) \n node _source_ok_T_18 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) \n node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) \n node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) \n node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) \n node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) \n wire _source_ok_WIRE : UInt<1>[4] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n connect _source_ok_WIRE[1], _source_ok_T_11 \n connect _source_ok_WIRE[2], _source_ok_T_17 \n connect _source_ok_WIRE[3], _source_ok_T_23 \n node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) \n node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) \n node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) \n node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 1, 0) \n node _T_4 = shr(io.in.a.bits.source, 2) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<2>(0h3)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) \n node _T_17 = shr(io.in.a.bits.source, 2) \n node _T_18 = eq(_T_17, UInt<1>(0h1)) \n node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_20 = and(_T_18, _T_19) \n node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) \n node _T_22 = and(_T_20, _T_21) \n node _T_23 = eq(_T_22, UInt<1>(0h0)) \n node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_25 = cvt(_T_24) \n node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) \n node _T_27 = asSInt(_T_26) \n node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) \n node _T_29 = or(_T_23, _T_28) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) \n node _T_30 = shr(io.in.a.bits.source, 2) \n node _T_31 = eq(_T_30, UInt<2>(0h2)) \n node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_33 = and(_T_31, _T_32) \n node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) \n node _T_35 = and(_T_33, _T_34) \n node _T_36 = eq(_T_35, UInt<1>(0h0)) \n node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_38 = cvt(_T_37) \n node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) \n node _T_40 = asSInt(_T_39) \n node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) \n node _T_42 = or(_T_36, _T_41) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) \n node _T_43 = shr(io.in.a.bits.source, 2) \n node _T_44 = eq(_T_43, UInt<2>(0h3)) \n node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) \n node _T_48 = and(_T_46, _T_47) \n node _T_49 = eq(_T_48, UInt<1>(0h0)) \n node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_51 = cvt(_T_50) \n node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) \n node _T_53 = asSInt(_T_52) \n node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) \n node _T_55 = or(_T_49, _T_54) \n node _T_56 = and(_T_16, _T_29) \n node _T_57 = and(_T_56, _T_42) \n node _T_58 = and(_T_57, _T_55) \n node _T_59 = asUInt(reset) \n node _T_60 = eq(_T_59, UInt<1>(0h0)) \n when _T_60 : \n node _T_61 = eq(_T_58, UInt<1>(0h0)) \n when _T_61 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_58, UInt<1>(0h1), \"\") : assert_1 \n node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_62 : \n node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_65 = and(_T_63, _T_64) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) \n node _T_66 = shr(io.in.a.bits.source, 2) \n node _T_67 = eq(_T_66, UInt<1>(0h0)) \n node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_69 = and(_T_67, _T_68) \n node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) \n node _T_71 = and(_T_69, _T_70) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) \n node _T_72 = shr(io.in.a.bits.source, 2) \n node _T_73 = eq(_T_72, UInt<1>(0h1)) \n node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_75 = and(_T_73, _T_74) \n node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) \n node _T_77 = and(_T_75, _T_76) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) \n node _T_78 = shr(io.in.a.bits.source, 2) \n node _T_79 = eq(_T_78, UInt<2>(0h2)) \n node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_81 = and(_T_79, _T_80) \n node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) \n node _T_83 = and(_T_81, _T_82) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) \n node _T_84 = shr(io.in.a.bits.source, 2) \n node _T_85 = eq(_T_84, UInt<2>(0h3)) \n node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_87 = and(_T_85, _T_86) \n node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) \n node _T_89 = and(_T_87, _T_88) \n node _T_90 = or(_T_71, _T_77) \n node _T_91 = or(_T_90, _T_83) \n node _T_92 = or(_T_91, _T_89) \n node _T_93 = and(_T_65, _T_92) \n node _T_94 = or(UInt<1>(0h0), _T_93) \n node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_97 = cvt(_T_96) \n node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) \n node _T_99 = asSInt(_T_98) \n node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) \n node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_102 = cvt(_T_101) \n node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) \n node _T_104 = asSInt(_T_103) \n node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) \n node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_107 = cvt(_T_106) \n node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) \n node _T_109 = asSInt(_T_108) \n node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) \n node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_112 = cvt(_T_111) \n node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) \n node _T_114 = asSInt(_T_113) \n node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) \n node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_117 = cvt(_T_116) \n node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) \n node _T_119 = asSInt(_T_118) \n node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) \n node _T_121 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_122 = cvt(_T_121) \n node _T_123 = and(_T_122, asSInt(UInt<27>(0h4000000))) \n node _T_124 = asSInt(_T_123) \n node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) \n node _T_126 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_127 = cvt(_T_126) \n node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000))) \n node _T_129 = asSInt(_T_128) \n node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) \n node _T_131 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_132 = cvt(_T_131) \n node _T_133 = and(_T_132, asSInt(UInt<30>(0h20000000))) \n node _T_134 = asSInt(_T_133) \n node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) \n node _T_136 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_137 = cvt(_T_136) \n node _T_138 = and(_T_137, asSInt(UInt<15>(0h4000))) \n node _T_139 = asSInt(_T_138) \n node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) \n node _T_141 = or(_T_100, _T_105) \n node _T_142 = or(_T_141, _T_110) \n node _T_143 = or(_T_142, _T_115) \n node _T_144 = or(_T_143, _T_120) \n node _T_145 = or(_T_144, _T_125) \n node _T_146 = or(_T_145, _T_130) \n node _T_147 = or(_T_146, _T_135) \n node _T_148 = or(_T_147, _T_140) \n node _T_149 = and(_T_95, _T_148) \n node _T_150 = or(UInt<1>(0h0), _T_149) \n node _T_151 = and(_T_94, _T_150) \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(_T_151, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_151, UInt<1>(0h1), \"\") : assert_2 \n node _T_155 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_156 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_157 = and(_T_155, _T_156) \n node _T_158 = or(UInt<1>(0h0), _T_157) \n node _T_159 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_160 = cvt(_T_159) \n node _T_161 = and(_T_160, asSInt(UInt<14>(0h2000))) \n node _T_162 = asSInt(_T_161) \n node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) \n node _T_164 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_165 = cvt(_T_164) \n node _T_166 = and(_T_165, asSInt(UInt<13>(0h1000))) \n node _T_167 = asSInt(_T_166) \n node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) \n node _T_169 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_170 = cvt(_T_169) \n node _T_171 = and(_T_170, asSInt(UInt<17>(0h10000))) \n node _T_172 = asSInt(_T_171) \n node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) \n node _T_174 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_175 = cvt(_T_174) \n node _T_176 = and(_T_175, asSInt(UInt<18>(0h2f000))) \n node _T_177 = asSInt(_T_176) \n node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) \n node _T_179 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_180 = cvt(_T_179) \n node _T_181 = and(_T_180, asSInt(UInt<17>(0h10000))) \n node _T_182 = asSInt(_T_181) \n node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) \n node _T_184 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_185 = cvt(_T_184) \n node _T_186 = and(_T_185, asSInt(UInt<27>(0h4000000))) \n node _T_187 = asSInt(_T_186) \n node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) \n node _T_189 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_190 = cvt(_T_189) \n node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) \n node _T_192 = asSInt(_T_191) \n node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) \n node _T_194 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_195 = cvt(_T_194) \n node _T_196 = and(_T_195, asSInt(UInt<30>(0h20000000))) \n node _T_197 = asSInt(_T_196) \n node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) \n node _T_199 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_200 = cvt(_T_199) \n node _T_201 = and(_T_200, asSInt(UInt<15>(0h4000))) \n node _T_202 = asSInt(_T_201) \n node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) \n node _T_204 = or(_T_163, _T_168) \n node _T_205 = or(_T_204, _T_173) \n node _T_206 = or(_T_205, _T_178) \n node _T_207 = or(_T_206, _T_183) \n node _T_208 = or(_T_207, _T_188) \n node _T_209 = or(_T_208, _T_193) \n node _T_210 = or(_T_209, _T_198) \n node _T_211 = or(_T_210, _T_203) \n node _T_212 = and(_T_158, _T_211) \n node _T_213 = or(UInt<1>(0h0), _T_212) \n node _T_214 = and(UInt<1>(0h0), _T_213) \n node _T_215 = asUInt(reset) \n node _T_216 = eq(_T_215, UInt<1>(0h0)) \n when _T_216 : \n node _T_217 = eq(_T_214, UInt<1>(0h0)) \n when _T_217 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_214, UInt<1>(0h1), \"\") : assert_3 \n node _T_218 = asUInt(reset) \n node _T_219 = eq(_T_218, UInt<1>(0h0)) \n when _T_219 : \n node _T_220 = eq(source_ok, UInt<1>(0h0)) \n when _T_220 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_4 \n node _T_221 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_T_221, UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_221, UInt<1>(0h1), \"\") : assert_5 \n node _T_225 = asUInt(reset) \n node _T_226 = eq(_T_225, UInt<1>(0h0)) \n when _T_226 : \n node _T_227 = eq(is_aligned, UInt<1>(0h0)) \n when _T_227 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_228 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_229 = asUInt(reset) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n when _T_230 : \n node _T_231 = eq(_T_228, UInt<1>(0h0)) \n when _T_231 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_228, UInt<1>(0h1), \"\") : assert_7 \n node _T_232 = not(io.in.a.bits.mask) \n node _T_233 = eq(_T_232, UInt<1>(0h0)) \n node _T_234 = asUInt(reset) \n node _T_235 = eq(_T_234, UInt<1>(0h0)) \n when _T_235 : \n node _T_236 = eq(_T_233, UInt<1>(0h0)) \n when _T_236 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_233, UInt<1>(0h1), \"\") : assert_8 \n node _T_237 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_238 = asUInt(reset) \n node _T_239 = eq(_T_238, UInt<1>(0h0)) \n when _T_239 : \n node _T_240 = eq(_T_237, UInt<1>(0h0)) \n when _T_240 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_237, UInt<1>(0h1), \"\") : assert_9 \n node _T_241 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_241 : \n node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_244 = and(_T_242, _T_243) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) \n node _T_245 = shr(io.in.a.bits.source, 2) \n node _T_246 = eq(_T_245, UInt<1>(0h0)) \n node _T_247 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_248 = and(_T_246, _T_247) \n node _T_249 = leq(uncommonBits_8, UInt<2>(0h3)) \n node _T_250 = and(_T_248, _T_249) \n node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) \n node _T_251 = shr(io.in.a.bits.source, 2) \n node _T_252 = eq(_T_251, UInt<1>(0h1)) \n node _T_253 = leq(UInt<1>(0h0), uncommonBits_9) \n node _T_254 = and(_T_252, _T_253) \n node _T_255 = leq(uncommonBits_9, UInt<2>(0h3)) \n node _T_256 = and(_T_254, _T_255) \n node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) \n node _T_257 = shr(io.in.a.bits.source, 2) \n node _T_258 = eq(_T_257, UInt<2>(0h2)) \n node _T_259 = leq(UInt<1>(0h0), uncommonBits_10) \n node _T_260 = and(_T_258, _T_259) \n node _T_261 = leq(uncommonBits_10, UInt<2>(0h3)) \n node _T_262 = and(_T_260, _T_261) \n node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) \n node _T_263 = shr(io.in.a.bits.source, 2) \n node _T_264 = eq(_T_263, UInt<2>(0h3)) \n node _T_265 = leq(UInt<1>(0h0), uncommonBits_11) \n node _T_266 = and(_T_264, _T_265) \n node _T_267 = leq(uncommonBits_11, UInt<2>(0h3)) \n node _T_268 = and(_T_266, _T_267) \n node _T_269 = or(_T_250, _T_256) \n node _T_270 = or(_T_269, _T_262) \n node _T_271 = or(_T_270, _T_268) \n node _T_272 = and(_T_244, _T_271) \n node _T_273 = or(UInt<1>(0h0), _T_272) \n node _T_274 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_275 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_276 = cvt(_T_275) \n node _T_277 = and(_T_276, asSInt(UInt<14>(0h2000))) \n node _T_278 = asSInt(_T_277) \n node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0))) \n node _T_280 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_281 = cvt(_T_280) \n node _T_282 = and(_T_281, asSInt(UInt<13>(0h1000))) \n node _T_283 = asSInt(_T_282) \n node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0))) \n node _T_285 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_286 = cvt(_T_285) \n node _T_287 = and(_T_286, asSInt(UInt<17>(0h10000))) \n node _T_288 = asSInt(_T_287) \n node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0))) \n node _T_290 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_291 = cvt(_T_290) \n node _T_292 = and(_T_291, asSInt(UInt<18>(0h2f000))) \n node _T_293 = asSInt(_T_292) \n node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) \n node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_296 = cvt(_T_295) \n node _T_297 = and(_T_296, asSInt(UInt<17>(0h10000))) \n node _T_298 = asSInt(_T_297) \n node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) \n node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_301 = cvt(_T_300) \n node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000))) \n node _T_303 = asSInt(_T_302) \n node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) \n node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_306 = cvt(_T_305) \n node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000))) \n node _T_308 = asSInt(_T_307) \n node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) \n node _T_310 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_311 = cvt(_T_310) \n node _T_312 = and(_T_311, asSInt(UInt<30>(0h20000000))) \n node _T_313 = asSInt(_T_312) \n node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) \n node _T_315 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_316 = cvt(_T_315) \n node _T_317 = and(_T_316, asSInt(UInt<15>(0h4000))) \n node _T_318 = asSInt(_T_317) \n node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) \n node _T_320 = or(_T_279, _T_284) \n node _T_321 = or(_T_320, _T_289) \n node _T_322 = or(_T_321, _T_294) \n node _T_323 = or(_T_322, _T_299) \n node _T_324 = or(_T_323, _T_304) \n node _T_325 = or(_T_324, _T_309) \n node _T_326 = or(_T_325, _T_314) \n node _T_327 = or(_T_326, _T_319) \n node _T_328 = and(_T_274, _T_327) \n node _T_329 = or(UInt<1>(0h0), _T_328) \n node _T_330 = and(_T_273, _T_329) \n node _T_331 = asUInt(reset) \n node _T_332 = eq(_T_331, UInt<1>(0h0)) \n when _T_332 : \n node _T_333 = eq(_T_330, UInt<1>(0h0)) \n when _T_333 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_330, UInt<1>(0h1), \"\") : assert_10 \n node _T_334 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_335 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_336 = and(_T_334, _T_335) \n node _T_337 = or(UInt<1>(0h0), _T_336) \n node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_339 = cvt(_T_338) \n node _T_340 = and(_T_339, asSInt(UInt<14>(0h2000))) \n node _T_341 = asSInt(_T_340) \n node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) \n node _T_343 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_344 = cvt(_T_343) \n node _T_345 = and(_T_344, asSInt(UInt<13>(0h1000))) \n node _T_346 = asSInt(_T_345) \n node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) \n node _T_348 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_349 = cvt(_T_348) \n node _T_350 = and(_T_349, asSInt(UInt<17>(0h10000))) \n node _T_351 = asSInt(_T_350) \n node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) \n node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_354 = cvt(_T_353) \n node _T_355 = and(_T_354, asSInt(UInt<18>(0h2f000))) \n node _T_356 = asSInt(_T_355) \n node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) \n node _T_358 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_359 = cvt(_T_358) \n node _T_360 = and(_T_359, asSInt(UInt<17>(0h10000))) \n node _T_361 = asSInt(_T_360) \n node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) \n node _T_363 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_364 = cvt(_T_363) \n node _T_365 = and(_T_364, asSInt(UInt<27>(0h4000000))) \n node _T_366 = asSInt(_T_365) \n node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0))) \n node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_369 = cvt(_T_368) \n node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000))) \n node _T_371 = asSInt(_T_370) \n node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) \n node _T_373 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_374 = cvt(_T_373) \n node _T_375 = and(_T_374, asSInt(UInt<30>(0h20000000))) \n node _T_376 = asSInt(_T_375) \n node _T_377 = eq(_T_376, asSInt(UInt<1>(0h0))) \n node _T_378 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_379 = cvt(_T_378) \n node _T_380 = and(_T_379, asSInt(UInt<15>(0h4000))) \n node _T_381 = asSInt(_T_380) \n node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) \n node _T_383 = or(_T_342, _T_347) \n node _T_384 = or(_T_383, _T_352) \n node _T_385 = or(_T_384, _T_357) \n node _T_386 = or(_T_385, _T_362) \n node _T_387 = or(_T_386, _T_367) \n node _T_388 = or(_T_387, _T_372) \n node _T_389 = or(_T_388, _T_377) \n node _T_390 = or(_T_389, _T_382) \n node _T_391 = and(_T_337, _T_390) \n node _T_392 = or(UInt<1>(0h0), _T_391) \n node _T_393 = and(UInt<1>(0h0), _T_392) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_11 \n node _T_397 = asUInt(reset) \n node _T_398 = eq(_T_397, UInt<1>(0h0)) \n when _T_398 : \n node _T_399 = eq(source_ok, UInt<1>(0h0)) \n when _T_399 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_12 \n node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_401 = asUInt(reset) \n node _T_402 = eq(_T_401, UInt<1>(0h0)) \n when _T_402 : \n node _T_403 = eq(_T_400, UInt<1>(0h0)) \n when _T_403 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_400, UInt<1>(0h1), \"\") : assert_13 \n node _T_404 = asUInt(reset) \n node _T_405 = eq(_T_404, UInt<1>(0h0)) \n when _T_405 : \n node _T_406 = eq(is_aligned, UInt<1>(0h0)) \n when _T_406 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_408 = asUInt(reset) \n node _T_409 = eq(_T_408, UInt<1>(0h0)) \n when _T_409 : \n node _T_410 = eq(_T_407, UInt<1>(0h0)) \n when _T_410 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_407, UInt<1>(0h1), \"\") : assert_15 \n node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_T_411, UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_411, UInt<1>(0h1), \"\") : assert_16 \n node _T_415 = not(io.in.a.bits.mask) \n node _T_416 = eq(_T_415, UInt<1>(0h0)) \n node _T_417 = asUInt(reset) \n node _T_418 = eq(_T_417, UInt<1>(0h0)) \n when _T_418 : \n node _T_419 = eq(_T_416, UInt<1>(0h0)) \n when _T_419 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_416, UInt<1>(0h1), \"\") : assert_17 \n node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_421 = asUInt(reset) \n node _T_422 = eq(_T_421, UInt<1>(0h0)) \n when _T_422 : \n node _T_423 = eq(_T_420, UInt<1>(0h0)) \n when _T_423 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_420, UInt<1>(0h1), \"\") : assert_18 \n node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_424 : \n node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_427 = and(_T_425, _T_426) \n node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) \n node _T_428 = shr(io.in.a.bits.source, 2) \n node _T_429 = eq(_T_428, UInt<1>(0h0)) \n node _T_430 = leq(UInt<1>(0h0), uncommonBits_12) \n node _T_431 = and(_T_429, _T_430) \n node _T_432 = leq(uncommonBits_12, UInt<2>(0h3)) \n node _T_433 = and(_T_431, _T_432) \n node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) \n node _T_434 = shr(io.in.a.bits.source, 2) \n node _T_435 = eq(_T_434, UInt<1>(0h1)) \n node _T_436 = leq(UInt<1>(0h0), uncommonBits_13) \n node _T_437 = and(_T_435, _T_436) \n node _T_438 = leq(uncommonBits_13, UInt<2>(0h3)) \n node _T_439 = and(_T_437, _T_438) \n node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) \n node _T_440 = shr(io.in.a.bits.source, 2) \n node _T_441 = eq(_T_440, UInt<2>(0h2)) \n node _T_442 = leq(UInt<1>(0h0), uncommonBits_14) \n node _T_443 = and(_T_441, _T_442) \n node _T_444 = leq(uncommonBits_14, UInt<2>(0h3)) \n node _T_445 = and(_T_443, _T_444) \n node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) \n node _T_446 = shr(io.in.a.bits.source, 2) \n node _T_447 = eq(_T_446, UInt<2>(0h3)) \n node _T_448 = leq(UInt<1>(0h0), uncommonBits_15) \n node _T_449 = and(_T_447, _T_448) \n node _T_450 = leq(uncommonBits_15, UInt<2>(0h3)) \n node _T_451 = and(_T_449, _T_450) \n node _T_452 = or(_T_433, _T_439) \n node _T_453 = or(_T_452, _T_445) \n node _T_454 = or(_T_453, _T_451) \n node _T_455 = and(_T_427, _T_454) \n node _T_456 = or(UInt<1>(0h0), _T_455) \n node _T_457 = asUInt(reset) \n node _T_458 = eq(_T_457, UInt<1>(0h0)) \n when _T_458 : \n node _T_459 = eq(_T_456, UInt<1>(0h0)) \n when _T_459 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_456, UInt<1>(0h1), \"\") : assert_19 \n node _T_460 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_461 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_462 = and(_T_460, _T_461) \n node _T_463 = or(UInt<1>(0h0), _T_462) \n node _T_464 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_465 = cvt(_T_464) \n node _T_466 = and(_T_465, asSInt(UInt<13>(0h1000))) \n node _T_467 = asSInt(_T_466) \n node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) \n node _T_469 = and(_T_463, _T_468) \n node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_471 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_472 = and(_T_470, _T_471) \n node _T_473 = or(UInt<1>(0h0), _T_472) \n node _T_474 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_475 = cvt(_T_474) \n node _T_476 = and(_T_475, asSInt(UInt<14>(0h2000))) \n node _T_477 = asSInt(_T_476) \n node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) \n node _T_479 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_480 = cvt(_T_479) \n node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000))) \n node _T_482 = asSInt(_T_481) \n node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0))) \n node _T_484 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_485 = cvt(_T_484) \n node _T_486 = and(_T_485, asSInt(UInt<18>(0h2f000))) \n node _T_487 = asSInt(_T_486) \n node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0))) \n node _T_489 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_490 = cvt(_T_489) \n node _T_491 = and(_T_490, asSInt(UInt<17>(0h10000))) \n node _T_492 = asSInt(_T_491) \n node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0))) \n node _T_494 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_495 = cvt(_T_494) \n node _T_496 = and(_T_495, asSInt(UInt<27>(0h4000000))) \n node _T_497 = asSInt(_T_496) \n node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) \n node _T_499 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_500 = cvt(_T_499) \n node _T_501 = and(_T_500, asSInt(UInt<13>(0h1000))) \n node _T_502 = asSInt(_T_501) \n node _T_503 = eq(_T_502, asSInt(UInt<1>(0h0))) \n node _T_504 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_505 = cvt(_T_504) \n node _T_506 = and(_T_505, asSInt(UInt<30>(0h20000000))) \n node _T_507 = asSInt(_T_506) \n node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) \n node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_510 = cvt(_T_509) \n node _T_511 = and(_T_510, asSInt(UInt<15>(0h4000))) \n node _T_512 = asSInt(_T_511) \n node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) \n node _T_514 = or(_T_478, _T_483) \n node _T_515 = or(_T_514, _T_488) \n node _T_516 = or(_T_515, _T_493) \n node _T_517 = or(_T_516, _T_498) \n node _T_518 = or(_T_517, _T_503) \n node _T_519 = or(_T_518, _T_508) \n node _T_520 = or(_T_519, _T_513) \n node _T_521 = and(_T_473, _T_520) \n node _T_522 = or(UInt<1>(0h0), _T_469) \n node _T_523 = or(_T_522, _T_521) \n node _T_524 = asUInt(reset) \n node _T_525 = eq(_T_524, UInt<1>(0h0)) \n when _T_525 : \n node _T_526 = eq(_T_523, UInt<1>(0h0)) \n when _T_526 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_523, UInt<1>(0h1), \"\") : assert_20 \n node _T_527 = asUInt(reset) \n node _T_528 = eq(_T_527, UInt<1>(0h0)) \n when _T_528 : \n node _T_529 = eq(source_ok, UInt<1>(0h0)) \n when _T_529 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_21 \n node _T_530 = asUInt(reset) \n node _T_531 = eq(_T_530, UInt<1>(0h0)) \n when _T_531 : \n node _T_532 = eq(is_aligned, UInt<1>(0h0)) \n when _T_532 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_534 = asUInt(reset) \n node _T_535 = eq(_T_534, UInt<1>(0h0)) \n when _T_535 : \n node _T_536 = eq(_T_533, UInt<1>(0h0)) \n when _T_536 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_533, UInt<1>(0h1), \"\") : assert_23 \n node _T_537 = eq(io.in.a.bits.mask, mask) \n node _T_538 = asUInt(reset) \n node _T_539 = eq(_T_538, UInt<1>(0h0)) \n when _T_539 : \n node _T_540 = eq(_T_537, UInt<1>(0h0)) \n when _T_540 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_537, UInt<1>(0h1), \"\") : assert_24 \n node _T_541 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_542 = asUInt(reset) \n node _T_543 = eq(_T_542, UInt<1>(0h0)) \n when _T_543 : \n node _T_544 = eq(_T_541, UInt<1>(0h0)) \n when _T_544 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_541, UInt<1>(0h1), \"\") : assert_25 \n node _T_545 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_545 : \n node _T_546 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_547 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_548 = and(_T_546, _T_547) \n node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) \n node _T_549 = shr(io.in.a.bits.source, 2) \n node _T_550 = eq(_T_549, UInt<1>(0h0)) \n node _T_551 = leq(UInt<1>(0h0), uncommonBits_16) \n node _T_552 = and(_T_550, _T_551) \n node _T_553 = leq(uncommonBits_16, UInt<2>(0h3)) \n node _T_554 = and(_T_552, _T_553) \n node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) \n node _T_555 = shr(io.in.a.bits.source, 2) \n node _T_556 = eq(_T_555, UInt<1>(0h1)) \n node _T_557 = leq(UInt<1>(0h0), uncommonBits_17) \n node _T_558 = and(_T_556, _T_557) \n node _T_559 = leq(uncommonBits_17, UInt<2>(0h3)) \n node _T_560 = and(_T_558, _T_559) \n node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) \n node _T_561 = shr(io.in.a.bits.source, 2) \n node _T_562 = eq(_T_561, UInt<2>(0h2)) \n node _T_563 = leq(UInt<1>(0h0), uncommonBits_18) \n node _T_564 = and(_T_562, _T_563) \n node _T_565 = leq(uncommonBits_18, UInt<2>(0h3)) \n node _T_566 = and(_T_564, _T_565) \n node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) \n node _T_567 = shr(io.in.a.bits.source, 2) \n node _T_568 = eq(_T_567, UInt<2>(0h3)) \n node _T_569 = leq(UInt<1>(0h0), uncommonBits_19) \n node _T_570 = and(_T_568, _T_569) \n node _T_571 = leq(uncommonBits_19, UInt<2>(0h3)) \n node _T_572 = and(_T_570, _T_571) \n node _T_573 = or(_T_554, _T_560) \n node _T_574 = or(_T_573, _T_566) \n node _T_575 = or(_T_574, _T_572) \n node _T_576 = and(_T_548, _T_575) \n node _T_577 = or(UInt<1>(0h0), _T_576) \n node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_580 = and(_T_578, _T_579) \n node _T_581 = or(UInt<1>(0h0), _T_580) \n node _T_582 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_583 = cvt(_T_582) \n node _T_584 = and(_T_583, asSInt(UInt<13>(0h1000))) \n node _T_585 = asSInt(_T_584) \n node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) \n node _T_587 = and(_T_581, _T_586) \n node _T_588 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_589 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_590 = and(_T_588, _T_589) \n node _T_591 = or(UInt<1>(0h0), _T_590) \n node _T_592 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_593 = cvt(_T_592) \n node _T_594 = and(_T_593, asSInt(UInt<14>(0h2000))) \n node _T_595 = asSInt(_T_594) \n node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) \n node _T_597 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_598 = cvt(_T_597) \n node _T_599 = and(_T_598, asSInt(UInt<18>(0h2f000))) \n node _T_600 = asSInt(_T_599) \n node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) \n node _T_602 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_603 = cvt(_T_602) \n node _T_604 = and(_T_603, asSInt(UInt<17>(0h10000))) \n node _T_605 = asSInt(_T_604) \n node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0))) \n node _T_607 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_608 = cvt(_T_607) \n node _T_609 = and(_T_608, asSInt(UInt<27>(0h4000000))) \n node _T_610 = asSInt(_T_609) \n node _T_611 = eq(_T_610, asSInt(UInt<1>(0h0))) \n node _T_612 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_613 = cvt(_T_612) \n node _T_614 = and(_T_613, asSInt(UInt<13>(0h1000))) \n node _T_615 = asSInt(_T_614) \n node _T_616 = eq(_T_615, asSInt(UInt<1>(0h0))) \n node _T_617 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_618 = cvt(_T_617) \n node _T_619 = and(_T_618, asSInt(UInt<15>(0h4000))) \n node _T_620 = asSInt(_T_619) \n node _T_621 = eq(_T_620, asSInt(UInt<1>(0h0))) \n node _T_622 = or(_T_596, _T_601) \n node _T_623 = or(_T_622, _T_606) \n node _T_624 = or(_T_623, _T_611) \n node _T_625 = or(_T_624, _T_616) \n node _T_626 = or(_T_625, _T_621) \n node _T_627 = and(_T_591, _T_626) \n node _T_628 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_629 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_630 = cvt(_T_629) \n node _T_631 = and(_T_630, asSInt(UInt<17>(0h10000))) \n node _T_632 = asSInt(_T_631) \n node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) \n node _T_634 = and(_T_628, _T_633) \n node _T_635 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_636 = leq(io.in.a.bits.size, UInt<4>(0h8)) \n node _T_637 = and(_T_635, _T_636) \n node _T_638 = or(UInt<1>(0h0), _T_637) \n node _T_639 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_640 = cvt(_T_639) \n node _T_641 = and(_T_640, asSInt(UInt<30>(0h20000000))) \n node _T_642 = asSInt(_T_641) \n node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0))) \n node _T_644 = and(_T_638, _T_643) \n node _T_645 = or(UInt<1>(0h0), _T_587) \n node _T_646 = or(_T_645, _T_627) \n node _T_647 = or(_T_646, _T_634) \n node _T_648 = or(_T_647, _T_644) \n node _T_649 = and(_T_577, _T_648) \n node _T_650 = asUInt(reset) \n node _T_651 = eq(_T_650, UInt<1>(0h0)) \n when _T_651 : \n node _T_652 = eq(_T_649, UInt<1>(0h0)) \n when _T_652 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_649, UInt<1>(0h1), \"\") : assert_26 \n node _T_653 = asUInt(reset) \n node _T_654 = eq(_T_653, UInt<1>(0h0)) \n when _T_654 : \n node _T_655 = eq(source_ok, UInt<1>(0h0)) \n when _T_655 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_27 \n node _T_656 = asUInt(reset) \n node _T_657 = eq(_T_656, UInt<1>(0h0)) \n when _T_657 : \n node _T_658 = eq(is_aligned, UInt<1>(0h0)) \n when _T_658 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_659 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_660 = asUInt(reset) \n node _T_661 = eq(_T_660, UInt<1>(0h0)) \n when _T_661 : \n node _T_662 = eq(_T_659, UInt<1>(0h0)) \n when _T_662 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_659, UInt<1>(0h1), \"\") : assert_29 \n node _T_663 = eq(io.in.a.bits.mask, mask) \n node _T_664 = asUInt(reset) \n node _T_665 = eq(_T_664, UInt<1>(0h0)) \n when _T_665 : \n node _T_666 = eq(_T_663, UInt<1>(0h0)) \n when _T_666 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_663, UInt<1>(0h1), \"\") : assert_30 \n node _T_667 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_667 : \n node _T_668 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_669 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_670 = and(_T_668, _T_669) \n node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) \n node _T_671 = shr(io.in.a.bits.source, 2) \n node _T_672 = eq(_T_671, UInt<1>(0h0)) \n node _T_673 = leq(UInt<1>(0h0), uncommonBits_20) \n node _T_674 = and(_T_672, _T_673) \n node _T_675 = leq(uncommonBits_20, UInt<2>(0h3)) \n node _T_676 = and(_T_674, _T_675) \n node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) \n node _T_677 = shr(io.in.a.bits.source, 2) \n node _T_678 = eq(_T_677, UInt<1>(0h1)) \n node _T_679 = leq(UInt<1>(0h0), uncommonBits_21) \n node _T_680 = and(_T_678, _T_679) \n node _T_681 = leq(uncommonBits_21, UInt<2>(0h3)) \n node _T_682 = and(_T_680, _T_681) \n node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) \n node _T_683 = shr(io.in.a.bits.source, 2) \n node _T_684 = eq(_T_683, UInt<2>(0h2)) \n node _T_685 = leq(UInt<1>(0h0), uncommonBits_22) \n node _T_686 = and(_T_684, _T_685) \n node _T_687 = leq(uncommonBits_22, UInt<2>(0h3)) \n node _T_688 = and(_T_686, _T_687) \n node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) \n node _T_689 = shr(io.in.a.bits.source, 2) \n node _T_690 = eq(_T_689, UInt<2>(0h3)) \n node _T_691 = leq(UInt<1>(0h0), uncommonBits_23) \n node _T_692 = and(_T_690, _T_691) \n node _T_693 = leq(uncommonBits_23, UInt<2>(0h3)) \n node _T_694 = and(_T_692, _T_693) \n node _T_695 = or(_T_676, _T_682) \n node _T_696 = or(_T_695, _T_688) \n node _T_697 = or(_T_696, _T_694) \n node _T_698 = and(_T_670, _T_697) \n node _T_699 = or(UInt<1>(0h0), _T_698) \n node _T_700 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_701 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_702 = and(_T_700, _T_701) \n node _T_703 = or(UInt<1>(0h0), _T_702) \n node _T_704 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_705 = cvt(_T_704) \n node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000))) \n node _T_707 = asSInt(_T_706) \n node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0))) \n node _T_709 = and(_T_703, _T_708) \n node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_711 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_712 = and(_T_710, _T_711) \n node _T_713 = or(UInt<1>(0h0), _T_712) \n node _T_714 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_715 = cvt(_T_714) \n node _T_716 = and(_T_715, asSInt(UInt<14>(0h2000))) \n node _T_717 = asSInt(_T_716) \n node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0))) \n node _T_719 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_720 = cvt(_T_719) \n node _T_721 = and(_T_720, asSInt(UInt<18>(0h2f000))) \n node _T_722 = asSInt(_T_721) \n node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) \n node _T_724 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_725 = cvt(_T_724) \n node _T_726 = and(_T_725, asSInt(UInt<17>(0h10000))) \n node _T_727 = asSInt(_T_726) \n node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0))) \n node _T_729 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_730 = cvt(_T_729) \n node _T_731 = and(_T_730, asSInt(UInt<27>(0h4000000))) \n node _T_732 = asSInt(_T_731) \n node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0))) \n node _T_734 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_735 = cvt(_T_734) \n node _T_736 = and(_T_735, asSInt(UInt<13>(0h1000))) \n node _T_737 = asSInt(_T_736) \n node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0))) \n node _T_739 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_740 = cvt(_T_739) \n node _T_741 = and(_T_740, asSInt(UInt<15>(0h4000))) \n node _T_742 = asSInt(_T_741) \n node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0))) \n node _T_744 = or(_T_718, _T_723) \n node _T_745 = or(_T_744, _T_728) \n node _T_746 = or(_T_745, _T_733) \n node _T_747 = or(_T_746, _T_738) \n node _T_748 = or(_T_747, _T_743) \n node _T_749 = and(_T_713, _T_748) \n node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_752 = cvt(_T_751) \n node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000))) \n node _T_754 = asSInt(_T_753) \n node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) \n node _T_756 = and(_T_750, _T_755) \n node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_758 = leq(io.in.a.bits.size, UInt<4>(0h8)) \n node _T_759 = and(_T_757, _T_758) \n node _T_760 = or(UInt<1>(0h0), _T_759) \n node _T_761 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_762 = cvt(_T_761) \n node _T_763 = and(_T_762, asSInt(UInt<30>(0h20000000))) \n node _T_764 = asSInt(_T_763) \n node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) \n node _T_766 = and(_T_760, _T_765) \n node _T_767 = or(UInt<1>(0h0), _T_709) \n node _T_768 = or(_T_767, _T_749) \n node _T_769 = or(_T_768, _T_756) \n node _T_770 = or(_T_769, _T_766) \n node _T_771 = and(_T_699, _T_770) \n node _T_772 = asUInt(reset) \n node _T_773 = eq(_T_772, UInt<1>(0h0)) \n when _T_773 : \n node _T_774 = eq(_T_771, UInt<1>(0h0)) \n when _T_774 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_771, UInt<1>(0h1), \"\") : assert_31 \n node _T_775 = asUInt(reset) \n node _T_776 = eq(_T_775, UInt<1>(0h0)) \n when _T_776 : \n node _T_777 = eq(source_ok, UInt<1>(0h0)) \n when _T_777 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_32 \n node _T_778 = asUInt(reset) \n node _T_779 = eq(_T_778, UInt<1>(0h0)) \n when _T_779 : \n node _T_780 = eq(is_aligned, UInt<1>(0h0)) \n when _T_780 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_781 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_782 = asUInt(reset) \n node _T_783 = eq(_T_782, UInt<1>(0h0)) \n when _T_783 : \n node _T_784 = eq(_T_781, UInt<1>(0h0)) \n when _T_784 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_781, UInt<1>(0h1), \"\") : assert_34 \n node _T_785 = not(mask) \n node _T_786 = and(io.in.a.bits.mask, _T_785) \n node _T_787 = eq(_T_786, UInt<1>(0h0)) \n node _T_788 = asUInt(reset) \n node _T_789 = eq(_T_788, UInt<1>(0h0)) \n when _T_789 : \n node _T_790 = eq(_T_787, UInt<1>(0h0)) \n when _T_790 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_787, UInt<1>(0h1), \"\") : assert_35 \n node _T_791 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_791 : \n node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_794 = and(_T_792, _T_793) \n node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) \n node _T_795 = shr(io.in.a.bits.source, 2) \n node _T_796 = eq(_T_795, UInt<1>(0h0)) \n node _T_797 = leq(UInt<1>(0h0), uncommonBits_24) \n node _T_798 = and(_T_796, _T_797) \n node _T_799 = leq(uncommonBits_24, UInt<2>(0h3)) \n node _T_800 = and(_T_798, _T_799) \n node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) \n node _T_801 = shr(io.in.a.bits.source, 2) \n node _T_802 = eq(_T_801, UInt<1>(0h1)) \n node _T_803 = leq(UInt<1>(0h0), uncommonBits_25) \n node _T_804 = and(_T_802, _T_803) \n node _T_805 = leq(uncommonBits_25, UInt<2>(0h3)) \n node _T_806 = and(_T_804, _T_805) \n node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) \n node _T_807 = shr(io.in.a.bits.source, 2) \n node _T_808 = eq(_T_807, UInt<2>(0h2)) \n node _T_809 = leq(UInt<1>(0h0), uncommonBits_26) \n node _T_810 = and(_T_808, _T_809) \n node _T_811 = leq(uncommonBits_26, UInt<2>(0h3)) \n node _T_812 = and(_T_810, _T_811) \n node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) \n node _T_813 = shr(io.in.a.bits.source, 2) \n node _T_814 = eq(_T_813, UInt<2>(0h3)) \n node _T_815 = leq(UInt<1>(0h0), uncommonBits_27) \n node _T_816 = and(_T_814, _T_815) \n node _T_817 = leq(uncommonBits_27, UInt<2>(0h3)) \n node _T_818 = and(_T_816, _T_817) \n node _T_819 = or(_T_800, _T_806) \n node _T_820 = or(_T_819, _T_812) \n node _T_821 = or(_T_820, _T_818) \n node _T_822 = and(_T_794, _T_821) \n node _T_823 = or(UInt<1>(0h0), _T_822) \n node _T_824 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_825 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_826 = and(_T_824, _T_825) \n node _T_827 = or(UInt<1>(0h0), _T_826) \n node _T_828 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_829 = cvt(_T_828) \n node _T_830 = and(_T_829, asSInt(UInt<14>(0h2000))) \n node _T_831 = asSInt(_T_830) \n node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) \n node _T_833 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_834 = cvt(_T_833) \n node _T_835 = and(_T_834, asSInt(UInt<13>(0h1000))) \n node _T_836 = asSInt(_T_835) \n node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0))) \n node _T_838 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_839 = cvt(_T_838) \n node _T_840 = and(_T_839, asSInt(UInt<18>(0h2f000))) \n node _T_841 = asSInt(_T_840) \n node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0))) \n node _T_843 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_844 = cvt(_T_843) \n node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000))) \n node _T_846 = asSInt(_T_845) \n node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0))) \n node _T_848 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_849 = cvt(_T_848) \n node _T_850 = and(_T_849, asSInt(UInt<27>(0h4000000))) \n node _T_851 = asSInt(_T_850) \n node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0))) \n node _T_853 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_854 = cvt(_T_853) \n node _T_855 = and(_T_854, asSInt(UInt<13>(0h1000))) \n node _T_856 = asSInt(_T_855) \n node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0))) \n node _T_858 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_859 = cvt(_T_858) \n node _T_860 = and(_T_859, asSInt(UInt<15>(0h4000))) \n node _T_861 = asSInt(_T_860) \n node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0))) \n node _T_863 = or(_T_832, _T_837) \n node _T_864 = or(_T_863, _T_842) \n node _T_865 = or(_T_864, _T_847) \n node _T_866 = or(_T_865, _T_852) \n node _T_867 = or(_T_866, _T_857) \n node _T_868 = or(_T_867, _T_862) \n node _T_869 = and(_T_827, _T_868) \n node _T_870 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_871 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_872 = cvt(_T_871) \n node _T_873 = and(_T_872, asSInt(UInt<17>(0h10000))) \n node _T_874 = asSInt(_T_873) \n node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) \n node _T_876 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_877 = cvt(_T_876) \n node _T_878 = and(_T_877, asSInt(UInt<30>(0h20000000))) \n node _T_879 = asSInt(_T_878) \n node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) \n node _T_881 = or(_T_875, _T_880) \n node _T_882 = and(_T_870, _T_881) \n node _T_883 = or(UInt<1>(0h0), _T_869) \n node _T_884 = or(_T_883, _T_882) \n node _T_885 = and(_T_823, _T_884) \n node _T_886 = asUInt(reset) \n node _T_887 = eq(_T_886, UInt<1>(0h0)) \n when _T_887 : \n node _T_888 = eq(_T_885, UInt<1>(0h0)) \n when _T_888 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_885, UInt<1>(0h1), \"\") : assert_36 \n node _T_889 = asUInt(reset) \n node _T_890 = eq(_T_889, UInt<1>(0h0)) \n when _T_890 : \n node _T_891 = eq(source_ok, UInt<1>(0h0)) \n when _T_891 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_892 = asUInt(reset) \n node _T_893 = eq(_T_892, UInt<1>(0h0)) \n when _T_893 : \n node _T_894 = eq(is_aligned, UInt<1>(0h0)) \n when _T_894 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_895 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_896 = asUInt(reset) \n node _T_897 = eq(_T_896, UInt<1>(0h0)) \n when _T_897 : \n node _T_898 = eq(_T_895, UInt<1>(0h0)) \n when _T_898 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_895, UInt<1>(0h1), \"\") : assert_39 \n node _T_899 = eq(io.in.a.bits.mask, mask) \n node _T_900 = asUInt(reset) \n node _T_901 = eq(_T_900, UInt<1>(0h0)) \n when _T_901 : \n node _T_902 = eq(_T_899, UInt<1>(0h0)) \n when _T_902 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_899, UInt<1>(0h1), \"\") : assert_40 \n node _T_903 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_903 : \n node _T_904 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_905 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_906 = and(_T_904, _T_905) \n node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) \n node _T_907 = shr(io.in.a.bits.source, 2) \n node _T_908 = eq(_T_907, UInt<1>(0h0)) \n node _T_909 = leq(UInt<1>(0h0), uncommonBits_28) \n node _T_910 = and(_T_908, _T_909) \n node _T_911 = leq(uncommonBits_28, UInt<2>(0h3)) \n node _T_912 = and(_T_910, _T_911) \n node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) \n node _T_913 = shr(io.in.a.bits.source, 2) \n node _T_914 = eq(_T_913, UInt<1>(0h1)) \n node _T_915 = leq(UInt<1>(0h0), uncommonBits_29) \n node _T_916 = and(_T_914, _T_915) \n node _T_917 = leq(uncommonBits_29, UInt<2>(0h3)) \n node _T_918 = and(_T_916, _T_917) \n node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) \n node _T_919 = shr(io.in.a.bits.source, 2) \n node _T_920 = eq(_T_919, UInt<2>(0h2)) \n node _T_921 = leq(UInt<1>(0h0), uncommonBits_30) \n node _T_922 = and(_T_920, _T_921) \n node _T_923 = leq(uncommonBits_30, UInt<2>(0h3)) \n node _T_924 = and(_T_922, _T_923) \n node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) \n node _T_925 = shr(io.in.a.bits.source, 2) \n node _T_926 = eq(_T_925, UInt<2>(0h3)) \n node _T_927 = leq(UInt<1>(0h0), uncommonBits_31) \n node _T_928 = and(_T_926, _T_927) \n node _T_929 = leq(uncommonBits_31, UInt<2>(0h3)) \n node _T_930 = and(_T_928, _T_929) \n node _T_931 = or(_T_912, _T_918) \n node _T_932 = or(_T_931, _T_924) \n node _T_933 = or(_T_932, _T_930) \n node _T_934 = and(_T_906, _T_933) \n node _T_935 = or(UInt<1>(0h0), _T_934) \n node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_937 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_938 = and(_T_936, _T_937) \n node _T_939 = or(UInt<1>(0h0), _T_938) \n node _T_940 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_941 = cvt(_T_940) \n node _T_942 = and(_T_941, asSInt(UInt<14>(0h2000))) \n node _T_943 = asSInt(_T_942) \n node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) \n node _T_945 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_946 = cvt(_T_945) \n node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000))) \n node _T_948 = asSInt(_T_947) \n node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) \n node _T_950 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_951 = cvt(_T_950) \n node _T_952 = and(_T_951, asSInt(UInt<18>(0h2f000))) \n node _T_953 = asSInt(_T_952) \n node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0))) \n node _T_955 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_956 = cvt(_T_955) \n node _T_957 = and(_T_956, asSInt(UInt<17>(0h10000))) \n node _T_958 = asSInt(_T_957) \n node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0))) \n node _T_960 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_961 = cvt(_T_960) \n node _T_962 = and(_T_961, asSInt(UInt<27>(0h4000000))) \n node _T_963 = asSInt(_T_962) \n node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0))) \n node _T_965 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_966 = cvt(_T_965) \n node _T_967 = and(_T_966, asSInt(UInt<13>(0h1000))) \n node _T_968 = asSInt(_T_967) \n node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0))) \n node _T_970 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_971 = cvt(_T_970) \n node _T_972 = and(_T_971, asSInt(UInt<15>(0h4000))) \n node _T_973 = asSInt(_T_972) \n node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) \n node _T_975 = or(_T_944, _T_949) \n node _T_976 = or(_T_975, _T_954) \n node _T_977 = or(_T_976, _T_959) \n node _T_978 = or(_T_977, _T_964) \n node _T_979 = or(_T_978, _T_969) \n node _T_980 = or(_T_979, _T_974) \n node _T_981 = and(_T_939, _T_980) \n node _T_982 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_983 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_984 = cvt(_T_983) \n node _T_985 = and(_T_984, asSInt(UInt<17>(0h10000))) \n node _T_986 = asSInt(_T_985) \n node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) \n node _T_988 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_989 = cvt(_T_988) \n node _T_990 = and(_T_989, asSInt(UInt<30>(0h20000000))) \n node _T_991 = asSInt(_T_990) \n node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0))) \n node _T_993 = or(_T_987, _T_992) \n node _T_994 = and(_T_982, _T_993) \n node _T_995 = or(UInt<1>(0h0), _T_981) \n node _T_996 = or(_T_995, _T_994) \n node _T_997 = and(_T_935, _T_996) \n node _T_998 = asUInt(reset) \n node _T_999 = eq(_T_998, UInt<1>(0h0)) \n when _T_999 : \n node _T_1000 = eq(_T_997, UInt<1>(0h0)) \n when _T_1000 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_997, UInt<1>(0h1), \"\") : assert_41 \n node _T_1001 = asUInt(reset) \n node _T_1002 = eq(_T_1001, UInt<1>(0h0)) \n when _T_1002 : \n node _T_1003 = eq(source_ok, UInt<1>(0h0)) \n when _T_1003 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_1004 = asUInt(reset) \n node _T_1005 = eq(_T_1004, UInt<1>(0h0)) \n when _T_1005 : \n node _T_1006 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1006 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_1007 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_1008 = asUInt(reset) \n node _T_1009 = eq(_T_1008, UInt<1>(0h0)) \n when _T_1009 : \n node _T_1010 = eq(_T_1007, UInt<1>(0h0)) \n when _T_1010 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_1007, UInt<1>(0h1), \"\") : assert_44 \n node _T_1011 = eq(io.in.a.bits.mask, mask) \n node _T_1012 = asUInt(reset) \n node _T_1013 = eq(_T_1012, UInt<1>(0h0)) \n when _T_1013 : \n node _T_1014 = eq(_T_1011, UInt<1>(0h0)) \n when _T_1014 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_1011, UInt<1>(0h1), \"\") : assert_45 \n node _T_1015 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_1015 : \n node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1017 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1018 = and(_T_1016, _T_1017) \n node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) \n node _T_1019 = shr(io.in.a.bits.source, 2) \n node _T_1020 = eq(_T_1019, UInt<1>(0h0)) \n node _T_1021 = leq(UInt<1>(0h0), uncommonBits_32) \n node _T_1022 = and(_T_1020, _T_1021) \n node _T_1023 = leq(uncommonBits_32, UInt<2>(0h3)) \n node _T_1024 = and(_T_1022, _T_1023) \n node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) \n node _T_1025 = shr(io.in.a.bits.source, 2) \n node _T_1026 = eq(_T_1025, UInt<1>(0h1)) \n node _T_1027 = leq(UInt<1>(0h0), uncommonBits_33) \n node _T_1028 = and(_T_1026, _T_1027) \n node _T_1029 = leq(uncommonBits_33, UInt<2>(0h3)) \n node _T_1030 = and(_T_1028, _T_1029) \n node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) \n node _T_1031 = shr(io.in.a.bits.source, 2) \n node _T_1032 = eq(_T_1031, UInt<2>(0h2)) \n node _T_1033 = leq(UInt<1>(0h0), uncommonBits_34) \n node _T_1034 = and(_T_1032, _T_1033) \n node _T_1035 = leq(uncommonBits_34, UInt<2>(0h3)) \n node _T_1036 = and(_T_1034, _T_1035) \n node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) \n node _T_1037 = shr(io.in.a.bits.source, 2) \n node _T_1038 = eq(_T_1037, UInt<2>(0h3)) \n node _T_1039 = leq(UInt<1>(0h0), uncommonBits_35) \n node _T_1040 = and(_T_1038, _T_1039) \n node _T_1041 = leq(uncommonBits_35, UInt<2>(0h3)) \n node _T_1042 = and(_T_1040, _T_1041) \n node _T_1043 = or(_T_1024, _T_1030) \n node _T_1044 = or(_T_1043, _T_1036) \n node _T_1045 = or(_T_1044, _T_1042) \n node _T_1046 = and(_T_1018, _T_1045) \n node _T_1047 = or(UInt<1>(0h0), _T_1046) \n node _T_1048 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1049 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_1050 = and(_T_1048, _T_1049) \n node _T_1051 = or(UInt<1>(0h0), _T_1050) \n node _T_1052 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_1053 = cvt(_T_1052) \n node _T_1054 = and(_T_1053, asSInt(UInt<13>(0h1000))) \n node _T_1055 = asSInt(_T_1054) \n node _T_1056 = eq(_T_1055, asSInt(UInt<1>(0h0))) \n node _T_1057 = and(_T_1051, _T_1056) \n node _T_1058 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1059 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_1060 = cvt(_T_1059) \n node _T_1061 = and(_T_1060, asSInt(UInt<14>(0h2000))) \n node _T_1062 = asSInt(_T_1061) \n node _T_1063 = eq(_T_1062, asSInt(UInt<1>(0h0))) \n node _T_1064 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_1065 = cvt(_T_1064) \n node _T_1066 = and(_T_1065, asSInt(UInt<17>(0h10000))) \n node _T_1067 = asSInt(_T_1066) \n node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0))) \n node _T_1069 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_1070 = cvt(_T_1069) \n node _T_1071 = and(_T_1070, asSInt(UInt<18>(0h2f000))) \n node _T_1072 = asSInt(_T_1071) \n node _T_1073 = eq(_T_1072, asSInt(UInt<1>(0h0))) \n node _T_1074 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_1075 = cvt(_T_1074) \n node _T_1076 = and(_T_1075, asSInt(UInt<17>(0h10000))) \n node _T_1077 = asSInt(_T_1076) \n node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0))) \n node _T_1079 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1080 = cvt(_T_1079) \n node _T_1081 = and(_T_1080, asSInt(UInt<27>(0h4000000))) \n node _T_1082 = asSInt(_T_1081) \n node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0))) \n node _T_1084 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1085 = cvt(_T_1084) \n node _T_1086 = and(_T_1085, asSInt(UInt<13>(0h1000))) \n node _T_1087 = asSInt(_T_1086) \n node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0))) \n node _T_1089 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) \n node _T_1090 = cvt(_T_1089) \n node _T_1091 = and(_T_1090, asSInt(UInt<30>(0h20000000))) \n node _T_1092 = asSInt(_T_1091) \n node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0))) \n node _T_1094 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_1095 = cvt(_T_1094) \n node _T_1096 = and(_T_1095, asSInt(UInt<15>(0h4000))) \n node _T_1097 = asSInt(_T_1096) \n node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0))) \n node _T_1099 = or(_T_1063, _T_1068) \n node _T_1100 = or(_T_1099, _T_1073) \n node _T_1101 = or(_T_1100, _T_1078) \n node _T_1102 = or(_T_1101, _T_1083) \n node _T_1103 = or(_T_1102, _T_1088) \n node _T_1104 = or(_T_1103, _T_1093) \n node _T_1105 = or(_T_1104, _T_1098) \n node _T_1106 = and(_T_1058, _T_1105) \n node _T_1107 = or(UInt<1>(0h0), _T_1057) \n node _T_1108 = or(_T_1107, _T_1106) \n node _T_1109 = and(_T_1047, _T_1108) \n node _T_1110 = asUInt(reset) \n node _T_1111 = eq(_T_1110, UInt<1>(0h0)) \n when _T_1111 : \n node _T_1112 = eq(_T_1109, UInt<1>(0h0)) \n when _T_1112 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_1109, UInt<1>(0h1), \"\") : assert_46 \n node _T_1113 = asUInt(reset) \n node _T_1114 = eq(_T_1113, UInt<1>(0h0)) \n when _T_1114 : \n node _T_1115 = eq(source_ok, UInt<1>(0h0)) \n when _T_1115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_1116 = asUInt(reset) \n node _T_1117 = eq(_T_1116, UInt<1>(0h0)) \n when _T_1117 : \n node _T_1118 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1118 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_1119 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_1120 = asUInt(reset) \n node _T_1121 = eq(_T_1120, UInt<1>(0h0)) \n when _T_1121 : \n node _T_1122 = eq(_T_1119, UInt<1>(0h0)) \n when _T_1122 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_1119, UInt<1>(0h1), \"\") : assert_49 \n node _T_1123 = eq(io.in.a.bits.mask, mask) \n node _T_1124 = asUInt(reset) \n node _T_1125 = eq(_T_1124, UInt<1>(0h0)) \n when _T_1125 : \n node _T_1126 = eq(_T_1123, UInt<1>(0h0)) \n when _T_1126 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_1123, UInt<1>(0h1), \"\") : assert_50 \n node _T_1127 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_1128 = asUInt(reset) \n node _T_1129 = eq(_T_1128, UInt<1>(0h0)) \n when _T_1129 : \n node _T_1130 = eq(_T_1127, UInt<1>(0h0)) \n when _T_1130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_1127, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_1131 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1132 = asUInt(reset) \n node _T_1133 = eq(_T_1132, UInt<1>(0h0)) \n when _T_1133 : \n node _T_1134 = eq(_T_1131, UInt<1>(0h0)) \n when _T_1134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_1131, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) \n node _source_ok_T_26 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) \n node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) \n node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) \n node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) \n node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) \n node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) \n node _source_ok_T_32 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) \n node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) \n node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) \n node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) \n node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) \n node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) \n node _source_ok_T_38 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) \n node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) \n node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) \n node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) \n node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) \n node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) \n node _source_ok_T_44 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) \n node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) \n node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) \n node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) \n node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) \n wire _source_ok_WIRE_1 : UInt<1>[4] \n connect _source_ok_WIRE_1[0], _source_ok_T_31 \n connect _source_ok_WIRE_1[1], _source_ok_T_37 \n connect _source_ok_WIRE_1[2], _source_ok_T_43 \n connect _source_ok_WIRE_1[3], _source_ok_T_49 \n node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) \n node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_1135 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_1135 : \n node _T_1136 = asUInt(reset) \n node _T_1137 = eq(_T_1136, UInt<1>(0h0)) \n when _T_1137 : \n node _T_1138 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1138 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_1139 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1140 = asUInt(reset) \n node _T_1141 = eq(_T_1140, UInt<1>(0h0)) \n when _T_1141 : \n node _T_1142 = eq(_T_1139, UInt<1>(0h0)) \n when _T_1142 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_1139, UInt<1>(0h1), \"\") : assert_54 \n node _T_1143 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1144 = asUInt(reset) \n node _T_1145 = eq(_T_1144, UInt<1>(0h0)) \n when _T_1145 : \n node _T_1146 = eq(_T_1143, UInt<1>(0h0)) \n when _T_1146 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_1143, UInt<1>(0h1), \"\") : assert_55 \n node _T_1147 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1148 = asUInt(reset) \n node _T_1149 = eq(_T_1148, UInt<1>(0h0)) \n when _T_1149 : \n node _T_1150 = eq(_T_1147, UInt<1>(0h0)) \n when _T_1150 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_1147, UInt<1>(0h1), \"\") : assert_56 \n node _T_1151 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1152 = asUInt(reset) \n node _T_1153 = eq(_T_1152, UInt<1>(0h0)) \n when _T_1153 : \n node _T_1154 = eq(_T_1151, UInt<1>(0h0)) \n when _T_1154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_1151, UInt<1>(0h1), \"\") : assert_57 \n node _T_1155 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_1155 : \n node _T_1156 = asUInt(reset) \n node _T_1157 = eq(_T_1156, UInt<1>(0h0)) \n when _T_1157 : \n node _T_1158 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1158 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_1159 = asUInt(reset) \n node _T_1160 = eq(_T_1159, UInt<1>(0h0)) \n when _T_1160 : \n node _T_1161 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1161 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_1162 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1163 = asUInt(reset) \n node _T_1164 = eq(_T_1163, UInt<1>(0h0)) \n when _T_1164 : \n node _T_1165 = eq(_T_1162, UInt<1>(0h0)) \n when _T_1165 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_1162, UInt<1>(0h1), \"\") : assert_60 \n node _T_1166 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1167 = asUInt(reset) \n node _T_1168 = eq(_T_1167, UInt<1>(0h0)) \n when _T_1168 : \n node _T_1169 = eq(_T_1166, UInt<1>(0h0)) \n when _T_1169 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_1166, UInt<1>(0h1), \"\") : assert_61 \n node _T_1170 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1171 = asUInt(reset) \n node _T_1172 = eq(_T_1171, UInt<1>(0h0)) \n when _T_1172 : \n node _T_1173 = eq(_T_1170, UInt<1>(0h0)) \n when _T_1173 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_1170, UInt<1>(0h1), \"\") : assert_62 \n node _T_1174 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1175 = asUInt(reset) \n node _T_1176 = eq(_T_1175, UInt<1>(0h0)) \n when _T_1176 : \n node _T_1177 = eq(_T_1174, UInt<1>(0h0)) \n when _T_1177 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_1174, UInt<1>(0h1), \"\") : assert_63 \n node _T_1178 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1179 = or(UInt<1>(0h1), _T_1178) \n node _T_1180 = asUInt(reset) \n node _T_1181 = eq(_T_1180, UInt<1>(0h0)) \n when _T_1181 : \n node _T_1182 = eq(_T_1179, UInt<1>(0h0)) \n when _T_1182 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_1179, UInt<1>(0h1), \"\") : assert_64 \n node _T_1183 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_1183 : \n node _T_1184 = asUInt(reset) \n node _T_1185 = eq(_T_1184, UInt<1>(0h0)) \n when _T_1185 : \n node _T_1186 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_1187 = asUInt(reset) \n node _T_1188 = eq(_T_1187, UInt<1>(0h0)) \n when _T_1188 : \n node _T_1189 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1189 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_1190 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1191 = asUInt(reset) \n node _T_1192 = eq(_T_1191, UInt<1>(0h0)) \n when _T_1192 : \n node _T_1193 = eq(_T_1190, UInt<1>(0h0)) \n when _T_1193 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_1190, UInt<1>(0h1), \"\") : assert_67 \n node _T_1194 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1195 = asUInt(reset) \n node _T_1196 = eq(_T_1195, UInt<1>(0h0)) \n when _T_1196 : \n node _T_1197 = eq(_T_1194, UInt<1>(0h0)) \n when _T_1197 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_1194, UInt<1>(0h1), \"\") : assert_68 \n node _T_1198 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1199 = asUInt(reset) \n node _T_1200 = eq(_T_1199, UInt<1>(0h0)) \n when _T_1200 : \n node _T_1201 = eq(_T_1198, UInt<1>(0h0)) \n when _T_1201 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_1198, UInt<1>(0h1), \"\") : assert_69 \n node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1203 = or(_T_1202, io.in.d.bits.corrupt) \n node _T_1204 = asUInt(reset) \n node _T_1205 = eq(_T_1204, UInt<1>(0h0)) \n when _T_1205 : \n node _T_1206 = eq(_T_1203, UInt<1>(0h0)) \n when _T_1206 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_1203, UInt<1>(0h1), \"\") : assert_70 \n node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1208 = or(UInt<1>(0h1), _T_1207) \n node _T_1209 = asUInt(reset) \n node _T_1210 = eq(_T_1209, UInt<1>(0h0)) \n when _T_1210 : \n node _T_1211 = eq(_T_1208, UInt<1>(0h0)) \n when _T_1211 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_1208, UInt<1>(0h1), \"\") : assert_71 \n node _T_1212 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_1212 : \n node _T_1213 = asUInt(reset) \n node _T_1214 = eq(_T_1213, UInt<1>(0h0)) \n when _T_1214 : \n node _T_1215 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1215 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_1216 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1217 = asUInt(reset) \n node _T_1218 = eq(_T_1217, UInt<1>(0h0)) \n when _T_1218 : \n node _T_1219 = eq(_T_1216, UInt<1>(0h0)) \n when _T_1219 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_1216, UInt<1>(0h1), \"\") : assert_73 \n node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1221 = asUInt(reset) \n node _T_1222 = eq(_T_1221, UInt<1>(0h0)) \n when _T_1222 : \n node _T_1223 = eq(_T_1220, UInt<1>(0h0)) \n when _T_1223 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_1220, UInt<1>(0h1), \"\") : assert_74 \n node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1225 = or(UInt<1>(0h1), _T_1224) \n node _T_1226 = asUInt(reset) \n node _T_1227 = eq(_T_1226, UInt<1>(0h0)) \n when _T_1227 : \n node _T_1228 = eq(_T_1225, UInt<1>(0h0)) \n when _T_1228 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_1225, UInt<1>(0h1), \"\") : assert_75 \n node _T_1229 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_1229 : \n node _T_1230 = asUInt(reset) \n node _T_1231 = eq(_T_1230, UInt<1>(0h0)) \n when _T_1231 : \n node _T_1232 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1232 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_1233 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1234 = asUInt(reset) \n node _T_1235 = eq(_T_1234, UInt<1>(0h0)) \n when _T_1235 : \n node _T_1236 = eq(_T_1233, UInt<1>(0h0)) \n when _T_1236 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_1233, UInt<1>(0h1), \"\") : assert_77 \n node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1238 = or(_T_1237, io.in.d.bits.corrupt) \n node _T_1239 = asUInt(reset) \n node _T_1240 = eq(_T_1239, UInt<1>(0h0)) \n when _T_1240 : \n node _T_1241 = eq(_T_1238, UInt<1>(0h0)) \n when _T_1241 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_1238, UInt<1>(0h1), \"\") : assert_78 \n node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1243 = or(UInt<1>(0h1), _T_1242) \n node _T_1244 = asUInt(reset) \n node _T_1245 = eq(_T_1244, UInt<1>(0h0)) \n when _T_1245 : \n node _T_1246 = eq(_T_1243, UInt<1>(0h0)) \n when _T_1246 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_1243, UInt<1>(0h1), \"\") : assert_79 \n node _T_1247 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_1247 : \n node _T_1248 = asUInt(reset) \n node _T_1249 = eq(_T_1248, UInt<1>(0h0)) \n when _T_1249 : \n node _T_1250 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1250 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_1251 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1252 = asUInt(reset) \n node _T_1253 = eq(_T_1252, UInt<1>(0h0)) \n when _T_1253 : \n node _T_1254 = eq(_T_1251, UInt<1>(0h0)) \n when _T_1254 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_1251, UInt<1>(0h1), \"\") : assert_81 \n node _T_1255 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1256 = asUInt(reset) \n node _T_1257 = eq(_T_1256, UInt<1>(0h0)) \n when _T_1257 : \n node _T_1258 = eq(_T_1255, UInt<1>(0h0)) \n when _T_1258 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_1255, UInt<1>(0h1), \"\") : assert_82 \n node _T_1259 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1260 = or(UInt<1>(0h1), _T_1259) \n node _T_1261 = asUInt(reset) \n node _T_1262 = eq(_T_1261, UInt<1>(0h0)) \n when _T_1262 : \n node _T_1263 = eq(_T_1260, UInt<1>(0h0)) \n when _T_1263 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_1260, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<4>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_1264 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_1265 = asUInt(reset) \n node _T_1266 = eq(_T_1265, UInt<1>(0h0)) \n when _T_1266 : \n node _T_1267 = eq(_T_1264, UInt<1>(0h0)) \n when _T_1267 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_1264, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<4>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_1268 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_1269 = asUInt(reset) \n node _T_1270 = eq(_T_1269, UInt<1>(0h0)) \n when _T_1270 : \n node _T_1271 = eq(_T_1268, UInt<1>(0h0)) \n when _T_1271 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_1268, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_1272 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_1273 = asUInt(reset) \n node _T_1274 = eq(_T_1273, UInt<1>(0h0)) \n when _T_1274 : \n node _T_1275 = eq(_T_1272, UInt<1>(0h0)) \n when _T_1275 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_1272, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_1276 = eq(a_first, UInt<1>(0h0)) \n node _T_1277 = and(io.in.a.valid, _T_1276) \n when _T_1277 : \n node _T_1278 = eq(io.in.a.bits.opcode, opcode) \n node _T_1279 = asUInt(reset) \n node _T_1280 = eq(_T_1279, UInt<1>(0h0)) \n when _T_1280 : \n node _T_1281 = eq(_T_1278, UInt<1>(0h0)) \n when _T_1281 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_1278, UInt<1>(0h1), \"\") : assert_87 \n node _T_1282 = eq(io.in.a.bits.param, param) \n node _T_1283 = asUInt(reset) \n node _T_1284 = eq(_T_1283, UInt<1>(0h0)) \n when _T_1284 : \n node _T_1285 = eq(_T_1282, UInt<1>(0h0)) \n when _T_1285 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_1282, UInt<1>(0h1), \"\") : assert_88 \n node _T_1286 = eq(io.in.a.bits.size, size) \n node _T_1287 = asUInt(reset) \n node _T_1288 = eq(_T_1287, UInt<1>(0h0)) \n when _T_1288 : \n node _T_1289 = eq(_T_1286, UInt<1>(0h0)) \n when _T_1289 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_1286, UInt<1>(0h1), \"\") : assert_89 \n node _T_1290 = eq(io.in.a.bits.source, source) \n node _T_1291 = asUInt(reset) \n node _T_1292 = eq(_T_1291, UInt<1>(0h0)) \n when _T_1292 : \n node _T_1293 = eq(_T_1290, UInt<1>(0h0)) \n when _T_1293 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1290, UInt<1>(0h1), \"\") : assert_90 \n node _T_1294 = eq(io.in.a.bits.address, address) \n node _T_1295 = asUInt(reset) \n node _T_1296 = eq(_T_1295, UInt<1>(0h0)) \n when _T_1296 : \n node _T_1297 = eq(_T_1294, UInt<1>(0h0)) \n when _T_1297 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1294, UInt<1>(0h1), \"\") : assert_91 \n node _T_1298 = and(io.in.a.ready, io.in.a.valid) \n node _T_1299 = and(_T_1298, a_first) \n when _T_1299 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_1300 = eq(d_first, UInt<1>(0h0)) \n node _T_1301 = and(io.in.d.valid, _T_1300) \n when _T_1301 : \n node _T_1302 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_1303 = asUInt(reset) \n node _T_1304 = eq(_T_1303, UInt<1>(0h0)) \n when _T_1304 : \n node _T_1305 = eq(_T_1302, UInt<1>(0h0)) \n when _T_1305 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1302, UInt<1>(0h1), \"\") : assert_92 \n node _T_1306 = eq(io.in.d.bits.param, param_1) \n node _T_1307 = asUInt(reset) \n node _T_1308 = eq(_T_1307, UInt<1>(0h0)) \n when _T_1308 : \n node _T_1309 = eq(_T_1306, UInt<1>(0h0)) \n when _T_1309 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1306, UInt<1>(0h1), \"\") : assert_93 \n node _T_1310 = eq(io.in.d.bits.size, size_1) \n node _T_1311 = asUInt(reset) \n node _T_1312 = eq(_T_1311, UInt<1>(0h0)) \n when _T_1312 : \n node _T_1313 = eq(_T_1310, UInt<1>(0h0)) \n when _T_1313 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_1310, UInt<1>(0h1), \"\") : assert_94 \n node _T_1314 = eq(io.in.d.bits.source, source_1) \n node _T_1315 = asUInt(reset) \n node _T_1316 = eq(_T_1315, UInt<1>(0h0)) \n when _T_1316 : \n node _T_1317 = eq(_T_1314, UInt<1>(0h0)) \n when _T_1317 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_1314, UInt<1>(0h1), \"\") : assert_95 \n node _T_1318 = eq(io.in.d.bits.sink, sink) \n node _T_1319 = asUInt(reset) \n node _T_1320 = eq(_T_1319, UInt<1>(0h0)) \n when _T_1320 : \n node _T_1321 = eq(_T_1318, UInt<1>(0h0)) \n when _T_1321 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_1318, UInt<1>(0h1), \"\") : assert_96 \n node _T_1322 = eq(io.in.d.bits.denied, denied) \n node _T_1323 = asUInt(reset) \n node _T_1324 = eq(_T_1323, UInt<1>(0h0)) \n when _T_1324 : \n node _T_1325 = eq(_T_1322, UInt<1>(0h0)) \n when _T_1325 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1322, UInt<1>(0h1), \"\") : assert_97 \n node _T_1326 = and(io.in.d.ready, io.in.d.valid) \n node _T_1327 = and(_T_1326, d_first) \n when _T_1327 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) \n regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<16> \n connect a_set, UInt<16>(0h0) \n wire a_set_wo_ready : UInt<16> \n connect a_set_wo_ready, UInt<16>(0h0) \n wire a_opcodes_set : UInt<64> \n connect a_opcodes_set, UInt<64>(0h0) \n wire a_sizes_set : UInt<128> \n connect a_sizes_set, UInt<128>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<8> \n connect a_size_lookup, UInt<8>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<5> \n connect a_sizes_set_interm, UInt<5>(0h0) \n node _T_1328 = and(io.in.a.valid, a_first_1) \n node _T_1329 = and(_T_1328, UInt<1>(0h1)) \n when _T_1329 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_1330 = and(io.in.a.ready, io.in.a.valid) \n node _T_1331 = and(_T_1330, a_first_1) \n node _T_1332 = and(_T_1331, UInt<1>(0h1)) \n when _T_1332 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_1333 = dshr(inflight, io.in.a.bits.source) \n node _T_1334 = bits(_T_1333, 0, 0) \n node _T_1335 = eq(_T_1334, UInt<1>(0h0)) \n node _T_1336 = asUInt(reset) \n node _T_1337 = eq(_T_1336, UInt<1>(0h0)) \n when _T_1337 : \n node _T_1338 = eq(_T_1335, UInt<1>(0h0)) \n when _T_1338 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1335, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<16> \n connect d_clr, UInt<16>(0h0) \n wire d_clr_wo_ready : UInt<16> \n connect d_clr_wo_ready, UInt<16>(0h0) \n wire d_opcodes_clr : UInt<64> \n connect d_opcodes_clr, UInt<64>(0h0) \n wire d_sizes_clr : UInt<128> \n connect d_sizes_clr, UInt<128>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1339 = and(io.in.d.valid, d_first_1) \n node _T_1340 = and(_T_1339, UInt<1>(0h1)) \n node _T_1341 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1342 = and(_T_1340, _T_1341) \n when _T_1342 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_1343 = and(io.in.d.ready, io.in.d.valid) \n node _T_1344 = and(_T_1343, d_first_1) \n node _T_1345 = and(_T_1344, UInt<1>(0h1)) \n node _T_1346 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1347 = and(_T_1345, _T_1346) \n when _T_1347 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_1348 = and(io.in.d.valid, d_first_1) \n node _T_1349 = and(_T_1348, UInt<1>(0h1)) \n node _T_1350 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1351 = and(_T_1349, _T_1350) \n when _T_1351 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_1352 = dshr(inflight, io.in.d.bits.source) \n node _T_1353 = bits(_T_1352, 0, 0) \n node _T_1354 = or(_T_1353, same_cycle_resp) \n node _T_1355 = asUInt(reset) \n node _T_1356 = eq(_T_1355, UInt<1>(0h0)) \n when _T_1356 : \n node _T_1357 = eq(_T_1354, UInt<1>(0h0)) \n when _T_1357 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1354, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_1358 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_1359 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_1360 = or(_T_1358, _T_1359) \n node _T_1361 = asUInt(reset) \n node _T_1362 = eq(_T_1361, UInt<1>(0h0)) \n when _T_1362 : \n node _T_1363 = eq(_T_1360, UInt<1>(0h0)) \n when _T_1363 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1360, UInt<1>(0h1), \"\") : assert_100 \n node _T_1364 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_1365 = asUInt(reset) \n node _T_1366 = eq(_T_1365, UInt<1>(0h0)) \n when _T_1366 : \n node _T_1367 = eq(_T_1364, UInt<1>(0h0)) \n when _T_1367 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_1364, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_1368 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_1369 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_1370 = or(_T_1368, _T_1369) \n node _T_1371 = asUInt(reset) \n node _T_1372 = eq(_T_1371, UInt<1>(0h0)) \n when _T_1372 : \n node _T_1373 = eq(_T_1370, UInt<1>(0h0)) \n when _T_1373 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_1370, UInt<1>(0h1), \"\") : assert_102 \n node _T_1374 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_1375 = asUInt(reset) \n node _T_1376 = eq(_T_1375, UInt<1>(0h0)) \n when _T_1376 : \n node _T_1377 = eq(_T_1374, UInt<1>(0h0)) \n when _T_1377 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_1374, UInt<1>(0h1), \"\") : assert_103 \n node _T_1378 = and(io.in.d.valid, d_first_1) \n node _T_1379 = and(_T_1378, a_first_1) \n node _T_1380 = and(_T_1379, io.in.a.valid) \n node _T_1381 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_1382 = and(_T_1380, _T_1381) \n node _T_1383 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_1384 = and(_T_1382, _T_1383) \n when _T_1384 : \n node _T_1385 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_1386 = or(_T_1385, io.in.a.ready) \n node _T_1387 = asUInt(reset) \n node _T_1388 = eq(_T_1387, UInt<1>(0h0)) \n when _T_1388 : \n node _T_1389 = eq(_T_1386, UInt<1>(0h0)) \n when _T_1389 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1386, UInt<1>(0h1), \"\") : assert_104 \n node _T_1390 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_1391 = orr(a_set_wo_ready) \n node _T_1392 = eq(_T_1391, UInt<1>(0h0)) \n node _T_1393 = or(_T_1390, _T_1392) \n node _T_1394 = asUInt(reset) \n node _T_1395 = eq(_T_1394, UInt<1>(0h0)) \n when _T_1395 : \n node _T_1396 = eq(_T_1393, UInt<1>(0h0)) \n when _T_1396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1393, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_40 \n node _T_1397 = orr(inflight) \n node _T_1398 = eq(_T_1397, UInt<1>(0h0)) \n node _T_1399 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_1400 = or(_T_1398, _T_1399) \n node _T_1401 = lt(watchdog, plusarg_reader.out) \n node _T_1402 = or(_T_1400, _T_1401) \n node _T_1403 = asUInt(reset) \n node _T_1404 = eq(_T_1403, UInt<1>(0h0)) \n when _T_1404 : \n node _T_1405 = eq(_T_1402, UInt<1>(0h0)) \n when _T_1405 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1402, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_1406 = and(io.in.a.ready, io.in.a.valid) \n node _T_1407 = and(io.in.d.ready, io.in.d.valid) \n node _T_1408 = or(_T_1406, _T_1407) \n when _T_1408 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) \n regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<16> \n connect c_set, UInt<16>(0h0) \n wire c_set_wo_ready : UInt<16> \n connect c_set_wo_ready, UInt<16>(0h0) \n wire c_opcodes_set : UInt<64> \n connect c_opcodes_set, UInt<64>(0h0) \n wire c_sizes_set : UInt<128> \n connect c_sizes_set, UInt<128>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<8> \n connect c_size_lookup, UInt<8>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<5> \n connect c_sizes_set_interm, UInt<5>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<4>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_1409 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<4>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_1410 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_1411 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_1412 = and(_T_1410, _T_1411) \n node _T_1413 = and(_T_1409, _T_1412) \n when _T_1413 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<4>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_1414 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_1415 = and(_T_1414, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<4>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_1416 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_1417 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_1418 = and(_T_1416, _T_1417) \n node _T_1419 = and(_T_1415, _T_1418) \n when _T_1419 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<4>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_1420 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_1421 = bits(_T_1420, 0, 0) \n node _T_1422 = eq(_T_1421, UInt<1>(0h0)) \n node _T_1423 = asUInt(reset) \n node _T_1424 = eq(_T_1423, UInt<1>(0h0)) \n when _T_1424 : \n node _T_1425 = eq(_T_1422, UInt<1>(0h0)) \n when _T_1425 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_1422, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<16> \n connect d_clr_1, UInt<16>(0h0) \n wire d_clr_wo_ready_1 : UInt<16> \n connect d_clr_wo_ready_1, UInt<16>(0h0) \n wire d_opcodes_clr_1 : UInt<64> \n connect d_opcodes_clr_1, UInt<64>(0h0) \n wire d_sizes_clr_1 : UInt<128> \n connect d_sizes_clr_1, UInt<128>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1426 = and(io.in.d.valid, d_first_2) \n node _T_1427 = and(_T_1426, UInt<1>(0h1)) \n node _T_1428 = and(_T_1427, d_release_ack_1) \n when _T_1428 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_1429 = and(io.in.d.ready, io.in.d.valid) \n node _T_1430 = and(_T_1429, d_first_2) \n node _T_1431 = and(_T_1430, UInt<1>(0h1)) \n node _T_1432 = and(_T_1431, d_release_ack_1) \n when _T_1432 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_1433 = and(io.in.d.valid, d_first_2) \n node _T_1434 = and(_T_1433, UInt<1>(0h1)) \n node _T_1435 = and(_T_1434, d_release_ack_1) \n when _T_1435 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_1436 = dshr(inflight_1, io.in.d.bits.source) \n node _T_1437 = bits(_T_1436, 0, 0) \n node _T_1438 = or(_T_1437, same_cycle_resp_1) \n node _T_1439 = asUInt(reset) \n node _T_1440 = eq(_T_1439, UInt<1>(0h0)) \n when _T_1440 : \n node _T_1441 = eq(_T_1438, UInt<1>(0h0)) \n when _T_1441 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_1438, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<32>(0h0) \n connect _WIRE_16.bits.source, UInt<4>(0h0) \n connect _WIRE_16.bits.size, UInt<4>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_1442 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_1443 = asUInt(reset) \n node _T_1444 = eq(_T_1443, UInt<1>(0h0)) \n when _T_1444 : \n node _T_1445 = eq(_T_1442, UInt<1>(0h0)) \n when _T_1445 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_1442, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_1446 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_1447 = asUInt(reset) \n node _T_1448 = eq(_T_1447, UInt<1>(0h0)) \n when _T_1448 : \n node _T_1449 = eq(_T_1446, UInt<1>(0h0)) \n when _T_1449 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1446, UInt<1>(0h1), \"\") : assert_110 \n node _T_1450 = and(io.in.d.valid, d_first_2) \n node _T_1451 = and(_T_1450, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<32>(0h0) \n connect _WIRE_18.bits.source, UInt<4>(0h0) \n connect _WIRE_18.bits.size, UInt<4>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_1452 = and(_T_1451, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<32>(0h0) \n connect _WIRE_20.bits.source, UInt<4>(0h0) \n connect _WIRE_20.bits.size, UInt<4>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_1453 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_1454 = and(_T_1452, _T_1453) \n node _T_1455 = and(_T_1454, d_release_ack_1) \n node _T_1456 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_1457 = and(_T_1455, _T_1456) \n when _T_1457 : \n node _T_1458 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<32>(0h0) \n connect _WIRE_22.bits.source, UInt<4>(0h0) \n connect _WIRE_22.bits.size, UInt<4>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_1459 = or(_T_1458, _WIRE_23.ready) \n node _T_1460 = asUInt(reset) \n node _T_1461 = eq(_T_1460, UInt<1>(0h0)) \n when _T_1461 : \n node _T_1462 = eq(_T_1459, UInt<1>(0h0)) \n when _T_1462 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1459, UInt<1>(0h1), \"\") : assert_111 \n node _T_1463 = orr(c_set_wo_ready) \n when _T_1463 : \n node _T_1464 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_1465 = asUInt(reset) \n node _T_1466 = eq(_T_1465, UInt<1>(0h0)) \n when _T_1466 : \n node _T_1467 = eq(_T_1464, UInt<1>(0h0)) \n when _T_1467 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_1464, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_41 \n node _T_1468 = orr(inflight_1) \n node _T_1469 = eq(_T_1468, UInt<1>(0h0)) \n node _T_1470 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_1471 = or(_T_1469, _T_1470) \n node _T_1472 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_1473 = or(_T_1471, _T_1472) \n node _T_1474 = asUInt(reset) \n node _T_1475 = eq(_T_1474, UInt<1>(0h0)) \n when _T_1475 : \n node _T_1476 = eq(_T_1473, UInt<1>(0h0)) \n when _T_1476 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_1473, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<4>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_1477 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_1478 = and(io.in.d.ready, io.in.d.valid) \n node _T_1479 = or(_T_1477, _T_1478) \n when _T_1479 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_20(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [8:0] c_first_beats1_decode = 9'h0;\t// @[Edges.scala:220:59]\n wire [8:0] c_first_beats1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] _c_first_count_T = 9'h0;\t// @[Edges.scala:234:27]\n wire [8:0] c_first_count = 9'h0;\t// @[Edges.scala:234:25]\n wire [8:0] _c_first_counter_T = 9'h0;\t// @[Edges.scala:236:21]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_10 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_14 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_16 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_20 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_22 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_28 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_30 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_34 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_36 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_40 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_42 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_46 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_48 = 1'h1;\t// @[Parameters.scala:57:20]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [8:0] c_first_counter1 = 9'h1FF;\t// @[Edges.scala:230:28]\n wire [9:0] _c_first_counter1_T = 10'h3FF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] c_opcodes_set = 64'h0;\t// @[Monitor.scala:740:34]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_first_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_first_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [131:0] _c_sizes_set_T_1 = 132'h0;\t// @[Monitor.scala:768:52]\n wire [6:0] _c_opcodes_set_T = 7'h0;\t// @[Monitor.scala:767:79]\n wire [6:0] _c_sizes_set_T = 7'h0;\t// @[Monitor.scala:768:77]\n wire [130:0] _c_opcodes_set_T_1 = 131'h0;\t// @[Monitor.scala:767:54]\n wire [4:0] _c_sizes_set_interm_T_1 = 5'h1;\t// @[Monitor.scala:766:59]\n wire [4:0] c_sizes_set_interm = 5'h0;\t// @[Monitor.scala:755:40]\n wire [4:0] _c_sizes_set_interm_T = 5'h0;\t// @[Monitor.scala:766:51]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [15:0] _c_set_wo_ready_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [15:0] _c_set_T = 16'h1;\t// @[OneHot.scala:58:35]\n wire [127:0] c_sizes_set = 128'h0;\t// @[Monitor.scala:741:34]\n wire [15:0] c_set = 16'h0;\t// @[Monitor.scala:738:34]\n wire [15:0] c_set_wo_ready = 16'h0;\t// @[Monitor.scala:739:34]\n wire [11:0] _c_first_beats1_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _c_first_beats1_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _a_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_sizes_clr_T = 4'h8;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_sizes_clr_T_6 = 4'h8;\t// @[Monitor.scala:791:48]\n wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_1 = _source_ok_T == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_3 = _source_ok_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_5 = _source_ok_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_7 = _source_ok_T_6 == 2'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_9 = _source_ok_T_7;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_11 = _source_ok_T_9;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_13 = _source_ok_T_12 == 2'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_15 = _source_ok_T_13;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_17 = _source_ok_T_15;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2 = _source_ok_T_17;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_19 = &_source_ok_T_18;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_21 = _source_ok_T_19;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_23 = _source_ok_T_21;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_3 = _source_ok_T_23;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_27 = _source_ok_T_26 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_29 = _source_ok_T_27;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_31 = _source_ok_T_29;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_0 = _source_ok_T_31;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_33 = _source_ok_T_32 == 2'h1;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_35 = _source_ok_T_33;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_37 = _source_ok_T_35;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_37;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_39 = _source_ok_T_38 == 2'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_41 = _source_ok_T_39;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_43 = _source_ok_T_41;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_2 = _source_ok_T_43;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_45 = &_source_ok_T_44;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_47 = _source_ok_T_45;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_49 = _source_ok_T_47;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_3 = _source_ok_T_49;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _T_1406 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_1406;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_1406;\t// @[Decoupled.scala:51:35]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg [3:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_1479 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_1479;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_1479;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_1479;\t// @[Decoupled.scala:51:35]\n wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg [3:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [15:0] inflight;\t// @[Monitor.scala:614:27]\n reg [63:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [127:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [15:0] a_set;\t// @[Monitor.scala:626:34]\n wire [15:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [63:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [127:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [6:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [6:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [6:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [6:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [7:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :641:65]\n wire [6:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65]\n wire [6:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_2;\t// @[Monitor.scala:641:65, :681:99]\n wire [6:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_2;\t// @[Monitor.scala:641:65, :750:67]\n wire [6:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_2;\t// @[Monitor.scala:641:65, :791:99]\n wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[7:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [4:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [15:0] _GEN_4 = 16'h1 << _GEN_3;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_4;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_4;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1332 = _T_1406 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_1332 ? _a_set_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_1332 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_1332 ? _a_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_1332 ? _a_opcodes_set_T_1[63:0] : 64'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :660:77]\n wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_1332 ? _a_sizes_set_T_1[127:0] : 128'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [15:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [15:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [63:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [127:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_5;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_5;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_1378 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0};\t// @[OneHot.scala:58:35]\n wire [15:0] _GEN_7 = 16'h1 << _GEN_6;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_7;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_1378 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1347 = _T_1479 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_1347 ? _d_clr_T : 16'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_1347 ? _d_opcodes_clr_T_5[63:0] : 64'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_1347 ? _d_sizes_clr_T_5[127:0] : 128'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [15:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [15:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [15:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [15:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [63:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [127:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [7:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[7:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [15:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [15:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [63:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [127:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_1450 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_1450 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0;\t// @[OneHot.scala:58:35]\n wire _T_1432 = _T_1479 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_1432 ? _d_clr_T_1 : 16'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_1432 ? _d_opcodes_clr_T_11[63:0] : 64'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_1432 ? _d_sizes_clr_T_11[127:0] : 128'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [15:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":35474,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module RVCExpander_8 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>} \n\n\n node _io_rvc_T = bits(io.in, 1, 0) \n node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3)) \n connect io.rvc, _io_rvc_T_1 \n node _io_out_s_opc_T = bits(io.in, 12, 5) \n node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T) \n node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f)) \n node _io_out_s_T = bits(io.in, 10, 7) \n node _io_out_s_T_1 = bits(io.in, 12, 11) \n node _io_out_s_T_2 = bits(io.in, 5, 5) \n node _io_out_s_T_3 = bits(io.in, 6, 6) \n node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0)) \n node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1) \n node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2) \n node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo) \n node _io_out_s_T_5 = bits(io.in, 4, 2) \n node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5) \n node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc) \n node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2)) \n node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0)) \n node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1) \n node _io_out_s_T_8 = bits(io.in, 4, 2) \n node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8) \n node _io_out_s_T_10 = bits(io.in, 4, 2) \n node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10) \n node _io_out_s_T_12 = bits(io.in, 31, 27) \n wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_0.bits, _io_out_s_T_7 \n connect io_out_s_0.rd, _io_out_s_T_9 \n connect io_out_s_0.rs1, UInt<5>(0h2) \n connect io_out_s_0.rs2, _io_out_s_T_11 \n connect io_out_s_0.rs3, _io_out_s_T_12 \n node _io_out_s_T_13 = bits(io.in, 6, 5) \n node _io_out_s_T_14 = bits(io.in, 12, 10) \n node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14) \n node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0)) \n node _io_out_s_T_16 = bits(io.in, 9, 7) \n node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16) \n node _io_out_s_T_18 = bits(io.in, 4, 2) \n node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18) \n node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7)) \n node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17) \n node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3)) \n node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2) \n node _io_out_s_T_21 = bits(io.in, 4, 2) \n node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21) \n node _io_out_s_T_23 = bits(io.in, 9, 7) \n node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23) \n node _io_out_s_T_25 = bits(io.in, 4, 2) \n node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25) \n node _io_out_s_T_27 = bits(io.in, 31, 27) \n wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_1.bits, _io_out_s_T_20 \n connect io_out_s_1.rd, _io_out_s_T_22 \n connect io_out_s_1.rs1, _io_out_s_T_24 \n connect io_out_s_1.rs2, _io_out_s_T_26 \n connect io_out_s_1.rs3, _io_out_s_T_27 \n node _io_out_s_T_28 = bits(io.in, 5, 5) \n node _io_out_s_T_29 = bits(io.in, 12, 10) \n node _io_out_s_T_30 = bits(io.in, 6, 6) \n node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0)) \n node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29) \n node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3) \n node _io_out_s_T_32 = bits(io.in, 9, 7) \n node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32) \n node _io_out_s_T_34 = bits(io.in, 4, 2) \n node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34) \n node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3)) \n node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33) \n node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2)) \n node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4) \n node _io_out_s_T_37 = bits(io.in, 4, 2) \n node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37) \n node _io_out_s_T_39 = bits(io.in, 9, 7) \n node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39) \n node _io_out_s_T_41 = bits(io.in, 4, 2) \n node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41) \n node _io_out_s_T_43 = bits(io.in, 31, 27) \n wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_2.bits, _io_out_s_T_36 \n connect io_out_s_2.rd, _io_out_s_T_38 \n connect io_out_s_2.rs1, _io_out_s_T_40 \n connect io_out_s_2.rs2, _io_out_s_T_42 \n connect io_out_s_2.rs3, _io_out_s_T_43 \n node _io_out_s_T_44 = bits(io.in, 6, 5) \n node _io_out_s_T_45 = bits(io.in, 12, 10) \n node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45) \n node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0)) \n node _io_out_s_T_47 = bits(io.in, 9, 7) \n node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47) \n node _io_out_s_T_49 = bits(io.in, 4, 2) \n node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49) \n node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3)) \n node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48) \n node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3)) \n node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5) \n node _io_out_s_T_52 = bits(io.in, 4, 2) \n node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52) \n node _io_out_s_T_54 = bits(io.in, 9, 7) \n node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54) \n node _io_out_s_T_56 = bits(io.in, 4, 2) \n node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56) \n node _io_out_s_T_58 = bits(io.in, 31, 27) \n wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_3.bits, _io_out_s_T_51 \n connect io_out_s_3.rd, _io_out_s_T_53 \n connect io_out_s_3.rs1, _io_out_s_T_55 \n connect io_out_s_3.rs2, _io_out_s_T_57 \n connect io_out_s_3.rs3, _io_out_s_T_58 \n node _io_out_s_T_59 = bits(io.in, 5, 5) \n node _io_out_s_T_60 = bits(io.in, 12, 10) \n node _io_out_s_T_61 = bits(io.in, 6, 6) \n node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0)) \n node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60) \n node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6) \n node _io_out_s_T_63 = shr(_io_out_s_T_62, 5) \n node _io_out_s_T_64 = bits(io.in, 4, 2) \n node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64) \n node _io_out_s_T_66 = bits(io.in, 9, 7) \n node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66) \n node _io_out_s_T_68 = bits(io.in, 5, 5) \n node _io_out_s_T_69 = bits(io.in, 12, 10) \n node _io_out_s_T_70 = bits(io.in, 6, 6) \n node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0)) \n node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69) \n node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7) \n node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0) \n node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72) \n node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f)) \n node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65) \n node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67) \n node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8) \n node _io_out_s_T_74 = bits(io.in, 4, 2) \n node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74) \n node _io_out_s_T_76 = bits(io.in, 9, 7) \n node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76) \n node _io_out_s_T_78 = bits(io.in, 4, 2) \n node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78) \n node _io_out_s_T_80 = bits(io.in, 31, 27) \n wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_4.bits, _io_out_s_T_73 \n connect io_out_s_4.rd, _io_out_s_T_75 \n connect io_out_s_4.rs1, _io_out_s_T_77 \n connect io_out_s_4.rs2, _io_out_s_T_79 \n connect io_out_s_4.rs3, _io_out_s_T_80 \n node _io_out_s_T_81 = bits(io.in, 6, 5) \n node _io_out_s_T_82 = bits(io.in, 12, 10) \n node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82) \n node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0)) \n node _io_out_s_T_84 = shr(_io_out_s_T_83, 5) \n node _io_out_s_T_85 = bits(io.in, 4, 2) \n node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85) \n node _io_out_s_T_87 = bits(io.in, 9, 7) \n node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87) \n node _io_out_s_T_89 = bits(io.in, 6, 5) \n node _io_out_s_T_90 = bits(io.in, 12, 10) \n node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90) \n node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0)) \n node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0) \n node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92) \n node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27)) \n node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86) \n node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88) \n node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9) \n node _io_out_s_T_94 = bits(io.in, 4, 2) \n node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94) \n node _io_out_s_T_96 = bits(io.in, 9, 7) \n node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96) \n node _io_out_s_T_98 = bits(io.in, 4, 2) \n node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98) \n node _io_out_s_T_100 = bits(io.in, 31, 27) \n wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_5.bits, _io_out_s_T_93 \n connect io_out_s_5.rd, _io_out_s_T_95 \n connect io_out_s_5.rs1, _io_out_s_T_97 \n connect io_out_s_5.rs2, _io_out_s_T_99 \n connect io_out_s_5.rs3, _io_out_s_T_100 \n node _io_out_s_T_101 = bits(io.in, 5, 5) \n node _io_out_s_T_102 = bits(io.in, 12, 10) \n node _io_out_s_T_103 = bits(io.in, 6, 6) \n node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0)) \n node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102) \n node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10) \n node _io_out_s_T_105 = shr(_io_out_s_T_104, 5) \n node _io_out_s_T_106 = bits(io.in, 4, 2) \n node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106) \n node _io_out_s_T_108 = bits(io.in, 9, 7) \n node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108) \n node _io_out_s_T_110 = bits(io.in, 5, 5) \n node _io_out_s_T_111 = bits(io.in, 12, 10) \n node _io_out_s_T_112 = bits(io.in, 6, 6) \n node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0)) \n node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111) \n node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11) \n node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0) \n node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114) \n node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23)) \n node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107) \n node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109) \n node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12) \n node _io_out_s_T_116 = bits(io.in, 4, 2) \n node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116) \n node _io_out_s_T_118 = bits(io.in, 9, 7) \n node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118) \n node _io_out_s_T_120 = bits(io.in, 4, 2) \n node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120) \n node _io_out_s_T_122 = bits(io.in, 31, 27) \n wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_6.bits, _io_out_s_T_115 \n connect io_out_s_6.rd, _io_out_s_T_117 \n connect io_out_s_6.rs1, _io_out_s_T_119 \n connect io_out_s_6.rs2, _io_out_s_T_121 \n connect io_out_s_6.rs3, _io_out_s_T_122 \n node _io_out_s_T_123 = bits(io.in, 6, 5) \n node _io_out_s_T_124 = bits(io.in, 12, 10) \n node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124) \n node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0)) \n node _io_out_s_T_126 = shr(_io_out_s_T_125, 5) \n node _io_out_s_T_127 = bits(io.in, 4, 2) \n node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127) \n node _io_out_s_T_129 = bits(io.in, 9, 7) \n node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129) \n node _io_out_s_T_131 = bits(io.in, 6, 5) \n node _io_out_s_T_132 = bits(io.in, 12, 10) \n node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132) \n node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0)) \n node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0) \n node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134) \n node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23)) \n node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128) \n node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130) \n node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13) \n node _io_out_s_T_136 = bits(io.in, 4, 2) \n node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136) \n node _io_out_s_T_138 = bits(io.in, 9, 7) \n node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138) \n node _io_out_s_T_140 = bits(io.in, 4, 2) \n node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140) \n node _io_out_s_T_142 = bits(io.in, 31, 27) \n wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_7.bits, _io_out_s_T_135 \n connect io_out_s_7.rd, _io_out_s_T_137 \n connect io_out_s_7.rs1, _io_out_s_T_139 \n connect io_out_s_7.rs2, _io_out_s_T_141 \n connect io_out_s_7.rs3, _io_out_s_T_142 \n node _io_out_s_T_143 = bits(io.in, 12, 12) \n node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_T_145 = bits(io.in, 6, 2) \n node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145) \n node _io_out_s_T_147 = bits(io.in, 11, 7) \n node _io_out_s_T_148 = bits(io.in, 11, 7) \n node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13)) \n node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147) \n node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0)) \n node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14) \n node _io_out_s_T_150 = bits(io.in, 11, 7) \n node _io_out_s_T_151 = bits(io.in, 11, 7) \n node _io_out_s_T_152 = bits(io.in, 4, 2) \n node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152) \n node _io_out_s_T_154 = bits(io.in, 31, 27) \n wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_8.bits, _io_out_s_T_149 \n connect io_out_s_8.rd, _io_out_s_T_150 \n connect io_out_s_8.rs1, _io_out_s_T_151 \n connect io_out_s_8.rs2, _io_out_s_T_153 \n connect io_out_s_8.rs3, _io_out_s_T_154 \n node _io_out_s_opc_T_2 = bits(io.in, 11, 7) \n node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2) \n node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f)) \n node _io_out_s_T_155 = bits(io.in, 12, 12) \n node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_T_157 = bits(io.in, 6, 2) \n node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157) \n node _io_out_s_T_159 = bits(io.in, 11, 7) \n node _io_out_s_T_160 = bits(io.in, 11, 7) \n node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1) \n node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159) \n node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0)) \n node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15) \n node _io_out_s_T_162 = bits(io.in, 11, 7) \n node _io_out_s_T_163 = bits(io.in, 11, 7) \n node _io_out_s_T_164 = bits(io.in, 4, 2) \n node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164) \n node _io_out_s_T_166 = bits(io.in, 31, 27) \n wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_9.bits, _io_out_s_T_161 \n connect io_out_s_9.rd, _io_out_s_T_162 \n connect io_out_s_9.rs1, _io_out_s_T_163 \n connect io_out_s_9.rs2, _io_out_s_T_165 \n connect io_out_s_9.rs3, _io_out_s_T_166 \n node _io_out_s_T_167 = bits(io.in, 12, 12) \n node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_T_169 = bits(io.in, 6, 2) \n node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169) \n node _io_out_s_T_171 = bits(io.in, 11, 7) \n node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13)) \n node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0)) \n node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0)) \n node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16) \n node _io_out_s_T_173 = bits(io.in, 11, 7) \n node _io_out_s_T_174 = bits(io.in, 4, 2) \n node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174) \n node _io_out_s_T_176 = bits(io.in, 31, 27) \n wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_10.bits, _io_out_s_T_172 \n connect io_out_s_10.rd, _io_out_s_T_173 \n connect io_out_s_10.rs1, UInt<5>(0h0) \n connect io_out_s_10.rs2, _io_out_s_T_175 \n connect io_out_s_10.rs3, _io_out_s_T_176 \n node _io_out_s_opc_T_4 = bits(io.in, 12, 12) \n node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_opc_T_6 = bits(io.in, 6, 2) \n node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6) \n node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7) \n node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f)) \n node _io_out_s_me_T = bits(io.in, 12, 12) \n node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0)) \n node _io_out_s_me_T_2 = bits(io.in, 6, 2) \n node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2) \n node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0)) \n node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12) \n node _io_out_s_me_T_5 = bits(io.in, 11, 7) \n node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5) \n node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2) \n node _io_out_s_me_T_7 = bits(io.in, 11, 7) \n node _io_out_s_me_T_8 = bits(io.in, 11, 7) \n node _io_out_s_me_T_9 = bits(io.in, 4, 2) \n node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9) \n node _io_out_s_me_T_11 = bits(io.in, 31, 27) \n wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_me.bits, _io_out_s_me_T_6 \n connect io_out_s_me.rd, _io_out_s_me_T_7 \n connect io_out_s_me.rs1, _io_out_s_me_T_8 \n connect io_out_s_me.rs2, _io_out_s_me_T_10 \n connect io_out_s_me.rs3, _io_out_s_me_T_11 \n node _io_out_s_T_177 = bits(io.in, 11, 7) \n node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0)) \n node _io_out_s_T_179 = bits(io.in, 11, 7) \n node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2)) \n node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180) \n node _io_out_s_opc_T_9 = bits(io.in, 12, 12) \n node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_opc_T_11 = bits(io.in, 6, 2) \n node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11) \n node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12) \n node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f)) \n node _io_out_s_T_182 = bits(io.in, 12, 12) \n node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0)) \n node _io_out_s_T_184 = bits(io.in, 4, 3) \n node _io_out_s_T_185 = bits(io.in, 5, 5) \n node _io_out_s_T_186 = bits(io.in, 2, 2) \n node _io_out_s_T_187 = bits(io.in, 6, 6) \n node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187) \n node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0)) \n node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184) \n node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185) \n node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17) \n node _io_out_s_T_189 = bits(io.in, 11, 7) \n node _io_out_s_T_190 = bits(io.in, 11, 7) \n node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3) \n node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189) \n node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0)) \n node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18) \n node _io_out_s_T_192 = bits(io.in, 11, 7) \n node _io_out_s_T_193 = bits(io.in, 11, 7) \n node _io_out_s_T_194 = bits(io.in, 4, 2) \n node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194) \n node _io_out_s_T_196 = bits(io.in, 31, 27) \n wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_res.bits, _io_out_s_T_191 \n connect io_out_s_res.rd, _io_out_s_T_192 \n connect io_out_s_res.rs1, _io_out_s_T_193 \n connect io_out_s_res.rs2, _io_out_s_T_195 \n connect io_out_s_res.rs3, _io_out_s_T_196 \n node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me) \n node _io_out_s_T_197 = bits(io.in, 12, 12) \n node _io_out_s_T_198 = bits(io.in, 6, 2) \n node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198) \n node _io_out_s_T_200 = bits(io.in, 9, 7) \n node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200) \n node _io_out_s_T_202 = bits(io.in, 9, 7) \n node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202) \n node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13)) \n node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201) \n node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5)) \n node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19) \n node _io_out_s_T_205 = bits(io.in, 12, 12) \n node _io_out_s_T_206 = bits(io.in, 6, 2) \n node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206) \n node _io_out_s_T_208 = bits(io.in, 9, 7) \n node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208) \n node _io_out_s_T_210 = bits(io.in, 9, 7) \n node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210) \n node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13)) \n node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209) \n node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5)) \n node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20) \n node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000)) \n node _io_out_s_T_214 = bits(io.in, 12, 12) \n node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0)) \n node _io_out_s_T_216 = bits(io.in, 6, 2) \n node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216) \n node _io_out_s_T_218 = bits(io.in, 9, 7) \n node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218) \n node _io_out_s_T_220 = bits(io.in, 9, 7) \n node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220) \n node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13)) \n node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219) \n node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7)) \n node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21) \n node _io_out_s_funct_T = bits(io.in, 12, 12) \n node _io_out_s_funct_T_1 = bits(io.in, 6, 5) \n node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1) \n node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1)) \n node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0)) \n node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2)) \n node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4) \n node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3)) \n node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6) \n node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4)) \n node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8) \n node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5)) \n node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10) \n node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6)) \n node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12) \n node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7)) \n node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14) \n node _io_out_s_sub_T = bits(io.in, 6, 5) \n node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0)) \n node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0)) \n node _io_out_s_opc_T_14 = bits(io.in, 12, 12) \n node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33)) \n node _io_out_s_T_223 = bits(io.in, 4, 2) \n node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223) \n node _io_out_s_T_225 = bits(io.in, 9, 7) \n node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225) \n node _io_out_s_T_227 = bits(io.in, 9, 7) \n node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227) \n node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4) \n node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226) \n node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct) \n node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22) \n node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub) \n node _io_out_s_T_231 = bits(io.in, 11, 10) \n node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1)) \n node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204) \n node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2)) \n node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233) \n node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3)) \n node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235) \n node _io_out_s_T_238 = bits(io.in, 9, 7) \n node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238) \n node _io_out_s_T_240 = bits(io.in, 9, 7) \n node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240) \n node _io_out_s_T_242 = bits(io.in, 4, 2) \n node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242) \n node _io_out_s_T_244 = bits(io.in, 31, 27) \n wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_12.bits, _io_out_s_T_237 \n connect io_out_s_12.rd, _io_out_s_T_239 \n connect io_out_s_12.rs1, _io_out_s_T_241 \n connect io_out_s_12.rs2, _io_out_s_T_243 \n connect io_out_s_12.rs3, _io_out_s_T_244 \n node _io_out_s_T_245 = bits(io.in, 12, 12) \n node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0)) \n node _io_out_s_T_247 = bits(io.in, 8, 8) \n node _io_out_s_T_248 = bits(io.in, 10, 9) \n node _io_out_s_T_249 = bits(io.in, 6, 6) \n node _io_out_s_T_250 = bits(io.in, 7, 7) \n node _io_out_s_T_251 = bits(io.in, 2, 2) \n node _io_out_s_T_252 = bits(io.in, 11, 11) \n node _io_out_s_T_253 = bits(io.in, 5, 3) \n node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0)) \n node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252) \n node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo) \n node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250) \n node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247) \n node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248) \n node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo) \n node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23) \n node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20) \n node _io_out_s_T_256 = bits(io.in, 12, 12) \n node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0)) \n node _io_out_s_T_258 = bits(io.in, 8, 8) \n node _io_out_s_T_259 = bits(io.in, 10, 9) \n node _io_out_s_T_260 = bits(io.in, 6, 6) \n node _io_out_s_T_261 = bits(io.in, 7, 7) \n node _io_out_s_T_262 = bits(io.in, 2, 2) \n node _io_out_s_T_263 = bits(io.in, 11, 11) \n node _io_out_s_T_264 = bits(io.in, 5, 3) \n node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0)) \n node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263) \n node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1) \n node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261) \n node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258) \n node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259) \n node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1) \n node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24) \n node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1) \n node _io_out_s_T_267 = bits(io.in, 12, 12) \n node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0)) \n node _io_out_s_T_269 = bits(io.in, 8, 8) \n node _io_out_s_T_270 = bits(io.in, 10, 9) \n node _io_out_s_T_271 = bits(io.in, 6, 6) \n node _io_out_s_T_272 = bits(io.in, 7, 7) \n node _io_out_s_T_273 = bits(io.in, 2, 2) \n node _io_out_s_T_274 = bits(io.in, 11, 11) \n node _io_out_s_T_275 = bits(io.in, 5, 3) \n node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0)) \n node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274) \n node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2) \n node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272) \n node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269) \n node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270) \n node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2) \n node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25) \n node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11) \n node _io_out_s_T_278 = bits(io.in, 12, 12) \n node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0)) \n node _io_out_s_T_280 = bits(io.in, 8, 8) \n node _io_out_s_T_281 = bits(io.in, 10, 9) \n node _io_out_s_T_282 = bits(io.in, 6, 6) \n node _io_out_s_T_283 = bits(io.in, 7, 7) \n node _io_out_s_T_284 = bits(io.in, 2, 2) \n node _io_out_s_T_285 = bits(io.in, 11, 11) \n node _io_out_s_T_286 = bits(io.in, 5, 3) \n node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0)) \n node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285) \n node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3) \n node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283) \n node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280) \n node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281) \n node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3) \n node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26) \n node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12) \n node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0)) \n node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f)) \n node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266) \n node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277) \n node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27) \n node _io_out_s_T_290 = bits(io.in, 9, 7) \n node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290) \n node _io_out_s_T_292 = bits(io.in, 4, 2) \n node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292) \n node _io_out_s_T_294 = bits(io.in, 31, 27) \n wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_13.bits, _io_out_s_T_289 \n connect io_out_s_13.rd, UInt<5>(0h0) \n connect io_out_s_13.rs1, _io_out_s_T_291 \n connect io_out_s_13.rs2, _io_out_s_T_293 \n connect io_out_s_13.rs3, _io_out_s_T_294 \n node _io_out_s_T_295 = bits(io.in, 12, 12) \n node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_297 = bits(io.in, 6, 5) \n node _io_out_s_T_298 = bits(io.in, 2, 2) \n node _io_out_s_T_299 = bits(io.in, 11, 10) \n node _io_out_s_T_300 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300) \n node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0)) \n node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297) \n node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298) \n node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28) \n node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12) \n node _io_out_s_T_303 = bits(io.in, 12, 12) \n node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_305 = bits(io.in, 6, 5) \n node _io_out_s_T_306 = bits(io.in, 2, 2) \n node _io_out_s_T_307 = bits(io.in, 11, 10) \n node _io_out_s_T_308 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308) \n node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0)) \n node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305) \n node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306) \n node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29) \n node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5) \n node _io_out_s_T_311 = bits(io.in, 9, 7) \n node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311) \n node _io_out_s_T_313 = bits(io.in, 12, 12) \n node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_315 = bits(io.in, 6, 5) \n node _io_out_s_T_316 = bits(io.in, 2, 2) \n node _io_out_s_T_317 = bits(io.in, 11, 10) \n node _io_out_s_T_318 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318) \n node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0)) \n node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315) \n node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316) \n node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30) \n node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1) \n node _io_out_s_T_321 = bits(io.in, 12, 12) \n node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_323 = bits(io.in, 6, 5) \n node _io_out_s_T_324 = bits(io.in, 2, 2) \n node _io_out_s_T_325 = bits(io.in, 11, 10) \n node _io_out_s_T_326 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326) \n node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0)) \n node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323) \n node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324) \n node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31) \n node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11) \n node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63)) \n node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320) \n node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4) \n node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312) \n node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310) \n node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4) \n node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32) \n node _io_out_s_T_330 = bits(io.in, 9, 7) \n node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330) \n node _io_out_s_T_332 = bits(io.in, 9, 7) \n node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332) \n node _io_out_s_T_334 = bits(io.in, 31, 27) \n wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_14.bits, _io_out_s_T_329 \n connect io_out_s_14.rd, _io_out_s_T_331 \n connect io_out_s_14.rs1, _io_out_s_T_333 \n connect io_out_s_14.rs2, UInt<5>(0h0) \n connect io_out_s_14.rs3, _io_out_s_T_334 \n node _io_out_s_T_335 = bits(io.in, 12, 12) \n node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_337 = bits(io.in, 6, 5) \n node _io_out_s_T_338 = bits(io.in, 2, 2) \n node _io_out_s_T_339 = bits(io.in, 11, 10) \n node _io_out_s_T_340 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340) \n node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0)) \n node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337) \n node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338) \n node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33) \n node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12) \n node _io_out_s_T_343 = bits(io.in, 12, 12) \n node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_345 = bits(io.in, 6, 5) \n node _io_out_s_T_346 = bits(io.in, 2, 2) \n node _io_out_s_T_347 = bits(io.in, 11, 10) \n node _io_out_s_T_348 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348) \n node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0)) \n node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345) \n node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346) \n node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34) \n node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5) \n node _io_out_s_T_351 = bits(io.in, 9, 7) \n node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351) \n node _io_out_s_T_353 = bits(io.in, 12, 12) \n node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_355 = bits(io.in, 6, 5) \n node _io_out_s_T_356 = bits(io.in, 2, 2) \n node _io_out_s_T_357 = bits(io.in, 11, 10) \n node _io_out_s_T_358 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358) \n node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0)) \n node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355) \n node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356) \n node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35) \n node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1) \n node _io_out_s_T_361 = bits(io.in, 12, 12) \n node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0)) \n node _io_out_s_T_363 = bits(io.in, 6, 5) \n node _io_out_s_T_364 = bits(io.in, 2, 2) \n node _io_out_s_T_365 = bits(io.in, 11, 10) \n node _io_out_s_T_366 = bits(io.in, 4, 3) \n node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366) \n node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0)) \n node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363) \n node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364) \n node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36) \n node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11) \n node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63)) \n node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360) \n node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5) \n node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352) \n node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350) \n node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5) \n node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37) \n node _io_out_s_T_370 = bits(io.in, 9, 7) \n node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370) \n node _io_out_s_T_372 = bits(io.in, 31, 27) \n wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_15.bits, _io_out_s_T_369 \n connect io_out_s_15.rd, UInt<5>(0h0) \n connect io_out_s_15.rs1, _io_out_s_T_371 \n connect io_out_s_15.rs2, UInt<5>(0h0) \n connect io_out_s_15.rs3, _io_out_s_T_372 \n node _io_out_s_load_opc_T = bits(io.in, 11, 7) \n node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T) \n node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f)) \n node _io_out_s_T_373 = bits(io.in, 12, 12) \n node _io_out_s_T_374 = bits(io.in, 6, 2) \n node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374) \n node _io_out_s_T_376 = bits(io.in, 11, 7) \n node _io_out_s_T_377 = bits(io.in, 11, 7) \n node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13)) \n node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376) \n node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1)) \n node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38) \n node _io_out_s_T_379 = bits(io.in, 11, 7) \n node _io_out_s_T_380 = bits(io.in, 11, 7) \n node _io_out_s_T_381 = bits(io.in, 6, 2) \n node _io_out_s_T_382 = bits(io.in, 31, 27) \n wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_16.bits, _io_out_s_T_378 \n connect io_out_s_16.rd, _io_out_s_T_379 \n connect io_out_s_16.rs1, _io_out_s_T_380 \n connect io_out_s_16.rs2, _io_out_s_T_381 \n connect io_out_s_16.rs3, _io_out_s_T_382 \n node _io_out_s_T_383 = bits(io.in, 4, 2) \n node _io_out_s_T_384 = bits(io.in, 12, 12) \n node _io_out_s_T_385 = bits(io.in, 6, 5) \n node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0)) \n node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384) \n node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39) \n node _io_out_s_T_387 = bits(io.in, 11, 7) \n node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7)) \n node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2)) \n node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3)) \n node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40) \n node _io_out_s_T_389 = bits(io.in, 11, 7) \n node _io_out_s_T_390 = bits(io.in, 6, 2) \n node _io_out_s_T_391 = bits(io.in, 31, 27) \n wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_17.bits, _io_out_s_T_388 \n connect io_out_s_17.rd, _io_out_s_T_389 \n connect io_out_s_17.rs1, UInt<5>(0h2) \n connect io_out_s_17.rs2, _io_out_s_T_390 \n connect io_out_s_17.rs3, _io_out_s_T_391 \n node _io_out_s_T_392 = bits(io.in, 3, 2) \n node _io_out_s_T_393 = bits(io.in, 12, 12) \n node _io_out_s_T_394 = bits(io.in, 6, 4) \n node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0)) \n node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393) \n node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41) \n node _io_out_s_T_396 = bits(io.in, 11, 7) \n node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc) \n node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2)) \n node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2)) \n node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42) \n node _io_out_s_T_398 = bits(io.in, 11, 7) \n node _io_out_s_T_399 = bits(io.in, 6, 2) \n node _io_out_s_T_400 = bits(io.in, 31, 27) \n wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_18.bits, _io_out_s_T_397 \n connect io_out_s_18.rd, _io_out_s_T_398 \n connect io_out_s_18.rs1, UInt<5>(0h2) \n connect io_out_s_18.rs2, _io_out_s_T_399 \n connect io_out_s_18.rs3, _io_out_s_T_400 \n node _io_out_s_T_401 = bits(io.in, 4, 2) \n node _io_out_s_T_402 = bits(io.in, 12, 12) \n node _io_out_s_T_403 = bits(io.in, 6, 5) \n node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0)) \n node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402) \n node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43) \n node _io_out_s_T_405 = bits(io.in, 11, 7) \n node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc) \n node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2)) \n node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3)) \n node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44) \n node _io_out_s_T_407 = bits(io.in, 11, 7) \n node _io_out_s_T_408 = bits(io.in, 6, 2) \n node _io_out_s_T_409 = bits(io.in, 31, 27) \n wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_19.bits, _io_out_s_T_406 \n connect io_out_s_19.rd, _io_out_s_T_407 \n connect io_out_s_19.rs1, UInt<5>(0h2) \n connect io_out_s_19.rs2, _io_out_s_T_408 \n connect io_out_s_19.rs3, _io_out_s_T_409 \n node _io_out_s_mv_T = bits(io.in, 6, 2) \n node _io_out_s_mv_T_1 = bits(io.in, 11, 7) \n node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33)) \n node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0)) \n node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0)) \n node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo) \n node _io_out_s_mv_T_3 = bits(io.in, 11, 7) \n node _io_out_s_mv_T_4 = bits(io.in, 6, 2) \n node _io_out_s_mv_T_5 = bits(io.in, 31, 27) \n wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_mv.bits, _io_out_s_mv_T_2 \n connect io_out_s_mv.rd, _io_out_s_mv_T_3 \n connect io_out_s_mv.rs1, UInt<5>(0h0) \n connect io_out_s_mv.rs2, _io_out_s_mv_T_4 \n connect io_out_s_mv.rs3, _io_out_s_mv_T_5 \n node _io_out_s_add_T = bits(io.in, 6, 2) \n node _io_out_s_add_T_1 = bits(io.in, 11, 7) \n node _io_out_s_add_T_2 = bits(io.in, 11, 7) \n node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33)) \n node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1) \n node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0)) \n node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo) \n node _io_out_s_add_T_4 = bits(io.in, 11, 7) \n node _io_out_s_add_T_5 = bits(io.in, 11, 7) \n node _io_out_s_add_T_6 = bits(io.in, 6, 2) \n node _io_out_s_add_T_7 = bits(io.in, 31, 27) \n wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_add.bits, _io_out_s_add_T_3 \n connect io_out_s_add.rd, _io_out_s_add_T_4 \n connect io_out_s_add.rs1, _io_out_s_add_T_5 \n connect io_out_s_add.rs2, _io_out_s_add_T_6 \n connect io_out_s_add.rs3, _io_out_s_add_T_7 \n node _io_out_s_jr_T = bits(io.in, 6, 2) \n node _io_out_s_jr_T_1 = bits(io.in, 11, 7) \n node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67)) \n node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1) \n node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0)) \n node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo) \n node _io_out_s_reserved_T = shr(io_out_s_jr, 7) \n node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f)) \n node _io_out_s_jr_reserved_T = bits(io.in, 11, 7) \n node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T) \n node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved) \n node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7) \n node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2) \n node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27) \n wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2 \n connect io_out_s_jr_reserved.rd, UInt<5>(0h0) \n connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3 \n connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4 \n connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5 \n node _io_out_s_jr_mv_T = bits(io.in, 6, 2) \n node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T) \n node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved) \n node _io_out_s_jalr_T = bits(io.in, 6, 2) \n node _io_out_s_jalr_T_1 = bits(io.in, 11, 7) \n node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67)) \n node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1) \n node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0)) \n node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo) \n node _io_out_s_ebreak_T = shr(io_out_s_jr, 7) \n node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73)) \n node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000)) \n node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7) \n node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T) \n node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak) \n node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7) \n node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2) \n node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27) \n wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2 \n connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1) \n connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3 \n connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4 \n connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5 \n node _io_out_s_jalr_add_T = bits(io.in, 6, 2) \n node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T) \n node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak) \n node _io_out_s_T_410 = bits(io.in, 12, 12) \n node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv) \n node _io_out_s_T_411 = bits(io.in, 9, 7) \n node _io_out_s_T_412 = bits(io.in, 12, 10) \n node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412) \n node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0)) \n node _io_out_s_T_414 = shr(_io_out_s_T_413, 5) \n node _io_out_s_T_415 = bits(io.in, 6, 2) \n node _io_out_s_T_416 = bits(io.in, 9, 7) \n node _io_out_s_T_417 = bits(io.in, 12, 10) \n node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417) \n node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0)) \n node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0) \n node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419) \n node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27)) \n node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415) \n node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2)) \n node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45) \n node _io_out_s_T_421 = bits(io.in, 11, 7) \n node _io_out_s_T_422 = bits(io.in, 6, 2) \n node _io_out_s_T_423 = bits(io.in, 31, 27) \n wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_21.bits, _io_out_s_T_420 \n connect io_out_s_21.rd, _io_out_s_T_421 \n connect io_out_s_21.rs1, UInt<5>(0h2) \n connect io_out_s_21.rs2, _io_out_s_T_422 \n connect io_out_s_21.rs3, _io_out_s_T_423 \n node _io_out_s_T_424 = bits(io.in, 8, 7) \n node _io_out_s_T_425 = bits(io.in, 12, 9) \n node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425) \n node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0)) \n node _io_out_s_T_427 = shr(_io_out_s_T_426, 5) \n node _io_out_s_T_428 = bits(io.in, 6, 2) \n node _io_out_s_T_429 = bits(io.in, 8, 7) \n node _io_out_s_T_430 = bits(io.in, 12, 9) \n node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430) \n node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0)) \n node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0) \n node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432) \n node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23)) \n node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428) \n node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2)) \n node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46) \n node _io_out_s_T_434 = bits(io.in, 11, 7) \n node _io_out_s_T_435 = bits(io.in, 6, 2) \n node _io_out_s_T_436 = bits(io.in, 31, 27) \n wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_22.bits, _io_out_s_T_433 \n connect io_out_s_22.rd, _io_out_s_T_434 \n connect io_out_s_22.rs1, UInt<5>(0h2) \n connect io_out_s_22.rs2, _io_out_s_T_435 \n connect io_out_s_22.rs3, _io_out_s_T_436 \n node _io_out_s_T_437 = bits(io.in, 9, 7) \n node _io_out_s_T_438 = bits(io.in, 12, 10) \n node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438) \n node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0)) \n node _io_out_s_T_440 = shr(_io_out_s_T_439, 5) \n node _io_out_s_T_441 = bits(io.in, 6, 2) \n node _io_out_s_T_442 = bits(io.in, 9, 7) \n node _io_out_s_T_443 = bits(io.in, 12, 10) \n node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443) \n node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0)) \n node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0) \n node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445) \n node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23)) \n node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441) \n node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2)) \n node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47) \n node _io_out_s_T_447 = bits(io.in, 11, 7) \n node _io_out_s_T_448 = bits(io.in, 6, 2) \n node _io_out_s_T_449 = bits(io.in, 31, 27) \n wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_23.bits, _io_out_s_T_446 \n connect io_out_s_23.rd, _io_out_s_T_447 \n connect io_out_s_23.rs1, UInt<5>(0h2) \n connect io_out_s_23.rs2, _io_out_s_T_448 \n connect io_out_s_23.rs3, _io_out_s_T_449 \n node _io_out_s_T_450 = bits(io.in, 11, 7) \n node _io_out_s_T_451 = bits(io.in, 19, 15) \n node _io_out_s_T_452 = bits(io.in, 24, 20) \n node _io_out_s_T_453 = bits(io.in, 31, 27) \n wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_24.bits, io.in \n connect io_out_s_24.rd, _io_out_s_T_450 \n connect io_out_s_24.rs1, _io_out_s_T_451 \n connect io_out_s_24.rs2, _io_out_s_T_452 \n connect io_out_s_24.rs3, _io_out_s_T_453 \n node _io_out_s_T_454 = bits(io.in, 11, 7) \n node _io_out_s_T_455 = bits(io.in, 19, 15) \n node _io_out_s_T_456 = bits(io.in, 24, 20) \n node _io_out_s_T_457 = bits(io.in, 31, 27) \n wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_25.bits, io.in \n connect io_out_s_25.rd, _io_out_s_T_454 \n connect io_out_s_25.rs1, _io_out_s_T_455 \n connect io_out_s_25.rs2, _io_out_s_T_456 \n connect io_out_s_25.rs3, _io_out_s_T_457 \n node _io_out_s_T_458 = bits(io.in, 11, 7) \n node _io_out_s_T_459 = bits(io.in, 19, 15) \n node _io_out_s_T_460 = bits(io.in, 24, 20) \n node _io_out_s_T_461 = bits(io.in, 31, 27) \n wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_26.bits, io.in \n connect io_out_s_26.rd, _io_out_s_T_458 \n connect io_out_s_26.rs1, _io_out_s_T_459 \n connect io_out_s_26.rs2, _io_out_s_T_460 \n connect io_out_s_26.rs3, _io_out_s_T_461 \n node _io_out_s_T_462 = bits(io.in, 11, 7) \n node _io_out_s_T_463 = bits(io.in, 19, 15) \n node _io_out_s_T_464 = bits(io.in, 24, 20) \n node _io_out_s_T_465 = bits(io.in, 31, 27) \n wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_27.bits, io.in \n connect io_out_s_27.rd, _io_out_s_T_462 \n connect io_out_s_27.rs1, _io_out_s_T_463 \n connect io_out_s_27.rs2, _io_out_s_T_464 \n connect io_out_s_27.rs3, _io_out_s_T_465 \n node _io_out_s_T_466 = bits(io.in, 11, 7) \n node _io_out_s_T_467 = bits(io.in, 19, 15) \n node _io_out_s_T_468 = bits(io.in, 24, 20) \n node _io_out_s_T_469 = bits(io.in, 31, 27) \n wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_28.bits, io.in \n connect io_out_s_28.rd, _io_out_s_T_466 \n connect io_out_s_28.rs1, _io_out_s_T_467 \n connect io_out_s_28.rs2, _io_out_s_T_468 \n connect io_out_s_28.rs3, _io_out_s_T_469 \n node _io_out_s_T_470 = bits(io.in, 11, 7) \n node _io_out_s_T_471 = bits(io.in, 19, 15) \n node _io_out_s_T_472 = bits(io.in, 24, 20) \n node _io_out_s_T_473 = bits(io.in, 31, 27) \n wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_29.bits, io.in \n connect io_out_s_29.rd, _io_out_s_T_470 \n connect io_out_s_29.rs1, _io_out_s_T_471 \n connect io_out_s_29.rs2, _io_out_s_T_472 \n connect io_out_s_29.rs3, _io_out_s_T_473 \n node _io_out_s_T_474 = bits(io.in, 11, 7) \n node _io_out_s_T_475 = bits(io.in, 19, 15) \n node _io_out_s_T_476 = bits(io.in, 24, 20) \n node _io_out_s_T_477 = bits(io.in, 31, 27) \n wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_30.bits, io.in \n connect io_out_s_30.rd, _io_out_s_T_474 \n connect io_out_s_30.rs1, _io_out_s_T_475 \n connect io_out_s_30.rs2, _io_out_s_T_476 \n connect io_out_s_30.rs3, _io_out_s_T_477 \n node _io_out_s_T_478 = bits(io.in, 11, 7) \n node _io_out_s_T_479 = bits(io.in, 19, 15) \n node _io_out_s_T_480 = bits(io.in, 24, 20) \n node _io_out_s_T_481 = bits(io.in, 31, 27) \n wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} \n connect io_out_s_31.bits, io.in \n connect io_out_s_31.rd, _io_out_s_T_478 \n connect io_out_s_31.rs1, _io_out_s_T_479 \n connect io_out_s_31.rs2, _io_out_s_T_480 \n connect io_out_s_31.rs3, _io_out_s_T_481 \n node _io_out_T = bits(io.in, 1, 0) \n node _io_out_T_1 = bits(io.in, 15, 13) \n node _io_out_T_2 = cat(_io_out_T, _io_out_T_1) \n node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1)) \n node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0) \n node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2)) \n node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4) \n node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3)) \n node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6) \n node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4)) \n node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8) \n node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5)) \n node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10) \n node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6)) \n node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12) \n node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7)) \n node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14) \n node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8)) \n node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16) \n node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9)) \n node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18) \n node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha)) \n node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20) \n node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb)) \n node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22) \n node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc)) \n node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24) \n node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd)) \n node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26) \n node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he)) \n node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28) \n node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf)) \n node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30) \n node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10)) \n node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32) \n node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11)) \n node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34) \n node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12)) \n node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36) \n node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13)) \n node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38) \n node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14)) \n node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40) \n node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15)) \n node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42) \n node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16)) \n node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44) \n node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17)) \n node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46) \n node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18)) \n node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48) \n node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19)) \n node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50) \n node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a)) \n node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52) \n node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b)) \n node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54) \n node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c)) \n node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56) \n node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d)) \n node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58) \n node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e)) \n node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60) \n node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f)) \n node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62) \n connect io.out, _io_out_T_64 \n node _io_ill_s_T = bits(io.in, 12, 2) \n node _io_ill_s_T_1 = orr(_io_ill_s_T) \n node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0)) \n node _io_ill_s_T_2 = bits(io.in, 11, 7) \n node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0)) \n node _io_ill_s_T_3 = bits(io.in, 12, 12) \n node _io_ill_s_T_4 = bits(io.in, 6, 2) \n node _io_ill_s_T_5 = orr(_io_ill_s_T_4) \n node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5) \n node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0)) \n node _io_ill_s_T_7 = bits(io.in, 12, 10) \n node _io_ill_s_T_8 = andr(_io_ill_s_T_7) \n node _io_ill_s_T_9 = bits(io.in, 6, 6) \n node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1)) \n node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10) \n node _io_ill_s_T_11 = bits(io.in, 11, 7) \n node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0)) \n node _io_ill_s_T_12 = bits(io.in, 11, 7) \n node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0)) \n node _io_ill_s_T_13 = bits(io.in, 12, 2) \n node _io_ill_s_T_14 = orr(_io_ill_s_T_13) \n node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0)) \n node _io_ill_T = bits(io.in, 1, 0) \n node _io_ill_T_1 = bits(io.in, 15, 13) \n node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1) \n node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1)) \n node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0) \n node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2)) \n node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4) \n node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3)) \n node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6) \n node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4)) \n node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8) \n node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5)) \n node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10) \n node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6)) \n node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12) \n node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7)) \n node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14) \n node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8)) \n node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16) \n node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9)) \n node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18) \n node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha)) \n node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20) \n node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb)) \n node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22) \n node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc)) \n node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24) \n node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd)) \n node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26) \n node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he)) \n node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28) \n node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf)) \n node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30) \n node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10)) \n node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32) \n node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11)) \n node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34) \n node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12)) \n node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36) \n node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13)) \n node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38) \n node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14)) \n node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40) \n node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15)) \n node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42) \n node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16)) \n node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44) \n node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17)) \n node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46) \n node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18)) \n node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48) \n node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19)) \n node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50) \n node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a)) \n node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52) \n node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b)) \n node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54) \n node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c)) \n node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56) \n node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d)) \n node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58) \n node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e)) \n node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60) \n node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f)) \n node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62) \n connect io.ill, _io_ill_T_64"},"response":{"kind":"string","value":"module RVCExpander_8(\t// @[RVC.scala:190:7]\n input clock,\t// @[RVC.scala:190:7]\n input reset,\t// @[RVC.scala:190:7]\n input [31:0] io_in,\t// @[RVC.scala:191:14]\n output [31:0] io_out_bits,\t// @[RVC.scala:191:14]\n output io_rvc\t// @[RVC.scala:191:14]\n);\n\n wire [31:0] io_in_0 = io_in;\t// @[RVC.scala:190:7]\n wire [11:0] io_out_s_jr_lo = 12'h67;\t// @[RVC.scala:135:19]\n wire [4:0] io_out_s_10_rs1 = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_13_rd = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_14_rs2 = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_15_rd = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_15_rs2 = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_mv_rs1 = 5'h0;\t// @[RVC.scala:21:19]\n wire [4:0] io_out_s_jr_reserved_rd = 5'h0;\t// @[RVC.scala:21:19]\n wire [11:0] io_out_s_jalr_lo = 12'hE7;\t// @[RVC.scala:139:21]\n wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_0_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_17_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_18_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_19_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_21_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_22_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_23_rs1 = 5'h2;\t// @[package.scala:39:86]\n wire [31:0] io_out_s_24_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_25_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_26_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_27_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_28_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_29_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_30_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] io_out_s_31_bits = io_in_0;\t// @[RVC.scala:21:19, :190:7]\n wire [31:0] _io_out_T_64_bits;\t// @[package.scala:39:76]\n wire [4:0] _io_out_T_64_rd;\t// @[package.scala:39:76]\n wire [4:0] _io_out_T_64_rs1;\t// @[package.scala:39:76]\n wire [4:0] _io_out_T_64_rs2;\t// @[package.scala:39:76]\n wire [4:0] _io_out_T_64_rs3;\t// @[package.scala:39:76]\n wire _io_rvc_T_1;\t// @[RVC.scala:199:26]\n wire _io_ill_T_64;\t// @[package.scala:39:76]\n wire [31:0] io_out_bits_0;\t// @[RVC.scala:190:7]\n wire [4:0] io_out_rd;\t// @[RVC.scala:190:7]\n wire [4:0] io_out_rs1;\t// @[RVC.scala:190:7]\n wire [4:0] io_out_rs2;\t// @[RVC.scala:190:7]\n wire [4:0] io_out_rs3;\t// @[RVC.scala:190:7]\n wire io_rvc_0;\t// @[RVC.scala:190:7]\n wire io_ill;\t// @[RVC.scala:190:7]\n wire [1:0] _io_rvc_T = io_in_0[1:0];\t// @[RVC.scala:190:7, :199:20]\n wire [1:0] _io_out_T = io_in_0[1:0];\t// @[RVC.scala:154:12, :190:7, :199:20]\n wire [1:0] _io_ill_T = io_in_0[1:0];\t// @[RVC.scala:186:12, :190:7, :199:20]\n assign _io_rvc_T_1 = _io_rvc_T != 2'h3;\t// @[RVC.scala:199:{20,26}]\n assign io_rvc_0 = _io_rvc_T_1;\t// @[RVC.scala:190:7, :199:26]\n wire [7:0] _io_out_s_opc_T = io_in_0[12:5];\t// @[RVC.scala:53:22, :190:7]\n wire _io_out_s_opc_T_1 = |_io_out_s_opc_T;\t// @[RVC.scala:53:{22,29}]\n wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F;\t// @[RVC.scala:53:{20,29}]\n wire [3:0] _io_out_s_T = io_in_0[10:7];\t// @[RVC.scala:34:26, :190:7]\n wire [1:0] _io_out_s_T_1 = io_in_0[12:11];\t// @[RVC.scala:34:35, :190:7]\n wire _io_out_s_T_2 = io_in_0[5];\t// @[RVC.scala:34:45, :190:7]\n wire _io_out_s_T_28 = io_in_0[5];\t// @[RVC.scala:34:45, :35:20, :190:7]\n wire _io_out_s_T_59 = io_in_0[5];\t// @[RVC.scala:34:45, :35:20, :190:7]\n wire _io_out_s_T_68 = io_in_0[5];\t// @[RVC.scala:34:45, :35:20, :190:7]\n wire _io_out_s_T_101 = io_in_0[5];\t// @[RVC.scala:34:45, :35:20, :190:7]\n wire _io_out_s_T_110 = io_in_0[5];\t// @[RVC.scala:34:45, :35:20, :190:7]\n wire _io_out_s_T_185 = io_in_0[5];\t// @[RVC.scala:34:45, :42:50, :190:7]\n wire _io_out_s_T_3 = io_in_0[6];\t// @[RVC.scala:34:51, :190:7]\n wire _io_out_s_T_30 = io_in_0[6];\t// @[RVC.scala:34:51, :35:36, :190:7]\n wire _io_out_s_T_61 = io_in_0[6];\t// @[RVC.scala:34:51, :35:36, :190:7]\n wire _io_out_s_T_70 = io_in_0[6];\t// @[RVC.scala:34:51, :35:36, :190:7]\n wire _io_out_s_T_103 = io_in_0[6];\t// @[RVC.scala:34:51, :35:36, :190:7]\n wire _io_out_s_T_112 = io_in_0[6];\t// @[RVC.scala:34:51, :35:36, :190:7]\n wire _io_out_s_T_187 = io_in_0[6];\t// @[RVC.scala:34:51, :42:62, :190:7]\n wire _io_out_s_T_249 = io_in_0[6];\t// @[RVC.scala:34:51, :44:51, :190:7]\n wire _io_out_s_T_260 = io_in_0[6];\t// @[RVC.scala:34:51, :44:51, :190:7]\n wire _io_out_s_T_271 = io_in_0[6];\t// @[RVC.scala:34:51, :44:51, :190:7]\n wire _io_out_s_T_282 = io_in_0[6];\t// @[RVC.scala:34:51, :44:51, :190:7]\n wire _io_ill_s_T_9 = io_in_0[6];\t// @[RVC.scala:34:51, :169:69, :190:7]\n wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0};\t// @[RVC.scala:34:{24,51}]\n wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1};\t// @[RVC.scala:34:{24,26,35}]\n wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2};\t// @[RVC.scala:34:{24,45}]\n wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo};\t// @[RVC.scala:34:24]\n wire [2:0] _io_out_s_T_5 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_8 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_10 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_18 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_21 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_25 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_34 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_37 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_41 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_49 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_52 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_56 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_64 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_74 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_78 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_85 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_94 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_98 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_106 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_116 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_120 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_127 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_136 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_140 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_152 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_164 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_174 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_194 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_223 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_242 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_292 = io_in_0[4:2];\t// @[RVC.scala:31:29, :190:7]\n wire [2:0] _io_out_s_T_383 = io_in_0[4:2];\t// @[RVC.scala:31:29, :38:22, :190:7]\n wire [2:0] _io_out_s_T_401 = io_in_0[4:2];\t// @[RVC.scala:31:29, :38:22, :190:7]\n wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc};\t// @[RVC.scala:31:17, :53:20, :54:15]\n wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2};\t// @[package.scala:39:86]\n wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0};\t// @[RVC.scala:54:15]\n wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1};\t// @[RVC.scala:54:15]\n wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_0_rd = _io_out_s_T_9;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_12 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_27 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_43 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_58 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_80 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_100 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_122 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_142 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_154 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_166 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_176 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_196 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_244 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_294 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_334 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_372 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_382 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_391 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_400 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_409 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_423 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_436 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_449 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_453 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_457 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_461 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_465 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_469 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_473 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_477 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] _io_out_s_T_481 = io_in_0[31:27];\t// @[RVC.scala:20:101, :190:7]\n wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_0_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_0_bits = {2'h0, _io_out_s_T_7};\t// @[RVC.scala:21:19, :22:14, :54:15]\n wire [1:0] _io_out_s_T_13 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_T_44 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_T_81 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_T_89 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_T_123 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_T_131 = io_in_0[6:5];\t// @[RVC.scala:36:20, :190:7]\n wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5];\t// @[RVC.scala:36:20, :102:77, :190:7]\n wire [1:0] _io_out_s_sub_T = io_in_0[6:5];\t// @[RVC.scala:36:20, :103:24, :190:7]\n wire [1:0] _io_out_s_T_297 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_305 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_315 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_323 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_337 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_345 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_355 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_363 = io_in_0[6:5];\t// @[RVC.scala:36:20, :45:35, :190:7]\n wire [1:0] _io_out_s_T_385 = io_in_0[6:5];\t// @[RVC.scala:36:20, :38:37, :190:7]\n wire [1:0] _io_out_s_T_403 = io_in_0[6:5];\t// @[RVC.scala:36:20, :38:37, :190:7]\n wire [2:0] _io_out_s_T_14 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_29 = io_in_0[12:10];\t// @[RVC.scala:35:26, :36:28, :190:7]\n wire [2:0] _io_out_s_T_45 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_60 = io_in_0[12:10];\t// @[RVC.scala:35:26, :36:28, :190:7]\n wire [2:0] _io_out_s_T_69 = io_in_0[12:10];\t// @[RVC.scala:35:26, :36:28, :190:7]\n wire [2:0] _io_out_s_T_82 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_90 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_102 = io_in_0[12:10];\t// @[RVC.scala:35:26, :36:28, :190:7]\n wire [2:0] _io_out_s_T_111 = io_in_0[12:10];\t// @[RVC.scala:35:26, :36:28, :190:7]\n wire [2:0] _io_out_s_T_124 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_132 = io_in_0[12:10];\t// @[RVC.scala:36:28, :190:7]\n wire [2:0] _io_out_s_T_412 = io_in_0[12:10];\t// @[RVC.scala:36:28, :40:30, :190:7]\n wire [2:0] _io_out_s_T_417 = io_in_0[12:10];\t// @[RVC.scala:36:28, :40:30, :190:7]\n wire [2:0] _io_out_s_T_438 = io_in_0[12:10];\t// @[RVC.scala:36:28, :40:30, :190:7]\n wire [2:0] _io_out_s_T_443 = io_in_0[12:10];\t// @[RVC.scala:36:28, :40:30, :190:7]\n wire [2:0] _io_ill_s_T_7 = io_in_0[12:10];\t// @[RVC.scala:36:28, :169:22, :190:7]\n wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0};\t// @[RVC.scala:36:18]\n wire [2:0] _io_out_s_T_16 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_23 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_32 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_39 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_47 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_54 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_66 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_76 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_87 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_96 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_108 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_118 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_129 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_138 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_200 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_202 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_208 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_210 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_218 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_220 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_225 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_227 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_238 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_240 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_290 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_311 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_330 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_332 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_351 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_370 = io_in_0[9:7];\t// @[RVC.scala:30:29, :190:7]\n wire [2:0] _io_out_s_T_411 = io_in_0[9:7];\t// @[RVC.scala:30:29, :40:22, :190:7]\n wire [2:0] _io_out_s_T_416 = io_in_0[9:7];\t// @[RVC.scala:30:29, :40:22, :190:7]\n wire [2:0] _io_out_s_T_437 = io_in_0[9:7];\t// @[RVC.scala:30:29, :40:22, :190:7]\n wire [2:0] _io_out_s_T_442 = io_in_0[9:7];\t// @[RVC.scala:30:29, :40:22, :190:7]\n wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7};\t// @[RVC.scala:31:17, :58:23]\n wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17};\t// @[RVC.scala:30:17, :36:18, :58:23]\n wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3};\t// @[RVC.scala:58:23]\n wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2};\t// @[RVC.scala:58:23]\n wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_1_rd = _io_out_s_T_22;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_1_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_1_bits = {4'h0, _io_out_s_T_20};\t// @[RVC.scala:21:19, :22:14, :58:23]\n wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0};\t// @[RVC.scala:35:{18,36}]\n wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29};\t// @[RVC.scala:35:{18,20,26}]\n wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3};\t// @[RVC.scala:35:18]\n wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3};\t// @[RVC.scala:31:17, :57:22]\n wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33};\t// @[RVC.scala:30:17, :35:18, :57:22]\n wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2};\t// @[package.scala:39:86]\n wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4};\t// @[RVC.scala:57:22]\n wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_2_rd = _io_out_s_T_38;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_2_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_2_bits = {5'h0, _io_out_s_T_36};\t// @[RVC.scala:21:19, :22:14, :57:22]\n wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0};\t// @[RVC.scala:36:18]\n wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3};\t// @[RVC.scala:31:17, :56:22]\n wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48};\t// @[RVC.scala:30:17, :36:18, :56:22]\n wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3};\t// @[RVC.scala:56:22]\n wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5};\t// @[RVC.scala:56:22]\n wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_3_rd = _io_out_s_T_53;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_3_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_3_bits = {4'h0, _io_out_s_T_51};\t// @[RVC.scala:21:19, :22:14, :56:22]\n wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0};\t// @[RVC.scala:35:{18,36}]\n wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60};\t// @[RVC.scala:35:{18,20,26}]\n wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6};\t// @[RVC.scala:35:18]\n wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5];\t// @[RVC.scala:35:18, :63:32]\n wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66};\t// @[package.scala:39:86]\n wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0};\t// @[RVC.scala:35:{18,36}]\n wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69};\t// @[RVC.scala:35:{18,20,26}]\n wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7};\t// @[RVC.scala:35:18]\n wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0];\t// @[RVC.scala:35:18, :63:65]\n wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72};\t// @[package.scala:39:86]\n wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F};\t// @[RVC.scala:63:25]\n wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65};\t// @[RVC.scala:31:17, :63:{25,32}]\n wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67};\t// @[RVC.scala:30:17, :63:25]\n wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8};\t// @[RVC.scala:63:25]\n wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_4_rd = _io_out_s_T_75;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_4_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_4_bits = {5'h0, _io_out_s_T_73};\t// @[RVC.scala:21:19, :22:14, :63:25]\n wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0};\t// @[RVC.scala:36:18]\n wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5];\t// @[RVC.scala:36:18, :66:30]\n wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0};\t// @[RVC.scala:36:18]\n wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0];\t// @[RVC.scala:36:18, :66:63]\n wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92};\t// @[RVC.scala:66:{23,63}]\n wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27};\t// @[RVC.scala:66:23]\n wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86};\t// @[RVC.scala:31:17, :66:{23,30}]\n wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88};\t// @[RVC.scala:30:17, :66:23]\n wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9};\t// @[RVC.scala:66:23]\n wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_5_rd = _io_out_s_T_95;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_5_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_5_bits = {4'h0, _io_out_s_T_93};\t// @[RVC.scala:21:19, :22:14, :66:23]\n wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0};\t// @[RVC.scala:35:{18,36}]\n wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102};\t// @[RVC.scala:35:{18,20,26}]\n wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10};\t// @[RVC.scala:35:18]\n wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5];\t// @[RVC.scala:35:18, :65:29]\n wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108};\t// @[package.scala:39:86]\n wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0};\t// @[RVC.scala:35:{18,36}]\n wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111};\t// @[RVC.scala:35:{18,20,26}]\n wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11};\t// @[RVC.scala:35:18]\n wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0];\t// @[RVC.scala:35:18, :65:62]\n wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114};\t// @[package.scala:39:86]\n wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23};\t// @[RVC.scala:65:22]\n wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107};\t// @[RVC.scala:31:17, :65:{22,29}]\n wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109};\t// @[RVC.scala:30:17, :65:22]\n wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12};\t// @[RVC.scala:65:22]\n wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_6_rd = _io_out_s_T_117;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_6_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_6_bits = {5'h0, _io_out_s_T_115};\t// @[RVC.scala:21:19, :22:14, :65:22]\n wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0};\t// @[RVC.scala:36:18]\n wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5];\t// @[RVC.scala:36:18, :64:29]\n wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132};\t// @[RVC.scala:36:{18,20,28}]\n wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0};\t// @[RVC.scala:36:18]\n wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0];\t// @[RVC.scala:36:18, :64:62]\n wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134};\t// @[RVC.scala:64:{22,62}]\n wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23};\t// @[RVC.scala:64:22]\n wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128};\t// @[RVC.scala:31:17, :64:{22,29}]\n wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130};\t// @[RVC.scala:30:17, :64:22]\n wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13};\t// @[RVC.scala:64:22]\n wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_7_rd = _io_out_s_T_137;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_7_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_7_bits = {4'h0, _io_out_s_T_135};\t// @[RVC.scala:21:19, :22:14, :64:22]\n wire _io_out_s_T_143 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_T_155 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_T_167 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_opc_T_4 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_me_T = io_in_0[12];\t// @[RVC.scala:41:30, :43:30, :190:7]\n wire _io_out_s_opc_T_9 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_T_182 = io_in_0[12];\t// @[RVC.scala:42:34, :43:30, :190:7]\n wire _io_out_s_T_197 = io_in_0[12];\t// @[RVC.scala:43:30, :46:20, :190:7]\n wire _io_out_s_T_205 = io_in_0[12];\t// @[RVC.scala:43:30, :46:20, :190:7]\n wire _io_out_s_T_214 = io_in_0[12];\t// @[RVC.scala:43:30, :190:7]\n wire _io_out_s_funct_T = io_in_0[12];\t// @[RVC.scala:43:30, :102:70, :190:7]\n wire _io_out_s_opc_T_14 = io_in_0[12];\t// @[RVC.scala:43:30, :104:24, :190:7]\n wire _io_out_s_T_245 = io_in_0[12];\t// @[RVC.scala:43:30, :44:28, :190:7]\n wire _io_out_s_T_256 = io_in_0[12];\t// @[RVC.scala:43:30, :44:28, :190:7]\n wire _io_out_s_T_267 = io_in_0[12];\t// @[RVC.scala:43:30, :44:28, :190:7]\n wire _io_out_s_T_278 = io_in_0[12];\t// @[RVC.scala:43:30, :44:28, :190:7]\n wire _io_out_s_T_295 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_303 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_313 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_321 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_335 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_343 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_353 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_361 = io_in_0[12];\t// @[RVC.scala:43:30, :45:27, :190:7]\n wire _io_out_s_T_373 = io_in_0[12];\t// @[RVC.scala:43:30, :46:20, :190:7]\n wire _io_out_s_T_384 = io_in_0[12];\t// @[RVC.scala:38:30, :43:30, :190:7]\n wire _io_out_s_T_393 = io_in_0[12];\t// @[RVC.scala:37:30, :43:30, :190:7]\n wire _io_out_s_T_402 = io_in_0[12];\t// @[RVC.scala:38:30, :43:30, :190:7]\n wire _io_out_s_T_410 = io_in_0[12];\t// @[RVC.scala:43:30, :143:12, :190:7]\n wire _io_ill_s_T_3 = io_in_0[12];\t// @[RVC.scala:43:30, :168:19, :190:7]\n wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}};\t// @[RVC.scala:43:{25,30}]\n wire [4:0] _io_out_s_T_145 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_T_157 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_T_169 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2];\t// @[RVC.scala:41:38, :43:38, :190:7]\n wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_T_198 = io_in_0[6:2];\t// @[RVC.scala:43:38, :46:27, :190:7]\n wire [4:0] _io_out_s_T_206 = io_in_0[6:2];\t// @[RVC.scala:43:38, :46:27, :190:7]\n wire [4:0] _io_out_s_T_216 = io_in_0[6:2];\t// @[RVC.scala:43:38, :190:7]\n wire [4:0] _io_out_s_T_374 = io_in_0[6:2];\t// @[RVC.scala:43:38, :46:27, :190:7]\n wire [4:0] _io_out_s_T_381 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_390 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_399 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_408 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_mv_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_add_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jr_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jalr_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_415 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_422 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_428 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_435 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_441 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_out_s_T_448 = io_in_0[6:2];\t// @[RVC.scala:32:14, :43:38, :190:7]\n wire [4:0] _io_ill_s_T_4 = io_in_0[6:2];\t// @[RVC.scala:43:38, :168:27, :190:7]\n wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145};\t// @[RVC.scala:43:{20,25,38}]\n wire [4:0] _io_out_s_T_147 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_148 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_150 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_151 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_159 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_160 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_162 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_163 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_171 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_173 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_177 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_179 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_189 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_190 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_192 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_193 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_376 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_377 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_379 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_380 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_387 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_389 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_396 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_398 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_405 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_407 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_421 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_434 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_447 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_out_s_T_450 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_454 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_458 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_462 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_466 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_470 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_474 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_out_s_T_478 = io_in_0[11:7];\t// @[RVC.scala:20:36, :33:13, :190:7]\n wire [4:0] _io_ill_s_T_2 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_ill_s_T_11 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [4:0] _io_ill_s_T_12 = io_in_0[11:7];\t// @[RVC.scala:33:13, :190:7]\n wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13};\t// @[RVC.scala:33:13, :75:24]\n wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147};\t// @[RVC.scala:33:13, :43:20, :75:24]\n wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0};\t// @[RVC.scala:75:24]\n wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14};\t// @[RVC.scala:75:24]\n wire [31:0] io_out_s_8_bits = _io_out_s_T_149;\t// @[RVC.scala:21:19, :75:24]\n wire [4:0] io_out_s_8_rd = _io_out_s_T_150;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154;\t// @[RVC.scala:20:101, :21:19]\n wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2;\t// @[RVC.scala:33:13, :77:24]\n wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3};\t// @[RVC.scala:77:{20,24}]\n wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}};\t// @[RVC.scala:43:{25,30}]\n wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157};\t// @[RVC.scala:43:{20,25,38}]\n wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1};\t// @[RVC.scala:33:13, :77:20, :78:15]\n wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159};\t// @[RVC.scala:33:13, :43:20, :78:15]\n wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0};\t// @[RVC.scala:78:15]\n wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15};\t// @[RVC.scala:78:15]\n wire [31:0] io_out_s_9_bits = _io_out_s_T_161;\t// @[RVC.scala:21:19, :78:15]\n wire [4:0] io_out_s_9_rd = _io_out_s_T_162;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166;\t// @[RVC.scala:20:101, :21:19]\n wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}};\t// @[RVC.scala:43:{25,30}]\n wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169};\t// @[RVC.scala:43:{20,25,38}]\n wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13};\t// @[RVC.scala:33:13, :84:22]\n wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0};\t// @[RVC.scala:43:20, :84:22]\n wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0};\t// @[RVC.scala:84:22]\n wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16};\t// @[RVC.scala:84:22]\n wire [31:0] io_out_s_10_bits = _io_out_s_T_172;\t// @[RVC.scala:21:19, :84:22]\n wire [4:0] io_out_s_10_rd = _io_out_s_T_173;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176;\t// @[RVC.scala:20:101, :21:19]\n wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}};\t// @[RVC.scala:43:{25,30}]\n wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6};\t// @[RVC.scala:43:{20,25,38}]\n wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7;\t// @[RVC.scala:43:20, :90:29]\n wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7};\t// @[RVC.scala:90:{20,29}]\n wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}};\t// @[RVC.scala:41:{24,30}]\n wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2};\t// @[RVC.scala:41:{19,24,38}]\n wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0};\t// @[RVC.scala:41:19]\n wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12];\t// @[RVC.scala:41:19, :91:31]\n wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5};\t// @[RVC.scala:33:13, :91:{24,31}]\n wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2};\t// @[RVC.scala:90:20, :91:24]\n wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6;\t// @[RVC.scala:21:19, :91:24]\n wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11;\t// @[RVC.scala:20:101, :21:19]\n wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0;\t// @[RVC.scala:33:13, :92:14]\n wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2;\t// @[package.scala:39:86]\n wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180;\t// @[RVC.scala:92:{14,21,27}]\n wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}};\t// @[RVC.scala:43:{25,30}]\n wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11};\t// @[RVC.scala:43:{20,25,38}]\n wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12;\t// @[RVC.scala:43:20, :86:29]\n wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F;\t// @[RVC.scala:86:{20,29}]\n wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}};\t// @[RVC.scala:42:{29,34}]\n wire [1:0] _io_out_s_T_184 = io_in_0[4:3];\t// @[RVC.scala:42:42, :190:7]\n wire [1:0] _io_out_s_T_300 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_308 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_318 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_326 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_340 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_348 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_358 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire [1:0] _io_out_s_T_366 = io_in_0[4:3];\t// @[RVC.scala:42:42, :45:59, :190:7]\n wire _io_out_s_T_186 = io_in_0[2];\t// @[RVC.scala:42:56, :190:7]\n wire _io_out_s_T_251 = io_in_0[2];\t// @[RVC.scala:42:56, :44:63, :190:7]\n wire _io_out_s_T_262 = io_in_0[2];\t// @[RVC.scala:42:56, :44:63, :190:7]\n wire _io_out_s_T_273 = io_in_0[2];\t// @[RVC.scala:42:56, :44:63, :190:7]\n wire _io_out_s_T_284 = io_in_0[2];\t// @[RVC.scala:42:56, :44:63, :190:7]\n wire _io_out_s_T_298 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_306 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_316 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_324 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_338 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_346 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_356 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire _io_out_s_T_364 = io_in_0[2];\t// @[RVC.scala:42:56, :45:43, :190:7]\n wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187};\t// @[RVC.scala:42:{24,56,62}]\n wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0};\t// @[RVC.scala:42:24]\n wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184};\t// @[RVC.scala:42:{24,29,42}]\n wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185};\t// @[RVC.scala:42:{24,50}]\n wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17};\t// @[RVC.scala:42:24]\n wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3};\t// @[RVC.scala:33:13, :86:20, :87:15]\n wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189};\t// @[RVC.scala:33:13, :42:24, :87:15]\n wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0};\t// @[RVC.scala:87:15]\n wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18};\t// @[RVC.scala:87:15]\n wire [31:0] io_out_s_res_bits = _io_out_s_T_191;\t// @[RVC.scala:21:19, :87:15]\n wire [4:0] io_out_s_res_rd = _io_out_s_T_192;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits;\t// @[RVC.scala:21:19, :92:{10,21}]\n wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd;\t// @[RVC.scala:21:19, :92:{10,21}]\n wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1;\t// @[RVC.scala:21:19, :92:{10,21}]\n wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2;\t// @[RVC.scala:21:19, :92:{10,21}]\n wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3;\t// @[RVC.scala:21:19, :92:{10,21}]\n wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198};\t// @[RVC.scala:46:{18,20,27}]\n wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13};\t// @[RVC.scala:30:17, :98:21]\n wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201};\t// @[RVC.scala:30:17, :46:18, :98:21]\n wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5};\t// @[RVC.scala:98:21]\n wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19};\t// @[RVC.scala:98:21]\n wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206};\t// @[RVC.scala:46:{18,20,27}]\n wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13};\t// @[RVC.scala:30:17, :98:21]\n wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209};\t// @[RVC.scala:30:17, :46:18, :98:21]\n wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5};\t// @[RVC.scala:98:21]\n wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20};\t// @[RVC.scala:98:21]\n wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212};\t// @[RVC.scala:98:21, :99:23]\n wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}};\t// @[RVC.scala:43:{25,30}]\n wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216};\t// @[RVC.scala:43:{20,25,38}]\n wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13};\t// @[RVC.scala:30:17, :100:21]\n wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219};\t// @[RVC.scala:30:17, :43:20, :100:21]\n wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7};\t// @[RVC.scala:100:21]\n wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21};\t// @[RVC.scala:100:21]\n wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1};\t// @[RVC.scala:102:{68,70,77}]\n wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0};\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6;\t// @[package.scala:39:86]\n wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2;\t// @[package.scala:39:86]\n wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14;\t// @[package.scala:39:{76,86}]\n wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0;\t// @[RVC.scala:103:{24,30}]\n wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0};\t// @[RVC.scala:103:{22,30}]\n wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3};\t// @[RVC.scala:104:{22,24}]\n wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227};\t// @[package.scala:39:86]\n wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4};\t// @[RVC.scala:30:17, :104:22, :105:12]\n wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226};\t// @[RVC.scala:30:17, :31:17, :105:12]\n wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct};\t// @[package.scala:39:76]\n wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22};\t// @[RVC.scala:105:12]\n wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub;\t// @[RVC.scala:103:22, :105:{12,43}]\n wire [1:0] _io_out_s_T_231 = io_in_0[11:10];\t// @[RVC.scala:107:42, :190:7]\n wire [1:0] _io_out_s_T_299 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_307 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_317 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_325 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_339 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_347 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_357 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire [1:0] _io_out_s_T_365 = io_in_0[11:10];\t// @[RVC.scala:45:49, :107:42, :190:7]\n wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1;\t// @[package.scala:39:86]\n wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204};\t// @[package.scala:39:{76,86}]\n wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2;\t// @[package.scala:39:86]\n wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233};\t// @[package.scala:39:{76,86}]\n wire _io_out_s_T_236 = &_io_out_s_T_231;\t// @[package.scala:39:86]\n wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235;\t// @[package.scala:39:{76,86}]\n wire [31:0] io_out_s_12_bits = _io_out_s_T_237;\t// @[package.scala:39:76]\n wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_12_rd = _io_out_s_T_239;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244;\t// @[RVC.scala:20:101, :21:19]\n wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}};\t// @[RVC.scala:44:{22,28}]\n wire _io_out_s_T_247 = io_in_0[8];\t// @[RVC.scala:44:36, :190:7]\n wire _io_out_s_T_258 = io_in_0[8];\t// @[RVC.scala:44:36, :190:7]\n wire _io_out_s_T_269 = io_in_0[8];\t// @[RVC.scala:44:36, :190:7]\n wire _io_out_s_T_280 = io_in_0[8];\t// @[RVC.scala:44:36, :190:7]\n wire [1:0] _io_out_s_T_248 = io_in_0[10:9];\t// @[RVC.scala:44:42, :190:7]\n wire [1:0] _io_out_s_T_259 = io_in_0[10:9];\t// @[RVC.scala:44:42, :190:7]\n wire [1:0] _io_out_s_T_270 = io_in_0[10:9];\t// @[RVC.scala:44:42, :190:7]\n wire [1:0] _io_out_s_T_281 = io_in_0[10:9];\t// @[RVC.scala:44:42, :190:7]\n wire _io_out_s_T_250 = io_in_0[7];\t// @[RVC.scala:44:57, :190:7]\n wire _io_out_s_T_261 = io_in_0[7];\t// @[RVC.scala:44:57, :190:7]\n wire _io_out_s_T_272 = io_in_0[7];\t// @[RVC.scala:44:57, :190:7]\n wire _io_out_s_T_283 = io_in_0[7];\t// @[RVC.scala:44:57, :190:7]\n wire _io_out_s_T_252 = io_in_0[11];\t// @[RVC.scala:44:69, :190:7]\n wire _io_out_s_T_263 = io_in_0[11];\t// @[RVC.scala:44:69, :190:7]\n wire _io_out_s_T_274 = io_in_0[11];\t// @[RVC.scala:44:69, :190:7]\n wire _io_out_s_T_285 = io_in_0[11];\t// @[RVC.scala:44:69, :190:7]\n wire [2:0] _io_out_s_T_253 = io_in_0[5:3];\t// @[RVC.scala:44:76, :190:7]\n wire [2:0] _io_out_s_T_264 = io_in_0[5:3];\t// @[RVC.scala:44:76, :190:7]\n wire [2:0] _io_out_s_T_275 = io_in_0[5:3];\t// @[RVC.scala:44:76, :190:7]\n wire [2:0] _io_out_s_T_286 = io_in_0[5:3];\t// @[RVC.scala:44:76, :190:7]\n wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0};\t// @[RVC.scala:44:{17,76}]\n wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252};\t// @[RVC.scala:44:{17,63,69}]\n wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo};\t// @[RVC.scala:44:17]\n wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250};\t// @[RVC.scala:44:{17,51,57}]\n wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247};\t// @[RVC.scala:44:{17,22,36}]\n wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248};\t// @[RVC.scala:44:{17,42}]\n wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo};\t// @[RVC.scala:44:17]\n wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23};\t// @[RVC.scala:44:17]\n wire _io_out_s_T_255 = _io_out_s_T_254[20];\t// @[RVC.scala:44:17, :94:26]\n wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}};\t// @[RVC.scala:44:{22,28}]\n wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0};\t// @[RVC.scala:44:{17,76}]\n wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263};\t// @[RVC.scala:44:{17,63,69}]\n wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1};\t// @[RVC.scala:44:17]\n wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261};\t// @[RVC.scala:44:{17,51,57}]\n wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258};\t// @[RVC.scala:44:{17,22,36}]\n wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259};\t// @[RVC.scala:44:{17,42}]\n wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1};\t// @[RVC.scala:44:17]\n wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24};\t// @[RVC.scala:44:17]\n wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1];\t// @[RVC.scala:44:17, :94:36]\n wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}};\t// @[RVC.scala:44:{22,28}]\n wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0};\t// @[RVC.scala:44:{17,76}]\n wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274};\t// @[RVC.scala:44:{17,63,69}]\n wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2};\t// @[RVC.scala:44:17]\n wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272};\t// @[RVC.scala:44:{17,51,57}]\n wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269};\t// @[RVC.scala:44:{17,22,36}]\n wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270};\t// @[RVC.scala:44:{17,42}]\n wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2};\t// @[RVC.scala:44:17]\n wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25};\t// @[RVC.scala:44:17]\n wire _io_out_s_T_277 = _io_out_s_T_276[11];\t// @[RVC.scala:44:17, :94:48]\n wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}};\t// @[RVC.scala:44:{22,28}]\n wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0};\t// @[RVC.scala:44:{17,76}]\n wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285};\t// @[RVC.scala:44:{17,63,69}]\n wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3};\t// @[RVC.scala:44:17]\n wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283};\t// @[RVC.scala:44:{17,51,57}]\n wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280};\t// @[RVC.scala:44:{17,22,36}]\n wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281};\t// @[RVC.scala:44:{17,42}]\n wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3};\t// @[RVC.scala:44:17]\n wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26};\t// @[RVC.scala:44:17]\n wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12];\t// @[RVC.scala:44:17, :94:58]\n wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0};\t// @[RVC.scala:94:{21,58}]\n wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F};\t// @[RVC.scala:94:21]\n wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266};\t// @[RVC.scala:94:{21,26,36}]\n wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277};\t// @[RVC.scala:94:{21,48}]\n wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27};\t// @[RVC.scala:94:21]\n wire [31:0] io_out_s_13_bits = _io_out_s_T_289;\t// @[RVC.scala:21:19, :94:21]\n wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293;\t// @[RVC.scala:21:19, :31:17]\n wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28};\t// @[RVC.scala:45:17]\n wire _io_out_s_T_302 = _io_out_s_T_301[12];\t// @[RVC.scala:45:17, :95:29]\n wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29};\t// @[RVC.scala:45:17]\n wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5];\t// @[RVC.scala:45:17, :95:39]\n wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30};\t// @[RVC.scala:45:17]\n wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1];\t// @[RVC.scala:45:17, :95:71]\n wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31};\t// @[RVC.scala:45:17]\n wire _io_out_s_T_328 = _io_out_s_T_327[11];\t// @[RVC.scala:45:17, :95:82]\n wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63};\t// @[RVC.scala:95:{24,82}]\n wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320};\t// @[RVC.scala:95:{24,71}]\n wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4};\t// @[RVC.scala:95:24]\n wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312};\t// @[RVC.scala:30:17, :95:24]\n wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310};\t// @[RVC.scala:95:{24,29,39}]\n wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4};\t// @[RVC.scala:95:24]\n wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32};\t// @[RVC.scala:95:24]\n wire [31:0] io_out_s_14_bits = _io_out_s_T_329;\t// @[RVC.scala:21:19, :95:24]\n wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_14_rd = _io_out_s_T_331;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33};\t// @[RVC.scala:45:17]\n wire _io_out_s_T_342 = _io_out_s_T_341[12];\t// @[RVC.scala:45:17, :96:29]\n wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34};\t// @[RVC.scala:45:17]\n wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5];\t// @[RVC.scala:45:17, :96:39]\n wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351};\t// @[package.scala:39:86]\n wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35};\t// @[RVC.scala:45:17]\n wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1];\t// @[RVC.scala:45:17, :96:71]\n wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}};\t// @[RVC.scala:45:{22,27}]\n wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366};\t// @[RVC.scala:45:{17,49,59}]\n wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0};\t// @[RVC.scala:45:17]\n wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363};\t// @[RVC.scala:45:{17,22,35}]\n wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364};\t// @[RVC.scala:45:{17,43}]\n wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36};\t// @[RVC.scala:45:17]\n wire _io_out_s_T_368 = _io_out_s_T_367[11];\t// @[RVC.scala:45:17, :96:82]\n wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63};\t// @[RVC.scala:96:{24,82}]\n wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360};\t// @[package.scala:39:86]\n wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5};\t// @[RVC.scala:96:24]\n wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352};\t// @[RVC.scala:30:17, :96:24]\n wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350};\t// @[RVC.scala:96:{24,29,39}]\n wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5};\t// @[RVC.scala:96:24]\n wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37};\t// @[RVC.scala:96:24]\n wire [31:0] io_out_s_15_bits = _io_out_s_T_369;\t// @[RVC.scala:21:19, :96:24]\n wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370};\t// @[package.scala:39:86]\n wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371;\t// @[RVC.scala:21:19, :30:17]\n wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372;\t// @[RVC.scala:20:101, :21:19]\n wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T;\t// @[RVC.scala:33:13, :113:27]\n wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F;\t// @[RVC.scala:113:{23,27}]\n wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374};\t// @[RVC.scala:46:{18,20,27}]\n wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13};\t// @[RVC.scala:33:13, :114:24]\n wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376};\t// @[RVC.scala:33:13, :46:18, :114:24]\n wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1};\t// @[package.scala:39:86]\n wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38};\t// @[RVC.scala:114:24]\n wire [4:0] io_out_s_16_rd = _io_out_s_T_379;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_16_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_16_bits = {6'h0, _io_out_s_T_378};\t// @[RVC.scala:21:19, :22:14, :105:43, :114:24]\n wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0};\t// @[RVC.scala:38:{20,37}]\n wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384};\t// @[RVC.scala:38:{20,22,30}]\n wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39};\t// @[RVC.scala:38:20]\n wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7};\t// @[RVC.scala:33:13, :117:25]\n wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2};\t// @[package.scala:39:86]\n wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3};\t// @[RVC.scala:117:25]\n wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40};\t// @[RVC.scala:117:25]\n wire [4:0] io_out_s_17_rd = _io_out_s_T_389;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_17_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_17_bits = {3'h0, _io_out_s_T_388};\t// @[RVC.scala:21:19, :22:14, :117:25]\n wire [1:0] _io_out_s_T_392 = io_in_0[3:2];\t// @[RVC.scala:37:22, :190:7]\n wire [2:0] _io_out_s_T_394 = io_in_0[6:4];\t// @[RVC.scala:37:37, :190:7]\n wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0};\t// @[RVC.scala:37:{20,37}]\n wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393};\t// @[RVC.scala:37:{20,22,30}]\n wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41};\t// @[RVC.scala:37:20]\n wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc};\t// @[RVC.scala:33:13, :113:23, :116:24]\n wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2};\t// @[package.scala:39:86]\n wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2};\t// @[package.scala:39:86]\n wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42};\t// @[RVC.scala:116:24]\n wire [4:0] io_out_s_18_rd = _io_out_s_T_398;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_18_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_18_bits = {4'h0, _io_out_s_T_397};\t// @[RVC.scala:21:19, :22:14, :116:24]\n wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0};\t// @[RVC.scala:38:{20,37}]\n wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402};\t// @[RVC.scala:38:{20,22,30}]\n wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43};\t// @[RVC.scala:38:20]\n wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc};\t// @[RVC.scala:33:13, :113:23, :115:24]\n wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2};\t// @[package.scala:39:86]\n wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3};\t// @[RVC.scala:115:24]\n wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44};\t// @[RVC.scala:115:24]\n wire [4:0] io_out_s_19_rd = _io_out_s_T_407;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_19_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_19_bits = {3'h0, _io_out_s_T_406};\t// @[RVC.scala:21:19, :22:14, :115:24]\n wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33};\t// @[RVC.scala:33:13, :132:22]\n wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0};\t// @[RVC.scala:32:14, :132:22]\n wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0};\t// @[RVC.scala:132:22]\n wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo};\t// @[RVC.scala:132:22]\n wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_mv_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2};\t// @[RVC.scala:21:19, :22:14, :132:22]\n wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33};\t// @[RVC.scala:33:13, :134:25]\n wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1};\t// @[RVC.scala:32:14, :33:13, :134:25]\n wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0};\t// @[RVC.scala:134:25]\n wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo};\t// @[RVC.scala:134:25]\n wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_add_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3};\t// @[RVC.scala:21:19, :22:14, :134:25]\n wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1};\t// @[RVC.scala:32:14, :33:13, :135:19]\n wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0};\t// @[RVC.scala:135:19]\n wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67};\t// @[RVC.scala:135:19]\n wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7];\t// @[RVC.scala:135:19, :136:29]\n wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7];\t// @[RVC.scala:135:19, :136:29, :140:27]\n wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F};\t// @[RVC.scala:136:{25,29}]\n wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T;\t// @[RVC.scala:33:13, :137:37]\n wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved;\t// @[RVC.scala:135:19, :136:25, :137:{33,37}]\n wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_jr_reserved_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2};\t// @[RVC.scala:21:19, :22:14, :137:33]\n wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T;\t// @[RVC.scala:32:14, :138:27]\n wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits;\t// @[RVC.scala:21:19, :138:{22,27}]\n wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0;\t// @[RVC.scala:21:19, :138:{22,27}]\n wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1;\t// @[RVC.scala:21:19, :138:{22,27}]\n wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2;\t// @[RVC.scala:21:19, :138:{22,27}]\n wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3;\t// @[RVC.scala:21:19, :138:{22,27}]\n wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1};\t// @[RVC.scala:32:14, :33:13, :139:21]\n wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0};\t// @[RVC.scala:139:21]\n wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7};\t// @[RVC.scala:139:21]\n wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73};\t// @[RVC.scala:140:{23,27}]\n wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000};\t// @[RVC.scala:140:{23,46}]\n wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T;\t// @[RVC.scala:33:13, :141:37]\n wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak;\t// @[RVC.scala:139:21, :140:46, :141:{33,37}]\n wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_jalr_ebreak_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2};\t// @[RVC.scala:21:19, :22:14, :141:33]\n wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T;\t// @[RVC.scala:32:14, :142:30]\n wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits;\t// @[RVC.scala:21:19, :142:{25,30}]\n wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1;\t// @[package.scala:39:86]\n wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1;\t// @[RVC.scala:21:19, :142:{25,30}]\n wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2;\t// @[RVC.scala:21:19, :142:{25,30}]\n wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3;\t// @[RVC.scala:21:19, :142:{25,30}]\n wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits;\t// @[RVC.scala:138:22, :142:25, :143:{10,12}]\n wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd;\t// @[RVC.scala:138:22, :142:25, :143:{10,12}]\n wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1;\t// @[RVC.scala:138:22, :142:25, :143:{10,12}]\n wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2;\t// @[RVC.scala:138:22, :142:25, :143:{10,12}]\n wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3;\t// @[RVC.scala:138:22, :142:25, :143:{10,12}]\n wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412};\t// @[RVC.scala:40:{20,22,30}]\n wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0};\t// @[RVC.scala:40:20]\n wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5];\t// @[RVC.scala:40:20, :124:34]\n wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417};\t// @[RVC.scala:40:{20,22,30}]\n wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0};\t// @[RVC.scala:40:20]\n wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0];\t// @[RVC.scala:40:20, :124:66]\n wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419};\t// @[RVC.scala:124:{25,66}]\n wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27};\t// @[RVC.scala:124:25]\n wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415};\t// @[RVC.scala:32:14, :124:{25,34}]\n wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2};\t// @[package.scala:39:86]\n wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45};\t// @[RVC.scala:124:25]\n wire [4:0] io_out_s_21_rd = _io_out_s_T_421;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_21_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_21_bits = {3'h0, _io_out_s_T_420};\t// @[RVC.scala:21:19, :22:14, :124:25]\n wire [1:0] _io_out_s_T_424 = io_in_0[8:7];\t// @[RVC.scala:39:22, :190:7]\n wire [1:0] _io_out_s_T_429 = io_in_0[8:7];\t// @[RVC.scala:39:22, :190:7]\n wire [3:0] _io_out_s_T_425 = io_in_0[12:9];\t// @[RVC.scala:39:30, :190:7]\n wire [3:0] _io_out_s_T_430 = io_in_0[12:9];\t// @[RVC.scala:39:30, :190:7]\n wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425};\t// @[RVC.scala:39:{20,22,30}]\n wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0};\t// @[RVC.scala:39:20]\n wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5];\t// @[RVC.scala:39:20, :123:33]\n wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430};\t// @[RVC.scala:39:{20,22,30}]\n wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0};\t// @[RVC.scala:39:20]\n wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0];\t// @[RVC.scala:39:20, :123:65]\n wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432};\t// @[package.scala:39:86]\n wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23};\t// @[RVC.scala:123:24]\n wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428};\t// @[RVC.scala:32:14, :123:{24,33}]\n wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2};\t// @[package.scala:39:86]\n wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46};\t// @[RVC.scala:123:24]\n wire [4:0] io_out_s_22_rd = _io_out_s_T_434;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_22_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_22_bits = {4'h0, _io_out_s_T_433};\t// @[RVC.scala:21:19, :22:14, :123:24]\n wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438};\t// @[RVC.scala:40:{20,22,30}]\n wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0};\t// @[RVC.scala:40:20]\n wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5];\t// @[RVC.scala:40:20, :122:33]\n wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443};\t// @[RVC.scala:40:{20,22,30}]\n wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0};\t// @[RVC.scala:40:20]\n wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0];\t// @[RVC.scala:40:20, :122:65]\n wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445};\t// @[RVC.scala:122:{24,65}]\n wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23};\t// @[RVC.scala:122:24]\n wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441};\t// @[RVC.scala:32:14, :122:{24,33}]\n wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2};\t// @[package.scala:39:86]\n wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47};\t// @[RVC.scala:122:24]\n wire [4:0] io_out_s_23_rd = _io_out_s_T_447;\t// @[RVC.scala:21:19, :33:13]\n wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448;\t// @[RVC.scala:21:19, :32:14]\n wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449;\t// @[RVC.scala:20:101, :21:19]\n wire [31:0] io_out_s_23_bits;\t// @[RVC.scala:21:19]\n assign io_out_s_23_bits = {3'h0, _io_out_s_T_446};\t// @[RVC.scala:21:19, :22:14, :122:24]\n wire [4:0] io_out_s_24_rd = _io_out_s_T_450;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] _io_out_s_T_451 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_455 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_459 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_463 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_467 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_471 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_475 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] _io_out_s_T_479 = io_in_0[19:15];\t// @[RVC.scala:20:57, :190:7]\n wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] _io_out_s_T_452 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_456 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_460 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_464 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_468 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_472 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_476 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] _io_out_s_T_480 = io_in_0[24:20];\t// @[RVC.scala:20:79, :190:7]\n wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_25_rd = _io_out_s_T_454;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_26_rd = _io_out_s_T_458;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_27_rd = _io_out_s_T_462;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_28_rd = _io_out_s_T_466;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_29_rd = _io_out_s_T_470;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_30_rd = _io_out_s_T_474;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477;\t// @[RVC.scala:20:101, :21:19]\n wire [4:0] io_out_s_31_rd = _io_out_s_T_478;\t// @[RVC.scala:20:36, :21:19]\n wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479;\t// @[RVC.scala:20:57, :21:19]\n wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480;\t// @[RVC.scala:20:79, :21:19]\n wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481;\t// @[RVC.scala:20:101, :21:19]\n wire [2:0] _io_out_T_1 = io_in_0[15:13];\t// @[RVC.scala:154:20, :190:7]\n wire [2:0] _io_ill_T_1 = io_in_0[15:13];\t// @[RVC.scala:154:20, :186:20, :190:7]\n wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1};\t// @[RVC.scala:154:{10,12,20}]\n wire _io_out_T_3 = _io_out_T_2 == 5'h1;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_5 = _io_out_T_2 == 5'h2;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_7 = _io_out_T_2 == 5'h3;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_9 = _io_out_T_2 == 5'h4;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_11 = _io_out_T_2 == 5'h5;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_13 = _io_out_T_2 == 5'h6;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_15 = _io_out_T_2 == 5'h7;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_17 = _io_out_T_2 == 5'h8;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_19 = _io_out_T_2 == 5'h9;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_21 = _io_out_T_2 == 5'hA;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_23 = _io_out_T_2 == 5'hB;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_25 = _io_out_T_2 == 5'hC;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_27 = _io_out_T_2 == 5'hD;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_29 = _io_out_T_2 == 5'hE;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_31 = _io_out_T_2 == 5'hF;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_33 = _io_out_T_2 == 5'h10;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_35 = _io_out_T_2 == 5'h11;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_37 = _io_out_T_2 == 5'h12;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_39 = _io_out_T_2 == 5'h13;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_41 = _io_out_T_2 == 5'h14;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_43 = _io_out_T_2 == 5'h15;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_45 = _io_out_T_2 == 5'h16;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_47 = _io_out_T_2 == 5'h17;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_49 = _io_out_T_2 == 5'h18;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_51 = _io_out_T_2 == 5'h19;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_53 = _io_out_T_2 == 5'h1A;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_55 = _io_out_T_2 == 5'h1B;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_57 = _io_out_T_2 == 5'h1C;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_59 = _io_out_T_2 == 5'h1D;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_61 = _io_out_T_2 == 5'h1E;\t// @[package.scala:39:86]\n wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2;\t// @[package.scala:39:{76,86}]\n wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3;\t// @[package.scala:39:{76,86}]\n wire _io_out_T_63 = &_io_out_T_2;\t// @[package.scala:39:86]\n assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits;\t// @[package.scala:39:{76,86}]\n assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd;\t// @[package.scala:39:{76,86}]\n assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1;\t// @[package.scala:39:{76,86}]\n assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2;\t// @[package.scala:39:{76,86}]\n assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3;\t// @[package.scala:39:{76,86}]\n assign io_out_bits_0 = _io_out_T_64_bits;\t// @[package.scala:39:76]\n assign io_out_rd = _io_out_T_64_rd;\t// @[package.scala:39:76]\n assign io_out_rs1 = _io_out_T_64_rs1;\t// @[package.scala:39:76]\n assign io_out_rs2 = _io_out_T_64_rs2;\t// @[package.scala:39:76]\n assign io_out_rs3 = _io_out_T_64_rs3;\t// @[package.scala:39:76]\n wire [10:0] _io_ill_s_T = io_in_0[12:2];\t// @[RVC.scala:158:19, :190:7]\n wire [10:0] _io_ill_s_T_13 = io_in_0[12:2];\t// @[RVC.scala:158:19, :177:21, :190:7]\n wire _io_ill_s_T_1 = |_io_ill_s_T;\t// @[RVC.scala:158:{19,27}]\n wire io_ill_s_0 = ~_io_ill_s_T_1;\t// @[RVC.scala:158:{16,27}]\n wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0;\t// @[RVC.scala:33:13, :167:47]\n wire _io_ill_s_T_5 = |_io_ill_s_T_4;\t// @[RVC.scala:168:{27,34}]\n wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5;\t// @[RVC.scala:168:{19,24,34}]\n wire io_ill_s_11 = ~_io_ill_s_T_6;\t// @[RVC.scala:168:{16,24}]\n wire _io_ill_s_T_8 = &_io_ill_s_T_7;\t// @[RVC.scala:169:{22,31}]\n wire _io_ill_s_T_10 = _io_ill_s_T_9;\t// @[RVC.scala:169:{69,73}]\n wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10;\t// @[RVC.scala:169:{31,36,73}]\n wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0;\t// @[RVC.scala:33:13, :175:18]\n wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0;\t// @[RVC.scala:33:13, :175:18]\n wire _io_ill_s_T_14 = |_io_ill_s_T_13;\t// @[RVC.scala:177:{21,29}]\n wire io_ill_s_20 = ~_io_ill_s_T_14;\t// @[RVC.scala:177:{18,29}]\n wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1};\t// @[RVC.scala:186:{10,12,20}]\n wire _io_ill_T_3 = _io_ill_T_2 == 5'h1;\t// @[package.scala:39:86]\n wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_5 = _io_ill_T_2 == 5'h2;\t// @[package.scala:39:86]\n wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_7 = _io_ill_T_2 == 5'h3;\t// @[package.scala:39:86]\n wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_9 = _io_ill_T_2 == 5'h4;\t// @[package.scala:39:86]\n wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_11 = _io_ill_T_2 == 5'h5;\t// @[package.scala:39:86]\n wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_13 = _io_ill_T_2 == 5'h6;\t// @[package.scala:39:86]\n wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_15 = _io_ill_T_2 == 5'h7;\t// @[package.scala:39:86]\n wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_17 = _io_ill_T_2 == 5'h8;\t// @[package.scala:39:86]\n wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_19 = _io_ill_T_2 == 5'h9;\t// @[package.scala:39:86]\n wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_21 = _io_ill_T_2 == 5'hA;\t// @[package.scala:39:86]\n wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_23 = _io_ill_T_2 == 5'hB;\t// @[package.scala:39:86]\n wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_25 = _io_ill_T_2 == 5'hC;\t// @[package.scala:39:86]\n wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_27 = _io_ill_T_2 == 5'hD;\t// @[package.scala:39:86]\n wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_29 = _io_ill_T_2 == 5'hE;\t// @[package.scala:39:86]\n wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_31 = _io_ill_T_2 == 5'hF;\t// @[package.scala:39:86]\n wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_33 = _io_ill_T_2 == 5'h10;\t// @[package.scala:39:86]\n wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_35 = _io_ill_T_2 == 5'h11;\t// @[package.scala:39:86]\n wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_37 = _io_ill_T_2 == 5'h12;\t// @[package.scala:39:86]\n wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_39 = _io_ill_T_2 == 5'h13;\t// @[package.scala:39:86]\n wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_41 = _io_ill_T_2 == 5'h14;\t// @[package.scala:39:86]\n wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_43 = _io_ill_T_2 == 5'h15;\t// @[package.scala:39:86]\n wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_45 = _io_ill_T_2 == 5'h16;\t// @[package.scala:39:86]\n wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_47 = _io_ill_T_2 == 5'h17;\t// @[package.scala:39:86]\n wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_49 = _io_ill_T_2 == 5'h18;\t// @[package.scala:39:86]\n wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_51 = _io_ill_T_2 == 5'h19;\t// @[package.scala:39:86]\n wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A;\t// @[package.scala:39:86]\n wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B;\t// @[package.scala:39:86]\n wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C;\t// @[package.scala:39:86]\n wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D;\t// @[package.scala:39:86]\n wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E;\t// @[package.scala:39:86]\n wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60;\t// @[package.scala:39:{76,86}]\n wire _io_ill_T_63 = &_io_ill_T_2;\t// @[package.scala:39:86]\n assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62;\t// @[package.scala:39:{76,86}]\n assign io_ill = _io_ill_T_64;\t// @[package.scala:39:76]\n assign io_out_bits = io_out_bits_0;\t// @[RVC.scala:190:7]\n assign io_rvc = io_rvc_0;\t// @[RVC.scala:190:7]\nendmodule"}}},{"rowIdx":35475,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) \n node _source_ok_T_1 = shr(io.in.a.bits.source, 2) \n node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) \n node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) \n node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) \n node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) \n node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n wire _source_ok_WIRE : UInt<1>[3] \n connect _source_ok_WIRE[0], _source_ok_T \n connect _source_ok_WIRE[1], _source_ok_T_6 \n connect _source_ok_WIRE[2], _source_ok_T_7 \n node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) \n node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) \n node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 1, 0) \n node _T_12 = shr(io.in.a.bits.source, 2) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n node _T_14 = leq(UInt<1>(0h0), uncommonBits) \n node _T_15 = and(_T_13, _T_14) \n node _T_16 = leq(uncommonBits, UInt<2>(0h3)) \n node _T_17 = and(_T_15, _T_16) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_20 = cvt(_T_19) \n node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) \n node _T_22 = asSInt(_T_21) \n node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) \n node _T_24 = or(_T_18, _T_23) \n node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_26 = eq(_T_25, UInt<1>(0h0)) \n node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_28 = cvt(_T_27) \n node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) \n node _T_30 = asSInt(_T_29) \n node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) \n node _T_32 = or(_T_26, _T_31) \n node _T_33 = and(_T_11, _T_24) \n node _T_34 = and(_T_33, _T_32) \n node _T_35 = asUInt(reset) \n node _T_36 = eq(_T_35, UInt<1>(0h0)) \n when _T_36 : \n node _T_37 = eq(_T_34, UInt<1>(0h0)) \n when _T_37 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_34, UInt<1>(0h1), \"\") : assert_1 \n node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_38 : \n node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_41 = and(_T_39, _T_40) \n node _T_42 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) \n node _T_43 = shr(io.in.a.bits.source, 2) \n node _T_44 = eq(_T_43, UInt<1>(0h0)) \n node _T_45 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = leq(uncommonBits_1, UInt<2>(0h3)) \n node _T_48 = and(_T_46, _T_47) \n node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_50 = or(_T_42, _T_48) \n node _T_51 = or(_T_50, _T_49) \n node _T_52 = and(_T_41, _T_51) \n node _T_53 = or(UInt<1>(0h0), _T_52) \n node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_56 = cvt(_T_55) \n node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) \n node _T_58 = asSInt(_T_57) \n node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) \n node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_61 = cvt(_T_60) \n node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) \n node _T_63 = asSInt(_T_62) \n node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) \n node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_66 = cvt(_T_65) \n node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) \n node _T_68 = asSInt(_T_67) \n node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) \n node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_71 = cvt(_T_70) \n node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) \n node _T_73 = asSInt(_T_72) \n node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) \n node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_76 = cvt(_T_75) \n node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) \n node _T_78 = asSInt(_T_77) \n node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) \n node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_81 = cvt(_T_80) \n node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) \n node _T_83 = asSInt(_T_82) \n node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) \n node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_86 = cvt(_T_85) \n node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) \n node _T_88 = asSInt(_T_87) \n node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) \n node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_91 = cvt(_T_90) \n node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) \n node _T_93 = asSInt(_T_92) \n node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) \n node _T_95 = or(_T_59, _T_64) \n node _T_96 = or(_T_95, _T_69) \n node _T_97 = or(_T_96, _T_74) \n node _T_98 = or(_T_97, _T_79) \n node _T_99 = or(_T_98, _T_84) \n node _T_100 = or(_T_99, _T_89) \n node _T_101 = or(_T_100, _T_94) \n node _T_102 = and(_T_54, _T_101) \n node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_104 = or(UInt<1>(0h0), _T_103) \n node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_106 = cvt(_T_105) \n node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) \n node _T_108 = asSInt(_T_107) \n node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) \n node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_111 = cvt(_T_110) \n node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) \n node _T_113 = asSInt(_T_112) \n node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) \n node _T_115 = or(_T_109, _T_114) \n node _T_116 = and(_T_104, _T_115) \n node _T_117 = or(UInt<1>(0h0), _T_102) \n node _T_118 = or(_T_117, _T_116) \n node _T_119 = and(_T_53, _T_118) \n node _T_120 = asUInt(reset) \n node _T_121 = eq(_T_120, UInt<1>(0h0)) \n when _T_121 : \n node _T_122 = eq(_T_119, UInt<1>(0h0)) \n when _T_122 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_119, UInt<1>(0h1), \"\") : assert_2 \n node _T_123 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) \n node _T_124 = shr(io.in.a.bits.source, 2) \n node _T_125 = eq(_T_124, UInt<1>(0h0)) \n node _T_126 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_127 = and(_T_125, _T_126) \n node _T_128 = leq(uncommonBits_2, UInt<2>(0h3)) \n node _T_129 = and(_T_127, _T_128) \n node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n wire _WIRE : UInt<1>[3] \n connect _WIRE[0], _T_123 \n connect _WIRE[1], _T_129 \n connect _WIRE[2], _T_130 \n node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_132 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_133 = mux(_WIRE[1], _T_131, UInt<1>(0h0)) \n node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_135 = or(_T_132, _T_133) \n node _T_136 = or(_T_135, _T_134) \n wire _WIRE_1 : UInt<1> \n connect _WIRE_1, _T_136 \n node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_139 = and(_T_137, _T_138) \n node _T_140 = or(UInt<1>(0h0), _T_139) \n node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_142 = cvt(_T_141) \n node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) \n node _T_144 = asSInt(_T_143) \n node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) \n node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_147 = cvt(_T_146) \n node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) \n node _T_149 = asSInt(_T_148) \n node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) \n node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_152 = cvt(_T_151) \n node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) \n node _T_154 = asSInt(_T_153) \n node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) \n node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_157 = cvt(_T_156) \n node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) \n node _T_159 = asSInt(_T_158) \n node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) \n node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_162 = cvt(_T_161) \n node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) \n node _T_164 = asSInt(_T_163) \n node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) \n node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_167 = cvt(_T_166) \n node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) \n node _T_169 = asSInt(_T_168) \n node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) \n node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_172 = cvt(_T_171) \n node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) \n node _T_174 = asSInt(_T_173) \n node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) \n node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_177 = cvt(_T_176) \n node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) \n node _T_179 = asSInt(_T_178) \n node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) \n node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_182 = cvt(_T_181) \n node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) \n node _T_184 = asSInt(_T_183) \n node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) \n node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_187 = cvt(_T_186) \n node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) \n node _T_189 = asSInt(_T_188) \n node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) \n node _T_191 = or(_T_145, _T_150) \n node _T_192 = or(_T_191, _T_155) \n node _T_193 = or(_T_192, _T_160) \n node _T_194 = or(_T_193, _T_165) \n node _T_195 = or(_T_194, _T_170) \n node _T_196 = or(_T_195, _T_175) \n node _T_197 = or(_T_196, _T_180) \n node _T_198 = or(_T_197, _T_185) \n node _T_199 = or(_T_198, _T_190) \n node _T_200 = and(_T_140, _T_199) \n node _T_201 = or(UInt<1>(0h0), _T_200) \n node _T_202 = and(_WIRE_1, _T_201) \n node _T_203 = asUInt(reset) \n node _T_204 = eq(_T_203, UInt<1>(0h0)) \n when _T_204 : \n node _T_205 = eq(_T_202, UInt<1>(0h0)) \n when _T_205 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_202, UInt<1>(0h1), \"\") : assert_3 \n node _T_206 = asUInt(reset) \n node _T_207 = eq(_T_206, UInt<1>(0h0)) \n when _T_207 : \n node _T_208 = eq(source_ok, UInt<1>(0h0)) \n when _T_208 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_4 \n node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_210 = asUInt(reset) \n node _T_211 = eq(_T_210, UInt<1>(0h0)) \n when _T_211 : \n node _T_212 = eq(_T_209, UInt<1>(0h0)) \n when _T_212 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_209, UInt<1>(0h1), \"\") : assert_5 \n node _T_213 = asUInt(reset) \n node _T_214 = eq(_T_213, UInt<1>(0h0)) \n when _T_214 : \n node _T_215 = eq(is_aligned, UInt<1>(0h0)) \n when _T_215 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_217 = asUInt(reset) \n node _T_218 = eq(_T_217, UInt<1>(0h0)) \n when _T_218 : \n node _T_219 = eq(_T_216, UInt<1>(0h0)) \n when _T_219 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_216, UInt<1>(0h1), \"\") : assert_7 \n node _T_220 = not(io.in.a.bits.mask) \n node _T_221 = eq(_T_220, UInt<1>(0h0)) \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_T_221, UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_221, UInt<1>(0h1), \"\") : assert_8 \n node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_226 = asUInt(reset) \n node _T_227 = eq(_T_226, UInt<1>(0h0)) \n when _T_227 : \n node _T_228 = eq(_T_225, UInt<1>(0h0)) \n when _T_228 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_225, UInt<1>(0h1), \"\") : assert_9 \n node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_229 : \n node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_232 = and(_T_230, _T_231) \n node _T_233 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) \n node _T_234 = shr(io.in.a.bits.source, 2) \n node _T_235 = eq(_T_234, UInt<1>(0h0)) \n node _T_236 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_237 = and(_T_235, _T_236) \n node _T_238 = leq(uncommonBits_3, UInt<2>(0h3)) \n node _T_239 = and(_T_237, _T_238) \n node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_241 = or(_T_233, _T_239) \n node _T_242 = or(_T_241, _T_240) \n node _T_243 = and(_T_232, _T_242) \n node _T_244 = or(UInt<1>(0h0), _T_243) \n node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_247 = cvt(_T_246) \n node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) \n node _T_249 = asSInt(_T_248) \n node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) \n node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_252 = cvt(_T_251) \n node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) \n node _T_254 = asSInt(_T_253) \n node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) \n node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_257 = cvt(_T_256) \n node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) \n node _T_259 = asSInt(_T_258) \n node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) \n node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_262 = cvt(_T_261) \n node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) \n node _T_264 = asSInt(_T_263) \n node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) \n node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_267 = cvt(_T_266) \n node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) \n node _T_269 = asSInt(_T_268) \n node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) \n node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_272 = cvt(_T_271) \n node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) \n node _T_274 = asSInt(_T_273) \n node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) \n node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_277 = cvt(_T_276) \n node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) \n node _T_279 = asSInt(_T_278) \n node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) \n node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_282 = cvt(_T_281) \n node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) \n node _T_284 = asSInt(_T_283) \n node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) \n node _T_286 = or(_T_250, _T_255) \n node _T_287 = or(_T_286, _T_260) \n node _T_288 = or(_T_287, _T_265) \n node _T_289 = or(_T_288, _T_270) \n node _T_290 = or(_T_289, _T_275) \n node _T_291 = or(_T_290, _T_280) \n node _T_292 = or(_T_291, _T_285) \n node _T_293 = and(_T_245, _T_292) \n node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_295 = or(UInt<1>(0h0), _T_294) \n node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_297 = cvt(_T_296) \n node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) \n node _T_299 = asSInt(_T_298) \n node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) \n node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_302 = cvt(_T_301) \n node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) \n node _T_304 = asSInt(_T_303) \n node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) \n node _T_306 = or(_T_300, _T_305) \n node _T_307 = and(_T_295, _T_306) \n node _T_308 = or(UInt<1>(0h0), _T_293) \n node _T_309 = or(_T_308, _T_307) \n node _T_310 = and(_T_244, _T_309) \n node _T_311 = asUInt(reset) \n node _T_312 = eq(_T_311, UInt<1>(0h0)) \n when _T_312 : \n node _T_313 = eq(_T_310, UInt<1>(0h0)) \n when _T_313 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_310, UInt<1>(0h1), \"\") : assert_10 \n node _T_314 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) \n node _T_315 = shr(io.in.a.bits.source, 2) \n node _T_316 = eq(_T_315, UInt<1>(0h0)) \n node _T_317 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_318 = and(_T_316, _T_317) \n node _T_319 = leq(uncommonBits_4, UInt<2>(0h3)) \n node _T_320 = and(_T_318, _T_319) \n node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n wire _WIRE_2 : UInt<1>[3] \n connect _WIRE_2[0], _T_314 \n connect _WIRE_2[1], _T_320 \n connect _WIRE_2[2], _T_321 \n node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) \n node _T_323 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_324 = mux(_WIRE_2[1], _T_322, UInt<1>(0h0)) \n node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_326 = or(_T_323, _T_324) \n node _T_327 = or(_T_326, _T_325) \n wire _WIRE_3 : UInt<1> \n connect _WIRE_3, _T_327 \n node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_330 = and(_T_328, _T_329) \n node _T_331 = or(UInt<1>(0h0), _T_330) \n node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_333 = cvt(_T_332) \n node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) \n node _T_335 = asSInt(_T_334) \n node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) \n node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_338 = cvt(_T_337) \n node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) \n node _T_340 = asSInt(_T_339) \n node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) \n node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_343 = cvt(_T_342) \n node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) \n node _T_345 = asSInt(_T_344) \n node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) \n node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_348 = cvt(_T_347) \n node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) \n node _T_350 = asSInt(_T_349) \n node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) \n node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_353 = cvt(_T_352) \n node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) \n node _T_355 = asSInt(_T_354) \n node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) \n node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_358 = cvt(_T_357) \n node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) \n node _T_360 = asSInt(_T_359) \n node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) \n node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_363 = cvt(_T_362) \n node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) \n node _T_365 = asSInt(_T_364) \n node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) \n node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_368 = cvt(_T_367) \n node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) \n node _T_370 = asSInt(_T_369) \n node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) \n node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_373 = cvt(_T_372) \n node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) \n node _T_375 = asSInt(_T_374) \n node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) \n node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_378 = cvt(_T_377) \n node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) \n node _T_380 = asSInt(_T_379) \n node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) \n node _T_382 = or(_T_336, _T_341) \n node _T_383 = or(_T_382, _T_346) \n node _T_384 = or(_T_383, _T_351) \n node _T_385 = or(_T_384, _T_356) \n node _T_386 = or(_T_385, _T_361) \n node _T_387 = or(_T_386, _T_366) \n node _T_388 = or(_T_387, _T_371) \n node _T_389 = or(_T_388, _T_376) \n node _T_390 = or(_T_389, _T_381) \n node _T_391 = and(_T_331, _T_390) \n node _T_392 = or(UInt<1>(0h0), _T_391) \n node _T_393 = and(_WIRE_3, _T_392) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_11 \n node _T_397 = asUInt(reset) \n node _T_398 = eq(_T_397, UInt<1>(0h0)) \n when _T_398 : \n node _T_399 = eq(source_ok, UInt<1>(0h0)) \n when _T_399 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_12 \n node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_401 = asUInt(reset) \n node _T_402 = eq(_T_401, UInt<1>(0h0)) \n when _T_402 : \n node _T_403 = eq(_T_400, UInt<1>(0h0)) \n when _T_403 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_400, UInt<1>(0h1), \"\") : assert_13 \n node _T_404 = asUInt(reset) \n node _T_405 = eq(_T_404, UInt<1>(0h0)) \n when _T_405 : \n node _T_406 = eq(is_aligned, UInt<1>(0h0)) \n when _T_406 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_408 = asUInt(reset) \n node _T_409 = eq(_T_408, UInt<1>(0h0)) \n when _T_409 : \n node _T_410 = eq(_T_407, UInt<1>(0h0)) \n when _T_410 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_407, UInt<1>(0h1), \"\") : assert_15 \n node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_T_411, UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_411, UInt<1>(0h1), \"\") : assert_16 \n node _T_415 = not(io.in.a.bits.mask) \n node _T_416 = eq(_T_415, UInt<1>(0h0)) \n node _T_417 = asUInt(reset) \n node _T_418 = eq(_T_417, UInt<1>(0h0)) \n when _T_418 : \n node _T_419 = eq(_T_416, UInt<1>(0h0)) \n when _T_419 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_416, UInt<1>(0h1), \"\") : assert_17 \n node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_421 = asUInt(reset) \n node _T_422 = eq(_T_421, UInt<1>(0h0)) \n when _T_422 : \n node _T_423 = eq(_T_420, UInt<1>(0h0)) \n when _T_423 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_420, UInt<1>(0h1), \"\") : assert_18 \n node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_424 : \n node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_427 = and(_T_425, _T_426) \n node _T_428 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) \n node _T_429 = shr(io.in.a.bits.source, 2) \n node _T_430 = eq(_T_429, UInt<1>(0h0)) \n node _T_431 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_432 = and(_T_430, _T_431) \n node _T_433 = leq(uncommonBits_5, UInt<2>(0h3)) \n node _T_434 = and(_T_432, _T_433) \n node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_436 = or(_T_428, _T_434) \n node _T_437 = or(_T_436, _T_435) \n node _T_438 = and(_T_427, _T_437) \n node _T_439 = or(UInt<1>(0h0), _T_438) \n node _T_440 = asUInt(reset) \n node _T_441 = eq(_T_440, UInt<1>(0h0)) \n when _T_441 : \n node _T_442 = eq(_T_439, UInt<1>(0h0)) \n when _T_442 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_439, UInt<1>(0h1), \"\") : assert_19 \n node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_445 = and(_T_443, _T_444) \n node _T_446 = or(UInt<1>(0h0), _T_445) \n node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_448 = cvt(_T_447) \n node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) \n node _T_450 = asSInt(_T_449) \n node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) \n node _T_452 = and(_T_446, _T_451) \n node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_455 = and(_T_453, _T_454) \n node _T_456 = or(UInt<1>(0h0), _T_455) \n node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_458 = cvt(_T_457) \n node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) \n node _T_460 = asSInt(_T_459) \n node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) \n node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_463 = cvt(_T_462) \n node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) \n node _T_465 = asSInt(_T_464) \n node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) \n node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_468 = cvt(_T_467) \n node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) \n node _T_470 = asSInt(_T_469) \n node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) \n node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_473 = cvt(_T_472) \n node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) \n node _T_475 = asSInt(_T_474) \n node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) \n node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_478 = cvt(_T_477) \n node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) \n node _T_480 = asSInt(_T_479) \n node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) \n node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_483 = cvt(_T_482) \n node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) \n node _T_485 = asSInt(_T_484) \n node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) \n node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_488 = cvt(_T_487) \n node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) \n node _T_490 = asSInt(_T_489) \n node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) \n node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_493 = cvt(_T_492) \n node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) \n node _T_495 = asSInt(_T_494) \n node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) \n node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_498 = cvt(_T_497) \n node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) \n node _T_500 = asSInt(_T_499) \n node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) \n node _T_502 = or(_T_461, _T_466) \n node _T_503 = or(_T_502, _T_471) \n node _T_504 = or(_T_503, _T_476) \n node _T_505 = or(_T_504, _T_481) \n node _T_506 = or(_T_505, _T_486) \n node _T_507 = or(_T_506, _T_491) \n node _T_508 = or(_T_507, _T_496) \n node _T_509 = or(_T_508, _T_501) \n node _T_510 = and(_T_456, _T_509) \n node _T_511 = or(UInt<1>(0h0), _T_452) \n node _T_512 = or(_T_511, _T_510) \n node _T_513 = asUInt(reset) \n node _T_514 = eq(_T_513, UInt<1>(0h0)) \n when _T_514 : \n node _T_515 = eq(_T_512, UInt<1>(0h0)) \n when _T_515 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_512, UInt<1>(0h1), \"\") : assert_20 \n node _T_516 = asUInt(reset) \n node _T_517 = eq(_T_516, UInt<1>(0h0)) \n when _T_517 : \n node _T_518 = eq(source_ok, UInt<1>(0h0)) \n when _T_518 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_21 \n node _T_519 = asUInt(reset) \n node _T_520 = eq(_T_519, UInt<1>(0h0)) \n when _T_520 : \n node _T_521 = eq(is_aligned, UInt<1>(0h0)) \n when _T_521 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_523 = asUInt(reset) \n node _T_524 = eq(_T_523, UInt<1>(0h0)) \n when _T_524 : \n node _T_525 = eq(_T_522, UInt<1>(0h0)) \n when _T_525 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_522, UInt<1>(0h1), \"\") : assert_23 \n node _T_526 = eq(io.in.a.bits.mask, mask) \n node _T_527 = asUInt(reset) \n node _T_528 = eq(_T_527, UInt<1>(0h0)) \n when _T_528 : \n node _T_529 = eq(_T_526, UInt<1>(0h0)) \n when _T_529 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_526, UInt<1>(0h1), \"\") : assert_24 \n node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_531 = asUInt(reset) \n node _T_532 = eq(_T_531, UInt<1>(0h0)) \n when _T_532 : \n node _T_533 = eq(_T_530, UInt<1>(0h0)) \n when _T_533 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_530, UInt<1>(0h1), \"\") : assert_25 \n node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_534 : \n node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_537 = and(_T_535, _T_536) \n node _T_538 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) \n node _T_539 = shr(io.in.a.bits.source, 2) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n node _T_541 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_542 = and(_T_540, _T_541) \n node _T_543 = leq(uncommonBits_6, UInt<2>(0h3)) \n node _T_544 = and(_T_542, _T_543) \n node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_546 = or(_T_538, _T_544) \n node _T_547 = or(_T_546, _T_545) \n node _T_548 = and(_T_537, _T_547) \n node _T_549 = or(UInt<1>(0h0), _T_548) \n node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_552 = and(_T_550, _T_551) \n node _T_553 = or(UInt<1>(0h0), _T_552) \n node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_555 = cvt(_T_554) \n node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) \n node _T_557 = asSInt(_T_556) \n node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) \n node _T_559 = and(_T_553, _T_558) \n node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_562 = and(_T_560, _T_561) \n node _T_563 = or(UInt<1>(0h0), _T_562) \n node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_565 = cvt(_T_564) \n node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) \n node _T_567 = asSInt(_T_566) \n node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) \n node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_570 = cvt(_T_569) \n node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) \n node _T_572 = asSInt(_T_571) \n node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) \n node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_575 = cvt(_T_574) \n node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) \n node _T_577 = asSInt(_T_576) \n node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) \n node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_580 = cvt(_T_579) \n node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) \n node _T_582 = asSInt(_T_581) \n node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) \n node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_585 = cvt(_T_584) \n node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) \n node _T_587 = asSInt(_T_586) \n node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) \n node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_590 = cvt(_T_589) \n node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) \n node _T_592 = asSInt(_T_591) \n node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) \n node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_595 = cvt(_T_594) \n node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) \n node _T_597 = asSInt(_T_596) \n node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) \n node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_600 = cvt(_T_599) \n node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) \n node _T_602 = asSInt(_T_601) \n node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) \n node _T_604 = or(_T_568, _T_573) \n node _T_605 = or(_T_604, _T_578) \n node _T_606 = or(_T_605, _T_583) \n node _T_607 = or(_T_606, _T_588) \n node _T_608 = or(_T_607, _T_593) \n node _T_609 = or(_T_608, _T_598) \n node _T_610 = or(_T_609, _T_603) \n node _T_611 = and(_T_563, _T_610) \n node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_614 = cvt(_T_613) \n node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) \n node _T_616 = asSInt(_T_615) \n node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) \n node _T_618 = and(_T_612, _T_617) \n node _T_619 = or(UInt<1>(0h0), _T_559) \n node _T_620 = or(_T_619, _T_611) \n node _T_621 = or(_T_620, _T_618) \n node _T_622 = and(_T_549, _T_621) \n node _T_623 = asUInt(reset) \n node _T_624 = eq(_T_623, UInt<1>(0h0)) \n when _T_624 : \n node _T_625 = eq(_T_622, UInt<1>(0h0)) \n when _T_625 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_622, UInt<1>(0h1), \"\") : assert_26 \n node _T_626 = asUInt(reset) \n node _T_627 = eq(_T_626, UInt<1>(0h0)) \n when _T_627 : \n node _T_628 = eq(source_ok, UInt<1>(0h0)) \n when _T_628 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_27 \n node _T_629 = asUInt(reset) \n node _T_630 = eq(_T_629, UInt<1>(0h0)) \n when _T_630 : \n node _T_631 = eq(is_aligned, UInt<1>(0h0)) \n when _T_631 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_633 = asUInt(reset) \n node _T_634 = eq(_T_633, UInt<1>(0h0)) \n when _T_634 : \n node _T_635 = eq(_T_632, UInt<1>(0h0)) \n when _T_635 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_632, UInt<1>(0h1), \"\") : assert_29 \n node _T_636 = eq(io.in.a.bits.mask, mask) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_30 \n node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_640 : \n node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_643 = and(_T_641, _T_642) \n node _T_644 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) \n node _T_645 = shr(io.in.a.bits.source, 2) \n node _T_646 = eq(_T_645, UInt<1>(0h0)) \n node _T_647 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_648 = and(_T_646, _T_647) \n node _T_649 = leq(uncommonBits_7, UInt<2>(0h3)) \n node _T_650 = and(_T_648, _T_649) \n node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_652 = or(_T_644, _T_650) \n node _T_653 = or(_T_652, _T_651) \n node _T_654 = and(_T_643, _T_653) \n node _T_655 = or(UInt<1>(0h0), _T_654) \n node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_658 = and(_T_656, _T_657) \n node _T_659 = or(UInt<1>(0h0), _T_658) \n node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_661 = cvt(_T_660) \n node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) \n node _T_663 = asSInt(_T_662) \n node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) \n node _T_665 = and(_T_659, _T_664) \n node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_668 = and(_T_666, _T_667) \n node _T_669 = or(UInt<1>(0h0), _T_668) \n node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_671 = cvt(_T_670) \n node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) \n node _T_673 = asSInt(_T_672) \n node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) \n node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_676 = cvt(_T_675) \n node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) \n node _T_678 = asSInt(_T_677) \n node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) \n node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_681 = cvt(_T_680) \n node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) \n node _T_683 = asSInt(_T_682) \n node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) \n node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_686 = cvt(_T_685) \n node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) \n node _T_688 = asSInt(_T_687) \n node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) \n node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_691 = cvt(_T_690) \n node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) \n node _T_693 = asSInt(_T_692) \n node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) \n node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_696 = cvt(_T_695) \n node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) \n node _T_698 = asSInt(_T_697) \n node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) \n node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_701 = cvt(_T_700) \n node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) \n node _T_703 = asSInt(_T_702) \n node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) \n node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_706 = cvt(_T_705) \n node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) \n node _T_708 = asSInt(_T_707) \n node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) \n node _T_710 = or(_T_674, _T_679) \n node _T_711 = or(_T_710, _T_684) \n node _T_712 = or(_T_711, _T_689) \n node _T_713 = or(_T_712, _T_694) \n node _T_714 = or(_T_713, _T_699) \n node _T_715 = or(_T_714, _T_704) \n node _T_716 = or(_T_715, _T_709) \n node _T_717 = and(_T_669, _T_716) \n node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_720 = cvt(_T_719) \n node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) \n node _T_722 = asSInt(_T_721) \n node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) \n node _T_724 = and(_T_718, _T_723) \n node _T_725 = or(UInt<1>(0h0), _T_665) \n node _T_726 = or(_T_725, _T_717) \n node _T_727 = or(_T_726, _T_724) \n node _T_728 = and(_T_655, _T_727) \n node _T_729 = asUInt(reset) \n node _T_730 = eq(_T_729, UInt<1>(0h0)) \n when _T_730 : \n node _T_731 = eq(_T_728, UInt<1>(0h0)) \n when _T_731 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_728, UInt<1>(0h1), \"\") : assert_31 \n node _T_732 = asUInt(reset) \n node _T_733 = eq(_T_732, UInt<1>(0h0)) \n when _T_733 : \n node _T_734 = eq(source_ok, UInt<1>(0h0)) \n when _T_734 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_32 \n node _T_735 = asUInt(reset) \n node _T_736 = eq(_T_735, UInt<1>(0h0)) \n when _T_736 : \n node _T_737 = eq(is_aligned, UInt<1>(0h0)) \n when _T_737 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_739 = asUInt(reset) \n node _T_740 = eq(_T_739, UInt<1>(0h0)) \n when _T_740 : \n node _T_741 = eq(_T_738, UInt<1>(0h0)) \n when _T_741 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_738, UInt<1>(0h1), \"\") : assert_34 \n node _T_742 = not(mask) \n node _T_743 = and(io.in.a.bits.mask, _T_742) \n node _T_744 = eq(_T_743, UInt<1>(0h0)) \n node _T_745 = asUInt(reset) \n node _T_746 = eq(_T_745, UInt<1>(0h0)) \n when _T_746 : \n node _T_747 = eq(_T_744, UInt<1>(0h0)) \n when _T_747 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_744, UInt<1>(0h1), \"\") : assert_35 \n node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_748 : \n node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_751 = and(_T_749, _T_750) \n node _T_752 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) \n node _T_753 = shr(io.in.a.bits.source, 2) \n node _T_754 = eq(_T_753, UInt<1>(0h0)) \n node _T_755 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_756 = and(_T_754, _T_755) \n node _T_757 = leq(uncommonBits_8, UInt<2>(0h3)) \n node _T_758 = and(_T_756, _T_757) \n node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_760 = or(_T_752, _T_758) \n node _T_761 = or(_T_760, _T_759) \n node _T_762 = and(_T_751, _T_761) \n node _T_763 = or(UInt<1>(0h0), _T_762) \n node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_766 = and(_T_764, _T_765) \n node _T_767 = or(UInt<1>(0h0), _T_766) \n node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_769 = cvt(_T_768) \n node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) \n node _T_771 = asSInt(_T_770) \n node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) \n node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_774 = cvt(_T_773) \n node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) \n node _T_776 = asSInt(_T_775) \n node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) \n node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_779 = cvt(_T_778) \n node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) \n node _T_781 = asSInt(_T_780) \n node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) \n node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_784 = cvt(_T_783) \n node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) \n node _T_786 = asSInt(_T_785) \n node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) \n node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_789 = cvt(_T_788) \n node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) \n node _T_791 = asSInt(_T_790) \n node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) \n node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_794 = cvt(_T_793) \n node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000))) \n node _T_796 = asSInt(_T_795) \n node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) \n node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_799 = cvt(_T_798) \n node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000))) \n node _T_801 = asSInt(_T_800) \n node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) \n node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_804 = cvt(_T_803) \n node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000))) \n node _T_806 = asSInt(_T_805) \n node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) \n node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_809 = cvt(_T_808) \n node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000))) \n node _T_811 = asSInt(_T_810) \n node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) \n node _T_813 = or(_T_772, _T_777) \n node _T_814 = or(_T_813, _T_782) \n node _T_815 = or(_T_814, _T_787) \n node _T_816 = or(_T_815, _T_792) \n node _T_817 = or(_T_816, _T_797) \n node _T_818 = or(_T_817, _T_802) \n node _T_819 = or(_T_818, _T_807) \n node _T_820 = or(_T_819, _T_812) \n node _T_821 = and(_T_767, _T_820) \n node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_824 = cvt(_T_823) \n node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) \n node _T_826 = asSInt(_T_825) \n node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) \n node _T_828 = and(_T_822, _T_827) \n node _T_829 = or(UInt<1>(0h0), _T_821) \n node _T_830 = or(_T_829, _T_828) \n node _T_831 = and(_T_763, _T_830) \n node _T_832 = asUInt(reset) \n node _T_833 = eq(_T_832, UInt<1>(0h0)) \n when _T_833 : \n node _T_834 = eq(_T_831, UInt<1>(0h0)) \n when _T_834 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_831, UInt<1>(0h1), \"\") : assert_36 \n node _T_835 = asUInt(reset) \n node _T_836 = eq(_T_835, UInt<1>(0h0)) \n when _T_836 : \n node _T_837 = eq(source_ok, UInt<1>(0h0)) \n when _T_837 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_37 \n node _T_838 = asUInt(reset) \n node _T_839 = eq(_T_838, UInt<1>(0h0)) \n when _T_839 : \n node _T_840 = eq(is_aligned, UInt<1>(0h0)) \n when _T_840 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_842 = asUInt(reset) \n node _T_843 = eq(_T_842, UInt<1>(0h0)) \n when _T_843 : \n node _T_844 = eq(_T_841, UInt<1>(0h0)) \n when _T_844 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_841, UInt<1>(0h1), \"\") : assert_39 \n node _T_845 = eq(io.in.a.bits.mask, mask) \n node _T_846 = asUInt(reset) \n node _T_847 = eq(_T_846, UInt<1>(0h0)) \n when _T_847 : \n node _T_848 = eq(_T_845, UInt<1>(0h0)) \n when _T_848 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_845, UInt<1>(0h1), \"\") : assert_40 \n node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_849 : \n node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_852 = and(_T_850, _T_851) \n node _T_853 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) \n node _T_854 = shr(io.in.a.bits.source, 2) \n node _T_855 = eq(_T_854, UInt<1>(0h0)) \n node _T_856 = leq(UInt<1>(0h0), uncommonBits_9) \n node _T_857 = and(_T_855, _T_856) \n node _T_858 = leq(uncommonBits_9, UInt<2>(0h3)) \n node _T_859 = and(_T_857, _T_858) \n node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_861 = or(_T_853, _T_859) \n node _T_862 = or(_T_861, _T_860) \n node _T_863 = and(_T_852, _T_862) \n node _T_864 = or(UInt<1>(0h0), _T_863) \n node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_867 = and(_T_865, _T_866) \n node _T_868 = or(UInt<1>(0h0), _T_867) \n node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_870 = cvt(_T_869) \n node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000))) \n node _T_872 = asSInt(_T_871) \n node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) \n node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_875 = cvt(_T_874) \n node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) \n node _T_877 = asSInt(_T_876) \n node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) \n node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_880 = cvt(_T_879) \n node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000))) \n node _T_882 = asSInt(_T_881) \n node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) \n node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_885 = cvt(_T_884) \n node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000))) \n node _T_887 = asSInt(_T_886) \n node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) \n node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_890 = cvt(_T_889) \n node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) \n node _T_892 = asSInt(_T_891) \n node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) \n node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_895 = cvt(_T_894) \n node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) \n node _T_897 = asSInt(_T_896) \n node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) \n node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_900 = cvt(_T_899) \n node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) \n node _T_902 = asSInt(_T_901) \n node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) \n node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_905 = cvt(_T_904) \n node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) \n node _T_907 = asSInt(_T_906) \n node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) \n node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_910 = cvt(_T_909) \n node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) \n node _T_912 = asSInt(_T_911) \n node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) \n node _T_914 = or(_T_873, _T_878) \n node _T_915 = or(_T_914, _T_883) \n node _T_916 = or(_T_915, _T_888) \n node _T_917 = or(_T_916, _T_893) \n node _T_918 = or(_T_917, _T_898) \n node _T_919 = or(_T_918, _T_903) \n node _T_920 = or(_T_919, _T_908) \n node _T_921 = or(_T_920, _T_913) \n node _T_922 = and(_T_868, _T_921) \n node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_925 = cvt(_T_924) \n node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) \n node _T_927 = asSInt(_T_926) \n node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) \n node _T_929 = and(_T_923, _T_928) \n node _T_930 = or(UInt<1>(0h0), _T_922) \n node _T_931 = or(_T_930, _T_929) \n node _T_932 = and(_T_864, _T_931) \n node _T_933 = asUInt(reset) \n node _T_934 = eq(_T_933, UInt<1>(0h0)) \n when _T_934 : \n node _T_935 = eq(_T_932, UInt<1>(0h0)) \n when _T_935 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_932, UInt<1>(0h1), \"\") : assert_41 \n node _T_936 = asUInt(reset) \n node _T_937 = eq(_T_936, UInt<1>(0h0)) \n when _T_937 : \n node _T_938 = eq(source_ok, UInt<1>(0h0)) \n when _T_938 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_42 \n node _T_939 = asUInt(reset) \n node _T_940 = eq(_T_939, UInt<1>(0h0)) \n when _T_940 : \n node _T_941 = eq(is_aligned, UInt<1>(0h0)) \n when _T_941 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_943 = asUInt(reset) \n node _T_944 = eq(_T_943, UInt<1>(0h0)) \n when _T_944 : \n node _T_945 = eq(_T_942, UInt<1>(0h0)) \n when _T_945 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_942, UInt<1>(0h1), \"\") : assert_44 \n node _T_946 = eq(io.in.a.bits.mask, mask) \n node _T_947 = asUInt(reset) \n node _T_948 = eq(_T_947, UInt<1>(0h0)) \n when _T_948 : \n node _T_949 = eq(_T_946, UInt<1>(0h0)) \n when _T_949 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_946, UInt<1>(0h1), \"\") : assert_45 \n node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_950 : \n node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_953 = and(_T_951, _T_952) \n node _T_954 = eq(io.in.a.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) \n node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) \n node _T_955 = shr(io.in.a.bits.source, 2) \n node _T_956 = eq(_T_955, UInt<1>(0h0)) \n node _T_957 = leq(UInt<1>(0h0), uncommonBits_10) \n node _T_958 = and(_T_956, _T_957) \n node _T_959 = leq(uncommonBits_10, UInt<2>(0h3)) \n node _T_960 = and(_T_958, _T_959) \n node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4)) \n node _T_962 = or(_T_954, _T_960) \n node _T_963 = or(_T_962, _T_961) \n node _T_964 = and(_T_953, _T_963) \n node _T_965 = or(UInt<1>(0h0), _T_964) \n node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_968 = and(_T_966, _T_967) \n node _T_969 = or(UInt<1>(0h0), _T_968) \n node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000)) \n node _T_971 = cvt(_T_970) \n node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000))) \n node _T_973 = asSInt(_T_972) \n node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) \n node _T_975 = and(_T_969, _T_974) \n node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_978 = cvt(_T_977) \n node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000))) \n node _T_980 = asSInt(_T_979) \n node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) \n node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000)) \n node _T_983 = cvt(_T_982) \n node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000))) \n node _T_985 = asSInt(_T_984) \n node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) \n node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000)) \n node _T_988 = cvt(_T_987) \n node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000))) \n node _T_990 = asSInt(_T_989) \n node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) \n node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) \n node _T_993 = cvt(_T_992) \n node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) \n node _T_995 = asSInt(_T_994) \n node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) \n node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) \n node _T_998 = cvt(_T_997) \n node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000))) \n node _T_1000 = asSInt(_T_999) \n node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) \n node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) \n node _T_1003 = cvt(_T_1002) \n node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000))) \n node _T_1005 = asSInt(_T_1004) \n node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) \n node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) \n node _T_1008 = cvt(_T_1007) \n node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) \n node _T_1010 = asSInt(_T_1009) \n node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) \n node _T_1012 = or(_T_981, _T_986) \n node _T_1013 = or(_T_1012, _T_991) \n node _T_1014 = or(_T_1013, _T_996) \n node _T_1015 = or(_T_1014, _T_1001) \n node _T_1016 = or(_T_1015, _T_1006) \n node _T_1017 = or(_T_1016, _T_1011) \n node _T_1018 = and(_T_976, _T_1017) \n node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_1021 = and(_T_1019, _T_1020) \n node _T_1022 = or(UInt<1>(0h0), _T_1021) \n node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_1024 = cvt(_T_1023) \n node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000))) \n node _T_1026 = asSInt(_T_1025) \n node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) \n node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) \n node _T_1029 = cvt(_T_1028) \n node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000))) \n node _T_1031 = asSInt(_T_1030) \n node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0))) \n node _T_1033 = or(_T_1027, _T_1032) \n node _T_1034 = and(_T_1022, _T_1033) \n node _T_1035 = or(UInt<1>(0h0), _T_975) \n node _T_1036 = or(_T_1035, _T_1018) \n node _T_1037 = or(_T_1036, _T_1034) \n node _T_1038 = and(_T_965, _T_1037) \n node _T_1039 = asUInt(reset) \n node _T_1040 = eq(_T_1039, UInt<1>(0h0)) \n when _T_1040 : \n node _T_1041 = eq(_T_1038, UInt<1>(0h0)) \n when _T_1041 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_1038, UInt<1>(0h1), \"\") : assert_46 \n node _T_1042 = asUInt(reset) \n node _T_1043 = eq(_T_1042, UInt<1>(0h0)) \n when _T_1043 : \n node _T_1044 = eq(source_ok, UInt<1>(0h0)) \n when _T_1044 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, source_ok, UInt<1>(0h1), \"\") : assert_47 \n node _T_1045 = asUInt(reset) \n node _T_1046 = eq(_T_1045, UInt<1>(0h0)) \n when _T_1046 : \n node _T_1047 = eq(is_aligned, UInt<1>(0h0)) \n when _T_1047 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_1049 = asUInt(reset) \n node _T_1050 = eq(_T_1049, UInt<1>(0h0)) \n when _T_1050 : \n node _T_1051 = eq(_T_1048, UInt<1>(0h0)) \n when _T_1051 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_1048, UInt<1>(0h1), \"\") : assert_49 \n node _T_1052 = eq(io.in.a.bits.mask, mask) \n node _T_1053 = asUInt(reset) \n node _T_1054 = eq(_T_1053, UInt<1>(0h0)) \n when _T_1054 : \n node _T_1055 = eq(_T_1052, UInt<1>(0h0)) \n when _T_1055 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_1052, UInt<1>(0h1), \"\") : assert_50 \n node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_1057 = asUInt(reset) \n node _T_1058 = eq(_T_1057, UInt<1>(0h0)) \n when _T_1058 : \n node _T_1059 = eq(_T_1056, UInt<1>(0h0)) \n when _T_1059 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_1056, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_1061 = asUInt(reset) \n node _T_1062 = eq(_T_1061, UInt<1>(0h0)) \n when _T_1062 : \n node _T_1063 = eq(_T_1060, UInt<1>(0h0)) \n when _T_1063 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_1060, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_9 = eq(io.in.d.bits.source, UInt<4>(0h8)) \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) \n node _source_ok_T_10 = shr(io.in.d.bits.source, 2) \n node _source_ok_T_11 = eq(_source_ok_T_10, UInt<1>(0h0)) \n node _source_ok_T_12 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_13 = and(_source_ok_T_11, _source_ok_T_12) \n node _source_ok_T_14 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) \n node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) \n node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4)) \n wire _source_ok_WIRE_1 : UInt<1>[3] \n connect _source_ok_WIRE_1[0], _source_ok_T_9 \n connect _source_ok_WIRE_1[1], _source_ok_T_15 \n connect _source_ok_WIRE_1[2], _source_ok_T_16 \n node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) \n node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) \n node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) \n node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_1064 : \n node _T_1065 = asUInt(reset) \n node _T_1066 = eq(_T_1065, UInt<1>(0h0)) \n when _T_1066 : \n node _T_1067 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1067 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_53 \n node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1069 = asUInt(reset) \n node _T_1070 = eq(_T_1069, UInt<1>(0h0)) \n when _T_1070 : \n node _T_1071 = eq(_T_1068, UInt<1>(0h0)) \n when _T_1071 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_1068, UInt<1>(0h1), \"\") : assert_54 \n node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1073 = asUInt(reset) \n node _T_1074 = eq(_T_1073, UInt<1>(0h0)) \n when _T_1074 : \n node _T_1075 = eq(_T_1072, UInt<1>(0h0)) \n when _T_1075 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_1072, UInt<1>(0h1), \"\") : assert_55 \n node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1077 = asUInt(reset) \n node _T_1078 = eq(_T_1077, UInt<1>(0h0)) \n when _T_1078 : \n node _T_1079 = eq(_T_1076, UInt<1>(0h0)) \n when _T_1079 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_1076, UInt<1>(0h1), \"\") : assert_56 \n node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1081 = asUInt(reset) \n node _T_1082 = eq(_T_1081, UInt<1>(0h0)) \n when _T_1082 : \n node _T_1083 = eq(_T_1080, UInt<1>(0h0)) \n when _T_1083 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_1080, UInt<1>(0h1), \"\") : assert_57 \n node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_1084 : \n node _T_1085 = asUInt(reset) \n node _T_1086 = eq(_T_1085, UInt<1>(0h0)) \n when _T_1086 : \n node _T_1087 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1087 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_58 \n node _T_1088 = asUInt(reset) \n node _T_1089 = eq(_T_1088, UInt<1>(0h0)) \n when _T_1089 : \n node _T_1090 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1090 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1092 = asUInt(reset) \n node _T_1093 = eq(_T_1092, UInt<1>(0h0)) \n when _T_1093 : \n node _T_1094 = eq(_T_1091, UInt<1>(0h0)) \n when _T_1094 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_1091, UInt<1>(0h1), \"\") : assert_60 \n node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1096 = asUInt(reset) \n node _T_1097 = eq(_T_1096, UInt<1>(0h0)) \n when _T_1097 : \n node _T_1098 = eq(_T_1095, UInt<1>(0h0)) \n when _T_1098 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_1095, UInt<1>(0h1), \"\") : assert_61 \n node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1100 = asUInt(reset) \n node _T_1101 = eq(_T_1100, UInt<1>(0h0)) \n when _T_1101 : \n node _T_1102 = eq(_T_1099, UInt<1>(0h0)) \n when _T_1102 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_1099, UInt<1>(0h1), \"\") : assert_62 \n node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1104 = asUInt(reset) \n node _T_1105 = eq(_T_1104, UInt<1>(0h0)) \n when _T_1105 : \n node _T_1106 = eq(_T_1103, UInt<1>(0h0)) \n when _T_1106 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_1103, UInt<1>(0h1), \"\") : assert_63 \n node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1108 = or(UInt<1>(0h1), _T_1107) \n node _T_1109 = asUInt(reset) \n node _T_1110 = eq(_T_1109, UInt<1>(0h0)) \n when _T_1110 : \n node _T_1111 = eq(_T_1108, UInt<1>(0h0)) \n when _T_1111 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_1108, UInt<1>(0h1), \"\") : assert_64 \n node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_1112 : \n node _T_1113 = asUInt(reset) \n node _T_1114 = eq(_T_1113, UInt<1>(0h0)) \n when _T_1114 : \n node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_65 \n node _T_1116 = asUInt(reset) \n node _T_1117 = eq(_T_1116, UInt<1>(0h0)) \n when _T_1117 : \n node _T_1118 = eq(sink_ok, UInt<1>(0h0)) \n when _T_1118 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_1120 = asUInt(reset) \n node _T_1121 = eq(_T_1120, UInt<1>(0h0)) \n when _T_1121 : \n node _T_1122 = eq(_T_1119, UInt<1>(0h0)) \n when _T_1122 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_1119, UInt<1>(0h1), \"\") : assert_67 \n node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1124 = asUInt(reset) \n node _T_1125 = eq(_T_1124, UInt<1>(0h0)) \n when _T_1125 : \n node _T_1126 = eq(_T_1123, UInt<1>(0h0)) \n when _T_1126 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_1123, UInt<1>(0h1), \"\") : assert_68 \n node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_1128 = asUInt(reset) \n node _T_1129 = eq(_T_1128, UInt<1>(0h0)) \n when _T_1129 : \n node _T_1130 = eq(_T_1127, UInt<1>(0h0)) \n when _T_1130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_1127, UInt<1>(0h1), \"\") : assert_69 \n node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1132 = or(_T_1131, io.in.d.bits.corrupt) \n node _T_1133 = asUInt(reset) \n node _T_1134 = eq(_T_1133, UInt<1>(0h0)) \n when _T_1134 : \n node _T_1135 = eq(_T_1132, UInt<1>(0h0)) \n when _T_1135 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_1132, UInt<1>(0h1), \"\") : assert_70 \n node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1137 = or(UInt<1>(0h1), _T_1136) \n node _T_1138 = asUInt(reset) \n node _T_1139 = eq(_T_1138, UInt<1>(0h0)) \n when _T_1139 : \n node _T_1140 = eq(_T_1137, UInt<1>(0h0)) \n when _T_1140 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_1137, UInt<1>(0h1), \"\") : assert_71 \n node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_1141 : \n node _T_1142 = asUInt(reset) \n node _T_1143 = eq(_T_1142, UInt<1>(0h0)) \n when _T_1143 : \n node _T_1144 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1144 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_72 \n node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1146 = asUInt(reset) \n node _T_1147 = eq(_T_1146, UInt<1>(0h0)) \n when _T_1147 : \n node _T_1148 = eq(_T_1145, UInt<1>(0h0)) \n when _T_1148 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_1145, UInt<1>(0h1), \"\") : assert_73 \n node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1150 = asUInt(reset) \n node _T_1151 = eq(_T_1150, UInt<1>(0h0)) \n when _T_1151 : \n node _T_1152 = eq(_T_1149, UInt<1>(0h0)) \n when _T_1152 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_1149, UInt<1>(0h1), \"\") : assert_74 \n node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1154 = or(UInt<1>(0h1), _T_1153) \n node _T_1155 = asUInt(reset) \n node _T_1156 = eq(_T_1155, UInt<1>(0h0)) \n when _T_1156 : \n node _T_1157 = eq(_T_1154, UInt<1>(0h0)) \n when _T_1157 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_1154, UInt<1>(0h1), \"\") : assert_75 \n node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_1158 : \n node _T_1159 = asUInt(reset) \n node _T_1160 = eq(_T_1159, UInt<1>(0h0)) \n when _T_1160 : \n node _T_1161 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1161 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_76 \n node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1163 = asUInt(reset) \n node _T_1164 = eq(_T_1163, UInt<1>(0h0)) \n when _T_1164 : \n node _T_1165 = eq(_T_1162, UInt<1>(0h0)) \n when _T_1165 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_1162, UInt<1>(0h1), \"\") : assert_77 \n node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1167 = or(_T_1166, io.in.d.bits.corrupt) \n node _T_1168 = asUInt(reset) \n node _T_1169 = eq(_T_1168, UInt<1>(0h0)) \n when _T_1169 : \n node _T_1170 = eq(_T_1167, UInt<1>(0h0)) \n when _T_1170 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_1167, UInt<1>(0h1), \"\") : assert_78 \n node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1172 = or(UInt<1>(0h1), _T_1171) \n node _T_1173 = asUInt(reset) \n node _T_1174 = eq(_T_1173, UInt<1>(0h0)) \n when _T_1174 : \n node _T_1175 = eq(_T_1172, UInt<1>(0h0)) \n when _T_1175 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_1172, UInt<1>(0h1), \"\") : assert_79 \n node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_1176 : \n node _T_1177 = asUInt(reset) \n node _T_1178 = eq(_T_1177, UInt<1>(0h0)) \n when _T_1178 : \n node _T_1179 = eq(source_ok_1, UInt<1>(0h0)) \n when _T_1179 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, source_ok_1, UInt<1>(0h1), \"\") : assert_80 \n node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_1181 = asUInt(reset) \n node _T_1182 = eq(_T_1181, UInt<1>(0h0)) \n when _T_1182 : \n node _T_1183 = eq(_T_1180, UInt<1>(0h0)) \n when _T_1183 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_1180, UInt<1>(0h1), \"\") : assert_81 \n node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_1185 = asUInt(reset) \n node _T_1186 = eq(_T_1185, UInt<1>(0h0)) \n when _T_1186 : \n node _T_1187 = eq(_T_1184, UInt<1>(0h0)) \n when _T_1187 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_1184, UInt<1>(0h1), \"\") : assert_82 \n node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_1189 = or(UInt<1>(0h1), _T_1188) \n node _T_1190 = asUInt(reset) \n node _T_1191 = eq(_T_1190, UInt<1>(0h0)) \n when _T_1191 : \n node _T_1192 = eq(_T_1189, UInt<1>(0h0)) \n when _T_1192 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_1189, UInt<1>(0h1), \"\") : assert_83 \n when io.in.b.valid : \n node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) \n node _T_1194 = asUInt(reset) \n node _T_1195 = eq(_T_1194, UInt<1>(0h0)) \n when _T_1195 : \n node _T_1196 = eq(_T_1193, UInt<1>(0h0)) \n when _T_1196 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_1193, UInt<1>(0h1), \"\") : assert_84 \n node _T_1197 = eq(io.in.b.bits.source, UInt<4>(0h8)) \n node _T_1198 = eq(_T_1197, UInt<1>(0h0)) \n node _T_1199 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1200 = cvt(_T_1199) \n node _T_1201 = and(_T_1200, asSInt(UInt<1>(0h0))) \n node _T_1202 = asSInt(_T_1201) \n node _T_1203 = eq(_T_1202, asSInt(UInt<1>(0h0))) \n node _T_1204 = or(_T_1198, _T_1203) \n node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) \n node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) \n node _T_1205 = shr(io.in.b.bits.source, 2) \n node _T_1206 = eq(_T_1205, UInt<1>(0h0)) \n node _T_1207 = leq(UInt<1>(0h0), uncommonBits_11) \n node _T_1208 = and(_T_1206, _T_1207) \n node _T_1209 = leq(uncommonBits_11, UInt<2>(0h3)) \n node _T_1210 = and(_T_1208, _T_1209) \n node _T_1211 = eq(_T_1210, UInt<1>(0h0)) \n node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1213 = cvt(_T_1212) \n node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) \n node _T_1215 = asSInt(_T_1214) \n node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) \n node _T_1217 = or(_T_1211, _T_1216) \n node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4)) \n node _T_1219 = eq(_T_1218, UInt<1>(0h0)) \n node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1221 = cvt(_T_1220) \n node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) \n node _T_1223 = asSInt(_T_1222) \n node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) \n node _T_1225 = or(_T_1219, _T_1224) \n node _T_1226 = and(_T_1204, _T_1217) \n node _T_1227 = and(_T_1226, _T_1225) \n node _T_1228 = asUInt(reset) \n node _T_1229 = eq(_T_1228, UInt<1>(0h0)) \n when _T_1229 : \n node _T_1230 = eq(_T_1227, UInt<1>(0h0)) \n when _T_1230 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_1227, UInt<1>(0h1), \"\") : assert_85 \n node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _address_ok_T_1 = cvt(_address_ok_T) \n node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_3 = asSInt(_address_ok_T_2) \n node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) \n node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) \n node _address_ok_T_6 = cvt(_address_ok_T_5) \n node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_8 = asSInt(_address_ok_T_7) \n node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) \n node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _address_ok_T_11 = cvt(_address_ok_T_10) \n node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_13 = asSInt(_address_ok_T_12) \n node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) \n node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _address_ok_T_16 = cvt(_address_ok_T_15) \n node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_18 = asSInt(_address_ok_T_17) \n node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) \n node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _address_ok_T_21 = cvt(_address_ok_T_20) \n node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_23 = asSInt(_address_ok_T_22) \n node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) \n node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) \n node _address_ok_T_26 = cvt(_address_ok_T_25) \n node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_28 = asSInt(_address_ok_T_27) \n node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) \n node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _address_ok_T_31 = cvt(_address_ok_T_30) \n node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_33 = asSInt(_address_ok_T_32) \n node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) \n node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _address_ok_T_36 = cvt(_address_ok_T_35) \n node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_38 = asSInt(_address_ok_T_37) \n node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) \n node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _address_ok_T_41 = cvt(_address_ok_T_40) \n node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_43 = asSInt(_address_ok_T_42) \n node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) \n node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _address_ok_T_46 = cvt(_address_ok_T_45) \n node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) \n node _address_ok_T_48 = asSInt(_address_ok_T_47) \n node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) \n node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _address_ok_T_51 = cvt(_address_ok_T_50) \n node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_53 = asSInt(_address_ok_T_52) \n node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) \n node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _address_ok_T_56 = cvt(_address_ok_T_55) \n node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) \n node _address_ok_T_58 = asSInt(_address_ok_T_57) \n node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) \n wire _address_ok_WIRE : UInt<1>[12] \n connect _address_ok_WIRE[0], _address_ok_T_4 \n connect _address_ok_WIRE[1], _address_ok_T_9 \n connect _address_ok_WIRE[2], _address_ok_T_14 \n connect _address_ok_WIRE[3], _address_ok_T_19 \n connect _address_ok_WIRE[4], _address_ok_T_24 \n connect _address_ok_WIRE[5], _address_ok_T_29 \n connect _address_ok_WIRE[6], _address_ok_T_34 \n connect _address_ok_WIRE[7], _address_ok_T_39 \n connect _address_ok_WIRE[8], _address_ok_T_44 \n connect _address_ok_WIRE[9], _address_ok_T_49 \n connect _address_ok_WIRE[10], _address_ok_T_54 \n connect _address_ok_WIRE[11], _address_ok_T_59 \n node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) \n node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) \n node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) \n node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) \n node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) \n node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) \n node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) \n node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) \n node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) \n node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) \n node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) \n node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) \n node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) \n node is_aligned_mask_1 = not(_is_aligned_mask_T_3) \n node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) \n node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) \n node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) \n node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) \n node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) \n node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) \n node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) \n node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) \n node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) \n node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) \n node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) \n node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) \n node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) \n node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) \n node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) \n node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) \n node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) \n node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) \n node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) \n node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) \n node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) \n node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) \n node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) \n node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) \n node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) \n node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) \n node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) \n node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) \n node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) \n node mask_size_1 = bits(mask_sizeOH_1, 0, 0) \n node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) \n node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) \n node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) \n node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) \n node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) \n node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) \n node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) \n node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) \n node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) \n node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) \n node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) \n node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) \n node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) \n node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) \n node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) \n node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) \n node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) \n node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) \n node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) \n node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) \n node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) \n node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) \n node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) \n node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) \n node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) \n node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) \n node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) \n node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) \n node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) \n node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) \n node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) \n node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) \n node mask_1 = cat(mask_hi_1, mask_lo_1) \n node _legal_source_T = eq(io.in.b.bits.source, UInt<4>(0h8)) \n node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) \n node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) \n node _legal_source_T_1 = shr(io.in.b.bits.source, 2) \n node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0)) \n node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits) \n node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3) \n node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3)) \n node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5) \n node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4)) \n wire _legal_source_WIRE : UInt<1>[3] \n connect _legal_source_WIRE[0], _legal_source_T \n connect _legal_source_WIRE[1], _legal_source_T_6 \n connect _legal_source_WIRE[2], _legal_source_T_7 \n node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<4>(0h8), UInt<1>(0h0)) \n node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) \n node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) \n node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) \n node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) \n wire _legal_source_WIRE_1 : UInt<4> \n connect _legal_source_WIRE_1, _legal_source_T_12 \n node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) \n node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) \n when _T_1231 : \n node _T_1232 = eq(io.in.b.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) \n node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) \n node _T_1233 = shr(io.in.b.bits.source, 2) \n node _T_1234 = eq(_T_1233, UInt<1>(0h0)) \n node _T_1235 = leq(UInt<1>(0h0), uncommonBits_12) \n node _T_1236 = and(_T_1234, _T_1235) \n node _T_1237 = leq(uncommonBits_12, UInt<2>(0h3)) \n node _T_1238 = and(_T_1236, _T_1237) \n node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4)) \n wire _WIRE_4 : UInt<1>[3] \n connect _WIRE_4[0], _T_1232 \n connect _WIRE_4[1], _T_1238 \n connect _WIRE_4[2], _T_1239 \n node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size) \n node _T_1241 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1242 = mux(_WIRE_4[1], _T_1240, UInt<1>(0h0)) \n node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1244 = or(_T_1241, _T_1242) \n node _T_1245 = or(_T_1244, _T_1243) \n wire _WIRE_5 : UInt<1> \n connect _WIRE_5, _T_1245 \n node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1248 = and(_T_1246, _T_1247) \n node _T_1249 = or(UInt<1>(0h0), _T_1248) \n node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1251 = cvt(_T_1250) \n node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000))) \n node _T_1253 = asSInt(_T_1252) \n node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) \n node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1256 = cvt(_T_1255) \n node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000))) \n node _T_1258 = asSInt(_T_1257) \n node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) \n node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1261 = cvt(_T_1260) \n node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000))) \n node _T_1263 = asSInt(_T_1262) \n node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) \n node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1266 = cvt(_T_1265) \n node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000))) \n node _T_1268 = asSInt(_T_1267) \n node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) \n node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1271 = cvt(_T_1270) \n node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) \n node _T_1273 = asSInt(_T_1272) \n node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) \n node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1276 = cvt(_T_1275) \n node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000))) \n node _T_1278 = asSInt(_T_1277) \n node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) \n node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1281 = cvt(_T_1280) \n node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) \n node _T_1283 = asSInt(_T_1282) \n node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) \n node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1286 = cvt(_T_1285) \n node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000))) \n node _T_1288 = asSInt(_T_1287) \n node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) \n node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1291 = cvt(_T_1290) \n node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000))) \n node _T_1293 = asSInt(_T_1292) \n node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) \n node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1296 = cvt(_T_1295) \n node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000))) \n node _T_1298 = asSInt(_T_1297) \n node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) \n node _T_1300 = or(_T_1254, _T_1259) \n node _T_1301 = or(_T_1300, _T_1264) \n node _T_1302 = or(_T_1301, _T_1269) \n node _T_1303 = or(_T_1302, _T_1274) \n node _T_1304 = or(_T_1303, _T_1279) \n node _T_1305 = or(_T_1304, _T_1284) \n node _T_1306 = or(_T_1305, _T_1289) \n node _T_1307 = or(_T_1306, _T_1294) \n node _T_1308 = or(_T_1307, _T_1299) \n node _T_1309 = and(_T_1249, _T_1308) \n node _T_1310 = or(UInt<1>(0h0), _T_1309) \n node _T_1311 = and(_WIRE_5, _T_1310) \n node _T_1312 = asUInt(reset) \n node _T_1313 = eq(_T_1312, UInt<1>(0h0)) \n when _T_1313 : \n node _T_1314 = eq(_T_1311, UInt<1>(0h0)) \n when _T_1314 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_1311, UInt<1>(0h1), \"\") : assert_86 \n node _T_1315 = asUInt(reset) \n node _T_1316 = eq(_T_1315, UInt<1>(0h0)) \n when _T_1316 : \n node _T_1317 = eq(address_ok, UInt<1>(0h0)) \n when _T_1317 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_87 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_87 \n node _T_1318 = asUInt(reset) \n node _T_1319 = eq(_T_1318, UInt<1>(0h0)) \n when _T_1319 : \n node _T_1320 = eq(legal_source, UInt<1>(0h0)) \n when _T_1320 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_88 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_88 \n node _T_1321 = asUInt(reset) \n node _T_1322 = eq(_T_1321, UInt<1>(0h0)) \n when _T_1322 : \n node _T_1323 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1323 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_89 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_89 \n node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2)) \n node _T_1325 = asUInt(reset) \n node _T_1326 = eq(_T_1325, UInt<1>(0h0)) \n when _T_1326 : \n node _T_1327 = eq(_T_1324, UInt<1>(0h0)) \n when _T_1327 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_1324, UInt<1>(0h1), \"\") : assert_90 \n node _T_1328 = eq(io.in.b.bits.mask, mask_1) \n node _T_1329 = asUInt(reset) \n node _T_1330 = eq(_T_1329, UInt<1>(0h0)) \n when _T_1330 : \n node _T_1331 = eq(_T_1328, UInt<1>(0h0)) \n when _T_1331 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_1328, UInt<1>(0h1), \"\") : assert_91 \n node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) \n node _T_1333 = asUInt(reset) \n node _T_1334 = eq(_T_1333, UInt<1>(0h0)) \n when _T_1334 : \n node _T_1335 = eq(_T_1332, UInt<1>(0h0)) \n when _T_1335 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_1332, UInt<1>(0h1), \"\") : assert_92 \n node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) \n when _T_1336 : \n node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1339 = and(_T_1337, _T_1338) \n node _T_1340 = or(UInt<1>(0h0), _T_1339) \n node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1342 = cvt(_T_1341) \n node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000))) \n node _T_1344 = asSInt(_T_1343) \n node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) \n node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1347 = cvt(_T_1346) \n node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) \n node _T_1349 = asSInt(_T_1348) \n node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) \n node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1352 = cvt(_T_1351) \n node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000))) \n node _T_1354 = asSInt(_T_1353) \n node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) \n node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1357 = cvt(_T_1356) \n node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000))) \n node _T_1359 = asSInt(_T_1358) \n node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) \n node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1362 = cvt(_T_1361) \n node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) \n node _T_1364 = asSInt(_T_1363) \n node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) \n node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1367 = cvt(_T_1366) \n node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) \n node _T_1369 = asSInt(_T_1368) \n node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) \n node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1372 = cvt(_T_1371) \n node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) \n node _T_1374 = asSInt(_T_1373) \n node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) \n node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1377 = cvt(_T_1376) \n node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000))) \n node _T_1379 = asSInt(_T_1378) \n node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) \n node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1382 = cvt(_T_1381) \n node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000))) \n node _T_1384 = asSInt(_T_1383) \n node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) \n node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1387 = cvt(_T_1386) \n node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000))) \n node _T_1389 = asSInt(_T_1388) \n node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) \n node _T_1391 = or(_T_1345, _T_1350) \n node _T_1392 = or(_T_1391, _T_1355) \n node _T_1393 = or(_T_1392, _T_1360) \n node _T_1394 = or(_T_1393, _T_1365) \n node _T_1395 = or(_T_1394, _T_1370) \n node _T_1396 = or(_T_1395, _T_1375) \n node _T_1397 = or(_T_1396, _T_1380) \n node _T_1398 = or(_T_1397, _T_1385) \n node _T_1399 = or(_T_1398, _T_1390) \n node _T_1400 = and(_T_1340, _T_1399) \n node _T_1401 = or(UInt<1>(0h0), _T_1400) \n node _T_1402 = and(UInt<1>(0h0), _T_1401) \n node _T_1403 = asUInt(reset) \n node _T_1404 = eq(_T_1403, UInt<1>(0h0)) \n when _T_1404 : \n node _T_1405 = eq(_T_1402, UInt<1>(0h0)) \n when _T_1405 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_1402, UInt<1>(0h1), \"\") : assert_93 \n node _T_1406 = asUInt(reset) \n node _T_1407 = eq(_T_1406, UInt<1>(0h0)) \n when _T_1407 : \n node _T_1408 = eq(address_ok, UInt<1>(0h0)) \n when _T_1408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_94 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_94 \n node _T_1409 = asUInt(reset) \n node _T_1410 = eq(_T_1409, UInt<1>(0h0)) \n when _T_1410 : \n node _T_1411 = eq(legal_source, UInt<1>(0h0)) \n when _T_1411 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_95 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_95 \n node _T_1412 = asUInt(reset) \n node _T_1413 = eq(_T_1412, UInt<1>(0h0)) \n when _T_1413 : \n node _T_1414 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_96 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_96 \n node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0)) \n node _T_1416 = asUInt(reset) \n node _T_1417 = eq(_T_1416, UInt<1>(0h0)) \n when _T_1417 : \n node _T_1418 = eq(_T_1415, UInt<1>(0h0)) \n when _T_1418 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_1415, UInt<1>(0h1), \"\") : assert_97 \n node _T_1419 = eq(io.in.b.bits.mask, mask_1) \n node _T_1420 = asUInt(reset) \n node _T_1421 = eq(_T_1420, UInt<1>(0h0)) \n when _T_1421 : \n node _T_1422 = eq(_T_1419, UInt<1>(0h0)) \n when _T_1422 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_1419, UInt<1>(0h1), \"\") : assert_98 \n node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) \n node _T_1424 = asUInt(reset) \n node _T_1425 = eq(_T_1424, UInt<1>(0h0)) \n when _T_1425 : \n node _T_1426 = eq(_T_1423, UInt<1>(0h0)) \n when _T_1426 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_1423, UInt<1>(0h1), \"\") : assert_99 \n node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) \n when _T_1427 : \n node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1430 = and(_T_1428, _T_1429) \n node _T_1431 = or(UInt<1>(0h0), _T_1430) \n node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1433 = cvt(_T_1432) \n node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000))) \n node _T_1435 = asSInt(_T_1434) \n node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) \n node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1438 = cvt(_T_1437) \n node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000))) \n node _T_1440 = asSInt(_T_1439) \n node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) \n node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1443 = cvt(_T_1442) \n node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000))) \n node _T_1445 = asSInt(_T_1444) \n node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) \n node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1448 = cvt(_T_1447) \n node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000))) \n node _T_1450 = asSInt(_T_1449) \n node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) \n node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1453 = cvt(_T_1452) \n node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) \n node _T_1455 = asSInt(_T_1454) \n node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) \n node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1458 = cvt(_T_1457) \n node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) \n node _T_1460 = asSInt(_T_1459) \n node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) \n node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1463 = cvt(_T_1462) \n node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) \n node _T_1465 = asSInt(_T_1464) \n node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) \n node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1468 = cvt(_T_1467) \n node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000))) \n node _T_1470 = asSInt(_T_1469) \n node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) \n node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1473 = cvt(_T_1472) \n node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000))) \n node _T_1475 = asSInt(_T_1474) \n node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) \n node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1478 = cvt(_T_1477) \n node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000))) \n node _T_1480 = asSInt(_T_1479) \n node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) \n node _T_1482 = or(_T_1436, _T_1441) \n node _T_1483 = or(_T_1482, _T_1446) \n node _T_1484 = or(_T_1483, _T_1451) \n node _T_1485 = or(_T_1484, _T_1456) \n node _T_1486 = or(_T_1485, _T_1461) \n node _T_1487 = or(_T_1486, _T_1466) \n node _T_1488 = or(_T_1487, _T_1471) \n node _T_1489 = or(_T_1488, _T_1476) \n node _T_1490 = or(_T_1489, _T_1481) \n node _T_1491 = and(_T_1431, _T_1490) \n node _T_1492 = or(UInt<1>(0h0), _T_1491) \n node _T_1493 = and(UInt<1>(0h0), _T_1492) \n node _T_1494 = asUInt(reset) \n node _T_1495 = eq(_T_1494, UInt<1>(0h0)) \n when _T_1495 : \n node _T_1496 = eq(_T_1493, UInt<1>(0h0)) \n when _T_1496 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_1493, UInt<1>(0h1), \"\") : assert_100 \n node _T_1497 = asUInt(reset) \n node _T_1498 = eq(_T_1497, UInt<1>(0h0)) \n when _T_1498 : \n node _T_1499 = eq(address_ok, UInt<1>(0h0)) \n when _T_1499 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_101 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_101 \n node _T_1500 = asUInt(reset) \n node _T_1501 = eq(_T_1500, UInt<1>(0h0)) \n when _T_1501 : \n node _T_1502 = eq(legal_source, UInt<1>(0h0)) \n when _T_1502 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_102 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_102 \n node _T_1503 = asUInt(reset) \n node _T_1504 = eq(_T_1503, UInt<1>(0h0)) \n when _T_1504 : \n node _T_1505 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1505 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_103 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_103 \n node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0)) \n node _T_1507 = asUInt(reset) \n node _T_1508 = eq(_T_1507, UInt<1>(0h0)) \n when _T_1508 : \n node _T_1509 = eq(_T_1506, UInt<1>(0h0)) \n when _T_1509 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_1506, UInt<1>(0h1), \"\") : assert_104 \n node _T_1510 = eq(io.in.b.bits.mask, mask_1) \n node _T_1511 = asUInt(reset) \n node _T_1512 = eq(_T_1511, UInt<1>(0h0)) \n when _T_1512 : \n node _T_1513 = eq(_T_1510, UInt<1>(0h0)) \n when _T_1513 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_1510, UInt<1>(0h1), \"\") : assert_105 \n node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) \n when _T_1514 : \n node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1517 = and(_T_1515, _T_1516) \n node _T_1518 = or(UInt<1>(0h0), _T_1517) \n node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1520 = cvt(_T_1519) \n node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000))) \n node _T_1522 = asSInt(_T_1521) \n node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) \n node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1525 = cvt(_T_1524) \n node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) \n node _T_1527 = asSInt(_T_1526) \n node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) \n node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1530 = cvt(_T_1529) \n node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000))) \n node _T_1532 = asSInt(_T_1531) \n node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) \n node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1535 = cvt(_T_1534) \n node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000))) \n node _T_1537 = asSInt(_T_1536) \n node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) \n node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1540 = cvt(_T_1539) \n node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) \n node _T_1542 = asSInt(_T_1541) \n node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) \n node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1545 = cvt(_T_1544) \n node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000))) \n node _T_1547 = asSInt(_T_1546) \n node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) \n node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1550 = cvt(_T_1549) \n node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) \n node _T_1552 = asSInt(_T_1551) \n node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) \n node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1555 = cvt(_T_1554) \n node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000))) \n node _T_1557 = asSInt(_T_1556) \n node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) \n node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1560 = cvt(_T_1559) \n node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) \n node _T_1562 = asSInt(_T_1561) \n node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) \n node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1565 = cvt(_T_1564) \n node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) \n node _T_1567 = asSInt(_T_1566) \n node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) \n node _T_1569 = or(_T_1523, _T_1528) \n node _T_1570 = or(_T_1569, _T_1533) \n node _T_1571 = or(_T_1570, _T_1538) \n node _T_1572 = or(_T_1571, _T_1543) \n node _T_1573 = or(_T_1572, _T_1548) \n node _T_1574 = or(_T_1573, _T_1553) \n node _T_1575 = or(_T_1574, _T_1558) \n node _T_1576 = or(_T_1575, _T_1563) \n node _T_1577 = or(_T_1576, _T_1568) \n node _T_1578 = and(_T_1518, _T_1577) \n node _T_1579 = or(UInt<1>(0h0), _T_1578) \n node _T_1580 = and(UInt<1>(0h0), _T_1579) \n node _T_1581 = asUInt(reset) \n node _T_1582 = eq(_T_1581, UInt<1>(0h0)) \n when _T_1582 : \n node _T_1583 = eq(_T_1580, UInt<1>(0h0)) \n when _T_1583 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_1580, UInt<1>(0h1), \"\") : assert_106 \n node _T_1584 = asUInt(reset) \n node _T_1585 = eq(_T_1584, UInt<1>(0h0)) \n when _T_1585 : \n node _T_1586 = eq(address_ok, UInt<1>(0h0)) \n when _T_1586 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_107 \n node _T_1587 = asUInt(reset) \n node _T_1588 = eq(_T_1587, UInt<1>(0h0)) \n when _T_1588 : \n node _T_1589 = eq(legal_source, UInt<1>(0h0)) \n when _T_1589 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_108 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_108 \n node _T_1590 = asUInt(reset) \n node _T_1591 = eq(_T_1590, UInt<1>(0h0)) \n when _T_1591 : \n node _T_1592 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1592 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_109 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_109 \n node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0)) \n node _T_1594 = asUInt(reset) \n node _T_1595 = eq(_T_1594, UInt<1>(0h0)) \n when _T_1595 : \n node _T_1596 = eq(_T_1593, UInt<1>(0h0)) \n when _T_1596 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_1593, UInt<1>(0h1), \"\") : assert_110 \n node _T_1597 = not(mask_1) \n node _T_1598 = and(io.in.b.bits.mask, _T_1597) \n node _T_1599 = eq(_T_1598, UInt<1>(0h0)) \n node _T_1600 = asUInt(reset) \n node _T_1601 = eq(_T_1600, UInt<1>(0h0)) \n when _T_1601 : \n node _T_1602 = eq(_T_1599, UInt<1>(0h0)) \n when _T_1602 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_1599, UInt<1>(0h1), \"\") : assert_111 \n node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) \n when _T_1603 : \n node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1606 = and(_T_1604, _T_1605) \n node _T_1607 = or(UInt<1>(0h0), _T_1606) \n node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1609 = cvt(_T_1608) \n node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000))) \n node _T_1611 = asSInt(_T_1610) \n node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) \n node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1614 = cvt(_T_1613) \n node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) \n node _T_1616 = asSInt(_T_1615) \n node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) \n node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1619 = cvt(_T_1618) \n node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000))) \n node _T_1621 = asSInt(_T_1620) \n node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) \n node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1624 = cvt(_T_1623) \n node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000))) \n node _T_1626 = asSInt(_T_1625) \n node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) \n node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1629 = cvt(_T_1628) \n node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) \n node _T_1631 = asSInt(_T_1630) \n node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) \n node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1634 = cvt(_T_1633) \n node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000))) \n node _T_1636 = asSInt(_T_1635) \n node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) \n node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1639 = cvt(_T_1638) \n node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) \n node _T_1641 = asSInt(_T_1640) \n node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) \n node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1644 = cvt(_T_1643) \n node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000))) \n node _T_1646 = asSInt(_T_1645) \n node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) \n node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1649 = cvt(_T_1648) \n node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000))) \n node _T_1651 = asSInt(_T_1650) \n node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) \n node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1654 = cvt(_T_1653) \n node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000))) \n node _T_1656 = asSInt(_T_1655) \n node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) \n node _T_1658 = or(_T_1612, _T_1617) \n node _T_1659 = or(_T_1658, _T_1622) \n node _T_1660 = or(_T_1659, _T_1627) \n node _T_1661 = or(_T_1660, _T_1632) \n node _T_1662 = or(_T_1661, _T_1637) \n node _T_1663 = or(_T_1662, _T_1642) \n node _T_1664 = or(_T_1663, _T_1647) \n node _T_1665 = or(_T_1664, _T_1652) \n node _T_1666 = or(_T_1665, _T_1657) \n node _T_1667 = and(_T_1607, _T_1666) \n node _T_1668 = or(UInt<1>(0h0), _T_1667) \n node _T_1669 = and(UInt<1>(0h0), _T_1668) \n node _T_1670 = asUInt(reset) \n node _T_1671 = eq(_T_1670, UInt<1>(0h0)) \n when _T_1671 : \n node _T_1672 = eq(_T_1669, UInt<1>(0h0)) \n when _T_1672 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_1669, UInt<1>(0h1), \"\") : assert_112 \n node _T_1673 = asUInt(reset) \n node _T_1674 = eq(_T_1673, UInt<1>(0h0)) \n when _T_1674 : \n node _T_1675 = eq(address_ok, UInt<1>(0h0)) \n when _T_1675 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_113 \n node _T_1676 = asUInt(reset) \n node _T_1677 = eq(_T_1676, UInt<1>(0h0)) \n when _T_1677 : \n node _T_1678 = eq(legal_source, UInt<1>(0h0)) \n when _T_1678 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_114 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_114 \n node _T_1679 = asUInt(reset) \n node _T_1680 = eq(_T_1679, UInt<1>(0h0)) \n when _T_1680 : \n node _T_1681 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1681 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_115 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_115 \n node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4)) \n node _T_1683 = asUInt(reset) \n node _T_1684 = eq(_T_1683, UInt<1>(0h0)) \n when _T_1684 : \n node _T_1685 = eq(_T_1682, UInt<1>(0h0)) \n when _T_1685 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_116 \n assert(clock, _T_1682, UInt<1>(0h1), \"\") : assert_116 \n node _T_1686 = eq(io.in.b.bits.mask, mask_1) \n node _T_1687 = asUInt(reset) \n node _T_1688 = eq(_T_1687, UInt<1>(0h0)) \n when _T_1688 : \n node _T_1689 = eq(_T_1686, UInt<1>(0h0)) \n when _T_1689 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_117 \n assert(clock, _T_1686, UInt<1>(0h1), \"\") : assert_117 \n node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) \n when _T_1690 : \n node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1693 = and(_T_1691, _T_1692) \n node _T_1694 = or(UInt<1>(0h0), _T_1693) \n node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1696 = cvt(_T_1695) \n node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000))) \n node _T_1698 = asSInt(_T_1697) \n node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0))) \n node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1701 = cvt(_T_1700) \n node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000))) \n node _T_1703 = asSInt(_T_1702) \n node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0))) \n node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1706 = cvt(_T_1705) \n node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000))) \n node _T_1708 = asSInt(_T_1707) \n node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) \n node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1711 = cvt(_T_1710) \n node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000))) \n node _T_1713 = asSInt(_T_1712) \n node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) \n node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1716 = cvt(_T_1715) \n node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) \n node _T_1718 = asSInt(_T_1717) \n node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) \n node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1721 = cvt(_T_1720) \n node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000))) \n node _T_1723 = asSInt(_T_1722) \n node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) \n node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1726 = cvt(_T_1725) \n node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) \n node _T_1728 = asSInt(_T_1727) \n node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) \n node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1731 = cvt(_T_1730) \n node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000))) \n node _T_1733 = asSInt(_T_1732) \n node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) \n node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1736 = cvt(_T_1735) \n node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000))) \n node _T_1738 = asSInt(_T_1737) \n node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) \n node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1741 = cvt(_T_1740) \n node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000))) \n node _T_1743 = asSInt(_T_1742) \n node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) \n node _T_1745 = or(_T_1699, _T_1704) \n node _T_1746 = or(_T_1745, _T_1709) \n node _T_1747 = or(_T_1746, _T_1714) \n node _T_1748 = or(_T_1747, _T_1719) \n node _T_1749 = or(_T_1748, _T_1724) \n node _T_1750 = or(_T_1749, _T_1729) \n node _T_1751 = or(_T_1750, _T_1734) \n node _T_1752 = or(_T_1751, _T_1739) \n node _T_1753 = or(_T_1752, _T_1744) \n node _T_1754 = and(_T_1694, _T_1753) \n node _T_1755 = or(UInt<1>(0h0), _T_1754) \n node _T_1756 = and(UInt<1>(0h0), _T_1755) \n node _T_1757 = asUInt(reset) \n node _T_1758 = eq(_T_1757, UInt<1>(0h0)) \n when _T_1758 : \n node _T_1759 = eq(_T_1756, UInt<1>(0h0)) \n when _T_1759 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_118 \n assert(clock, _T_1756, UInt<1>(0h1), \"\") : assert_118 \n node _T_1760 = asUInt(reset) \n node _T_1761 = eq(_T_1760, UInt<1>(0h0)) \n when _T_1761 : \n node _T_1762 = eq(address_ok, UInt<1>(0h0)) \n when _T_1762 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_119 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_119 \n node _T_1763 = asUInt(reset) \n node _T_1764 = eq(_T_1763, UInt<1>(0h0)) \n when _T_1764 : \n node _T_1765 = eq(legal_source, UInt<1>(0h0)) \n when _T_1765 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_120 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_120 \n node _T_1766 = asUInt(reset) \n node _T_1767 = eq(_T_1766, UInt<1>(0h0)) \n when _T_1767 : \n node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1768 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_121 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_121 \n node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3)) \n node _T_1770 = asUInt(reset) \n node _T_1771 = eq(_T_1770, UInt<1>(0h0)) \n when _T_1771 : \n node _T_1772 = eq(_T_1769, UInt<1>(0h0)) \n when _T_1772 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_122 \n assert(clock, _T_1769, UInt<1>(0h1), \"\") : assert_122 \n node _T_1773 = eq(io.in.b.bits.mask, mask_1) \n node _T_1774 = asUInt(reset) \n node _T_1775 = eq(_T_1774, UInt<1>(0h0)) \n when _T_1775 : \n node _T_1776 = eq(_T_1773, UInt<1>(0h0)) \n when _T_1776 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_123 \n assert(clock, _T_1773, UInt<1>(0h1), \"\") : assert_123 \n node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) \n when _T_1777 : \n node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) \n node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) \n node _T_1780 = and(_T_1778, _T_1779) \n node _T_1781 = or(UInt<1>(0h0), _T_1780) \n node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) \n node _T_1783 = cvt(_T_1782) \n node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) \n node _T_1785 = asSInt(_T_1784) \n node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) \n node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) \n node _T_1788 = cvt(_T_1787) \n node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) \n node _T_1790 = asSInt(_T_1789) \n node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) \n node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) \n node _T_1793 = cvt(_T_1792) \n node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) \n node _T_1795 = asSInt(_T_1794) \n node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) \n node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000)) \n node _T_1798 = cvt(_T_1797) \n node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000))) \n node _T_1800 = asSInt(_T_1799) \n node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) \n node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) \n node _T_1803 = cvt(_T_1802) \n node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) \n node _T_1805 = asSInt(_T_1804) \n node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) \n node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) \n node _T_1808 = cvt(_T_1807) \n node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000))) \n node _T_1810 = asSInt(_T_1809) \n node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) \n node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) \n node _T_1813 = cvt(_T_1812) \n node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) \n node _T_1815 = asSInt(_T_1814) \n node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) \n node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) \n node _T_1818 = cvt(_T_1817) \n node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000))) \n node _T_1820 = asSInt(_T_1819) \n node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) \n node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) \n node _T_1823 = cvt(_T_1822) \n node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000))) \n node _T_1825 = asSInt(_T_1824) \n node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) \n node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) \n node _T_1828 = cvt(_T_1827) \n node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000))) \n node _T_1830 = asSInt(_T_1829) \n node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) \n node _T_1832 = or(_T_1786, _T_1791) \n node _T_1833 = or(_T_1832, _T_1796) \n node _T_1834 = or(_T_1833, _T_1801) \n node _T_1835 = or(_T_1834, _T_1806) \n node _T_1836 = or(_T_1835, _T_1811) \n node _T_1837 = or(_T_1836, _T_1816) \n node _T_1838 = or(_T_1837, _T_1821) \n node _T_1839 = or(_T_1838, _T_1826) \n node _T_1840 = or(_T_1839, _T_1831) \n node _T_1841 = and(_T_1781, _T_1840) \n node _T_1842 = or(UInt<1>(0h0), _T_1841) \n node _T_1843 = and(UInt<1>(0h0), _T_1842) \n node _T_1844 = asUInt(reset) \n node _T_1845 = eq(_T_1844, UInt<1>(0h0)) \n when _T_1845 : \n node _T_1846 = eq(_T_1843, UInt<1>(0h0)) \n when _T_1846 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_124 \n assert(clock, _T_1843, UInt<1>(0h1), \"\") : assert_124 \n node _T_1847 = asUInt(reset) \n node _T_1848 = eq(_T_1847, UInt<1>(0h0)) \n when _T_1848 : \n node _T_1849 = eq(address_ok, UInt<1>(0h0)) \n when _T_1849 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_125 \n assert(clock, address_ok, UInt<1>(0h1), \"\") : assert_125 \n node _T_1850 = asUInt(reset) \n node _T_1851 = eq(_T_1850, UInt<1>(0h0)) \n when _T_1851 : \n node _T_1852 = eq(legal_source, UInt<1>(0h0)) \n when _T_1852 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_126 \n assert(clock, legal_source, UInt<1>(0h1), \"\") : assert_126 \n node _T_1853 = asUInt(reset) \n node _T_1854 = eq(_T_1853, UInt<1>(0h0)) \n when _T_1854 : \n node _T_1855 = eq(is_aligned_1, UInt<1>(0h0)) \n when _T_1855 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_127 \n assert(clock, is_aligned_1, UInt<1>(0h1), \"\") : assert_127 \n node _T_1856 = eq(io.in.b.bits.mask, mask_1) \n node _T_1857 = asUInt(reset) \n node _T_1858 = eq(_T_1857, UInt<1>(0h0)) \n when _T_1858 : \n node _T_1859 = eq(_T_1856, UInt<1>(0h0)) \n when _T_1859 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_128 \n assert(clock, _T_1856, UInt<1>(0h1), \"\") : assert_128 \n node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) \n node _T_1861 = asUInt(reset) \n node _T_1862 = eq(_T_1861, UInt<1>(0h0)) \n when _T_1862 : \n node _T_1863 = eq(_T_1860, UInt<1>(0h0)) \n when _T_1863 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_129 \n assert(clock, _T_1860, UInt<1>(0h1), \"\") : assert_129 \n when io.in.c.valid : \n node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) \n node _T_1865 = asUInt(reset) \n node _T_1866 = eq(_T_1865, UInt<1>(0h0)) \n when _T_1866 : \n node _T_1867 = eq(_T_1864, UInt<1>(0h0)) \n when _T_1867 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_130 \n assert(clock, _T_1864, UInt<1>(0h1), \"\") : assert_130 \n node _source_ok_T_18 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) \n node _source_ok_T_19 = shr(io.in.c.bits.source, 2) \n node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h0)) \n node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) \n node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) \n node _source_ok_T_23 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) \n node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) \n node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n wire _source_ok_WIRE_2 : UInt<1>[3] \n connect _source_ok_WIRE_2[0], _source_ok_T_18 \n connect _source_ok_WIRE_2[1], _source_ok_T_24 \n connect _source_ok_WIRE_2[2], _source_ok_T_25 \n node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) \n node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) \n node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) \n node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) \n node is_aligned_mask_2 = not(_is_aligned_mask_T_5) \n node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) \n node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) \n node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _address_ok_T_71 = cvt(_address_ok_T_70) \n node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_73 = asSInt(_address_ok_T_72) \n node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) \n node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) \n node _address_ok_T_76 = cvt(_address_ok_T_75) \n node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_78 = asSInt(_address_ok_T_77) \n node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) \n node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) \n node _address_ok_T_81 = cvt(_address_ok_T_80) \n node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_83 = asSInt(_address_ok_T_82) \n node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) \n node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) \n node _address_ok_T_86 = cvt(_address_ok_T_85) \n node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_88 = asSInt(_address_ok_T_87) \n node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) \n node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) \n node _address_ok_T_91 = cvt(_address_ok_T_90) \n node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_93 = asSInt(_address_ok_T_92) \n node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) \n node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) \n node _address_ok_T_96 = cvt(_address_ok_T_95) \n node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_98 = asSInt(_address_ok_T_97) \n node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) \n node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) \n node _address_ok_T_101 = cvt(_address_ok_T_100) \n node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_103 = asSInt(_address_ok_T_102) \n node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) \n node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) \n node _address_ok_T_106 = cvt(_address_ok_T_105) \n node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_108 = asSInt(_address_ok_T_107) \n node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) \n node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) \n node _address_ok_T_111 = cvt(_address_ok_T_110) \n node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) \n node _address_ok_T_113 = asSInt(_address_ok_T_112) \n node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) \n node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) \n node _address_ok_T_116 = cvt(_address_ok_T_115) \n node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) \n node _address_ok_T_118 = asSInt(_address_ok_T_117) \n node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) \n node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) \n node _address_ok_T_121 = cvt(_address_ok_T_120) \n node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) \n node _address_ok_T_123 = asSInt(_address_ok_T_122) \n node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) \n node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) \n node _address_ok_T_126 = cvt(_address_ok_T_125) \n node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) \n node _address_ok_T_128 = asSInt(_address_ok_T_127) \n node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) \n wire _address_ok_WIRE_1 : UInt<1>[12] \n connect _address_ok_WIRE_1[0], _address_ok_T_74 \n connect _address_ok_WIRE_1[1], _address_ok_T_79 \n connect _address_ok_WIRE_1[2], _address_ok_T_84 \n connect _address_ok_WIRE_1[3], _address_ok_T_89 \n connect _address_ok_WIRE_1[4], _address_ok_T_94 \n connect _address_ok_WIRE_1[5], _address_ok_T_99 \n connect _address_ok_WIRE_1[6], _address_ok_T_104 \n connect _address_ok_WIRE_1[7], _address_ok_T_109 \n connect _address_ok_WIRE_1[8], _address_ok_T_114 \n connect _address_ok_WIRE_1[9], _address_ok_T_119 \n connect _address_ok_WIRE_1[10], _address_ok_T_124 \n connect _address_ok_WIRE_1[11], _address_ok_T_129 \n node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) \n node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) \n node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) \n node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) \n node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) \n node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) \n node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) \n node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) \n node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) \n node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) \n node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) \n node _T_1868 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _T_1869 = eq(_T_1868, UInt<1>(0h0)) \n node _T_1870 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_1871 = cvt(_T_1870) \n node _T_1872 = and(_T_1871, asSInt(UInt<1>(0h0))) \n node _T_1873 = asSInt(_T_1872) \n node _T_1874 = eq(_T_1873, asSInt(UInt<1>(0h0))) \n node _T_1875 = or(_T_1869, _T_1874) \n node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) \n node _T_1876 = shr(io.in.c.bits.source, 2) \n node _T_1877 = eq(_T_1876, UInt<1>(0h0)) \n node _T_1878 = leq(UInt<1>(0h0), uncommonBits_13) \n node _T_1879 = and(_T_1877, _T_1878) \n node _T_1880 = leq(uncommonBits_13, UInt<2>(0h3)) \n node _T_1881 = and(_T_1879, _T_1880) \n node _T_1882 = eq(_T_1881, UInt<1>(0h0)) \n node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_1884 = cvt(_T_1883) \n node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0))) \n node _T_1886 = asSInt(_T_1885) \n node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0))) \n node _T_1888 = or(_T_1882, _T_1887) \n node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n node _T_1890 = eq(_T_1889, UInt<1>(0h0)) \n node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_1892 = cvt(_T_1891) \n node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0))) \n node _T_1894 = asSInt(_T_1893) \n node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) \n node _T_1896 = or(_T_1890, _T_1895) \n node _T_1897 = and(_T_1875, _T_1888) \n node _T_1898 = and(_T_1897, _T_1896) \n node _T_1899 = asUInt(reset) \n node _T_1900 = eq(_T_1899, UInt<1>(0h0)) \n when _T_1900 : \n node _T_1901 = eq(_T_1898, UInt<1>(0h0)) \n when _T_1901 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_131 \n assert(clock, _T_1898, UInt<1>(0h1), \"\") : assert_131 \n node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) \n when _T_1902 : \n node _T_1903 = asUInt(reset) \n node _T_1904 = eq(_T_1903, UInt<1>(0h0)) \n when _T_1904 : \n node _T_1905 = eq(address_ok_1, UInt<1>(0h0)) \n when _T_1905 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_132 \n assert(clock, address_ok_1, UInt<1>(0h1), \"\") : assert_132 \n node _T_1906 = asUInt(reset) \n node _T_1907 = eq(_T_1906, UInt<1>(0h0)) \n when _T_1907 : \n node _T_1908 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_1908 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_133 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_133 \n node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3)) \n node _T_1910 = asUInt(reset) \n node _T_1911 = eq(_T_1910, UInt<1>(0h0)) \n when _T_1911 : \n node _T_1912 = eq(_T_1909, UInt<1>(0h0)) \n when _T_1912 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_134 \n assert(clock, _T_1909, UInt<1>(0h1), \"\") : assert_134 \n node _T_1913 = asUInt(reset) \n node _T_1914 = eq(_T_1913, UInt<1>(0h0)) \n when _T_1914 : \n node _T_1915 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_1915 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_135 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_135 \n node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5)) \n node _T_1917 = asUInt(reset) \n node _T_1918 = eq(_T_1917, UInt<1>(0h0)) \n when _T_1918 : \n node _T_1919 = eq(_T_1916, UInt<1>(0h0)) \n when _T_1919 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_136 \n assert(clock, _T_1916, UInt<1>(0h1), \"\") : assert_136 \n node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) \n node _T_1921 = asUInt(reset) \n node _T_1922 = eq(_T_1921, UInt<1>(0h0)) \n when _T_1922 : \n node _T_1923 = eq(_T_1920, UInt<1>(0h0)) \n when _T_1923 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_137 \n assert(clock, _T_1920, UInt<1>(0h1), \"\") : assert_137 \n node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) \n when _T_1924 : \n node _T_1925 = asUInt(reset) \n node _T_1926 = eq(_T_1925, UInt<1>(0h0)) \n when _T_1926 : \n node _T_1927 = eq(address_ok_1, UInt<1>(0h0)) \n when _T_1927 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_138 \n assert(clock, address_ok_1, UInt<1>(0h1), \"\") : assert_138 \n node _T_1928 = asUInt(reset) \n node _T_1929 = eq(_T_1928, UInt<1>(0h0)) \n when _T_1929 : \n node _T_1930 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_1930 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_139 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_139 \n node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3)) \n node _T_1932 = asUInt(reset) \n node _T_1933 = eq(_T_1932, UInt<1>(0h0)) \n when _T_1933 : \n node _T_1934 = eq(_T_1931, UInt<1>(0h0)) \n when _T_1934 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_140 \n assert(clock, _T_1931, UInt<1>(0h1), \"\") : assert_140 \n node _T_1935 = asUInt(reset) \n node _T_1936 = eq(_T_1935, UInt<1>(0h0)) \n when _T_1936 : \n node _T_1937 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_1937 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_141 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_141 \n node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5)) \n node _T_1939 = asUInt(reset) \n node _T_1940 = eq(_T_1939, UInt<1>(0h0)) \n when _T_1940 : \n node _T_1941 = eq(_T_1938, UInt<1>(0h0)) \n when _T_1941 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_142 \n assert(clock, _T_1938, UInt<1>(0h1), \"\") : assert_142 \n node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) \n when _T_1942 : \n node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size) \n node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc)) \n node _T_1945 = and(_T_1943, _T_1944) \n node _T_1946 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) \n node _T_1947 = shr(io.in.c.bits.source, 2) \n node _T_1948 = eq(_T_1947, UInt<1>(0h0)) \n node _T_1949 = leq(UInt<1>(0h0), uncommonBits_14) \n node _T_1950 = and(_T_1948, _T_1949) \n node _T_1951 = leq(uncommonBits_14, UInt<2>(0h3)) \n node _T_1952 = and(_T_1950, _T_1951) \n node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n node _T_1954 = or(_T_1946, _T_1952) \n node _T_1955 = or(_T_1954, _T_1953) \n node _T_1956 = and(_T_1945, _T_1955) \n node _T_1957 = or(UInt<1>(0h0), _T_1956) \n node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_1960 = cvt(_T_1959) \n node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000))) \n node _T_1962 = asSInt(_T_1961) \n node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0))) \n node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000)) \n node _T_1965 = cvt(_T_1964) \n node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000))) \n node _T_1967 = asSInt(_T_1966) \n node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0))) \n node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000)) \n node _T_1970 = cvt(_T_1969) \n node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000))) \n node _T_1972 = asSInt(_T_1971) \n node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) \n node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000)) \n node _T_1975 = cvt(_T_1974) \n node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000))) \n node _T_1977 = asSInt(_T_1976) \n node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) \n node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) \n node _T_1980 = cvt(_T_1979) \n node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) \n node _T_1982 = asSInt(_T_1981) \n node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) \n node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) \n node _T_1985 = cvt(_T_1984) \n node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000))) \n node _T_1987 = asSInt(_T_1986) \n node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) \n node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) \n node _T_1990 = cvt(_T_1989) \n node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000))) \n node _T_1992 = asSInt(_T_1991) \n node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) \n node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) \n node _T_1995 = cvt(_T_1994) \n node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) \n node _T_1997 = asSInt(_T_1996) \n node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) \n node _T_1999 = or(_T_1963, _T_1968) \n node _T_2000 = or(_T_1999, _T_1973) \n node _T_2001 = or(_T_2000, _T_1978) \n node _T_2002 = or(_T_2001, _T_1983) \n node _T_2003 = or(_T_2002, _T_1988) \n node _T_2004 = or(_T_2003, _T_1993) \n node _T_2005 = or(_T_2004, _T_1998) \n node _T_2006 = and(_T_1958, _T_2005) \n node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size) \n node _T_2008 = or(UInt<1>(0h0), _T_2007) \n node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) \n node _T_2010 = cvt(_T_2009) \n node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000))) \n node _T_2012 = asSInt(_T_2011) \n node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0))) \n node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) \n node _T_2015 = cvt(_T_2014) \n node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000))) \n node _T_2017 = asSInt(_T_2016) \n node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0))) \n node _T_2019 = or(_T_2013, _T_2018) \n node _T_2020 = and(_T_2008, _T_2019) \n node _T_2021 = or(UInt<1>(0h0), _T_2006) \n node _T_2022 = or(_T_2021, _T_2020) \n node _T_2023 = and(_T_1957, _T_2022) \n node _T_2024 = asUInt(reset) \n node _T_2025 = eq(_T_2024, UInt<1>(0h0)) \n when _T_2025 : \n node _T_2026 = eq(_T_2023, UInt<1>(0h0)) \n when _T_2026 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_143 \n assert(clock, _T_2023, UInt<1>(0h1), \"\") : assert_143 \n node _T_2027 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) \n node _T_2028 = shr(io.in.c.bits.source, 2) \n node _T_2029 = eq(_T_2028, UInt<1>(0h0)) \n node _T_2030 = leq(UInt<1>(0h0), uncommonBits_15) \n node _T_2031 = and(_T_2029, _T_2030) \n node _T_2032 = leq(uncommonBits_15, UInt<2>(0h3)) \n node _T_2033 = and(_T_2031, _T_2032) \n node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n wire _WIRE_6 : UInt<1>[3] \n connect _WIRE_6[0], _T_2027 \n connect _WIRE_6[1], _T_2033 \n connect _WIRE_6[2], _T_2034 \n node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size) \n node _T_2036 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_2037 = mux(_WIRE_6[1], _T_2035, UInt<1>(0h0)) \n node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_2039 = or(_T_2036, _T_2037) \n node _T_2040 = or(_T_2039, _T_2038) \n wire _WIRE_7 : UInt<1> \n connect _WIRE_7, _T_2040 \n node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size) \n node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc)) \n node _T_2043 = and(_T_2041, _T_2042) \n node _T_2044 = or(UInt<1>(0h0), _T_2043) \n node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_2046 = cvt(_T_2045) \n node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000))) \n node _T_2048 = asSInt(_T_2047) \n node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0))) \n node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000)) \n node _T_2051 = cvt(_T_2050) \n node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000))) \n node _T_2053 = asSInt(_T_2052) \n node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0))) \n node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000)) \n node _T_2056 = cvt(_T_2055) \n node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000))) \n node _T_2058 = asSInt(_T_2057) \n node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) \n node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000)) \n node _T_2061 = cvt(_T_2060) \n node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000))) \n node _T_2063 = asSInt(_T_2062) \n node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) \n node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) \n node _T_2066 = cvt(_T_2065) \n node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) \n node _T_2068 = asSInt(_T_2067) \n node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) \n node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) \n node _T_2071 = cvt(_T_2070) \n node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000))) \n node _T_2073 = asSInt(_T_2072) \n node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) \n node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) \n node _T_2076 = cvt(_T_2075) \n node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) \n node _T_2078 = asSInt(_T_2077) \n node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) \n node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) \n node _T_2081 = cvt(_T_2080) \n node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000))) \n node _T_2083 = asSInt(_T_2082) \n node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) \n node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) \n node _T_2086 = cvt(_T_2085) \n node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) \n node _T_2088 = asSInt(_T_2087) \n node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) \n node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) \n node _T_2091 = cvt(_T_2090) \n node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000))) \n node _T_2093 = asSInt(_T_2092) \n node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) \n node _T_2095 = or(_T_2049, _T_2054) \n node _T_2096 = or(_T_2095, _T_2059) \n node _T_2097 = or(_T_2096, _T_2064) \n node _T_2098 = or(_T_2097, _T_2069) \n node _T_2099 = or(_T_2098, _T_2074) \n node _T_2100 = or(_T_2099, _T_2079) \n node _T_2101 = or(_T_2100, _T_2084) \n node _T_2102 = or(_T_2101, _T_2089) \n node _T_2103 = or(_T_2102, _T_2094) \n node _T_2104 = and(_T_2044, _T_2103) \n node _T_2105 = or(UInt<1>(0h0), _T_2104) \n node _T_2106 = and(_WIRE_7, _T_2105) \n node _T_2107 = asUInt(reset) \n node _T_2108 = eq(_T_2107, UInt<1>(0h0)) \n when _T_2108 : \n node _T_2109 = eq(_T_2106, UInt<1>(0h0)) \n when _T_2109 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_144 \n assert(clock, _T_2106, UInt<1>(0h1), \"\") : assert_144 \n node _T_2110 = asUInt(reset) \n node _T_2111 = eq(_T_2110, UInt<1>(0h0)) \n when _T_2111 : \n node _T_2112 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_2112 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_145 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_145 \n node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3)) \n node _T_2114 = asUInt(reset) \n node _T_2115 = eq(_T_2114, UInt<1>(0h0)) \n when _T_2115 : \n node _T_2116 = eq(_T_2113, UInt<1>(0h0)) \n when _T_2116 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_146 \n assert(clock, _T_2113, UInt<1>(0h1), \"\") : assert_146 \n node _T_2117 = asUInt(reset) \n node _T_2118 = eq(_T_2117, UInt<1>(0h0)) \n when _T_2118 : \n node _T_2119 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_2119 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_147 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_147 \n node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5)) \n node _T_2121 = asUInt(reset) \n node _T_2122 = eq(_T_2121, UInt<1>(0h0)) \n when _T_2122 : \n node _T_2123 = eq(_T_2120, UInt<1>(0h0)) \n when _T_2123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_148 \n assert(clock, _T_2120, UInt<1>(0h1), \"\") : assert_148 \n node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) \n node _T_2125 = asUInt(reset) \n node _T_2126 = eq(_T_2125, UInt<1>(0h0)) \n when _T_2126 : \n node _T_2127 = eq(_T_2124, UInt<1>(0h0)) \n when _T_2127 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_149 \n assert(clock, _T_2124, UInt<1>(0h1), \"\") : assert_149 \n node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) \n when _T_2128 : \n node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size) \n node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc)) \n node _T_2131 = and(_T_2129, _T_2130) \n node _T_2132 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) \n node _T_2133 = shr(io.in.c.bits.source, 2) \n node _T_2134 = eq(_T_2133, UInt<1>(0h0)) \n node _T_2135 = leq(UInt<1>(0h0), uncommonBits_16) \n node _T_2136 = and(_T_2134, _T_2135) \n node _T_2137 = leq(uncommonBits_16, UInt<2>(0h3)) \n node _T_2138 = and(_T_2136, _T_2137) \n node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n node _T_2140 = or(_T_2132, _T_2138) \n node _T_2141 = or(_T_2140, _T_2139) \n node _T_2142 = and(_T_2131, _T_2141) \n node _T_2143 = or(UInt<1>(0h0), _T_2142) \n node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_2146 = cvt(_T_2145) \n node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000))) \n node _T_2148 = asSInt(_T_2147) \n node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0))) \n node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000)) \n node _T_2151 = cvt(_T_2150) \n node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) \n node _T_2153 = asSInt(_T_2152) \n node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) \n node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000)) \n node _T_2156 = cvt(_T_2155) \n node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000))) \n node _T_2158 = asSInt(_T_2157) \n node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) \n node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000)) \n node _T_2161 = cvt(_T_2160) \n node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000))) \n node _T_2163 = asSInt(_T_2162) \n node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) \n node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) \n node _T_2166 = cvt(_T_2165) \n node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) \n node _T_2168 = asSInt(_T_2167) \n node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) \n node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) \n node _T_2171 = cvt(_T_2170) \n node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000))) \n node _T_2173 = asSInt(_T_2172) \n node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) \n node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) \n node _T_2176 = cvt(_T_2175) \n node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000))) \n node _T_2178 = asSInt(_T_2177) \n node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) \n node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) \n node _T_2181 = cvt(_T_2180) \n node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) \n node _T_2183 = asSInt(_T_2182) \n node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) \n node _T_2185 = or(_T_2149, _T_2154) \n node _T_2186 = or(_T_2185, _T_2159) \n node _T_2187 = or(_T_2186, _T_2164) \n node _T_2188 = or(_T_2187, _T_2169) \n node _T_2189 = or(_T_2188, _T_2174) \n node _T_2190 = or(_T_2189, _T_2179) \n node _T_2191 = or(_T_2190, _T_2184) \n node _T_2192 = and(_T_2144, _T_2191) \n node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size) \n node _T_2194 = or(UInt<1>(0h0), _T_2193) \n node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) \n node _T_2196 = cvt(_T_2195) \n node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000))) \n node _T_2198 = asSInt(_T_2197) \n node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0))) \n node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) \n node _T_2201 = cvt(_T_2200) \n node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000))) \n node _T_2203 = asSInt(_T_2202) \n node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0))) \n node _T_2205 = or(_T_2199, _T_2204) \n node _T_2206 = and(_T_2194, _T_2205) \n node _T_2207 = or(UInt<1>(0h0), _T_2192) \n node _T_2208 = or(_T_2207, _T_2206) \n node _T_2209 = and(_T_2143, _T_2208) \n node _T_2210 = asUInt(reset) \n node _T_2211 = eq(_T_2210, UInt<1>(0h0)) \n when _T_2211 : \n node _T_2212 = eq(_T_2209, UInt<1>(0h0)) \n when _T_2212 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_150 \n assert(clock, _T_2209, UInt<1>(0h1), \"\") : assert_150 \n node _T_2213 = eq(io.in.c.bits.source, UInt<4>(0h8)) \n node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) \n node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) \n node _T_2214 = shr(io.in.c.bits.source, 2) \n node _T_2215 = eq(_T_2214, UInt<1>(0h0)) \n node _T_2216 = leq(UInt<1>(0h0), uncommonBits_17) \n node _T_2217 = and(_T_2215, _T_2216) \n node _T_2218 = leq(uncommonBits_17, UInt<2>(0h3)) \n node _T_2219 = and(_T_2217, _T_2218) \n node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4)) \n wire _WIRE_8 : UInt<1>[3] \n connect _WIRE_8[0], _T_2213 \n connect _WIRE_8[1], _T_2219 \n connect _WIRE_8[2], _T_2220 \n node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size) \n node _T_2222 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_2223 = mux(_WIRE_8[1], _T_2221, UInt<1>(0h0)) \n node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) \n node _T_2225 = or(_T_2222, _T_2223) \n node _T_2226 = or(_T_2225, _T_2224) \n wire _WIRE_9 : UInt<1> \n connect _WIRE_9, _T_2226 \n node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size) \n node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc)) \n node _T_2229 = and(_T_2227, _T_2228) \n node _T_2230 = or(UInt<1>(0h0), _T_2229) \n node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0)) \n node _T_2232 = cvt(_T_2231) \n node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000))) \n node _T_2234 = asSInt(_T_2233) \n node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0))) \n node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000)) \n node _T_2237 = cvt(_T_2236) \n node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000))) \n node _T_2239 = asSInt(_T_2238) \n node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0))) \n node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000)) \n node _T_2242 = cvt(_T_2241) \n node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000))) \n node _T_2244 = asSInt(_T_2243) \n node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) \n node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000)) \n node _T_2247 = cvt(_T_2246) \n node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000))) \n node _T_2249 = asSInt(_T_2248) \n node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) \n node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) \n node _T_2252 = cvt(_T_2251) \n node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) \n node _T_2254 = asSInt(_T_2253) \n node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) \n node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) \n node _T_2257 = cvt(_T_2256) \n node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000))) \n node _T_2259 = asSInt(_T_2258) \n node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) \n node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) \n node _T_2262 = cvt(_T_2261) \n node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) \n node _T_2264 = asSInt(_T_2263) \n node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) \n node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) \n node _T_2267 = cvt(_T_2266) \n node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000))) \n node _T_2269 = asSInt(_T_2268) \n node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) \n node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) \n node _T_2272 = cvt(_T_2271) \n node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000))) \n node _T_2274 = asSInt(_T_2273) \n node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) \n node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) \n node _T_2277 = cvt(_T_2276) \n node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000))) \n node _T_2279 = asSInt(_T_2278) \n node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) \n node _T_2281 = or(_T_2235, _T_2240) \n node _T_2282 = or(_T_2281, _T_2245) \n node _T_2283 = or(_T_2282, _T_2250) \n node _T_2284 = or(_T_2283, _T_2255) \n node _T_2285 = or(_T_2284, _T_2260) \n node _T_2286 = or(_T_2285, _T_2265) \n node _T_2287 = or(_T_2286, _T_2270) \n node _T_2288 = or(_T_2287, _T_2275) \n node _T_2289 = or(_T_2288, _T_2280) \n node _T_2290 = and(_T_2230, _T_2289) \n node _T_2291 = or(UInt<1>(0h0), _T_2290) \n node _T_2292 = and(_WIRE_9, _T_2291) \n node _T_2293 = asUInt(reset) \n node _T_2294 = eq(_T_2293, UInt<1>(0h0)) \n when _T_2294 : \n node _T_2295 = eq(_T_2292, UInt<1>(0h0)) \n when _T_2295 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_151 \n assert(clock, _T_2292, UInt<1>(0h1), \"\") : assert_151 \n node _T_2296 = asUInt(reset) \n node _T_2297 = eq(_T_2296, UInt<1>(0h0)) \n when _T_2297 : \n node _T_2298 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_2298 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_152 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_152 \n node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3)) \n node _T_2300 = asUInt(reset) \n node _T_2301 = eq(_T_2300, UInt<1>(0h0)) \n when _T_2301 : \n node _T_2302 = eq(_T_2299, UInt<1>(0h0)) \n when _T_2302 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_153 \n assert(clock, _T_2299, UInt<1>(0h1), \"\") : assert_153 \n node _T_2303 = asUInt(reset) \n node _T_2304 = eq(_T_2303, UInt<1>(0h0)) \n when _T_2304 : \n node _T_2305 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_2305 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_154 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_154 \n node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5)) \n node _T_2307 = asUInt(reset) \n node _T_2308 = eq(_T_2307, UInt<1>(0h0)) \n when _T_2308 : \n node _T_2309 = eq(_T_2306, UInt<1>(0h0)) \n when _T_2309 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_155 \n assert(clock, _T_2306, UInt<1>(0h1), \"\") : assert_155 \n node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) \n when _T_2310 : \n node _T_2311 = asUInt(reset) \n node _T_2312 = eq(_T_2311, UInt<1>(0h0)) \n when _T_2312 : \n node _T_2313 = eq(address_ok_1, UInt<1>(0h0)) \n when _T_2313 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_156 \n assert(clock, address_ok_1, UInt<1>(0h1), \"\") : assert_156 \n node _T_2314 = asUInt(reset) \n node _T_2315 = eq(_T_2314, UInt<1>(0h0)) \n when _T_2315 : \n node _T_2316 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_2316 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_157 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_157 \n node _T_2317 = asUInt(reset) \n node _T_2318 = eq(_T_2317, UInt<1>(0h0)) \n when _T_2318 : \n node _T_2319 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_2319 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_158 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_158 \n node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0)) \n node _T_2321 = asUInt(reset) \n node _T_2322 = eq(_T_2321, UInt<1>(0h0)) \n when _T_2322 : \n node _T_2323 = eq(_T_2320, UInt<1>(0h0)) \n when _T_2323 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_159 \n assert(clock, _T_2320, UInt<1>(0h1), \"\") : assert_159 \n node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) \n node _T_2325 = asUInt(reset) \n node _T_2326 = eq(_T_2325, UInt<1>(0h0)) \n when _T_2326 : \n node _T_2327 = eq(_T_2324, UInt<1>(0h0)) \n when _T_2327 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_160 \n assert(clock, _T_2324, UInt<1>(0h1), \"\") : assert_160 \n node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) \n when _T_2328 : \n node _T_2329 = asUInt(reset) \n node _T_2330 = eq(_T_2329, UInt<1>(0h0)) \n when _T_2330 : \n node _T_2331 = eq(address_ok_1, UInt<1>(0h0)) \n when _T_2331 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_161 \n assert(clock, address_ok_1, UInt<1>(0h1), \"\") : assert_161 \n node _T_2332 = asUInt(reset) \n node _T_2333 = eq(_T_2332, UInt<1>(0h0)) \n when _T_2333 : \n node _T_2334 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_2334 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_162 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_162 \n node _T_2335 = asUInt(reset) \n node _T_2336 = eq(_T_2335, UInt<1>(0h0)) \n when _T_2336 : \n node _T_2337 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_2337 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_163 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_163 \n node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0)) \n node _T_2339 = asUInt(reset) \n node _T_2340 = eq(_T_2339, UInt<1>(0h0)) \n when _T_2340 : \n node _T_2341 = eq(_T_2338, UInt<1>(0h0)) \n when _T_2341 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_164 \n assert(clock, _T_2338, UInt<1>(0h1), \"\") : assert_164 \n node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) \n when _T_2342 : \n node _T_2343 = asUInt(reset) \n node _T_2344 = eq(_T_2343, UInt<1>(0h0)) \n when _T_2344 : \n node _T_2345 = eq(address_ok_1, UInt<1>(0h0)) \n when _T_2345 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_165 \n assert(clock, address_ok_1, UInt<1>(0h1), \"\") : assert_165 \n node _T_2346 = asUInt(reset) \n node _T_2347 = eq(_T_2346, UInt<1>(0h0)) \n when _T_2347 : \n node _T_2348 = eq(source_ok_2, UInt<1>(0h0)) \n when _T_2348 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_166 \n assert(clock, source_ok_2, UInt<1>(0h1), \"\") : assert_166 \n node _T_2349 = asUInt(reset) \n node _T_2350 = eq(_T_2349, UInt<1>(0h0)) \n when _T_2350 : \n node _T_2351 = eq(is_aligned_2, UInt<1>(0h0)) \n when _T_2351 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_167 \n assert(clock, is_aligned_2, UInt<1>(0h1), \"\") : assert_167 \n node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0)) \n node _T_2353 = asUInt(reset) \n node _T_2354 = eq(_T_2353, UInt<1>(0h0)) \n when _T_2354 : \n node _T_2355 = eq(_T_2352, UInt<1>(0h0)) \n when _T_2355 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_168 \n assert(clock, _T_2352, UInt<1>(0h1), \"\") : assert_168 \n node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) \n node _T_2357 = asUInt(reset) \n node _T_2358 = eq(_T_2357, UInt<1>(0h0)) \n when _T_2358 : \n node _T_2359 = eq(_T_2356, UInt<1>(0h0)) \n when _T_2359 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_169 \n assert(clock, _T_2356, UInt<1>(0h1), \"\") : assert_169 \n when io.in.e.valid : \n node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) \n node _T_2360 = asUInt(reset) \n node _T_2361 = eq(_T_2360, UInt<1>(0h0)) \n when _T_2361 : \n node _T_2362 = eq(sink_ok_1, UInt<1>(0h0)) \n when _T_2362 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_170 \n assert(clock, sink_ok_1, UInt<1>(0h1), \"\") : assert_170 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_2363 = eq(a_first, UInt<1>(0h0)) \n node _T_2364 = and(io.in.a.valid, _T_2363) \n when _T_2364 : \n node _T_2365 = eq(io.in.a.bits.opcode, opcode) \n node _T_2366 = asUInt(reset) \n node _T_2367 = eq(_T_2366, UInt<1>(0h0)) \n when _T_2367 : \n node _T_2368 = eq(_T_2365, UInt<1>(0h0)) \n when _T_2368 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_171 \n assert(clock, _T_2365, UInt<1>(0h1), \"\") : assert_171 \n node _T_2369 = eq(io.in.a.bits.param, param) \n node _T_2370 = asUInt(reset) \n node _T_2371 = eq(_T_2370, UInt<1>(0h0)) \n when _T_2371 : \n node _T_2372 = eq(_T_2369, UInt<1>(0h0)) \n when _T_2372 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_172 \n assert(clock, _T_2369, UInt<1>(0h1), \"\") : assert_172 \n node _T_2373 = eq(io.in.a.bits.size, size) \n node _T_2374 = asUInt(reset) \n node _T_2375 = eq(_T_2374, UInt<1>(0h0)) \n when _T_2375 : \n node _T_2376 = eq(_T_2373, UInt<1>(0h0)) \n when _T_2376 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_173 \n assert(clock, _T_2373, UInt<1>(0h1), \"\") : assert_173 \n node _T_2377 = eq(io.in.a.bits.source, source) \n node _T_2378 = asUInt(reset) \n node _T_2379 = eq(_T_2378, UInt<1>(0h0)) \n when _T_2379 : \n node _T_2380 = eq(_T_2377, UInt<1>(0h0)) \n when _T_2380 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_174 \n assert(clock, _T_2377, UInt<1>(0h1), \"\") : assert_174 \n node _T_2381 = eq(io.in.a.bits.address, address) \n node _T_2382 = asUInt(reset) \n node _T_2383 = eq(_T_2382, UInt<1>(0h0)) \n when _T_2383 : \n node _T_2384 = eq(_T_2381, UInt<1>(0h0)) \n when _T_2384 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_175 \n assert(clock, _T_2381, UInt<1>(0h1), \"\") : assert_175 \n node _T_2385 = and(io.in.a.ready, io.in.a.valid) \n node _T_2386 = and(_T_2385, a_first) \n when _T_2386 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_2387 = eq(d_first, UInt<1>(0h0)) \n node _T_2388 = and(io.in.d.valid, _T_2387) \n when _T_2388 : \n node _T_2389 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_2390 = asUInt(reset) \n node _T_2391 = eq(_T_2390, UInt<1>(0h0)) \n when _T_2391 : \n node _T_2392 = eq(_T_2389, UInt<1>(0h0)) \n when _T_2392 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_176 \n assert(clock, _T_2389, UInt<1>(0h1), \"\") : assert_176 \n node _T_2393 = eq(io.in.d.bits.param, param_1) \n node _T_2394 = asUInt(reset) \n node _T_2395 = eq(_T_2394, UInt<1>(0h0)) \n when _T_2395 : \n node _T_2396 = eq(_T_2393, UInt<1>(0h0)) \n when _T_2396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_177 \n assert(clock, _T_2393, UInt<1>(0h1), \"\") : assert_177 \n node _T_2397 = eq(io.in.d.bits.size, size_1) \n node _T_2398 = asUInt(reset) \n node _T_2399 = eq(_T_2398, UInt<1>(0h0)) \n when _T_2399 : \n node _T_2400 = eq(_T_2397, UInt<1>(0h0)) \n when _T_2400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_178 \n assert(clock, _T_2397, UInt<1>(0h1), \"\") : assert_178 \n node _T_2401 = eq(io.in.d.bits.source, source_1) \n node _T_2402 = asUInt(reset) \n node _T_2403 = eq(_T_2402, UInt<1>(0h0)) \n when _T_2403 : \n node _T_2404 = eq(_T_2401, UInt<1>(0h0)) \n when _T_2404 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_179 \n assert(clock, _T_2401, UInt<1>(0h1), \"\") : assert_179 \n node _T_2405 = eq(io.in.d.bits.sink, sink) \n node _T_2406 = asUInt(reset) \n node _T_2407 = eq(_T_2406, UInt<1>(0h0)) \n when _T_2407 : \n node _T_2408 = eq(_T_2405, UInt<1>(0h0)) \n when _T_2408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_180 \n assert(clock, _T_2405, UInt<1>(0h1), \"\") : assert_180 \n node _T_2409 = eq(io.in.d.bits.denied, denied) \n node _T_2410 = asUInt(reset) \n node _T_2411 = eq(_T_2410, UInt<1>(0h0)) \n when _T_2411 : \n node _T_2412 = eq(_T_2409, UInt<1>(0h0)) \n when _T_2412 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_181 \n assert(clock, _T_2409, UInt<1>(0h1), \"\") : assert_181 \n node _T_2413 = and(io.in.d.ready, io.in.d.valid) \n node _T_2414 = and(_T_2413, d_first) \n when _T_2414 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n node _b_first_T = and(io.in.b.ready, io.in.b.valid) \n node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) \n node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) \n node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) \n node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) \n node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) \n node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) \n node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) \n regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) \n node b_first_counter1 = tail(_b_first_counter1_T, 1) \n node b_first = eq(b_first_counter, UInt<1>(0h0)) \n node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) \n node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) \n node b_first_last = or(_b_first_last_T, _b_first_last_T_1) \n node b_first_done = and(b_first_last, _b_first_T) \n node _b_first_count_T = not(b_first_counter1) \n node b_first_count = and(b_first_beats1, _b_first_count_T) \n when _b_first_T : \n node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) \n connect b_first_counter, _b_first_counter_T \n reg opcode_2 : UInt, clock \n reg param_2 : UInt, clock \n reg size_2 : UInt, clock \n reg source_2 : UInt, clock \n reg address_1 : UInt, clock \n node _T_2415 = eq(b_first, UInt<1>(0h0)) \n node _T_2416 = and(io.in.b.valid, _T_2415) \n when _T_2416 : \n node _T_2417 = eq(io.in.b.bits.opcode, opcode_2) \n node _T_2418 = asUInt(reset) \n node _T_2419 = eq(_T_2418, UInt<1>(0h0)) \n when _T_2419 : \n node _T_2420 = eq(_T_2417, UInt<1>(0h0)) \n when _T_2420 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_182 \n assert(clock, _T_2417, UInt<1>(0h1), \"\") : assert_182 \n node _T_2421 = eq(io.in.b.bits.param, param_2) \n node _T_2422 = asUInt(reset) \n node _T_2423 = eq(_T_2422, UInt<1>(0h0)) \n when _T_2423 : \n node _T_2424 = eq(_T_2421, UInt<1>(0h0)) \n when _T_2424 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_183 \n assert(clock, _T_2421, UInt<1>(0h1), \"\") : assert_183 \n node _T_2425 = eq(io.in.b.bits.size, size_2) \n node _T_2426 = asUInt(reset) \n node _T_2427 = eq(_T_2426, UInt<1>(0h0)) \n when _T_2427 : \n node _T_2428 = eq(_T_2425, UInt<1>(0h0)) \n when _T_2428 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_184 \n assert(clock, _T_2425, UInt<1>(0h1), \"\") : assert_184 \n node _T_2429 = eq(io.in.b.bits.source, source_2) \n node _T_2430 = asUInt(reset) \n node _T_2431 = eq(_T_2430, UInt<1>(0h0)) \n when _T_2431 : \n node _T_2432 = eq(_T_2429, UInt<1>(0h0)) \n when _T_2432 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_185 \n assert(clock, _T_2429, UInt<1>(0h1), \"\") : assert_185 \n node _T_2433 = eq(io.in.b.bits.address, address_1) \n node _T_2434 = asUInt(reset) \n node _T_2435 = eq(_T_2434, UInt<1>(0h0)) \n when _T_2435 : \n node _T_2436 = eq(_T_2433, UInt<1>(0h0)) \n when _T_2436 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_186 \n assert(clock, _T_2433, UInt<1>(0h1), \"\") : assert_186 \n node _T_2437 = and(io.in.b.ready, io.in.b.valid) \n node _T_2438 = and(_T_2437, b_first) \n when _T_2438 : \n connect opcode_2, io.in.b.bits.opcode \n connect param_2, io.in.b.bits.param \n connect size_2, io.in.b.bits.size \n connect source_2, io.in.b.bits.source \n connect address_1, io.in.b.bits.address \n node _c_first_T = and(io.in.c.ready, io.in.c.valid) \n node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) \n node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n reg opcode_3 : UInt, clock \n reg param_3 : UInt, clock \n reg size_3 : UInt, clock \n reg source_3 : UInt, clock \n reg address_2 : UInt, clock \n node _T_2439 = eq(c_first, UInt<1>(0h0)) \n node _T_2440 = and(io.in.c.valid, _T_2439) \n when _T_2440 : \n node _T_2441 = eq(io.in.c.bits.opcode, opcode_3) \n node _T_2442 = asUInt(reset) \n node _T_2443 = eq(_T_2442, UInt<1>(0h0)) \n when _T_2443 : \n node _T_2444 = eq(_T_2441, UInt<1>(0h0)) \n when _T_2444 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_187 \n assert(clock, _T_2441, UInt<1>(0h1), \"\") : assert_187 \n node _T_2445 = eq(io.in.c.bits.param, param_3) \n node _T_2446 = asUInt(reset) \n node _T_2447 = eq(_T_2446, UInt<1>(0h0)) \n when _T_2447 : \n node _T_2448 = eq(_T_2445, UInt<1>(0h0)) \n when _T_2448 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_188 \n assert(clock, _T_2445, UInt<1>(0h1), \"\") : assert_188 \n node _T_2449 = eq(io.in.c.bits.size, size_3) \n node _T_2450 = asUInt(reset) \n node _T_2451 = eq(_T_2450, UInt<1>(0h0)) \n when _T_2451 : \n node _T_2452 = eq(_T_2449, UInt<1>(0h0)) \n when _T_2452 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_189 \n assert(clock, _T_2449, UInt<1>(0h1), \"\") : assert_189 \n node _T_2453 = eq(io.in.c.bits.source, source_3) \n node _T_2454 = asUInt(reset) \n node _T_2455 = eq(_T_2454, UInt<1>(0h0)) \n when _T_2455 : \n node _T_2456 = eq(_T_2453, UInt<1>(0h0)) \n when _T_2456 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_190 \n assert(clock, _T_2453, UInt<1>(0h1), \"\") : assert_190 \n node _T_2457 = eq(io.in.c.bits.address, address_2) \n node _T_2458 = asUInt(reset) \n node _T_2459 = eq(_T_2458, UInt<1>(0h0)) \n when _T_2459 : \n node _T_2460 = eq(_T_2457, UInt<1>(0h0)) \n when _T_2460 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_191 \n assert(clock, _T_2457, UInt<1>(0h1), \"\") : assert_191 \n node _T_2461 = and(io.in.c.ready, io.in.c.valid) \n node _T_2462 = and(_T_2461, c_first) \n when _T_2462 : \n connect opcode_3, io.in.c.bits.opcode \n connect param_3, io.in.c.bits.param \n connect size_3, io.in.c.bits.size \n connect source_3, io.in.c.bits.source \n connect address_2, io.in.c.bits.address \n regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) \n regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) \n regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<9> \n connect a_set, UInt<9>(0h0) \n wire a_set_wo_ready : UInt<9> \n connect a_set_wo_ready, UInt<9>(0h0) \n wire a_opcodes_set : UInt<36> \n connect a_opcodes_set, UInt<36>(0h0) \n wire a_sizes_set : UInt<72> \n connect a_sizes_set, UInt<72>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<8> \n connect a_size_lookup, UInt<8>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<5> \n connect a_sizes_set_interm, UInt<5>(0h0) \n node _T_2463 = and(io.in.a.valid, a_first_1) \n node _T_2464 = and(_T_2463, UInt<1>(0h1)) \n when _T_2464 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_2465 = and(io.in.a.ready, io.in.a.valid) \n node _T_2466 = and(_T_2465, a_first_1) \n node _T_2467 = and(_T_2466, UInt<1>(0h1)) \n when _T_2467 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_2468 = dshr(inflight, io.in.a.bits.source) \n node _T_2469 = bits(_T_2468, 0, 0) \n node _T_2470 = eq(_T_2469, UInt<1>(0h0)) \n node _T_2471 = asUInt(reset) \n node _T_2472 = eq(_T_2471, UInt<1>(0h0)) \n when _T_2472 : \n node _T_2473 = eq(_T_2470, UInt<1>(0h0)) \n when _T_2473 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_192 \n assert(clock, _T_2470, UInt<1>(0h1), \"\") : assert_192 \n wire d_clr : UInt<9> \n connect d_clr, UInt<9>(0h0) \n wire d_clr_wo_ready : UInt<9> \n connect d_clr_wo_ready, UInt<9>(0h0) \n wire d_opcodes_clr : UInt<36> \n connect d_opcodes_clr, UInt<36>(0h0) \n wire d_sizes_clr : UInt<72> \n connect d_sizes_clr, UInt<72>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_2474 = and(io.in.d.valid, d_first_1) \n node _T_2475 = and(_T_2474, UInt<1>(0h1)) \n node _T_2476 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_2477 = and(_T_2475, _T_2476) \n when _T_2477 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_2478 = and(io.in.d.ready, io.in.d.valid) \n node _T_2479 = and(_T_2478, d_first_1) \n node _T_2480 = and(_T_2479, UInt<1>(0h1)) \n node _T_2481 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_2482 = and(_T_2480, _T_2481) \n when _T_2482 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_2483 = and(io.in.d.valid, d_first_1) \n node _T_2484 = and(_T_2483, UInt<1>(0h1)) \n node _T_2485 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_2486 = and(_T_2484, _T_2485) \n when _T_2486 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_2487 = dshr(inflight, io.in.d.bits.source) \n node _T_2488 = bits(_T_2487, 0, 0) \n node _T_2489 = or(_T_2488, same_cycle_resp) \n node _T_2490 = asUInt(reset) \n node _T_2491 = eq(_T_2490, UInt<1>(0h0)) \n when _T_2491 : \n node _T_2492 = eq(_T_2489, UInt<1>(0h0)) \n when _T_2492 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_193 \n assert(clock, _T_2489, UInt<1>(0h1), \"\") : assert_193 \n when same_cycle_resp : \n node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_2495 = or(_T_2493, _T_2494) \n node _T_2496 = asUInt(reset) \n node _T_2497 = eq(_T_2496, UInt<1>(0h0)) \n when _T_2497 : \n node _T_2498 = eq(_T_2495, UInt<1>(0h0)) \n when _T_2498 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_194 \n assert(clock, _T_2495, UInt<1>(0h1), \"\") : assert_194 \n node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_2500 = asUInt(reset) \n node _T_2501 = eq(_T_2500, UInt<1>(0h0)) \n when _T_2501 : \n node _T_2502 = eq(_T_2499, UInt<1>(0h0)) \n when _T_2502 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_195 \n assert(clock, _T_2499, UInt<1>(0h1), \"\") : assert_195 \n else :\n\n node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_2505 = or(_T_2503, _T_2504) \n node _T_2506 = asUInt(reset) \n node _T_2507 = eq(_T_2506, UInt<1>(0h0)) \n when _T_2507 : \n node _T_2508 = eq(_T_2505, UInt<1>(0h0)) \n when _T_2508 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_196 \n assert(clock, _T_2505, UInt<1>(0h1), \"\") : assert_196 \n node _T_2509 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_2510 = asUInt(reset) \n node _T_2511 = eq(_T_2510, UInt<1>(0h0)) \n when _T_2511 : \n node _T_2512 = eq(_T_2509, UInt<1>(0h0)) \n when _T_2512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_197 \n assert(clock, _T_2509, UInt<1>(0h1), \"\") : assert_197 \n node _T_2513 = and(io.in.d.valid, d_first_1) \n node _T_2514 = and(_T_2513, a_first_1) \n node _T_2515 = and(_T_2514, io.in.a.valid) \n node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_2517 = and(_T_2515, _T_2516) \n node _T_2518 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_2519 = and(_T_2517, _T_2518) \n when _T_2519 : \n node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_2521 = or(_T_2520, io.in.a.ready) \n node _T_2522 = asUInt(reset) \n node _T_2523 = eq(_T_2522, UInt<1>(0h0)) \n when _T_2523 : \n node _T_2524 = eq(_T_2521, UInt<1>(0h0)) \n when _T_2524 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_198 \n assert(clock, _T_2521, UInt<1>(0h1), \"\") : assert_198 \n node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_2526 = orr(a_set_wo_ready) \n node _T_2527 = eq(_T_2526, UInt<1>(0h0)) \n node _T_2528 = or(_T_2525, _T_2527) \n node _T_2529 = asUInt(reset) \n node _T_2530 = eq(_T_2529, UInt<1>(0h0)) \n when _T_2530 : \n node _T_2531 = eq(_T_2528, UInt<1>(0h0)) \n when _T_2531 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_199 \n assert(clock, _T_2528, UInt<1>(0h1), \"\") : assert_199 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_84 \n node _T_2532 = orr(inflight) \n node _T_2533 = eq(_T_2532, UInt<1>(0h0)) \n node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_2535 = or(_T_2533, _T_2534) \n node _T_2536 = lt(watchdog, plusarg_reader.out) \n node _T_2537 = or(_T_2535, _T_2536) \n node _T_2538 = asUInt(reset) \n node _T_2539 = eq(_T_2538, UInt<1>(0h0)) \n when _T_2539 : \n node _T_2540 = eq(_T_2537, UInt<1>(0h0)) \n when _T_2540 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_200 \n assert(clock, _T_2537, UInt<1>(0h1), \"\") : assert_200 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_2541 = and(io.in.a.ready, io.in.a.valid) \n node _T_2542 = and(io.in.d.ready, io.in.d.valid) \n node _T_2543 = or(_T_2541, _T_2542) \n when _T_2543 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) \n regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) \n node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) \n node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) \n node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) \n node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) \n node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) \n node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) \n node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) \n regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) \n node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) \n node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) \n node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) \n node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) \n node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) \n node c_first_done_1 = and(c_first_last_1, _c_first_T_1) \n node _c_first_count_T_1 = not(c_first_counter1_1) \n node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) \n when _c_first_T_1 : \n node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) \n connect c_first_counter_1, _c_first_counter_T_1 \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<9> \n connect c_set, UInt<9>(0h0) \n wire c_set_wo_ready : UInt<9> \n connect c_set_wo_ready, UInt<9>(0h0) \n wire c_opcodes_set : UInt<36> \n connect c_opcodes_set, UInt<36>(0h0) \n wire c_sizes_set : UInt<72> \n connect c_sizes_set, UInt<72>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<8> \n connect c_size_lookup, UInt<8>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<5> \n connect c_sizes_set_interm, UInt<5>(0h0) \n node _T_2544 = and(io.in.c.valid, c_first_1) \n node _T_2545 = bits(io.in.c.bits.opcode, 2, 2) \n node _T_2546 = bits(io.in.c.bits.opcode, 1, 1) \n node _T_2547 = and(_T_2545, _T_2546) \n node _T_2548 = and(_T_2544, _T_2547) \n when _T_2548 : \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n node _T_2549 = and(io.in.c.ready, io.in.c.valid) \n node _T_2550 = and(_T_2549, c_first_1) \n node _T_2551 = bits(io.in.c.bits.opcode, 2, 2) \n node _T_2552 = bits(io.in.c.bits.opcode, 1, 1) \n node _T_2553 = and(_T_2551, _T_2552) \n node _T_2554 = and(_T_2550, _T_2553) \n when _T_2554 : \n node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) \n connect c_set, _c_set_T \n node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n node _T_2555 = dshr(inflight_1, io.in.c.bits.source) \n node _T_2556 = bits(_T_2555, 0, 0) \n node _T_2557 = eq(_T_2556, UInt<1>(0h0)) \n node _T_2558 = asUInt(reset) \n node _T_2559 = eq(_T_2558, UInt<1>(0h0)) \n when _T_2559 : \n node _T_2560 = eq(_T_2557, UInt<1>(0h0)) \n when _T_2560 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_201 \n assert(clock, _T_2557, UInt<1>(0h1), \"\") : assert_201 \n node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) \n node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<9> \n connect d_clr_1, UInt<9>(0h0) \n wire d_clr_wo_ready_1 : UInt<9> \n connect d_clr_wo_ready_1, UInt<9>(0h0) \n wire d_opcodes_clr_1 : UInt<36> \n connect d_opcodes_clr_1, UInt<36>(0h0) \n wire d_sizes_clr_1 : UInt<72> \n connect d_sizes_clr_1, UInt<72>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_2561 = and(io.in.d.valid, d_first_2) \n node _T_2562 = and(_T_2561, UInt<1>(0h1)) \n node _T_2563 = and(_T_2562, d_release_ack_1) \n when _T_2563 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_2564 = and(io.in.d.ready, io.in.d.valid) \n node _T_2565 = and(_T_2564, d_first_2) \n node _T_2566 = and(_T_2565, UInt<1>(0h1)) \n node _T_2567 = and(_T_2566, d_release_ack_1) \n when _T_2567 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_2568 = and(io.in.d.valid, d_first_2) \n node _T_2569 = and(_T_2568, UInt<1>(0h1)) \n node _T_2570 = and(_T_2569, d_release_ack_1) \n when _T_2570 : \n node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) \n node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_2571 = dshr(inflight_1, io.in.d.bits.source) \n node _T_2572 = bits(_T_2571, 0, 0) \n node _T_2573 = or(_T_2572, same_cycle_resp_1) \n node _T_2574 = asUInt(reset) \n node _T_2575 = eq(_T_2574, UInt<1>(0h0)) \n when _T_2575 : \n node _T_2576 = eq(_T_2573, UInt<1>(0h0)) \n when _T_2576 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_202 \n assert(clock, _T_2573, UInt<1>(0h1), \"\") : assert_202 \n when same_cycle_resp_1 : \n node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size) \n node _T_2578 = asUInt(reset) \n node _T_2579 = eq(_T_2578, UInt<1>(0h0)) \n when _T_2579 : \n node _T_2580 = eq(_T_2577, UInt<1>(0h0)) \n when _T_2580 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_203 \n assert(clock, _T_2577, UInt<1>(0h1), \"\") : assert_203 \n else :\n\n node _T_2581 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_2582 = asUInt(reset) \n node _T_2583 = eq(_T_2582, UInt<1>(0h0)) \n when _T_2583 : \n node _T_2584 = eq(_T_2581, UInt<1>(0h0)) \n when _T_2584 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_204 \n assert(clock, _T_2581, UInt<1>(0h1), \"\") : assert_204 \n node _T_2585 = and(io.in.d.valid, d_first_2) \n node _T_2586 = and(_T_2585, c_first_1) \n node _T_2587 = and(_T_2586, io.in.c.valid) \n node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source) \n node _T_2589 = and(_T_2587, _T_2588) \n node _T_2590 = and(_T_2589, d_release_ack_1) \n node _T_2591 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_2592 = and(_T_2590, _T_2591) \n when _T_2592 : \n node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_2594 = or(_T_2593, io.in.c.ready) \n node _T_2595 = asUInt(reset) \n node _T_2596 = eq(_T_2595, UInt<1>(0h0)) \n when _T_2596 : \n node _T_2597 = eq(_T_2594, UInt<1>(0h0)) \n when _T_2597 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_205 \n assert(clock, _T_2594, UInt<1>(0h1), \"\") : assert_205 \n node _T_2598 = orr(c_set_wo_ready) \n when _T_2598 : \n node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_2600 = asUInt(reset) \n node _T_2601 = eq(_T_2600, UInt<1>(0h0)) \n when _T_2601 : \n node _T_2602 = eq(_T_2599, UInt<1>(0h0)) \n when _T_2602 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_206 \n assert(clock, _T_2599, UInt<1>(0h1), \"\") : assert_206 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_85 \n node _T_2603 = orr(inflight_1) \n node _T_2604 = eq(_T_2603, UInt<1>(0h0)) \n node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_2606 = or(_T_2604, _T_2605) \n node _T_2607 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_2608 = or(_T_2606, _T_2607) \n node _T_2609 = asUInt(reset) \n node _T_2610 = eq(_T_2609, UInt<1>(0h0)) \n when _T_2610 : \n node _T_2611 = eq(_T_2608, UInt<1>(0h0)) \n when _T_2611 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_207 \n assert(clock, _T_2608, UInt<1>(0h1), \"\") : assert_207 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n node _T_2612 = and(io.in.c.ready, io.in.c.valid) \n node _T_2613 = and(io.in.d.ready, io.in.d.valid) \n node _T_2614 = or(_T_2612, _T_2613) \n when _T_2614 : \n connect watchdog_1, UInt<1>(0h0) \n regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) \n node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) \n node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) \n node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) \n node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) \n node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) \n regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) \n node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) \n node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) \n node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) \n node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) \n node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) \n node d_first_done_3 = and(d_first_last_3, _d_first_T_3) \n node _d_first_count_T_3 = not(d_first_counter1_3) \n node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) \n when _d_first_T_3 : \n node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) \n connect d_first_counter_3, _d_first_counter_T_3 \n wire d_set : UInt<8> \n connect d_set, UInt<8>(0h0) \n node _T_2615 = and(io.in.d.ready, io.in.d.valid) \n node _T_2616 = and(_T_2615, d_first_3) \n node _T_2617 = bits(io.in.d.bits.opcode, 2, 2) \n node _T_2618 = bits(io.in.d.bits.opcode, 1, 1) \n node _T_2619 = eq(_T_2618, UInt<1>(0h0)) \n node _T_2620 = and(_T_2617, _T_2619) \n node _T_2621 = and(_T_2616, _T_2620) \n when _T_2621 : \n node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) \n connect d_set, _d_set_T \n node _T_2622 = dshr(inflight_2, io.in.d.bits.sink) \n node _T_2623 = bits(_T_2622, 0, 0) \n node _T_2624 = eq(_T_2623, UInt<1>(0h0)) \n node _T_2625 = asUInt(reset) \n node _T_2626 = eq(_T_2625, UInt<1>(0h0)) \n when _T_2626 : \n node _T_2627 = eq(_T_2624, UInt<1>(0h0)) \n when _T_2627 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_208 \n assert(clock, _T_2624, UInt<1>(0h1), \"\") : assert_208 \n wire e_clr : UInt<8> \n connect e_clr, UInt<8>(0h0) \n node _T_2628 = and(io.in.e.ready, io.in.e.valid) \n node _T_2629 = and(_T_2628, UInt<1>(0h1)) \n node _T_2630 = and(_T_2629, UInt<1>(0h1)) \n when _T_2630 : \n node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) \n connect e_clr, _e_clr_T \n node _T_2631 = or(d_set, inflight_2) \n node _T_2632 = dshr(_T_2631, io.in.e.bits.sink) \n node _T_2633 = bits(_T_2632, 0, 0) \n node _T_2634 = asUInt(reset) \n node _T_2635 = eq(_T_2634, UInt<1>(0h0)) \n when _T_2635 : \n node _T_2636 = eq(_T_2633, UInt<1>(0h0)) \n when _T_2636 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_209 \n assert(clock, _T_2633, UInt<1>(0h1), \"\") : assert_209 \n node _inflight_T_6 = or(inflight_2, d_set) \n node _inflight_T_7 = not(e_clr) \n node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) \n connect inflight_2, _inflight_T_8"},"response":{"kind":"string","value":"module TLMonitor_42(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_b_ready,\t// @[Monitor.scala:20:14]\n input io_in_b_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_b_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_b_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_b_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_b_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_b_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_b_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_b_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_b_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_c_ready,\t// @[Monitor.scala:20:14]\n input io_in_c_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_c_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_c_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_c_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_c_bits_source,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_c_bits_address,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_c_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_c_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [3:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_e_ready,\t// @[Monitor.scala:20:14]\n input io_in_e_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_e_bits_sink\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_b_ready_0 = io_in_b_ready;\t// @[Monitor.scala:36:7]\n wire io_in_b_valid_0 = io_in_b_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_c_ready_0 = io_in_c_ready;\t// @[Monitor.scala:36:7]\n wire io_in_c_valid_0 = io_in_c_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_e_ready_0 = io_in_e_ready;\t// @[Monitor.scala:36:7]\n wire io_in_e_valid_0 = io_in_e_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink;\t// @[Monitor.scala:36:7]\n wire [15:0] _a_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hFF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hFF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hFF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h100;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h100;\t// @[Monitor.scala:724:51]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [8:0] b_first_beats1 = 9'h0;\t// @[Edges.scala:221:14]\n wire [8:0] b_first_count = 9'h0;\t// @[Edges.scala:234:25]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_12 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_14 = 1'h1;\t// @[Parameters.scala:57:20]\n wire sink_ok = 1'h1;\t// @[Monitor.scala:309:31]\n wire _legal_source_T_3 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _legal_source_T_5 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _source_ok_T_21 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_23 = 1'h1;\t// @[Parameters.scala:57:20]\n wire sink_ok_1 = 1'h1;\t// @[Monitor.scala:367:31]\n wire _b_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire b_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _legal_source_T_9 = 1'h0;\t// @[Mux.scala:30:73]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _a_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_sizes_clr_T = 4'h8;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_size_lookup_T_2 = 4'h8;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_sizes_clr_T_6 = 4'h8;\t// @[Monitor.scala:791:48]\n wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0;\t// @[Misc.scala:202:34]\n wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T = io_in_b_bits_address_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0;\t// @[Monitor.scala:36:7]\n wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = io_in_a_bits_source_0 == 4'h8;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_0 = _source_ok_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T_1 = io_in_a_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_2 = _source_ok_T_1 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_4 = _source_ok_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_6 = _source_ok_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1 = _source_ok_T_6;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h4;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_2 = _source_ok_T_7;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [26:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [1:0] uncommonBits = _uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_9 = io_in_d_bits_source_0 == 4'h8;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_0 = _source_ok_T_9;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T_10 = io_in_d_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_11 = _source_ok_T_10 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_13 = _source_ok_T_11;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_15 = _source_ok_T_13;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_1_1 = _source_ok_T_15;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h4;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_1_2 = _source_ok_T_16;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire _legal_source_T = io_in_b_bits_source_0 == 4'h8;\t// @[Monitor.scala:36:7]\n wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _legal_source_T_1 = io_in_b_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h4;\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_3 = _address_ok_T_2;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_4 = _address_ok_T_3 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_0 = _address_ok_T_4;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_8 = _address_ok_T_7;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_9 = _address_ok_T_8 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1 = _address_ok_T_9;\t// @[Parameters.scala:612:40]\n wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_13 = _address_ok_T_12;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_14 = _address_ok_T_13 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_2 = _address_ok_T_14;\t// @[Parameters.scala:612:40]\n wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_18 = _address_ok_T_17;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_19 = _address_ok_T_18 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_3 = _address_ok_T_19;\t// @[Parameters.scala:612:40]\n wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_23 = _address_ok_T_22;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_24 = _address_ok_T_23 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_4 = _address_ok_T_24;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_28 = _address_ok_T_27;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_29 = _address_ok_T_28 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_5 = _address_ok_T_29;\t// @[Parameters.scala:612:40]\n wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_33 = _address_ok_T_32;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_34 = _address_ok_T_33 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_6 = _address_ok_T_34;\t// @[Parameters.scala:612:40]\n wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_38 = _address_ok_T_37;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_39 = _address_ok_T_38 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_7 = _address_ok_T_39;\t// @[Parameters.scala:612:40]\n wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_43 = _address_ok_T_42;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_44 = _address_ok_T_43 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_8 = _address_ok_T_44;\t// @[Parameters.scala:612:40]\n wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_48 = _address_ok_T_47;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_49 = _address_ok_T_48 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_9 = _address_ok_T_49;\t// @[Parameters.scala:612:40]\n wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_53 = _address_ok_T_52;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_54 = _address_ok_T_53 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_10 = _address_ok_T_54;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000;\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_58 = _address_ok_T_57;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_59 = _address_ok_T_58 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_11 = _address_ok_T_59;\t// @[Parameters.scala:612:40]\n wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10;\t// @[Parameters.scala:612:40, :636:64]\n wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11;\t// @[Parameters.scala:612:40, :636:64]\n wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T_2;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T_2 = _GEN_8;\t// @[package.scala:243:71]\n wire [26:0] _b_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _b_first_beats1_decode_T = _GEN_8;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1};\t// @[package.scala:243:46]\n wire is_aligned_1 = _is_aligned_T_1 == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size_1 = mask_sizeOH_1[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size_1 = mask_sizeOH_1[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit_1 = io_in_b_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit_1 = ~mask_sub_bit_1;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire mask_size_1 = mask_sizeOH_1[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit_1 = io_in_b_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit_1 = ~mask_bit_1;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_8 = mask_size_1 & mask_eq_8;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_9 = mask_size_1 & mask_eq_9;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_10 = mask_size_1 & mask_eq_10;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_11 = mask_size_1 & mask_eq_11;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_12 = mask_size_1 & mask_eq_12;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_13 = mask_size_1 & mask_eq_13;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_14 = mask_size_1 & mask_eq_14;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_15 = mask_size_1 & mask_eq_15;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1};\t// @[Misc.scala:222:10]\n wire [7:0] mask_1 = {mask_hi_1, mask_lo_1};\t// @[Misc.scala:222:10]\n wire _legal_source_WIRE_0 = _legal_source_T;\t// @[Parameters.scala:1138:31]\n wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _legal_source_T_2 = _legal_source_T_1 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _legal_source_T_4 = _legal_source_T_2;\t// @[Parameters.scala:54:{32,67}]\n wire _legal_source_T_6 = _legal_source_T_4;\t// @[Parameters.scala:54:67, :56:48]\n wire _legal_source_WIRE_1 = _legal_source_T_6;\t// @[Parameters.scala:1138:31]\n wire _legal_source_WIRE_2 = _legal_source_T_7;\t// @[Parameters.scala:1138:31]\n wire [3:0] _legal_source_T_8 = {_legal_source_WIRE_0, 3'h0};\t// @[Mux.scala:30:73]\n wire [3:0] _legal_source_T_11 = _legal_source_T_8;\t// @[Mux.scala:30:73]\n wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0};\t// @[Mux.scala:30:73]\n wire [3:0] _legal_source_T_12 = {_legal_source_T_11[3], _legal_source_T_11[2:0] | _legal_source_T_10};\t// @[Mux.scala:30:73]\n wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12;\t// @[Mux.scala:30:73]\n wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0;\t// @[Mux.scala:30:73]\n wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_18 = io_in_c_bits_source_0 == 4'h8;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_2_0 = _source_ok_T_18;\t// @[Parameters.scala:1138:31]\n wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] _source_ok_T_19 = io_in_c_bits_source_0[3:2];\t// @[Monitor.scala:36:7]\n wire _source_ok_T_20 = _source_ok_T_19 == 2'h0;\t// @[Parameters.scala:54:{10,32}]\n wire _source_ok_T_22 = _source_ok_T_20;\t// @[Parameters.scala:54:{32,67}]\n wire _source_ok_T_24 = _source_ok_T_22;\t// @[Parameters.scala:54:67, :56:48]\n wire _source_ok_WIRE_2_1 = _source_ok_T_24;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h4;\t// @[Monitor.scala:36:7]\n wire _source_ok_WIRE_2_2 = _source_ok_T_25;\t// @[Parameters.scala:1138:31]\n wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1;\t// @[Parameters.scala:1138:31, :1139:46]\n wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2;\t// @[Parameters.scala:1138:31, :1139:46]\n wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _is_aligned_mask_T_4;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T_4 = _GEN_9;\t// @[package.scala:243:71]\n wire [26:0] _c_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _c_first_beats1_decode_T = _GEN_9;\t// @[package.scala:243:71]\n wire [26:0] _c_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _c_first_beats1_decode_T_3 = _GEN_9;\t// @[package.scala:243:71]\n wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5;\t// @[package.scala:243:{46,76}]\n wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2};\t// @[package.scala:243:46]\n wire is_aligned_2 = _is_aligned_T_2 == 32'h0;\t// @[Edges.scala:21:{16,24}]\n wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_73 = _address_ok_T_72;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_74 = _address_ok_T_73 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_0 = _address_ok_T_74;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_78 = _address_ok_T_77;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_79 = _address_ok_T_78 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_1 = _address_ok_T_79;\t// @[Parameters.scala:612:40]\n wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_83 = _address_ok_T_82;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_84 = _address_ok_T_83 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_2 = _address_ok_T_84;\t// @[Parameters.scala:612:40]\n wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_88 = _address_ok_T_87;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_89 = _address_ok_T_88 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_3 = _address_ok_T_89;\t// @[Parameters.scala:612:40]\n wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_93 = _address_ok_T_92;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_94 = _address_ok_T_93 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_4 = _address_ok_T_94;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_98 = _address_ok_T_97;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_99 = _address_ok_T_98 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_5 = _address_ok_T_99;\t// @[Parameters.scala:612:40]\n wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_103 = _address_ok_T_102;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_104 = _address_ok_T_103 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_6 = _address_ok_T_104;\t// @[Parameters.scala:612:40]\n wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_108 = _address_ok_T_107;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_109 = _address_ok_T_108 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_7 = _address_ok_T_109;\t// @[Parameters.scala:612:40]\n wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_113 = _address_ok_T_112;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_114 = _address_ok_T_113 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_8 = _address_ok_T_114;\t// @[Parameters.scala:612:40]\n wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_118 = _address_ok_T_117;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_119 = _address_ok_T_118 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_9 = _address_ok_T_119;\t// @[Parameters.scala:612:40]\n wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000;\t// @[Monitor.scala:36:7]\n wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17};\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_123 = _address_ok_T_122;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_124 = _address_ok_T_123 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_10 = _address_ok_T_124;\t// @[Parameters.scala:612:40]\n wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000;\t// @[Monitor.scala:36:7]\n wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _address_ok_T_128 = _address_ok_T_127;\t// @[Parameters.scala:137:46]\n wire _address_ok_T_129 = _address_ok_T_128 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _address_ok_WIRE_1_11 = _address_ok_T_129;\t// @[Parameters.scala:612:40]\n wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9;\t// @[Parameters.scala:612:40, :636:64]\n wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10;\t// @[Parameters.scala:612:40, :636:64]\n wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11;\t// @[Parameters.scala:612:40, :636:64]\n wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0];\t// @[Parameters.scala:52:{29,56}]\n wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_2541;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_2541;\t// @[Decoupled.scala:51:35]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [3:0] size;\t// @[Monitor.scala:389:22]\n reg [3:0] source;\t// @[Monitor.scala:390:22]\n reg [31:0] address;\t// @[Monitor.scala:391:22]\n wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_2615;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_2615;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_2615;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_3;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_3 = _T_2615;\t// @[Decoupled.scala:51:35]\n wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_18;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_18;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_18;\t// @[package.scala:243:71]\n wire [26:0] _d_first_beats1_decode_T_9;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_9 = _GEN_18;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [3:0] size_1;\t// @[Monitor.scala:540:22]\n reg [3:0] source_1;\t// @[Monitor.scala:541:22]\n reg [2:0] sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0;\t// @[Decoupled.scala:51:35]\n wire b_first_done = _b_first_T;\t// @[Decoupled.scala:51:35]\n wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T;\t// @[Edges.scala:97:{28,37}]\n reg [8:0] b_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire b_first = b_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _b_first_last_T = b_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire [8:0] _b_first_count_T = ~b_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_2;\t// @[Monitor.scala:410:22]\n reg [1:0] param_2;\t// @[Monitor.scala:411:22]\n reg [3:0] size_2;\t// @[Monitor.scala:412:22]\n reg [3:0] source_2;\t// @[Monitor.scala:413:22]\n reg [31:0] address_1;\t// @[Monitor.scala:414:22]\n wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0;\t// @[Decoupled.scala:51:35]\n wire _c_first_T;\t// @[Decoupled.scala:51:35]\n assign _c_first_T = _T_2612;\t// @[Decoupled.scala:51:35]\n wire _c_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _c_first_T_1 = _T_2612;\t// @[Decoupled.scala:51:35]\n wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0;\t// @[Edges.scala:102:36, :220:59, :221:14]\n reg [8:0] c_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire c_first = c_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _c_first_last_T = c_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _c_first_last_T_1 = c_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire c_first_last = _c_first_last_T | _c_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire c_first_done = c_first_last & _c_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _c_first_count_T = ~c_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_3;\t// @[Monitor.scala:515:22]\n reg [2:0] param_3;\t// @[Monitor.scala:516:22]\n reg [3:0] size_3;\t// @[Monitor.scala:517:22]\n reg [3:0] source_3;\t// @[Monitor.scala:518:22]\n reg [31:0] address_2;\t// @[Monitor.scala:519:22]\n reg [8:0] inflight;\t// @[Monitor.scala:614:27]\n reg [35:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [71:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [8:0] a_set;\t// @[Monitor.scala:626:34]\n wire [8:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [35:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [71:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [6:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [6:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_19;\t// @[Monitor.scala:637:69]\n wire [6:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_19;\t// @[Monitor.scala:637:69, :680:101]\n wire [6:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_19;\t// @[Monitor.scala:637:69, :749:69]\n wire [6:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_19;\t// @[Monitor.scala:637:69, :790:101]\n wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [7:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [6:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :641:65]\n wire [6:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_20;\t// @[Monitor.scala:641:65]\n wire [6:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_20;\t// @[Monitor.scala:641:65, :681:99]\n wire [6:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_20;\t// @[Monitor.scala:641:65, :750:67]\n wire [6:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_20;\t// @[Monitor.scala:641:65, :791:99]\n wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[7:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [4:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [15:0] _GEN_21 = 16'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_21;\t// @[OneHot.scala:58:35]\n wire [15:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_21;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire _T_2467 = _T_2541 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_2467 ? _a_set_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[35:0] : 36'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :660:77]\n wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[71:0] : 72'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [8:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [8:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [35:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [71:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_22;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_22;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_2513 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [15:0] _GEN_23 = 16'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_23;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_23;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_23;\t// @[OneHot.scala:58:35]\n wire [15:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_23;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_2482 ? _d_clr_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[35:0] : 36'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[71:0] : 72'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [8:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [8:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [8:0] inflight_1;\t// @[Monitor.scala:726:35]\n reg [35:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n reg [71:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3];\t// @[package.scala:243:46]\n wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0;\t// @[Edges.scala:102:36, :220:59, :221:14]\n reg [8:0] c_first_counter_1;\t// @[Edges.scala:229:27]\n wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0];\t// @[Edges.scala:230:28]\n wire c_first_1 = c_first_counter_1 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _c_first_last_T_2 = c_first_counter_1 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire c_first_done_1 = c_first_last_1 & _c_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [8:0] c_set;\t// @[Monitor.scala:738:34]\n wire [8:0] c_set_wo_ready;\t// @[Monitor.scala:739:34]\n wire [35:0] c_opcodes_set;\t// @[Monitor.scala:740:34]\n wire [71:0] c_sizes_set;\t// @[Monitor.scala:741:34]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [7:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[7:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [3:0] c_opcodes_set_interm;\t// @[Monitor.scala:754:40]\n wire [4:0] c_sizes_set_interm;\t// @[Monitor.scala:755:40]\n wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1;\t// @[Monitor.scala:36:7, :759:26, :795:44]\n wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1];\t// @[Monitor.scala:36:7]\n wire [15:0] _GEN_24 = 16'h1 << io_in_c_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [15:0] _c_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _c_set_wo_ready_T = _GEN_24;\t// @[OneHot.scala:58:35]\n wire [15:0] _c_set_T;\t// @[OneHot.scala:58:35]\n assign _c_set_T = _GEN_24;\t// @[OneHot.scala:58:35]\n assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5;\t// @[Decoupled.scala:51:35]\n assign c_set = _T_2554 ? _c_set_T[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :765:53]\n wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:765:{53,61}]\n assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]\n wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :766:51]\n wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1};\t// @[Monitor.scala:766:{51,59}]\n assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0;\t// @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]\n wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :767:79]\n wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T;\t// @[Monitor.scala:659:54, :754:40, :767:{54,79}]\n assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[35:0] : 36'h0;\t// @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]\n wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0};\t// @[Monitor.scala:36:7, :768:77]\n wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T;\t// @[Monitor.scala:659:54, :755:40, :768:{52,77}]\n assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[71:0] : 72'h0;\t// @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]\n wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4;\t// @[Monitor.scala:36:7, :772:47]\n wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5;\t// @[Monitor.scala:36:7, :772:95]\n wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1;\t// @[Monitor.scala:772:{47,71,95}]\n wire [8:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [8:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [35:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [71:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_2585 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_2567 ? _d_clr_T_1[8:0] : 9'h0;\t// @[OneHot.scala:58:35]\n wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[35:0] : 36'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[71:0] : 72'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5;\t// @[Edges.scala:68:{36,40,51}]\n wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6;\t// @[Monitor.scala:795:{44,55}]\n wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :795:113]\n wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8;\t// @[Monitor.scala:795:{55,88,113}]\n wire [8:0] _inflight_T_3 = inflight_1 | c_set;\t// @[Monitor.scala:726:35, :738:34, :814:35]\n wire [8:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set;\t// @[Monitor.scala:727:35, :740:34, :815:43]\n wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set;\t// @[Monitor.scala:728:35, :741:34, :816:41]\n wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]\n wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1;\t// @[Monitor.scala:818:27, :823:26]\n wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0];\t// @[Monitor.scala:823:26]\n reg [7:0] inflight_2;\t// @[Monitor.scala:828:27]\n wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3];\t// @[package.scala:243:46]\n wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter_3;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0];\t// @[Edges.scala:230:28]\n wire d_first_3 = d_first_counter_3 == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_6 = d_first_counter_3 == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_3 = d_first_last_3 & _d_first_T_3;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [7:0] d_set;\t// @[Monitor.scala:833:25]\n wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]);\t// @[Decoupled.scala:51:35]\n wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0};\t// @[OneHot.scala:58:35]\n wire [7:0] _d_set_T = 8'h1 << _GEN_25;\t// @[OneHot.scala:58:35]\n assign d_set = _T_2621 ? _d_set_T : 8'h0;\t// @[OneHot.scala:58:35]\n wire [7:0] e_clr;\t// @[Monitor.scala:839:25]\n wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0;\t// @[Decoupled.scala:51:35]\n wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0};\t// @[OneHot.scala:58:35]\n wire [7:0] _e_clr_T = 8'h1 << _GEN_26;\t// @[OneHot.scala:58:35]\n assign e_clr = _T_2630 ? _e_clr_T : 8'h0;\t// @[OneHot.scala:58:35]"}}},{"rowIdx":35476,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_3 : \n input clock : Clock \n input reset : Reset \n output io : { flip count : UInt<32>} \n\n\n inst plusarg_reader of plusarg_reader_111 \n node _T = gt(plusarg_reader.out, UInt<1>(0h0)) \n when _T : \n node _T_1 = lt(io.count, plusarg_reader.out) \n node _T_2 = asUInt(reset) \n node _T_3 = eq(_T_2, UInt<1>(0h0)) \n when _T_3 : \n node _T_4 = eq(_T_1, UInt<1>(0h0)) \n when _T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\\n at PlusArg.scala:64 assert (io.count < max, s\\\"Timeout exceeded: $docstring\\\")\\n\") : printf \n assert(clock, _T_1, UInt<1>(0h1), \"\") : assert"},"response":{"kind":"string","value":"module PlusArgTimeout_3(\t// @[PlusArg.scala:58:7]\n input clock,\t// @[PlusArg.scala:58:7]\n input reset,\t// @[PlusArg.scala:58:7]\n input [31:0] io_count\t// @[PlusArg.scala:59:14]\n);\n\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:62:19]\n wire [31:0] io_count_0 = io_count;\t// @[PlusArg.scala:58:7]"}}},{"rowIdx":35477,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_11 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} \n\n\n node _reg_T = asAsyncReset(reset) \n regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) \n when io.en : \n connect reg, io.d \n connect io.q, reg"},"response":{"kind":"string","value":"module AsyncResetRegVec_w1_i0_11(\t// @[AsyncResetReg.scala:56:7]\n input clock,\t// @[AsyncResetReg.scala:56:7]\n input reset\t// @[AsyncResetReg.scala:56:7]\n);\n\n wire _reg_T = reset;\t// @[AsyncResetReg.scala:61:29]\n wire io_en = 1'h1;\t// @[AsyncResetReg.scala:56:7, :59:14]\n wire io_d = 1'h0;\t// @[AsyncResetReg.scala:56:7]\n wire io_q = 1'h0;\t// @[AsyncResetReg.scala:56:7]\nendmodule"}}},{"rowIdx":35478,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_43 : \n output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} \n\n\n node _intAsRawFloat_sign_T = bits(io.in, 0, 0) \n node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) \n node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) \n node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) \n node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) \n node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) \n node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) \n node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) \n node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) \n node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) \n node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) \n node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) \n wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} \n connect intAsRawFloat.isNaN, UInt<1>(0h0) \n connect intAsRawFloat.isInf, UInt<1>(0h0) \n node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) \n node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) \n connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 \n connect intAsRawFloat.sign, intAsRawFloat_sign \n node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) \n node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) \n node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) \n node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) \n connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 \n connect intAsRawFloat.sig, intAsRawFloat_sig \n inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43 \n connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig \n connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp \n connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign \n connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero \n connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf \n connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN \n connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode \n connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess \n connect io.out, roundAnyRawFNToRecFN.io.out \n connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags"},"response":{"kind":"string","value":"module INToRecFN_i1_e8_s24_43();\t// @[INToRecFN.scala:43:7]\n wire [1:0] _intAsRawFloat_absIn_T = 2'h3;\t// @[rawFloatFromIN.scala:52:31]\n wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1;\t// @[rawFloatFromIN.scala:53:44]\n wire [2:0] _intAsRawFloat_sig_T = 3'h2;\t// @[rawFloatFromIN.scala:56:22]\n wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4;\t// @[rawFloatFromIN.scala:64:33]\n wire [3:0] intAsRawFloat_sExp = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n wire [1:0] intAsRawFloat_extAbsIn = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [1:0] intAsRawFloat_sig = 2'h1;\t// @[rawFloatFromIN.scala:53:53, :59:23, :65:20]\n wire [4:0] io_exceptionFlags = 5'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [32:0] io_out = 33'h80000000;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire [2:0] io_roundingMode = 3'h0;\t// @[INToRecFN.scala:43:7, :46:16, :60:15]\n wire io_in = 1'h1;\t// @[Mux.scala:50:70]\n wire io_detectTininess = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_sign_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_absIn_T_1 = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_absIn = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_adjustedNormDist_T = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_adjustedNormDist = 1'h1;\t// @[Mux.scala:50:70]\n wire intAsRawFloat_sig_0 = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_isZero_T = 1'h1;\t// @[Mux.scala:50:70]\n wire _intAsRawFloat_out_sExp_T = 1'h1;\t// @[Mux.scala:50:70]\n wire io_signedIn = 1'h0;\t// @[INToRecFN.scala:43:7]\n wire intAsRawFloat_sign = 1'h0;\t// @[rawFloatFromIN.scala:51:29]\n wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0;\t// @[primitives.scala:91:52]\n wire intAsRawFloat_isNaN = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isInf = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isZero = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_sign_0 = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire _intAsRawFloat_out_isZero_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:62:23]\n wire _intAsRawFloat_out_sExp_T_1 = 1'h0;\t// @[rawFloatFromIN.scala:64:36]\n RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43 roundAnyRawFNToRecFN ();\t// @[INToRecFN.scala:60:15]\nendmodule"}}},{"rowIdx":35479,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_138 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_148 \n connect io_out_sink_extend.clock, clock\n\n connect io_out_sink_extend.reset, reset\n\n connect io_out_sink_extend.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_sink_extend.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_138(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_148 io_out_sink_extend (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":35480,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_154 : \n input clock : Clock \n input reset : Reset \n output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} \n\n\n regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) \n reg value_reg : { symbol : UInt<10>}, clock \n connect io.output_prev.key, key_reg \n connect io.output_prev.value, value_reg \n connect io.output_nxt.key, key_reg \n connect io.output_nxt.value, value_reg \n connect io.cur_output_keyval.key, key_reg \n connect io.cur_output_keyval.value, value_reg \n when io.cmd.valid : \n node _T = eq(UInt<1>(0h0), io.cmd.bits) \n when _T : \n connect key_reg, io.input_nxt.key \n connect value_reg, io.input_nxt.value \n else :\n\n node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) \n when _T_1 : \n when io.insert_here : \n connect key_reg, io.cur_input_keyval.key \n connect value_reg, io.cur_input_keyval.value \n else :\n\n node _T_2 = geq(key_reg, io.cur_input_keyval.key) \n when _T_2 : \n connect key_reg, io.input_prev.key \n connect value_reg, io.input_prev.value \n else :\n\n skip"},"response":{"kind":"string","value":"module PriorityQueueStage_154(\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n input clock,\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n input reset,\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n output [30:0] io_output_prev_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_output_prev_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [30:0] io_output_nxt_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_output_nxt_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_input_prev_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_input_prev_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_input_nxt_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_input_nxt_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_cmd_valid,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_cmd_bits,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input io_insert_here,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [30:0] io_cur_input_keyval_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n input [9:0] io_cur_input_keyval_value_symbol,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [30:0] io_cur_output_keyval_key,\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n output [9:0] io_cur_output_keyval_value_symbol\t// @[ShiftRegisterPriorityQueue.scala:22:14]\n);\n\n wire [30:0] io_input_prev_key_0 = io_input_prev_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_input_nxt_key_0 = io_input_nxt_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_cmd_valid_0 = io_cmd_valid;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_cmd_bits_0 = io_cmd_bits;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire io_insert_here_0 = io_insert_here;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_output_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_output_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_output_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_output_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [9:0] io_cur_output_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n wire [30:0] io_cur_output_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n reg [30:0] key_reg;\t// @[ShiftRegisterPriorityQueue.scala:30:24]\n assign io_output_prev_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n assign io_output_nxt_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n assign io_cur_output_keyval_key_0 = key_reg;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n reg [9:0] value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:31:22]\n assign io_output_prev_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n assign io_output_nxt_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n wire _T_2 = key_reg >= io_cur_input_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]\n always @(posedge clock) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (reset)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= 31'h7FFFFFFF;\t// @[ShiftRegisterPriorityQueue.scala:30:24]\n else if (io_cmd_valid_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_cmd_bits_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_insert_here_0)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= io_cur_input_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n else if (_T_2)\t// @[ShiftRegisterPriorityQueue.scala:52:30]\n key_reg <= io_input_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n end\n else\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n key_reg <= io_input_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]\n end\n if (io_cmd_valid_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_cmd_bits_0) begin\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n if (io_insert_here_0)\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n value_reg_symbol <= io_cur_input_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n else if (_T_2)\t// @[ShiftRegisterPriorityQueue.scala:52:30]\n value_reg_symbol <= io_input_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n end\n else\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n value_reg_symbol <= io_input_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]\n end\n always @(posedge)\n assign io_output_prev_key = io_output_prev_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_prev_value_symbol = io_output_prev_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_nxt_key = io_output_nxt_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_cur_output_keyval_key = io_cur_output_keyval_key_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\n assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0;\t// @[ShiftRegisterPriorityQueue.scala:21:7]\nendmodule"}}},{"rowIdx":35481,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_483 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_483(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":35482,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Router_44 : \n input clock : Clock \n input reset : Reset \n output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} \n\n\n wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate destNodesIn.vc_free \n invalidate destNodesIn.credit_return \n invalidate destNodesIn.flit[0].bits.virt_channel_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node \n invalidate destNodesIn.flit[0].bits.flow.ingress_node_id \n invalidate destNodesIn.flit[0].bits.flow.ingress_node \n invalidate destNodesIn.flit[0].bits.flow.vnet_id \n invalidate destNodesIn.flit[0].bits.payload \n invalidate destNodesIn.flit[0].bits.tail \n invalidate destNodesIn.flit[0].bits.head \n invalidate destNodesIn.flit[0].valid \n inst monitor of NoCMonitor_98 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.vc_free, destNodesIn.vc_free \n connect monitor.io.in.credit_return, destNodesIn.credit_return \n connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id \n connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id \n connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node \n connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id \n connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node \n connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id \n connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload \n connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail \n connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head \n connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid \n wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate destNodesIn_1.vc_free \n invalidate destNodesIn_1.credit_return \n invalidate destNodesIn_1.flit[0].bits.virt_channel_id \n invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id \n invalidate destNodesIn_1.flit[0].bits.flow.egress_node \n invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id \n invalidate destNodesIn_1.flit[0].bits.flow.ingress_node \n invalidate destNodesIn_1.flit[0].bits.flow.vnet_id \n invalidate destNodesIn_1.flit[0].bits.payload \n invalidate destNodesIn_1.flit[0].bits.tail \n invalidate destNodesIn_1.flit[0].bits.head \n invalidate destNodesIn_1.flit[0].valid \n inst monitor_1 of NoCMonitor_99 \n connect monitor_1.clock, clock\n\n connect monitor_1.reset, reset\n\n connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free \n connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return \n connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id \n connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id \n connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node \n connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id \n connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node \n connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id \n connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload \n connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail \n connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head \n connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid \n wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate destNodesIn_2.vc_free \n invalidate destNodesIn_2.credit_return \n invalidate destNodesIn_2.flit[0].bits.virt_channel_id \n invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id \n invalidate destNodesIn_2.flit[0].bits.flow.egress_node \n invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id \n invalidate destNodesIn_2.flit[0].bits.flow.ingress_node \n invalidate destNodesIn_2.flit[0].bits.flow.vnet_id \n invalidate destNodesIn_2.flit[0].bits.payload \n invalidate destNodesIn_2.flit[0].bits.tail \n invalidate destNodesIn_2.flit[0].bits.head \n invalidate destNodesIn_2.flit[0].valid \n inst monitor_2 of NoCMonitor_100 \n connect monitor_2.clock, clock\n\n connect monitor_2.reset, reset\n\n connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free \n connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return \n connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id \n connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id \n connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node \n connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id \n connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node \n connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id \n connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload \n connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail \n connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head \n connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid \n wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate sourceNodesOut.vc_free \n invalidate sourceNodesOut.credit_return \n invalidate sourceNodesOut.flit[0].bits.virt_channel_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node \n invalidate sourceNodesOut.flit[0].bits.flow.vnet_id \n invalidate sourceNodesOut.flit[0].bits.payload \n invalidate sourceNodesOut.flit[0].bits.tail \n invalidate sourceNodesOut.flit[0].bits.head \n invalidate sourceNodesOut.flit[0].valid \n wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate sourceNodesOut_1.vc_free \n invalidate sourceNodesOut_1.credit_return \n invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id \n invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id \n invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node \n invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id \n invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node \n invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id \n invalidate sourceNodesOut_1.flit[0].bits.payload \n invalidate sourceNodesOut_1.flit[0].bits.tail \n invalidate sourceNodesOut_1.flit[0].bits.head \n invalidate sourceNodesOut_1.flit[0].valid \n wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate sourceNodesOut_2.vc_free \n invalidate sourceNodesOut_2.credit_return \n invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id \n invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id \n invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node \n invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id \n invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node \n invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id \n invalidate sourceNodesOut_2.flit[0].bits.payload \n invalidate sourceNodesOut_2.flit[0].bits.tail \n invalidate sourceNodesOut_2.flit[0].bits.head \n invalidate sourceNodesOut_2.flit[0].valid \n wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} \n invalidate debugNodeOut.sa_stall[0] \n invalidate debugNodeOut.sa_stall[1] \n invalidate debugNodeOut.sa_stall[2] \n invalidate debugNodeOut.va_stall[0] \n invalidate debugNodeOut.va_stall[1] \n invalidate debugNodeOut.va_stall[2] \n connect destNodesIn, auto.dest_nodes_in_0 \n connect destNodesIn_1, auto.dest_nodes_in_1 \n connect destNodesIn_2, auto.dest_nodes_in_2 \n connect auto.source_nodes_out_0, sourceNodesOut \n connect auto.source_nodes_out_1, sourceNodesOut_1 \n connect auto.source_nodes_out_2, sourceNodesOut_2 \n connect auto.debug_out, debugNodeOut \n inst input_unit_0_from_6 of InputUnit_98 \n connect input_unit_0_from_6.clock, clock\n\n connect input_unit_0_from_6.reset, reset\n\n inst input_unit_1_from_14 of InputUnit_99 \n connect input_unit_1_from_14.clock, clock\n\n connect input_unit_1_from_14.reset, reset\n\n inst input_unit_2_from_16 of InputUnit_100 \n connect input_unit_2_from_16.clock, clock\n\n connect input_unit_2_from_16.reset, reset\n\n inst output_unit_0_to_6 of OutputUnit_98 \n connect output_unit_0_to_6.clock, clock\n\n connect output_unit_0_to_6.reset, reset\n\n inst output_unit_1_to_14 of OutputUnit_99 \n connect output_unit_1_to_14.clock, clock\n\n connect output_unit_1_to_14.reset, reset\n\n inst output_unit_2_to_16 of OutputUnit_100 \n connect output_unit_2_to_16.clock, clock\n\n connect output_unit_2_to_16.reset, reset\n\n inst switch of Switch_44 \n connect switch.clock, clock\n\n connect switch.reset, reset\n\n inst switch_allocator of SwitchAllocator_44 \n connect switch_allocator.clock, clock\n\n connect switch_allocator.reset, reset\n\n inst vc_allocator of RotatingSingleVCAllocator_44 \n connect vc_allocator.clock, clock\n\n connect vc_allocator.reset, reset\n\n inst route_computer of RouteComputer_44 \n connect route_computer.clock, clock\n\n connect route_computer.reset, reset\n\n node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) \n node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) \n node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) \n node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) \n node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) \n node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) \n node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) \n wire fires_count : UInt \n connect fires_count, _fires_count_T_6 \n connect input_unit_0_from_6.io.in, destNodesIn \n connect input_unit_1_from_14.io.in, destNodesIn_1 \n connect input_unit_2_from_16.io.in, destNodesIn_2 \n connect output_unit_0_to_6.io.out.vc_free, sourceNodesOut.vc_free \n connect output_unit_0_to_6.io.out.credit_return, sourceNodesOut.credit_return \n connect sourceNodesOut.flit, output_unit_0_to_6.io.out.flit \n connect output_unit_1_to_14.io.out.vc_free, sourceNodesOut_1.vc_free \n connect output_unit_1_to_14.io.out.credit_return, sourceNodesOut_1.credit_return \n connect sourceNodesOut_1.flit, output_unit_1_to_14.io.out.flit \n connect output_unit_2_to_16.io.out.vc_free, sourceNodesOut_2.vc_free \n connect output_unit_2_to_16.io.out.credit_return, sourceNodesOut_2.credit_return \n connect sourceNodesOut_2.flit, output_unit_2_to_16.io.out.flit \n connect route_computer.io.req.`0`, input_unit_0_from_6.io.router_req \n connect route_computer.io.req.`1`, input_unit_1_from_14.io.router_req \n connect route_computer.io.req.`2`, input_unit_2_from_16.io.router_req \n connect input_unit_0_from_6.io.router_resp, route_computer.io.resp.`0` \n connect input_unit_1_from_14.io.router_resp, route_computer.io.resp.`1` \n connect input_unit_2_from_16.io.router_resp, route_computer.io.resp.`2` \n connect vc_allocator.io.req.`0`, input_unit_0_from_6.io.vcalloc_req \n connect vc_allocator.io.req.`1`, input_unit_1_from_14.io.vcalloc_req \n connect vc_allocator.io.req.`2`, input_unit_2_from_16.io.vcalloc_req \n connect input_unit_0_from_6.io.vcalloc_resp, vc_allocator.io.resp.`0` \n connect input_unit_1_from_14.io.vcalloc_resp, vc_allocator.io.resp.`1` \n connect input_unit_2_from_16.io.vcalloc_resp, vc_allocator.io.resp.`2` \n connect output_unit_0_to_6.io.allocs, vc_allocator.io.out_allocs.`0` \n connect output_unit_1_to_14.io.allocs, vc_allocator.io.out_allocs.`1` \n connect output_unit_2_to_16.io.allocs, vc_allocator.io.out_allocs.`2` \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_6.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_6.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_6.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_6.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_6.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_6.io.channel_status[1].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_6.io.channel_status[1].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[1].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_6.io.channel_status[1].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_6.io.channel_status[1].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_6.io.channel_status[1].occupied \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_6.io.channel_status[2].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_6.io.channel_status[2].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[2].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_6.io.channel_status[2].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_6.io.channel_status[2].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_6.io.channel_status[2].occupied \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_6.io.channel_status[3].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_6.io.channel_status[3].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[3].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_6.io.channel_status[3].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_6.io.channel_status[3].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_6.io.channel_status[3].occupied \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_6.io.channel_status[4].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_6.io.channel_status[4].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[4].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_6.io.channel_status[4].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_6.io.channel_status[4].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_6.io.channel_status[4].occupied \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_14.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_14.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_14.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_14.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_14.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_14.io.channel_status[1].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_14.io.channel_status[1].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[1].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_14.io.channel_status[1].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_14.io.channel_status[1].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_14.io.channel_status[1].occupied \n connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_14.io.channel_status[2].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_14.io.channel_status[2].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[2].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_14.io.channel_status[2].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_14.io.channel_status[2].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_14.io.channel_status[2].occupied \n connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_14.io.channel_status[3].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_14.io.channel_status[3].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[3].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_14.io.channel_status[3].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_14.io.channel_status[3].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_14.io.channel_status[3].occupied \n connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_14.io.channel_status[4].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_14.io.channel_status[4].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[4].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_14.io.channel_status[4].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_14.io.channel_status[4].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_14.io.channel_status[4].occupied \n connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_16.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_16.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_16.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_16.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_16.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_16.io.channel_status[1].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_16.io.channel_status[1].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[1].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_16.io.channel_status[1].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_16.io.channel_status[1].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_16.io.channel_status[1].occupied \n connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_16.io.channel_status[2].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_16.io.channel_status[2].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[2].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_16.io.channel_status[2].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_16.io.channel_status[2].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_16.io.channel_status[2].occupied \n connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_16.io.channel_status[3].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_16.io.channel_status[3].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[3].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_16.io.channel_status[3].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_16.io.channel_status[3].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_16.io.channel_status[3].occupied \n connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_16.io.channel_status[4].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_16.io.channel_status[4].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[4].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_16.io.channel_status[4].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_16.io.channel_status[4].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_16.io.channel_status[4].occupied \n connect input_unit_0_from_6.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0] \n connect input_unit_0_from_6.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1] \n connect input_unit_0_from_6.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2] \n connect input_unit_0_from_6.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3] \n connect input_unit_0_from_6.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4] \n connect input_unit_0_from_6.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0] \n connect input_unit_0_from_6.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1] \n connect input_unit_0_from_6.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2] \n connect input_unit_0_from_6.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3] \n connect input_unit_0_from_6.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4] \n connect input_unit_0_from_6.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0] \n connect input_unit_0_from_6.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1] \n connect input_unit_0_from_6.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2] \n connect input_unit_0_from_6.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3] \n connect input_unit_0_from_6.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4] \n connect input_unit_1_from_14.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0] \n connect input_unit_1_from_14.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1] \n connect input_unit_1_from_14.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2] \n connect input_unit_1_from_14.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3] \n connect input_unit_1_from_14.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4] \n connect input_unit_1_from_14.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0] \n connect input_unit_1_from_14.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1] \n connect input_unit_1_from_14.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2] \n connect input_unit_1_from_14.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3] \n connect input_unit_1_from_14.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4] \n connect input_unit_1_from_14.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0] \n connect input_unit_1_from_14.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1] \n connect input_unit_1_from_14.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2] \n connect input_unit_1_from_14.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3] \n connect input_unit_1_from_14.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4] \n connect input_unit_2_from_16.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0] \n connect input_unit_2_from_16.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1] \n connect input_unit_2_from_16.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2] \n connect input_unit_2_from_16.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3] \n connect input_unit_2_from_16.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4] \n connect input_unit_2_from_16.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0] \n connect input_unit_2_from_16.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1] \n connect input_unit_2_from_16.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2] \n connect input_unit_2_from_16.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3] \n connect input_unit_2_from_16.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4] \n connect input_unit_2_from_16.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0] \n connect input_unit_2_from_16.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1] \n connect input_unit_2_from_16.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2] \n connect input_unit_2_from_16.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3] \n connect input_unit_2_from_16.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4] \n connect switch_allocator.io.req.`0`[0], input_unit_0_from_6.io.salloc_req[0] \n connect switch_allocator.io.req.`1`[0], input_unit_1_from_14.io.salloc_req[0] \n connect switch_allocator.io.req.`2`[0], input_unit_2_from_16.io.salloc_req[0] \n connect output_unit_0_to_6.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail \n connect output_unit_0_to_6.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc \n connect output_unit_0_to_6.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail \n connect output_unit_0_to_6.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc \n connect output_unit_0_to_6.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail \n connect output_unit_0_to_6.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc \n connect output_unit_0_to_6.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail \n connect output_unit_0_to_6.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc \n connect output_unit_0_to_6.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail \n connect output_unit_0_to_6.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc \n connect output_unit_1_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail \n connect output_unit_1_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc \n connect output_unit_1_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail \n connect output_unit_1_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc \n connect output_unit_1_to_14.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail \n connect output_unit_1_to_14.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc \n connect output_unit_1_to_14.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail \n connect output_unit_1_to_14.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc \n connect output_unit_1_to_14.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail \n connect output_unit_1_to_14.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc \n connect output_unit_2_to_16.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail \n connect output_unit_2_to_16.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc \n connect output_unit_2_to_16.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail \n connect output_unit_2_to_16.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc \n connect output_unit_2_to_16.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail \n connect output_unit_2_to_16.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc \n connect output_unit_2_to_16.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail \n connect output_unit_2_to_16.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc \n connect output_unit_2_to_16.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail \n connect output_unit_2_to_16.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc \n connect switch.io.in.`0`[0], input_unit_0_from_6.io.out[0] \n connect switch.io.in.`1`[0], input_unit_1_from_14.io.out[0] \n connect switch.io.in.`2`[0], input_unit_2_from_16.io.out[0] \n connect output_unit_0_to_6.io.in, switch.io.out.`0` \n connect output_unit_1_to_14.io.in, switch.io.out.`1` \n connect output_unit_2_to_16.io.in, switch.io.out.`2` \n reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock \n connect REG, switch_allocator.io.switch_sel \n connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] \n connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] \n connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] \n connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] \n connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] \n connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] \n connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] \n connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] \n connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] \n connect input_unit_0_from_6.io.block, UInt<1>(0h0) \n connect input_unit_1_from_14.io.block, UInt<1>(0h0) \n connect input_unit_2_from_16.io.block, UInt<1>(0h0) \n connect debugNodeOut.va_stall[0], input_unit_0_from_6.io.debug.va_stall \n connect debugNodeOut.va_stall[1], input_unit_1_from_14.io.debug.va_stall \n connect debugNodeOut.va_stall[2], input_unit_2_from_16.io.debug.va_stall \n connect debugNodeOut.sa_stall[0], input_unit_0_from_6.io.debug.sa_stall \n connect debugNodeOut.sa_stall[1], input_unit_1_from_14.io.debug.sa_stall \n connect debugNodeOut.sa_stall[2], input_unit_2_from_16.io.debug.sa_stall \n regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) \n node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) \n connect debug_tsc, _debug_tsc_T_1 \n regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) \n node _debug_sample_T_1 = tail(_debug_sample_T, 1) \n connect debug_sample, _debug_sample_T_1 \n inst plusarg_reader of plusarg_reader_92 \n node _T = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_1 = tail(_T, 1) \n node _T_2 = eq(debug_sample, _T_1) \n when _T_2 : \n connect debug_sample, UInt<1>(0h0) \n regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) \n node _util_ctr_T_1 = tail(_util_ctr_T, 1) \n connect util_ctr, _util_ctr_T_1 \n node _fired_T = or(fired, destNodesIn.flit[0].valid) \n connect fired, _fired_T \n node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_5 = tail(_T_4, 1) \n node _T_6 = eq(debug_sample, _T_5) \n node _T_7 = and(_T_3, _T_6) \n node _T_8 = and(_T_7, fired) \n when _T_8 : \n node _T_9 = asUInt(reset) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n when _T_10 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 6 15 %d\\n\", debug_tsc, util_ctr) : printf \n connect fired, destNodesIn.flit[0].valid \n regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) \n node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) \n connect util_ctr_1, _util_ctr_T_3 \n node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) \n connect fired_1, _fired_T_1 \n node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_13 = tail(_T_12, 1) \n node _T_14 = eq(debug_sample, _T_13) \n node _T_15 = and(_T_11, _T_14) \n node _T_16 = and(_T_15, fired_1) \n when _T_16 : \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 14 15 %d\\n\", debug_tsc, util_ctr_1) : printf_1 \n connect fired_1, destNodesIn_1.flit[0].valid \n regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) \n node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) \n connect util_ctr_2, _util_ctr_T_5 \n node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) \n connect fired_2, _fired_T_2 \n node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_21 = tail(_T_20, 1) \n node _T_22 = eq(debug_sample, _T_21) \n node _T_23 = and(_T_19, _T_22) \n node _T_24 = and(_T_23, fired_2) \n when _T_24 : \n node _T_25 = asUInt(reset) \n node _T_26 = eq(_T_25, UInt<1>(0h0)) \n when _T_26 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 16 15 %d\\n\", debug_tsc, util_ctr_2) : printf_2 \n connect fired_2, destNodesIn_2.flit[0].valid"},"response":{"kind":"string","value":"module Router_44(\t// @[Router.scala:89:25]\n input clock,\t// @[Router.scala:89:25]\n input reset,\t// @[Router.scala:89:25]\n output [2:0] auto_debug_out_va_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_va_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_va_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_2_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_2_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_2_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_2_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_2_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_2_vc_free,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_0_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_2_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_2_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_2_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_2_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_2_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_1_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_1_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_1_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_0_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_0_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_0_vc_free\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [19:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire _route_computer_io_resp_2_vc_sel_1_1;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_2_4;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_4;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_1_1;\t// @[Router.scala:136:32]\n wire _vc_allocator_io_req_2_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_1_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_0_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_1_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_2_4;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_4;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_2_4_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_1_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_4_alloc;\t// @[Router.scala:133:30]\n wire _switch_allocator_io_req_2_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_1_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_0_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_2_4_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_1_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_4_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_2_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_2_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_2_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_io_out_2_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_2_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_2_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_2_0_bits_payload;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_2_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_2_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_1_0_bits_payload;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_1_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_1_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_0_0_bits_payload;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_0_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _output_unit_2_to_16_io_credit_available_4;\t// @[Router.scala:122:13]\n wire _output_unit_2_to_16_io_channel_status_4_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_14_io_credit_available_1;\t// @[Router.scala:122:13]\n wire _output_unit_1_to_14_io_channel_status_1_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_6_io_credit_available_4;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_6_io_channel_status_4_occupied;\t// @[Router.scala:122:13]\n wire [2:0] _input_unit_2_from_16_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_2_from_16_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_2_from_16_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_2_from_16_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_2_from_16_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_2_from_16_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_vcalloc_req_bits_vc_sel_1_1;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_2_4;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_1_1;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_2_from_16_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_2_from_16_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_2_from_16_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_14_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_14_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_1_from_14_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_1_from_14_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_1_from_14_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_1_from_14_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_vcalloc_req_bits_vc_sel_2_4;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_vcalloc_req_bits_vc_sel_0_4;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_2_4;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_1_1;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_1_from_14_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_1_from_14_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_1_from_14_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_6_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_6_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_1;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_2_4;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_1;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_6_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_0_from_6_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_6_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_16_io_vcalloc_req_valid};\t// @[Decoupled.scala:51:35]\n reg REG_2_0_2_0;\t// @[Router.scala:178:14]\n reg REG_2_0_1_0;\t// @[Router.scala:178:14]\n reg REG_2_0_0_0;\t// @[Router.scala:178:14]\n reg REG_1_0_2_0;\t// @[Router.scala:178:14]\n reg REG_1_0_1_0;\t// @[Router.scala:178:14]\n reg REG_1_0_0_0;\t// @[Router.scala:178:14]\n reg REG_0_0_2_0;\t// @[Router.scala:178:14]\n reg REG_0_0_1_0;\t// @[Router.scala:178:14]\n reg REG_0_0_0_0;\t// @[Router.scala:178:14]\n reg [63:0] debug_tsc;\t// @[Router.scala:195:28]\n reg [63:0] debug_sample;\t// @[Router.scala:197:31]\n wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1};\t// @[PlusArg.scala:80:11]\n reg [63:0] util_ctr;\t// @[Router.scala:203:29]\n reg fired;\t// @[Router.scala:204:26]\n wire _GEN_0 = (|_plusarg_reader_out) & _GEN;\t// @[PlusArg.scala:80:11]\n wire _GEN_1 = _GEN_0 & fired;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_1;\t// @[Router.scala:203:29]\n reg fired_1;\t// @[Router.scala:204:26]\n wire _GEN_2 = _GEN_0 & fired_1;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_2;\t// @[Router.scala:203:29]\n reg fired_2;\t// @[Router.scala:204:26]\n wire _GEN_3 = _GEN_0 & fired_2;\t// @[Router.scala:204:26, :207:{33,71}]"}}},{"rowIdx":35483,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic : \n input clock : Clock \n input reset : Reset \n output io : { flip addr_matches : UInt<8>, flip youngest_st_idx : UInt<3>, forwarding_val : UInt<1>, forwarding_idx : UInt<3>} \n\n\n wire age_mask : UInt<1>[8] \n connect age_mask[0], UInt<1>(0h1) \n node _T = geq(UInt<1>(0h0), io.youngest_st_idx) \n when _T : \n connect age_mask[0], UInt<1>(0h0) \n connect age_mask[1], UInt<1>(0h1) \n node _T_1 = geq(UInt<1>(0h1), io.youngest_st_idx) \n when _T_1 : \n connect age_mask[1], UInt<1>(0h0) \n connect age_mask[2], UInt<1>(0h1) \n node _T_2 = geq(UInt<2>(0h2), io.youngest_st_idx) \n when _T_2 : \n connect age_mask[2], UInt<1>(0h0) \n connect age_mask[3], UInt<1>(0h1) \n node _T_3 = geq(UInt<2>(0h3), io.youngest_st_idx) \n when _T_3 : \n connect age_mask[3], UInt<1>(0h0) \n connect age_mask[4], UInt<1>(0h1) \n node _T_4 = geq(UInt<3>(0h4), io.youngest_st_idx) \n when _T_4 : \n connect age_mask[4], UInt<1>(0h0) \n connect age_mask[5], UInt<1>(0h1) \n node _T_5 = geq(UInt<3>(0h5), io.youngest_st_idx) \n when _T_5 : \n connect age_mask[5], UInt<1>(0h0) \n connect age_mask[6], UInt<1>(0h1) \n node _T_6 = geq(UInt<3>(0h6), io.youngest_st_idx) \n when _T_6 : \n connect age_mask[6], UInt<1>(0h0) \n connect age_mask[7], UInt<1>(0h1) \n node _T_7 = geq(UInt<3>(0h7), io.youngest_st_idx) \n when _T_7 : \n connect age_mask[7], UInt<1>(0h0) \n wire matches : UInt<16> \n node matches_lo_lo = cat(age_mask[1], age_mask[0]) \n node matches_lo_hi = cat(age_mask[3], age_mask[2]) \n node matches_lo = cat(matches_lo_hi, matches_lo_lo) \n node matches_hi_lo = cat(age_mask[5], age_mask[4]) \n node matches_hi_hi = cat(age_mask[7], age_mask[6]) \n node matches_hi = cat(matches_hi_hi, matches_hi_lo) \n node _matches_T = cat(matches_hi, matches_lo) \n node _matches_T_1 = and(io.addr_matches, _matches_T) \n node _matches_T_2 = cat(_matches_T_1, io.addr_matches) \n connect matches, _matches_T_2 \n wire found_match : UInt<1> \n connect found_match, UInt<1>(0h0) \n connect io.forwarding_idx, UInt<1>(0h0) \n node _T_8 = bits(matches, 0, 0) \n when _T_8 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<1>(0h0) \n node _T_9 = bits(matches, 1, 1) \n when _T_9 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<1>(0h1) \n node _T_10 = bits(matches, 2, 2) \n when _T_10 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<2>(0h2) \n node _T_11 = bits(matches, 3, 3) \n when _T_11 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<2>(0h3) \n node _T_12 = bits(matches, 4, 4) \n when _T_12 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h4) \n node _T_13 = bits(matches, 5, 5) \n when _T_13 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h5) \n node _T_14 = bits(matches, 6, 6) \n when _T_14 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h6) \n node _T_15 = bits(matches, 7, 7) \n when _T_15 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h7) \n node _T_16 = bits(matches, 8, 8) \n when _T_16 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<1>(0h0) \n node _T_17 = bits(matches, 9, 9) \n when _T_17 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<1>(0h1) \n node _T_18 = bits(matches, 10, 10) \n when _T_18 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<2>(0h2) \n node _T_19 = bits(matches, 11, 11) \n when _T_19 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<2>(0h3) \n node _T_20 = bits(matches, 12, 12) \n when _T_20 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h4) \n node _T_21 = bits(matches, 13, 13) \n when _T_21 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h5) \n node _T_22 = bits(matches, 14, 14) \n when _T_22 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h6) \n node _T_23 = bits(matches, 15, 15) \n when _T_23 : \n connect found_match, UInt<1>(0h1) \n connect io.forwarding_idx, UInt<3>(0h7) \n connect io.forwarding_val, found_match"},"response":{"kind":"string","value":"module ForwardingAgeLogic(\t// @[lsu.scala:1678:7]\n input clock,\t// @[lsu.scala:1678:7]\n input reset,\t// @[lsu.scala:1678:7]\n input [7:0] io_addr_matches,\t// @[lsu.scala:1680:15]\n input [2:0] io_youngest_st_idx,\t// @[lsu.scala:1680:15]\n output [2:0] io_forwarding_idx\t// @[lsu.scala:1680:15]\n);\n\n wire [7:0] io_addr_matches_0 = io_addr_matches;\t// @[lsu.scala:1678:7]\n wire [2:0] io_youngest_st_idx_0 = io_youngest_st_idx;\t// @[lsu.scala:1678:7]\n wire age_mask_7 = 1'h0;\t// @[lsu.scala:1691:23]\n wire found_match;\t// @[lsu.scala:1706:26]\n wire io_forwarding_val;\t// @[lsu.scala:1678:7]\n wire [2:0] io_forwarding_idx_0;\t// @[lsu.scala:1678:7]\n wire age_mask_0;\t// @[lsu.scala:1691:23]\n wire age_mask_1;\t// @[lsu.scala:1691:23]\n wire age_mask_2;\t// @[lsu.scala:1691:23]\n wire age_mask_3;\t// @[lsu.scala:1691:23]\n wire age_mask_4;\t// @[lsu.scala:1691:23]\n wire age_mask_5;\t// @[lsu.scala:1691:23]\n wire age_mask_6;\t// @[lsu.scala:1691:23]\n assign age_mask_0 = |io_youngest_st_idx_0;\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_1 = |(io_youngest_st_idx_0[2:1]);\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_2 = io_youngest_st_idx_0 > 3'h2;\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_3 = io_youngest_st_idx_0[2];\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_4 = io_youngest_st_idx_0 > 3'h4;\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_5 = io_youngest_st_idx_0 > 3'h5;\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n assign age_mask_6 = &io_youngest_st_idx_0;\t// @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]\n wire [15:0] _matches_T_2;\t// @[lsu.scala:1703:18]\n wire [15:0] matches_0;\t// @[lsu.scala:1702:22]\n wire [1:0] matches_lo_lo = {age_mask_1, age_mask_0};\t// @[lsu.scala:1691:23, :1703:46]\n wire [1:0] matches_lo_hi = {age_mask_3, age_mask_2};\t// @[lsu.scala:1691:23, :1703:46]\n wire [3:0] matches_lo = {matches_lo_hi, matches_lo_lo};\t// @[lsu.scala:1703:46]\n wire [1:0] matches_hi_lo = {age_mask_5, age_mask_4};\t// @[lsu.scala:1691:23, :1703:46]\n wire [1:0] matches_hi_hi = {1'h0, age_mask_6};\t// @[lsu.scala:1691:23, :1703:46]\n wire [3:0] matches_hi = {matches_hi_hi, matches_hi_lo};\t// @[lsu.scala:1703:46]\n wire [7:0] _matches_T = {matches_hi, matches_lo};\t// @[lsu.scala:1703:46]\n wire [7:0] _matches_T_1 = io_addr_matches_0 & _matches_T;\t// @[lsu.scala:1678:7, :1703:{35,46}]\n assign _matches_T_2 = {_matches_T_1, io_addr_matches_0};\t// @[lsu.scala:1678:7, :1703:{18,35}]\n assign matches_0 = _matches_T_2;\t// @[lsu.scala:1702:22, :1703:18]\n assign io_forwarding_val = found_match;\t// @[lsu.scala:1678:7, :1706:26]\n assign found_match = |matches_0;\t// @[lsu.scala:1702:22, :1706:26, :1714:7, :1715:22]\n assign io_forwarding_idx_0 = matches_0[15] ? 3'h7 : matches_0[14] ? 3'h6 : matches_0[13] ? 3'h5 : matches_0[12] ? 3'h4 : matches_0[11] ? 3'h3 : matches_0[10] ? 3'h2 : matches_0[9] ? 3'h1 : matches_0[8] ? 3'h0 : matches_0[7] ? 3'h7 : matches_0[6] ? 3'h6 : matches_0[5] ? 3'h5 : matches_0[4] ? 3'h4 : matches_0[3] ? 3'h3 : matches_0[2] ? 3'h2 : {2'h0, matches_0[1]};\t// @[lsu.scala:1678:7, :1694:19, :1695:17, :1696:7, :1697:22, :1702:22, :1713:20, :1714:7, :1716:28]\n assign io_forwarding_idx = io_forwarding_idx_0;\t// @[lsu.scala:1678:7]\nendmodule"}}},{"rowIdx":35484,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AXI4Fragmenter_1 : \n input clock : Clock \n input reset : Reset \n output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}} \n\n\n wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}} \n invalidate nodeIn.r.bits.last \n invalidate nodeIn.r.bits.resp \n invalidate nodeIn.r.bits.data \n invalidate nodeIn.r.bits.id \n invalidate nodeIn.r.valid \n invalidate nodeIn.r.ready \n invalidate nodeIn.ar.bits.qos \n invalidate nodeIn.ar.bits.prot \n invalidate nodeIn.ar.bits.cache \n invalidate nodeIn.ar.bits.lock \n invalidate nodeIn.ar.bits.burst \n invalidate nodeIn.ar.bits.size \n invalidate nodeIn.ar.bits.len \n invalidate nodeIn.ar.bits.addr \n invalidate nodeIn.ar.bits.id \n invalidate nodeIn.ar.valid \n invalidate nodeIn.ar.ready \n invalidate nodeIn.b.bits.resp \n invalidate nodeIn.b.bits.id \n invalidate nodeIn.b.valid \n invalidate nodeIn.b.ready \n invalidate nodeIn.w.bits.last \n invalidate nodeIn.w.bits.strb \n invalidate nodeIn.w.bits.data \n invalidate nodeIn.w.valid \n invalidate nodeIn.w.ready \n invalidate nodeIn.aw.bits.qos \n invalidate nodeIn.aw.bits.prot \n invalidate nodeIn.aw.bits.cache \n invalidate nodeIn.aw.bits.lock \n invalidate nodeIn.aw.bits.burst \n invalidate nodeIn.aw.bits.size \n invalidate nodeIn.aw.bits.len \n invalidate nodeIn.aw.bits.addr \n invalidate nodeIn.aw.bits.id \n invalidate nodeIn.aw.valid \n invalidate nodeIn.aw.ready \n wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}} \n invalidate nodeOut.r.bits.last \n invalidate nodeOut.r.bits.echo.real_last \n invalidate nodeOut.r.bits.resp \n invalidate nodeOut.r.bits.data \n invalidate nodeOut.r.bits.id \n invalidate nodeOut.r.valid \n invalidate nodeOut.r.ready \n invalidate nodeOut.ar.bits.echo.real_last \n invalidate nodeOut.ar.bits.qos \n invalidate nodeOut.ar.bits.prot \n invalidate nodeOut.ar.bits.cache \n invalidate nodeOut.ar.bits.lock \n invalidate nodeOut.ar.bits.burst \n invalidate nodeOut.ar.bits.size \n invalidate nodeOut.ar.bits.len \n invalidate nodeOut.ar.bits.addr \n invalidate nodeOut.ar.bits.id \n invalidate nodeOut.ar.valid \n invalidate nodeOut.ar.ready \n invalidate nodeOut.b.bits.echo.real_last \n invalidate nodeOut.b.bits.resp \n invalidate nodeOut.b.bits.id \n invalidate nodeOut.b.valid \n invalidate nodeOut.b.ready \n invalidate nodeOut.w.bits.last \n invalidate nodeOut.w.bits.strb \n invalidate nodeOut.w.bits.data \n invalidate nodeOut.w.valid \n invalidate nodeOut.w.ready \n invalidate nodeOut.aw.bits.echo.real_last \n invalidate nodeOut.aw.bits.qos \n invalidate nodeOut.aw.bits.prot \n invalidate nodeOut.aw.bits.cache \n invalidate nodeOut.aw.bits.lock \n invalidate nodeOut.aw.bits.burst \n invalidate nodeOut.aw.bits.size \n invalidate nodeOut.aw.bits.len \n invalidate nodeOut.aw.bits.addr \n invalidate nodeOut.aw.bits.id \n invalidate nodeOut.aw.valid \n invalidate nodeOut.aw.ready \n connect auto.out, nodeOut \n connect nodeIn, auto.in \n inst deq_q of Queue1_AXI4BundleAR_1 \n connect deq_q.clock, clock\n\n connect deq_q.reset, reset\n\n connect deq_q.io.enq.valid, nodeIn.ar.valid \n connect deq_q.io.enq.bits.qos, nodeIn.ar.bits.qos \n connect deq_q.io.enq.bits.prot, nodeIn.ar.bits.prot \n connect deq_q.io.enq.bits.cache, nodeIn.ar.bits.cache \n connect deq_q.io.enq.bits.lock, nodeIn.ar.bits.lock \n connect deq_q.io.enq.bits.burst, nodeIn.ar.bits.burst \n connect deq_q.io.enq.bits.size, nodeIn.ar.bits.size \n connect deq_q.io.enq.bits.len, nodeIn.ar.bits.len \n connect deq_q.io.enq.bits.addr, nodeIn.ar.bits.addr \n connect deq_q.io.enq.bits.id, nodeIn.ar.bits.id \n connect nodeIn.ar.ready, deq_q.io.enq.ready \n wire irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}} \n connect irr.bits, deq_q.io.deq.bits \n connect irr.valid, deq_q.io.deq.valid \n connect deq_q.io.deq.ready, irr.ready \n wire in_ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}} \n regreset busy : UInt<1>, clock, reset, UInt<1>(0h0) \n reg r_addr : UInt<29>, clock \n reg r_len : UInt<8>, clock \n node len = mux(busy, r_len, irr.bits.len) \n node addr = mux(busy, r_addr, irr.bits.addr) \n node lo = bits(addr, 2, 0) \n node alignment = bits(addr, 10, 3) \n node _support1_T = xor(addr, UInt<1>(0h0)) \n node _support1_T_1 = cvt(_support1_T) \n node _support1_T_2 = and(_support1_T_1, asSInt(UInt<1>(0h0))) \n node _support1_T_3 = asSInt(_support1_T_2) \n node _support1_T_4 = eq(_support1_T_3, asSInt(UInt<1>(0h0))) \n node _fillLow_T = shr(len, 1) \n node _fillLow_T_1 = or(len, _fillLow_T) \n node _fillLow_T_2 = shr(_fillLow_T_1, 2) \n node _fillLow_T_3 = or(_fillLow_T_1, _fillLow_T_2) \n node _fillLow_T_4 = shr(_fillLow_T_3, 4) \n node _fillLow_T_5 = or(_fillLow_T_3, _fillLow_T_4) \n node _fillLow_T_6 = bits(_fillLow_T_5, 7, 0) \n node fillLow = shr(_fillLow_T_6, 1) \n node _wipeHigh_T = not(len) \n node _wipeHigh_T_1 = shl(_wipeHigh_T, 1) \n node _wipeHigh_T_2 = bits(_wipeHigh_T_1, 7, 0) \n node _wipeHigh_T_3 = or(_wipeHigh_T, _wipeHigh_T_2) \n node _wipeHigh_T_4 = shl(_wipeHigh_T_3, 2) \n node _wipeHigh_T_5 = bits(_wipeHigh_T_4, 7, 0) \n node _wipeHigh_T_6 = or(_wipeHigh_T_3, _wipeHigh_T_5) \n node _wipeHigh_T_7 = shl(_wipeHigh_T_6, 4) \n node _wipeHigh_T_8 = bits(_wipeHigh_T_7, 7, 0) \n node _wipeHigh_T_9 = or(_wipeHigh_T_6, _wipeHigh_T_8) \n node _wipeHigh_T_10 = bits(_wipeHigh_T_9, 7, 0) \n node wipeHigh = not(_wipeHigh_T_10) \n node remain1 = or(fillLow, wipeHigh) \n node _align1_T = shl(alignment, 1) \n node _align1_T_1 = bits(_align1_T, 7, 0) \n node _align1_T_2 = or(alignment, _align1_T_1) \n node _align1_T_3 = shl(_align1_T_2, 2) \n node _align1_T_4 = bits(_align1_T_3, 7, 0) \n node _align1_T_5 = or(_align1_T_2, _align1_T_4) \n node _align1_T_6 = shl(_align1_T_5, 4) \n node _align1_T_7 = bits(_align1_T_6, 7, 0) \n node _align1_T_8 = or(_align1_T_5, _align1_T_7) \n node _align1_T_9 = bits(_align1_T_8, 7, 0) \n node align1 = not(_align1_T_9) \n node _maxSupported1_T = and(remain1, align1) \n node maxSupported1 = and(_maxSupported1_T, UInt<1>(0h0)) \n node fixed = eq(irr.bits.burst, UInt<2>(0h0)) \n node narrow = neq(irr.bits.size, UInt<2>(0h3)) \n node bad = or(fixed, narrow) \n node beats1 = mux(bad, UInt<1>(0h0), maxSupported1) \n node _beats_T = shl(beats1, 1) \n node _beats_T_1 = or(_beats_T, UInt<1>(0h1)) \n node _beats_T_2 = cat(UInt<1>(0h0), beats1) \n node _beats_T_3 = not(_beats_T_2) \n node beats = and(_beats_T_1, _beats_T_3) \n node _inc_addr_T = dshl(beats, irr.bits.size) \n node _inc_addr_T_1 = add(addr, _inc_addr_T) \n node inc_addr = tail(_inc_addr_T_1, 1) \n node _wrapMask_T = cat(irr.bits.len, UInt<8>(0hff)) \n node _wrapMask_T_1 = dshl(_wrapMask_T, irr.bits.size) \n node wrapMask = shr(_wrapMask_T_1, 8) \n wire mux_addr : UInt \n connect mux_addr, inc_addr \n node _T = eq(irr.bits.burst, UInt<2>(0h2)) \n when _T : \n node _mux_addr_T = and(inc_addr, wrapMask) \n node _mux_addr_T_1 = not(irr.bits.addr) \n node _mux_addr_T_2 = or(_mux_addr_T_1, wrapMask) \n node _mux_addr_T_3 = not(_mux_addr_T_2) \n node _mux_addr_T_4 = or(_mux_addr_T, _mux_addr_T_3) \n connect mux_addr, _mux_addr_T_4 \n node _T_1 = eq(irr.bits.burst, UInt<2>(0h0)) \n when _T_1 : \n connect mux_addr, irr.bits.addr \n node ar_last = eq(beats1, len) \n node _irr_ready_T = and(in_ar.ready, ar_last) \n connect irr.ready, _irr_ready_T \n connect in_ar.valid, irr.valid \n connect in_ar.bits.qos, irr.bits.qos \n connect in_ar.bits.prot, irr.bits.prot \n connect in_ar.bits.cache, irr.bits.cache \n connect in_ar.bits.lock, irr.bits.lock \n connect in_ar.bits.burst, irr.bits.burst \n connect in_ar.bits.size, irr.bits.size \n connect in_ar.bits.len, irr.bits.len \n connect in_ar.bits.addr, irr.bits.addr \n connect in_ar.bits.id, irr.bits.id \n connect in_ar.bits.len, beats1 \n node _out_bits_addr_T = not(addr) \n node _out_bits_addr_T_1 = dshl(UInt<3>(0h7), irr.bits.size) \n node _out_bits_addr_T_2 = bits(_out_bits_addr_T_1, 2, 0) \n node _out_bits_addr_T_3 = not(_out_bits_addr_T_2) \n node _out_bits_addr_T_4 = or(_out_bits_addr_T, _out_bits_addr_T_3) \n node _out_bits_addr_T_5 = not(_out_bits_addr_T_4) \n connect in_ar.bits.addr, _out_bits_addr_T_5 \n node _T_2 = and(in_ar.ready, in_ar.valid) \n when _T_2 : \n node _busy_T = eq(ar_last, UInt<1>(0h0)) \n connect busy, _busy_T \n connect r_addr, mux_addr \n node _r_len_T = sub(len, beats) \n node _r_len_T_1 = tail(_r_len_T, 1) \n connect r_len, _r_len_T_1 \n inst deq_q_1 of Queue1_AXI4BundleAW_1 \n connect deq_q_1.clock, clock\n\n connect deq_q_1.reset, reset\n\n connect deq_q_1.io.enq.valid, nodeIn.aw.valid \n connect deq_q_1.io.enq.bits.qos, nodeIn.aw.bits.qos \n connect deq_q_1.io.enq.bits.prot, nodeIn.aw.bits.prot \n connect deq_q_1.io.enq.bits.cache, nodeIn.aw.bits.cache \n connect deq_q_1.io.enq.bits.lock, nodeIn.aw.bits.lock \n connect deq_q_1.io.enq.bits.burst, nodeIn.aw.bits.burst \n connect deq_q_1.io.enq.bits.size, nodeIn.aw.bits.size \n connect deq_q_1.io.enq.bits.len, nodeIn.aw.bits.len \n connect deq_q_1.io.enq.bits.addr, nodeIn.aw.bits.addr \n connect deq_q_1.io.enq.bits.id, nodeIn.aw.bits.id \n connect nodeIn.aw.ready, deq_q_1.io.enq.ready \n wire irr_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}} \n connect irr_1.bits, deq_q_1.io.deq.bits \n connect irr_1.valid, deq_q_1.io.deq.valid \n connect deq_q_1.io.deq.ready, irr_1.ready \n wire in_aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}} \n regreset busy_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n reg r_addr_1 : UInt<29>, clock \n reg r_len_1 : UInt<8>, clock \n node len_1 = mux(busy_1, r_len_1, irr_1.bits.len) \n node addr_1 = mux(busy_1, r_addr_1, irr_1.bits.addr) \n node lo_1 = bits(addr_1, 2, 0) \n node alignment_1 = bits(addr_1, 10, 3) \n node _support1_T_5 = xor(addr_1, UInt<1>(0h0)) \n node _support1_T_6 = cvt(_support1_T_5) \n node _support1_T_7 = and(_support1_T_6, asSInt(UInt<1>(0h0))) \n node _support1_T_8 = asSInt(_support1_T_7) \n node _support1_T_9 = eq(_support1_T_8, asSInt(UInt<1>(0h0))) \n node _fillLow_T_7 = shr(len_1, 1) \n node _fillLow_T_8 = or(len_1, _fillLow_T_7) \n node _fillLow_T_9 = shr(_fillLow_T_8, 2) \n node _fillLow_T_10 = or(_fillLow_T_8, _fillLow_T_9) \n node _fillLow_T_11 = shr(_fillLow_T_10, 4) \n node _fillLow_T_12 = or(_fillLow_T_10, _fillLow_T_11) \n node _fillLow_T_13 = bits(_fillLow_T_12, 7, 0) \n node fillLow_1 = shr(_fillLow_T_13, 1) \n node _wipeHigh_T_11 = not(len_1) \n node _wipeHigh_T_12 = shl(_wipeHigh_T_11, 1) \n node _wipeHigh_T_13 = bits(_wipeHigh_T_12, 7, 0) \n node _wipeHigh_T_14 = or(_wipeHigh_T_11, _wipeHigh_T_13) \n node _wipeHigh_T_15 = shl(_wipeHigh_T_14, 2) \n node _wipeHigh_T_16 = bits(_wipeHigh_T_15, 7, 0) \n node _wipeHigh_T_17 = or(_wipeHigh_T_14, _wipeHigh_T_16) \n node _wipeHigh_T_18 = shl(_wipeHigh_T_17, 4) \n node _wipeHigh_T_19 = bits(_wipeHigh_T_18, 7, 0) \n node _wipeHigh_T_20 = or(_wipeHigh_T_17, _wipeHigh_T_19) \n node _wipeHigh_T_21 = bits(_wipeHigh_T_20, 7, 0) \n node wipeHigh_1 = not(_wipeHigh_T_21) \n node remain1_1 = or(fillLow_1, wipeHigh_1) \n node _align1_T_10 = shl(alignment_1, 1) \n node _align1_T_11 = bits(_align1_T_10, 7, 0) \n node _align1_T_12 = or(alignment_1, _align1_T_11) \n node _align1_T_13 = shl(_align1_T_12, 2) \n node _align1_T_14 = bits(_align1_T_13, 7, 0) \n node _align1_T_15 = or(_align1_T_12, _align1_T_14) \n node _align1_T_16 = shl(_align1_T_15, 4) \n node _align1_T_17 = bits(_align1_T_16, 7, 0) \n node _align1_T_18 = or(_align1_T_15, _align1_T_17) \n node _align1_T_19 = bits(_align1_T_18, 7, 0) \n node align1_1 = not(_align1_T_19) \n node _maxSupported1_T_1 = and(remain1_1, align1_1) \n node maxSupported1_1 = and(_maxSupported1_T_1, UInt<1>(0h0)) \n node fixed_1 = eq(irr_1.bits.burst, UInt<2>(0h0)) \n node narrow_1 = neq(irr_1.bits.size, UInt<2>(0h3)) \n node bad_1 = or(fixed_1, narrow_1) \n node beats1_1 = mux(bad_1, UInt<1>(0h0), maxSupported1_1) \n node _beats_T_4 = shl(beats1_1, 1) \n node _beats_T_5 = or(_beats_T_4, UInt<1>(0h1)) \n node _beats_T_6 = cat(UInt<1>(0h0), beats1_1) \n node _beats_T_7 = not(_beats_T_6) \n node w_beats = and(_beats_T_5, _beats_T_7) \n node _inc_addr_T_2 = dshl(w_beats, irr_1.bits.size) \n node _inc_addr_T_3 = add(addr_1, _inc_addr_T_2) \n node inc_addr_1 = tail(_inc_addr_T_3, 1) \n node _wrapMask_T_2 = cat(irr_1.bits.len, UInt<8>(0hff)) \n node _wrapMask_T_3 = dshl(_wrapMask_T_2, irr_1.bits.size) \n node wrapMask_1 = shr(_wrapMask_T_3, 8) \n wire mux_addr_1 : UInt \n connect mux_addr_1, inc_addr_1 \n node _T_3 = eq(irr_1.bits.burst, UInt<2>(0h2)) \n when _T_3 : \n node _mux_addr_T_5 = and(inc_addr_1, wrapMask_1) \n node _mux_addr_T_6 = not(irr_1.bits.addr) \n node _mux_addr_T_7 = or(_mux_addr_T_6, wrapMask_1) \n node _mux_addr_T_8 = not(_mux_addr_T_7) \n node _mux_addr_T_9 = or(_mux_addr_T_5, _mux_addr_T_8) \n connect mux_addr_1, _mux_addr_T_9 \n node _T_4 = eq(irr_1.bits.burst, UInt<2>(0h0)) \n when _T_4 : \n connect mux_addr_1, irr_1.bits.addr \n node aw_last = eq(beats1_1, len_1) \n node _irr_ready_T_1 = and(in_aw.ready, aw_last) \n connect irr_1.ready, _irr_ready_T_1 \n connect in_aw.valid, irr_1.valid \n connect in_aw.bits.qos, irr_1.bits.qos \n connect in_aw.bits.prot, irr_1.bits.prot \n connect in_aw.bits.cache, irr_1.bits.cache \n connect in_aw.bits.lock, irr_1.bits.lock \n connect in_aw.bits.burst, irr_1.bits.burst \n connect in_aw.bits.size, irr_1.bits.size \n connect in_aw.bits.len, irr_1.bits.len \n connect in_aw.bits.addr, irr_1.bits.addr \n connect in_aw.bits.id, irr_1.bits.id \n connect in_aw.bits.len, beats1_1 \n node _out_bits_addr_T_6 = not(addr_1) \n node _out_bits_addr_T_7 = dshl(UInt<3>(0h7), irr_1.bits.size) \n node _out_bits_addr_T_8 = bits(_out_bits_addr_T_7, 2, 0) \n node _out_bits_addr_T_9 = not(_out_bits_addr_T_8) \n node _out_bits_addr_T_10 = or(_out_bits_addr_T_6, _out_bits_addr_T_9) \n node _out_bits_addr_T_11 = not(_out_bits_addr_T_10) \n connect in_aw.bits.addr, _out_bits_addr_T_11 \n node _T_5 = and(in_aw.ready, in_aw.valid) \n when _T_5 : \n node _busy_T_1 = eq(aw_last, UInt<1>(0h0)) \n connect busy_1, _busy_T_1 \n connect r_addr_1, mux_addr_1 \n node _r_len_T_2 = sub(len_1, w_beats) \n node _r_len_T_3 = tail(_r_len_T_2, 1) \n connect r_len_1, _r_len_T_3 \n inst in_w_deq_q of Queue1_AXI4BundleW_2 \n connect in_w_deq_q.clock, clock\n\n connect in_w_deq_q.reset, reset\n\n connect in_w_deq_q.io.enq.valid, nodeIn.w.valid \n connect in_w_deq_q.io.enq.bits.last, nodeIn.w.bits.last \n connect in_w_deq_q.io.enq.bits.strb, nodeIn.w.bits.strb \n connect in_w_deq_q.io.enq.bits.data, nodeIn.w.bits.data \n connect nodeIn.w.ready, in_w_deq_q.io.enq.ready \n wire in_w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}} \n connect in_w.bits, in_w_deq_q.io.deq.bits \n connect in_w.valid, in_w_deq_q.io.deq.valid \n connect in_w_deq_q.io.deq.ready, in_w.ready \n connect nodeOut.ar.bits.qos, in_ar.bits.qos \n connect nodeOut.ar.bits.prot, in_ar.bits.prot \n connect nodeOut.ar.bits.cache, in_ar.bits.cache \n connect nodeOut.ar.bits.lock, in_ar.bits.lock \n connect nodeOut.ar.bits.burst, in_ar.bits.burst \n connect nodeOut.ar.bits.size, in_ar.bits.size \n connect nodeOut.ar.bits.len, in_ar.bits.len \n connect nodeOut.ar.bits.addr, in_ar.bits.addr \n connect nodeOut.ar.bits.id, in_ar.bits.id \n connect nodeOut.ar.valid, in_ar.valid \n connect in_ar.ready, nodeOut.ar.ready \n connect nodeOut.ar.bits.echo.real_last, ar_last \n regreset wbeats_latched : UInt<1>, clock, reset, UInt<1>(0h0) \n wire wbeats_ready : UInt<1> \n wire wbeats_valid : UInt<1> \n node _T_6 = and(wbeats_valid, wbeats_ready) \n when _T_6 : \n connect wbeats_latched, UInt<1>(0h1) \n node _T_7 = and(nodeOut.aw.ready, nodeOut.aw.valid) \n when _T_7 : \n connect wbeats_latched, UInt<1>(0h0) \n node _nodeOut_aw_valid_T = or(wbeats_ready, wbeats_latched) \n node _nodeOut_aw_valid_T_1 = and(in_aw.valid, _nodeOut_aw_valid_T) \n connect nodeOut.aw.valid, _nodeOut_aw_valid_T_1 \n node _in_aw_ready_T = or(wbeats_ready, wbeats_latched) \n node _in_aw_ready_T_1 = and(nodeOut.aw.ready, _in_aw_ready_T) \n connect in_aw.ready, _in_aw_ready_T_1 \n node _wbeats_valid_T = eq(wbeats_latched, UInt<1>(0h0)) \n node _wbeats_valid_T_1 = and(in_aw.valid, _wbeats_valid_T) \n connect wbeats_valid, _wbeats_valid_T_1 \n connect nodeOut.aw.bits.qos, in_aw.bits.qos \n connect nodeOut.aw.bits.prot, in_aw.bits.prot \n connect nodeOut.aw.bits.cache, in_aw.bits.cache \n connect nodeOut.aw.bits.lock, in_aw.bits.lock \n connect nodeOut.aw.bits.burst, in_aw.bits.burst \n connect nodeOut.aw.bits.size, in_aw.bits.size \n connect nodeOut.aw.bits.len, in_aw.bits.len \n connect nodeOut.aw.bits.addr, in_aw.bits.addr \n connect nodeOut.aw.bits.id, in_aw.bits.id \n connect nodeOut.aw.bits.echo.real_last, aw_last \n regreset w_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node w_idle = eq(w_counter, UInt<1>(0h0)) \n node _w_todo_T = mux(wbeats_valid, w_beats, UInt<1>(0h0)) \n node w_todo = mux(w_idle, _w_todo_T, w_counter) \n node w_last = eq(w_todo, UInt<1>(0h1)) \n node _w_counter_T = and(nodeOut.w.ready, nodeOut.w.valid) \n node _w_counter_T_1 = sub(w_todo, _w_counter_T) \n node _w_counter_T_2 = tail(_w_counter_T_1, 1) \n connect w_counter, _w_counter_T_2 \n node _T_8 = and(nodeOut.w.ready, nodeOut.w.valid) \n node _T_9 = eq(_T_8, UInt<1>(0h0)) \n node _T_10 = neq(w_todo, UInt<1>(0h0)) \n node _T_11 = or(_T_9, _T_10) \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n node _T_14 = eq(_T_11, UInt<1>(0h0)) \n when _T_14 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Fragmenter.scala:181 assert (!out.w.fire || w_todo =/= 0.U) // underflow impossible\\n\") : printf \n assert(clock, _T_11, UInt<1>(0h1), \"\") : assert \n connect wbeats_ready, w_idle \n node _nodeOut_w_valid_T = eq(wbeats_ready, UInt<1>(0h0)) \n node _nodeOut_w_valid_T_1 = or(_nodeOut_w_valid_T, wbeats_valid) \n node _nodeOut_w_valid_T_2 = and(in_w.valid, _nodeOut_w_valid_T_1) \n connect nodeOut.w.valid, _nodeOut_w_valid_T_2 \n node _in_w_ready_T = eq(wbeats_ready, UInt<1>(0h0)) \n node _in_w_ready_T_1 = or(_in_w_ready_T, wbeats_valid) \n node _in_w_ready_T_2 = and(nodeOut.w.ready, _in_w_ready_T_1) \n connect in_w.ready, _in_w_ready_T_2 \n connect nodeOut.w.bits.last, in_w.bits.last \n connect nodeOut.w.bits.strb, in_w.bits.strb \n connect nodeOut.w.bits.data, in_w.bits.data \n connect nodeOut.w.bits.last, w_last \n node _T_15 = eq(nodeOut.w.valid, UInt<1>(0h0)) \n node _T_16 = eq(in_w.bits.last, UInt<1>(0h0)) \n node _T_17 = or(_T_15, _T_16) \n node _T_18 = or(_T_17, w_last) \n node _T_19 = asUInt(reset) \n node _T_20 = eq(_T_19, UInt<1>(0h0)) \n when _T_20 : \n node _T_21 = eq(_T_18, UInt<1>(0h0)) \n when _T_21 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Fragmenter.scala:190 assert (!out.w.valid || !in_w.bits.last || w_last)\\n\") : printf_1 \n assert(clock, _T_18, UInt<1>(0h1), \"\") : assert_1 \n connect nodeIn.r.bits.last, nodeOut.r.bits.last \n connect nodeIn.r.bits.resp, nodeOut.r.bits.resp \n connect nodeIn.r.bits.data, nodeOut.r.bits.data \n connect nodeIn.r.bits.id, nodeOut.r.bits.id \n connect nodeIn.r.valid, nodeOut.r.valid \n connect nodeOut.r.ready, nodeIn.r.ready \n node _nodeIn_r_bits_last_T = and(nodeOut.r.bits.last, nodeOut.r.bits.echo.real_last) \n connect nodeIn.r.bits.last, _nodeIn_r_bits_last_T \n connect nodeIn.b.bits.resp, nodeOut.b.bits.resp \n connect nodeIn.b.bits.id, nodeOut.b.bits.id \n connect nodeIn.b.valid, nodeOut.b.valid \n connect nodeOut.b.ready, nodeIn.b.ready \n node _nodeIn_b_valid_T = and(nodeOut.b.valid, nodeOut.b.bits.echo.real_last) \n connect nodeIn.b.valid, _nodeIn_b_valid_T \n node _nodeOut_b_ready_T = eq(nodeOut.b.bits.echo.real_last, UInt<1>(0h0)) \n node _nodeOut_b_ready_T_1 = or(nodeIn.b.ready, _nodeOut_b_ready_T) \n connect nodeOut.b.ready, _nodeOut_b_ready_T_1 \n wire _error_WIRE : UInt<2>[16] \n connect _error_WIRE[0], UInt<2>(0h0) \n connect _error_WIRE[1], UInt<2>(0h0) \n connect _error_WIRE[2], UInt<2>(0h0) \n connect _error_WIRE[3], UInt<2>(0h0) \n connect _error_WIRE[4], UInt<2>(0h0) \n connect _error_WIRE[5], UInt<2>(0h0) \n connect _error_WIRE[6], UInt<2>(0h0) \n connect _error_WIRE[7], UInt<2>(0h0) \n connect _error_WIRE[8], UInt<2>(0h0) \n connect _error_WIRE[9], UInt<2>(0h0) \n connect _error_WIRE[10], UInt<2>(0h0) \n connect _error_WIRE[11], UInt<2>(0h0) \n connect _error_WIRE[12], UInt<2>(0h0) \n connect _error_WIRE[13], UInt<2>(0h0) \n connect _error_WIRE[14], UInt<2>(0h0) \n connect _error_WIRE[15], UInt<2>(0h0) \n regreset error : UInt<2>[16], clock, reset, _error_WIRE \n node _nodeIn_b_bits_resp_T = or(nodeOut.b.bits.resp, error[nodeOut.b.bits.id]) \n connect nodeIn.b.bits.resp, _nodeIn_b_bits_resp_T \n node shiftAmount = bits(nodeOut.b.bits.id, 3, 0) \n node _T_22 = dshl(UInt<1>(0h1), shiftAmount) \n node _T_23 = bits(_T_22, 15, 0) \n node _T_24 = bits(_T_23, 0, 0) \n node _T_25 = bits(_T_23, 1, 1) \n node _T_26 = bits(_T_23, 2, 2) \n node _T_27 = bits(_T_23, 3, 3) \n node _T_28 = bits(_T_23, 4, 4) \n node _T_29 = bits(_T_23, 5, 5) \n node _T_30 = bits(_T_23, 6, 6) \n node _T_31 = bits(_T_23, 7, 7) \n node _T_32 = bits(_T_23, 8, 8) \n node _T_33 = bits(_T_23, 9, 9) \n node _T_34 = bits(_T_23, 10, 10) \n node _T_35 = bits(_T_23, 11, 11) \n node _T_36 = bits(_T_23, 12, 12) \n node _T_37 = bits(_T_23, 13, 13) \n node _T_38 = bits(_T_23, 14, 14) \n node _T_39 = bits(_T_23, 15, 15) \n node _T_40 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_41 = and(_T_24, _T_40) \n when _T_41 : \n node _error_0_T = or(error[0], nodeOut.b.bits.resp) \n node _error_0_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_0_T) \n connect error[0], _error_0_T_1 \n node _T_42 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_43 = and(_T_25, _T_42) \n when _T_43 : \n node _error_1_T = or(error[1], nodeOut.b.bits.resp) \n node _error_1_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_1_T) \n connect error[1], _error_1_T_1 \n node _T_44 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_45 = and(_T_26, _T_44) \n when _T_45 : \n node _error_2_T = or(error[2], nodeOut.b.bits.resp) \n node _error_2_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_2_T) \n connect error[2], _error_2_T_1 \n node _T_46 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_47 = and(_T_27, _T_46) \n when _T_47 : \n node _error_3_T = or(error[3], nodeOut.b.bits.resp) \n node _error_3_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_3_T) \n connect error[3], _error_3_T_1 \n node _T_48 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_49 = and(_T_28, _T_48) \n when _T_49 : \n node _error_4_T = or(error[4], nodeOut.b.bits.resp) \n node _error_4_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_4_T) \n connect error[4], _error_4_T_1 \n node _T_50 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_51 = and(_T_29, _T_50) \n when _T_51 : \n node _error_5_T = or(error[5], nodeOut.b.bits.resp) \n node _error_5_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_5_T) \n connect error[5], _error_5_T_1 \n node _T_52 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_53 = and(_T_30, _T_52) \n when _T_53 : \n node _error_6_T = or(error[6], nodeOut.b.bits.resp) \n node _error_6_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_6_T) \n connect error[6], _error_6_T_1 \n node _T_54 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_55 = and(_T_31, _T_54) \n when _T_55 : \n node _error_7_T = or(error[7], nodeOut.b.bits.resp) \n node _error_7_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_7_T) \n connect error[7], _error_7_T_1 \n node _T_56 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_57 = and(_T_32, _T_56) \n when _T_57 : \n node _error_8_T = or(error[8], nodeOut.b.bits.resp) \n node _error_8_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_8_T) \n connect error[8], _error_8_T_1 \n node _T_58 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_59 = and(_T_33, _T_58) \n when _T_59 : \n node _error_9_T = or(error[9], nodeOut.b.bits.resp) \n node _error_9_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_9_T) \n connect error[9], _error_9_T_1 \n node _T_60 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_61 = and(_T_34, _T_60) \n when _T_61 : \n node _error_10_T = or(error[10], nodeOut.b.bits.resp) \n node _error_10_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_10_T) \n connect error[10], _error_10_T_1 \n node _T_62 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_63 = and(_T_35, _T_62) \n when _T_63 : \n node _error_11_T = or(error[11], nodeOut.b.bits.resp) \n node _error_11_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_11_T) \n connect error[11], _error_11_T_1 \n node _T_64 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_65 = and(_T_36, _T_64) \n when _T_65 : \n node _error_12_T = or(error[12], nodeOut.b.bits.resp) \n node _error_12_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_12_T) \n connect error[12], _error_12_T_1 \n node _T_66 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_67 = and(_T_37, _T_66) \n when _T_67 : \n node _error_13_T = or(error[13], nodeOut.b.bits.resp) \n node _error_13_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_13_T) \n connect error[13], _error_13_T_1 \n node _T_68 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_69 = and(_T_38, _T_68) \n when _T_69 : \n node _error_14_T = or(error[14], nodeOut.b.bits.resp) \n node _error_14_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_14_T) \n connect error[14], _error_14_T_1 \n node _T_70 = and(nodeOut.b.ready, nodeOut.b.valid) \n node _T_71 = and(_T_39, _T_70) \n when _T_71 : \n node _error_15_T = or(error[15], nodeOut.b.bits.resp) \n node _error_15_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_15_T) \n connect error[15], _error_15_T_1"},"response":{"kind":"string","value":"module AXI4Fragmenter_1(\t// @[Fragmenter.scala:37:9]\n input clock,\t// @[Fragmenter.scala:37:9]\n input reset,\t// @[Fragmenter.scala:37:9]\n output auto_in_aw_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_aw_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [28:0] auto_in_aw_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_aw_bits_len,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_aw_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_aw_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_aw_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_aw_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_aw_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_w_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_w_valid,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_in_w_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_w_bits_strb,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_w_bits_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_b_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_b_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_b_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_b_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_ar_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_ar_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [28:0] auto_in_ar_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_in_ar_bits_len,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_ar_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_in_ar_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_ar_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_in_ar_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_in_ar_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n input auto_in_r_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_r_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_in_r_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_in_r_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_in_r_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n output auto_in_r_bits_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_aw_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_aw_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_aw_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [28:0] auto_out_aw_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_aw_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_aw_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_aw_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_aw_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_aw_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_aw_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_aw_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_w_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_w_valid,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_out_w_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_out_w_bits_strb,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_w_bits_last,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_b_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_b_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_b_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_b_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_ar_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_ar_valid,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_ar_bits_id,\t// @[LazyModuleImp.scala:107:25]\n output [28:0] auto_out_ar_bits_addr,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_ar_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_out_ar_bits_burst,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_ar_bits_lock,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_ar_bits_cache,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_out_ar_bits_prot,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_out_ar_bits_qos,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_ar_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n output auto_out_r_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_r_valid,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_out_r_bits_id,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_out_r_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_out_r_bits_resp,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_r_bits_echo_real_last,\t// @[LazyModuleImp.scala:107:25]\n input auto_out_r_bits_last\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire irr_1_valid;\t// @[Decoupled.scala:401:19]\n wire [2:0] irr_1_bits_prot;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_1_bits_cache;\t// @[Decoupled.scala:401:19]\n wire irr_1_bits_lock;\t// @[Decoupled.scala:401:19]\n wire [1:0] irr_1_bits_burst;\t// @[Decoupled.scala:401:19]\n wire [2:0] irr_1_bits_size;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_1_bits_id;\t// @[Decoupled.scala:401:19]\n wire irr_valid;\t// @[Decoupled.scala:401:19]\n wire [2:0] irr_bits_prot;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_bits_cache;\t// @[Decoupled.scala:401:19]\n wire irr_bits_lock;\t// @[Decoupled.scala:401:19]\n wire [1:0] irr_bits_burst;\t// @[Decoupled.scala:401:19]\n wire [2:0] irr_bits_size;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_bits_id;\t// @[Decoupled.scala:401:19]\n wire auto_in_aw_valid_0 = auto_in_aw_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [28:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst;\t// @[Fragmenter.scala:37:9]\n wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos;\t// @[Fragmenter.scala:37:9]\n wire auto_in_w_valid_0 = auto_in_w_valid;\t// @[Fragmenter.scala:37:9]\n wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb;\t// @[Fragmenter.scala:37:9]\n wire auto_in_w_bits_last_0 = auto_in_w_bits_last;\t// @[Fragmenter.scala:37:9]\n wire auto_in_b_ready_0 = auto_in_b_ready;\t// @[Fragmenter.scala:37:9]\n wire auto_in_ar_valid_0 = auto_in_ar_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [28:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst;\t// @[Fragmenter.scala:37:9]\n wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos;\t// @[Fragmenter.scala:37:9]\n wire auto_in_r_ready_0 = auto_in_r_ready;\t// @[Fragmenter.scala:37:9]\n wire auto_out_aw_ready_0 = auto_out_aw_ready;\t// @[Fragmenter.scala:37:9]\n wire auto_out_w_ready_0 = auto_out_w_ready;\t// @[Fragmenter.scala:37:9]\n wire auto_out_b_valid_0 = auto_out_b_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp;\t// @[Fragmenter.scala:37:9]\n wire auto_out_b_bits_echo_real_last_0 = auto_out_b_bits_echo_real_last;\t// @[Fragmenter.scala:37:9]\n wire auto_out_ar_ready_0 = auto_out_ar_ready;\t// @[Fragmenter.scala:37:9]\n wire auto_out_r_valid_0 = auto_out_r_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp;\t// @[Fragmenter.scala:37:9]\n wire auto_out_r_bits_echo_real_last_0 = auto_out_r_bits_echo_real_last;\t// @[Fragmenter.scala:37:9]\n wire auto_out_r_bits_last_0 = auto_out_r_bits_last;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_out_aw_bits_len = 8'h0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_out_ar_bits_len = 8'h0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] nodeOut_aw_bits_len = 8'h0;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_ar_bits_len = 8'h0;\t// @[MixedNode.scala:542:17]\n wire [7:0] in_ar_bits_len = 8'h0;\t// @[Fragmenter.scala:66:23]\n wire [7:0] maxSupported1 = 8'h0;\t// @[Fragmenter.scala:97:46]\n wire [7:0] beats1 = 8'h0;\t// @[Fragmenter.scala:105:25]\n wire [7:0] in_aw_bits_len = 8'h0;\t// @[Fragmenter.scala:66:23]\n wire [7:0] maxSupported1_1 = 8'h0;\t// @[Fragmenter.scala:97:46]\n wire [7:0] beats1_1 = 8'h0;\t// @[Fragmenter.scala:105:25]\n wire [1:0] _error_WIRE_0 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_1 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_2 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_3 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_4 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_5 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_6 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_7 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_8 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_9 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_10 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_11 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_12 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_13 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_14 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [1:0] _error_WIRE_15 = 2'h0;\t// @[Fragmenter.scala:211:60]\n wire [8:0] _beats_T_1 = 9'h1;\t// @[package.scala:241:40]\n wire [8:0] beats = 9'h1;\t// @[package.scala:241:47]\n wire [8:0] _beats_T_5 = 9'h1;\t// @[package.scala:241:40]\n wire [8:0] w_beats = 9'h1;\t// @[package.scala:241:47]\n wire [8:0] _beats_T_3 = 9'h1FF;\t// @[package.scala:241:49]\n wire [8:0] _beats_T_7 = 9'h1FF;\t// @[package.scala:241:49]\n wire [8:0] _beats_T = 9'h0;\t// @[package.scala:241:35]\n wire [8:0] _beats_T_2 = 9'h0;\t// @[package.scala:241:53]\n wire [8:0] _beats_T_4 = 9'h0;\t// @[package.scala:241:35]\n wire [8:0] _beats_T_6 = 9'h0;\t// @[package.scala:241:53]\n wire _support1_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _support1_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire [29:0] _support1_T_2 = 30'h0;\t// @[Parameters.scala:137:46]\n wire [29:0] _support1_T_3 = 30'h0;\t// @[Parameters.scala:137:46]\n wire [29:0] _support1_T_7 = 30'h0;\t// @[Parameters.scala:137:46]\n wire [29:0] _support1_T_8 = 30'h0;\t// @[Parameters.scala:137:46]\n wire nodeIn_aw_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_aw_valid = auto_in_aw_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [28:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_w_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_w_valid = auto_in_w_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_w_bits_last = auto_in_w_bits_last_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_b_ready = auto_in_b_ready_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_b_valid;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_b_bits_id;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_b_bits_resp;\t// @[MixedNode.scala:551:17]\n wire nodeIn_ar_ready;\t// @[MixedNode.scala:551:17]\n wire nodeIn_ar_valid = auto_in_ar_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [28:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_r_ready = auto_in_r_ready_0;\t// @[Fragmenter.scala:37:9]\n wire nodeIn_r_valid;\t// @[MixedNode.scala:551:17]\n wire [3:0] nodeIn_r_bits_id;\t// @[MixedNode.scala:551:17]\n wire [63:0] nodeIn_r_bits_data;\t// @[MixedNode.scala:551:17]\n wire [1:0] nodeIn_r_bits_resp;\t// @[MixedNode.scala:551:17]\n wire nodeIn_r_bits_last;\t// @[MixedNode.scala:551:17]\n wire nodeOut_aw_ready = auto_out_aw_ready_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_aw_valid;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_aw_bits_id;\t// @[MixedNode.scala:542:17]\n wire [28:0] nodeOut_aw_bits_addr;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_aw_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_aw_bits_burst;\t// @[MixedNode.scala:542:17]\n wire nodeOut_aw_bits_lock;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_aw_bits_cache;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_aw_bits_prot;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_aw_bits_qos;\t// @[MixedNode.scala:542:17]\n wire nodeOut_aw_bits_echo_real_last;\t// @[MixedNode.scala:542:17]\n wire nodeOut_w_ready = auto_out_w_ready_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_w_valid;\t// @[MixedNode.scala:542:17]\n wire [63:0] nodeOut_w_bits_data;\t// @[MixedNode.scala:542:17]\n wire [7:0] nodeOut_w_bits_strb;\t// @[MixedNode.scala:542:17]\n wire nodeOut_w_bits_last;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_b_valid = auto_out_b_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_b_bits_echo_real_last = auto_out_b_bits_echo_real_last_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_ar_ready = auto_out_ar_ready_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_ar_valid;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_ar_bits_id;\t// @[MixedNode.scala:542:17]\n wire [28:0] nodeOut_ar_bits_addr;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_ar_bits_size;\t// @[MixedNode.scala:542:17]\n wire [1:0] nodeOut_ar_bits_burst;\t// @[MixedNode.scala:542:17]\n wire nodeOut_ar_bits_lock;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_ar_bits_cache;\t// @[MixedNode.scala:542:17]\n wire [2:0] nodeOut_ar_bits_prot;\t// @[MixedNode.scala:542:17]\n wire [3:0] nodeOut_ar_bits_qos;\t// @[MixedNode.scala:542:17]\n wire nodeOut_ar_bits_echo_real_last;\t// @[MixedNode.scala:542:17]\n wire nodeOut_r_ready;\t// @[MixedNode.scala:542:17]\n wire nodeOut_r_valid = auto_out_r_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_r_bits_echo_real_last = auto_out_r_bits_echo_real_last_0;\t// @[Fragmenter.scala:37:9]\n wire nodeOut_r_bits_last = auto_out_r_bits_last_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_aw_ready_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_w_ready_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_b_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_in_b_bits_resp_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_b_valid_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_ar_ready_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_in_r_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [63:0] auto_in_r_bits_data_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_in_r_bits_resp_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_r_bits_last_0;\t// @[Fragmenter.scala:37:9]\n wire auto_in_r_valid_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_aw_bits_echo_real_last_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_aw_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [28:0] auto_out_aw_bits_addr_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_out_aw_bits_size_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_out_aw_bits_burst_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_aw_bits_lock_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_aw_bits_cache_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_out_aw_bits_prot_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_aw_bits_qos_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_aw_valid_0;\t// @[Fragmenter.scala:37:9]\n wire [63:0] auto_out_w_bits_data_0;\t// @[Fragmenter.scala:37:9]\n wire [7:0] auto_out_w_bits_strb_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_w_bits_last_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_w_valid_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_b_ready_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_ar_bits_echo_real_last_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_ar_bits_id_0;\t// @[Fragmenter.scala:37:9]\n wire [28:0] auto_out_ar_bits_addr_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_out_ar_bits_size_0;\t// @[Fragmenter.scala:37:9]\n wire [1:0] auto_out_ar_bits_burst_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_ar_bits_lock_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_ar_bits_cache_0;\t// @[Fragmenter.scala:37:9]\n wire [2:0] auto_out_ar_bits_prot_0;\t// @[Fragmenter.scala:37:9]\n wire [3:0] auto_out_ar_bits_qos_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_ar_valid_0;\t// @[Fragmenter.scala:37:9]\n wire auto_out_r_ready_0;\t// @[Fragmenter.scala:37:9]\n assign auto_in_aw_ready_0 = nodeIn_aw_ready;\t// @[Fragmenter.scala:37:9]\n assign auto_in_w_ready_0 = nodeIn_w_ready;\t// @[Fragmenter.scala:37:9]\n wire _nodeIn_b_valid_T;\t// @[Fragmenter.scala:207:33]\n assign auto_in_b_valid_0 = nodeIn_b_valid;\t// @[Fragmenter.scala:37:9]\n assign auto_in_b_bits_id_0 = nodeIn_b_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [1:0] _nodeIn_b_bits_resp_T;\t// @[Fragmenter.scala:212:41]\n assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp;\t// @[Fragmenter.scala:37:9]\n assign auto_in_ar_ready_0 = nodeIn_ar_ready;\t// @[Fragmenter.scala:37:9]\n assign nodeOut_r_ready = nodeIn_r_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign auto_in_r_valid_0 = nodeIn_r_valid;\t// @[Fragmenter.scala:37:9]\n assign auto_in_r_bits_id_0 = nodeIn_r_bits_id;\t// @[Fragmenter.scala:37:9]\n assign auto_in_r_bits_data_0 = nodeIn_r_bits_data;\t// @[Fragmenter.scala:37:9]\n assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp;\t// @[Fragmenter.scala:37:9]\n wire _nodeIn_r_bits_last_T;\t// @[Fragmenter.scala:198:41]\n assign auto_in_r_bits_last_0 = nodeIn_r_bits_last;\t// @[Fragmenter.scala:37:9]\n wire _nodeOut_aw_valid_T_1;\t// @[Fragmenter.scala:167:35]\n assign auto_out_aw_valid_0 = nodeOut_aw_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_aw_bits_id;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [28:0] in_aw_bits_addr;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr;\t// @[Fragmenter.scala:37:9]\n wire [2:0] in_aw_bits_size;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size;\t// @[Fragmenter.scala:37:9]\n wire [1:0] in_aw_bits_burst;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst;\t// @[Fragmenter.scala:37:9]\n wire in_aw_bits_lock;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_aw_bits_cache;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache;\t// @[Fragmenter.scala:37:9]\n wire [2:0] in_aw_bits_prot;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_aw_bits_qos;\t// @[Fragmenter.scala:66:23]\n assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos;\t// @[Fragmenter.scala:37:9]\n wire aw_last;\t// @[Fragmenter.scala:118:27]\n assign auto_out_aw_bits_echo_real_last_0 = nodeOut_aw_bits_echo_real_last;\t// @[Fragmenter.scala:37:9]\n wire _nodeOut_w_valid_T_2;\t// @[Fragmenter.scala:185:33]\n assign auto_out_w_valid_0 = nodeOut_w_valid;\t// @[Fragmenter.scala:37:9]\n wire [63:0] in_w_bits_data;\t// @[Decoupled.scala:401:19]\n assign auto_out_w_bits_data_0 = nodeOut_w_bits_data;\t// @[Fragmenter.scala:37:9]\n wire [7:0] in_w_bits_strb;\t// @[Decoupled.scala:401:19]\n assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb;\t// @[Fragmenter.scala:37:9]\n wire w_last;\t// @[Fragmenter.scala:179:27]\n assign auto_out_w_bits_last_0 = nodeOut_w_bits_last;\t// @[Fragmenter.scala:37:9]\n wire _nodeOut_b_ready_T_1;\t// @[Fragmenter.scala:208:33]\n assign auto_out_b_ready_0 = nodeOut_b_ready;\t// @[Fragmenter.scala:37:9]\n assign nodeIn_b_bits_id = nodeOut_b_bits_id;\t// @[MixedNode.scala:542:17, :551:17]\n wire [3:0] shiftAmount = nodeOut_b_bits_id;\t// @[OneHot.scala:64:49]\n wire in_ar_ready = nodeOut_ar_ready;\t// @[Fragmenter.scala:66:23]\n wire in_ar_valid;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_valid_0 = nodeOut_ar_valid;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_ar_bits_id;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id;\t// @[Fragmenter.scala:37:9]\n wire [28:0] in_ar_bits_addr;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr;\t// @[Fragmenter.scala:37:9]\n wire [2:0] in_ar_bits_size;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size;\t// @[Fragmenter.scala:37:9]\n wire [1:0] in_ar_bits_burst;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst;\t// @[Fragmenter.scala:37:9]\n wire in_ar_bits_lock;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_ar_bits_cache;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache;\t// @[Fragmenter.scala:37:9]\n wire [2:0] in_ar_bits_prot;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot;\t// @[Fragmenter.scala:37:9]\n wire [3:0] in_ar_bits_qos;\t// @[Fragmenter.scala:66:23]\n assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos;\t// @[Fragmenter.scala:37:9]\n wire ar_last;\t// @[Fragmenter.scala:118:27]\n assign auto_out_ar_bits_echo_real_last_0 = nodeOut_ar_bits_echo_real_last;\t// @[Fragmenter.scala:37:9]\n assign auto_out_r_ready_0 = nodeOut_r_ready;\t// @[Fragmenter.scala:37:9]\n assign nodeIn_r_valid = nodeOut_r_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_r_bits_id = nodeOut_r_bits_id;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_r_bits_data = nodeOut_r_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign nodeIn_r_bits_resp = nodeOut_r_bits_resp;\t// @[MixedNode.scala:542:17, :551:17]\n wire _irr_ready_T;\t// @[Fragmenter.scala:119:30]\n assign in_ar_valid = irr_valid;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_id = irr_bits_id;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_size = irr_bits_size;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_burst = irr_bits_burst;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_lock = irr_bits_lock;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_cache = irr_bits_cache;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_prot = irr_bits_prot;\t// @[Decoupled.scala:401:19]\n wire [28:0] irr_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [7:0] irr_bits_len;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_bits_qos;\t// @[Decoupled.scala:401:19]\n assign in_ar_bits_qos = irr_bits_qos;\t// @[Decoupled.scala:401:19]\n wire irr_ready;\t// @[Decoupled.scala:401:19]\n assign nodeOut_ar_valid = in_ar_valid;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_id = in_ar_bits_id;\t// @[Fragmenter.scala:66:23]\n wire [28:0] _out_bits_addr_T_5;\t// @[Fragmenter.scala:130:26]\n assign nodeOut_ar_bits_addr = in_ar_bits_addr;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_size = in_ar_bits_size;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_burst = in_ar_bits_burst;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_lock = in_ar_bits_lock;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_cache = in_ar_bits_cache;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_prot = in_ar_bits_prot;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_ar_bits_qos = in_ar_bits_qos;\t// @[Fragmenter.scala:66:23]\n reg busy;\t// @[Fragmenter.scala:68:29]\n reg [28:0] r_addr;\t// @[Fragmenter.scala:69:25]\n reg [7:0] r_len;\t// @[Fragmenter.scala:70:25]\n wire [7:0] len = busy ? r_len : irr_bits_len;\t// @[Decoupled.scala:401:19]\n wire [28:0] addr = busy ? r_addr : irr_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [28:0] _support1_T = addr;\t// @[Parameters.scala:137:31]\n wire [2:0] lo = addr[2:0];\t// @[Fragmenter.scala:73:23, :75:49]\n wire [7:0] alignment = addr[10:3];\t// @[Fragmenter.scala:73:23, :77:29]\n wire [29:0] _support1_T_1 = {1'h0, _support1_T};\t// @[Parameters.scala:137:{31,41}]\n wire [6:0] _fillLow_T = len[7:1];\t// @[package.scala:262:48]\n wire [7:0] _fillLow_T_1 = {len[7], len[6:0] | _fillLow_T};\t// @[package.scala:262:{43,48}]\n wire [5:0] _fillLow_T_2 = _fillLow_T_1[7:2];\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_3 = {_fillLow_T_1[7:6], _fillLow_T_1[5:0] | _fillLow_T_2};\t// @[package.scala:262:{43,48}]\n wire [3:0] _fillLow_T_4 = _fillLow_T_3[7:4];\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_5 = {_fillLow_T_4, _fillLow_T_3[3:0] | _fillLow_T_4};\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_6 = _fillLow_T_5;\t// @[package.scala:262:43, :263:17]\n wire [6:0] fillLow = _fillLow_T_6[7:1];\t// @[package.scala:263:17]\n wire [7:0] _wipeHigh_T = ~len;\t// @[Fragmenter.scala:72:23, :94:33]\n wire [8:0] _wipeHigh_T_1 = {_wipeHigh_T, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _wipeHigh_T_2 = _wipeHigh_T_1[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_3 = _wipeHigh_T | _wipeHigh_T_2;\t// @[package.scala:253:{43,53}]\n wire [9:0] _wipeHigh_T_4 = {_wipeHigh_T_3, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _wipeHigh_T_5 = _wipeHigh_T_4[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_6 = _wipeHigh_T_3 | _wipeHigh_T_5;\t// @[package.scala:253:{43,53}]\n wire [11:0] _wipeHigh_T_7 = {_wipeHigh_T_6, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _wipeHigh_T_8 = _wipeHigh_T_7[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_9 = _wipeHigh_T_6 | _wipeHigh_T_8;\t// @[package.scala:253:{43,53}]\n wire [7:0] _wipeHigh_T_10 = _wipeHigh_T_9;\t// @[package.scala:253:43, :254:17]\n wire [7:0] wipeHigh = ~_wipeHigh_T_10;\t// @[package.scala:254:17]\n wire [7:0] remain1 = {1'h0, fillLow} | wipeHigh;\t// @[Fragmenter.scala:93:37, :94:24, :95:32]\n wire [8:0] _align1_T = {alignment, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _align1_T_1 = _align1_T[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_2 = alignment | _align1_T_1;\t// @[package.scala:253:{43,53}]\n wire [9:0] _align1_T_3 = {_align1_T_2, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _align1_T_4 = _align1_T_3[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_5 = _align1_T_2 | _align1_T_4;\t// @[package.scala:253:{43,53}]\n wire [11:0] _align1_T_6 = {_align1_T_5, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _align1_T_7 = _align1_T_6[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_8 = _align1_T_5 | _align1_T_7;\t// @[package.scala:253:{43,53}]\n wire [7:0] _align1_T_9 = _align1_T_8;\t// @[package.scala:253:43, :254:17]\n wire [7:0] align1 = ~_align1_T_9;\t// @[package.scala:254:17]\n wire [7:0] _maxSupported1_T = remain1 & align1;\t// @[Fragmenter.scala:95:32, :96:24, :97:37]\n wire fixed = irr_bits_burst == 2'h0;\t// @[Decoupled.scala:401:19]\n wire narrow = irr_bits_size != 3'h3;\t// @[Decoupled.scala:401:19]\n wire bad = fixed | narrow;\t// @[Fragmenter.scala:100:34, :101:34, :102:25]\n wire [15:0] _inc_addr_T = 16'h1 << irr_bits_size;\t// @[Decoupled.scala:401:19]\n wire [29:0] _inc_addr_T_1 = {1'h0, addr} + {14'h0, _inc_addr_T};\t// @[Fragmenter.scala:73:23, :108:{29,38}]\n wire [28:0] inc_addr = _inc_addr_T_1[28:0];\t// @[Fragmenter.scala:108:29]\n wire [15:0] _wrapMask_T = {irr_bits_len, 8'hFF};\t// @[Decoupled.scala:401:19]\n wire [22:0] _wrapMask_T_1 = {7'h0, _wrapMask_T} << irr_bits_size;\t// @[Decoupled.scala:401:19]\n wire [14:0] wrapMask = _wrapMask_T_1[22:8];\t// @[Bundles.scala:33:{21,30}]\n wire [28:0] mux_addr;\t// @[Fragmenter.scala:110:35]\n wire [28:0] _mux_addr_T = {14'h0, inc_addr[14:0] & wrapMask};\t// @[Fragmenter.scala:108:29, :112:33]\n wire [28:0] _mux_addr_T_1 = ~irr_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [28:0] _mux_addr_T_2 = {_mux_addr_T_1[28:15], _mux_addr_T_1[14:0] | wrapMask};\t// @[Fragmenter.scala:112:{49,62}]\n wire [28:0] _mux_addr_T_3 = ~_mux_addr_T_2;\t// @[Fragmenter.scala:112:{47,62}]\n wire [28:0] _mux_addr_T_4 = _mux_addr_T | _mux_addr_T_3;\t// @[Fragmenter.scala:112:{33,45,47}]\n assign mux_addr = fixed ? irr_bits_addr : irr_bits_burst == 2'h2 ? _mux_addr_T_4 : inc_addr;\t// @[Decoupled.scala:401:19]\n assign ar_last = len == 8'h0;\t// @[Fragmenter.scala:72:23, :118:27]\n assign nodeOut_ar_bits_echo_real_last = ar_last;\t// @[Fragmenter.scala:118:27]\n assign _irr_ready_T = in_ar_ready & ar_last;\t// @[Fragmenter.scala:66:23, :118:27, :119:30]\n assign irr_ready = _irr_ready_T;\t// @[Decoupled.scala:401:19]\n wire [28:0] _out_bits_addr_T = ~addr;\t// @[Fragmenter.scala:73:23, :130:28]\n wire [9:0] _out_bits_addr_T_1 = 10'h7 << irr_bits_size;\t// @[Decoupled.scala:401:19]\n wire [2:0] _out_bits_addr_T_2 = _out_bits_addr_T_1[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _out_bits_addr_T_3 = ~_out_bits_addr_T_2;\t// @[package.scala:243:{46,76}]\n wire [28:0] _out_bits_addr_T_4 = {_out_bits_addr_T[28:3], _out_bits_addr_T[2:0] | _out_bits_addr_T_3};\t// @[package.scala:243:46]\n assign _out_bits_addr_T_5 = ~_out_bits_addr_T_4;\t// @[Fragmenter.scala:130:{26,34}]\n assign in_ar_bits_addr = _out_bits_addr_T_5;\t// @[Fragmenter.scala:66:23, :130:26]\n wire _busy_T = ~ar_last;\t// @[Fragmenter.scala:118:27, :133:19]\n wire [9:0] _r_len_T = {2'h0, len} - 10'h1;\t// @[Fragmenter.scala:72:23, :135:25]\n wire [8:0] _r_len_T_1 = _r_len_T[8:0];\t// @[Fragmenter.scala:135:25]\n wire _irr_ready_T_1;\t// @[Fragmenter.scala:119:30]\n wire in_aw_valid = irr_1_valid;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_id = irr_1_bits_id;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_size = irr_1_bits_size;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_burst = irr_1_bits_burst;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_lock = irr_1_bits_lock;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_cache = irr_1_bits_cache;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_prot = irr_1_bits_prot;\t// @[Decoupled.scala:401:19]\n wire [28:0] irr_1_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [7:0] irr_1_bits_len;\t// @[Decoupled.scala:401:19]\n wire [3:0] irr_1_bits_qos;\t// @[Decoupled.scala:401:19]\n assign in_aw_bits_qos = irr_1_bits_qos;\t// @[Decoupled.scala:401:19]\n wire irr_1_ready;\t// @[Decoupled.scala:401:19]\n wire _in_aw_ready_T_1;\t// @[Fragmenter.scala:168:35]\n assign nodeOut_aw_bits_id = in_aw_bits_id;\t// @[Fragmenter.scala:66:23]\n wire [28:0] _out_bits_addr_T_11;\t// @[Fragmenter.scala:130:26]\n assign nodeOut_aw_bits_addr = in_aw_bits_addr;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_size = in_aw_bits_size;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_burst = in_aw_bits_burst;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_lock = in_aw_bits_lock;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_cache = in_aw_bits_cache;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_prot = in_aw_bits_prot;\t// @[Fragmenter.scala:66:23]\n assign nodeOut_aw_bits_qos = in_aw_bits_qos;\t// @[Fragmenter.scala:66:23]\n wire in_aw_ready;\t// @[Fragmenter.scala:66:23]\n reg busy_1;\t// @[Fragmenter.scala:68:29]\n reg [28:0] r_addr_1;\t// @[Fragmenter.scala:69:25]\n reg [7:0] r_len_1;\t// @[Fragmenter.scala:70:25]\n wire [7:0] len_1 = busy_1 ? r_len_1 : irr_1_bits_len;\t// @[Decoupled.scala:401:19]\n wire [28:0] addr_1 = busy_1 ? r_addr_1 : irr_1_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [28:0] _support1_T_5 = addr_1;\t// @[Parameters.scala:137:31]\n wire [2:0] lo_1 = addr_1[2:0];\t// @[Fragmenter.scala:73:23, :75:49]\n wire [7:0] alignment_1 = addr_1[10:3];\t// @[Fragmenter.scala:73:23, :77:29]\n wire [29:0] _support1_T_6 = {1'h0, _support1_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [6:0] _fillLow_T_7 = len_1[7:1];\t// @[package.scala:262:48]\n wire [7:0] _fillLow_T_8 = {len_1[7], len_1[6:0] | _fillLow_T_7};\t// @[package.scala:262:{43,48}]\n wire [5:0] _fillLow_T_9 = _fillLow_T_8[7:2];\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_10 = {_fillLow_T_8[7:6], _fillLow_T_8[5:0] | _fillLow_T_9};\t// @[package.scala:262:{43,48}]\n wire [3:0] _fillLow_T_11 = _fillLow_T_10[7:4];\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_12 = {_fillLow_T_11, _fillLow_T_10[3:0] | _fillLow_T_11};\t// @[package.scala:262:{43,48}]\n wire [7:0] _fillLow_T_13 = _fillLow_T_12;\t// @[package.scala:262:43, :263:17]\n wire [6:0] fillLow_1 = _fillLow_T_13[7:1];\t// @[package.scala:263:17]\n wire [7:0] _wipeHigh_T_11 = ~len_1;\t// @[Fragmenter.scala:72:23, :94:33]\n wire [8:0] _wipeHigh_T_12 = {_wipeHigh_T_11, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _wipeHigh_T_13 = _wipeHigh_T_12[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_14 = _wipeHigh_T_11 | _wipeHigh_T_13;\t// @[package.scala:253:{43,53}]\n wire [9:0] _wipeHigh_T_15 = {_wipeHigh_T_14, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _wipeHigh_T_16 = _wipeHigh_T_15[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_17 = _wipeHigh_T_14 | _wipeHigh_T_16;\t// @[package.scala:253:{43,53}]\n wire [11:0] _wipeHigh_T_18 = {_wipeHigh_T_17, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _wipeHigh_T_19 = _wipeHigh_T_18[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _wipeHigh_T_20 = _wipeHigh_T_17 | _wipeHigh_T_19;\t// @[package.scala:253:{43,53}]\n wire [7:0] _wipeHigh_T_21 = _wipeHigh_T_20;\t// @[package.scala:253:43, :254:17]\n wire [7:0] wipeHigh_1 = ~_wipeHigh_T_21;\t// @[package.scala:254:17]\n wire [7:0] remain1_1 = {1'h0, fillLow_1} | wipeHigh_1;\t// @[Fragmenter.scala:93:37, :94:24, :95:32]\n wire [8:0] _align1_T_10 = {alignment_1, 1'h0};\t// @[package.scala:253:48]\n wire [7:0] _align1_T_11 = _align1_T_10[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_12 = alignment_1 | _align1_T_11;\t// @[package.scala:253:{43,53}]\n wire [9:0] _align1_T_13 = {_align1_T_12, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _align1_T_14 = _align1_T_13[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_15 = _align1_T_12 | _align1_T_14;\t// @[package.scala:253:{43,53}]\n wire [11:0] _align1_T_16 = {_align1_T_15, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [7:0] _align1_T_17 = _align1_T_16[7:0];\t// @[package.scala:253:{48,53}]\n wire [7:0] _align1_T_18 = _align1_T_15 | _align1_T_17;\t// @[package.scala:253:{43,53}]\n wire [7:0] _align1_T_19 = _align1_T_18;\t// @[package.scala:253:43, :254:17]\n wire [7:0] align1_1 = ~_align1_T_19;\t// @[package.scala:254:17]\n wire [7:0] _maxSupported1_T_1 = remain1_1 & align1_1;\t// @[Fragmenter.scala:95:32, :96:24, :97:37]\n wire fixed_1 = irr_1_bits_burst == 2'h0;\t// @[Decoupled.scala:401:19]\n wire narrow_1 = irr_1_bits_size != 3'h3;\t// @[Decoupled.scala:401:19]\n wire bad_1 = fixed_1 | narrow_1;\t// @[Fragmenter.scala:100:34, :101:34, :102:25]\n wire [15:0] _inc_addr_T_2 = 16'h1 << irr_1_bits_size;\t// @[Decoupled.scala:401:19]\n wire [29:0] _inc_addr_T_3 = {1'h0, addr_1} + {14'h0, _inc_addr_T_2};\t// @[Fragmenter.scala:73:23, :108:{29,38}]\n wire [28:0] inc_addr_1 = _inc_addr_T_3[28:0];\t// @[Fragmenter.scala:108:29]\n wire [15:0] _wrapMask_T_2 = {irr_1_bits_len, 8'hFF};\t// @[Decoupled.scala:401:19]\n wire [22:0] _wrapMask_T_3 = {7'h0, _wrapMask_T_2} << irr_1_bits_size;\t// @[Decoupled.scala:401:19]\n wire [14:0] wrapMask_1 = _wrapMask_T_3[22:8];\t// @[Bundles.scala:33:{21,30}]\n wire [28:0] mux_addr_1;\t// @[Fragmenter.scala:110:35]\n wire [28:0] _mux_addr_T_5 = {14'h0, inc_addr_1[14:0] & wrapMask_1};\t// @[Fragmenter.scala:108:29, :112:33]\n wire [28:0] _mux_addr_T_6 = ~irr_1_bits_addr;\t// @[Decoupled.scala:401:19]\n wire [28:0] _mux_addr_T_7 = {_mux_addr_T_6[28:15], _mux_addr_T_6[14:0] | wrapMask_1};\t// @[Fragmenter.scala:112:{49,62}]\n wire [28:0] _mux_addr_T_8 = ~_mux_addr_T_7;\t// @[Fragmenter.scala:112:{47,62}]\n wire [28:0] _mux_addr_T_9 = _mux_addr_T_5 | _mux_addr_T_8;\t// @[Fragmenter.scala:112:{33,45,47}]\n assign mux_addr_1 = fixed_1 ? irr_1_bits_addr : irr_1_bits_burst == 2'h2 ? _mux_addr_T_9 : inc_addr_1;\t// @[Decoupled.scala:401:19]\n assign aw_last = len_1 == 8'h0;\t// @[Fragmenter.scala:72:23, :118:27]\n assign nodeOut_aw_bits_echo_real_last = aw_last;\t// @[Fragmenter.scala:118:27]\n assign _irr_ready_T_1 = in_aw_ready & aw_last;\t// @[Fragmenter.scala:66:23, :118:27, :119:30]\n assign irr_1_ready = _irr_ready_T_1;\t// @[Decoupled.scala:401:19]\n wire [28:0] _out_bits_addr_T_6 = ~addr_1;\t// @[Fragmenter.scala:73:23, :130:28]\n wire [9:0] _out_bits_addr_T_7 = 10'h7 << irr_1_bits_size;\t// @[Decoupled.scala:401:19]\n wire [2:0] _out_bits_addr_T_8 = _out_bits_addr_T_7[2:0];\t// @[package.scala:243:{71,76}]\n wire [2:0] _out_bits_addr_T_9 = ~_out_bits_addr_T_8;\t// @[package.scala:243:{46,76}]\n wire [28:0] _out_bits_addr_T_10 = {_out_bits_addr_T_6[28:3], _out_bits_addr_T_6[2:0] | _out_bits_addr_T_9};\t// @[package.scala:243:46]\n assign _out_bits_addr_T_11 = ~_out_bits_addr_T_10;\t// @[Fragmenter.scala:130:{26,34}]\n assign in_aw_bits_addr = _out_bits_addr_T_11;\t// @[Fragmenter.scala:66:23, :130:26]\n wire _busy_T_1 = ~aw_last;\t// @[Fragmenter.scala:118:27, :133:19]\n wire [9:0] _r_len_T_2 = {2'h0, len_1} - 10'h1;\t// @[Fragmenter.scala:72:23, :135:25]\n wire [8:0] _r_len_T_3 = _r_len_T_2[8:0];\t// @[Fragmenter.scala:135:25]\n wire _in_w_ready_T_2;\t// @[Fragmenter.scala:186:33]\n assign nodeOut_w_bits_data = in_w_bits_data;\t// @[Decoupled.scala:401:19]\n assign nodeOut_w_bits_strb = in_w_bits_strb;\t// @[Decoupled.scala:401:19]\n wire in_w_bits_last;\t// @[Decoupled.scala:401:19]\n wire in_w_ready;\t// @[Decoupled.scala:401:19]\n wire in_w_valid;\t// @[Decoupled.scala:401:19]\n reg wbeats_latched;\t// @[Fragmenter.scala:160:35]\n wire w_idle;\t// @[Fragmenter.scala:177:30]\n wire wbeats_ready;\t// @[Fragmenter.scala:161:30]\n wire _wbeats_valid_T_1;\t// @[Fragmenter.scala:169:35]\n wire wbeats_valid;\t// @[Fragmenter.scala:162:30]\n wire _GEN = wbeats_ready | wbeats_latched;\t// @[Fragmenter.scala:160:35, :161:30, :167:52]\n wire _nodeOut_aw_valid_T;\t// @[Fragmenter.scala:167:52]\n assign _nodeOut_aw_valid_T = _GEN;\t// @[Fragmenter.scala:167:52]\n wire _in_aw_ready_T;\t// @[Fragmenter.scala:168:52]\n assign _in_aw_ready_T = _GEN;\t// @[Fragmenter.scala:167:52, :168:52]\n assign _nodeOut_aw_valid_T_1 = in_aw_valid & _nodeOut_aw_valid_T;\t// @[Fragmenter.scala:66:23, :167:{35,52}]\n assign nodeOut_aw_valid = _nodeOut_aw_valid_T_1;\t// @[Fragmenter.scala:167:35]\n assign _in_aw_ready_T_1 = nodeOut_aw_ready & _in_aw_ready_T;\t// @[Fragmenter.scala:168:{35,52}]\n assign in_aw_ready = _in_aw_ready_T_1;\t// @[Fragmenter.scala:66:23, :168:35]\n wire _wbeats_valid_T = ~wbeats_latched;\t// @[Fragmenter.scala:160:35, :169:38]\n assign _wbeats_valid_T_1 = in_aw_valid & _wbeats_valid_T;\t// @[Fragmenter.scala:66:23, :169:{35,38}]\n assign wbeats_valid = _wbeats_valid_T_1;\t// @[Fragmenter.scala:162:30, :169:35]\n reg [8:0] w_counter;\t// @[Fragmenter.scala:176:30]\n assign w_idle = w_counter == 9'h0;\t// @[Fragmenter.scala:176:30, :177:30]\n assign wbeats_ready = w_idle;\t// @[Fragmenter.scala:161:30, :177:30]\n wire [8:0] _w_todo_T = {8'h0, wbeats_valid};\t// @[Fragmenter.scala:162:30, :178:35]\n wire [8:0] w_todo = w_idle ? _w_todo_T : w_counter;\t// @[Fragmenter.scala:176:30, :177:30, :178:{23,35}]\n assign w_last = w_todo == 9'h1;\t// @[Fragmenter.scala:178:23, :179:27]\n assign nodeOut_w_bits_last = w_last;\t// @[Fragmenter.scala:179:27]\n wire _w_counter_T = nodeOut_w_ready & nodeOut_w_valid;\t// @[Decoupled.scala:51:35]\n wire [9:0] _w_counter_T_1 = {1'h0, w_todo} - {9'h0, _w_counter_T};\t// @[Decoupled.scala:51:35]\n wire [8:0] _w_counter_T_2 = _w_counter_T_1[8:0];\t// @[Fragmenter.scala:180:27]\n wire _nodeOut_w_valid_T = ~wbeats_ready;\t// @[Fragmenter.scala:161:30, :185:37]\n wire _nodeOut_w_valid_T_1 = _nodeOut_w_valid_T | wbeats_valid;\t// @[Fragmenter.scala:162:30, :185:{37,51}]\n assign _nodeOut_w_valid_T_2 = in_w_valid & _nodeOut_w_valid_T_1;\t// @[Decoupled.scala:401:19]\n assign nodeOut_w_valid = _nodeOut_w_valid_T_2;\t// @[Fragmenter.scala:185:33]\n wire _in_w_ready_T = ~wbeats_ready;\t// @[Fragmenter.scala:161:30, :185:37, :186:37]\n wire _in_w_ready_T_1 = _in_w_ready_T | wbeats_valid;\t// @[Fragmenter.scala:162:30, :186:{37,51}]\n assign _in_w_ready_T_2 = nodeOut_w_ready & _in_w_ready_T_1;\t// @[Fragmenter.scala:186:{33,51}]\n assign in_w_ready = _in_w_ready_T_2;\t// @[Decoupled.scala:401:19]"}}},{"rowIdx":35485,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_24 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} \n\n\n regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) \n reg flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock \n inst q of Queue2_EgressFlit_24 \n connect q.clock, clock\n\n connect q.reset, reset\n\n connect q.io.enq.valid, io.in[0].valid \n connect q.io.enq.bits.head, io.in[0].bits.head \n connect q.io.enq.bits.tail, io.in[0].bits.tail \n node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) \n node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) \n node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) \n node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node) \n node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) \n node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) \n node _q_io_enq_bits_ingress_id_T_12 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0he), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_13 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0hf), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_14 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h10), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h11), UInt<1>(0h0)) \n node _q_io_enq_bits_ingress_id_T_16 = or(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) \n node _q_io_enq_bits_ingress_id_T_17 = or(_q_io_enq_bits_ingress_id_T_16, _q_io_enq_bits_ingress_id_T_14) \n node _q_io_enq_bits_ingress_id_T_18 = or(_q_io_enq_bits_ingress_id_T_17, _q_io_enq_bits_ingress_id_T_15) \n wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> \n connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_18 \n connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE \n connect q.io.enq.bits.payload, io.in[0].bits.payload \n connect io.out.bits, q.io.deq.bits \n connect io.out.valid, q.io.deq.valid \n connect q.io.deq.ready, io.out.ready \n node _T = eq(q.io.enq.ready, UInt<1>(0h0)) \n node _T_1 = and(q.io.enq.valid, _T) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n node _T_3 = asUInt(reset) \n node _T_4 = eq(_T_3, UInt<1>(0h0)) \n when _T_4 : \n node _T_5 = eq(_T_2, UInt<1>(0h0)) \n when _T_5 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\\n\") : printf \n assert(clock, _T_2, UInt<1>(0h1), \"\") : assert \n node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) \n connect io.credit_available[0], _io_credit_available_0_T \n node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) \n connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T \n connect io.channel_status[0].flow, flow \n node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) \n when _T_6 : \n connect channel_empty, UInt<1>(0h1) \n when io.allocs[0].alloc : \n connect channel_empty, UInt<1>(0h0) \n connect flow, io.allocs[0].flow"},"response":{"kind":"string","value":"module EgressUnit_24(\t// @[EgressUnit.scala:12:7]\n input clock,\t// @[EgressUnit.scala:12:7]\n input reset,\t// @[EgressUnit.scala:12:7]\n input io_in_0_valid,\t// @[EgressUnit.scala:18:14]\n input io_in_0_bits_head,\t// @[EgressUnit.scala:18:14]\n input io_in_0_bits_tail,\t// @[EgressUnit.scala:18:14]\n input [36:0] io_in_0_bits_payload,\t// @[EgressUnit.scala:18:14]\n input [3:0] io_in_0_bits_flow_ingress_node,\t// @[EgressUnit.scala:18:14]\n input [1:0] io_in_0_bits_flow_ingress_node_id,\t// @[EgressUnit.scala:18:14]\n output io_credit_available_0,\t// @[EgressUnit.scala:18:14]\n output io_channel_status_0_occupied,\t// @[EgressUnit.scala:18:14]\n input io_allocs_0_alloc,\t// @[EgressUnit.scala:18:14]\n input io_credit_alloc_0_alloc,\t// @[EgressUnit.scala:18:14]\n input io_credit_alloc_0_tail,\t// @[EgressUnit.scala:18:14]\n input io_out_ready,\t// @[EgressUnit.scala:18:14]\n output io_out_valid,\t// @[EgressUnit.scala:18:14]\n output io_out_bits_head,\t// @[EgressUnit.scala:18:14]\n output io_out_bits_tail,\t// @[EgressUnit.scala:18:14]\n output [36:0] io_out_bits_payload\t// @[EgressUnit.scala:18:14]\n);\n\n wire _q_io_enq_ready;\t// @[EgressUnit.scala:22:17]\n wire [1:0] _q_io_count;\t// @[EgressUnit.scala:22:17]\n reg channel_empty;\t// @[EgressUnit.scala:20:30]\n wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 2'h0;\t// @[EgressUnit.scala:32:27]"}}},{"rowIdx":35486,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_47 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_47(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35487,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_99 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}} \n\n\n wire _in_flight_WIRE : UInt<1>[5] \n connect _in_flight_WIRE[0], UInt<1>(0h0) \n connect _in_flight_WIRE[1], UInt<1>(0h0) \n connect _in_flight_WIRE[2], UInt<1>(0h0) \n connect _in_flight_WIRE[3], UInt<1>(0h0) \n connect _in_flight_WIRE[4], UInt<1>(0h0) \n regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE \n when io.in.flit[0].valid : \n when io.in.flit[0].bits.head : \n connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) \n node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Flit head/tail sequencing is broken\\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \\\"Flit head/tail sequencing is broken\\\")\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n when io.in.flit[0].bits.tail : \n connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) \n node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) \n when _T_4 : \n node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) \n node _T_6 = or(_T_5, UInt<1>(0h0)) \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n node _T_9 = eq(_T_6, UInt<1>(0h0)) \n when _T_9 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_1 \n assert(clock, _T_6, UInt<1>(0h1), \"\") : assert_1 \n node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) \n node _T_11 = or(_T_10, UInt<1>(0h0)) \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n node _T_14 = eq(_T_11, UInt<1>(0h0)) \n when _T_14 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_2 \n assert(clock, _T_11, UInt<1>(0h1), \"\") : assert_2 \n node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) \n node _T_16 = or(_T_15, UInt<1>(0h0)) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_3 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_3 \n node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) \n node _T_21 = or(_T_20, UInt<1>(0h0)) \n node _T_22 = asUInt(reset) \n node _T_23 = eq(_T_22, UInt<1>(0h0)) \n when _T_23 : \n node _T_24 = eq(_T_21, UInt<1>(0h0)) \n when _T_24 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_4 \n assert(clock, _T_21, UInt<1>(0h1), \"\") : assert_4 \n node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4)) \n node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) \n node _T_28 = and(_T_26, _T_27) \n node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_30 = and(_T_28, _T_29) \n node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_32 = and(_T_30, _T_31) \n node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8)) \n node _T_35 = and(_T_33, _T_34) \n node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_37 = and(_T_35, _T_36) \n node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_39 = and(_T_37, _T_38) \n node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0)) \n node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) \n node _T_42 = and(_T_40, _T_41) \n node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) \n node _T_44 = and(_T_42, _T_43) \n node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = or(_T_32, _T_39) \n node _T_48 = or(_T_47, _T_46) \n node _T_49 = or(_T_25, _T_48) \n node _T_50 = asUInt(reset) \n node _T_51 = eq(_T_50, UInt<1>(0h0)) \n when _T_51 : \n node _T_52 = eq(_T_49, UInt<1>(0h0)) \n when _T_52 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\\n\") : printf_5 \n assert(clock, _T_49, UInt<1>(0h1), \"\") : assert_5"},"response":{"kind":"string","value":"module NoCMonitor_99(\t// @[Monitor.scala:11:7]\n input clock,\t// @[Monitor.scala:11:7]\n input reset,\t// @[Monitor.scala:11:7]\n input io_in_flit_0_valid,\t// @[Monitor.scala:12:14]\n input io_in_flit_0_bits_head,\t// @[Monitor.scala:12:14]\n input io_in_flit_0_bits_tail,\t// @[Monitor.scala:12:14]\n input [4:0] io_in_flit_0_bits_flow_ingress_node,\t// @[Monitor.scala:12:14]\n input [1:0] io_in_flit_0_bits_flow_ingress_node_id,\t// @[Monitor.scala:12:14]\n input [4:0] io_in_flit_0_bits_flow_egress_node,\t// @[Monitor.scala:12:14]\n input [1:0] io_in_flit_0_bits_flow_egress_node_id,\t// @[Monitor.scala:12:14]\n input [2:0] io_in_flit_0_bits_virt_channel_id\t// @[Monitor.scala:12:14]\n);\n\n reg in_flight_0;\t// @[Monitor.scala:16:26]\n reg in_flight_1;\t// @[Monitor.scala:16:26]\n reg in_flight_2;\t// @[Monitor.scala:16:26]\n reg in_flight_3;\t// @[Monitor.scala:16:26]\n reg in_flight_4;\t// @[Monitor.scala:16:26]\n wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0;\t// @[Monitor.scala:21:46]\n wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1;\t// @[Monitor.scala:21:46]\n wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2;\t// @[Monitor.scala:21:46]\n wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3;\t// @[Monitor.scala:21:46]"}}},{"rowIdx":35488,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TageTable_3 : \n input clock : Clock \n input reset : Reset \n output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} \n\n\n regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) \n regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0) \n node _reset_idx_T = add(reset_idx, doing_reset) \n node _reset_idx_T_1 = tail(_reset_idx_T, 1) \n connect reset_idx, _reset_idx_T_1 \n node _T = eq(reset_idx, UInt<8>(0hff)) \n when _T : \n connect doing_reset, UInt<1>(0h0) \n node _T_1 = shr(io.f1_req_pc, 4) \n node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) \n node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) \n node idx_history = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1) \n node _idx_T = xor(_T_1, idx_history) \n node s1_hashed_idx = bits(_idx_T, 7, 0) \n node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0) \n node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8) \n node tag_history = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1) \n node _tag_T = shr(_T_1, 8) \n node _tag_T_1 = xor(_tag_T, tag_history) \n node s1_tag = bits(_tag_T_1, 7, 0) \n smem tage_u_16 : UInt<1>[8] [256] \n smem tage_table_16 : UInt<12>[4] [256] \n reg s2_tag : UInt, clock \n connect s2_tag, s1_tag \n wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] \n wire s2_req_rus : UInt<1>[8] \n node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) \n node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) \n node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) \n node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) \n node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) \n node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) \n node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) \n node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) \n node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) \n node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) \n node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) \n node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) \n node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) \n node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) \n node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) \n node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) \n wire s2_req_rhits : UInt<1>[4] \n connect s2_req_rhits[0], _s2_req_rhits_T_3 \n connect s2_req_rhits[1], _s2_req_rhits_T_7 \n connect s2_req_rhits[2], _s2_req_rhits_T_11 \n connect s2_req_rhits[3], _s2_req_rhits_T_15 \n connect io.f2_resp[0].valid, s2_req_rhits[0] \n node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0]) \n connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T \n connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr \n connect io.f2_resp[1].valid, s2_req_rhits[1] \n node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2]) \n connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T \n connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr \n connect io.f2_resp[2].valid, s2_req_rhits[2] \n node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4]) \n connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T \n connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr \n connect io.f2_resp[3].valid, s2_req_rhits[3] \n node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6]) \n connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T \n connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr \n regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0) \n when doing_reset : \n connect clear_u_ctr, UInt<1>(0h1) \n else :\n\n node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) \n node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) \n connect clear_u_ctr, _clear_u_ctr_T_1 \n node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) \n node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) \n node _clear_u_hi_T = bits(clear_u_ctr, 19, 19) \n node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1)) \n node _clear_u_lo_T = bits(clear_u_ctr, 19, 19) \n node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0)) \n node clear_u_idx = shr(clear_u_ctr, 11) \n wire _clear_u_mask_WIRE : UInt<1>[8] \n connect _clear_u_mask_WIRE[0], clear_u_lo \n connect _clear_u_mask_WIRE[1], clear_u_hi \n connect _clear_u_mask_WIRE[2], clear_u_lo \n connect _clear_u_mask_WIRE[3], clear_u_hi \n connect _clear_u_mask_WIRE[4], clear_u_lo \n connect _clear_u_mask_WIRE[5], clear_u_hi \n connect _clear_u_mask_WIRE[6], clear_u_lo \n connect _clear_u_mask_WIRE[7], clear_u_hi \n node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0]) \n node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2]) \n node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo) \n node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4]) \n node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6]) \n node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo) \n node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo) \n node _T_2 = shr(io.update_pc, 4) \n node idx_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) \n node idx_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) \n node idx_history_1 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1) \n node _idx_T_1 = xor(_T_2, idx_history_1) \n node update_idx = bits(_idx_T_1, 7, 0) \n node tag_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0) \n node tag_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8) \n node tag_history_1 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1) \n node _tag_T_2 = shr(_T_2, 8) \n node _tag_T_3 = xor(_tag_T_2, tag_history_1) \n node update_tag = bits(_tag_T_3, 7, 0) \n wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] \n node _wen_T = or(io.update_mask[0], io.update_mask[1]) \n node _wen_T_1 = or(_wen_T, io.update_mask[2]) \n node _wen_T_2 = or(_wen_T_1, io.update_mask[3]) \n node _wen_T_3 = or(doing_reset, _wen_T_2) \n wire wen : UInt<1> \n connect wen, _wen_T_3 \n wire _rdata_WIRE : UInt<8> \n invalidate _rdata_WIRE \n when io.f1_req_valid : \n connect _rdata_WIRE, s1_hashed_idx \n read mport rdata = tage_table_16[_rdata_WIRE], clock \n reg REG : UInt<1>, clock \n connect REG, wen \n node _T_3 = and(REG, UInt<1>(0h0)) \n when _T_3 : \n wire _WIRE : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] \n connect _WIRE[0].ctr, UInt<3>(0h0) \n connect _WIRE[0].tag, UInt<8>(0h0) \n connect _WIRE[0].valid, UInt<1>(0h0) \n connect _WIRE[1].ctr, UInt<3>(0h0) \n connect _WIRE[1].tag, UInt<8>(0h0) \n connect _WIRE[1].valid, UInt<1>(0h0) \n connect _WIRE[2].ctr, UInt<3>(0h0) \n connect _WIRE[2].tag, UInt<8>(0h0) \n connect _WIRE[2].valid, UInt<1>(0h0) \n connect _WIRE[3].ctr, UInt<3>(0h0) \n connect _WIRE[3].tag, UInt<8>(0h0) \n connect _WIRE[3].valid, UInt<1>(0h0) \n connect s2_req_rtage, _WIRE \n else :\n\n wire _WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} \n wire _WIRE_2 : UInt<12> \n connect _WIRE_2, rdata[0] \n node _T_4 = bits(_WIRE_2, 2, 0) \n connect _WIRE_1.ctr, _T_4 \n node _T_5 = bits(_WIRE_2, 10, 3) \n connect _WIRE_1.tag, _T_5 \n node _T_6 = bits(_WIRE_2, 11, 11) \n connect _WIRE_1.valid, _T_6 \n wire _WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} \n wire _WIRE_4 : UInt<12> \n connect _WIRE_4, rdata[1] \n node _T_7 = bits(_WIRE_4, 2, 0) \n connect _WIRE_3.ctr, _T_7 \n node _T_8 = bits(_WIRE_4, 10, 3) \n connect _WIRE_3.tag, _T_8 \n node _T_9 = bits(_WIRE_4, 11, 11) \n connect _WIRE_3.valid, _T_9 \n wire _WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} \n wire _WIRE_6 : UInt<12> \n connect _WIRE_6, rdata[2] \n node _T_10 = bits(_WIRE_6, 2, 0) \n connect _WIRE_5.ctr, _T_10 \n node _T_11 = bits(_WIRE_6, 10, 3) \n connect _WIRE_5.tag, _T_11 \n node _T_12 = bits(_WIRE_6, 11, 11) \n connect _WIRE_5.valid, _T_12 \n wire _WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>} \n wire _WIRE_8 : UInt<12> \n connect _WIRE_8, rdata[3] \n node _T_13 = bits(_WIRE_8, 2, 0) \n connect _WIRE_7.ctr, _T_13 \n node _T_14 = bits(_WIRE_8, 10, 3) \n connect _WIRE_7.tag, _T_14 \n node _T_15 = bits(_WIRE_8, 11, 11) \n connect _WIRE_7.valid, _T_15 \n wire _WIRE_9 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4] \n connect _WIRE_9[0].ctr, _WIRE_1.ctr \n connect _WIRE_9[0].tag, _WIRE_1.tag \n connect _WIRE_9[0].valid, _WIRE_1.valid \n connect _WIRE_9[1].ctr, _WIRE_3.ctr \n connect _WIRE_9[1].tag, _WIRE_3.tag \n connect _WIRE_9[1].valid, _WIRE_3.valid \n connect _WIRE_9[2].ctr, _WIRE_5.ctr \n connect _WIRE_9[2].tag, _WIRE_5.tag \n connect _WIRE_9[2].valid, _WIRE_5.valid \n connect _WIRE_9[3].ctr, _WIRE_7.ctr \n connect _WIRE_9[3].tag, _WIRE_7.tag \n connect _WIRE_9[3].valid, _WIRE_7.valid \n connect s2_req_rtage, _WIRE_9 \n when wen : \n node widx = mux(doing_reset, reset_idx, update_idx) \n wire _wdata_WIRE : UInt<12>[4] \n connect _wdata_WIRE[0], UInt<12>(0h0) \n connect _wdata_WIRE[1], UInt<12>(0h0) \n connect _wdata_WIRE[2], UInt<12>(0h0) \n connect _wdata_WIRE[3], UInt<12>(0h0) \n node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag) \n node _wdata_T = cat(wdata_hi, update_wdata[0].ctr) \n node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) \n node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr) \n node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) \n node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr) \n node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) \n node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr) \n wire _wdata_WIRE_1 : UInt<12>[4] \n connect _wdata_WIRE_1[0], _wdata_T \n connect _wdata_WIRE_1[1], _wdata_T_1 \n connect _wdata_WIRE_1[2], _wdata_T_2 \n connect _wdata_WIRE_1[3], _wdata_T_3 \n node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1) \n node _wmask_T = not(UInt<4>(0h0)) \n node wmask_lo = cat(io.update_mask[1], io.update_mask[0]) \n node wmask_hi = cat(io.update_mask[3], io.update_mask[2]) \n node _wmask_T_1 = cat(wmask_hi, wmask_lo) \n node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) \n node _T_16 = bits(wmask, 0, 0) \n node _T_17 = bits(wmask, 1, 1) \n node _T_18 = bits(wmask, 2, 2) \n node _T_19 = bits(wmask, 3, 3) \n write mport MPORT = tage_table_16[widx], clock \n when _T_16 : \n connect MPORT[0], wdata[0] \n when _T_17 : \n connect MPORT[1], wdata[1] \n when _T_18 : \n connect MPORT[2], wdata[2] \n when _T_19 : \n connect MPORT[3], wdata[3] \n wire update_u_mask : UInt<1>[8] \n connect update_u_mask[0], io.update_u_mask[0] \n connect update_u_mask[1], io.update_u_mask[0] \n connect update_u_mask[2], io.update_u_mask[1] \n connect update_u_mask[3], io.update_u_mask[1] \n connect update_u_mask[4], io.update_u_mask[2] \n connect update_u_mask[5], io.update_u_mask[2] \n connect update_u_mask[6], io.update_u_mask[3] \n connect update_u_mask[7], io.update_u_mask[3] \n node _update_u_wen_T = or(doing_reset, doing_clear_u) \n node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1]) \n node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2]) \n node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3]) \n node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4]) \n node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5]) \n node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6]) \n node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7]) \n node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7) \n wire update_u_wen : UInt<1> \n connect update_u_wen, _update_u_wen_T_8 \n wire _u_rdata_WIRE : UInt<8> \n invalidate _u_rdata_WIRE \n when io.f1_req_valid : \n connect _u_rdata_WIRE, s1_hashed_idx \n read mport u_rdata = tage_u_16[_u_rdata_WIRE], clock \n connect s2_req_rus, u_rdata \n when update_u_wen : \n node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx) \n node widx_1 = mux(doing_reset, reset_idx, _widx_T) \n node _wdata_T_4 = or(doing_reset, doing_clear_u) \n wire _wdata_WIRE_2 : UInt<1>[8] \n connect _wdata_WIRE_2[0], UInt<1>(0h0) \n connect _wdata_WIRE_2[1], UInt<1>(0h0) \n connect _wdata_WIRE_2[2], UInt<1>(0h0) \n connect _wdata_WIRE_2[3], UInt<1>(0h0) \n connect _wdata_WIRE_2[4], UInt<1>(0h0) \n connect _wdata_WIRE_2[5], UInt<1>(0h0) \n connect _wdata_WIRE_2[6], UInt<1>(0h0) \n connect _wdata_WIRE_2[7], UInt<1>(0h0) \n node wdata_lo = cat(io.update_u[1], io.update_u[0]) \n node wdata_hi_4 = cat(io.update_u[3], io.update_u[2]) \n node _wdata_T_5 = cat(wdata_hi_4, wdata_lo) \n node _wdata_T_6 = bits(_wdata_T_5, 0, 0) \n node _wdata_T_7 = bits(_wdata_T_5, 1, 1) \n node _wdata_T_8 = bits(_wdata_T_5, 2, 2) \n node _wdata_T_9 = bits(_wdata_T_5, 3, 3) \n node _wdata_T_10 = bits(_wdata_T_5, 4, 4) \n node _wdata_T_11 = bits(_wdata_T_5, 5, 5) \n node _wdata_T_12 = bits(_wdata_T_5, 6, 6) \n node _wdata_T_13 = bits(_wdata_T_5, 7, 7) \n wire _wdata_WIRE_3 : UInt<1>[8] \n connect _wdata_WIRE_3[0], _wdata_T_6 \n connect _wdata_WIRE_3[1], _wdata_T_7 \n connect _wdata_WIRE_3[2], _wdata_T_8 \n connect _wdata_WIRE_3[3], _wdata_T_9 \n connect _wdata_WIRE_3[4], _wdata_T_10 \n connect _wdata_WIRE_3[5], _wdata_T_11 \n connect _wdata_WIRE_3[6], _wdata_T_12 \n connect _wdata_WIRE_3[7], _wdata_T_13 \n node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3) \n node _wmask_T_2 = not(UInt<8>(0h0)) \n node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0]) \n node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2]) \n node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo) \n node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4]) \n node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6]) \n node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo) \n node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) \n node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3) \n node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4) \n node _T_20 = bits(wmask_1, 0, 0) \n node _T_21 = bits(wmask_1, 1, 1) \n node _T_22 = bits(wmask_1, 2, 2) \n node _T_23 = bits(wmask_1, 3, 3) \n node _T_24 = bits(wmask_1, 4, 4) \n node _T_25 = bits(wmask_1, 5, 5) \n node _T_26 = bits(wmask_1, 6, 6) \n node _T_27 = bits(wmask_1, 7, 7) \n node _T_28 = bits(widx_1, 7, 0) \n write mport MPORT_1 = tage_u_16[_T_28], clock \n when _T_20 : \n connect MPORT_1[0], wdata_1[0] \n when _T_21 : \n connect MPORT_1[1], wdata_1[1] \n when _T_22 : \n connect MPORT_1[2], wdata_1[2] \n when _T_23 : \n connect MPORT_1[3], wdata_1[3] \n when _T_24 : \n connect MPORT_1[4], wdata_1[4] \n when _T_25 : \n connect MPORT_1[5], wdata_1[5] \n when _T_26 : \n connect MPORT_1[6], wdata_1[6] \n when _T_27 : \n connect MPORT_1[7], wdata_1[7] \n reg wrbypass_tags : UInt<8>[2], clock \n reg wrbypass_idxs : UInt<8>[2], clock \n reg wrbypass : UInt<3>[4][2], clock \n regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) \n node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) \n node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) \n node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) \n node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) \n node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) \n node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) \n node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) \n node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) \n node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) \n node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) \n wire wrbypass_hits : UInt<1>[2] \n connect wrbypass_hits[0], _wrbypass_hits_T_4 \n connect wrbypass_hits[1], _wrbypass_hits_T_9 \n node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) \n node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) \n node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) \n node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) \n node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) \n node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) \n node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) \n node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) \n node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) \n node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) \n node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) \n node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) \n node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) \n node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) \n node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) \n node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) \n node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) \n node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) \n node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) \n node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) \n node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) \n node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) \n node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) \n node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) \n node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) \n connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 \n connect update_wdata[0].valid, UInt<1>(0h1) \n connect update_wdata[0].tag, update_tag \n node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) \n node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) \n node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) \n node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) \n node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) \n node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) \n node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) \n node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) \n node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) \n node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) \n node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) \n node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) \n node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) \n node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) \n node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) \n node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) \n node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) \n node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) \n node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) \n node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) \n node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) \n node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) \n node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) \n connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 \n connect update_wdata[1].valid, UInt<1>(0h1) \n connect update_wdata[1].tag, update_tag \n node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) \n node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) \n node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) \n node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) \n node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) \n node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) \n node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) \n node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) \n node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) \n node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) \n node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) \n node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) \n node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) \n node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) \n node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) \n node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) \n node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) \n node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) \n node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) \n node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) \n node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) \n node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) \n node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) \n connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 \n connect update_wdata[2].valid, UInt<1>(0h1) \n connect update_wdata[2].tag, update_tag \n node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) \n node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) \n node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) \n node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) \n node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) \n node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) \n node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) \n node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) \n node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) \n node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) \n node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) \n node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) \n node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) \n node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) \n node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) \n node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) \n node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) \n node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) \n node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) \n node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) \n node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) \n node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) \n node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) \n connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 \n connect update_wdata[3].valid, UInt<1>(0h1) \n connect update_wdata[3].tag, update_tag \n node _T_29 = or(io.update_mask[0], io.update_mask[1]) \n node _T_30 = or(_T_29, io.update_mask[2]) \n node _T_31 = or(_T_30, io.update_mask[3]) \n when _T_31 : \n node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1]) \n when _T_32 : \n wire _WIRE_10 : UInt<3>[4] \n connect _WIRE_10[0], update_wdata[0].ctr \n connect _WIRE_10[1], update_wdata[1].ctr \n connect _WIRE_10[2], update_wdata[2].ctr \n connect _WIRE_10[3], update_wdata[3].ctr \n connect wrbypass[wrbypass_hit_idx], _WIRE_10 \n else :\n\n wire _WIRE_11 : UInt<3>[4] \n connect _WIRE_11[0], update_wdata[0].ctr \n connect _WIRE_11[1], update_wdata[1].ctr \n connect _WIRE_11[2], update_wdata[2].ctr \n connect _WIRE_11[3], update_wdata[3].ctr \n connect wrbypass[wrbypass_enq_idx], _WIRE_11 \n connect wrbypass_tags[wrbypass_enq_idx], update_tag \n connect wrbypass_idxs[wrbypass_enq_idx], update_idx \n node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) \n node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) \n node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) \n connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2"},"response":{"kind":"string","value":"module TageTable_3(\t// @[tage.scala:24:7]\n input clock,\t// @[tage.scala:24:7]\n input reset,\t// @[tage.scala:24:7]\n input io_f1_req_valid,\t// @[tage.scala:31:14]\n input [39:0] io_f1_req_pc,\t// @[tage.scala:31:14]\n input [63:0] io_f1_req_ghist,\t// @[tage.scala:31:14]\n output io_f2_resp_0_valid,\t// @[tage.scala:31:14]\n output [2:0] io_f2_resp_0_bits_ctr,\t// @[tage.scala:31:14]\n output [1:0] io_f2_resp_0_bits_u,\t// @[tage.scala:31:14]\n output io_f2_resp_1_valid,\t// @[tage.scala:31:14]\n output [2:0] io_f2_resp_1_bits_ctr,\t// @[tage.scala:31:14]\n output [1:0] io_f2_resp_1_bits_u,\t// @[tage.scala:31:14]\n output io_f2_resp_2_valid,\t// @[tage.scala:31:14]\n output [2:0] io_f2_resp_2_bits_ctr,\t// @[tage.scala:31:14]\n output [1:0] io_f2_resp_2_bits_u,\t// @[tage.scala:31:14]\n output io_f2_resp_3_valid,\t// @[tage.scala:31:14]\n output [2:0] io_f2_resp_3_bits_ctr,\t// @[tage.scala:31:14]\n output [1:0] io_f2_resp_3_bits_u,\t// @[tage.scala:31:14]\n input io_update_mask_0,\t// @[tage.scala:31:14]\n input io_update_mask_1,\t// @[tage.scala:31:14]\n input io_update_mask_2,\t// @[tage.scala:31:14]\n input io_update_mask_3,\t// @[tage.scala:31:14]\n input io_update_taken_0,\t// @[tage.scala:31:14]\n input io_update_taken_1,\t// @[tage.scala:31:14]\n input io_update_taken_2,\t// @[tage.scala:31:14]\n input io_update_taken_3,\t// @[tage.scala:31:14]\n input io_update_alloc_0,\t// @[tage.scala:31:14]\n input io_update_alloc_1,\t// @[tage.scala:31:14]\n input io_update_alloc_2,\t// @[tage.scala:31:14]\n input io_update_alloc_3,\t// @[tage.scala:31:14]\n input [2:0] io_update_old_ctr_0,\t// @[tage.scala:31:14]\n input [2:0] io_update_old_ctr_1,\t// @[tage.scala:31:14]\n input [2:0] io_update_old_ctr_2,\t// @[tage.scala:31:14]\n input [2:0] io_update_old_ctr_3,\t// @[tage.scala:31:14]\n input [39:0] io_update_pc,\t// @[tage.scala:31:14]\n input [63:0] io_update_hist,\t// @[tage.scala:31:14]\n input io_update_u_mask_0,\t// @[tage.scala:31:14]\n input io_update_u_mask_1,\t// @[tage.scala:31:14]\n input io_update_u_mask_2,\t// @[tage.scala:31:14]\n input io_update_u_mask_3,\t// @[tage.scala:31:14]\n input [1:0] io_update_u_0,\t// @[tage.scala:31:14]\n input [1:0] io_update_u_1,\t// @[tage.scala:31:14]\n input [1:0] io_update_u_2,\t// @[tage.scala:31:14]\n input [1:0] io_update_u_3\t// @[tage.scala:31:14]\n);\n\n wire [47:0] _tage_table_16_R0_data;\t// @[tage.scala:90:27]\n wire [7:0] _tage_u_16_R0_data;\t// @[tage.scala:89:27]\n wire io_f1_req_valid_0 = io_f1_req_valid;\t// @[tage.scala:24:7]\n wire [39:0] io_f1_req_pc_0 = io_f1_req_pc;\t// @[tage.scala:24:7]\n wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist;\t// @[tage.scala:24:7]\n wire io_update_mask_0_0 = io_update_mask_0;\t// @[tage.scala:24:7]\n wire io_update_mask_1_0 = io_update_mask_1;\t// @[tage.scala:24:7]\n wire io_update_mask_2_0 = io_update_mask_2;\t// @[tage.scala:24:7]\n wire io_update_mask_3_0 = io_update_mask_3;\t// @[tage.scala:24:7]\n wire io_update_taken_0_0 = io_update_taken_0;\t// @[tage.scala:24:7]\n wire io_update_taken_1_0 = io_update_taken_1;\t// @[tage.scala:24:7]\n wire io_update_taken_2_0 = io_update_taken_2;\t// @[tage.scala:24:7]\n wire io_update_taken_3_0 = io_update_taken_3;\t// @[tage.scala:24:7]\n wire io_update_alloc_0_0 = io_update_alloc_0;\t// @[tage.scala:24:7]\n wire io_update_alloc_1_0 = io_update_alloc_1;\t// @[tage.scala:24:7]\n wire io_update_alloc_2_0 = io_update_alloc_2;\t// @[tage.scala:24:7]\n wire io_update_alloc_3_0 = io_update_alloc_3;\t// @[tage.scala:24:7]\n wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0;\t// @[tage.scala:24:7]\n wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1;\t// @[tage.scala:24:7]\n wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2;\t// @[tage.scala:24:7]\n wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3;\t// @[tage.scala:24:7]\n wire [39:0] io_update_pc_0 = io_update_pc;\t// @[tage.scala:24:7]\n wire [63:0] io_update_hist_0 = io_update_hist;\t// @[tage.scala:24:7]\n wire io_update_u_mask_0_0 = io_update_u_mask_0;\t// @[tage.scala:24:7]\n wire io_update_u_mask_1_0 = io_update_u_mask_1;\t// @[tage.scala:24:7]\n wire io_update_u_mask_2_0 = io_update_u_mask_2;\t// @[tage.scala:24:7]\n wire io_update_u_mask_3_0 = io_update_u_mask_3;\t// @[tage.scala:24:7]\n wire [1:0] io_update_u_0_0 = io_update_u_0;\t// @[tage.scala:24:7]\n wire [1:0] io_update_u_1_0 = io_update_u_1;\t// @[tage.scala:24:7]\n wire [1:0] io_update_u_2_0 = io_update_u_2;\t// @[tage.scala:24:7]\n wire [1:0] io_update_u_3_0 = io_update_u_3;\t// @[tage.scala:24:7]\n wire update_wdata_0_valid = 1'h1;\t// @[tage.scala:120:26]\n wire update_wdata_1_valid = 1'h1;\t// @[tage.scala:120:26]\n wire update_wdata_2_valid = 1'h1;\t// @[tage.scala:120:26]\n wire update_wdata_3_valid = 1'h1;\t// @[tage.scala:120:26]\n wire [11:0] _wdata_WIRE_0 = 12'h0;\t// @[tage.scala:130:41]\n wire [11:0] _wdata_WIRE_1 = 12'h0;\t// @[tage.scala:130:41]\n wire [11:0] _wdata_WIRE_2 = 12'h0;\t// @[tage.scala:130:41]\n wire [11:0] _wdata_WIRE_3 = 12'h0;\t// @[tage.scala:130:41]\n wire [3:0] _wmask_T = 4'hF;\t// @[tage.scala:131:34]\n wire _wdata_WIRE_2_0 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_1 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_2 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_3 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_4 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_5 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_6 = 1'h0;\t// @[tage.scala:145:58]\n wire _wdata_WIRE_2_7 = 1'h0;\t// @[tage.scala:145:58]\n wire [7:0] _wmask_T_2 = 8'hFF;\t// @[tage.scala:146:34]\n wire s2_req_rhits_0;\t// @[tage.scala:100:29]\n wire [2:0] s2_req_rtage_0_ctr;\t// @[tage.scala:98:26]\n wire [1:0] _io_f2_resp_0_bits_u_T;\t// @[tage.scala:105:34]\n wire s2_req_rhits_1;\t// @[tage.scala:100:29]\n wire [2:0] s2_req_rtage_1_ctr;\t// @[tage.scala:98:26]\n wire [1:0] _io_f2_resp_1_bits_u_T;\t// @[tage.scala:105:34]\n wire s2_req_rhits_2;\t// @[tage.scala:100:29]\n wire [2:0] s2_req_rtage_2_ctr;\t// @[tage.scala:98:26]\n wire [1:0] _io_f2_resp_2_bits_u_T;\t// @[tage.scala:105:34]\n wire s2_req_rhits_3;\t// @[tage.scala:100:29]\n wire [2:0] s2_req_rtage_3_ctr;\t// @[tage.scala:98:26]\n wire [1:0] _io_f2_resp_3_bits_u_T;\t// @[tage.scala:105:34]\n wire update_u_mask_0 = io_update_u_mask_0_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_1 = io_update_u_mask_0_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_2 = io_update_u_mask_1_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_3 = io_update_u_mask_1_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_4 = io_update_u_mask_2_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_5 = io_update_u_mask_2_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_6 = io_update_u_mask_3_0;\t// @[tage.scala:24:7, :135:30]\n wire update_u_mask_7 = io_update_u_mask_3_0;\t// @[tage.scala:24:7, :135:30]\n wire [2:0] io_f2_resp_0_bits_ctr_0;\t// @[tage.scala:24:7]\n wire [1:0] io_f2_resp_0_bits_u_0;\t// @[tage.scala:24:7]\n wire io_f2_resp_0_valid_0;\t// @[tage.scala:24:7]\n wire [2:0] io_f2_resp_1_bits_ctr_0;\t// @[tage.scala:24:7]\n wire [1:0] io_f2_resp_1_bits_u_0;\t// @[tage.scala:24:7]\n wire io_f2_resp_1_valid_0;\t// @[tage.scala:24:7]\n wire [2:0] io_f2_resp_2_bits_ctr_0;\t// @[tage.scala:24:7]\n wire [1:0] io_f2_resp_2_bits_u_0;\t// @[tage.scala:24:7]\n wire io_f2_resp_2_valid_0;\t// @[tage.scala:24:7]\n wire [2:0] io_f2_resp_3_bits_ctr_0;\t// @[tage.scala:24:7]\n wire [1:0] io_f2_resp_3_bits_u_0;\t// @[tage.scala:24:7]\n wire io_f2_resp_3_valid_0;\t// @[tage.scala:24:7]\n reg doing_reset;\t// @[tage.scala:72:28]\n reg [7:0] reset_idx;\t// @[tage.scala:73:26]\n wire [8:0] _GEN = {1'h0, reset_idx};\t// @[tage.scala:73:26, :74:26]\n wire [8:0] _reset_idx_T = _GEN + {8'h0, doing_reset};\t// @[tage.scala:72:28, :74:26]\n wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0];\t// @[tage.scala:74:26]\n wire [7:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[7:0];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[7:0];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[15:8];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[15:8];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] idx_history = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1;\t// @[tage.scala:53:11, :55:25]\n wire [27:0] _tag_T = io_f1_req_pc_0[39:12];\t// @[frontend.scala:149:35]\n wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history};\t// @[frontend.scala:149:35]\n wire [7:0] s1_hashed_idx = _idx_T[7:0];\t// @[tage.scala:60:{29,43}]\n wire [7:0] _rdata_WIRE = s1_hashed_idx;\t// @[tage.scala:60:43, :122:99]\n wire [7:0] _u_rdata_WIRE = s1_hashed_idx;\t// @[tage.scala:60:43, :140:12]\n wire [7:0] tag_history = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1;\t// @[tage.scala:53:11, :55:25]\n wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history};\t// @[tage.scala:55:25, :62:{30,50}]\n wire [7:0] s1_tag = _tag_T_1[7:0];\t// @[tage.scala:62:{50,64}]\n wire wdata_1_0;\t// @[tage.scala:145:20]\n wire wdata_1_1;\t// @[tage.scala:145:20]\n wire wdata_1_2;\t// @[tage.scala:145:20]\n wire wdata_1_3;\t// @[tage.scala:145:20]\n wire wdata_1_4;\t// @[tage.scala:145:20]\n wire wdata_1_5;\t// @[tage.scala:145:20]\n wire wdata_1_6;\t// @[tage.scala:145:20]\n wire wdata_1_7;\t// @[tage.scala:145:20]\n wire s2_req_rus_0 = _tage_u_16_R0_data[0];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_1 = _tage_u_16_R0_data[1];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_2 = _tage_u_16_R0_data[2];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_3 = _tage_u_16_R0_data[3];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_4 = _tage_u_16_R0_data[4];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_5 = _tage_u_16_R0_data[5];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_6 = _tage_u_16_R0_data[6];\t// @[tage.scala:89:27, :99:24]\n wire s2_req_rus_7 = _tage_u_16_R0_data[7];\t// @[tage.scala:89:27, :99:24]\n wire [11:0] wdata_0;\t// @[tage.scala:130:20]\n wire [11:0] wdata_1;\t// @[tage.scala:130:20]\n wire [11:0] wdata_2;\t// @[tage.scala:130:20]\n wire [11:0] wdata_3;\t// @[tage.scala:130:20]\n reg [7:0] s2_tag;\t// @[tage.scala:96:29]\n assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr;\t// @[tage.scala:24:7, :98:26]\n assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr;\t// @[tage.scala:24:7, :98:26]\n assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr;\t// @[tage.scala:24:7, :98:26]\n assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr;\t// @[tage.scala:24:7, :98:26]\n wire s2_req_rtage_0_valid;\t// @[tage.scala:98:26]\n wire [7:0] s2_req_rtage_0_tag;\t// @[tage.scala:98:26]\n wire s2_req_rtage_1_valid;\t// @[tage.scala:98:26]\n wire [7:0] s2_req_rtage_1_tag;\t// @[tage.scala:98:26]\n wire s2_req_rtage_2_valid;\t// @[tage.scala:98:26]\n wire [7:0] s2_req_rtage_2_tag;\t// @[tage.scala:98:26]\n wire s2_req_rtage_3_valid;\t// @[tage.scala:98:26]\n wire [7:0] s2_req_rtage_3_tag;\t// @[tage.scala:98:26]\n wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag;\t// @[tage.scala:96:29, :98:26, :100:69]\n wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T;\t// @[tage.scala:98:26, :100:{60,69}]\n wire _s2_req_rhits_T_2 = ~doing_reset;\t// @[tage.scala:72:28, :100:83]\n wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2;\t// @[tage.scala:100:{60,80,83}]\n assign s2_req_rhits_0 = _s2_req_rhits_T_3;\t// @[tage.scala:100:{29,80}]\n wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag;\t// @[tage.scala:96:29, :98:26, :100:69]\n wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4;\t// @[tage.scala:98:26, :100:{60,69}]\n wire _s2_req_rhits_T_6 = ~doing_reset;\t// @[tage.scala:72:28, :100:83]\n wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6;\t// @[tage.scala:100:{60,80,83}]\n assign s2_req_rhits_1 = _s2_req_rhits_T_7;\t// @[tage.scala:100:{29,80}]\n wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag;\t// @[tage.scala:96:29, :98:26, :100:69]\n wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8;\t// @[tage.scala:98:26, :100:{60,69}]\n wire _s2_req_rhits_T_10 = ~doing_reset;\t// @[tage.scala:72:28, :100:83]\n wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10;\t// @[tage.scala:100:{60,80,83}]\n assign s2_req_rhits_2 = _s2_req_rhits_T_11;\t// @[tage.scala:100:{29,80}]\n wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag;\t// @[tage.scala:96:29, :98:26, :100:69]\n wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12;\t// @[tage.scala:98:26, :100:{60,69}]\n wire _s2_req_rhits_T_14 = ~doing_reset;\t// @[tage.scala:72:28, :100:83]\n wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14;\t// @[tage.scala:100:{60,80,83}]\n assign s2_req_rhits_3 = _s2_req_rhits_T_15;\t// @[tage.scala:100:{29,80}]\n assign io_f2_resp_0_valid_0 = s2_req_rhits_0;\t// @[tage.scala:24:7, :100:29]\n assign io_f2_resp_1_valid_0 = s2_req_rhits_1;\t// @[tage.scala:24:7, :100:29]\n assign io_f2_resp_2_valid_0 = s2_req_rhits_2;\t// @[tage.scala:24:7, :100:29]\n assign io_f2_resp_3_valid_0 = s2_req_rhits_3;\t// @[tage.scala:24:7, :100:29]\n assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0};\t// @[tage.scala:99:24, :105:34]\n assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T;\t// @[tage.scala:24:7, :105:34]\n assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2};\t// @[tage.scala:99:24, :105:34]\n assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T;\t// @[tage.scala:24:7, :105:34]\n assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4};\t// @[tage.scala:99:24, :105:34]\n assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T;\t// @[tage.scala:24:7, :105:34]\n assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6};\t// @[tage.scala:99:24, :105:34]\n assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T;\t// @[tage.scala:24:7, :105:34]\n reg [19:0] clear_u_ctr;\t// @[tage.scala:109:28]\n wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1;\t// @[tage.scala:109:28, :110:85]\n wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0];\t// @[tage.scala:110:85]\n wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0];\t// @[tage.scala:109:28, :112:34]\n wire doing_clear_u = _doing_clear_u_T == 11'h0;\t// @[tage.scala:112:{34,61}]\n wire _clear_u_hi_T = clear_u_ctr[19];\t// @[tage.scala:109:28, :113:31]\n wire _clear_u_lo_T = clear_u_ctr[19];\t// @[tage.scala:109:28, :113:31, :114:31]\n wire clear_u_hi = _clear_u_hi_T;\t// @[tage.scala:113:{31,72}]\n wire _clear_u_mask_WIRE_1 = clear_u_hi;\t// @[tage.scala:113:72, :116:29]\n wire _clear_u_mask_WIRE_3 = clear_u_hi;\t// @[tage.scala:113:72, :116:29]\n wire _clear_u_mask_WIRE_5 = clear_u_hi;\t// @[tage.scala:113:72, :116:29]\n wire _clear_u_mask_WIRE_7 = clear_u_hi;\t// @[tage.scala:113:72, :116:29]\n wire clear_u_lo = ~_clear_u_lo_T;\t// @[tage.scala:114:{31,72}]\n wire _clear_u_mask_WIRE_0 = clear_u_lo;\t// @[tage.scala:114:72, :116:29]\n wire _clear_u_mask_WIRE_2 = clear_u_lo;\t// @[tage.scala:114:72, :116:29]\n wire _clear_u_mask_WIRE_4 = clear_u_lo;\t// @[tage.scala:114:72, :116:29]\n wire _clear_u_mask_WIRE_6 = clear_u_lo;\t// @[tage.scala:114:72, :116:29]\n wire [8:0] clear_u_idx = clear_u_ctr[19:11];\t// @[tage.scala:109:28, :115:33]\n wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0};\t// @[tage.scala:116:{29,109}]\n wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2};\t// @[tage.scala:116:{29,109}]\n wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo};\t// @[tage.scala:116:109]\n wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4};\t// @[tage.scala:116:{29,109}]\n wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6};\t// @[tage.scala:116:{29,109}]\n wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo};\t// @[tage.scala:116:109]\n wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo};\t// @[tage.scala:116:109]\n wire [7:0] idx_history_hist_chunks_0_1 = io_update_hist_0[7:0];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] tag_history_hist_chunks_0_1 = io_update_hist_0[7:0];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] idx_history_hist_chunks_1_1 = io_update_hist_0[15:8];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] tag_history_hist_chunks_1_1 = io_update_hist_0[15:8];\t// @[tage.scala:24:7, :53:11]\n wire [7:0] idx_history_1 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1;\t// @[tage.scala:53:11, :55:25]\n wire [27:0] _tag_T_2 = io_update_pc_0[39:12];\t// @[frontend.scala:149:35]\n wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1};\t// @[frontend.scala:149:35]\n wire [7:0] update_idx = _idx_T_1[7:0];\t// @[tage.scala:60:{29,43}]\n wire [7:0] tag_history_1 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1;\t// @[tage.scala:53:11, :55:25]\n wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1};\t// @[tage.scala:55:25, :62:{30,50}]\n wire [7:0] update_tag = _tag_T_3[7:0];\t// @[tage.scala:62:{50,64}]\n wire [7:0] update_wdata_0_tag = update_tag;\t// @[tage.scala:62:64, :120:26]\n wire [7:0] update_wdata_1_tag = update_tag;\t// @[tage.scala:62:64, :120:26]\n wire [7:0] update_wdata_2_tag = update_tag;\t// @[tage.scala:62:64, :120:26]\n wire [7:0] update_wdata_3_tag = update_tag;\t// @[tage.scala:62:64, :120:26]\n wire [2:0] _update_wdata_0_ctr_T_22;\t// @[tage.scala:168:33]\n wire [2:0] _update_wdata_1_ctr_T_22;\t// @[tage.scala:168:33]\n wire [2:0] _update_wdata_2_ctr_T_22;\t// @[tage.scala:168:33]\n wire [2:0] _update_wdata_3_ctr_T_22;\t// @[tage.scala:168:33]\n wire [2:0] update_wdata_0_ctr;\t// @[tage.scala:120:26]\n wire [2:0] update_wdata_1_ctr;\t// @[tage.scala:120:26]\n wire [2:0] update_wdata_2_ctr;\t// @[tage.scala:120:26]\n wire [2:0] update_wdata_3_ctr;\t// @[tage.scala:120:26]\n wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0;\t// @[tage.scala:24:7, :121:60]\n wire _wen_T_1 = _wen_T | io_update_mask_2_0;\t// @[tage.scala:24:7, :121:60]\n wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0;\t// @[tage.scala:24:7, :121:60]\n wire _wen_T_3 = doing_reset | _wen_T_2;\t// @[tage.scala:72:28, :121:{34,60}]\n wire wen = _wen_T_3;\t// @[tage.scala:121:{21,34}]\n reg REG;\t// @[tage.scala:123:16]\n assign s2_req_rtage_0_ctr = _tage_table_16_R0_data[2:0];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_0_tag = _tage_table_16_R0_data[10:3];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_0_valid = _tage_table_16_R0_data[11];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_1_ctr = _tage_table_16_R0_data[14:12];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_1_tag = _tage_table_16_R0_data[22:15];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_1_valid = _tage_table_16_R0_data[23];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_2_ctr = _tage_table_16_R0_data[26:24];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_2_tag = _tage_table_16_R0_data[34:27];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_2_valid = _tage_table_16_R0_data[35];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_3_ctr = _tage_table_16_R0_data[38:36];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_3_tag = _tage_table_16_R0_data[46:39];\t// @[tage.scala:90:27, :98:26, :126:49]\n assign s2_req_rtage_3_valid = _tage_table_16_R0_data[47];\t// @[tage.scala:90:27, :98:26, :126:49]\n wire [7:0] widx = doing_reset ? reset_idx : update_idx;\t// @[tage.scala:60:43, :72:28, :73:26, :129:19]\n wire [8:0] wdata_hi = {1'h1, update_wdata_0_tag};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_T = {wdata_hi, update_wdata_0_ctr};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_WIRE_1_0 = _wdata_T;\t// @[tage.scala:130:{94,114}]\n wire [8:0] wdata_hi_1 = {1'h1, update_wdata_1_tag};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_WIRE_1_1 = _wdata_T_1;\t// @[tage.scala:130:{94,114}]\n wire [8:0] wdata_hi_2 = {1'h1, update_wdata_2_tag};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_WIRE_1_2 = _wdata_T_2;\t// @[tage.scala:130:{94,114}]\n wire [8:0] wdata_hi_3 = {1'h1, update_wdata_3_tag};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr};\t// @[tage.scala:120:26, :130:114]\n wire [11:0] _wdata_WIRE_1_3 = _wdata_T_3;\t// @[tage.scala:130:{94,114}]\n assign wdata_0 = doing_reset ? 12'h0 : _wdata_WIRE_1_0;\t// @[tage.scala:72:28, :130:{20,94}]\n assign wdata_1 = doing_reset ? 12'h0 : _wdata_WIRE_1_1;\t// @[tage.scala:72:28, :130:{20,94}]\n assign wdata_2 = doing_reset ? 12'h0 : _wdata_WIRE_1_2;\t// @[tage.scala:72:28, :130:{20,94}]\n assign wdata_3 = doing_reset ? 12'h0 : _wdata_WIRE_1_3;\t// @[tage.scala:72:28, :130:{20,94}]\n wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0};\t// @[tage.scala:24:7, :131:70]\n wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0};\t// @[tage.scala:24:7, :131:70]\n wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo};\t// @[tage.scala:131:70]\n wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1;\t// @[tage.scala:72:28, :131:{20,70}]\n wire _GEN_0 = doing_reset | doing_clear_u;\t// @[tage.scala:72:28, :112:61, :136:43]\n wire _update_u_wen_T;\t// @[tage.scala:136:43]\n assign _update_u_wen_T = _GEN_0;\t// @[tage.scala:136:43]\n wire _wdata_T_4;\t// @[tage.scala:145:33]\n assign _wdata_T_4 = _GEN_0;\t// @[tage.scala:136:43, :145:33]\n wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7;\t// @[tage.scala:135:30, :136:85]\n wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7;\t// @[tage.scala:136:{43,60,85}]\n wire update_u_wen = _update_u_wen_T_8;\t// @[tage.scala:136:{30,60}]\n wire [8:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx};\t// @[tage.scala:60:43, :112:61, :115:33, :144:47]\n wire [8:0] widx_1 = doing_reset ? _GEN : _widx_T;\t// @[tage.scala:72:28, :74:26, :144:{19,47}]\n wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0};\t// @[tage.scala:24:7, :145:110]\n wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0};\t// @[tage.scala:24:7, :145:110]\n wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo};\t// @[tage.scala:145:110]\n wire _wdata_T_6 = _wdata_T_5[0];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_0 = _wdata_T_6;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_7 = _wdata_T_5[1];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_1 = _wdata_T_7;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_8 = _wdata_T_5[2];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_2 = _wdata_T_8;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_9 = _wdata_T_5[3];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_3 = _wdata_T_9;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_10 = _wdata_T_5[4];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_4 = _wdata_T_10;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_11 = _wdata_T_5[5];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_5 = _wdata_T_11;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_12 = _wdata_T_5[6];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_6 = _wdata_T_12;\t// @[tage.scala:145:{97,117}]\n wire _wdata_T_13 = _wdata_T_5[7];\t// @[tage.scala:145:{110,117}]\n wire _wdata_WIRE_3_7 = _wdata_T_13;\t// @[tage.scala:145:{97,117}]\n assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6;\t// @[tage.scala:145:{20,33,97}]\n assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7;\t// @[tage.scala:145:{20,33,97}]\n wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0};\t// @[tage.scala:135:30, :146:106]\n wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2};\t// @[tage.scala:135:30, :146:106]\n wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo};\t// @[tage.scala:146:106]\n wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4};\t// @[tage.scala:135:30, :146:106]\n wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6};\t// @[tage.scala:135:30, :146:106]\n wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo};\t// @[tage.scala:146:106]\n wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1};\t// @[tage.scala:146:106]\n wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3;\t// @[tage.scala:112:61, :116:109, :146:{62,106}]\n wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4;\t// @[tage.scala:72:28, :146:{20,62}]\n reg [7:0] wrbypass_tags_0;\t// @[tage.scala:154:29]\n reg [7:0] wrbypass_tags_1;\t// @[tage.scala:154:29]\n reg [7:0] wrbypass_idxs_0;\t// @[tage.scala:155:29]\n reg [7:0] wrbypass_idxs_1;\t// @[tage.scala:155:29]\n reg [2:0] wrbypass_0_0;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_0_1;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_0_2;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_0_3;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_1_0;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_1_1;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_1_2;\t// @[tage.scala:156:29]\n reg [2:0] wrbypass_1_3;\t// @[tage.scala:156:29]\n reg wrbypass_enq_idx;\t// @[tage.scala:157:33]\n wire _wrbypass_hits_T = ~doing_reset;\t// @[tage.scala:72:28, :100:83, :160:5]\n wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag;\t// @[tage.scala:62:64, :154:29, :161:22]\n wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1;\t// @[tage.scala:160:{5,18}, :161:22]\n wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx;\t// @[tage.scala:60:43, :155:29, :162:22]\n wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3;\t// @[tage.scala:160:18, :161:37, :162:22]\n wire wrbypass_hits_0 = _wrbypass_hits_T_4;\t// @[tage.scala:159:33, :161:37]\n wire _wrbypass_hits_T_5 = ~doing_reset;\t// @[tage.scala:72:28, :100:83, :160:5]\n wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag;\t// @[tage.scala:62:64, :154:29, :161:22]\n wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6;\t// @[tage.scala:160:{5,18}, :161:22]\n wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx;\t// @[tage.scala:60:43, :155:29, :162:22]\n wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8;\t// @[tage.scala:160:18, :161:37, :162:22]\n wire wrbypass_hits_1 = _wrbypass_hits_T_9;\t// @[tage.scala:159:33, :161:37]\n wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1;\t// @[tage.scala:159:33, :164:48]\n wire wrbypass_hit_idx = ~wrbypass_hits_0;\t// @[Mux.scala:50:70]\n wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3;\t// @[tage.scala:24:7, :169:10]\n wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0;\t// @[tage.scala:24:7, :67:9]\n wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0;\t// @[Mux.scala:50:70]\n wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1;\t// @[Mux.scala:50:70]\n wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2;\t// @[Mux.scala:50:70]\n wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3;\t// @[Mux.scala:50:70]\n wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0;\t// @[tage.scala:67:25]\n wire [3:0] _GEN_5 = {1'h0, _GEN_1};\t// @[tage.scala:67:{25,43}]\n wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_0_ctr_T_6 = &_GEN_1;\t// @[tage.scala:67:25, :68:25]\n wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0;\t// @[tage.scala:24:7, :67:25]\n wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0};\t// @[tage.scala:24:7, :67:43]\n wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0;\t// @[tage.scala:24:7, :68:25]\n wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20;\t// @[tage.scala:67:8, :164:48, :172:10]\n assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21;\t// @[tage.scala:24:7, :168:33, :169:10, :172:10]\n assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22;\t// @[tage.scala:120:26, :168:33]\n wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3;\t// @[tage.scala:24:7, :169:10]\n wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0;\t// @[tage.scala:67:25]\n wire [3:0] _GEN_7 = {1'h0, _GEN_2};\t// @[tage.scala:67:{25,43}]\n wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_1_ctr_T_6 = &_GEN_2;\t// @[tage.scala:67:25, :68:25]\n wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0;\t// @[tage.scala:24:7, :67:25]\n wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0};\t// @[tage.scala:24:7, :67:43]\n wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0;\t// @[tage.scala:24:7, :68:25]\n wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20;\t// @[tage.scala:67:8, :164:48, :172:10]\n assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21;\t// @[tage.scala:24:7, :168:33, :169:10, :172:10]\n assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22;\t// @[tage.scala:120:26, :168:33]\n wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3;\t// @[tage.scala:24:7, :169:10]\n wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0;\t// @[tage.scala:67:25]\n wire [3:0] _GEN_9 = {1'h0, _GEN_3};\t// @[tage.scala:67:{25,43}]\n wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_2_ctr_T_6 = &_GEN_3;\t// @[tage.scala:67:25, :68:25]\n wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0;\t// @[tage.scala:24:7, :67:25]\n wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0};\t// @[tage.scala:24:7, :67:43]\n wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0;\t// @[tage.scala:24:7, :68:25]\n wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20;\t// @[tage.scala:67:8, :164:48, :172:10]\n assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21;\t// @[tage.scala:24:7, :168:33, :169:10, :172:10]\n assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22;\t// @[tage.scala:120:26, :168:33]\n wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3;\t// @[tage.scala:24:7, :169:10]\n wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0;\t// @[tage.scala:67:25]\n wire [3:0] _GEN_11 = {1'h0, _GEN_4};\t// @[tage.scala:67:{25,43}]\n wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_3_ctr_T_6 = &_GEN_4;\t// @[tage.scala:67:25, :68:25]\n wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0;\t// @[tage.scala:24:7, :67:9]\n wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0;\t// @[tage.scala:24:7, :67:25]\n wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0};\t// @[tage.scala:24:7, :67:43]\n wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1;\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0];\t// @[tage.scala:67:43]\n wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14;\t// @[tage.scala:67:{20,25,43}]\n wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0;\t// @[tage.scala:24:7, :68:25]\n wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1;\t// @[tage.scala:67:43, :68:43]\n wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0];\t// @[tage.scala:68:43]\n wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18;\t// @[tage.scala:68:{20,25,43}]\n wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19;\t// @[tage.scala:67:{8,9,20}, :68:20]\n wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20;\t// @[tage.scala:67:8, :164:48, :172:10]\n assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21;\t// @[tage.scala:24:7, :168:33, :169:10, :172:10]\n assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22;\t// @[tage.scala:120:26, :168:33]\n wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1;\t// @[util.scala:211:14]\n wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0];\t// @[util.scala:211:14]\n wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1;\t// @[util.scala:211:{14,20}]\n wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0;\t// @[tage.scala:24:7, :121:60, :180:32]\n wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx;\t// @[Mux.scala:50:70]\n wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx;\t// @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]\n wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx;\t// @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]\n always @(posedge clock) begin\t// @[tage.scala:24:7]\n if (reset) begin\t// @[tage.scala:24:7]\n doing_reset <= 1'h1;\t// @[tage.scala:72:28]\n reset_idx <= 8'h0;\t// @[tage.scala:73:26]\n clear_u_ctr <= 20'h0;\t// @[tage.scala:109:28]\n wrbypass_enq_idx <= 1'h0;\t// @[tage.scala:157:33]\n end\n else begin\t// @[tage.scala:24:7]\n doing_reset <= reset_idx != 8'hFF & doing_reset;\t// @[tage.scala:72:28, :73:26, :75:{19,36,50}]\n reset_idx <= _reset_idx_T_1;\t// @[tage.scala:73:26, :74:26]\n clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1;\t// @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]\n if (~_T_31 | wrbypass_hit) begin\t// @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39]\n end\n else\t// @[tage.scala:157:33, :180:38, :181:39]\n wrbypass_enq_idx <= _wrbypass_enq_idx_T_2;\t// @[util.scala:211:20]\n end\n s2_tag <= s1_tag;\t// @[tage.scala:62:64, :96:29]\n REG <= wen;\t// @[tage.scala:121:21, :123:16]\n if (_GEN_14) begin\t// @[tage.scala:154:29, :180:38, :181:39, :185:39]\n end\n else\t// @[tage.scala:154:29, :180:38, :181:39, :185:39]\n wrbypass_tags_0 <= update_tag;\t// @[tage.scala:62:64, :154:29]\n if (_GEN_15) begin\t// @[tage.scala:154:29, :180:38, :181:39, :185:39]\n end\n else\t// @[tage.scala:154:29, :180:38, :181:39, :185:39]\n wrbypass_tags_1 <= update_tag;\t// @[tage.scala:62:64, :154:29]\n if (_GEN_14) begin\t// @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]\n end\n else\t// @[tage.scala:155:29, :180:38, :181:39, :186:39]\n wrbypass_idxs_0 <= update_idx;\t// @[tage.scala:60:43, :155:29]\n if (_GEN_15) begin\t// @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]\n end\n else\t// @[tage.scala:155:29, :180:38, :181:39, :186:39]\n wrbypass_idxs_1 <= update_idx;\t// @[tage.scala:60:43, :155:29]\n if (~_T_31 | _GEN_13) begin\t// @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]\n end\n else begin\t// @[tage.scala:156:29, :180:38, :181:39]\n wrbypass_0_0 <= update_wdata_0_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_0_1 <= update_wdata_1_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_0_2 <= update_wdata_2_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_0_3 <= update_wdata_3_ctr;\t// @[tage.scala:120:26, :156:29]\n end\n if (_T_31 & _GEN_13) begin\t// @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]\n wrbypass_1_0 <= update_wdata_0_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_1_1 <= update_wdata_1_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_1_2 <= update_wdata_2_ctr;\t// @[tage.scala:120:26, :156:29]\n wrbypass_1_3 <= update_wdata_3_ctr;\t// @[tage.scala:120:26, :156:29]\n end\n always @(posedge)\n tage_u_16 tage_u_16 (\t// @[tage.scala:89:27]\n .R0_addr (_u_rdata_WIRE),\t// @[tage.scala:140:12]\n .R0_en (io_f1_req_valid_0),\t// @[tage.scala:24:7]\n .R0_clk (clock),\n .R0_data (_tage_u_16_R0_data),\n .W0_addr (widx_1[7:0]),\t// @[tage.scala:144:19, :147:13]\n .W0_en (update_u_wen),\t// @[tage.scala:136:30]\n .W0_clk (clock),\n .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}),\t// @[tage.scala:89:27, :145:20]\n .W0_mask (wmask_1)\t// @[tage.scala:146:20]\n );\t// @[tage.scala:89:27]\n tage_table_16 tage_table_16 (\t// @[tage.scala:90:27]\n .R0_addr (_rdata_WIRE),\t// @[tage.scala:122:99]\n .R0_en (io_f1_req_valid_0),\t// @[tage.scala:24:7]\n .R0_clk (clock),\n .R0_data (_tage_table_16_R0_data),\n .W0_addr (widx),\t// @[tage.scala:129:19]\n .W0_en (wen),\t// @[tage.scala:121:21]\n .W0_clk (clock),\n .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}),\t// @[tage.scala:90:27, :130:20]\n .W0_mask (wmask)\t// @[tage.scala:131:20]\n );\t// @[tage.scala:90:27]\n assign io_f2_resp_0_valid = io_f2_resp_0_valid_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_1_valid = io_f2_resp_1_valid_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_2_valid = io_f2_resp_2_valid_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_3_valid = io_f2_resp_3_valid_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0;\t// @[tage.scala:24:7]\n assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0;\t// @[tage.scala:24:7]\nendmodule"}}},{"rowIdx":35489,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLFIFOFixer_3 : \n input clock : Clock \n input reset : Reset \n output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} \n invalidate anonIn.d.bits.corrupt \n invalidate anonIn.d.bits.data \n invalidate anonIn.d.bits.denied \n invalidate anonIn.d.bits.sink \n invalidate anonIn.d.bits.source \n invalidate anonIn.d.bits.size \n invalidate anonIn.d.bits.param \n invalidate anonIn.d.bits.opcode \n invalidate anonIn.d.valid \n invalidate anonIn.d.ready \n invalidate anonIn.a.bits.corrupt \n invalidate anonIn.a.bits.data \n invalidate anonIn.a.bits.mask \n invalidate anonIn.a.bits.address \n invalidate anonIn.a.bits.source \n invalidate anonIn.a.bits.size \n invalidate anonIn.a.bits.param \n invalidate anonIn.a.bits.opcode \n invalidate anonIn.a.valid \n invalidate anonIn.a.ready \n inst monitor of TLMonitor_21 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, anonIn.d.bits.data \n connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink \n connect monitor.io.in.d.bits.source, anonIn.d.bits.source \n connect monitor.io.in.d.bits.size, anonIn.d.bits.size \n connect monitor.io.in.d.bits.param, anonIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode \n connect monitor.io.in.d.valid, anonIn.d.valid \n connect monitor.io.in.d.ready, anonIn.d.ready \n connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, anonIn.a.bits.data \n connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask \n connect monitor.io.in.a.bits.address, anonIn.a.bits.address \n connect monitor.io.in.a.bits.source, anonIn.a.bits.source \n connect monitor.io.in.a.bits.size, anonIn.a.bits.size \n connect monitor.io.in.a.bits.param, anonIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode \n connect monitor.io.in.a.valid, anonIn.a.valid \n connect monitor.io.in.a.ready, anonIn.a.ready \n wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} \n invalidate anonOut.d.bits.corrupt \n invalidate anonOut.d.bits.data \n invalidate anonOut.d.bits.denied \n invalidate anonOut.d.bits.sink \n invalidate anonOut.d.bits.source \n invalidate anonOut.d.bits.size \n invalidate anonOut.d.bits.param \n invalidate anonOut.d.bits.opcode \n invalidate anonOut.d.valid \n invalidate anonOut.d.ready \n invalidate anonOut.a.bits.corrupt \n invalidate anonOut.a.bits.data \n invalidate anonOut.a.bits.mask \n invalidate anonOut.a.bits.address \n invalidate anonOut.a.bits.source \n invalidate anonOut.a.bits.size \n invalidate anonOut.a.bits.param \n invalidate anonOut.a.bits.opcode \n invalidate anonOut.a.valid \n invalidate anonOut.a.ready \n connect auto.anon_out, anonOut \n connect anonIn, auto.anon_in \n node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) \n node _a_notFIFO_T_1 = cvt(_a_notFIFO_T) \n node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0))) \n node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2) \n node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0))) \n node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0)) \n node _a_id_T_1 = cvt(_a_id_T) \n node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<33>(0h9a113000))) \n node _a_id_T_3 = asSInt(_a_id_T_2) \n node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0))) \n node _a_id_T_5 = xor(anonIn.a.bits.address, UInt<13>(0h1000)) \n node _a_id_T_6 = cvt(_a_id_T_5) \n node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<33>(0h9a113000))) \n node _a_id_T_8 = asSInt(_a_id_T_7) \n node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0))) \n node _a_id_T_10 = xor(anonIn.a.bits.address, UInt<29>(0h10000000)) \n node _a_id_T_11 = cvt(_a_id_T_10) \n node _a_id_T_12 = and(_a_id_T_11, asSInt(UInt<33>(0h9a113000))) \n node _a_id_T_13 = asSInt(_a_id_T_12) \n node _a_id_T_14 = eq(_a_id_T_13, asSInt(UInt<1>(0h0))) \n node _a_id_T_15 = or(_a_id_T_9, _a_id_T_14) \n node _a_id_T_16 = xor(anonIn.a.bits.address, UInt<14>(0h3000)) \n node _a_id_T_17 = cvt(_a_id_T_16) \n node _a_id_T_18 = and(_a_id_T_17, asSInt(UInt<33>(0h9a113000))) \n node _a_id_T_19 = asSInt(_a_id_T_18) \n node _a_id_T_20 = eq(_a_id_T_19, asSInt(UInt<1>(0h0))) \n node _a_id_T_21 = xor(anonIn.a.bits.address, UInt<17>(0h10000)) \n node _a_id_T_22 = cvt(_a_id_T_21) \n node _a_id_T_23 = and(_a_id_T_22, asSInt(UInt<33>(0h9a110000))) \n node _a_id_T_24 = asSInt(_a_id_T_23) \n node _a_id_T_25 = eq(_a_id_T_24, asSInt(UInt<1>(0h0))) \n node _a_id_T_26 = xor(anonIn.a.bits.address, UInt<21>(0h100000)) \n node _a_id_T_27 = cvt(_a_id_T_26) \n node _a_id_T_28 = and(_a_id_T_27, asSInt(UInt<33>(0h9a103000))) \n node _a_id_T_29 = asSInt(_a_id_T_28) \n node _a_id_T_30 = eq(_a_id_T_29, asSInt(UInt<1>(0h0))) \n node _a_id_T_31 = xor(anonIn.a.bits.address, UInt<26>(0h2000000)) \n node _a_id_T_32 = cvt(_a_id_T_31) \n node _a_id_T_33 = and(_a_id_T_32, asSInt(UInt<33>(0h9a110000))) \n node _a_id_T_34 = asSInt(_a_id_T_33) \n node _a_id_T_35 = eq(_a_id_T_34, asSInt(UInt<1>(0h0))) \n node _a_id_T_36 = xor(anonIn.a.bits.address, UInt<28>(0h8000000)) \n node _a_id_T_37 = cvt(_a_id_T_36) \n node _a_id_T_38 = and(_a_id_T_37, asSInt(UInt<33>(0h98000000))) \n node _a_id_T_39 = asSInt(_a_id_T_38) \n node _a_id_T_40 = eq(_a_id_T_39, asSInt(UInt<1>(0h0))) \n node _a_id_T_41 = xor(anonIn.a.bits.address, UInt<32>(0h80000000)) \n node _a_id_T_42 = cvt(_a_id_T_41) \n node _a_id_T_43 = and(_a_id_T_42, asSInt(UInt<33>(0h9a110000))) \n node _a_id_T_44 = asSInt(_a_id_T_43) \n node _a_id_T_45 = eq(_a_id_T_44, asSInt(UInt<1>(0h0))) \n node _a_id_T_46 = mux(_a_id_T_4, UInt<4>(0h8), UInt<1>(0h0)) \n node _a_id_T_47 = mux(_a_id_T_15, UInt<2>(0h3), UInt<1>(0h0)) \n node _a_id_T_48 = mux(_a_id_T_20, UInt<1>(0h1), UInt<1>(0h0)) \n node _a_id_T_49 = mux(_a_id_T_25, UInt<3>(0h4), UInt<1>(0h0)) \n node _a_id_T_50 = mux(_a_id_T_30, UInt<3>(0h6), UInt<1>(0h0)) \n node _a_id_T_51 = mux(_a_id_T_35, UInt<3>(0h5), UInt<1>(0h0)) \n node _a_id_T_52 = mux(_a_id_T_40, UInt<3>(0h7), UInt<1>(0h0)) \n node _a_id_T_53 = mux(_a_id_T_45, UInt<2>(0h2), UInt<1>(0h0)) \n node _a_id_T_54 = or(_a_id_T_46, _a_id_T_47) \n node _a_id_T_55 = or(_a_id_T_54, _a_id_T_48) \n node _a_id_T_56 = or(_a_id_T_55, _a_id_T_49) \n node _a_id_T_57 = or(_a_id_T_56, _a_id_T_50) \n node _a_id_T_58 = or(_a_id_T_57, _a_id_T_51) \n node _a_id_T_59 = or(_a_id_T_58, _a_id_T_52) \n node _a_id_T_60 = or(_a_id_T_59, _a_id_T_53) \n wire a_id : UInt<4> \n connect a_id, _a_id_T_60 \n node a_noDomain = eq(a_id, UInt<1>(0h0)) \n node _a_first_T = and(anonIn.a.ready, anonIn.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n node _d_first_T = and(anonOut.d.ready, anonOut.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6)) \n node d_first = and(d_first_first, _d_first_T_1) \n wire _flight_WIRE : UInt<1>[129] \n connect _flight_WIRE[0], UInt<1>(0h0) \n connect _flight_WIRE[1], UInt<1>(0h0) \n connect _flight_WIRE[2], UInt<1>(0h0) \n connect _flight_WIRE[3], UInt<1>(0h0) \n connect _flight_WIRE[4], UInt<1>(0h0) \n connect _flight_WIRE[5], UInt<1>(0h0) \n connect _flight_WIRE[6], UInt<1>(0h0) \n connect _flight_WIRE[7], UInt<1>(0h0) \n connect _flight_WIRE[8], UInt<1>(0h0) \n connect _flight_WIRE[9], UInt<1>(0h0) \n connect _flight_WIRE[10], UInt<1>(0h0) \n connect _flight_WIRE[11], UInt<1>(0h0) \n connect _flight_WIRE[12], UInt<1>(0h0) \n connect _flight_WIRE[13], UInt<1>(0h0) \n connect _flight_WIRE[14], UInt<1>(0h0) \n connect _flight_WIRE[15], UInt<1>(0h0) \n connect _flight_WIRE[16], UInt<1>(0h0) \n connect _flight_WIRE[17], UInt<1>(0h0) \n connect _flight_WIRE[18], UInt<1>(0h0) \n connect _flight_WIRE[19], UInt<1>(0h0) \n connect _flight_WIRE[20], UInt<1>(0h0) \n connect _flight_WIRE[21], UInt<1>(0h0) \n connect _flight_WIRE[22], UInt<1>(0h0) \n connect _flight_WIRE[23], UInt<1>(0h0) \n connect _flight_WIRE[24], UInt<1>(0h0) \n connect _flight_WIRE[25], UInt<1>(0h0) \n connect _flight_WIRE[26], UInt<1>(0h0) \n connect _flight_WIRE[27], UInt<1>(0h0) \n connect _flight_WIRE[28], UInt<1>(0h0) \n connect _flight_WIRE[29], UInt<1>(0h0) \n connect _flight_WIRE[30], UInt<1>(0h0) \n connect _flight_WIRE[31], UInt<1>(0h0) \n connect _flight_WIRE[32], UInt<1>(0h0) \n connect _flight_WIRE[33], UInt<1>(0h0) \n connect _flight_WIRE[34], UInt<1>(0h0) \n connect _flight_WIRE[35], UInt<1>(0h0) \n connect _flight_WIRE[36], UInt<1>(0h0) \n connect _flight_WIRE[37], UInt<1>(0h0) \n connect _flight_WIRE[38], UInt<1>(0h0) \n connect _flight_WIRE[39], UInt<1>(0h0) \n connect _flight_WIRE[40], UInt<1>(0h0) \n connect _flight_WIRE[41], UInt<1>(0h0) \n connect _flight_WIRE[42], UInt<1>(0h0) \n connect _flight_WIRE[43], UInt<1>(0h0) \n connect _flight_WIRE[44], UInt<1>(0h0) \n connect _flight_WIRE[45], UInt<1>(0h0) \n connect _flight_WIRE[46], UInt<1>(0h0) \n connect _flight_WIRE[47], UInt<1>(0h0) \n connect _flight_WIRE[48], UInt<1>(0h0) \n connect _flight_WIRE[49], UInt<1>(0h0) \n connect _flight_WIRE[50], UInt<1>(0h0) \n connect _flight_WIRE[51], UInt<1>(0h0) \n connect _flight_WIRE[52], UInt<1>(0h0) \n connect _flight_WIRE[53], UInt<1>(0h0) \n connect _flight_WIRE[54], UInt<1>(0h0) \n connect _flight_WIRE[55], UInt<1>(0h0) \n connect _flight_WIRE[56], UInt<1>(0h0) \n connect _flight_WIRE[57], UInt<1>(0h0) \n connect _flight_WIRE[58], UInt<1>(0h0) \n connect _flight_WIRE[59], UInt<1>(0h0) \n connect _flight_WIRE[60], UInt<1>(0h0) \n connect _flight_WIRE[61], UInt<1>(0h0) \n connect _flight_WIRE[62], UInt<1>(0h0) \n connect _flight_WIRE[63], UInt<1>(0h0) \n connect _flight_WIRE[64], UInt<1>(0h0) \n connect _flight_WIRE[65], UInt<1>(0h0) \n connect _flight_WIRE[66], UInt<1>(0h0) \n connect _flight_WIRE[67], UInt<1>(0h0) \n connect _flight_WIRE[68], UInt<1>(0h0) \n connect _flight_WIRE[69], UInt<1>(0h0) \n connect _flight_WIRE[70], UInt<1>(0h0) \n connect _flight_WIRE[71], UInt<1>(0h0) \n connect _flight_WIRE[72], UInt<1>(0h0) \n connect _flight_WIRE[73], UInt<1>(0h0) \n connect _flight_WIRE[74], UInt<1>(0h0) \n connect _flight_WIRE[75], UInt<1>(0h0) \n connect _flight_WIRE[76], UInt<1>(0h0) \n connect _flight_WIRE[77], UInt<1>(0h0) \n connect _flight_WIRE[78], UInt<1>(0h0) \n connect _flight_WIRE[79], UInt<1>(0h0) \n connect _flight_WIRE[80], UInt<1>(0h0) \n connect _flight_WIRE[81], UInt<1>(0h0) \n connect _flight_WIRE[82], UInt<1>(0h0) \n connect _flight_WIRE[83], UInt<1>(0h0) \n connect _flight_WIRE[84], UInt<1>(0h0) \n connect _flight_WIRE[85], UInt<1>(0h0) \n connect _flight_WIRE[86], UInt<1>(0h0) \n connect _flight_WIRE[87], UInt<1>(0h0) \n connect _flight_WIRE[88], UInt<1>(0h0) \n connect _flight_WIRE[89], UInt<1>(0h0) \n connect _flight_WIRE[90], UInt<1>(0h0) \n connect _flight_WIRE[91], UInt<1>(0h0) \n connect _flight_WIRE[92], UInt<1>(0h0) \n connect _flight_WIRE[93], UInt<1>(0h0) \n connect _flight_WIRE[94], UInt<1>(0h0) \n connect _flight_WIRE[95], UInt<1>(0h0) \n connect _flight_WIRE[96], UInt<1>(0h0) \n connect _flight_WIRE[97], UInt<1>(0h0) \n connect _flight_WIRE[98], UInt<1>(0h0) \n connect _flight_WIRE[99], UInt<1>(0h0) \n connect _flight_WIRE[100], UInt<1>(0h0) \n connect _flight_WIRE[101], UInt<1>(0h0) \n connect _flight_WIRE[102], UInt<1>(0h0) \n connect _flight_WIRE[103], UInt<1>(0h0) \n connect _flight_WIRE[104], UInt<1>(0h0) \n connect _flight_WIRE[105], UInt<1>(0h0) \n connect _flight_WIRE[106], UInt<1>(0h0) \n connect _flight_WIRE[107], UInt<1>(0h0) \n connect _flight_WIRE[108], UInt<1>(0h0) \n connect _flight_WIRE[109], UInt<1>(0h0) \n connect _flight_WIRE[110], UInt<1>(0h0) \n connect _flight_WIRE[111], UInt<1>(0h0) \n connect _flight_WIRE[112], UInt<1>(0h0) \n connect _flight_WIRE[113], UInt<1>(0h0) \n connect _flight_WIRE[114], UInt<1>(0h0) \n connect _flight_WIRE[115], UInt<1>(0h0) \n connect _flight_WIRE[116], UInt<1>(0h0) \n connect _flight_WIRE[117], UInt<1>(0h0) \n connect _flight_WIRE[118], UInt<1>(0h0) \n connect _flight_WIRE[119], UInt<1>(0h0) \n connect _flight_WIRE[120], UInt<1>(0h0) \n connect _flight_WIRE[121], UInt<1>(0h0) \n connect _flight_WIRE[122], UInt<1>(0h0) \n connect _flight_WIRE[123], UInt<1>(0h0) \n connect _flight_WIRE[124], UInt<1>(0h0) \n connect _flight_WIRE[125], UInt<1>(0h0) \n connect _flight_WIRE[126], UInt<1>(0h0) \n connect _flight_WIRE[127], UInt<1>(0h0) \n connect _flight_WIRE[128], UInt<1>(0h0) \n regreset flight : UInt<1>[129], clock, reset, _flight_WIRE \n node _T = and(anonIn.a.ready, anonIn.a.valid) \n node _T_1 = and(a_first, _T) \n when _T_1 : \n node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n connect flight[anonIn.a.bits.source], _flight_T \n node _T_2 = and(anonIn.d.ready, anonIn.d.valid) \n node _T_3 = and(d_first, _T_2) \n when _T_3 : \n connect flight[anonIn.d.bits.source], UInt<1>(0h0) \n node _stalls_a_sel_uncommonBits_T = or(anonIn.a.bits.source, UInt<3>(0h0)) \n node stalls_a_sel_uncommonBits = bits(_stalls_a_sel_uncommonBits_T, 2, 0) \n node _stalls_a_sel_T = shr(anonIn.a.bits.source, 3) \n node _stalls_a_sel_T_1 = eq(_stalls_a_sel_T, UInt<2>(0h2)) \n node _stalls_a_sel_T_2 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits) \n node _stalls_a_sel_T_3 = and(_stalls_a_sel_T_1, _stalls_a_sel_T_2) \n node _stalls_a_sel_T_4 = leq(stalls_a_sel_uncommonBits, UInt<3>(0h7)) \n node stalls_a_sel = and(_stalls_a_sel_T_3, _stalls_a_sel_T_4) \n node _stalls_id_T = and(anonIn.a.ready, anonIn.a.valid) \n node _stalls_id_T_1 = and(_stalls_id_T, stalls_a_sel) \n node _stalls_id_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _stalls_id_T_3 = and(_stalls_id_T_1, _stalls_id_T_2) \n reg stalls_id : UInt<4>, clock \n when _stalls_id_T_3 : \n connect stalls_id, a_id \n node _stalls_T = and(stalls_a_sel, a_first) \n node _stalls_T_1 = or(flight[16], flight[17]) \n node _stalls_T_2 = or(_stalls_T_1, flight[18]) \n node _stalls_T_3 = or(_stalls_T_2, flight[19]) \n node _stalls_T_4 = or(_stalls_T_3, flight[20]) \n node _stalls_T_5 = or(_stalls_T_4, flight[21]) \n node _stalls_T_6 = or(_stalls_T_5, flight[22]) \n node _stalls_T_7 = or(_stalls_T_6, flight[23]) \n node _stalls_T_8 = and(_stalls_T, _stalls_T_7) \n node _stalls_T_9 = neq(stalls_id, a_id) \n node _stalls_T_10 = or(a_noDomain, _stalls_T_9) \n node stalls_0 = and(_stalls_T_8, _stalls_T_10) \n node _stalls_a_sel_uncommonBits_T_1 = or(anonIn.a.bits.source, UInt<3>(0h0)) \n node stalls_a_sel_uncommonBits_1 = bits(_stalls_a_sel_uncommonBits_T_1, 2, 0) \n node _stalls_a_sel_T_5 = shr(anonIn.a.bits.source, 3) \n node _stalls_a_sel_T_6 = eq(_stalls_a_sel_T_5, UInt<2>(0h3)) \n node _stalls_a_sel_T_7 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_1) \n node _stalls_a_sel_T_8 = and(_stalls_a_sel_T_6, _stalls_a_sel_T_7) \n node _stalls_a_sel_T_9 = leq(stalls_a_sel_uncommonBits_1, UInt<3>(0h7)) \n node stalls_a_sel_1 = and(_stalls_a_sel_T_8, _stalls_a_sel_T_9) \n node _stalls_id_T_4 = and(anonIn.a.ready, anonIn.a.valid) \n node _stalls_id_T_5 = and(_stalls_id_T_4, stalls_a_sel_1) \n node _stalls_id_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _stalls_id_T_7 = and(_stalls_id_T_5, _stalls_id_T_6) \n reg stalls_id_1 : UInt<4>, clock \n when _stalls_id_T_7 : \n connect stalls_id_1, a_id \n node _stalls_T_11 = and(stalls_a_sel_1, a_first) \n node _stalls_T_12 = or(flight[24], flight[25]) \n node _stalls_T_13 = or(_stalls_T_12, flight[26]) \n node _stalls_T_14 = or(_stalls_T_13, flight[27]) \n node _stalls_T_15 = or(_stalls_T_14, flight[28]) \n node _stalls_T_16 = or(_stalls_T_15, flight[29]) \n node _stalls_T_17 = or(_stalls_T_16, flight[30]) \n node _stalls_T_18 = or(_stalls_T_17, flight[31]) \n node _stalls_T_19 = and(_stalls_T_11, _stalls_T_18) \n node _stalls_T_20 = neq(stalls_id_1, a_id) \n node _stalls_T_21 = or(a_noDomain, _stalls_T_20) \n node stalls_1 = and(_stalls_T_19, _stalls_T_21) \n node _stall_T = or(UInt<1>(0h0), stalls_0) \n node stall = or(_stall_T, stalls_1) \n connect anonOut.a, anonIn.a \n connect anonIn.d, anonOut.d \n node _anonOut_a_valid_T = eq(stall, UInt<1>(0h0)) \n node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T) \n node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1) \n connect anonOut.a.valid, _anonOut_a_valid_T_2 \n node _anonIn_a_ready_T = eq(stall, UInt<1>(0h0)) \n node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T) \n node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1) \n connect anonIn.a.ready, _anonIn_a_ready_T_2 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<8>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n connect _WIRE_1.valid, UInt<1>(0h0) \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<8>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n connect _WIRE_3.ready, UInt<1>(0h1) \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n connect _WIRE_5.ready, UInt<1>(0h1) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.mask, UInt<8>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<8>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<2>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n connect _WIRE_7.ready, UInt<1>(0h1) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<8>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n connect _WIRE_9.valid, UInt<1>(0h0) \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_10.bits.sink, UInt<1>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n connect _WIRE_11.valid, UInt<1>(0h0) \n node _T_4 = and(anonIn.a.valid, stall) \n regreset SourceIdFIFOed : UInt<129>, clock, reset, UInt<129>(0h0) \n wire SourceIdSet : UInt<129> \n connect SourceIdSet, UInt<129>(0h0) \n wire SourceIdClear : UInt<129> \n connect SourceIdClear, UInt<129>(0h0) \n node _T_5 = and(anonIn.a.ready, anonIn.a.valid) \n node _T_6 = and(a_first, _T_5) \n node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_8 = and(_T_6, _T_7) \n when _T_8 : \n node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source) \n connect SourceIdSet, _SourceIdSet_T \n node _T_9 = and(anonIn.d.ready, anonIn.d.valid) \n node _T_10 = and(d_first, _T_9) \n when _T_10 : \n node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source) \n connect SourceIdClear, _SourceIdClear_T \n node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet) \n connect SourceIdFIFOed, _SourceIdFIFOed_T \n node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<129>(0h1ffffffffffffffffffffffffffffffff), UInt<129>(0h0)) \n node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T) \n node _T_11 = or(flight[0], flight[1]) \n node _T_12 = or(_T_11, flight[2]) \n node _T_13 = or(_T_12, flight[3]) \n node _T_14 = or(_T_13, flight[4]) \n node _T_15 = or(_T_14, flight[5]) \n node _T_16 = or(_T_15, flight[6]) \n node _T_17 = or(_T_16, flight[7]) \n node _T_18 = or(_T_17, flight[8]) \n node _T_19 = or(_T_18, flight[9]) \n node _T_20 = or(_T_19, flight[10]) \n node _T_21 = or(_T_20, flight[11]) \n node _T_22 = or(_T_21, flight[12]) \n node _T_23 = or(_T_22, flight[13]) \n node _T_24 = or(_T_23, flight[14]) \n node _T_25 = or(_T_24, flight[15]) \n node _T_26 = or(_T_25, flight[16]) \n node _T_27 = or(_T_26, flight[17]) \n node _T_28 = or(_T_27, flight[18]) \n node _T_29 = or(_T_28, flight[19]) \n node _T_30 = or(_T_29, flight[20]) \n node _T_31 = or(_T_30, flight[21]) \n node _T_32 = or(_T_31, flight[22]) \n node _T_33 = or(_T_32, flight[23]) \n node _T_34 = or(_T_33, flight[24]) \n node _T_35 = or(_T_34, flight[25]) \n node _T_36 = or(_T_35, flight[26]) \n node _T_37 = or(_T_36, flight[27]) \n node _T_38 = or(_T_37, flight[28]) \n node _T_39 = or(_T_38, flight[29]) \n node _T_40 = or(_T_39, flight[30]) \n node _T_41 = or(_T_40, flight[31]) \n node _T_42 = or(_T_41, flight[32]) \n node _T_43 = or(_T_42, flight[33]) \n node _T_44 = or(_T_43, flight[34]) \n node _T_45 = or(_T_44, flight[35]) \n node _T_46 = or(_T_45, flight[36]) \n node _T_47 = or(_T_46, flight[37]) \n node _T_48 = or(_T_47, flight[38]) \n node _T_49 = or(_T_48, flight[39]) \n node _T_50 = or(_T_49, flight[40]) \n node _T_51 = or(_T_50, flight[41]) \n node _T_52 = or(_T_51, flight[42]) \n node _T_53 = or(_T_52, flight[43]) \n node _T_54 = or(_T_53, flight[44]) \n node _T_55 = or(_T_54, flight[45]) \n node _T_56 = or(_T_55, flight[46]) \n node _T_57 = or(_T_56, flight[47]) \n node _T_58 = or(_T_57, flight[48]) \n node _T_59 = or(_T_58, flight[49]) \n node _T_60 = or(_T_59, flight[50]) \n node _T_61 = or(_T_60, flight[51]) \n node _T_62 = or(_T_61, flight[52]) \n node _T_63 = or(_T_62, flight[53]) \n node _T_64 = or(_T_63, flight[54]) \n node _T_65 = or(_T_64, flight[55]) \n node _T_66 = or(_T_65, flight[56]) \n node _T_67 = or(_T_66, flight[57]) \n node _T_68 = or(_T_67, flight[58]) \n node _T_69 = or(_T_68, flight[59]) \n node _T_70 = or(_T_69, flight[60]) \n node _T_71 = or(_T_70, flight[61]) \n node _T_72 = or(_T_71, flight[62]) \n node _T_73 = or(_T_72, flight[63]) \n node _T_74 = or(_T_73, flight[64]) \n node _T_75 = or(_T_74, flight[65]) \n node _T_76 = or(_T_75, flight[66]) \n node _T_77 = or(_T_76, flight[67]) \n node _T_78 = or(_T_77, flight[68]) \n node _T_79 = or(_T_78, flight[69]) \n node _T_80 = or(_T_79, flight[70]) \n node _T_81 = or(_T_80, flight[71]) \n node _T_82 = or(_T_81, flight[72]) \n node _T_83 = or(_T_82, flight[73]) \n node _T_84 = or(_T_83, flight[74]) \n node _T_85 = or(_T_84, flight[75]) \n node _T_86 = or(_T_85, flight[76]) \n node _T_87 = or(_T_86, flight[77]) \n node _T_88 = or(_T_87, flight[78]) \n node _T_89 = or(_T_88, flight[79]) \n node _T_90 = or(_T_89, flight[80]) \n node _T_91 = or(_T_90, flight[81]) \n node _T_92 = or(_T_91, flight[82]) \n node _T_93 = or(_T_92, flight[83]) \n node _T_94 = or(_T_93, flight[84]) \n node _T_95 = or(_T_94, flight[85]) \n node _T_96 = or(_T_95, flight[86]) \n node _T_97 = or(_T_96, flight[87]) \n node _T_98 = or(_T_97, flight[88]) \n node _T_99 = or(_T_98, flight[89]) \n node _T_100 = or(_T_99, flight[90]) \n node _T_101 = or(_T_100, flight[91]) \n node _T_102 = or(_T_101, flight[92]) \n node _T_103 = or(_T_102, flight[93]) \n node _T_104 = or(_T_103, flight[94]) \n node _T_105 = or(_T_104, flight[95]) \n node _T_106 = or(_T_105, flight[96]) \n node _T_107 = or(_T_106, flight[97]) \n node _T_108 = or(_T_107, flight[98]) \n node _T_109 = or(_T_108, flight[99]) \n node _T_110 = or(_T_109, flight[100]) \n node _T_111 = or(_T_110, flight[101]) \n node _T_112 = or(_T_111, flight[102]) \n node _T_113 = or(_T_112, flight[103]) \n node _T_114 = or(_T_113, flight[104]) \n node _T_115 = or(_T_114, flight[105]) \n node _T_116 = or(_T_115, flight[106]) \n node _T_117 = or(_T_116, flight[107]) \n node _T_118 = or(_T_117, flight[108]) \n node _T_119 = or(_T_118, flight[109]) \n node _T_120 = or(_T_119, flight[110]) \n node _T_121 = or(_T_120, flight[111]) \n node _T_122 = or(_T_121, flight[112]) \n node _T_123 = or(_T_122, flight[113]) \n node _T_124 = or(_T_123, flight[114]) \n node _T_125 = or(_T_124, flight[115]) \n node _T_126 = or(_T_125, flight[116]) \n node _T_127 = or(_T_126, flight[117]) \n node _T_128 = or(_T_127, flight[118]) \n node _T_129 = or(_T_128, flight[119]) \n node _T_130 = or(_T_129, flight[120]) \n node _T_131 = or(_T_130, flight[121]) \n node _T_132 = or(_T_131, flight[122]) \n node _T_133 = or(_T_132, flight[123]) \n node _T_134 = or(_T_133, flight[124]) \n node _T_135 = or(_T_134, flight[125]) \n node _T_136 = or(_T_135, flight[126]) \n node _T_137 = or(_T_136, flight[127]) \n node _T_138 = or(_T_137, flight[128]) \n node _T_139 = eq(_T_138, UInt<1>(0h0)) \n node _T_140 = gt(SourceIdSet, UInt<1>(0h0)) \n node _T_141 = gt(SourceIdClear, UInt<1>(0h0)) \n\n\n extmodule plusarg_reader_44 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32\n\n\n\n extmodule plusarg_reader_45 : \n output out : UInt<32>\n\n defname = plusarg_reader\n\n parameter DEFAULT = 0\n\n parameter FORMAT = \"tilelink_timeout=%d\"\n\n parameter WIDTH = 32"},"response":{"kind":"string","value":"module TLFIFOFixer_3(\t// @[FIFOFixer.scala:50:9]\n input clock,\t// @[FIFOFixer.scala:50:9]\n input reset,\t// @[FIFOFixer.scala:50:9]\n output auto_anon_in_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_in_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_in_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_in_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_in_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [7:0] auto_anon_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [63:0] auto_anon_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [7:0] auto_anon_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [63:0] auto_anon_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire [32:0] _a_notFIFO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _a_notFIFO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire _flight_WIRE_0 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_1 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_2 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_3 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_4 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_5 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_6 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_7 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_8 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_9 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_10 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_11 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_12 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_13 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_14 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_15 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_16 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_17 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_18 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_19 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_20 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_21 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_22 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_23 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_24 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_25 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_26 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_27 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_28 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_29 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_30 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_31 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_32 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_33 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_34 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_35 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_36 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_37 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_38 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_39 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_40 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_41 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_42 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_43 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_44 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_45 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_46 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_47 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_48 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_49 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_50 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_51 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_52 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_53 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_54 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_55 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_56 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_57 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_58 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_59 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_60 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_61 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_62 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_63 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_64 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_65 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_66 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_67 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_68 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_69 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_70 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_71 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_72 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_73 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_74 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_75 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_76 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_77 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_78 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_79 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_80 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_81 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_82 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_83 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_84 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_85 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_86 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_87 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_88 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_89 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_90 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_91 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_92 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_93 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_94 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_95 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_96 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_97 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_98 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_99 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_100 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_101 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_102 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_103 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_104 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_105 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_106 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_107 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_108 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_109 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_110 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_111 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_112 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_113 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_114 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_115 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_116 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_117 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_118 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_119 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_120 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_121 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_122 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_123 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_124 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_125 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_126 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_127 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _flight_WIRE_128 = 1'h0;\t// @[FIFOFixer.scala:79:35]\n wire _a_notFIFO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire _flight_T = 1'h1;\t// @[FIFOFixer.scala:80:65]\n wire _stalls_a_sel_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_2 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire _stalls_a_sel_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _stalls_a_sel_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _stalls_id_T_6 = 1'h1;\t// @[FIFOFixer.scala:85:59]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire [128:0] _allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;\t// @[FIFOFixer.scala:127:48]\n wire anonIn_a_valid = auto_anon_in_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_ready = auto_anon_in_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [7:0] anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [63:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_ready = auto_anon_out_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [7:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [7:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [63:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_in_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [1:0] auto_anon_in_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_in_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_in_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_in_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_in_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n wire [2:0] auto_anon_out_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n wire [3:0] auto_anon_out_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n wire [31:0] auto_anon_out_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n wire [7:0] auto_anon_out_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n wire [63:0] auto_anon_out_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n wire auto_anon_out_d_ready_0;\t// @[FIFOFixer.scala:50:9]\n wire _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n assign auto_anon_in_a_ready_0 = anonIn_a_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonOut_a_bits_opcode = anonIn_a_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_param = anonIn_a_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_size = anonIn_a_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_source = anonIn_a_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n wire [7:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n wire [7:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source;\t// @[Parameters.scala:52:29]\n assign anonOut_a_bits_address = anonIn_a_bits_address;\t// @[MixedNode.scala:542:17, :551:17]\n wire [31:0] _a_notFIFO_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n wire [31:0] _a_id_T = anonIn_a_bits_address;\t// @[Parameters.scala:137:31]\n assign anonOut_a_bits_mask = anonIn_a_bits_mask;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_data = anonIn_a_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonOut_d_ready = anonIn_d_ready;\t// @[MixedNode.scala:542:17, :551:17]\n assign auto_anon_in_d_valid_0 = anonIn_d_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n wire _anonOut_a_valid_T_2;\t// @[FIFOFixer.scala:95:33]\n assign auto_anon_out_a_valid_0 = anonOut_a_valid;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_d_ready_0 = anonOut_d_ready;\t// @[FIFOFixer.scala:50:9]\n assign anonIn_d_valid = anonOut_d_valid;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_opcode = anonOut_d_bits_opcode;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_param = anonOut_d_bits_param;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_size = anonOut_d_bits_size;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_source = anonOut_d_bits_source;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_sink = anonOut_d_bits_sink;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_denied = anonOut_d_bits_denied;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_data = anonOut_d_bits_data;\t// @[MixedNode.scala:542:17, :551:17]\n assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[MixedNode.scala:542:17, :551:17]\n wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_1 = {1'h0, _a_id_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_2 = _a_id_T_1 & 33'h9A113000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_3 = _a_id_T_2;\t// @[Parameters.scala:137:46]\n wire _a_id_T_4 = _a_id_T_3 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_5 = {anonIn_a_bits_address[31:13], anonIn_a_bits_address[12:0] ^ 13'h1000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_6 = {1'h0, _a_id_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_7 = _a_id_T_6 & 33'h9A113000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_8 = _a_id_T_7;\t// @[Parameters.scala:137:46]\n wire _a_id_T_9 = _a_id_T_8 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_10 = {anonIn_a_bits_address[31:29], anonIn_a_bits_address[28:0] ^ 29'h10000000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_11 = {1'h0, _a_id_T_10};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_12 = _a_id_T_11 & 33'h9A113000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_13 = _a_id_T_12;\t// @[Parameters.scala:137:46]\n wire _a_id_T_14 = _a_id_T_13 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_id_T_15 = _a_id_T_9 | _a_id_T_14;\t// @[Parameters.scala:629:89]\n wire [31:0] _a_id_T_16 = {anonIn_a_bits_address[31:14], anonIn_a_bits_address[13:0] ^ 14'h3000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_17 = {1'h0, _a_id_T_16};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_18 = _a_id_T_17 & 33'h9A113000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_19 = _a_id_T_18;\t// @[Parameters.scala:137:46]\n wire _a_id_T_20 = _a_id_T_19 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire _a_id_T_48 = _a_id_T_20;\t// @[Mux.scala:30:73]\n wire [31:0] _a_id_T_21 = {anonIn_a_bits_address[31:17], anonIn_a_bits_address[16:0] ^ 17'h10000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_22 = {1'h0, _a_id_T_21};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_23 = _a_id_T_22 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_24 = _a_id_T_23;\t// @[Parameters.scala:137:46]\n wire _a_id_T_25 = _a_id_T_24 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_26 = {anonIn_a_bits_address[31:21], anonIn_a_bits_address[20:0] ^ 21'h100000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_27 = {1'h0, _a_id_T_26};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_28 = _a_id_T_27 & 33'h9A103000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_29 = _a_id_T_28;\t// @[Parameters.scala:137:46]\n wire _a_id_T_30 = _a_id_T_29 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_31 = {anonIn_a_bits_address[31:26], anonIn_a_bits_address[25:0] ^ 26'h2000000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_32 = {1'h0, _a_id_T_31};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_33 = _a_id_T_32 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_34 = _a_id_T_33;\t// @[Parameters.scala:137:46]\n wire _a_id_T_35 = _a_id_T_34 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_36 = {anonIn_a_bits_address[31:28], anonIn_a_bits_address[27:0] ^ 28'h8000000};\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_37 = {1'h0, _a_id_T_36};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_38 = _a_id_T_37 & 33'h98000000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_39 = _a_id_T_38;\t// @[Parameters.scala:137:46]\n wire _a_id_T_40 = _a_id_T_39 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [31:0] _a_id_T_41 = anonIn_a_bits_address ^ 32'h80000000;\t// @[Parameters.scala:137:31]\n wire [32:0] _a_id_T_42 = {1'h0, _a_id_T_41};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _a_id_T_43 = _a_id_T_42 & 33'h9A110000;\t// @[Parameters.scala:137:{41,46}]\n wire [32:0] _a_id_T_44 = _a_id_T_43;\t// @[Parameters.scala:137:46]\n wire _a_id_T_45 = _a_id_T_44 == 33'h0;\t// @[Parameters.scala:137:{46,59}]\n wire [3:0] _a_id_T_46 = {_a_id_T_4, 3'h0};\t// @[Mux.scala:30:73]\n wire [1:0] _a_id_T_47 = {2{_a_id_T_15}};\t// @[Mux.scala:30:73]\n wire [2:0] _a_id_T_49 = {_a_id_T_25, 2'h0};\t// @[Mux.scala:30:73]\n wire [2:0] _a_id_T_50 = _a_id_T_30 ? 3'h6 : 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _a_id_T_51 = _a_id_T_35 ? 3'h5 : 3'h0;\t// @[Mux.scala:30:73]\n wire [2:0] _a_id_T_52 = {3{_a_id_T_40}};\t// @[Mux.scala:30:73]\n wire [1:0] _a_id_T_53 = {_a_id_T_45, 1'h0};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_54 = {_a_id_T_46[3:2], _a_id_T_46[1:0] | _a_id_T_47};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_55 = {_a_id_T_54[3:1], _a_id_T_54[0] | _a_id_T_48};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_56 = {_a_id_T_55[3], _a_id_T_55[2:0] | _a_id_T_49};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_57 = {_a_id_T_56[3], _a_id_T_56[2:0] | _a_id_T_50};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_58 = {_a_id_T_57[3], _a_id_T_57[2:0] | _a_id_T_51};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_59 = {_a_id_T_58[3], _a_id_T_58[2:0] | _a_id_T_52};\t// @[Mux.scala:30:73]\n wire [3:0] _a_id_T_60 = {_a_id_T_59[3:2], _a_id_T_59[1:0] | _a_id_T_53};\t// @[Mux.scala:30:73]\n wire [3:0] a_id = _a_id_T_60;\t// @[Mux.scala:30:73]\n wire a_noDomain = a_id == 4'h0;\t// @[Mux.scala:30:73]\n wire _T_5 = anonIn_a_ready & anonIn_a_valid;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T = _T_5;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_4;\t// @[Decoupled.scala:51:35]\n assign _stalls_id_T_4 = _T_5;\t// @[Decoupled.scala:51:35]\n wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2];\t// @[Edges.scala:92:37]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [8:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T = anonOut_d_ready & anonOut_d_valid;\t// @[Decoupled.scala:51:35]\n wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = anonOut_d_bits_opcode[0];\t// @[Edges.scala:106:36]\n wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [8:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0];\t// @[Edges.scala:230:28]\n wire d_first_first = d_first_counter == 9'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 9'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 9'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [8:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6;\t// @[FIFOFixer.scala:75:63]\n wire d_first = d_first_first & _d_first_T_1;\t// @[FIFOFixer.scala:75:{42,63}]\n reg flight_0;\t// @[FIFOFixer.scala:79:27]\n reg flight_1;\t// @[FIFOFixer.scala:79:27]\n reg flight_2;\t// @[FIFOFixer.scala:79:27]\n reg flight_3;\t// @[FIFOFixer.scala:79:27]\n reg flight_4;\t// @[FIFOFixer.scala:79:27]\n reg flight_5;\t// @[FIFOFixer.scala:79:27]\n reg flight_6;\t// @[FIFOFixer.scala:79:27]\n reg flight_7;\t// @[FIFOFixer.scala:79:27]\n reg flight_8;\t// @[FIFOFixer.scala:79:27]\n reg flight_9;\t// @[FIFOFixer.scala:79:27]\n reg flight_10;\t// @[FIFOFixer.scala:79:27]\n reg flight_11;\t// @[FIFOFixer.scala:79:27]\n reg flight_12;\t// @[FIFOFixer.scala:79:27]\n reg flight_13;\t// @[FIFOFixer.scala:79:27]\n reg flight_14;\t// @[FIFOFixer.scala:79:27]\n reg flight_15;\t// @[FIFOFixer.scala:79:27]\n reg flight_16;\t// @[FIFOFixer.scala:79:27]\n reg flight_17;\t// @[FIFOFixer.scala:79:27]\n reg flight_18;\t// @[FIFOFixer.scala:79:27]\n reg flight_19;\t// @[FIFOFixer.scala:79:27]\n reg flight_20;\t// @[FIFOFixer.scala:79:27]\n reg flight_21;\t// @[FIFOFixer.scala:79:27]\n reg flight_22;\t// @[FIFOFixer.scala:79:27]\n reg flight_23;\t// @[FIFOFixer.scala:79:27]\n reg flight_24;\t// @[FIFOFixer.scala:79:27]\n reg flight_25;\t// @[FIFOFixer.scala:79:27]\n reg flight_26;\t// @[FIFOFixer.scala:79:27]\n reg flight_27;\t// @[FIFOFixer.scala:79:27]\n reg flight_28;\t// @[FIFOFixer.scala:79:27]\n reg flight_29;\t// @[FIFOFixer.scala:79:27]\n reg flight_30;\t// @[FIFOFixer.scala:79:27]\n reg flight_31;\t// @[FIFOFixer.scala:79:27]\n reg flight_32;\t// @[FIFOFixer.scala:79:27]\n reg flight_33;\t// @[FIFOFixer.scala:79:27]\n reg flight_34;\t// @[FIFOFixer.scala:79:27]\n reg flight_35;\t// @[FIFOFixer.scala:79:27]\n reg flight_36;\t// @[FIFOFixer.scala:79:27]\n reg flight_37;\t// @[FIFOFixer.scala:79:27]\n reg flight_38;\t// @[FIFOFixer.scala:79:27]\n reg flight_39;\t// @[FIFOFixer.scala:79:27]\n reg flight_40;\t// @[FIFOFixer.scala:79:27]\n reg flight_41;\t// @[FIFOFixer.scala:79:27]\n reg flight_42;\t// @[FIFOFixer.scala:79:27]\n reg flight_43;\t// @[FIFOFixer.scala:79:27]\n reg flight_44;\t// @[FIFOFixer.scala:79:27]\n reg flight_45;\t// @[FIFOFixer.scala:79:27]\n reg flight_46;\t// @[FIFOFixer.scala:79:27]\n reg flight_47;\t// @[FIFOFixer.scala:79:27]\n reg flight_48;\t// @[FIFOFixer.scala:79:27]\n reg flight_49;\t// @[FIFOFixer.scala:79:27]\n reg flight_50;\t// @[FIFOFixer.scala:79:27]\n reg flight_51;\t// @[FIFOFixer.scala:79:27]\n reg flight_52;\t// @[FIFOFixer.scala:79:27]\n reg flight_53;\t// @[FIFOFixer.scala:79:27]\n reg flight_54;\t// @[FIFOFixer.scala:79:27]\n reg flight_55;\t// @[FIFOFixer.scala:79:27]\n reg flight_56;\t// @[FIFOFixer.scala:79:27]\n reg flight_57;\t// @[FIFOFixer.scala:79:27]\n reg flight_58;\t// @[FIFOFixer.scala:79:27]\n reg flight_59;\t// @[FIFOFixer.scala:79:27]\n reg flight_60;\t// @[FIFOFixer.scala:79:27]\n reg flight_61;\t// @[FIFOFixer.scala:79:27]\n reg flight_62;\t// @[FIFOFixer.scala:79:27]\n reg flight_63;\t// @[FIFOFixer.scala:79:27]\n reg flight_64;\t// @[FIFOFixer.scala:79:27]\n reg flight_65;\t// @[FIFOFixer.scala:79:27]\n reg flight_66;\t// @[FIFOFixer.scala:79:27]\n reg flight_67;\t// @[FIFOFixer.scala:79:27]\n reg flight_68;\t// @[FIFOFixer.scala:79:27]\n reg flight_69;\t// @[FIFOFixer.scala:79:27]\n reg flight_70;\t// @[FIFOFixer.scala:79:27]\n reg flight_71;\t// @[FIFOFixer.scala:79:27]\n reg flight_72;\t// @[FIFOFixer.scala:79:27]\n reg flight_73;\t// @[FIFOFixer.scala:79:27]\n reg flight_74;\t// @[FIFOFixer.scala:79:27]\n reg flight_75;\t// @[FIFOFixer.scala:79:27]\n reg flight_76;\t// @[FIFOFixer.scala:79:27]\n reg flight_77;\t// @[FIFOFixer.scala:79:27]\n reg flight_78;\t// @[FIFOFixer.scala:79:27]\n reg flight_79;\t// @[FIFOFixer.scala:79:27]\n reg flight_80;\t// @[FIFOFixer.scala:79:27]\n reg flight_81;\t// @[FIFOFixer.scala:79:27]\n reg flight_82;\t// @[FIFOFixer.scala:79:27]\n reg flight_83;\t// @[FIFOFixer.scala:79:27]\n reg flight_84;\t// @[FIFOFixer.scala:79:27]\n reg flight_85;\t// @[FIFOFixer.scala:79:27]\n reg flight_86;\t// @[FIFOFixer.scala:79:27]\n reg flight_87;\t// @[FIFOFixer.scala:79:27]\n reg flight_88;\t// @[FIFOFixer.scala:79:27]\n reg flight_89;\t// @[FIFOFixer.scala:79:27]\n reg flight_90;\t// @[FIFOFixer.scala:79:27]\n reg flight_91;\t// @[FIFOFixer.scala:79:27]\n reg flight_92;\t// @[FIFOFixer.scala:79:27]\n reg flight_93;\t// @[FIFOFixer.scala:79:27]\n reg flight_94;\t// @[FIFOFixer.scala:79:27]\n reg flight_95;\t// @[FIFOFixer.scala:79:27]\n reg flight_96;\t// @[FIFOFixer.scala:79:27]\n reg flight_97;\t// @[FIFOFixer.scala:79:27]\n reg flight_98;\t// @[FIFOFixer.scala:79:27]\n reg flight_99;\t// @[FIFOFixer.scala:79:27]\n reg flight_100;\t// @[FIFOFixer.scala:79:27]\n reg flight_101;\t// @[FIFOFixer.scala:79:27]\n reg flight_102;\t// @[FIFOFixer.scala:79:27]\n reg flight_103;\t// @[FIFOFixer.scala:79:27]\n reg flight_104;\t// @[FIFOFixer.scala:79:27]\n reg flight_105;\t// @[FIFOFixer.scala:79:27]\n reg flight_106;\t// @[FIFOFixer.scala:79:27]\n reg flight_107;\t// @[FIFOFixer.scala:79:27]\n reg flight_108;\t// @[FIFOFixer.scala:79:27]\n reg flight_109;\t// @[FIFOFixer.scala:79:27]\n reg flight_110;\t// @[FIFOFixer.scala:79:27]\n reg flight_111;\t// @[FIFOFixer.scala:79:27]\n reg flight_112;\t// @[FIFOFixer.scala:79:27]\n reg flight_113;\t// @[FIFOFixer.scala:79:27]\n reg flight_114;\t// @[FIFOFixer.scala:79:27]\n reg flight_115;\t// @[FIFOFixer.scala:79:27]\n reg flight_116;\t// @[FIFOFixer.scala:79:27]\n reg flight_117;\t// @[FIFOFixer.scala:79:27]\n reg flight_118;\t// @[FIFOFixer.scala:79:27]\n reg flight_119;\t// @[FIFOFixer.scala:79:27]\n reg flight_120;\t// @[FIFOFixer.scala:79:27]\n reg flight_121;\t// @[FIFOFixer.scala:79:27]\n reg flight_122;\t// @[FIFOFixer.scala:79:27]\n reg flight_123;\t// @[FIFOFixer.scala:79:27]\n reg flight_124;\t// @[FIFOFixer.scala:79:27]\n reg flight_125;\t// @[FIFOFixer.scala:79:27]\n reg flight_126;\t// @[FIFOFixer.scala:79:27]\n reg flight_127;\t// @[FIFOFixer.scala:79:27]\n reg flight_128;\t// @[FIFOFixer.scala:79:27]\n wire _T_9 = anonIn_d_ready & anonIn_d_valid;\t// @[Decoupled.scala:51:35]\n wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] _stalls_a_sel_T = anonIn_a_bits_source[7:3];\t// @[Parameters.scala:54:10]\n wire [4:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[7:3];\t// @[Parameters.scala:54:10]\n wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 5'h2;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel = _stalls_a_sel_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_3 = _stalls_id_T_1;\t// @[FIFOFixer.scala:85:{47,56}]\n reg [3:0] stalls_id;\t// @[FIFOFixer.scala:85:30]\n wire _stalls_T = stalls_a_sel & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_1 = flight_16 | flight_17;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_2 = _stalls_T_1 | flight_18;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_3 = _stalls_T_2 | flight_19;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_4 = _stalls_T_3 | flight_20;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_5 = _stalls_T_4 | flight_21;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_6 = _stalls_T_5 | flight_22;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_7 = _stalls_T_6 | flight_23;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_8 = _stalls_T & _stalls_T_7;\t// @[FIFOFixer.scala:88:{15,26,44}]\n wire _stalls_T_9 = stalls_id != a_id;\t// @[Mux.scala:30:73]\n wire _stalls_T_10 = a_noDomain | _stalls_T_9;\t// @[FIFOFixer.scala:63:29, :88:{65,71}]\n wire stalls_0 = _stalls_T_8 & _stalls_T_10;\t// @[FIFOFixer.scala:88:{26,50,65}]\n wire _stall_T = stalls_0;\t// @[FIFOFixer.scala:88:50, :91:45]\n wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0];\t// @[Parameters.scala:52:{29,56}]\n wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 5'h3;\t// @[Parameters.scala:54:{10,32}]\n wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6;\t// @[Parameters.scala:54:{32,67}]\n wire stalls_a_sel_1 = _stalls_a_sel_T_8;\t// @[Parameters.scala:54:67, :56:48]\n wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1;\t// @[Decoupled.scala:51:35]\n wire _stalls_id_T_7 = _stalls_id_T_5;\t// @[FIFOFixer.scala:85:{47,56}]\n reg [3:0] stalls_id_1;\t// @[FIFOFixer.scala:85:30]\n wire _stalls_T_11 = stalls_a_sel_1 & a_first;\t// @[FIFOFixer.scala:88:15]\n wire _stalls_T_12 = flight_24 | flight_25;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_13 = _stalls_T_12 | flight_26;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_14 = _stalls_T_13 | flight_27;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_15 = _stalls_T_14 | flight_28;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_16 = _stalls_T_15 | flight_29;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_17 = _stalls_T_16 | flight_30;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_18 = _stalls_T_17 | flight_31;\t// @[FIFOFixer.scala:79:27, :88:44]\n wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18;\t// @[FIFOFixer.scala:88:{15,26,44}]\n wire _stalls_T_20 = stalls_id_1 != a_id;\t// @[Mux.scala:30:73]\n wire _stalls_T_21 = a_noDomain | _stalls_T_20;\t// @[FIFOFixer.scala:63:29, :88:{65,71}]\n wire stalls_1 = _stalls_T_19 & _stalls_T_21;\t// @[FIFOFixer.scala:88:{26,50,65}]\n wire stall = _stall_T | stalls_1;\t// @[FIFOFixer.scala:88:50, :91:45]\n wire _anonOut_a_valid_T = ~stall;\t// @[FIFOFixer.scala:91:45, :95:50]\n wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T;\t// @[FIFOFixer.scala:95:{47,50}]\n assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1;\t// @[FIFOFixer.scala:95:{33,47}]\n assign anonOut_a_valid = _anonOut_a_valid_T_2;\t// @[FIFOFixer.scala:95:33]\n wire _anonIn_a_ready_T = ~stall;\t// @[FIFOFixer.scala:91:45, :95:50, :96:50]\n wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T;\t// @[FIFOFixer.scala:96:{47,50}]\n assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1;\t// @[FIFOFixer.scala:96:{33,47}]\n assign anonIn_a_ready = _anonIn_a_ready_T_2;\t// @[FIFOFixer.scala:96:33]\n reg [128:0] SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35]\n wire [128:0] SourceIdSet;\t// @[FIFOFixer.scala:116:36]\n wire [128:0] SourceIdClear;\t// @[FIFOFixer.scala:117:38]\n wire [255:0] _SourceIdSet_T = 256'h1 << anonIn_a_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [255:0] _SourceIdClear_T = 256'h1 << anonIn_d_bits_source;\t// @[OneHot.scala:58:35]\n assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[128:0] : 129'h0;\t// @[OneHot.scala:58:35]\n wire [128:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet;\t// @[FIFOFixer.scala:115:35, :116:36, :126:40]\n wire allIDs_FIFOed = &SourceIdFIFOed;\t// @[FIFOFixer.scala:115:35, :127:41]\n wire _T_1 = a_first & _T_5;\t// @[Decoupled.scala:51:35]\n wire _T_3 = d_first & _T_9;\t// @[Decoupled.scala:51:35]\n always @(posedge clock) begin\t// @[FIFOFixer.scala:50:9]\n if (reset) begin\t// @[FIFOFixer.scala:50:9]\n a_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n d_first_counter <= 9'h0;\t// @[Edges.scala:229:27]\n flight_0 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_1 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_2 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_3 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_4 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_5 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_6 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_7 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_8 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_9 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_10 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_11 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_12 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_13 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_14 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_15 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_16 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_17 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_18 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_19 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_20 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_21 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_22 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_23 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_24 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_25 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_26 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_27 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_28 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_29 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_30 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_31 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_32 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_33 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_34 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_35 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_36 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_37 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_38 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_39 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_40 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_41 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_42 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_43 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_44 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_45 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_46 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_47 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_48 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_49 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_50 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_51 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_52 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_53 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_54 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_55 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_56 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_57 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_58 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_59 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_60 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_61 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_62 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_63 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_64 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_65 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_66 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_67 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_68 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_69 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_70 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_71 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_72 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_73 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_74 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_75 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_76 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_77 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_78 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_79 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_80 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_81 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_82 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_83 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_84 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_85 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_86 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_87 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_88 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_89 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_90 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_91 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_92 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_93 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_94 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_95 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_96 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_97 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_98 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_99 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_100 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_101 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_102 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_103 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_104 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_105 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_106 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_107 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_108 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_109 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_110 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_111 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_112 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_113 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_114 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_115 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_116 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_117 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_118 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_119 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_120 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_121 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_122 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_123 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_124 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_125 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_126 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_127 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n flight_128 <= 1'h0;\t// @[FIFOFixer.scala:79:27]\n SourceIdFIFOed <= 129'h0;\t// @[FIFOFixer.scala:115:35]\n end\n else begin\t// @[FIFOFixer.scala:50:9]\n if (_a_first_T)\t// @[Decoupled.scala:51:35]\n a_first_counter <= _a_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n if (_d_first_T)\t// @[Decoupled.scala:51:35]\n d_first_counter <= _d_first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n flight_0 <= ~(_T_3 & anonIn_d_bits_source == 8'h0) & (_T_1 & anonIn_a_bits_source == 8'h0 | flight_0);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_1 <= ~(_T_3 & anonIn_d_bits_source == 8'h1) & (_T_1 & anonIn_a_bits_source == 8'h1 | flight_1);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_2 <= ~(_T_3 & anonIn_d_bits_source == 8'h2) & (_T_1 & anonIn_a_bits_source == 8'h2 | flight_2);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_3 <= ~(_T_3 & anonIn_d_bits_source == 8'h3) & (_T_1 & anonIn_a_bits_source == 8'h3 | flight_3);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_4 <= ~(_T_3 & anonIn_d_bits_source == 8'h4) & (_T_1 & anonIn_a_bits_source == 8'h4 | flight_4);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_5 <= ~(_T_3 & anonIn_d_bits_source == 8'h5) & (_T_1 & anonIn_a_bits_source == 8'h5 | flight_5);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_6 <= ~(_T_3 & anonIn_d_bits_source == 8'h6) & (_T_1 & anonIn_a_bits_source == 8'h6 | flight_6);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_7 <= ~(_T_3 & anonIn_d_bits_source == 8'h7) & (_T_1 & anonIn_a_bits_source == 8'h7 | flight_7);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_8 <= ~(_T_3 & anonIn_d_bits_source == 8'h8) & (_T_1 & anonIn_a_bits_source == 8'h8 | flight_8);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_9 <= ~(_T_3 & anonIn_d_bits_source == 8'h9) & (_T_1 & anonIn_a_bits_source == 8'h9 | flight_9);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_10 <= ~(_T_3 & anonIn_d_bits_source == 8'hA) & (_T_1 & anonIn_a_bits_source == 8'hA | flight_10);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_11 <= ~(_T_3 & anonIn_d_bits_source == 8'hB) & (_T_1 & anonIn_a_bits_source == 8'hB | flight_11);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_12 <= ~(_T_3 & anonIn_d_bits_source == 8'hC) & (_T_1 & anonIn_a_bits_source == 8'hC | flight_12);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_13 <= ~(_T_3 & anonIn_d_bits_source == 8'hD) & (_T_1 & anonIn_a_bits_source == 8'hD | flight_13);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_14 <= ~(_T_3 & anonIn_d_bits_source == 8'hE) & (_T_1 & anonIn_a_bits_source == 8'hE | flight_14);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_15 <= ~(_T_3 & anonIn_d_bits_source == 8'hF) & (_T_1 & anonIn_a_bits_source == 8'hF | flight_15);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_16 <= ~(_T_3 & anonIn_d_bits_source == 8'h10) & (_T_1 & anonIn_a_bits_source == 8'h10 | flight_16);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_17 <= ~(_T_3 & anonIn_d_bits_source == 8'h11) & (_T_1 & anonIn_a_bits_source == 8'h11 | flight_17);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_18 <= ~(_T_3 & anonIn_d_bits_source == 8'h12) & (_T_1 & anonIn_a_bits_source == 8'h12 | flight_18);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_19 <= ~(_T_3 & anonIn_d_bits_source == 8'h13) & (_T_1 & anonIn_a_bits_source == 8'h13 | flight_19);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_20 <= ~(_T_3 & anonIn_d_bits_source == 8'h14) & (_T_1 & anonIn_a_bits_source == 8'h14 | flight_20);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_21 <= ~(_T_3 & anonIn_d_bits_source == 8'h15) & (_T_1 & anonIn_a_bits_source == 8'h15 | flight_21);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_22 <= ~(_T_3 & anonIn_d_bits_source == 8'h16) & (_T_1 & anonIn_a_bits_source == 8'h16 | flight_22);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_23 <= ~(_T_3 & anonIn_d_bits_source == 8'h17) & (_T_1 & anonIn_a_bits_source == 8'h17 | flight_23);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_24 <= ~(_T_3 & anonIn_d_bits_source == 8'h18) & (_T_1 & anonIn_a_bits_source == 8'h18 | flight_24);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_25 <= ~(_T_3 & anonIn_d_bits_source == 8'h19) & (_T_1 & anonIn_a_bits_source == 8'h19 | flight_25);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_26 <= ~(_T_3 & anonIn_d_bits_source == 8'h1A) & (_T_1 & anonIn_a_bits_source == 8'h1A | flight_26);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_27 <= ~(_T_3 & anonIn_d_bits_source == 8'h1B) & (_T_1 & anonIn_a_bits_source == 8'h1B | flight_27);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_28 <= ~(_T_3 & anonIn_d_bits_source == 8'h1C) & (_T_1 & anonIn_a_bits_source == 8'h1C | flight_28);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_29 <= ~(_T_3 & anonIn_d_bits_source == 8'h1D) & (_T_1 & anonIn_a_bits_source == 8'h1D | flight_29);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_30 <= ~(_T_3 & anonIn_d_bits_source == 8'h1E) & (_T_1 & anonIn_a_bits_source == 8'h1E | flight_30);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_31 <= ~(_T_3 & anonIn_d_bits_source == 8'h1F) & (_T_1 & anonIn_a_bits_source == 8'h1F | flight_31);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_32 <= ~(_T_3 & anonIn_d_bits_source == 8'h20) & (_T_1 & anonIn_a_bits_source == 8'h20 | flight_32);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_33 <= ~(_T_3 & anonIn_d_bits_source == 8'h21) & (_T_1 & anonIn_a_bits_source == 8'h21 | flight_33);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_34 <= ~(_T_3 & anonIn_d_bits_source == 8'h22) & (_T_1 & anonIn_a_bits_source == 8'h22 | flight_34);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_35 <= ~(_T_3 & anonIn_d_bits_source == 8'h23) & (_T_1 & anonIn_a_bits_source == 8'h23 | flight_35);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_36 <= ~(_T_3 & anonIn_d_bits_source == 8'h24) & (_T_1 & anonIn_a_bits_source == 8'h24 | flight_36);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_37 <= ~(_T_3 & anonIn_d_bits_source == 8'h25) & (_T_1 & anonIn_a_bits_source == 8'h25 | flight_37);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_38 <= ~(_T_3 & anonIn_d_bits_source == 8'h26) & (_T_1 & anonIn_a_bits_source == 8'h26 | flight_38);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_39 <= ~(_T_3 & anonIn_d_bits_source == 8'h27) & (_T_1 & anonIn_a_bits_source == 8'h27 | flight_39);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_40 <= ~(_T_3 & anonIn_d_bits_source == 8'h28) & (_T_1 & anonIn_a_bits_source == 8'h28 | flight_40);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_41 <= ~(_T_3 & anonIn_d_bits_source == 8'h29) & (_T_1 & anonIn_a_bits_source == 8'h29 | flight_41);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_42 <= ~(_T_3 & anonIn_d_bits_source == 8'h2A) & (_T_1 & anonIn_a_bits_source == 8'h2A | flight_42);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_43 <= ~(_T_3 & anonIn_d_bits_source == 8'h2B) & (_T_1 & anonIn_a_bits_source == 8'h2B | flight_43);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_44 <= ~(_T_3 & anonIn_d_bits_source == 8'h2C) & (_T_1 & anonIn_a_bits_source == 8'h2C | flight_44);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_45 <= ~(_T_3 & anonIn_d_bits_source == 8'h2D) & (_T_1 & anonIn_a_bits_source == 8'h2D | flight_45);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_46 <= ~(_T_3 & anonIn_d_bits_source == 8'h2E) & (_T_1 & anonIn_a_bits_source == 8'h2E | flight_46);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_47 <= ~(_T_3 & anonIn_d_bits_source == 8'h2F) & (_T_1 & anonIn_a_bits_source == 8'h2F | flight_47);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_48 <= ~(_T_3 & anonIn_d_bits_source == 8'h30) & (_T_1 & anonIn_a_bits_source == 8'h30 | flight_48);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_49 <= ~(_T_3 & anonIn_d_bits_source == 8'h31) & (_T_1 & anonIn_a_bits_source == 8'h31 | flight_49);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_50 <= ~(_T_3 & anonIn_d_bits_source == 8'h32) & (_T_1 & anonIn_a_bits_source == 8'h32 | flight_50);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_51 <= ~(_T_3 & anonIn_d_bits_source == 8'h33) & (_T_1 & anonIn_a_bits_source == 8'h33 | flight_51);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_52 <= ~(_T_3 & anonIn_d_bits_source == 8'h34) & (_T_1 & anonIn_a_bits_source == 8'h34 | flight_52);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_53 <= ~(_T_3 & anonIn_d_bits_source == 8'h35) & (_T_1 & anonIn_a_bits_source == 8'h35 | flight_53);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_54 <= ~(_T_3 & anonIn_d_bits_source == 8'h36) & (_T_1 & anonIn_a_bits_source == 8'h36 | flight_54);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_55 <= ~(_T_3 & anonIn_d_bits_source == 8'h37) & (_T_1 & anonIn_a_bits_source == 8'h37 | flight_55);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_56 <= ~(_T_3 & anonIn_d_bits_source == 8'h38) & (_T_1 & anonIn_a_bits_source == 8'h38 | flight_56);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_57 <= ~(_T_3 & anonIn_d_bits_source == 8'h39) & (_T_1 & anonIn_a_bits_source == 8'h39 | flight_57);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_58 <= ~(_T_3 & anonIn_d_bits_source == 8'h3A) & (_T_1 & anonIn_a_bits_source == 8'h3A | flight_58);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_59 <= ~(_T_3 & anonIn_d_bits_source == 8'h3B) & (_T_1 & anonIn_a_bits_source == 8'h3B | flight_59);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_60 <= ~(_T_3 & anonIn_d_bits_source == 8'h3C) & (_T_1 & anonIn_a_bits_source == 8'h3C | flight_60);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_61 <= ~(_T_3 & anonIn_d_bits_source == 8'h3D) & (_T_1 & anonIn_a_bits_source == 8'h3D | flight_61);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_62 <= ~(_T_3 & anonIn_d_bits_source == 8'h3E) & (_T_1 & anonIn_a_bits_source == 8'h3E | flight_62);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_63 <= ~(_T_3 & anonIn_d_bits_source == 8'h3F) & (_T_1 & anonIn_a_bits_source == 8'h3F | flight_63);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_64 <= ~(_T_3 & anonIn_d_bits_source == 8'h40) & (_T_1 & anonIn_a_bits_source == 8'h40 | flight_64);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_65 <= ~(_T_3 & anonIn_d_bits_source == 8'h41) & (_T_1 & anonIn_a_bits_source == 8'h41 | flight_65);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_66 <= ~(_T_3 & anonIn_d_bits_source == 8'h42) & (_T_1 & anonIn_a_bits_source == 8'h42 | flight_66);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_67 <= ~(_T_3 & anonIn_d_bits_source == 8'h43) & (_T_1 & anonIn_a_bits_source == 8'h43 | flight_67);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_68 <= ~(_T_3 & anonIn_d_bits_source == 8'h44) & (_T_1 & anonIn_a_bits_source == 8'h44 | flight_68);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_69 <= ~(_T_3 & anonIn_d_bits_source == 8'h45) & (_T_1 & anonIn_a_bits_source == 8'h45 | flight_69);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_70 <= ~(_T_3 & anonIn_d_bits_source == 8'h46) & (_T_1 & anonIn_a_bits_source == 8'h46 | flight_70);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_71 <= ~(_T_3 & anonIn_d_bits_source == 8'h47) & (_T_1 & anonIn_a_bits_source == 8'h47 | flight_71);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_72 <= ~(_T_3 & anonIn_d_bits_source == 8'h48) & (_T_1 & anonIn_a_bits_source == 8'h48 | flight_72);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_73 <= ~(_T_3 & anonIn_d_bits_source == 8'h49) & (_T_1 & anonIn_a_bits_source == 8'h49 | flight_73);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_74 <= ~(_T_3 & anonIn_d_bits_source == 8'h4A) & (_T_1 & anonIn_a_bits_source == 8'h4A | flight_74);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_75 <= ~(_T_3 & anonIn_d_bits_source == 8'h4B) & (_T_1 & anonIn_a_bits_source == 8'h4B | flight_75);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_76 <= ~(_T_3 & anonIn_d_bits_source == 8'h4C) & (_T_1 & anonIn_a_bits_source == 8'h4C | flight_76);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_77 <= ~(_T_3 & anonIn_d_bits_source == 8'h4D) & (_T_1 & anonIn_a_bits_source == 8'h4D | flight_77);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_78 <= ~(_T_3 & anonIn_d_bits_source == 8'h4E) & (_T_1 & anonIn_a_bits_source == 8'h4E | flight_78);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_79 <= ~(_T_3 & anonIn_d_bits_source == 8'h4F) & (_T_1 & anonIn_a_bits_source == 8'h4F | flight_79);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_80 <= ~(_T_3 & anonIn_d_bits_source == 8'h50) & (_T_1 & anonIn_a_bits_source == 8'h50 | flight_80);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_81 <= ~(_T_3 & anonIn_d_bits_source == 8'h51) & (_T_1 & anonIn_a_bits_source == 8'h51 | flight_81);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_82 <= ~(_T_3 & anonIn_d_bits_source == 8'h52) & (_T_1 & anonIn_a_bits_source == 8'h52 | flight_82);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_83 <= ~(_T_3 & anonIn_d_bits_source == 8'h53) & (_T_1 & anonIn_a_bits_source == 8'h53 | flight_83);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_84 <= ~(_T_3 & anonIn_d_bits_source == 8'h54) & (_T_1 & anonIn_a_bits_source == 8'h54 | flight_84);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_85 <= ~(_T_3 & anonIn_d_bits_source == 8'h55) & (_T_1 & anonIn_a_bits_source == 8'h55 | flight_85);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_86 <= ~(_T_3 & anonIn_d_bits_source == 8'h56) & (_T_1 & anonIn_a_bits_source == 8'h56 | flight_86);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_87 <= ~(_T_3 & anonIn_d_bits_source == 8'h57) & (_T_1 & anonIn_a_bits_source == 8'h57 | flight_87);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_88 <= ~(_T_3 & anonIn_d_bits_source == 8'h58) & (_T_1 & anonIn_a_bits_source == 8'h58 | flight_88);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_89 <= ~(_T_3 & anonIn_d_bits_source == 8'h59) & (_T_1 & anonIn_a_bits_source == 8'h59 | flight_89);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_90 <= ~(_T_3 & anonIn_d_bits_source == 8'h5A) & (_T_1 & anonIn_a_bits_source == 8'h5A | flight_90);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_91 <= ~(_T_3 & anonIn_d_bits_source == 8'h5B) & (_T_1 & anonIn_a_bits_source == 8'h5B | flight_91);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_92 <= ~(_T_3 & anonIn_d_bits_source == 8'h5C) & (_T_1 & anonIn_a_bits_source == 8'h5C | flight_92);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_93 <= ~(_T_3 & anonIn_d_bits_source == 8'h5D) & (_T_1 & anonIn_a_bits_source == 8'h5D | flight_93);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_94 <= ~(_T_3 & anonIn_d_bits_source == 8'h5E) & (_T_1 & anonIn_a_bits_source == 8'h5E | flight_94);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_95 <= ~(_T_3 & anonIn_d_bits_source == 8'h5F) & (_T_1 & anonIn_a_bits_source == 8'h5F | flight_95);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_96 <= ~(_T_3 & anonIn_d_bits_source == 8'h60) & (_T_1 & anonIn_a_bits_source == 8'h60 | flight_96);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_97 <= ~(_T_3 & anonIn_d_bits_source == 8'h61) & (_T_1 & anonIn_a_bits_source == 8'h61 | flight_97);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_98 <= ~(_T_3 & anonIn_d_bits_source == 8'h62) & (_T_1 & anonIn_a_bits_source == 8'h62 | flight_98);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_99 <= ~(_T_3 & anonIn_d_bits_source == 8'h63) & (_T_1 & anonIn_a_bits_source == 8'h63 | flight_99);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_100 <= ~(_T_3 & anonIn_d_bits_source == 8'h64) & (_T_1 & anonIn_a_bits_source == 8'h64 | flight_100);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_101 <= ~(_T_3 & anonIn_d_bits_source == 8'h65) & (_T_1 & anonIn_a_bits_source == 8'h65 | flight_101);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_102 <= ~(_T_3 & anonIn_d_bits_source == 8'h66) & (_T_1 & anonIn_a_bits_source == 8'h66 | flight_102);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_103 <= ~(_T_3 & anonIn_d_bits_source == 8'h67) & (_T_1 & anonIn_a_bits_source == 8'h67 | flight_103);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_104 <= ~(_T_3 & anonIn_d_bits_source == 8'h68) & (_T_1 & anonIn_a_bits_source == 8'h68 | flight_104);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_105 <= ~(_T_3 & anonIn_d_bits_source == 8'h69) & (_T_1 & anonIn_a_bits_source == 8'h69 | flight_105);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_106 <= ~(_T_3 & anonIn_d_bits_source == 8'h6A) & (_T_1 & anonIn_a_bits_source == 8'h6A | flight_106);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_107 <= ~(_T_3 & anonIn_d_bits_source == 8'h6B) & (_T_1 & anonIn_a_bits_source == 8'h6B | flight_107);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_108 <= ~(_T_3 & anonIn_d_bits_source == 8'h6C) & (_T_1 & anonIn_a_bits_source == 8'h6C | flight_108);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_109 <= ~(_T_3 & anonIn_d_bits_source == 8'h6D) & (_T_1 & anonIn_a_bits_source == 8'h6D | flight_109);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_110 <= ~(_T_3 & anonIn_d_bits_source == 8'h6E) & (_T_1 & anonIn_a_bits_source == 8'h6E | flight_110);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_111 <= ~(_T_3 & anonIn_d_bits_source == 8'h6F) & (_T_1 & anonIn_a_bits_source == 8'h6F | flight_111);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_112 <= ~(_T_3 & anonIn_d_bits_source == 8'h70) & (_T_1 & anonIn_a_bits_source == 8'h70 | flight_112);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_113 <= ~(_T_3 & anonIn_d_bits_source == 8'h71) & (_T_1 & anonIn_a_bits_source == 8'h71 | flight_113);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_114 <= ~(_T_3 & anonIn_d_bits_source == 8'h72) & (_T_1 & anonIn_a_bits_source == 8'h72 | flight_114);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_115 <= ~(_T_3 & anonIn_d_bits_source == 8'h73) & (_T_1 & anonIn_a_bits_source == 8'h73 | flight_115);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_116 <= ~(_T_3 & anonIn_d_bits_source == 8'h74) & (_T_1 & anonIn_a_bits_source == 8'h74 | flight_116);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_117 <= ~(_T_3 & anonIn_d_bits_source == 8'h75) & (_T_1 & anonIn_a_bits_source == 8'h75 | flight_117);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_118 <= ~(_T_3 & anonIn_d_bits_source == 8'h76) & (_T_1 & anonIn_a_bits_source == 8'h76 | flight_118);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_119 <= ~(_T_3 & anonIn_d_bits_source == 8'h77) & (_T_1 & anonIn_a_bits_source == 8'h77 | flight_119);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_120 <= ~(_T_3 & anonIn_d_bits_source == 8'h78) & (_T_1 & anonIn_a_bits_source == 8'h78 | flight_120);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_121 <= ~(_T_3 & anonIn_d_bits_source == 8'h79) & (_T_1 & anonIn_a_bits_source == 8'h79 | flight_121);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_122 <= ~(_T_3 & anonIn_d_bits_source == 8'h7A) & (_T_1 & anonIn_a_bits_source == 8'h7A | flight_122);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_123 <= ~(_T_3 & anonIn_d_bits_source == 8'h7B) & (_T_1 & anonIn_a_bits_source == 8'h7B | flight_123);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_124 <= ~(_T_3 & anonIn_d_bits_source == 8'h7C) & (_T_1 & anonIn_a_bits_source == 8'h7C | flight_124);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_125 <= ~(_T_3 & anonIn_d_bits_source == 8'h7D) & (_T_1 & anonIn_a_bits_source == 8'h7D | flight_125);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_126 <= ~(_T_3 & anonIn_d_bits_source == 8'h7E) & (_T_1 & anonIn_a_bits_source == 8'h7E | flight_126);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_127 <= ~(_T_3 & anonIn_d_bits_source == 8'h7F) & (_T_1 & anonIn_a_bits_source == 8'h7F | flight_127);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n flight_128 <= ~(_T_3 & anonIn_d_bits_source == 8'h80) & (_T_1 & anonIn_a_bits_source == 8'h80 | flight_128);\t// @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]\n SourceIdFIFOed <= _SourceIdFIFOed_T;\t// @[FIFOFixer.scala:115:35, :126:40]\n end\n if (_stalls_id_T_3)\t// @[FIFOFixer.scala:85:56]\n stalls_id <= a_id;\t// @[Mux.scala:30:73]\n if (_stalls_id_T_7)\t// @[FIFOFixer.scala:85:56]\n stalls_id_1 <= a_id;\t// @[Mux.scala:30:73]\n always @(posedge)\n TLMonitor_21 monitor (\t// @[Nodes.scala:27:25]\n .clock (clock),\n .reset (reset),\n .io_in_a_ready (anonIn_a_ready),\t// @[MixedNode.scala:551:17]\n .io_in_a_valid (anonIn_a_valid),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_opcode (anonIn_a_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_param (anonIn_a_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_size (anonIn_a_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_source (anonIn_a_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_address (anonIn_a_bits_address),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_mask (anonIn_a_bits_mask),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_data (anonIn_a_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_a_bits_corrupt (anonIn_a_bits_corrupt),\t// @[MixedNode.scala:551:17]\n .io_in_d_ready (anonIn_d_ready),\t// @[MixedNode.scala:551:17]\n .io_in_d_valid (anonIn_d_valid),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_opcode (anonIn_d_bits_opcode),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_param (anonIn_d_bits_param),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_size (anonIn_d_bits_size),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_source (anonIn_d_bits_source),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_sink (anonIn_d_bits_sink),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_denied (anonIn_d_bits_denied),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_data (anonIn_d_bits_data),\t// @[MixedNode.scala:551:17]\n .io_in_d_bits_corrupt (anonIn_d_bits_corrupt)\t// @[MixedNode.scala:551:17]\n );\t// @[Nodes.scala:27:25]\n assign auto_anon_in_a_ready = auto_anon_in_a_ready_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_valid = auto_anon_in_d_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_valid = auto_anon_out_a_valid_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0;\t// @[FIFOFixer.scala:50:9]\n assign auto_anon_out_d_ready = auto_anon_out_d_ready_0;\t// @[FIFOFixer.scala:50:9]\nendmodule"}}},{"rowIdx":35490,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o1_a32d32s6k1z4u : \n input clock : Clock \n input reset : Reset \n output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} \n\n\n wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate anonIn.d.bits.corrupt \n invalidate anonIn.d.bits.data \n invalidate anonIn.d.bits.denied \n invalidate anonIn.d.bits.sink \n invalidate anonIn.d.bits.source \n invalidate anonIn.d.bits.size \n invalidate anonIn.d.bits.param \n invalidate anonIn.d.bits.opcode \n invalidate anonIn.d.valid \n invalidate anonIn.d.ready \n invalidate anonIn.a.bits.corrupt \n invalidate anonIn.a.bits.data \n invalidate anonIn.a.bits.mask \n invalidate anonIn.a.bits.address \n invalidate anonIn.a.bits.source \n invalidate anonIn.a.bits.size \n invalidate anonIn.a.bits.param \n invalidate anonIn.a.bits.opcode \n invalidate anonIn.a.valid \n invalidate anonIn.a.ready \n wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate anonIn_1.d.bits.corrupt \n invalidate anonIn_1.d.bits.data \n invalidate anonIn_1.d.bits.denied \n invalidate anonIn_1.d.bits.sink \n invalidate anonIn_1.d.bits.source \n invalidate anonIn_1.d.bits.size \n invalidate anonIn_1.d.bits.param \n invalidate anonIn_1.d.bits.opcode \n invalidate anonIn_1.d.valid \n invalidate anonIn_1.d.ready \n invalidate anonIn_1.a.bits.corrupt \n invalidate anonIn_1.a.bits.data \n invalidate anonIn_1.a.bits.mask \n invalidate anonIn_1.a.bits.address \n invalidate anonIn_1.a.bits.source \n invalidate anonIn_1.a.bits.size \n invalidate anonIn_1.a.bits.param \n invalidate anonIn_1.a.bits.opcode \n invalidate anonIn_1.a.valid \n invalidate anonIn_1.a.ready \n inst monitor of TLMonitor \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, anonIn.d.bits.data \n connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink \n connect monitor.io.in.d.bits.source, anonIn.d.bits.source \n connect monitor.io.in.d.bits.size, anonIn.d.bits.size \n connect monitor.io.in.d.bits.param, anonIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode \n connect monitor.io.in.d.valid, anonIn.d.valid \n connect monitor.io.in.d.ready, anonIn.d.ready \n connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, anonIn.a.bits.data \n connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask \n connect monitor.io.in.a.bits.address, anonIn.a.bits.address \n connect monitor.io.in.a.bits.source, anonIn.a.bits.source \n connect monitor.io.in.a.bits.size, anonIn.a.bits.size \n connect monitor.io.in.a.bits.param, anonIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode \n connect monitor.io.in.a.valid, anonIn.a.valid \n connect monitor.io.in.a.ready, anonIn.a.ready \n inst monitor_1 of TLMonitor_1 \n connect monitor_1.clock, clock\n\n connect monitor_1.reset, reset\n\n connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt \n connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data \n connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied \n connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink \n connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source \n connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size \n connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param \n connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode \n connect monitor_1.io.in.d.valid, anonIn_1.d.valid \n connect monitor_1.io.in.d.ready, anonIn_1.d.ready \n connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data \n connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask \n connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address \n connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source \n connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size \n connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param \n connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode \n connect monitor_1.io.in.a.valid, anonIn_1.a.valid \n connect monitor_1.io.in.a.ready, anonIn_1.a.ready \n wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} \n invalidate anonOut.d.bits.corrupt \n invalidate anonOut.d.bits.data \n invalidate anonOut.d.bits.denied \n invalidate anonOut.d.bits.sink \n invalidate anonOut.d.bits.source \n invalidate anonOut.d.bits.size \n invalidate anonOut.d.bits.param \n invalidate anonOut.d.bits.opcode \n invalidate anonOut.d.valid \n invalidate anonOut.d.ready \n invalidate anonOut.a.bits.corrupt \n invalidate anonOut.a.bits.data \n invalidate anonOut.a.bits.mask \n invalidate anonOut.a.bits.address \n invalidate anonOut.a.bits.source \n invalidate anonOut.a.bits.size \n invalidate anonOut.a.bits.param \n invalidate anonOut.a.bits.opcode \n invalidate anonOut.a.valid \n invalidate anonOut.a.ready \n connect auto.anon_out, anonOut \n connect anonIn, auto.anon_in_0 \n connect anonIn_1, auto.anon_in_1 \n wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2] \n connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt \n connect in[0].a.bits.data, anonIn.a.bits.data \n connect in[0].a.bits.mask, anonIn.a.bits.mask \n connect in[0].a.bits.address, anonIn.a.bits.address \n connect in[0].a.bits.source, anonIn.a.bits.source \n connect in[0].a.bits.size, anonIn.a.bits.size \n connect in[0].a.bits.param, anonIn.a.bits.param \n connect in[0].a.bits.opcode, anonIn.a.bits.opcode \n connect in[0].a.valid, anonIn.a.valid \n connect anonIn.a.ready, in[0].a.ready \n node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0)) \n connect in[0].a.bits.source, _in_0_a_bits_source_T \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<6>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n invalidate _WIRE_1.bits.corrupt \n invalidate _WIRE_1.bits.data \n invalidate _WIRE_1.bits.mask \n invalidate _WIRE_1.bits.address \n invalidate _WIRE_1.bits.source \n invalidate _WIRE_1.bits.size \n invalidate _WIRE_1.bits.param \n invalidate _WIRE_1.bits.opcode \n invalidate _WIRE_1.valid \n invalidate _WIRE_1.ready \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.mask, UInt<4>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<5>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<2>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n invalidate _WIRE_3.bits.corrupt \n invalidate _WIRE_3.bits.data \n invalidate _WIRE_3.bits.mask \n invalidate _WIRE_3.bits.address \n invalidate _WIRE_3.bits.source \n invalidate _WIRE_3.bits.size \n invalidate _WIRE_3.bits.param \n invalidate _WIRE_3.bits.opcode \n invalidate _WIRE_3.valid \n invalidate _WIRE_3.ready \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<32>(0h0) \n connect _WIRE_4.bits.mask, UInt<4>(0h0) \n connect _WIRE_4.bits.address, UInt<32>(0h0) \n connect _WIRE_4.bits.source, UInt<6>(0h0) \n connect _WIRE_4.bits.size, UInt<4>(0h0) \n connect _WIRE_4.bits.param, UInt<2>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n connect _WIRE_5.ready, UInt<1>(0h1) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.mask, UInt<4>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<5>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<2>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n connect _WIRE_7.valid, UInt<1>(0h0) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<6>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n invalidate _WIRE_9.bits.corrupt \n invalidate _WIRE_9.bits.data \n invalidate _WIRE_9.bits.address \n invalidate _WIRE_9.bits.source \n invalidate _WIRE_9.bits.size \n invalidate _WIRE_9.bits.param \n invalidate _WIRE_9.bits.opcode \n invalidate _WIRE_9.valid \n invalidate _WIRE_9.ready \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<5>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n invalidate _WIRE_11.bits.corrupt \n invalidate _WIRE_11.bits.data \n invalidate _WIRE_11.bits.address \n invalidate _WIRE_11.bits.source \n invalidate _WIRE_11.bits.size \n invalidate _WIRE_11.bits.param \n invalidate _WIRE_11.bits.opcode \n invalidate _WIRE_11.valid \n invalidate _WIRE_11.ready \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<6>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n connect _WIRE_13.valid, UInt<1>(0h0) \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<32>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<5>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n connect _WIRE_15.ready, UInt<1>(0h1) \n connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt \n connect anonIn.d.bits.data, in[0].d.bits.data \n connect anonIn.d.bits.denied, in[0].d.bits.denied \n connect anonIn.d.bits.sink, in[0].d.bits.sink \n connect anonIn.d.bits.source, in[0].d.bits.source \n connect anonIn.d.bits.size, in[0].d.bits.size \n connect anonIn.d.bits.param, in[0].d.bits.param \n connect anonIn.d.bits.opcode, in[0].d.bits.opcode \n connect anonIn.d.valid, in[0].d.valid \n connect in[0].d.ready, anonIn.d.ready \n node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0) \n connect anonIn.d.bits.source, _anonIn_d_bits_source_T \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_16.bits.sink, UInt<1>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n invalidate _WIRE_17.bits.sink \n invalidate _WIRE_17.valid \n invalidate _WIRE_17.ready \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_18.bits.sink, UInt<1>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n invalidate _WIRE_19.bits.sink \n invalidate _WIRE_19.valid \n invalidate _WIRE_19.ready \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_20.bits.sink, UInt<1>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n connect _WIRE_21.valid, UInt<1>(0h0) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_22.bits.sink, UInt<1>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n connect _WIRE_23.ready, UInt<1>(0h1) \n connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect in[1].a.bits.data, anonIn_1.a.bits.data \n connect in[1].a.bits.mask, anonIn_1.a.bits.mask \n connect in[1].a.bits.address, anonIn_1.a.bits.address \n connect in[1].a.bits.source, anonIn_1.a.bits.source \n connect in[1].a.bits.size, anonIn_1.a.bits.size \n connect in[1].a.bits.param, anonIn_1.a.bits.param \n connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode \n connect in[1].a.valid, anonIn_1.a.valid \n connect anonIn_1.a.ready, in[1].a.ready \n node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20)) \n connect in[1].a.bits.source, _in_1_a_bits_source_T \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.mask, UInt<4>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<6>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<2>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n invalidate _WIRE_25.bits.corrupt \n invalidate _WIRE_25.bits.data \n invalidate _WIRE_25.bits.mask \n invalidate _WIRE_25.bits.address \n invalidate _WIRE_25.bits.source \n invalidate _WIRE_25.bits.size \n invalidate _WIRE_25.bits.param \n invalidate _WIRE_25.bits.opcode \n invalidate _WIRE_25.valid \n invalidate _WIRE_25.ready \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<32>(0h0) \n connect _WIRE_26.bits.mask, UInt<4>(0h0) \n connect _WIRE_26.bits.address, UInt<32>(0h0) \n connect _WIRE_26.bits.source, UInt<1>(0h0) \n connect _WIRE_26.bits.size, UInt<4>(0h0) \n connect _WIRE_26.bits.param, UInt<2>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n invalidate _WIRE_27.bits.corrupt \n invalidate _WIRE_27.bits.data \n invalidate _WIRE_27.bits.mask \n invalidate _WIRE_27.bits.address \n invalidate _WIRE_27.bits.source \n invalidate _WIRE_27.bits.size \n invalidate _WIRE_27.bits.param \n invalidate _WIRE_27.bits.opcode \n invalidate _WIRE_27.valid \n invalidate _WIRE_27.ready \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_28.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_28.bits.data, UInt<32>(0h0) \n connect _WIRE_28.bits.mask, UInt<4>(0h0) \n connect _WIRE_28.bits.address, UInt<32>(0h0) \n connect _WIRE_28.bits.source, UInt<6>(0h0) \n connect _WIRE_28.bits.size, UInt<4>(0h0) \n connect _WIRE_28.bits.param, UInt<2>(0h0) \n connect _WIRE_28.bits.opcode, UInt<3>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n connect _WIRE_29.ready, UInt<1>(0h1) \n wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_30.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_30.bits.data, UInt<32>(0h0) \n connect _WIRE_30.bits.mask, UInt<4>(0h0) \n connect _WIRE_30.bits.address, UInt<32>(0h0) \n connect _WIRE_30.bits.source, UInt<1>(0h0) \n connect _WIRE_30.bits.size, UInt<4>(0h0) \n connect _WIRE_30.bits.param, UInt<2>(0h0) \n connect _WIRE_30.bits.opcode, UInt<3>(0h0) \n connect _WIRE_30.valid, UInt<1>(0h0) \n connect _WIRE_30.ready, UInt<1>(0h0) \n wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_31.bits, _WIRE_30.bits \n connect _WIRE_31.valid, _WIRE_30.valid \n connect _WIRE_31.ready, _WIRE_30.ready \n connect _WIRE_31.valid, UInt<1>(0h0) \n wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_32.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_32.bits.data, UInt<32>(0h0) \n connect _WIRE_32.bits.address, UInt<32>(0h0) \n connect _WIRE_32.bits.source, UInt<6>(0h0) \n connect _WIRE_32.bits.size, UInt<4>(0h0) \n connect _WIRE_32.bits.param, UInt<3>(0h0) \n connect _WIRE_32.bits.opcode, UInt<3>(0h0) \n connect _WIRE_32.valid, UInt<1>(0h0) \n connect _WIRE_32.ready, UInt<1>(0h0) \n wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_33.bits, _WIRE_32.bits \n connect _WIRE_33.valid, _WIRE_32.valid \n connect _WIRE_33.ready, _WIRE_32.ready \n invalidate _WIRE_33.bits.corrupt \n invalidate _WIRE_33.bits.data \n invalidate _WIRE_33.bits.address \n invalidate _WIRE_33.bits.source \n invalidate _WIRE_33.bits.size \n invalidate _WIRE_33.bits.param \n invalidate _WIRE_33.bits.opcode \n invalidate _WIRE_33.valid \n invalidate _WIRE_33.ready \n wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_34.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_34.bits.data, UInt<32>(0h0) \n connect _WIRE_34.bits.address, UInt<32>(0h0) \n connect _WIRE_34.bits.source, UInt<1>(0h0) \n connect _WIRE_34.bits.size, UInt<4>(0h0) \n connect _WIRE_34.bits.param, UInt<3>(0h0) \n connect _WIRE_34.bits.opcode, UInt<3>(0h0) \n connect _WIRE_34.valid, UInt<1>(0h0) \n connect _WIRE_34.ready, UInt<1>(0h0) \n wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_35.bits, _WIRE_34.bits \n connect _WIRE_35.valid, _WIRE_34.valid \n connect _WIRE_35.ready, _WIRE_34.ready \n invalidate _WIRE_35.bits.corrupt \n invalidate _WIRE_35.bits.data \n invalidate _WIRE_35.bits.address \n invalidate _WIRE_35.bits.source \n invalidate _WIRE_35.bits.size \n invalidate _WIRE_35.bits.param \n invalidate _WIRE_35.bits.opcode \n invalidate _WIRE_35.valid \n invalidate _WIRE_35.ready \n wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_36.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_36.bits.data, UInt<32>(0h0) \n connect _WIRE_36.bits.address, UInt<32>(0h0) \n connect _WIRE_36.bits.source, UInt<6>(0h0) \n connect _WIRE_36.bits.size, UInt<4>(0h0) \n connect _WIRE_36.bits.param, UInt<3>(0h0) \n connect _WIRE_36.bits.opcode, UInt<3>(0h0) \n connect _WIRE_36.valid, UInt<1>(0h0) \n connect _WIRE_36.ready, UInt<1>(0h0) \n wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_37.bits, _WIRE_36.bits \n connect _WIRE_37.valid, _WIRE_36.valid \n connect _WIRE_37.ready, _WIRE_36.ready \n connect _WIRE_37.valid, UInt<1>(0h0) \n wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_38.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_38.bits.data, UInt<32>(0h0) \n connect _WIRE_38.bits.address, UInt<32>(0h0) \n connect _WIRE_38.bits.source, UInt<1>(0h0) \n connect _WIRE_38.bits.size, UInt<4>(0h0) \n connect _WIRE_38.bits.param, UInt<3>(0h0) \n connect _WIRE_38.bits.opcode, UInt<3>(0h0) \n connect _WIRE_38.valid, UInt<1>(0h0) \n connect _WIRE_38.ready, UInt<1>(0h0) \n wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_39.bits, _WIRE_38.bits \n connect _WIRE_39.valid, _WIRE_38.valid \n connect _WIRE_39.ready, _WIRE_38.ready \n connect _WIRE_39.ready, UInt<1>(0h1) \n connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt \n connect anonIn_1.d.bits.data, in[1].d.bits.data \n connect anonIn_1.d.bits.denied, in[1].d.bits.denied \n connect anonIn_1.d.bits.sink, in[1].d.bits.sink \n connect anonIn_1.d.bits.source, in[1].d.bits.source \n connect anonIn_1.d.bits.size, in[1].d.bits.size \n connect anonIn_1.d.bits.param, in[1].d.bits.param \n connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode \n connect anonIn_1.d.valid, in[1].d.valid \n connect in[1].d.ready, anonIn_1.d.ready \n connect anonIn_1.d.bits.source, UInt<1>(0h0) \n wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_40.bits.sink, UInt<1>(0h0) \n connect _WIRE_40.valid, UInt<1>(0h0) \n connect _WIRE_40.ready, UInt<1>(0h0) \n wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_41.bits, _WIRE_40.bits \n connect _WIRE_41.valid, _WIRE_40.valid \n connect _WIRE_41.ready, _WIRE_40.ready \n invalidate _WIRE_41.bits.sink \n invalidate _WIRE_41.valid \n invalidate _WIRE_41.ready \n wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_42.bits.sink, UInt<1>(0h0) \n connect _WIRE_42.valid, UInt<1>(0h0) \n connect _WIRE_42.ready, UInt<1>(0h0) \n wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_43.bits, _WIRE_42.bits \n connect _WIRE_43.valid, _WIRE_42.valid \n connect _WIRE_43.ready, _WIRE_42.ready \n invalidate _WIRE_43.bits.sink \n invalidate _WIRE_43.valid \n invalidate _WIRE_43.ready \n wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_44.bits.sink, UInt<1>(0h0) \n connect _WIRE_44.valid, UInt<1>(0h0) \n connect _WIRE_44.ready, UInt<1>(0h0) \n wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_45.bits, _WIRE_44.bits \n connect _WIRE_45.valid, _WIRE_44.valid \n connect _WIRE_45.ready, _WIRE_44.ready \n connect _WIRE_45.valid, UInt<1>(0h0) \n wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_46.bits.sink, UInt<1>(0h0) \n connect _WIRE_46.valid, UInt<1>(0h0) \n connect _WIRE_46.ready, UInt<1>(0h0) \n wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_47.bits, _WIRE_46.bits \n connect _WIRE_47.valid, _WIRE_46.valid \n connect _WIRE_47.ready, _WIRE_46.ready \n connect _WIRE_47.ready, UInt<1>(0h1) \n wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[1] \n connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt \n connect anonOut.a.bits.data, out[0].a.bits.data \n connect anonOut.a.bits.mask, out[0].a.bits.mask \n connect anonOut.a.bits.address, out[0].a.bits.address \n connect anonOut.a.bits.source, out[0].a.bits.source \n connect anonOut.a.bits.size, out[0].a.bits.size \n connect anonOut.a.bits.param, out[0].a.bits.param \n connect anonOut.a.bits.opcode, out[0].a.bits.opcode \n connect anonOut.a.valid, out[0].a.valid \n connect out[0].a.ready, anonOut.a.ready \n wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_48.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_48.bits.data, UInt<32>(0h0) \n connect _WIRE_48.bits.mask, UInt<4>(0h0) \n connect _WIRE_48.bits.address, UInt<32>(0h0) \n connect _WIRE_48.bits.source, UInt<6>(0h0) \n connect _WIRE_48.bits.size, UInt<4>(0h0) \n connect _WIRE_48.bits.param, UInt<2>(0h0) \n connect _WIRE_48.bits.opcode, UInt<3>(0h0) \n connect _WIRE_48.valid, UInt<1>(0h0) \n connect _WIRE_48.ready, UInt<1>(0h0) \n wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_49.bits, _WIRE_48.bits \n connect _WIRE_49.valid, _WIRE_48.valid \n connect _WIRE_49.ready, _WIRE_48.ready \n invalidate _WIRE_49.bits.corrupt \n invalidate _WIRE_49.bits.data \n invalidate _WIRE_49.bits.mask \n invalidate _WIRE_49.bits.address \n invalidate _WIRE_49.bits.source \n invalidate _WIRE_49.bits.size \n invalidate _WIRE_49.bits.param \n invalidate _WIRE_49.bits.opcode \n invalidate _WIRE_49.valid \n invalidate _WIRE_49.ready \n wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_50.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_50.bits.data, UInt<32>(0h0) \n connect _WIRE_50.bits.mask, UInt<4>(0h0) \n connect _WIRE_50.bits.address, UInt<32>(0h0) \n connect _WIRE_50.bits.source, UInt<6>(0h0) \n connect _WIRE_50.bits.size, UInt<4>(0h0) \n connect _WIRE_50.bits.param, UInt<2>(0h0) \n connect _WIRE_50.bits.opcode, UInt<3>(0h0) \n connect _WIRE_50.valid, UInt<1>(0h0) \n connect _WIRE_50.ready, UInt<1>(0h0) \n wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_51.bits, _WIRE_50.bits \n connect _WIRE_51.valid, _WIRE_50.valid \n connect _WIRE_51.ready, _WIRE_50.ready \n invalidate _WIRE_51.bits.corrupt \n invalidate _WIRE_51.bits.data \n invalidate _WIRE_51.bits.mask \n invalidate _WIRE_51.bits.address \n invalidate _WIRE_51.bits.source \n invalidate _WIRE_51.bits.size \n invalidate _WIRE_51.bits.param \n invalidate _WIRE_51.bits.opcode \n invalidate _WIRE_51.valid \n invalidate _WIRE_51.ready \n wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_52.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_52.bits.data, UInt<32>(0h0) \n connect _WIRE_52.bits.mask, UInt<4>(0h0) \n connect _WIRE_52.bits.address, UInt<32>(0h0) \n connect _WIRE_52.bits.source, UInt<6>(0h0) \n connect _WIRE_52.bits.size, UInt<4>(0h0) \n connect _WIRE_52.bits.param, UInt<2>(0h0) \n connect _WIRE_52.bits.opcode, UInt<3>(0h0) \n connect _WIRE_52.valid, UInt<1>(0h0) \n connect _WIRE_52.ready, UInt<1>(0h0) \n wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_53.bits, _WIRE_52.bits \n connect _WIRE_53.valid, _WIRE_52.valid \n connect _WIRE_53.ready, _WIRE_52.ready \n connect _WIRE_53.valid, UInt<1>(0h0) \n wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_54.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_54.bits.data, UInt<32>(0h0) \n connect _WIRE_54.bits.mask, UInt<4>(0h0) \n connect _WIRE_54.bits.address, UInt<32>(0h0) \n connect _WIRE_54.bits.source, UInt<6>(0h0) \n connect _WIRE_54.bits.size, UInt<4>(0h0) \n connect _WIRE_54.bits.param, UInt<2>(0h0) \n connect _WIRE_54.bits.opcode, UInt<3>(0h0) \n connect _WIRE_54.valid, UInt<1>(0h0) \n connect _WIRE_54.ready, UInt<1>(0h0) \n wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_55.bits, _WIRE_54.bits \n connect _WIRE_55.valid, _WIRE_54.valid \n connect _WIRE_55.ready, _WIRE_54.ready \n connect _WIRE_55.ready, UInt<1>(0h1) \n wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_56.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_56.bits.data, UInt<32>(0h0) \n connect _WIRE_56.bits.address, UInt<32>(0h0) \n connect _WIRE_56.bits.source, UInt<6>(0h0) \n connect _WIRE_56.bits.size, UInt<4>(0h0) \n connect _WIRE_56.bits.param, UInt<3>(0h0) \n connect _WIRE_56.bits.opcode, UInt<3>(0h0) \n connect _WIRE_56.valid, UInt<1>(0h0) \n connect _WIRE_56.ready, UInt<1>(0h0) \n wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_57.bits, _WIRE_56.bits \n connect _WIRE_57.valid, _WIRE_56.valid \n connect _WIRE_57.ready, _WIRE_56.ready \n invalidate _WIRE_57.bits.corrupt \n invalidate _WIRE_57.bits.data \n invalidate _WIRE_57.bits.address \n invalidate _WIRE_57.bits.source \n invalidate _WIRE_57.bits.size \n invalidate _WIRE_57.bits.param \n invalidate _WIRE_57.bits.opcode \n invalidate _WIRE_57.valid \n invalidate _WIRE_57.ready \n wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_58.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_58.bits.data, UInt<32>(0h0) \n connect _WIRE_58.bits.address, UInt<32>(0h0) \n connect _WIRE_58.bits.source, UInt<6>(0h0) \n connect _WIRE_58.bits.size, UInt<4>(0h0) \n connect _WIRE_58.bits.param, UInt<3>(0h0) \n connect _WIRE_58.bits.opcode, UInt<3>(0h0) \n connect _WIRE_58.valid, UInt<1>(0h0) \n connect _WIRE_58.ready, UInt<1>(0h0) \n wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_59.bits, _WIRE_58.bits \n connect _WIRE_59.valid, _WIRE_58.valid \n connect _WIRE_59.ready, _WIRE_58.ready \n invalidate _WIRE_59.bits.corrupt \n invalidate _WIRE_59.bits.data \n invalidate _WIRE_59.bits.address \n invalidate _WIRE_59.bits.source \n invalidate _WIRE_59.bits.size \n invalidate _WIRE_59.bits.param \n invalidate _WIRE_59.bits.opcode \n invalidate _WIRE_59.valid \n invalidate _WIRE_59.ready \n wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_60.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_60.bits.data, UInt<32>(0h0) \n connect _WIRE_60.bits.address, UInt<32>(0h0) \n connect _WIRE_60.bits.source, UInt<6>(0h0) \n connect _WIRE_60.bits.size, UInt<4>(0h0) \n connect _WIRE_60.bits.param, UInt<3>(0h0) \n connect _WIRE_60.bits.opcode, UInt<3>(0h0) \n connect _WIRE_60.valid, UInt<1>(0h0) \n connect _WIRE_60.ready, UInt<1>(0h0) \n wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_61.bits, _WIRE_60.bits \n connect _WIRE_61.valid, _WIRE_60.valid \n connect _WIRE_61.ready, _WIRE_60.ready \n connect _WIRE_61.ready, UInt<1>(0h1) \n wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_62.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_62.bits.data, UInt<32>(0h0) \n connect _WIRE_62.bits.address, UInt<32>(0h0) \n connect _WIRE_62.bits.source, UInt<6>(0h0) \n connect _WIRE_62.bits.size, UInt<4>(0h0) \n connect _WIRE_62.bits.param, UInt<3>(0h0) \n connect _WIRE_62.bits.opcode, UInt<3>(0h0) \n connect _WIRE_62.valid, UInt<1>(0h0) \n connect _WIRE_62.ready, UInt<1>(0h0) \n wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_63.bits, _WIRE_62.bits \n connect _WIRE_63.valid, _WIRE_62.valid \n connect _WIRE_63.ready, _WIRE_62.ready \n connect _WIRE_63.valid, UInt<1>(0h0) \n connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt \n connect out[0].d.bits.data, anonOut.d.bits.data \n connect out[0].d.bits.denied, anonOut.d.bits.denied \n connect out[0].d.bits.sink, anonOut.d.bits.sink \n connect out[0].d.bits.source, anonOut.d.bits.source \n connect out[0].d.bits.size, anonOut.d.bits.size \n connect out[0].d.bits.param, anonOut.d.bits.param \n connect out[0].d.bits.opcode, anonOut.d.bits.opcode \n connect out[0].d.valid, anonOut.d.valid \n connect anonOut.d.ready, out[0].d.ready \n node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) \n connect out[0].d.bits.sink, _out_0_d_bits_sink_T \n wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_64.bits.sink, UInt<1>(0h0) \n connect _WIRE_64.valid, UInt<1>(0h0) \n connect _WIRE_64.ready, UInt<1>(0h0) \n wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_65.bits, _WIRE_64.bits \n connect _WIRE_65.valid, _WIRE_64.valid \n connect _WIRE_65.ready, _WIRE_64.ready \n invalidate _WIRE_65.bits.sink \n invalidate _WIRE_65.valid \n invalidate _WIRE_65.ready \n wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_66.bits.sink, UInt<1>(0h0) \n connect _WIRE_66.valid, UInt<1>(0h0) \n connect _WIRE_66.ready, UInt<1>(0h0) \n wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_67.bits, _WIRE_66.bits \n connect _WIRE_67.valid, _WIRE_66.valid \n connect _WIRE_67.ready, _WIRE_66.ready \n invalidate _WIRE_67.bits.sink \n invalidate _WIRE_67.valid \n invalidate _WIRE_67.ready \n wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_68.bits.sink, UInt<1>(0h0) \n connect _WIRE_68.valid, UInt<1>(0h0) \n connect _WIRE_68.ready, UInt<1>(0h0) \n wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_69.bits, _WIRE_68.bits \n connect _WIRE_69.valid, _WIRE_68.valid \n connect _WIRE_69.ready, _WIRE_68.ready \n connect _WIRE_69.ready, UInt<1>(0h1) \n wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_70.bits.sink, UInt<1>(0h0) \n connect _WIRE_70.valid, UInt<1>(0h0) \n connect _WIRE_70.ready, UInt<1>(0h0) \n wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_71.bits, _WIRE_70.bits \n connect _WIRE_71.valid, _WIRE_70.valid \n connect _WIRE_71.ready, _WIRE_70.ready \n connect _WIRE_71.valid, UInt<1>(0h0) \n wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _addressC_WIRE.bits.data, UInt<32>(0h0) \n connect _addressC_WIRE.bits.address, UInt<32>(0h0) \n connect _addressC_WIRE.bits.source, UInt<6>(0h0) \n connect _addressC_WIRE.bits.size, UInt<4>(0h0) \n connect _addressC_WIRE.bits.param, UInt<3>(0h0) \n connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) \n connect _addressC_WIRE.valid, UInt<1>(0h0) \n connect _addressC_WIRE.ready, UInt<1>(0h0) \n wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _addressC_WIRE_1.bits, _addressC_WIRE.bits \n connect _addressC_WIRE_1.valid, _addressC_WIRE.valid \n connect _addressC_WIRE_1.ready, _addressC_WIRE.ready \n wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _addressC_WIRE_2.bits.data, UInt<32>(0h0) \n connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) \n connect _addressC_WIRE_2.bits.source, UInt<6>(0h0) \n connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) \n connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) \n connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _addressC_WIRE_2.valid, UInt<1>(0h0) \n connect _addressC_WIRE_2.ready, UInt<1>(0h0) \n wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits \n connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid \n connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready \n node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_1 = cvt(_requestAIO_T) \n node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_3 = asSInt(_requestAIO_T_2) \n node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) \n node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) \n node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_6 = cvt(_requestAIO_T_5) \n node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_8 = asSInt(_requestAIO_T_7) \n node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) \n node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) \n node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_1 = cvt(_requestCIO_T) \n node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_3 = asSInt(_requestCIO_T_2) \n node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) \n node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) \n node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_6 = cvt(_requestCIO_T_5) \n node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_8 = asSInt(_requestCIO_T_7) \n node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) \n node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) \n wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _requestBOI_WIRE.bits.data, UInt<32>(0h0) \n connect _requestBOI_WIRE.bits.mask, UInt<4>(0h0) \n connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) \n connect _requestBOI_WIRE.bits.source, UInt<6>(0h0) \n connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) \n connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) \n connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _requestBOI_WIRE.valid, UInt<1>(0h0) \n connect _requestBOI_WIRE.ready, UInt<1>(0h0) \n wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits \n connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid \n connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready \n node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0)) \n node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0) \n node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5) \n node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0)) \n node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) \n node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) \n node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f)) \n node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) \n wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _requestBOI_WIRE_2.bits.data, UInt<32>(0h0) \n connect _requestBOI_WIRE_2.bits.mask, UInt<4>(0h0) \n connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _requestBOI_WIRE_2.bits.source, UInt<6>(0h0) \n connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) \n connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) \n connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) \n wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits \n connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid \n connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready \n node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<6>(0h20)) \n node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0)) \n node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0) \n node _requestDOI_T = shr(out[0].d.bits.source, 5) \n node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0)) \n node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) \n node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) \n node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f)) \n node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) \n node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<6>(0h20)) \n wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0) \n connect _requestEIO_WIRE.valid, UInt<1>(0h0) \n connect _requestEIO_WIRE.ready, UInt<1>(0h0) \n wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits \n connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid \n connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready \n wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0) \n connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) \n connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) \n wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits \n connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid \n connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready \n node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) \n node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) \n node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) \n node beatsAI_decode = shr(_beatsAI_decode_T_2, 2) \n node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) \n node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) \n node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) \n node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) \n node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) \n node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) \n node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 2) \n node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) \n node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) \n node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) \n wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _beatsBO_WIRE.bits.data, UInt<32>(0h0) \n connect _beatsBO_WIRE.bits.mask, UInt<4>(0h0) \n connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) \n connect _beatsBO_WIRE.bits.source, UInt<6>(0h0) \n connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) \n connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) \n connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) \n connect _beatsBO_WIRE.valid, UInt<1>(0h0) \n connect _beatsBO_WIRE.ready, UInt<1>(0h0) \n wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits \n connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid \n connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready \n node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) \n node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) \n node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) \n node beatsBO_decode = shr(_beatsBO_decode_T_2, 2) \n node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) \n node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) \n node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) \n wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _beatsCI_WIRE.bits.data, UInt<32>(0h0) \n connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) \n connect _beatsCI_WIRE.bits.source, UInt<6>(0h0) \n connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) \n connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) \n connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _beatsCI_WIRE.valid, UInt<1>(0h0) \n connect _beatsCI_WIRE.ready, UInt<1>(0h0) \n wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits \n connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid \n connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready \n node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) \n node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) \n node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) \n node beatsCI_decode = shr(_beatsCI_decode_T_2, 2) \n node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) \n node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) \n wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _beatsCI_WIRE_2.bits.data, UInt<32>(0h0) \n connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _beatsCI_WIRE_2.bits.source, UInt<6>(0h0) \n connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) \n connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) \n connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) \n wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits \n connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid \n connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready \n node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) \n node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) \n node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) \n node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 2) \n node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) \n node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) \n node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) \n node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) \n node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) \n node beatsDO_decode = shr(_beatsDO_decode_T_2, 2) \n node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) \n node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) \n wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0) \n connect _beatsEI_WIRE.valid, UInt<1>(0h0) \n connect _beatsEI_WIRE.ready, UInt<1>(0h0) \n wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits \n connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid \n connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready \n wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0) \n connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) \n connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) \n wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits \n connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid \n connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready \n wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered[0].bits, in[0].a.bits \n node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) \n connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 \n connect in[0].a.ready, portsAOI_filtered[0].ready \n wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered_1[0].bits, in[1].a.bits \n node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) \n connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 \n connect in[1].a.ready, portsAOI_filtered_1[0].ready \n wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _portsBIO_WIRE.bits.data, UInt<32>(0h0) \n connect _portsBIO_WIRE.bits.mask, UInt<4>(0h0) \n connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) \n connect _portsBIO_WIRE.bits.source, UInt<6>(0h0) \n connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) \n connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) \n connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) \n connect _portsBIO_WIRE.valid, UInt<1>(0h0) \n connect _portsBIO_WIRE.ready, UInt<1>(0h0) \n wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits \n connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid \n connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready \n wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2] \n connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits \n node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) \n node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) \n connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 \n connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits \n node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) \n node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) \n connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 \n node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) \n wire _portsBIO_WIRE_2 : UInt<1> \n connect _portsBIO_WIRE_2, _portsBIO_T_2 \n connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 \n wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _portsCOI_WIRE.bits.data, UInt<32>(0h0) \n connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) \n connect _portsCOI_WIRE.bits.source, UInt<6>(0h0) \n connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) \n connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) \n connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _portsCOI_WIRE.valid, UInt<1>(0h0) \n connect _portsCOI_WIRE.ready, UInt<1>(0h0) \n wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits \n connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid \n connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready \n wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits \n node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) \n connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 \n connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready \n wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _portsCOI_WIRE_2.bits.data, UInt<32>(0h0) \n connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _portsCOI_WIRE_2.bits.source, UInt<6>(0h0) \n connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) \n connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) \n connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) \n wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits \n connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid \n connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready \n wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits \n node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) \n connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 \n connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready \n wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2] \n connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[0].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[0].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[0].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[0].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) \n node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) \n connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 \n connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[1].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[1].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[1].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[1].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) \n node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) \n connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 \n node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) \n wire _portsDIO_out_0_d_ready_WIRE : UInt<1> \n connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 \n connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE \n wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0) \n connect _portsEOI_WIRE.valid, UInt<1>(0h0) \n connect _portsEOI_WIRE.ready, UInt<1>(0h0) \n wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits \n connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid \n connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready \n wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] \n connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits \n node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) \n connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 \n connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready \n wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0) \n connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) \n connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) \n wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits \n connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid \n connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready \n wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1] \n connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits \n node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) \n connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 \n connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready \n regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) \n node idle = eq(beatsLeft, UInt<1>(0h0)) \n node latch = and(idle, out[0].a.ready) \n node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) \n node readys_valid = bits(_readys_T, 1, 0) \n node _readys_T_1 = eq(readys_valid, _readys_T) \n node _readys_T_2 = asUInt(reset) \n node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) \n when _readys_T_3 : \n node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) \n when _readys_T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:22 assert (valid === valids)\\n\") : readys_printf \n assert(clock, _readys_T_1, UInt<1>(0h1), \"\") : readys_assert \n regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) \n node _readys_filter_T = not(readys_mask) \n node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) \n node readys_filter = cat(_readys_filter_T_1, readys_valid) \n node _readys_unready_T = shr(readys_filter, 1) \n node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) \n node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) \n node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) \n node _readys_unready_T_4 = shl(readys_mask, 2) \n node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) \n node _readys_readys_T = shr(readys_unready, 2) \n node _readys_readys_T_1 = bits(readys_unready, 1, 0) \n node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) \n node readys_readys = not(_readys_readys_T_2) \n node _readys_T_5 = orr(readys_valid) \n node _readys_T_6 = and(latch, _readys_T_5) \n when _readys_T_6 : \n node _readys_mask_T = and(readys_readys, readys_valid) \n node _readys_mask_T_1 = shl(_readys_mask_T, 1) \n node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) \n node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) \n node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) \n connect readys_mask, _readys_mask_T_4 \n node _readys_T_7 = bits(readys_readys, 1, 0) \n node _readys_T_8 = bits(_readys_T_7, 0, 0) \n node _readys_T_9 = bits(_readys_T_7, 1, 1) \n wire readys : UInt<1>[2] \n connect readys[0], _readys_T_8 \n connect readys[1], _readys_T_9 \n node _winner_T = and(readys[0], portsAOI_filtered[0].valid) \n node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) \n wire winner : UInt<1>[2] \n connect winner[0], _winner_T \n connect winner[1], _winner_T_1 \n node prefixOR_1 = or(UInt<1>(0h0), winner[0]) \n node _prefixOR_T = or(prefixOR_1, winner[1]) \n node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1 = eq(winner[0], UInt<1>(0h0)) \n node _T_2 = or(_T, _T_1) \n node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) \n node _T_4 = eq(winner[1], UInt<1>(0h0)) \n node _T_5 = or(_T_3, _T_4) \n node _T_6 = and(_T_2, _T_5) \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n node _T_9 = eq(_T_6, UInt<1>(0h0)) \n when _T_9 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\\n\") : printf \n assert(clock, _T_6, UInt<1>(0h1), \"\") : assert \n node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _T_11 = eq(_T_10, UInt<1>(0h0)) \n node _T_12 = or(winner[0], winner[1]) \n node _T_13 = or(_T_11, _T_12) \n node _T_14 = asUInt(reset) \n node _T_15 = eq(_T_14, UInt<1>(0h0)) \n when _T_15 : \n node _T_16 = eq(_T_13, UInt<1>(0h0)) \n when _T_16 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\\n\") : printf_1 \n assert(clock, _T_13, UInt<1>(0h1), \"\") : assert_1 \n node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) \n node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) \n node initBeats = or(maskedBeats_0, maskedBeats_1) \n node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) \n node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) \n node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) \n node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) \n connect beatsLeft, _beatsLeft_T_3 \n wire _state_WIRE : UInt<1>[2] \n connect _state_WIRE[0], UInt<1>(0h0) \n connect _state_WIRE[1], UInt<1>(0h0) \n regreset state : UInt<1>[2], clock, reset, _state_WIRE \n node muxState = mux(idle, winner, state) \n connect state, muxState \n node allowed = mux(idle, readys, state) \n node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) \n connect portsAOI_filtered[0].ready, _filtered_0_ready_T \n node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) \n connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 \n node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) \n wire _out_0_a_valid_WIRE : UInt<1> \n connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 \n node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) \n connect out[0].a.valid, _out_0_a_valid_T_4 \n wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>} \n node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) \n wire _out_0_a_bits_WIRE_1 : UInt<1> \n connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 \n connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 \n node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) \n wire _out_0_a_bits_WIRE_2 : UInt<32> \n connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 \n connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 \n node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) \n wire _out_0_a_bits_WIRE_3 : UInt<4> \n connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 \n connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 \n wire _out_0_a_bits_WIRE_4 : { } \n connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 \n wire _out_0_a_bits_WIRE_5 : { } \n connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 \n node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) \n wire _out_0_a_bits_WIRE_6 : UInt<32> \n connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 \n connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 \n node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) \n wire _out_0_a_bits_WIRE_7 : UInt<6> \n connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 \n connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 \n node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) \n wire _out_0_a_bits_WIRE_8 : UInt<4> \n connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 \n connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 \n node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) \n wire _out_0_a_bits_WIRE_9 : UInt<3> \n connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 \n connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 \n node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) \n wire _out_0_a_bits_WIRE_10 : UInt<3> \n connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 \n connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 \n connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt \n connect out[0].a.bits.data, _out_0_a_bits_WIRE.data \n connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask \n connect out[0].a.bits.address, _out_0_a_bits_WIRE.address \n connect out[0].a.bits.source, _out_0_a_bits_WIRE.source \n connect out[0].a.bits.size, _out_0_a_bits_WIRE.size \n connect out[0].a.bits.param, _out_0_a_bits_WIRE.param \n connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode \n wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_72.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_72.bits.data, UInt<32>(0h0) \n connect _WIRE_72.bits.address, UInt<32>(0h0) \n connect _WIRE_72.bits.source, UInt<6>(0h0) \n connect _WIRE_72.bits.size, UInt<4>(0h0) \n connect _WIRE_72.bits.param, UInt<3>(0h0) \n connect _WIRE_72.bits.opcode, UInt<3>(0h0) \n connect _WIRE_72.valid, UInt<1>(0h0) \n connect _WIRE_72.ready, UInt<1>(0h0) \n wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_73.bits, _WIRE_72.bits \n connect _WIRE_73.valid, _WIRE_72.valid \n connect _WIRE_73.ready, _WIRE_72.ready \n invalidate _WIRE_73.bits.corrupt \n invalidate _WIRE_73.bits.data \n invalidate _WIRE_73.bits.address \n invalidate _WIRE_73.bits.source \n invalidate _WIRE_73.bits.size \n invalidate _WIRE_73.bits.param \n invalidate _WIRE_73.bits.opcode \n wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_74.bits.sink, UInt<1>(0h0) \n connect _WIRE_74.valid, UInt<1>(0h0) \n connect _WIRE_74.ready, UInt<1>(0h0) \n wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_75.bits, _WIRE_74.bits \n connect _WIRE_75.valid, _WIRE_74.valid \n connect _WIRE_75.ready, _WIRE_74.ready \n invalidate _WIRE_75.bits.sink \n connect portsCOI_filtered[0].ready, UInt<1>(0h0) \n connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) \n connect portsEOI_filtered[0].ready, UInt<1>(0h0) \n connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) \n wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_76.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_76.bits.data, UInt<32>(0h0) \n connect _WIRE_76.bits.mask, UInt<4>(0h0) \n connect _WIRE_76.bits.address, UInt<32>(0h0) \n connect _WIRE_76.bits.source, UInt<6>(0h0) \n connect _WIRE_76.bits.size, UInt<4>(0h0) \n connect _WIRE_76.bits.param, UInt<2>(0h0) \n connect _WIRE_76.bits.opcode, UInt<3>(0h0) \n connect _WIRE_76.valid, UInt<1>(0h0) \n connect _WIRE_76.ready, UInt<1>(0h0) \n wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_77.bits, _WIRE_76.bits \n connect _WIRE_77.valid, _WIRE_76.valid \n connect _WIRE_77.ready, _WIRE_76.ready \n invalidate _WIRE_77.bits.corrupt \n invalidate _WIRE_77.bits.data \n invalidate _WIRE_77.bits.mask \n invalidate _WIRE_77.bits.address \n invalidate _WIRE_77.bits.source \n invalidate _WIRE_77.bits.size \n invalidate _WIRE_77.bits.param \n invalidate _WIRE_77.bits.opcode \n connect in[0].d, portsDIO_filtered[0] \n connect portsBIO_filtered[0].ready, UInt<1>(0h0) \n wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_78.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_78.bits.data, UInt<32>(0h0) \n connect _WIRE_78.bits.mask, UInt<4>(0h0) \n connect _WIRE_78.bits.address, UInt<32>(0h0) \n connect _WIRE_78.bits.source, UInt<6>(0h0) \n connect _WIRE_78.bits.size, UInt<4>(0h0) \n connect _WIRE_78.bits.param, UInt<2>(0h0) \n connect _WIRE_78.bits.opcode, UInt<3>(0h0) \n connect _WIRE_78.valid, UInt<1>(0h0) \n connect _WIRE_78.ready, UInt<1>(0h0) \n wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_79.bits, _WIRE_78.bits \n connect _WIRE_79.valid, _WIRE_78.valid \n connect _WIRE_79.ready, _WIRE_78.ready \n invalidate _WIRE_79.bits.corrupt \n invalidate _WIRE_79.bits.data \n invalidate _WIRE_79.bits.mask \n invalidate _WIRE_79.bits.address \n invalidate _WIRE_79.bits.source \n invalidate _WIRE_79.bits.size \n invalidate _WIRE_79.bits.param \n invalidate _WIRE_79.bits.opcode \n connect in[1].d, portsDIO_filtered[1] \n connect portsBIO_filtered[1].ready, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLXbar_sbus_i2_o1_a32d32s6k1z4u(\t// @[Xbar.scala:74:9]\n input clock,\t// @[Xbar.scala:74:9]\n input reset,\t// @[Xbar.scala:74:9]\n output auto_anon_in_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_in_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_anon_in_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_anon_in_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_in_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_anon_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_anon_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire out_0_d_bits_sink;\t// @[Xbar.scala:216:19]\n wire [5:0] in_1_a_bits_source;\t// @[Xbar.scala:159:18]\n wire [5:0] in_0_a_bits_source;\t// @[Xbar.scala:159:18]\n wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire _readys_T_2 = reset;\t// @[Arbiter.scala:22:12]\n wire auto_anon_in_1_d_bits_source = 1'h0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_bits_source = 1'h0;\t// @[MixedNode.scala:551:17]\n wire _addressC_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _requestBOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _requestBOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire requestBOI_0_1 = 1'h0;\t// @[Parameters.scala:46:9]\n wire _requestEIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_2_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_3_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsBO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_opdata_T = 1'h0;\t// @[Edges.scala:97:37]\n wire _beatsCI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire beatsCI_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _beatsCI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire beatsCI_opdata_1 = 1'h0;\t// @[Edges.scala:102:36]\n wire _beatsEI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_2_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_3_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsBIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _portsBIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _portsBIO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire portsBIO_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsBIO_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsBIO_filtered_1_valid_T = 1'h0;\t// @[Xbar.scala:355:54]\n wire _portsBIO_filtered_1_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsBIO_T = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_T_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_WIRE_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsCOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire portsCOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsCOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsCOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire portsCOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsCOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsEOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_1_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire portsEOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_0_bits_sink = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsEOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_2_bits_sink = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_3_bits_sink = 1'h0;\t// @[Bundles.scala:267:61]\n wire portsEOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_1_0_bits_sink = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _state_WIRE_0 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _state_WIRE_1 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _requestAIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_0_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestAIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_1_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestCIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_0_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestCIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_1_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestBOI_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestBOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestBOI_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestBOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestBOI_0_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire _requestDOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestDOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire beatsBO_opdata = 1'h1;\t// @[Edges.scala:97:28]\n wire _portsAOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsAOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsBIO_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsEOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsEOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire [31:0] _addressC_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _addressC_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _addressC_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _addressC_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _requestCIO_T = 32'h0;\t// @[Parameters.scala:137:31]\n wire [31:0] _requestCIO_T_5 = 32'h0;\t// @[Parameters.scala:137:31]\n wire [31:0] _requestBOI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _beatsBO_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _beatsBO_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _beatsCI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _portsBIO_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _portsBIO_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] portsBIO_filtered_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsBIO_filtered_0_bits_data = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsBIO_filtered_1_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsBIO_filtered_1_bits_data = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] _portsCOI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] portsCOI_filtered_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsCOI_filtered_0_bits_data = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0;\t// @[Xbar.scala:352:24]\n wire [5:0] _addressC_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _addressC_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] _addressC_WIRE_2_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _addressC_WIRE_3_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] _requestBOI_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:264:74]\n wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:264:61]\n wire [5:0] _requestBOI_uncommonBits_T = 6'h0;\t// @[Parameters.scala:52:29]\n wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0;\t// @[Bundles.scala:264:74]\n wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0;\t// @[Bundles.scala:264:61]\n wire [5:0] _beatsBO_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:264:74]\n wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:264:61]\n wire [5:0] _beatsCI_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] _beatsCI_WIRE_2_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _beatsCI_WIRE_3_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] _portsBIO_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:264:74]\n wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:264:61]\n wire [5:0] portsBIO_filtered_0_bits_source = 6'h0;\t// @[Xbar.scala:352:24]\n wire [5:0] portsBIO_filtered_1_bits_source = 6'h0;\t// @[Xbar.scala:352:24]\n wire [5:0] _portsCOI_WIRE_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] portsCOI_filtered_0_bits_source = 6'h0;\t// @[Xbar.scala:352:24]\n wire [5:0] _portsCOI_WIRE_2_bits_source = 6'h0;\t// @[Bundles.scala:265:74]\n wire [5:0] _portsCOI_WIRE_3_bits_source = 6'h0;\t// @[Bundles.scala:265:61]\n wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _addressC_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _addressC_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _addressC_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _addressC_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _requestBOI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _beatsBO_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _beatsCI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _portsBIO_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] portsBIO_filtered_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] portsBIO_filtered_1_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsCOI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] portsCOI_filtered_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _addressC_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] _requestBOI_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _beatsBO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _portsBIO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] portsBIO_filtered_0_bits_param = 2'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] portsBIO_filtered_1_bits_param = 2'h0;\t// @[Xbar.scala:352:24]\n wire [9:0] beatsBO_decode = 10'h0;\t// @[Edges.scala:220:59]\n wire [9:0] beatsBO_0 = 10'h0;\t// @[Edges.scala:221:14]\n wire [9:0] beatsCI_decode = 10'h0;\t// @[Edges.scala:220:59]\n wire [9:0] beatsCI_0 = 10'h0;\t// @[Edges.scala:221:14]\n wire [9:0] beatsCI_decode_1 = 10'h0;\t// @[Edges.scala:220:59]\n wire [9:0] beatsCI_1 = 10'h0;\t// @[Edges.scala:221:14]\n wire [11:0] _beatsBO_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsCI_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsCI_decode_T_5 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsBO_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [11:0] _beatsCI_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [11:0] _beatsCI_decode_T_4 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _beatsBO_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [26:0] _beatsCI_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [26:0] _beatsCI_decode_T_3 = 27'hFFF;\t// @[package.scala:243:71]\n wire [4:0] requestBOI_uncommonBits = 5'h0;\t// @[Parameters.scala:52:56]\n wire [32:0] _requestAIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_1 = 33'h0;\t// @[Parameters.scala:137:41]\n wire [32:0] _requestCIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_6 = 33'h0;\t// @[Parameters.scala:137:41]\n wire [32:0] _requestCIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire anonIn_1_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_1_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_1_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [31:0] anonIn_1_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_valid = auto_anon_in_0_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_ready = auto_anon_in_0_d_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [4:0] anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [31:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_ready = auto_anon_out_a_ready_0;\t// @[Xbar.scala:74:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [5:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_d_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_1_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_1_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_0_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [4:0] auto_anon_in_0_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [5:0] auto_anon_out_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_ready_0;\t// @[Xbar.scala:74:9]\n wire in_0_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_a_ready_0 = anonIn_a_ready;\t// @[Xbar.scala:74:9]\n wire in_0_a_valid = anonIn_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_param = anonIn_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_0_a_bits_size = anonIn_a_bits_size;\t// @[Xbar.scala:159:18]\n wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source;\t// @[Xbar.scala:166:55]\n wire [31:0] in_0_a_bits_address = anonIn_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [31:0] in_0_a_bits_data = anonIn_a_bits_data;\t// @[Xbar.scala:159:18]\n wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire in_0_d_ready = anonIn_d_ready;\t// @[Xbar.scala:159:18]\n wire in_0_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_valid_0 = anonIn_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [4:0] _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [31:0] in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire in_1_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready;\t// @[Xbar.scala:74:9]\n wire in_1_a_valid = anonIn_1_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size;\t// @[Xbar.scala:159:18]\n wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data;\t// @[Xbar.scala:159:18]\n wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire in_1_d_ready = anonIn_1_d_ready;\t// @[Xbar.scala:159:18]\n wire in_1_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [31:0] in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire out_0_a_ready = anonOut_a_ready;\t// @[Xbar.scala:216:19]\n wire out_0_a_valid;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_valid_0 = anonOut_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [5:0] out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [3:0] out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [31:0] out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data;\t// @[Xbar.scala:74:9]\n wire out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_d_ready_0 = anonOut_d_ready;\t// @[Xbar.scala:74:9]\n wire out_0_d_valid = anonOut_d_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_d_bits_param = anonOut_d_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] out_0_d_bits_size = anonOut_d_bits_size;\t// @[Xbar.scala:216:19]\n wire [5:0] out_0_d_bits_source = anonOut_d_bits_source;\t// @[Xbar.scala:216:19]\n wire _out_0_d_bits_sink_T = anonOut_d_bits_sink;\t// @[Xbar.scala:251:53]\n wire out_0_d_bits_denied = anonOut_d_bits_denied;\t// @[Xbar.scala:216:19]\n wire [31:0] out_0_d_bits_data = anonOut_d_bits_data;\t// @[Xbar.scala:216:19]\n wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire portsAOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_a_ready = in_0_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestAIO_T = in_0_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_ready = in_0_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_d_valid = in_0_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_opcode = in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_param = in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_size = in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [5:0] portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:352:24]\n wire portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_sink = in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_denied = in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [31:0] portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_data = in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_1_a_ready = in_1_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [5:0] _in_1_a_bits_source_T;\t// @[Xbar.scala:166:55]\n wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestAIO_T_5 = in_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_1_ready = in_1_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_1_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_valid = in_1_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_param = in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_size = in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [5:0] portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:352:24]\n wire portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_sink = in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_denied = in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [31:0] portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_data = in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire [5:0] in_0_d_bits_source;\t// @[Xbar.scala:159:18]\n wire [5:0] in_1_d_bits_source;\t// @[Xbar.scala:159:18]\n assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T};\t// @[Xbar.scala:159:18, :166:{29,55}]\n assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0];\t// @[Xbar.scala:156:69, :159:18]\n assign anonIn_d_bits_source = _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign _in_1_a_bits_source_T = {5'h10, anonIn_1_a_bits_source};\t// @[Xbar.scala:166:55]\n assign in_1_a_bits_source = _in_1_a_bits_source_T;\t// @[Xbar.scala:159:18, :166:55]\n wire _out_0_a_valid_T_4;\t// @[Arbiter.scala:96:24]\n assign anonOut_a_valid = out_0_a_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_opcode = out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_param;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_param = out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] _out_0_a_bits_WIRE_size;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_size = out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n wire [5:0] _out_0_a_bits_WIRE_source;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_source = out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n wire [31:0] _out_0_a_bits_WIRE_address;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_address = out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n wire [3:0] _out_0_a_bits_WIRE_mask;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_mask = out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n wire [31:0] _out_0_a_bits_WIRE_data;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_data = out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n wire _out_0_a_bits_WIRE_corrupt;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n assign anonOut_d_ready = out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_d_bits_sink = _out_0_d_bits_sink_T;\t// @[Xbar.scala:216:19, :251:53]\n wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0];\t// @[Parameters.scala:52:{29,56}]\n wire _requestDOI_T = out_0_d_bits_source[5];\t// @[Xbar.scala:216:19]\n wire _requestDOI_T_1 = ~_requestDOI_T;\t// @[Parameters.scala:54:{10,32}]\n wire _requestDOI_T_3 = _requestDOI_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire requestDOI_0_0 = _requestDOI_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _portsDIO_filtered_0_valid_T = requestDOI_0_0;\t// @[Xbar.scala:355:54]\n wire requestDOI_0_1 = out_0_d_bits_source == 6'h20;\t// @[Xbar.scala:216:19]\n wire _portsDIO_filtered_1_valid_T = requestDOI_0_1;\t// @[Xbar.scala:355:54]\n wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2];\t// @[package.scala:243:46]\n wire _beatsAI_opdata_T = in_0_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire beatsAI_opdata = ~_beatsAI_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2];\t// @[package.scala:243:46]\n wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2];\t// @[package.scala:243:46]\n wire beatsDO_opdata = out_0_d_bits_opcode[0];\t// @[Xbar.scala:216:19]\n wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n wire _filtered_0_ready_T;\t// @[Arbiter.scala:94:31]\n assign in_0_a_ready = portsAOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _filtered_0_ready_T_1;\t// @[Arbiter.scala:94:31]\n assign in_1_a_ready = portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_0_d_valid = portsDIO_filtered_0_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_param = portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_size = portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_source = portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_data = portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_1_d_valid = portsDIO_filtered_1_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_param = portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_size = portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_source = portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_data = portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready;\t// @[Mux.scala:30:73]\n wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready;\t// @[Mux.scala:30:73]\n wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1;\t// @[Mux.scala:30:73]\n assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2;\t// @[Mux.scala:30:73]\n assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n reg [9:0] beatsLeft;\t// @[Arbiter.scala:60:30]\n wire idle = beatsLeft == 10'h0;\t// @[Arbiter.scala:60:30, :61:28]\n wire latch = idle & out_0_a_ready;\t// @[Xbar.scala:216:19]\n wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid};\t// @[Xbar.scala:352:24]\n wire [1:0] readys_valid = _readys_T;\t// @[Arbiter.scala:21:23, :68:51]\n wire _readys_T_1 = readys_valid == _readys_T;\t// @[Arbiter.scala:21:23, :22:19, :68:51]\n wire _readys_T_3 = ~_readys_T_2;\t// @[Arbiter.scala:22:12]\n wire _readys_T_4 = ~_readys_T_1;\t// @[Arbiter.scala:22:{12,19}]\n reg [1:0] readys_mask;\t// @[Arbiter.scala:23:23]\n wire [1:0] _readys_filter_T = ~readys_mask;\t// @[Arbiter.scala:23:23, :24:30]\n wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T;\t// @[Arbiter.scala:21:23, :24:{28,30}]\n wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid};\t// @[Arbiter.scala:21:23, :24:{21,28}]\n wire [2:0] _readys_unready_T = readys_filter[3:1];\t// @[package.scala:262:48]\n wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T};\t// @[package.scala:262:{43,48}]\n wire [3:0] _readys_unready_T_2 = _readys_unready_T_1;\t// @[package.scala:262:43, :263:17]\n wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1];\t// @[package.scala:263:17]\n wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0};\t// @[Arbiter.scala:23:23, :25:66]\n wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4;\t// @[Arbiter.scala:25:{52,58,66}]\n wire [1:0] _readys_readys_T = readys_unready[3:2];\t// @[Arbiter.scala:25:58, :26:29]\n wire [1:0] _readys_readys_T_1 = readys_unready[1:0];\t// @[Arbiter.scala:25:58, :26:48]\n wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1;\t// @[Arbiter.scala:26:{29,39,48}]\n wire [1:0] readys_readys = ~_readys_readys_T_2;\t// @[Arbiter.scala:26:{18,39}]\n wire [1:0] _readys_T_7 = readys_readys;\t// @[Arbiter.scala:26:18, :30:11]\n wire _readys_T_5 = |readys_valid;\t// @[Arbiter.scala:21:23, :27:27]\n wire _readys_T_6 = latch & _readys_T_5;\t// @[Arbiter.scala:27:{18,27}, :62:24]\n wire [1:0] _readys_mask_T = readys_readys & readys_valid;\t// @[Arbiter.scala:21:23, :26:18, :28:29]\n wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0};\t// @[package.scala:253:48]\n wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0];\t// @[package.scala:253:{48,53}]\n wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2;\t// @[package.scala:253:{43,53}]\n wire [1:0] _readys_mask_T_4 = _readys_mask_T_3;\t// @[package.scala:253:43, :254:17]\n wire _readys_T_8 = _readys_T_7[0];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_0 = _readys_T_8;\t// @[Arbiter.scala:68:{27,76}]\n wire _readys_T_9 = _readys_T_7[1];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_1 = _readys_T_9;\t// @[Arbiter.scala:68:{27,76}]\n wire _winner_T = readys_0 & portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_0 = _winner_T;\t// @[Arbiter.scala:71:{27,69}]\n wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_1 = _winner_T_1;\t// @[Arbiter.scala:71:{27,69}]\n wire prefixOR_1 = winner_0;\t// @[Arbiter.scala:71:27, :76:48]\n wire _prefixOR_T = prefixOR_1 | winner_1;\t// @[Arbiter.scala:71:27, :76:48]\n wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]"}}},{"rowIdx":35491,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_192 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_209 \n connect io_out_source_valid_0.clock, clock\n\n connect io_out_source_valid_0.reset, reset\n\n connect io_out_source_valid_0.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_source_valid_0.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_192(\t// @[AsyncQueue.scala:58:7]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in = 1'h1;\t// @[ShiftReg.scala:45:23]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_209 io_out_source_valid_0 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":35492,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_67 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) \n node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0) \n node _source_ok_T = shr(io.in.a.bits.source, 5) \n node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) \n node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) \n node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) \n node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13)) \n node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T_5 \n node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) \n node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) \n node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) \n node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) \n node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) \n node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) \n node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) \n node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) \n node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) \n node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) \n node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) \n node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) \n node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) \n node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_eq_4 = and(mask_sub_2_2, mask_nbit) \n node _mask_acc_T_4 = and(mask_size, mask_eq_4) \n node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) \n node mask_eq_5 = and(mask_sub_2_2, mask_bit) \n node _mask_acc_T_5 = and(mask_size, mask_eq_5) \n node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) \n node mask_eq_6 = and(mask_sub_3_2, mask_nbit) \n node _mask_acc_T_6 = and(mask_size, mask_eq_6) \n node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) \n node mask_eq_7 = and(mask_sub_3_2, mask_bit) \n node _mask_acc_T_7 = and(mask_size, mask_eq_7) \n node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) \n node mask_lo_lo = cat(mask_acc_1, mask_acc) \n node mask_lo_hi = cat(mask_acc_3, mask_acc_2) \n node mask_lo = cat(mask_lo_hi, mask_lo_lo) \n node mask_hi_lo = cat(mask_acc_5, mask_acc_4) \n node mask_hi_hi = cat(mask_acc_7, mask_acc_6) \n node mask_hi = cat(mask_hi_hi, mask_hi_lo) \n node mask = cat(mask_hi, mask_lo) \n node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits = bits(_uncommonBits_T, 4, 0) \n node _T_4 = shr(io.in.a.bits.source, 5) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = leq(UInt<1>(0h0), uncommonBits) \n node _T_7 = and(_T_5, _T_6) \n node _T_8 = leq(uncommonBits, UInt<5>(0h13)) \n node _T_9 = and(_T_7, _T_8) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_12 = cvt(_T_11) \n node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) \n node _T_14 = asSInt(_T_13) \n node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) \n node _T_16 = or(_T_10, _T_15) \n node _T_17 = asUInt(reset) \n node _T_18 = eq(_T_17, UInt<1>(0h0)) \n when _T_18 : \n node _T_19 = eq(_T_16, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_16, UInt<1>(0h1), \"\") : assert_1 \n node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_20 : \n node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_23 = and(_T_21, _T_22) \n node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0) \n node _T_24 = shr(io.in.a.bits.source, 5) \n node _T_25 = eq(_T_24, UInt<1>(0h0)) \n node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) \n node _T_27 = and(_T_25, _T_26) \n node _T_28 = leq(uncommonBits_1, UInt<5>(0h13)) \n node _T_29 = and(_T_27, _T_28) \n node _T_30 = and(_T_23, _T_29) \n node _T_31 = or(UInt<1>(0h0), _T_30) \n node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_34 = cvt(_T_33) \n node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) \n node _T_36 = asSInt(_T_35) \n node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) \n node _T_38 = and(_T_32, _T_37) \n node _T_39 = or(UInt<1>(0h0), _T_38) \n node _T_40 = and(_T_31, _T_39) \n node _T_41 = asUInt(reset) \n node _T_42 = eq(_T_41, UInt<1>(0h0)) \n when _T_42 : \n node _T_43 = eq(_T_40, UInt<1>(0h0)) \n when _T_43 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_40, UInt<1>(0h1), \"\") : assert_2 \n node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_46 = and(_T_44, _T_45) \n node _T_47 = or(UInt<1>(0h0), _T_46) \n node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_49 = cvt(_T_48) \n node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) \n node _T_51 = asSInt(_T_50) \n node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) \n node _T_53 = and(_T_47, _T_52) \n node _T_54 = or(UInt<1>(0h0), _T_53) \n node _T_55 = and(UInt<1>(0h0), _T_54) \n node _T_56 = asUInt(reset) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n when _T_57 : \n node _T_58 = eq(_T_55, UInt<1>(0h0)) \n when _T_58 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_55, UInt<1>(0h1), \"\") : assert_3 \n node _T_59 = asUInt(reset) \n node _T_60 = eq(_T_59, UInt<1>(0h0)) \n when _T_60 : \n node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_61 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_63 = asUInt(reset) \n node _T_64 = eq(_T_63, UInt<1>(0h0)) \n when _T_64 : \n node _T_65 = eq(_T_62, UInt<1>(0h0)) \n when _T_65 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_62, UInt<1>(0h1), \"\") : assert_5 \n node _T_66 = asUInt(reset) \n node _T_67 = eq(_T_66, UInt<1>(0h0)) \n when _T_67 : \n node _T_68 = eq(is_aligned, UInt<1>(0h0)) \n when _T_68 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_70 = asUInt(reset) \n node _T_71 = eq(_T_70, UInt<1>(0h0)) \n when _T_71 : \n node _T_72 = eq(_T_69, UInt<1>(0h0)) \n when _T_72 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_69, UInt<1>(0h1), \"\") : assert_7 \n node _T_73 = not(io.in.a.bits.mask) \n node _T_74 = eq(_T_73, UInt<1>(0h0)) \n node _T_75 = asUInt(reset) \n node _T_76 = eq(_T_75, UInt<1>(0h0)) \n when _T_76 : \n node _T_77 = eq(_T_74, UInt<1>(0h0)) \n when _T_77 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_74, UInt<1>(0h1), \"\") : assert_8 \n node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_79 = asUInt(reset) \n node _T_80 = eq(_T_79, UInt<1>(0h0)) \n when _T_80 : \n node _T_81 = eq(_T_78, UInt<1>(0h0)) \n when _T_81 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_78, UInt<1>(0h1), \"\") : assert_9 \n node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_82 : \n node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_85 = and(_T_83, _T_84) \n node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0) \n node _T_86 = shr(io.in.a.bits.source, 5) \n node _T_87 = eq(_T_86, UInt<1>(0h0)) \n node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) \n node _T_89 = and(_T_87, _T_88) \n node _T_90 = leq(uncommonBits_2, UInt<5>(0h13)) \n node _T_91 = and(_T_89, _T_90) \n node _T_92 = and(_T_85, _T_91) \n node _T_93 = or(UInt<1>(0h0), _T_92) \n node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_96 = cvt(_T_95) \n node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) \n node _T_98 = asSInt(_T_97) \n node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) \n node _T_100 = and(_T_94, _T_99) \n node _T_101 = or(UInt<1>(0h0), _T_100) \n node _T_102 = and(_T_93, _T_101) \n node _T_103 = asUInt(reset) \n node _T_104 = eq(_T_103, UInt<1>(0h0)) \n when _T_104 : \n node _T_105 = eq(_T_102, UInt<1>(0h0)) \n when _T_105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_102, UInt<1>(0h1), \"\") : assert_10 \n node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_108 = and(_T_106, _T_107) \n node _T_109 = or(UInt<1>(0h0), _T_108) \n node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_111 = cvt(_T_110) \n node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) \n node _T_113 = asSInt(_T_112) \n node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) \n node _T_115 = and(_T_109, _T_114) \n node _T_116 = or(UInt<1>(0h0), _T_115) \n node _T_117 = and(UInt<1>(0h0), _T_116) \n node _T_118 = asUInt(reset) \n node _T_119 = eq(_T_118, UInt<1>(0h0)) \n when _T_119 : \n node _T_120 = eq(_T_117, UInt<1>(0h0)) \n when _T_120 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_117, UInt<1>(0h1), \"\") : assert_11 \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) \n node _T_125 = asUInt(reset) \n node _T_126 = eq(_T_125, UInt<1>(0h0)) \n when _T_126 : \n node _T_127 = eq(_T_124, UInt<1>(0h0)) \n when _T_127 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_124, UInt<1>(0h1), \"\") : assert_13 \n node _T_128 = asUInt(reset) \n node _T_129 = eq(_T_128, UInt<1>(0h0)) \n when _T_129 : \n node _T_130 = eq(is_aligned, UInt<1>(0h0)) \n when _T_130 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_132 = asUInt(reset) \n node _T_133 = eq(_T_132, UInt<1>(0h0)) \n when _T_133 : \n node _T_134 = eq(_T_131, UInt<1>(0h0)) \n when _T_134 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_131, UInt<1>(0h1), \"\") : assert_15 \n node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_136 = asUInt(reset) \n node _T_137 = eq(_T_136, UInt<1>(0h0)) \n when _T_137 : \n node _T_138 = eq(_T_135, UInt<1>(0h0)) \n when _T_138 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_135, UInt<1>(0h1), \"\") : assert_16 \n node _T_139 = not(io.in.a.bits.mask) \n node _T_140 = eq(_T_139, UInt<1>(0h0)) \n node _T_141 = asUInt(reset) \n node _T_142 = eq(_T_141, UInt<1>(0h0)) \n when _T_142 : \n node _T_143 = eq(_T_140, UInt<1>(0h0)) \n when _T_143 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_140, UInt<1>(0h1), \"\") : assert_17 \n node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_145 = asUInt(reset) \n node _T_146 = eq(_T_145, UInt<1>(0h0)) \n when _T_146 : \n node _T_147 = eq(_T_144, UInt<1>(0h0)) \n when _T_147 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_144, UInt<1>(0h1), \"\") : assert_18 \n node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_148 : \n node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_151 = and(_T_149, _T_150) \n node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0) \n node _T_152 = shr(io.in.a.bits.source, 5) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) \n node _T_155 = and(_T_153, _T_154) \n node _T_156 = leq(uncommonBits_3, UInt<5>(0h13)) \n node _T_157 = and(_T_155, _T_156) \n node _T_158 = and(_T_151, _T_157) \n node _T_159 = or(UInt<1>(0h0), _T_158) \n node _T_160 = asUInt(reset) \n node _T_161 = eq(_T_160, UInt<1>(0h0)) \n when _T_161 : \n node _T_162 = eq(_T_159, UInt<1>(0h0)) \n when _T_162 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_159, UInt<1>(0h1), \"\") : assert_19 \n node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_165 = and(_T_163, _T_164) \n node _T_166 = or(UInt<1>(0h0), _T_165) \n node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_168 = cvt(_T_167) \n node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) \n node _T_170 = asSInt(_T_169) \n node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) \n node _T_172 = and(_T_166, _T_171) \n node _T_173 = or(UInt<1>(0h0), _T_172) \n node _T_174 = asUInt(reset) \n node _T_175 = eq(_T_174, UInt<1>(0h0)) \n when _T_175 : \n node _T_176 = eq(_T_173, UInt<1>(0h0)) \n when _T_176 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_173, UInt<1>(0h1), \"\") : assert_20 \n node _T_177 = asUInt(reset) \n node _T_178 = eq(_T_177, UInt<1>(0h0)) \n when _T_178 : \n node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_179 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_180 = asUInt(reset) \n node _T_181 = eq(_T_180, UInt<1>(0h0)) \n when _T_181 : \n node _T_182 = eq(is_aligned, UInt<1>(0h0)) \n when _T_182 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_184 = asUInt(reset) \n node _T_185 = eq(_T_184, UInt<1>(0h0)) \n when _T_185 : \n node _T_186 = eq(_T_183, UInt<1>(0h0)) \n when _T_186 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_183, UInt<1>(0h1), \"\") : assert_23 \n node _T_187 = eq(io.in.a.bits.mask, mask) \n node _T_188 = asUInt(reset) \n node _T_189 = eq(_T_188, UInt<1>(0h0)) \n when _T_189 : \n node _T_190 = eq(_T_187, UInt<1>(0h0)) \n when _T_190 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_187, UInt<1>(0h1), \"\") : assert_24 \n node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_192 = asUInt(reset) \n node _T_193 = eq(_T_192, UInt<1>(0h0)) \n when _T_193 : \n node _T_194 = eq(_T_191, UInt<1>(0h0)) \n when _T_194 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_191, UInt<1>(0h1), \"\") : assert_25 \n node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_195 : \n node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_198 = and(_T_196, _T_197) \n node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0) \n node _T_199 = shr(io.in.a.bits.source, 5) \n node _T_200 = eq(_T_199, UInt<1>(0h0)) \n node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) \n node _T_202 = and(_T_200, _T_201) \n node _T_203 = leq(uncommonBits_4, UInt<5>(0h13)) \n node _T_204 = and(_T_202, _T_203) \n node _T_205 = and(_T_198, _T_204) \n node _T_206 = or(UInt<1>(0h0), _T_205) \n node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_209 = and(_T_207, _T_208) \n node _T_210 = or(UInt<1>(0h0), _T_209) \n node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_212 = cvt(_T_211) \n node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) \n node _T_214 = asSInt(_T_213) \n node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) \n node _T_216 = and(_T_210, _T_215) \n node _T_217 = or(UInt<1>(0h0), _T_216) \n node _T_218 = and(_T_206, _T_217) \n node _T_219 = asUInt(reset) \n node _T_220 = eq(_T_219, UInt<1>(0h0)) \n when _T_220 : \n node _T_221 = eq(_T_218, UInt<1>(0h0)) \n when _T_221 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_218, UInt<1>(0h1), \"\") : assert_26 \n node _T_222 = asUInt(reset) \n node _T_223 = eq(_T_222, UInt<1>(0h0)) \n when _T_223 : \n node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_224 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_225 = asUInt(reset) \n node _T_226 = eq(_T_225, UInt<1>(0h0)) \n when _T_226 : \n node _T_227 = eq(is_aligned, UInt<1>(0h0)) \n when _T_227 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_229 = asUInt(reset) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n when _T_230 : \n node _T_231 = eq(_T_228, UInt<1>(0h0)) \n when _T_231 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_228, UInt<1>(0h1), \"\") : assert_29 \n node _T_232 = eq(io.in.a.bits.mask, mask) \n node _T_233 = asUInt(reset) \n node _T_234 = eq(_T_233, UInt<1>(0h0)) \n when _T_234 : \n node _T_235 = eq(_T_232, UInt<1>(0h0)) \n when _T_235 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_232, UInt<1>(0h1), \"\") : assert_30 \n node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_236 : \n node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_239 = and(_T_237, _T_238) \n node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0) \n node _T_240 = shr(io.in.a.bits.source, 5) \n node _T_241 = eq(_T_240, UInt<1>(0h0)) \n node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) \n node _T_243 = and(_T_241, _T_242) \n node _T_244 = leq(uncommonBits_5, UInt<5>(0h13)) \n node _T_245 = and(_T_243, _T_244) \n node _T_246 = and(_T_239, _T_245) \n node _T_247 = or(UInt<1>(0h0), _T_246) \n node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) \n node _T_250 = and(_T_248, _T_249) \n node _T_251 = or(UInt<1>(0h0), _T_250) \n node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_253 = cvt(_T_252) \n node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000))) \n node _T_255 = asSInt(_T_254) \n node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) \n node _T_257 = and(_T_251, _T_256) \n node _T_258 = or(UInt<1>(0h0), _T_257) \n node _T_259 = and(_T_247, _T_258) \n node _T_260 = asUInt(reset) \n node _T_261 = eq(_T_260, UInt<1>(0h0)) \n when _T_261 : \n node _T_262 = eq(_T_259, UInt<1>(0h0)) \n when _T_262 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_259, UInt<1>(0h1), \"\") : assert_31 \n node _T_263 = asUInt(reset) \n node _T_264 = eq(_T_263, UInt<1>(0h0)) \n when _T_264 : \n node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_265 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_266 = asUInt(reset) \n node _T_267 = eq(_T_266, UInt<1>(0h0)) \n when _T_267 : \n node _T_268 = eq(is_aligned, UInt<1>(0h0)) \n when _T_268 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_270 = asUInt(reset) \n node _T_271 = eq(_T_270, UInt<1>(0h0)) \n when _T_271 : \n node _T_272 = eq(_T_269, UInt<1>(0h0)) \n when _T_272 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_269, UInt<1>(0h1), \"\") : assert_34 \n node _T_273 = not(mask) \n node _T_274 = and(io.in.a.bits.mask, _T_273) \n node _T_275 = eq(_T_274, UInt<1>(0h0)) \n node _T_276 = asUInt(reset) \n node _T_277 = eq(_T_276, UInt<1>(0h0)) \n when _T_277 : \n node _T_278 = eq(_T_275, UInt<1>(0h0)) \n when _T_278 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_275, UInt<1>(0h1), \"\") : assert_35 \n node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_279 : \n node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_282 = and(_T_280, _T_281) \n node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0) \n node _T_283 = shr(io.in.a.bits.source, 5) \n node _T_284 = eq(_T_283, UInt<1>(0h0)) \n node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) \n node _T_286 = and(_T_284, _T_285) \n node _T_287 = leq(uncommonBits_6, UInt<5>(0h13)) \n node _T_288 = and(_T_286, _T_287) \n node _T_289 = and(_T_282, _T_288) \n node _T_290 = or(UInt<1>(0h0), _T_289) \n node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_293 = cvt(_T_292) \n node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000))) \n node _T_295 = asSInt(_T_294) \n node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) \n node _T_297 = and(_T_291, _T_296) \n node _T_298 = or(UInt<1>(0h0), _T_297) \n node _T_299 = and(_T_290, _T_298) \n node _T_300 = asUInt(reset) \n node _T_301 = eq(_T_300, UInt<1>(0h0)) \n when _T_301 : \n node _T_302 = eq(_T_299, UInt<1>(0h0)) \n when _T_302 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_299, UInt<1>(0h1), \"\") : assert_36 \n node _T_303 = asUInt(reset) \n node _T_304 = eq(_T_303, UInt<1>(0h0)) \n when _T_304 : \n node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_305 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_306 = asUInt(reset) \n node _T_307 = eq(_T_306, UInt<1>(0h0)) \n when _T_307 : \n node _T_308 = eq(is_aligned, UInt<1>(0h0)) \n when _T_308 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_310 = asUInt(reset) \n node _T_311 = eq(_T_310, UInt<1>(0h0)) \n when _T_311 : \n node _T_312 = eq(_T_309, UInt<1>(0h0)) \n when _T_312 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_309, UInt<1>(0h1), \"\") : assert_39 \n node _T_313 = eq(io.in.a.bits.mask, mask) \n node _T_314 = asUInt(reset) \n node _T_315 = eq(_T_314, UInt<1>(0h0)) \n when _T_315 : \n node _T_316 = eq(_T_313, UInt<1>(0h0)) \n when _T_316 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_313, UInt<1>(0h1), \"\") : assert_40 \n node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_317 : \n node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_320 = and(_T_318, _T_319) \n node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0) \n node _T_321 = shr(io.in.a.bits.source, 5) \n node _T_322 = eq(_T_321, UInt<1>(0h0)) \n node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) \n node _T_324 = and(_T_322, _T_323) \n node _T_325 = leq(uncommonBits_7, UInt<5>(0h13)) \n node _T_326 = and(_T_324, _T_325) \n node _T_327 = and(_T_320, _T_326) \n node _T_328 = or(UInt<1>(0h0), _T_327) \n node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_331 = cvt(_T_330) \n node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) \n node _T_333 = asSInt(_T_332) \n node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) \n node _T_335 = and(_T_329, _T_334) \n node _T_336 = or(UInt<1>(0h0), _T_335) \n node _T_337 = and(_T_328, _T_336) \n node _T_338 = asUInt(reset) \n node _T_339 = eq(_T_338, UInt<1>(0h0)) \n when _T_339 : \n node _T_340 = eq(_T_337, UInt<1>(0h0)) \n when _T_340 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_337, UInt<1>(0h1), \"\") : assert_41 \n node _T_341 = asUInt(reset) \n node _T_342 = eq(_T_341, UInt<1>(0h0)) \n when _T_342 : \n node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_343 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_344 = asUInt(reset) \n node _T_345 = eq(_T_344, UInt<1>(0h0)) \n when _T_345 : \n node _T_346 = eq(is_aligned, UInt<1>(0h0)) \n when _T_346 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_348 = asUInt(reset) \n node _T_349 = eq(_T_348, UInt<1>(0h0)) \n when _T_349 : \n node _T_350 = eq(_T_347, UInt<1>(0h0)) \n when _T_350 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_347, UInt<1>(0h1), \"\") : assert_44 \n node _T_351 = eq(io.in.a.bits.mask, mask) \n node _T_352 = asUInt(reset) \n node _T_353 = eq(_T_352, UInt<1>(0h0)) \n when _T_353 : \n node _T_354 = eq(_T_351, UInt<1>(0h0)) \n when _T_354 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_351, UInt<1>(0h1), \"\") : assert_45 \n node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_355 : \n node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_358 = and(_T_356, _T_357) \n node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0)) \n node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0) \n node _T_359 = shr(io.in.a.bits.source, 5) \n node _T_360 = eq(_T_359, UInt<1>(0h0)) \n node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) \n node _T_362 = and(_T_360, _T_361) \n node _T_363 = leq(uncommonBits_8, UInt<5>(0h13)) \n node _T_364 = and(_T_362, _T_363) \n node _T_365 = and(_T_358, _T_364) \n node _T_366 = or(UInt<1>(0h0), _T_365) \n node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) \n node _T_369 = cvt(_T_368) \n node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000))) \n node _T_371 = asSInt(_T_370) \n node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) \n node _T_373 = and(_T_367, _T_372) \n node _T_374 = or(UInt<1>(0h0), _T_373) \n node _T_375 = and(_T_366, _T_374) \n node _T_376 = asUInt(reset) \n node _T_377 = eq(_T_376, UInt<1>(0h0)) \n when _T_377 : \n node _T_378 = eq(_T_375, UInt<1>(0h0)) \n when _T_378 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_375, UInt<1>(0h1), \"\") : assert_46 \n node _T_379 = asUInt(reset) \n node _T_380 = eq(_T_379, UInt<1>(0h0)) \n when _T_380 : \n node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_381 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_382 = asUInt(reset) \n node _T_383 = eq(_T_382, UInt<1>(0h0)) \n when _T_383 : \n node _T_384 = eq(is_aligned, UInt<1>(0h0)) \n when _T_384 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_386 = asUInt(reset) \n node _T_387 = eq(_T_386, UInt<1>(0h0)) \n when _T_387 : \n node _T_388 = eq(_T_385, UInt<1>(0h0)) \n when _T_388 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_385, UInt<1>(0h1), \"\") : assert_49 \n node _T_389 = eq(io.in.a.bits.mask, mask) \n node _T_390 = asUInt(reset) \n node _T_391 = eq(_T_390, UInt<1>(0h0)) \n when _T_391 : \n node _T_392 = eq(_T_389, UInt<1>(0h0)) \n when _T_392 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_389, UInt<1>(0h1), \"\") : assert_50 \n node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_394 = asUInt(reset) \n node _T_395 = eq(_T_394, UInt<1>(0h0)) \n when _T_395 : \n node _T_396 = eq(_T_393, UInt<1>(0h0)) \n when _T_396 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_393, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_398 = asUInt(reset) \n node _T_399 = eq(_T_398, UInt<1>(0h0)) \n when _T_399 : \n node _T_400 = eq(_T_397, UInt<1>(0h0)) \n when _T_400 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_397, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0)) \n node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0) \n node _source_ok_T_6 = shr(io.in.d.bits.source, 5) \n node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) \n node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) \n node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) \n node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13)) \n node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_11 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) \n node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_401 : \n node _T_402 = asUInt(reset) \n node _T_403 = eq(_T_402, UInt<1>(0h0)) \n when _T_403 : \n node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_404 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_406 = asUInt(reset) \n node _T_407 = eq(_T_406, UInt<1>(0h0)) \n when _T_407 : \n node _T_408 = eq(_T_405, UInt<1>(0h0)) \n when _T_408 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_405, UInt<1>(0h1), \"\") : assert_54 \n node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_410 = asUInt(reset) \n node _T_411 = eq(_T_410, UInt<1>(0h0)) \n when _T_411 : \n node _T_412 = eq(_T_409, UInt<1>(0h0)) \n when _T_412 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_409, UInt<1>(0h1), \"\") : assert_55 \n node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_414 = asUInt(reset) \n node _T_415 = eq(_T_414, UInt<1>(0h0)) \n when _T_415 : \n node _T_416 = eq(_T_413, UInt<1>(0h0)) \n when _T_416 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_413, UInt<1>(0h1), \"\") : assert_56 \n node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_418 = asUInt(reset) \n node _T_419 = eq(_T_418, UInt<1>(0h0)) \n when _T_419 : \n node _T_420 = eq(_T_417, UInt<1>(0h0)) \n when _T_420 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_417, UInt<1>(0h1), \"\") : assert_57 \n node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_421 : \n node _T_422 = asUInt(reset) \n node _T_423 = eq(_T_422, UInt<1>(0h0)) \n when _T_423 : \n node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_424 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_425 = asUInt(reset) \n node _T_426 = eq(_T_425, UInt<1>(0h0)) \n when _T_426 : \n node _T_427 = eq(sink_ok, UInt<1>(0h0)) \n when _T_427 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_429 = asUInt(reset) \n node _T_430 = eq(_T_429, UInt<1>(0h0)) \n when _T_430 : \n node _T_431 = eq(_T_428, UInt<1>(0h0)) \n when _T_431 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_428, UInt<1>(0h1), \"\") : assert_60 \n node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_433 = asUInt(reset) \n node _T_434 = eq(_T_433, UInt<1>(0h0)) \n when _T_434 : \n node _T_435 = eq(_T_432, UInt<1>(0h0)) \n when _T_435 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_432, UInt<1>(0h1), \"\") : assert_61 \n node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_437 = asUInt(reset) \n node _T_438 = eq(_T_437, UInt<1>(0h0)) \n when _T_438 : \n node _T_439 = eq(_T_436, UInt<1>(0h0)) \n when _T_439 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_436, UInt<1>(0h1), \"\") : assert_62 \n node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_441 = asUInt(reset) \n node _T_442 = eq(_T_441, UInt<1>(0h0)) \n when _T_442 : \n node _T_443 = eq(_T_440, UInt<1>(0h0)) \n when _T_443 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_440, UInt<1>(0h1), \"\") : assert_63 \n node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_445 = or(UInt<1>(0h0), _T_444) \n node _T_446 = asUInt(reset) \n node _T_447 = eq(_T_446, UInt<1>(0h0)) \n when _T_447 : \n node _T_448 = eq(_T_445, UInt<1>(0h0)) \n when _T_448 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_445, UInt<1>(0h1), \"\") : assert_64 \n node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_449 : \n node _T_450 = asUInt(reset) \n node _T_451 = eq(_T_450, UInt<1>(0h0)) \n when _T_451 : \n node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_452 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_453 = asUInt(reset) \n node _T_454 = eq(_T_453, UInt<1>(0h0)) \n when _T_454 : \n node _T_455 = eq(sink_ok, UInt<1>(0h0)) \n when _T_455 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) \n node _T_457 = asUInt(reset) \n node _T_458 = eq(_T_457, UInt<1>(0h0)) \n when _T_458 : \n node _T_459 = eq(_T_456, UInt<1>(0h0)) \n when _T_459 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_456, UInt<1>(0h1), \"\") : assert_67 \n node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_461 = asUInt(reset) \n node _T_462 = eq(_T_461, UInt<1>(0h0)) \n when _T_462 : \n node _T_463 = eq(_T_460, UInt<1>(0h0)) \n when _T_463 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_460, UInt<1>(0h1), \"\") : assert_68 \n node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_465 = asUInt(reset) \n node _T_466 = eq(_T_465, UInt<1>(0h0)) \n when _T_466 : \n node _T_467 = eq(_T_464, UInt<1>(0h0)) \n when _T_467 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_464, UInt<1>(0h1), \"\") : assert_69 \n node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_469 = or(_T_468, io.in.d.bits.corrupt) \n node _T_470 = asUInt(reset) \n node _T_471 = eq(_T_470, UInt<1>(0h0)) \n when _T_471 : \n node _T_472 = eq(_T_469, UInt<1>(0h0)) \n when _T_472 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_469, UInt<1>(0h1), \"\") : assert_70 \n node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_474 = or(UInt<1>(0h0), _T_473) \n node _T_475 = asUInt(reset) \n node _T_476 = eq(_T_475, UInt<1>(0h0)) \n when _T_476 : \n node _T_477 = eq(_T_474, UInt<1>(0h0)) \n when _T_477 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_474, UInt<1>(0h1), \"\") : assert_71 \n node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_478 : \n node _T_479 = asUInt(reset) \n node _T_480 = eq(_T_479, UInt<1>(0h0)) \n when _T_480 : \n node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_481 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_483 = asUInt(reset) \n node _T_484 = eq(_T_483, UInt<1>(0h0)) \n when _T_484 : \n node _T_485 = eq(_T_482, UInt<1>(0h0)) \n when _T_485 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_482, UInt<1>(0h1), \"\") : assert_73 \n node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_487 = asUInt(reset) \n node _T_488 = eq(_T_487, UInt<1>(0h0)) \n when _T_488 : \n node _T_489 = eq(_T_486, UInt<1>(0h0)) \n when _T_489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_486, UInt<1>(0h1), \"\") : assert_74 \n node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_491 = or(UInt<1>(0h0), _T_490) \n node _T_492 = asUInt(reset) \n node _T_493 = eq(_T_492, UInt<1>(0h0)) \n when _T_493 : \n node _T_494 = eq(_T_491, UInt<1>(0h0)) \n when _T_494 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_491, UInt<1>(0h1), \"\") : assert_75 \n node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_495 : \n node _T_496 = asUInt(reset) \n node _T_497 = eq(_T_496, UInt<1>(0h0)) \n when _T_497 : \n node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_498 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_500 = asUInt(reset) \n node _T_501 = eq(_T_500, UInt<1>(0h0)) \n when _T_501 : \n node _T_502 = eq(_T_499, UInt<1>(0h0)) \n when _T_502 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_499, UInt<1>(0h1), \"\") : assert_77 \n node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_504 = or(_T_503, io.in.d.bits.corrupt) \n node _T_505 = asUInt(reset) \n node _T_506 = eq(_T_505, UInt<1>(0h0)) \n when _T_506 : \n node _T_507 = eq(_T_504, UInt<1>(0h0)) \n when _T_507 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_504, UInt<1>(0h1), \"\") : assert_78 \n node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_509 = or(UInt<1>(0h0), _T_508) \n node _T_510 = asUInt(reset) \n node _T_511 = eq(_T_510, UInt<1>(0h0)) \n when _T_511 : \n node _T_512 = eq(_T_509, UInt<1>(0h0)) \n when _T_512 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_509, UInt<1>(0h1), \"\") : assert_79 \n node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_513 : \n node _T_514 = asUInt(reset) \n node _T_515 = eq(_T_514, UInt<1>(0h0)) \n when _T_515 : \n node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_516 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_518 = asUInt(reset) \n node _T_519 = eq(_T_518, UInt<1>(0h0)) \n when _T_519 : \n node _T_520 = eq(_T_517, UInt<1>(0h0)) \n when _T_520 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_517, UInt<1>(0h1), \"\") : assert_81 \n node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_522 = asUInt(reset) \n node _T_523 = eq(_T_522, UInt<1>(0h0)) \n when _T_523 : \n node _T_524 = eq(_T_521, UInt<1>(0h0)) \n when _T_524 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_521, UInt<1>(0h1), \"\") : assert_82 \n node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_526 = or(UInt<1>(0h0), _T_525) \n node _T_527 = asUInt(reset) \n node _T_528 = eq(_T_527, UInt<1>(0h0)) \n when _T_528 : \n node _T_529 = eq(_T_526, UInt<1>(0h0)) \n when _T_529 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_526, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<64>(0h0) \n connect _WIRE.bits.mask, UInt<8>(0h0) \n connect _WIRE.bits.address, UInt<28>(0h0) \n connect _WIRE.bits.source, UInt<5>(0h0) \n connect _WIRE.bits.size, UInt<3>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_531 = asUInt(reset) \n node _T_532 = eq(_T_531, UInt<1>(0h0)) \n when _T_532 : \n node _T_533 = eq(_T_530, UInt<1>(0h0)) \n when _T_533 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_530, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<64>(0h0) \n connect _WIRE_2.bits.address, UInt<28>(0h0) \n connect _WIRE_2.bits.source, UInt<5>(0h0) \n connect _WIRE_2.bits.size, UInt<3>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_535 = asUInt(reset) \n node _T_536 = eq(_T_535, UInt<1>(0h0)) \n when _T_536 : \n node _T_537 = eq(_T_534, UInt<1>(0h0)) \n when _T_537 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_534, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_539 = asUInt(reset) \n node _T_540 = eq(_T_539, UInt<1>(0h0)) \n when _T_540 : \n node _T_541 = eq(_T_538, UInt<1>(0h0)) \n when _T_541 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_538, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_542 = eq(a_first, UInt<1>(0h0)) \n node _T_543 = and(io.in.a.valid, _T_542) \n when _T_543 : \n node _T_544 = eq(io.in.a.bits.opcode, opcode) \n node _T_545 = asUInt(reset) \n node _T_546 = eq(_T_545, UInt<1>(0h0)) \n when _T_546 : \n node _T_547 = eq(_T_544, UInt<1>(0h0)) \n when _T_547 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_544, UInt<1>(0h1), \"\") : assert_87 \n node _T_548 = eq(io.in.a.bits.param, param) \n node _T_549 = asUInt(reset) \n node _T_550 = eq(_T_549, UInt<1>(0h0)) \n when _T_550 : \n node _T_551 = eq(_T_548, UInt<1>(0h0)) \n when _T_551 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_548, UInt<1>(0h1), \"\") : assert_88 \n node _T_552 = eq(io.in.a.bits.size, size) \n node _T_553 = asUInt(reset) \n node _T_554 = eq(_T_553, UInt<1>(0h0)) \n when _T_554 : \n node _T_555 = eq(_T_552, UInt<1>(0h0)) \n when _T_555 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_552, UInt<1>(0h1), \"\") : assert_89 \n node _T_556 = eq(io.in.a.bits.source, source) \n node _T_557 = asUInt(reset) \n node _T_558 = eq(_T_557, UInt<1>(0h0)) \n when _T_558 : \n node _T_559 = eq(_T_556, UInt<1>(0h0)) \n when _T_559 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_556, UInt<1>(0h1), \"\") : assert_90 \n node _T_560 = eq(io.in.a.bits.address, address) \n node _T_561 = asUInt(reset) \n node _T_562 = eq(_T_561, UInt<1>(0h0)) \n when _T_562 : \n node _T_563 = eq(_T_560, UInt<1>(0h0)) \n when _T_563 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_560, UInt<1>(0h1), \"\") : assert_91 \n node _T_564 = and(io.in.a.ready, io.in.a.valid) \n node _T_565 = and(_T_564, a_first) \n when _T_565 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_566 = eq(d_first, UInt<1>(0h0)) \n node _T_567 = and(io.in.d.valid, _T_566) \n when _T_567 : \n node _T_568 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_569 = asUInt(reset) \n node _T_570 = eq(_T_569, UInt<1>(0h0)) \n when _T_570 : \n node _T_571 = eq(_T_568, UInt<1>(0h0)) \n when _T_571 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_568, UInt<1>(0h1), \"\") : assert_92 \n node _T_572 = eq(io.in.d.bits.param, param_1) \n node _T_573 = asUInt(reset) \n node _T_574 = eq(_T_573, UInt<1>(0h0)) \n when _T_574 : \n node _T_575 = eq(_T_572, UInt<1>(0h0)) \n when _T_575 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_572, UInt<1>(0h1), \"\") : assert_93 \n node _T_576 = eq(io.in.d.bits.size, size_1) \n node _T_577 = asUInt(reset) \n node _T_578 = eq(_T_577, UInt<1>(0h0)) \n when _T_578 : \n node _T_579 = eq(_T_576, UInt<1>(0h0)) \n when _T_579 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_576, UInt<1>(0h1), \"\") : assert_94 \n node _T_580 = eq(io.in.d.bits.source, source_1) \n node _T_581 = asUInt(reset) \n node _T_582 = eq(_T_581, UInt<1>(0h0)) \n when _T_582 : \n node _T_583 = eq(_T_580, UInt<1>(0h0)) \n when _T_583 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_580, UInt<1>(0h1), \"\") : assert_95 \n node _T_584 = eq(io.in.d.bits.sink, sink) \n node _T_585 = asUInt(reset) \n node _T_586 = eq(_T_585, UInt<1>(0h0)) \n when _T_586 : \n node _T_587 = eq(_T_584, UInt<1>(0h0)) \n when _T_587 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_584, UInt<1>(0h1), \"\") : assert_96 \n node _T_588 = eq(io.in.d.bits.denied, denied) \n node _T_589 = asUInt(reset) \n node _T_590 = eq(_T_589, UInt<1>(0h0)) \n when _T_590 : \n node _T_591 = eq(_T_588, UInt<1>(0h0)) \n when _T_591 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_588, UInt<1>(0h1), \"\") : assert_97 \n node _T_592 = and(io.in.d.ready, io.in.d.valid) \n node _T_593 = and(_T_592, d_first) \n when _T_593 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0) \n regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0) \n regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<20> \n connect a_set, UInt<20>(0h0) \n wire a_set_wo_ready : UInt<20> \n connect a_set_wo_ready, UInt<20>(0h0) \n wire a_opcodes_set : UInt<80> \n connect a_opcodes_set, UInt<80>(0h0) \n wire a_sizes_set : UInt<80> \n connect a_sizes_set, UInt<80>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<4> \n connect a_sizes_set_interm, UInt<4>(0h0) \n node _T_594 = and(io.in.a.valid, a_first_1) \n node _T_595 = and(_T_594, UInt<1>(0h1)) \n when _T_595 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_596 = and(io.in.a.ready, io.in.a.valid) \n node _T_597 = and(_T_596, a_first_1) \n node _T_598 = and(_T_597, UInt<1>(0h1)) \n when _T_598 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_599 = dshr(inflight, io.in.a.bits.source) \n node _T_600 = bits(_T_599, 0, 0) \n node _T_601 = eq(_T_600, UInt<1>(0h0)) \n node _T_602 = asUInt(reset) \n node _T_603 = eq(_T_602, UInt<1>(0h0)) \n when _T_603 : \n node _T_604 = eq(_T_601, UInt<1>(0h0)) \n when _T_604 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_601, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<20> \n connect d_clr, UInt<20>(0h0) \n wire d_clr_wo_ready : UInt<20> \n connect d_clr_wo_ready, UInt<20>(0h0) \n wire d_opcodes_clr : UInt<80> \n connect d_opcodes_clr, UInt<80>(0h0) \n wire d_sizes_clr : UInt<80> \n connect d_sizes_clr, UInt<80>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_605 = and(io.in.d.valid, d_first_1) \n node _T_606 = and(_T_605, UInt<1>(0h1)) \n node _T_607 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_608 = and(_T_606, _T_607) \n when _T_608 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_609 = and(io.in.d.ready, io.in.d.valid) \n node _T_610 = and(_T_609, d_first_1) \n node _T_611 = and(_T_610, UInt<1>(0h1)) \n node _T_612 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_613 = and(_T_611, _T_612) \n when _T_613 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_614 = and(io.in.d.valid, d_first_1) \n node _T_615 = and(_T_614, UInt<1>(0h1)) \n node _T_616 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_617 = and(_T_615, _T_616) \n when _T_617 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_618 = dshr(inflight, io.in.d.bits.source) \n node _T_619 = bits(_T_618, 0, 0) \n node _T_620 = or(_T_619, same_cycle_resp) \n node _T_621 = asUInt(reset) \n node _T_622 = eq(_T_621, UInt<1>(0h0)) \n when _T_622 : \n node _T_623 = eq(_T_620, UInt<1>(0h0)) \n when _T_623 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_620, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_626 = or(_T_624, _T_625) \n node _T_627 = asUInt(reset) \n node _T_628 = eq(_T_627, UInt<1>(0h0)) \n when _T_628 : \n node _T_629 = eq(_T_626, UInt<1>(0h0)) \n when _T_629 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_626, UInt<1>(0h1), \"\") : assert_100 \n node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_631 = asUInt(reset) \n node _T_632 = eq(_T_631, UInt<1>(0h0)) \n when _T_632 : \n node _T_633 = eq(_T_630, UInt<1>(0h0)) \n when _T_633 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_630, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_636 = or(_T_634, _T_635) \n node _T_637 = asUInt(reset) \n node _T_638 = eq(_T_637, UInt<1>(0h0)) \n when _T_638 : \n node _T_639 = eq(_T_636, UInt<1>(0h0)) \n when _T_639 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_636, UInt<1>(0h1), \"\") : assert_102 \n node _T_640 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_641 = asUInt(reset) \n node _T_642 = eq(_T_641, UInt<1>(0h0)) \n when _T_642 : \n node _T_643 = eq(_T_640, UInt<1>(0h0)) \n when _T_643 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_640, UInt<1>(0h1), \"\") : assert_103 \n node _T_644 = and(io.in.d.valid, d_first_1) \n node _T_645 = and(_T_644, a_first_1) \n node _T_646 = and(_T_645, io.in.a.valid) \n node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_648 = and(_T_646, _T_647) \n node _T_649 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_650 = and(_T_648, _T_649) \n when _T_650 : \n node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_652 = or(_T_651, io.in.a.ready) \n node _T_653 = asUInt(reset) \n node _T_654 = eq(_T_653, UInt<1>(0h0)) \n when _T_654 : \n node _T_655 = eq(_T_652, UInt<1>(0h0)) \n when _T_655 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_652, UInt<1>(0h1), \"\") : assert_104 \n node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) \n node _T_657 = orr(a_set_wo_ready) \n node _T_658 = eq(_T_657, UInt<1>(0h0)) \n node _T_659 = or(_T_656, _T_658) \n node _T_660 = asUInt(reset) \n node _T_661 = eq(_T_660, UInt<1>(0h0)) \n when _T_661 : \n node _T_662 = eq(_T_659, UInt<1>(0h0)) \n when _T_662 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_659, UInt<1>(0h1), \"\") : assert_105 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_136 \n node _T_663 = orr(inflight) \n node _T_664 = eq(_T_663, UInt<1>(0h0)) \n node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_666 = or(_T_664, _T_665) \n node _T_667 = lt(watchdog, plusarg_reader.out) \n node _T_668 = or(_T_666, _T_667) \n node _T_669 = asUInt(reset) \n node _T_670 = eq(_T_669, UInt<1>(0h0)) \n when _T_670 : \n node _T_671 = eq(_T_668, UInt<1>(0h0)) \n when _T_671 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_668, UInt<1>(0h1), \"\") : assert_106 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_672 = and(io.in.a.ready, io.in.a.valid) \n node _T_673 = and(io.in.d.ready, io.in.d.valid) \n node _T_674 = or(_T_672, _T_673) \n when _T_674 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0) \n regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0) \n regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE.bits.address, UInt<28>(0h0) \n connect _c_first_WIRE.bits.source, UInt<5>(0h0) \n connect _c_first_WIRE.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<28>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<20> \n connect c_set, UInt<20>(0h0) \n wire c_set_wo_ready : UInt<20> \n connect c_set_wo_ready, UInt<20>(0h0) \n wire c_opcodes_set : UInt<80> \n connect c_opcodes_set, UInt<80>(0h0) \n wire c_sizes_set : UInt<80> \n connect c_sizes_set, UInt<80>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<4> \n connect c_sizes_set_interm, UInt<4>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<64>(0h0) \n connect _WIRE_6.bits.address, UInt<28>(0h0) \n connect _WIRE_6.bits.source, UInt<5>(0h0) \n connect _WIRE_6.bits.size, UInt<3>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_675 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<64>(0h0) \n connect _WIRE_8.bits.address, UInt<28>(0h0) \n connect _WIRE_8.bits.source, UInt<5>(0h0) \n connect _WIRE_8.bits.size, UInt<3>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_678 = and(_T_676, _T_677) \n node _T_679 = and(_T_675, _T_678) \n when _T_679 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<64>(0h0) \n connect _WIRE_10.bits.address, UInt<28>(0h0) \n connect _WIRE_10.bits.source, UInt<5>(0h0) \n connect _WIRE_10.bits.size, UInt<3>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_681 = and(_T_680, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<64>(0h0) \n connect _WIRE_12.bits.address, UInt<28>(0h0) \n connect _WIRE_12.bits.source, UInt<5>(0h0) \n connect _WIRE_12.bits.size, UInt<3>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_684 = and(_T_682, _T_683) \n node _T_685 = and(_T_681, _T_684) \n when _T_685 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_set_WIRE.bits.address, UInt<28>(0h0) \n connect _c_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<64>(0h0) \n connect _WIRE_14.bits.address, UInt<28>(0h0) \n connect _WIRE_14.bits.source, UInt<5>(0h0) \n connect _WIRE_14.bits.size, UInt<3>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_687 = bits(_T_686, 0, 0) \n node _T_688 = eq(_T_687, UInt<1>(0h0)) \n node _T_689 = asUInt(reset) \n node _T_690 = eq(_T_689, UInt<1>(0h0)) \n when _T_690 : \n node _T_691 = eq(_T_688, UInt<1>(0h0)) \n when _T_691 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_688, UInt<1>(0h1), \"\") : assert_107 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<20> \n connect d_clr_1, UInt<20>(0h0) \n wire d_clr_wo_ready_1 : UInt<20> \n connect d_clr_wo_ready_1, UInt<20>(0h0) \n wire d_opcodes_clr_1 : UInt<80> \n connect d_opcodes_clr_1, UInt<80>(0h0) \n wire d_sizes_clr_1 : UInt<80> \n connect d_sizes_clr_1, UInt<80>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_692 = and(io.in.d.valid, d_first_2) \n node _T_693 = and(_T_692, UInt<1>(0h1)) \n node _T_694 = and(_T_693, d_release_ack_1) \n when _T_694 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_695 = and(io.in.d.ready, io.in.d.valid) \n node _T_696 = and(_T_695, d_first_2) \n node _T_697 = and(_T_696, UInt<1>(0h1)) \n node _T_698 = and(_T_697, d_release_ack_1) \n when _T_698 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_699 = and(io.in.d.valid, d_first_2) \n node _T_700 = and(_T_699, UInt<1>(0h1)) \n node _T_701 = and(_T_700, d_release_ack_1) \n when _T_701 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_702 = dshr(inflight_1, io.in.d.bits.source) \n node _T_703 = bits(_T_702, 0, 0) \n node _T_704 = or(_T_703, same_cycle_resp_1) \n node _T_705 = asUInt(reset) \n node _T_706 = eq(_T_705, UInt<1>(0h0)) \n when _T_706 : \n node _T_707 = eq(_T_704, UInt<1>(0h0)) \n when _T_707 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_704, UInt<1>(0h1), \"\") : assert_108 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<64>(0h0) \n connect _WIRE_16.bits.address, UInt<28>(0h0) \n connect _WIRE_16.bits.source, UInt<5>(0h0) \n connect _WIRE_16.bits.size, UInt<3>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_709 = asUInt(reset) \n node _T_710 = eq(_T_709, UInt<1>(0h0)) \n when _T_710 : \n node _T_711 = eq(_T_708, UInt<1>(0h0)) \n when _T_711 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_708, UInt<1>(0h1), \"\") : assert_109 \n else :\n\n node _T_712 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_713 = asUInt(reset) \n node _T_714 = eq(_T_713, UInt<1>(0h0)) \n when _T_714 : \n node _T_715 = eq(_T_712, UInt<1>(0h0)) \n when _T_715 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_712, UInt<1>(0h1), \"\") : assert_110 \n node _T_716 = and(io.in.d.valid, d_first_2) \n node _T_717 = and(_T_716, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<64>(0h0) \n connect _WIRE_18.bits.address, UInt<28>(0h0) \n connect _WIRE_18.bits.source, UInt<5>(0h0) \n connect _WIRE_18.bits.size, UInt<3>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_718 = and(_T_717, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<64>(0h0) \n connect _WIRE_20.bits.address, UInt<28>(0h0) \n connect _WIRE_20.bits.source, UInt<5>(0h0) \n connect _WIRE_20.bits.size, UInt<3>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_720 = and(_T_718, _T_719) \n node _T_721 = and(_T_720, d_release_ack_1) \n node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_723 = and(_T_721, _T_722) \n when _T_723 : \n node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<64>(0h0) \n connect _WIRE_22.bits.address, UInt<28>(0h0) \n connect _WIRE_22.bits.source, UInt<5>(0h0) \n connect _WIRE_22.bits.size, UInt<3>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_725 = or(_T_724, _WIRE_23.ready) \n node _T_726 = asUInt(reset) \n node _T_727 = eq(_T_726, UInt<1>(0h0)) \n when _T_727 : \n node _T_728 = eq(_T_725, UInt<1>(0h0)) \n when _T_728 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_725, UInt<1>(0h1), \"\") : assert_111 \n node _T_729 = orr(c_set_wo_ready) \n when _T_729 : \n node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) \n node _T_731 = asUInt(reset) \n node _T_732 = eq(_T_731, UInt<1>(0h0)) \n when _T_732 : \n node _T_733 = eq(_T_730, UInt<1>(0h0)) \n when _T_733 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_112 \n assert(clock, _T_730, UInt<1>(0h1), \"\") : assert_112 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_137 \n node _T_734 = orr(inflight_1) \n node _T_735 = eq(_T_734, UInt<1>(0h0)) \n node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_737 = or(_T_735, _T_736) \n node _T_738 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_739 = or(_T_737, _T_738) \n node _T_740 = asUInt(reset) \n node _T_741 = eq(_T_740, UInt<1>(0h0)) \n when _T_741 : \n node _T_742 = eq(_T_739, UInt<1>(0h0)) \n when _T_742 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_113 \n assert(clock, _T_739, UInt<1>(0h1), \"\") : assert_113 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<64>(0h0) \n connect _WIRE_24.bits.address, UInt<28>(0h0) \n connect _WIRE_24.bits.source, UInt<5>(0h0) \n connect _WIRE_24.bits.size, UInt<3>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_744 = and(io.in.d.ready, io.in.d.valid) \n node _T_745 = or(_T_743, _T_744) \n when _T_745 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_67(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_a_bits_source,\t// @[Monitor.scala:20:14]\n input [27:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [7:0] io_in_a_bits_mask,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_a_bits_corrupt,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input [4:0] io_in_d_bits_source,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_sink,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input [63:0] io_in_d_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source;\t// @[Monitor.scala:36:7]\n wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink_0 = io_in_d_bits_sink;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire _source_ok_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _source_ok_T_6 = 1'h0;\t// @[Parameters.scala:54:10]\n wire sink_ok = 1'h0;\t// @[Monitor.scala:309:31]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_first_beats1_decode = 3'h0;\t// @[Edges.scala:220:59]\n wire [2:0] c_first_beats1 = 3'h0;\t// @[Edges.scala:221:14]\n wire [2:0] _c_first_count_T = 3'h0;\t// @[Edges.scala:234:27]\n wire [2:0] c_first_count = 3'h0;\t// @[Edges.scala:234:25]\n wire [2:0] _c_first_counter_T = 3'h0;\t// @[Edges.scala:236:21]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0;\t// @[Bundles.scala:265:61]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _source_ok_T_7 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _source_ok_T_8 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _source_ok_T_9 = 1'h1;\t// @[Parameters.scala:54:67]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire [2:0] c_first_counter1 = 3'h7;\t// @[Edges.scala:230:28]\n wire [3:0] _c_first_counter1_T = 4'hF;\t// @[Edges.scala:230:28]\n wire [63:0] _c_first_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_first_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_first_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0;\t// @[Bundles.scala:265:74]\n wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_first_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_first_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0;\t// @[Bundles.scala:265:74]\n wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_first_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_first_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [258:0] _c_opcodes_set_T_1 = 259'h0;\t// @[Monitor.scala:767:54]\n wire [258:0] _c_sizes_set_T_1 = 259'h0;\t// @[Monitor.scala:768:52]\n wire [7:0] _c_opcodes_set_T = 8'h0;\t// @[Monitor.scala:767:79]\n wire [7:0] _c_sizes_set_T = 8'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [3:0] _c_sizes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] c_sizes_set_interm = 4'h0;\t// @[Monitor.scala:755:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_sizes_set_interm_T = 4'h0;\t// @[Monitor.scala:766:51]\n wire [31:0] _c_set_wo_ready_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [31:0] _c_set_T = 32'h1;\t// @[OneHot.scala:58:35]\n wire [79:0] c_opcodes_set = 80'h0;\t// @[Monitor.scala:740:34]\n wire [79:0] c_sizes_set = 80'h0;\t// @[Monitor.scala:741:34]\n wire [19:0] c_set = 20'h0;\t// @[Monitor.scala:738:34]\n wire [19:0] c_set_wo_ready = 20'h0;\t// @[Monitor.scala:739:34]\n wire [5:0] _c_first_beats1_decode_T_2 = 6'h0;\t// @[package.scala:243:46]\n wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F;\t// @[package.scala:243:76]\n wire [12:0] _c_first_beats1_decode_T = 13'h3F;\t// @[package.scala:243:71]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0;\t// @[Misc.scala:202:34]\n wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0;\t// @[Monitor.scala:36:7]\n wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_5 = _source_ok_T_4;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_0 = _source_ok_T_5;\t// @[Parameters.scala:1138:31]\n wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _is_aligned_mask_T;\t// @[package.scala:243:71]\n assign _is_aligned_mask_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [12:0] _a_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _a_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1;\t// @[package.scala:243:{46,76}]\n wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask};\t// @[package.scala:243:46]\n wire is_aligned = _is_aligned_T == 28'h0;\t// @[Edges.scala:21:{16,24}]\n wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0];\t// @[OneHot.scala:64:49]\n wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0];\t// @[OneHot.scala:65:{12,27}]\n wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1};\t// @[OneHot.scala:65:27]\n wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2;\t// @[Misc.scala:206:21]\n wire mask_sub_sub_size = mask_sizeOH[2];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_sub_bit = io_in_a_bits_address_0[2];\t// @[Misc.scala:210:26]\n wire mask_sub_sub_1_2 = mask_sub_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_sub_nbit = ~mask_sub_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_sub_0_2 = mask_sub_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1;\t// @[Misc.scala:206:21, :215:{29,38}]\n wire mask_sub_size = mask_sizeOH[1];\t// @[Misc.scala:202:81, :209:26]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_size = mask_sizeOH[0];\t// @[Misc.scala:202:81, :209:26]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_size & mask_eq;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc = mask_sub_0_1 | _mask_acc_T;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_size & mask_eq_1;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_size & mask_eq_2;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_size & mask_eq_3;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_4 = mask_sub_2_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_4 = mask_size & mask_eq_4;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_5 = mask_sub_2_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_5 = mask_size & mask_eq_5;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_6 = mask_sub_3_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_6 = mask_size & mask_eq_6;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6;\t// @[Misc.scala:215:{29,38}]\n wire mask_eq_7 = mask_sub_3_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_7 = mask_size & mask_eq_7;\t// @[Misc.scala:209:26, :214:27, :215:38]\n wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7;\t// @[Misc.scala:215:{29,38}]\n wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo};\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4};\t// @[Misc.scala:215:29, :222:10]\n wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6};\t// @[Misc.scala:215:29, :222:10]\n wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo};\t// @[Misc.scala:222:10]\n wire [7:0] mask = {mask_hi, mask_lo};\t// @[Misc.scala:222:10]\n wire [4:0] uncommonBits = _uncommonBits_T;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_1 = _uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_2 = _uncommonBits_T_2;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_3 = _uncommonBits_T_3;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_4 = _uncommonBits_T_4;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_5 = _uncommonBits_T_5;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_6 = _uncommonBits_T_6;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_7 = _uncommonBits_T_7;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] uncommonBits_8 = _uncommonBits_T_8;\t// @[Parameters.scala:52:{29,56}]\n wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1;\t// @[Parameters.scala:52:{29,56}]\n wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14;\t// @[Parameters.scala:52:56, :57:20]\n wire _source_ok_T_11 = _source_ok_T_10;\t// @[Parameters.scala:56:48, :57:20]\n wire _source_ok_WIRE_1_0 = _source_ok_T_11;\t// @[Parameters.scala:1138:31]\n wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_672;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_672;\t// @[Decoupled.scala:51:35]\n wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire a_first = a_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T = a_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_1 = a_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last = _a_first_last_T | _a_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done = a_first_last & _a_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [2:0] param;\t// @[Monitor.scala:388:22]\n reg [2:0] size;\t// @[Monitor.scala:389:22]\n reg [4:0] source;\t// @[Monitor.scala:390:22]\n reg [27:0] address;\t// @[Monitor.scala:391:22]\n wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_745;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_745;\t// @[Decoupled.scala:51:35]\n wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN_0;\t// @[package.scala:243:71]\n wire [12:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN_0;\t// @[package.scala:243:71]\n wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3];\t// @[package.scala:243:46]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0];\t// @[Edges.scala:230:28]\n wire d_first = d_first_counter == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T = d_first_counter == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_1 = d_first_beats1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last = _d_first_last_T | _d_first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done = d_first_last & _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [2:0] size_1;\t// @[Monitor.scala:540:22]\n reg [4:0] source_1;\t// @[Monitor.scala:541:22]\n reg sink;\t// @[Monitor.scala:542:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [19:0] inflight;\t// @[Monitor.scala:614:27]\n reg [79:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n reg [79:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [2:0] a_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire a_first_1 = a_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_last_T_2 = a_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire a_first_done_1 = a_first_last_1 & _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_1;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0];\t// @[Edges.scala:230:28]\n wire d_first_1 = d_first_counter_1 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_2 = d_first_counter_1 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_1 = d_first_last_1 & _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [19:0] a_set;\t// @[Monitor.scala:626:34]\n wire [19:0] a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [79:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [79:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :637:69]\n wire [7:0] _a_opcode_lookup_T;\t// @[Monitor.scala:637:69]\n assign _a_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69]\n wire [7:0] _a_size_lookup_T;\t// @[Monitor.scala:641:65]\n assign _a_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :641:65]\n wire [7:0] _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:101]\n assign _d_opcodes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :680:101]\n wire [7:0] _d_sizes_clr_T_4;\t// @[Monitor.scala:681:99]\n assign _d_sizes_clr_T_4 = _GEN_1;\t// @[Monitor.scala:637:69, :681:99]\n wire [7:0] _c_opcode_lookup_T;\t// @[Monitor.scala:749:69]\n assign _c_opcode_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :749:69]\n wire [7:0] _c_size_lookup_T;\t// @[Monitor.scala:750:67]\n assign _c_size_lookup_T = _GEN_1;\t// @[Monitor.scala:637:69, :750:67]\n wire [7:0] _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:101]\n assign _d_opcodes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :790:101]\n wire [7:0] _d_sizes_clr_T_10;\t// @[Monitor.scala:791:99]\n assign _d_sizes_clr_T_10 = _GEN_1;\t// @[Monitor.scala:637:69, :791:99]\n wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T;\t// @[Monitor.scala:616:35, :637:{44,69}]\n wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:637:{44,97}]\n wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T;\t// @[Monitor.scala:618:33, :641:{40,65}]\n wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]};\t// @[Monitor.scala:641:{40,91}]\n wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [3:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26, :684:44]\n wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _a_set_wo_ready_T = _GEN_2;\t// @[OneHot.scala:58:35]\n wire [31:0] _a_set_T;\t// @[OneHot.scala:58:35]\n assign _a_set_T = _GEN_2;\t// @[OneHot.scala:58:35]\n assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_598 = _T_672 & a_first_1;\t// @[Decoupled.scala:51:35]\n assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]\n wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0};\t// @[Monitor.scala:36:7, :658:51]\n wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:658:{51,59}]\n assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]\n wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0};\t// @[Monitor.scala:36:7, :659:79]\n wire [7:0] _a_opcodes_set_T;\t// @[Monitor.scala:659:79]\n assign _a_opcodes_set_T = _GEN_3;\t// @[Monitor.scala:659:79]\n wire [7:0] _a_sizes_set_T;\t// @[Monitor.scala:660:77]\n assign _a_sizes_set_T = _GEN_3;\t// @[Monitor.scala:659:79, :660:77]\n wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T;\t// @[Monitor.scala:646:40, :659:{54,79}]\n assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]\n wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T;\t// @[Monitor.scala:648:38, :659:54, :660:{52,77}]\n assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0;\t// @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]\n wire [19:0] d_clr;\t// @[Monitor.scala:664:34]\n wire [19:0] d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [79:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [79:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_4;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_4;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_644 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T;\t// @[OneHot.scala:58:35]\n assign _d_clr_T = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_wo_ready_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_wo_ready_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n wire [31:0] _d_clr_T_1;\t// @[OneHot.scala:58:35]\n assign _d_clr_T_1 = _GEN_5;\t// @[OneHot.scala:58:35]\n assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_613 = _T_745 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4;\t// @[Monitor.scala:680:{76,101}]\n assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]\n wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4;\t// @[Monitor.scala:681:{74,99}]\n assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0;\t// @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0;\t// @[Monitor.scala:36:7, :684:113]\n wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2;\t// @[Monitor.scala:684:{55,88,113}]\n wire [19:0] _inflight_T = inflight | a_set;\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire [19:0] _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1;\t// @[Monitor.scala:705:{27,36,38}]\n wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [19:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [19:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [79:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [79:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3];\t// @[package.scala:243:46]\n wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n reg [2:0] d_first_counter_2;\t// @[Edges.scala:229:27]\n wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0];\t// @[Edges.scala:230:28]\n wire d_first_2 = d_first_counter_2 == 3'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_last_T_4 = d_first_counter_2 == 3'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0;\t// @[Edges.scala:221:14, :232:43]\n wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5;\t// @[Edges.scala:232:{25,33,43}]\n wire d_first_done_2 = d_first_last_2 & _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T;\t// @[Monitor.scala:727:35, :749:{44,69}]\n wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]};\t// @[Monitor.scala:749:{44,97}]\n wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T;\t// @[Monitor.scala:728:35, :750:{42,67}]\n wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]};\t// @[Monitor.scala:750:{42,93}]\n wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire [19:0] d_clr_1;\t// @[Monitor.scala:774:34]\n wire [19:0] d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [79:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [79:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_716 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire _T_698 = _T_745 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0;\t// @[OneHot.scala:58:35]\n wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10;\t// @[Monitor.scala:790:{76,101}]\n assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]\n wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10;\t// @[Monitor.scala:791:{74,99}]\n assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0;\t// @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]\n wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0;\t// @[Monitor.scala:36:7, :795:113]\n wire [19:0] _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4;\t// @[Monitor.scala:814:{35,44,46}]\n wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":35493,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_2 : \n input clock : Clock \n input reset : Reset \n output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}} \n\n\n regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) \n regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0) \n node _reset_idx_T = add(reset_idx, doing_reset) \n node _reset_idx_T_1 = tail(_reset_idx_T, 1) \n connect reset_idx, _reset_idx_T_1 \n node _T = eq(reset_idx, UInt<4>(0hf)) \n when _T : \n connect doing_reset, UInt<1>(0h0) \n reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock \n node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))\n\n node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)\n\n wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} \n connect f2_entry, entries[_f2_entry_T_1] \n node _T_1 = eq(io.update_idx, io.f2_req_idx) \n node _T_2 = and(io.update_repair, _T_1) \n when _T_2 : \n connect f2_entry.s_cnt, io.update_meta.s_cnt \n else :\n\n node _T_3 = eq(io.update_idx, io.f2_req_idx) \n node _T_4 = and(io.update_mispredict, _T_3) \n when _T_4 : \n connect f2_entry.s_cnt, UInt<1>(0h0) \n reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock \n connect f3_entry, f2_entry \n reg f3_scnt_REG : UInt, clock \n connect f3_scnt_REG, io.f2_req_idx \n node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG) \n node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T) \n node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt) \n node _f3_tag_T = bits(io.f2_req_idx, 13, 4) \n reg f3_tag : UInt, clock \n connect f3_tag, _f3_tag_T \n connect io.f3_pred, io.f3_pred_in \n connect io.f3_meta.s_cnt, f3_scnt \n node _T_5 = eq(f3_entry.tag, f3_tag) \n when _T_5 : \n node _T_6 = eq(f3_scnt, f3_entry.p_cnt) \n node _T_7 = eq(f3_entry.conf, UInt<3>(0h7)) \n node _T_8 = and(_T_6, _T_7) \n when _T_8 : \n node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0)) \n connect io.f3_pred, _io_f3_pred_T \n reg f4_fire : UInt<1>, clock \n connect f4_fire, io.f3_req_fire \n reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock \n connect f4_entry, f3_entry \n reg f4_tag : UInt, clock \n connect f4_tag, f3_tag \n reg f4_scnt : UInt, clock \n connect f4_scnt, f3_scnt \n reg f4_idx_REG : UInt, clock \n connect f4_idx_REG, io.f2_req_idx \n reg f4_idx : UInt, clock \n connect f4_idx, f4_idx_REG \n when f4_fire : \n node _T_9 = eq(f4_entry.tag, f4_tag) \n when _T_9 : \n node _T_10 = eq(f4_scnt, f4_entry.p_cnt) \n node _T_11 = eq(f4_entry.conf, UInt<3>(0h7)) \n node _T_12 = and(_T_10, _T_11) \n when _T_12 : \n node _T_13 = or(f4_idx, UInt<4>(0h0))\n\n node _T_14 = bits(_T_13, 3, 0)\n\n connect entries[_T_14].age, UInt<3>(0h7) \n node _T_15 = or(f4_idx, UInt<4>(0h0))\n\n node _T_16 = bits(_T_15, 3, 0)\n\n connect entries[_T_16].s_cnt, UInt<1>(0h0) \n else :\n\n node _T_17 = or(f4_idx, UInt<4>(0h0))\n\n node _T_18 = bits(_T_17, 3, 0)\n\n node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1)) \n node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1) \n connect entries[_T_18].s_cnt, _entries_s_cnt_T_1 \n node _T_19 = or(f4_idx, UInt<4>(0h0))\n\n node _T_20 = bits(_T_19, 3, 0)\n\n node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7)) \n node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1)) \n node _entries_age_T_2 = tail(_entries_age_T_1, 1) \n node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2) \n connect entries[_T_20].age, _entries_age_T_3 \n node _entry_T = or(io.update_idx, UInt<4>(0h0))\n\n node _entry_T_1 = bits(_entry_T, 3, 0)\n\n node tag = bits(io.update_idx, 13, 4) \n node tag_match = eq(entries[_entry_T_1].tag, tag) \n node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt) \n wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} \n connect wentry, entries[_entry_T_1] \n node _T_21 = eq(doing_reset, UInt<1>(0h0)) \n node _T_22 = and(io.update_mispredict, _T_21) \n when _T_22 : \n node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) \n node _T_24 = and(_T_23, tag_match) \n when _T_24 : \n connect wentry.s_cnt, UInt<1>(0h0) \n connect wentry.conf, UInt<1>(0h0) \n else :\n\n node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7)) \n node _T_26 = eq(tag_match, UInt<1>(0h0)) \n node _T_27 = and(_T_25, _T_26) \n when _T_27 : \n skip\n\n else :\n\n node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_29 = and(_T_28, tag_match) \n node _T_30 = and(_T_29, ctr_match) \n when _T_30 : \n node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1)) \n node _wentry_conf_T_1 = tail(_wentry_conf_T, 1) \n connect wentry.conf, _wentry_conf_T_1 \n connect wentry.s_cnt, UInt<1>(0h0) \n else :\n\n node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_32 = and(_T_31, tag_match) \n node _T_33 = eq(ctr_match, UInt<1>(0h0)) \n node _T_34 = and(_T_32, _T_33) \n when _T_34 : \n connect wentry.conf, UInt<1>(0h0) \n connect wentry.s_cnt, UInt<1>(0h0) \n connect wentry.p_cnt, io.update_meta.s_cnt \n else :\n\n node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_36 = eq(tag_match, UInt<1>(0h0)) \n node _T_37 = and(_T_35, _T_36) \n node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0)) \n node _T_39 = and(_T_37, _T_38) \n when _T_39 : \n connect wentry.tag, tag \n connect wentry.conf, UInt<1>(0h1) \n connect wentry.s_cnt, UInt<1>(0h0) \n connect wentry.p_cnt, io.update_meta.s_cnt \n else :\n\n node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_41 = eq(tag_match, UInt<1>(0h0)) \n node _T_42 = and(_T_40, _T_41) \n node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0)) \n node _T_44 = and(_T_42, _T_43) \n when _T_44 : \n node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1)) \n node _wentry_age_T_1 = tail(_wentry_age_T, 1) \n connect wentry.age, _wentry_age_T_1 \n else :\n\n node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_46 = and(_T_45, tag_match) \n node _T_47 = and(_T_46, ctr_match) \n when _T_47 : \n connect wentry.conf, UInt<1>(0h1) \n connect wentry.age, UInt<3>(0h7) \n connect wentry.s_cnt, UInt<1>(0h0) \n else :\n\n node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_49 = and(_T_48, tag_match) \n node _T_50 = eq(ctr_match, UInt<1>(0h0)) \n node _T_51 = and(_T_49, _T_50) \n when _T_51 : \n connect wentry.p_cnt, io.update_meta.s_cnt \n connect wentry.age, UInt<3>(0h7) \n connect wentry.s_cnt, UInt<1>(0h0) \n else :\n\n node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0)) \n node _T_53 = eq(tag_match, UInt<1>(0h0)) \n node _T_54 = and(_T_52, _T_53) \n when _T_54 : \n connect wentry.tag, tag \n connect wentry.conf, UInt<1>(0h1) \n connect wentry.age, UInt<3>(0h7) \n connect wentry.s_cnt, UInt<1>(0h0) \n connect wentry.p_cnt, io.update_meta.s_cnt \n node _T_55 = or(io.update_idx, UInt<4>(0h0))\n\n node _T_56 = bits(_T_55, 3, 0)\n\n connect entries[_T_56], wentry \n else :\n\n node _T_57 = eq(doing_reset, UInt<1>(0h0)) \n node _T_58 = and(io.update_repair, _T_57) \n when _T_58 : \n node _T_59 = eq(io.update_idx, f4_idx) \n node _T_60 = and(f4_fire, _T_59) \n node _T_61 = eq(_T_60, UInt<1>(0h0)) \n node _T_62 = and(tag_match, _T_61) \n when _T_62 : \n connect wentry.s_cnt, io.update_meta.s_cnt \n node _T_63 = or(io.update_idx, UInt<4>(0h0))\n\n node _T_64 = bits(_T_63, 3, 0)\n\n connect entries[_T_64], wentry \n when doing_reset : \n wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>} \n connect _entries_WIRE.s_cnt, UInt<10>(0h0) \n connect _entries_WIRE.p_cnt, UInt<10>(0h0) \n connect _entries_WIRE.age, UInt<3>(0h0) \n connect _entries_WIRE.conf, UInt<3>(0h0) \n connect _entries_WIRE.tag, UInt<10>(0h0) \n connect entries[reset_idx], _entries_WIRE"},"response":{"kind":"string","value":"module LoopBranchPredictorColumn_2(\t// @[loop.scala:39:9]\n input clock,\t// @[loop.scala:39:9]\n input reset,\t// @[loop.scala:39:9]\n input io_f2_req_valid,\t// @[loop.scala:43:16]\n input [35:0] io_f2_req_idx,\t// @[loop.scala:43:16]\n input io_f3_req_fire,\t// @[loop.scala:43:16]\n input io_f3_pred_in,\t// @[loop.scala:43:16]\n output io_f3_pred,\t// @[loop.scala:43:16]\n output [9:0] io_f3_meta_s_cnt,\t// @[loop.scala:43:16]\n input io_update_mispredict,\t// @[loop.scala:43:16]\n input io_update_repair,\t// @[loop.scala:43:16]\n input [35:0] io_update_idx,\t// @[loop.scala:43:16]\n input io_update_resolve_dir,\t// @[loop.scala:43:16]\n input [9:0] io_update_meta_s_cnt\t// @[loop.scala:43:16]\n);\n\n wire io_f2_req_valid_0 = io_f2_req_valid;\t// @[loop.scala:39:9]\n wire [35:0] io_f2_req_idx_0 = io_f2_req_idx;\t// @[loop.scala:39:9]\n wire io_f3_req_fire_0 = io_f3_req_fire;\t// @[loop.scala:39:9]\n wire io_f3_pred_in_0 = io_f3_pred_in;\t// @[loop.scala:39:9]\n wire io_update_mispredict_0 = io_update_mispredict;\t// @[loop.scala:39:9]\n wire io_update_repair_0 = io_update_repair;\t// @[loop.scala:39:9]\n wire [35:0] io_update_idx_0 = io_update_idx;\t// @[loop.scala:39:9]\n wire io_update_resolve_dir_0 = io_update_resolve_dir;\t// @[loop.scala:39:9]\n wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt;\t// @[loop.scala:39:9]\n wire [2:0] _entries_WIRE_conf = 3'h0;\t// @[loop.scala:176:43]\n wire [2:0] _entries_WIRE_age = 3'h0;\t// @[loop.scala:176:43]\n wire [9:0] _entries_WIRE_tag = 10'h0;\t// @[loop.scala:176:43]\n wire [9:0] _entries_WIRE_p_cnt = 10'h0;\t// @[loop.scala:176:43]\n wire [9:0] _entries_WIRE_s_cnt = 10'h0;\t// @[loop.scala:176:43]\n wire [35:0] _f2_entry_T = io_f2_req_idx_0;\t// @[loop.scala:39:9]\n wire [9:0] f3_scnt;\t// @[loop.scala:73:23]\n wire [35:0] _entry_T = io_update_idx_0;\t// @[loop.scala:39:9]\n wire [9:0] io_f3_meta_s_cnt_0;\t// @[loop.scala:39:9]\n wire io_f3_pred_0;\t// @[loop.scala:39:9]\n reg doing_reset;\t// @[loop.scala:59:30]\n reg [3:0] reset_idx;\t// @[loop.scala:60:28]\n wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset};\t// @[loop.scala:59:30, :60:28, :61:28]\n wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0];\t// @[loop.scala:61:28]\n reg [9:0] entries_0_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_0_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_0_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_0_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_0_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_1_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_1_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_1_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_1_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_1_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_2_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_2_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_2_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_2_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_2_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_3_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_3_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_3_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_3_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_3_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_4_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_4_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_4_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_4_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_4_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_5_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_5_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_5_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_5_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_5_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_6_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_6_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_6_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_6_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_6_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_7_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_7_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_7_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_7_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_7_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_8_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_8_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_8_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_8_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_8_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_9_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_9_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_9_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_9_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_9_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_10_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_10_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_10_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_10_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_10_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_11_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_11_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_11_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_11_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_11_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_12_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_12_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_12_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_12_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_12_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_13_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_13_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_13_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_13_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_13_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_14_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_14_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_14_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_14_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_14_s_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_15_tag;\t// @[loop.scala:65:22]\n reg [2:0] entries_15_conf;\t// @[loop.scala:65:22]\n reg [2:0] entries_15_age;\t// @[loop.scala:65:22]\n reg [9:0] entries_15_p_cnt;\t// @[loop.scala:65:22]\n reg [9:0] entries_15_s_cnt;\t// @[loop.scala:65:22]\n wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];\n wire [9:0] f2_entry_tag;\t// @[loop.scala:66:28]\n wire [2:0] f2_entry_conf;\t// @[loop.scala:66:28]\n wire [2:0] f2_entry_age;\t// @[loop.scala:66:28]\n wire [9:0] f2_entry_p_cnt;\t// @[loop.scala:66:28]\n wire [9:0] f2_entry_s_cnt;\t// @[loop.scala:66:28]\n wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}};\t// @[loop.scala:65:22, :66:28]\n assign f2_entry_tag = _GEN[_f2_entry_T_1];\t// @[loop.scala:66:28]\n wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}};\t// @[loop.scala:65:22, :66:28]\n assign f2_entry_conf = _GEN_0[_f2_entry_T_1];\t// @[loop.scala:66:28]\n wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}};\t// @[loop.scala:65:22, :66:28]\n assign f2_entry_age = _GEN_1[_f2_entry_T_1];\t// @[loop.scala:66:28]\n wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}};\t// @[loop.scala:65:22, :66:28]\n assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1];\t// @[loop.scala:66:28]\n wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}};\t// @[loop.scala:65:22, :66:28]\n wire _T_3 = io_update_idx_0 == io_f2_req_idx_0;\t// @[loop.scala:39:9, :67:45]\n assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1];\t// @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]\n reg [9:0] f3_entry_tag;\t// @[loop.scala:72:27]\n reg [2:0] f3_entry_conf;\t// @[loop.scala:72:27]\n reg [2:0] f3_entry_age;\t// @[loop.scala:72:27]\n reg [9:0] f3_entry_p_cnt;\t// @[loop.scala:72:27]\n reg [9:0] f3_entry_s_cnt;\t// @[loop.scala:72:27]\n reg [35:0] f3_scnt_REG;\t// @[loop.scala:73:69]\n wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG;\t// @[loop.scala:39:9, :73:{58,69}]\n wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T;\t// @[loop.scala:39:9, :73:{41,58}]\n assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt;\t// @[loop.scala:39:9, :72:27, :73:{23,41}]\n assign io_f3_meta_s_cnt_0 = f3_scnt;\t// @[loop.scala:39:9, :73:23]\n wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4];\t// @[loop.scala:39:9, :76:41]\n reg [9:0] f3_tag;\t// @[loop.scala:76:27]\n wire _io_f3_pred_T = ~io_f3_pred_in_0;\t// @[loop.scala:39:9, :83:23]\n assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0;\t// @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]\n reg f4_fire;\t// @[loop.scala:88:27]\n reg [9:0] f4_entry_tag;\t// @[loop.scala:89:27]\n reg [2:0] f4_entry_conf;\t// @[loop.scala:89:27]\n reg [2:0] f4_entry_age;\t// @[loop.scala:89:27]\n reg [9:0] f4_entry_p_cnt;\t// @[loop.scala:89:27]\n reg [9:0] f4_entry_s_cnt;\t// @[loop.scala:89:27]\n reg [9:0] f4_tag;\t// @[loop.scala:90:27]\n reg [9:0] f4_scnt;\t// @[loop.scala:91:27]\n reg [35:0] f4_idx_REG;\t// @[loop.scala:92:35]\n reg [35:0] f4_idx;\t// @[loop.scala:92:27]\n wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1;\t// @[loop.scala:91:27, :101:44]\n wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0];\t// @[loop.scala:101:44]\n wire _entries_age_T = &f4_entry_age;\t// @[loop.scala:89:27, :102:53]\n wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1;\t// @[loop.scala:89:27, :102:80]\n wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0];\t// @[loop.scala:102:80]\n wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2;\t// @[loop.scala:102:{39,53,80}]\n wire [3:0] _entry_T_1 = _entry_T[3:0];\n wire [9:0] tag = io_update_idx_0[13:4];\t// @[loop.scala:39:9, :109:28]\n wire tag_match = _GEN[_entry_T_1] == tag;\t// @[loop.scala:66:28, :109:28, :110:31]\n wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0;\t// @[loop.scala:39:9, :66:28, :110:31, :111:33]\n wire [9:0] wentry_tag;\t// @[loop.scala:112:26]\n wire [2:0] wentry_conf;\t// @[loop.scala:112:26]\n wire [2:0] wentry_age;\t// @[loop.scala:112:26]\n wire [9:0] wentry_p_cnt;\t// @[loop.scala:112:26]\n wire [9:0] wentry_s_cnt;\t// @[loop.scala:112:26]\n wire _T_22 = io_update_mispredict_0 & ~doing_reset;\t// @[loop.scala:39:9, :59:30, :114:{32,35}]\n wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match;\t// @[loop.scala:66:28, :110:31, :117:{24,32}]\n wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match;\t// @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]\n wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match;\t// @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]\n wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1;\t// @[loop.scala:66:28, :102:80, :110:31, :126:36]\n wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0];\t// @[loop.scala:126:36]\n wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match;\t// @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]\n wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0;\t// @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]\n wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]);\t// @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]\n wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1;\t// @[loop.scala:66:28, :110:31, :144:33]\n wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0];\t// @[loop.scala:144:33]\n wire _T_52 = _GEN_0[_entry_T_1] == 3'h0;\t// @[loop.scala:66:28, :110:31, :147:31]\n wire _T_47 = _T_52 & tag_match & ctr_match;\t// @[loop.scala:110:31, :111:33, :147:{31,39,52}]\n wire _T_51 = _T_52 & tag_match & ~ctr_match;\t// @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]\n wire _T_54 = _T_52 & ~tag_match;\t// @[loop.scala:110:31, :122:42, :147:31, :159:39]\n wire _GEN_4 = _T_47 | _T_51;\t// @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]\n wire _GEN_5 = _T_30 | _T_34;\t// @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]\n assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag;\t// @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]\n assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1];\t// @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]\n wire _GEN_6 = _T_51 | _T_54;\t// @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]\n wire _GEN_7 = _T_34 | _T_39;\t// @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]\n assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1];\t// @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]\n assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0;\t// @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]\n wire _T_58 = io_update_repair_0 & ~doing_reset;\t// @[loop.scala:39:9, :59:30, :114:35, :168:35]\n wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx);\t// @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]\n assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1];\t// @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]\n wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf);\t// @[loop.scala:89:27, :91:27, :97:{23,42,59}]\n wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag;\t// @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]\n always @(posedge clock) begin\t// @[loop.scala:39:9]\n if (reset) begin\t// @[loop.scala:39:9]\n doing_reset <= 1'h1;\t// @[loop.scala:59:30]\n reset_idx <= 4'h0;\t// @[loop.scala:60:28]\n end\n else begin\t// @[loop.scala:39:9]\n doing_reset <= reset_idx != 4'hF & doing_reset;\t// @[loop.scala:59:30, :60:28, :62:{21,38,52}]\n reset_idx <= _reset_idx_T_1;\t// @[loop.scala:60:28, :61:28]\n end\n if (doing_reset & reset_idx == 4'h0) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_0_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_0_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_0_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_0_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_0_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_0_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_0_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_0_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_0_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_0_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h0)\t// @[loop.scala:92:27, :98:33]\n entries_0_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h0)\t// @[loop.scala:92:27, :99:33]\n entries_0_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h0)\t// @[loop.scala:92:27, :102:33]\n entries_0_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h0)\t// @[loop.scala:92:27, :101:33]\n entries_0_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h1) begin\t// @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]\n entries_1_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_1_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_1_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_1_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_1_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin\t// @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_1_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_1_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_1_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_1_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_1_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h1)\t// @[loop.scala:92:27, :98:33, :102:80]\n entries_1_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h1)\t// @[loop.scala:92:27, :99:33, :102:80]\n entries_1_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h1)\t// @[loop.scala:92:27, :102:{33,80}]\n entries_1_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h1)\t// @[loop.scala:92:27, :101:33, :102:80]\n entries_1_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h2) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_2_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_2_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_2_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_2_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_2_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_2_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_2_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_2_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_2_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_2_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h2)\t// @[loop.scala:92:27, :98:33]\n entries_2_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h2)\t// @[loop.scala:92:27, :99:33]\n entries_2_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h2)\t// @[loop.scala:92:27, :102:33]\n entries_2_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h2)\t// @[loop.scala:92:27, :101:33]\n entries_2_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h3) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_3_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_3_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_3_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_3_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_3_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_3_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_3_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_3_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_3_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_3_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h3)\t// @[loop.scala:92:27, :98:33]\n entries_3_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h3)\t// @[loop.scala:92:27, :99:33]\n entries_3_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h3)\t// @[loop.scala:92:27, :102:33]\n entries_3_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h3)\t// @[loop.scala:92:27, :101:33]\n entries_3_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h4) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_4_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_4_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_4_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_4_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_4_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_4_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_4_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_4_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_4_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_4_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h4)\t// @[loop.scala:92:27, :98:33]\n entries_4_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h4)\t// @[loop.scala:92:27, :99:33]\n entries_4_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h4)\t// @[loop.scala:92:27, :102:33]\n entries_4_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h4)\t// @[loop.scala:92:27, :101:33]\n entries_4_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h5) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_5_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_5_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_5_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_5_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_5_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_5_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_5_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_5_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_5_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_5_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h5)\t// @[loop.scala:92:27, :98:33]\n entries_5_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h5)\t// @[loop.scala:92:27, :99:33]\n entries_5_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h5)\t// @[loop.scala:92:27, :102:33]\n entries_5_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h5)\t// @[loop.scala:92:27, :101:33]\n entries_5_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h6) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_6_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_6_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_6_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_6_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_6_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_6_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_6_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_6_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_6_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_6_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h6)\t// @[loop.scala:92:27, :98:33]\n entries_6_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h6)\t// @[loop.scala:92:27, :99:33]\n entries_6_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h6)\t// @[loop.scala:92:27, :102:33]\n entries_6_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h6)\t// @[loop.scala:92:27, :101:33]\n entries_6_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h7) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_7_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_7_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_7_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_7_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_7_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_7_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_7_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_7_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_7_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_7_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h7)\t// @[loop.scala:92:27, :98:33]\n entries_7_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h7)\t// @[loop.scala:92:27, :99:33]\n entries_7_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h7)\t// @[loop.scala:92:27, :102:33]\n entries_7_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h7)\t// @[loop.scala:92:27, :101:33]\n entries_7_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h8) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_8_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_8_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_8_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_8_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_8_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_8_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_8_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_8_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_8_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_8_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h8)\t// @[loop.scala:92:27, :98:33]\n entries_8_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h8)\t// @[loop.scala:92:27, :99:33]\n entries_8_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h8)\t// @[loop.scala:92:27, :102:33]\n entries_8_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h8)\t// @[loop.scala:92:27, :101:33]\n entries_8_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'h9) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_9_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_9_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_9_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_9_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_9_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_9_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_9_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_9_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_9_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_9_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h9)\t// @[loop.scala:92:27, :98:33]\n entries_9_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'h9)\t// @[loop.scala:92:27, :99:33]\n entries_9_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'h9)\t// @[loop.scala:92:27, :102:33]\n entries_9_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'h9)\t// @[loop.scala:92:27, :101:33]\n entries_9_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'hA) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_10_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_10_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_10_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_10_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_10_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_10_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_10_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_10_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_10_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_10_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hA)\t// @[loop.scala:92:27, :98:33]\n entries_10_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'hA)\t// @[loop.scala:92:27, :99:33]\n entries_10_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hA)\t// @[loop.scala:92:27, :102:33]\n entries_10_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'hA)\t// @[loop.scala:92:27, :101:33]\n entries_10_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'hB) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_11_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_11_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_11_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_11_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_11_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_11_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_11_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_11_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_11_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_11_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hB)\t// @[loop.scala:92:27, :98:33]\n entries_11_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'hB)\t// @[loop.scala:92:27, :99:33]\n entries_11_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hB)\t// @[loop.scala:92:27, :102:33]\n entries_11_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'hB)\t// @[loop.scala:92:27, :101:33]\n entries_11_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'hC) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_12_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_12_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_12_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_12_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_12_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_12_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_12_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_12_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_12_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_12_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hC)\t// @[loop.scala:92:27, :98:33]\n entries_12_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'hC)\t// @[loop.scala:92:27, :99:33]\n entries_12_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hC)\t// @[loop.scala:92:27, :102:33]\n entries_12_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'hC)\t// @[loop.scala:92:27, :101:33]\n entries_12_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'hD) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_13_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_13_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_13_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_13_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_13_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_13_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_13_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_13_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_13_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_13_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hD)\t// @[loop.scala:92:27, :98:33]\n entries_13_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'hD)\t// @[loop.scala:92:27, :99:33]\n entries_13_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hD)\t// @[loop.scala:92:27, :102:33]\n entries_13_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'hD)\t// @[loop.scala:92:27, :101:33]\n entries_13_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & reset_idx == 4'hE) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_14_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_14_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_14_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_14_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_14_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_14_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_14_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_14_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_14_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_14_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hE)\t// @[loop.scala:92:27, :98:33]\n entries_14_age <= 3'h7;\t// @[loop.scala:65:22]\n if (f4_idx[3:0] == 4'hE)\t// @[loop.scala:92:27, :99:33]\n entries_14_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (f4_idx[3:0] == 4'hE)\t// @[loop.scala:92:27, :102:33]\n entries_14_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (f4_idx[3:0] == 4'hE)\t// @[loop.scala:92:27, :101:33]\n entries_14_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n if (doing_reset & (&reset_idx)) begin\t// @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]\n entries_15_tag <= 10'h0;\t// @[loop.scala:65:22]\n entries_15_conf <= 3'h0;\t// @[loop.scala:65:22]\n entries_15_age <= 3'h0;\t// @[loop.scala:65:22]\n entries_15_p_cnt <= 10'h0;\t// @[loop.scala:65:22]\n entries_15_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin\t// @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]\n entries_15_tag <= wentry_tag;\t// @[loop.scala:65:22, :112:26]\n entries_15_conf <= wentry_conf;\t// @[loop.scala:65:22, :112:26]\n entries_15_age <= wentry_age;\t// @[loop.scala:65:22, :112:26]\n entries_15_p_cnt <= wentry_p_cnt;\t// @[loop.scala:65:22, :112:26]\n entries_15_s_cnt <= wentry_s_cnt;\t// @[loop.scala:65:22, :112:26]\n end\n else if (_GEN_8) begin\t// @[loop.scala:65:22, :95:20, :96:38, :97:68]\n if (_T_12) begin\t// @[loop.scala:97:42]\n if (&(f4_idx[3:0]))\t// @[loop.scala:92:27, :98:33]\n entries_15_age <= 3'h7;\t// @[loop.scala:65:22]\n if (&(f4_idx[3:0]))\t// @[loop.scala:92:27, :99:33]\n entries_15_s_cnt <= 10'h0;\t// @[loop.scala:65:22]\n end\n else begin\t// @[loop.scala:97:42]\n if (&(f4_idx[3:0]))\t// @[loop.scala:92:27, :102:33]\n entries_15_age <= _entries_age_T_3;\t// @[loop.scala:65:22, :102:39]\n if (&(f4_idx[3:0]))\t// @[loop.scala:92:27, :101:33]\n entries_15_s_cnt <= _entries_s_cnt_T_1;\t// @[loop.scala:65:22, :101:44]\n end\n end\n f3_entry_tag <= f2_entry_tag;\t// @[loop.scala:66:28, :72:27]\n f3_entry_conf <= f2_entry_conf;\t// @[loop.scala:66:28, :72:27]\n f3_entry_age <= f2_entry_age;\t// @[loop.scala:66:28, :72:27]\n f3_entry_p_cnt <= f2_entry_p_cnt;\t// @[loop.scala:66:28, :72:27]\n f3_entry_s_cnt <= f2_entry_s_cnt;\t// @[loop.scala:66:28, :72:27]\n f3_scnt_REG <= io_f2_req_idx_0;\t// @[loop.scala:39:9, :73:69]\n f3_tag <= _f3_tag_T;\t// @[loop.scala:76:{27,41}]\n f4_fire <= io_f3_req_fire_0;\t// @[loop.scala:39:9, :88:27]\n f4_entry_tag <= f3_entry_tag;\t// @[loop.scala:72:27, :89:27]\n f4_entry_conf <= f3_entry_conf;\t// @[loop.scala:72:27, :89:27]\n f4_entry_age <= f3_entry_age;\t// @[loop.scala:72:27, :89:27]\n f4_entry_p_cnt <= f3_entry_p_cnt;\t// @[loop.scala:72:27, :89:27]\n f4_entry_s_cnt <= f3_entry_s_cnt;\t// @[loop.scala:72:27, :89:27]\n f4_tag <= f3_tag;\t// @[loop.scala:76:27, :90:27]\n f4_scnt <= f3_scnt;\t// @[loop.scala:73:23, :91:27]\n f4_idx_REG <= io_f2_req_idx_0;\t// @[loop.scala:39:9, :92:35]\n f4_idx <= f4_idx_REG;\t// @[loop.scala:92:{27,35}]\n always @(posedge)\n assign io_f3_pred = io_f3_pred_0;\t// @[loop.scala:39:9]\n assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0;\t// @[loop.scala:39:9]\nendmodule"}}},{"rowIdx":35494,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_35 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_35(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35495,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_89 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_89(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35496,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_3 : \n output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}} \n\n\n inst mulFullRaw of MulFullRawFN_3 \n connect mulFullRaw.io.a.sig, io.a.sig \n connect mulFullRaw.io.a.sExp, io.a.sExp \n connect mulFullRaw.io.a.sign, io.a.sign \n connect mulFullRaw.io.a.isZero, io.a.isZero \n connect mulFullRaw.io.a.isInf, io.a.isInf \n connect mulFullRaw.io.a.isNaN, io.a.isNaN \n connect mulFullRaw.io.b.sig, io.b.sig \n connect mulFullRaw.io.b.sExp, io.b.sExp \n connect mulFullRaw.io.b.sign, io.b.sign \n connect mulFullRaw.io.b.isZero, io.b.isZero \n connect mulFullRaw.io.b.isInf, io.b.isInf \n connect mulFullRaw.io.b.isNaN, io.b.isNaN \n connect io.invalidExc, mulFullRaw.io.invalidExc \n connect io.rawOut, mulFullRaw.io.rawOut \n node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22) \n node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0) \n node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1) \n node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2) \n connect io.rawOut.sig, _io_rawOut_sig_T_3"},"response":{"kind":"string","value":"module MulRawFN_3(\t// @[MulRecFN.scala:75:7]\n input io_a_isNaN,\t// @[MulRecFN.scala:77:16]\n input io_a_isInf,\t// @[MulRecFN.scala:77:16]\n input io_a_isZero,\t// @[MulRecFN.scala:77:16]\n input io_a_sign,\t// @[MulRecFN.scala:77:16]\n input [9:0] io_a_sExp,\t// @[MulRecFN.scala:77:16]\n input [24:0] io_a_sig,\t// @[MulRecFN.scala:77:16]\n input io_b_isNaN,\t// @[MulRecFN.scala:77:16]\n input io_b_isInf,\t// @[MulRecFN.scala:77:16]\n input io_b_isZero,\t// @[MulRecFN.scala:77:16]\n input io_b_sign,\t// @[MulRecFN.scala:77:16]\n input [9:0] io_b_sExp,\t// @[MulRecFN.scala:77:16]\n input [24:0] io_b_sig,\t// @[MulRecFN.scala:77:16]\n output io_invalidExc,\t// @[MulRecFN.scala:77:16]\n output io_rawOut_isNaN,\t// @[MulRecFN.scala:77:16]\n output io_rawOut_isInf,\t// @[MulRecFN.scala:77:16]\n output io_rawOut_isZero,\t// @[MulRecFN.scala:77:16]\n output io_rawOut_sign,\t// @[MulRecFN.scala:77:16]\n output [9:0] io_rawOut_sExp,\t// @[MulRecFN.scala:77:16]\n output [26:0] io_rawOut_sig\t// @[MulRecFN.scala:77:16]\n);\n\n wire [47:0] _mulFullRaw_io_rawOut_sig;\t// @[MulRecFN.scala:84:28]\n wire io_a_isNaN_0 = io_a_isNaN;\t// @[MulRecFN.scala:75:7]\n wire io_a_isInf_0 = io_a_isInf;\t// @[MulRecFN.scala:75:7]\n wire io_a_isZero_0 = io_a_isZero;\t// @[MulRecFN.scala:75:7]\n wire io_a_sign_0 = io_a_sign;\t// @[MulRecFN.scala:75:7]\n wire [9:0] io_a_sExp_0 = io_a_sExp;\t// @[MulRecFN.scala:75:7]\n wire [24:0] io_a_sig_0 = io_a_sig;\t// @[MulRecFN.scala:75:7]\n wire io_b_isNaN_0 = io_b_isNaN;\t// @[MulRecFN.scala:75:7]\n wire io_b_isInf_0 = io_b_isInf;\t// @[MulRecFN.scala:75:7]\n wire io_b_isZero_0 = io_b_isZero;\t// @[MulRecFN.scala:75:7]\n wire io_b_sign_0 = io_b_sign;\t// @[MulRecFN.scala:75:7]\n wire [9:0] io_b_sExp_0 = io_b_sExp;\t// @[MulRecFN.scala:75:7]\n wire [24:0] io_b_sig_0 = io_b_sig;\t// @[MulRecFN.scala:75:7]\n wire [26:0] _io_rawOut_sig_T_3;\t// @[MulRecFN.scala:93:10]\n wire io_rawOut_isNaN_0;\t// @[MulRecFN.scala:75:7]\n wire io_rawOut_isInf_0;\t// @[MulRecFN.scala:75:7]\n wire io_rawOut_isZero_0;\t// @[MulRecFN.scala:75:7]\n wire io_rawOut_sign_0;\t// @[MulRecFN.scala:75:7]\n wire [9:0] io_rawOut_sExp_0;\t// @[MulRecFN.scala:75:7]\n wire [26:0] io_rawOut_sig_0;\t// @[MulRecFN.scala:75:7]\n wire io_invalidExc_0;\t// @[MulRecFN.scala:75:7]\n wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22];\t// @[MulRecFN.scala:84:28, :93:15]\n wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0];\t// @[MulRecFN.scala:84:28, :93:37]\n wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1;\t// @[MulRecFN.scala:93:{37,55}]\n assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2};\t// @[MulRecFN.scala:93:{10,15,55}]\n assign io_rawOut_sig_0 = _io_rawOut_sig_T_3;\t// @[MulRecFN.scala:75:7, :93:10]\n MulFullRawFN_3 mulFullRaw (\t// @[MulRecFN.scala:84:28]\n .io_a_isNaN (io_a_isNaN_0),\t// @[MulRecFN.scala:75:7]\n .io_a_isInf (io_a_isInf_0),\t// @[MulRecFN.scala:75:7]\n .io_a_isZero (io_a_isZero_0),\t// @[MulRecFN.scala:75:7]\n .io_a_sign (io_a_sign_0),\t// @[MulRecFN.scala:75:7]\n .io_a_sExp (io_a_sExp_0),\t// @[MulRecFN.scala:75:7]\n .io_a_sig (io_a_sig_0),\t// @[MulRecFN.scala:75:7]\n .io_b_isNaN (io_b_isNaN_0),\t// @[MulRecFN.scala:75:7]\n .io_b_isInf (io_b_isInf_0),\t// @[MulRecFN.scala:75:7]\n .io_b_isZero (io_b_isZero_0),\t// @[MulRecFN.scala:75:7]\n .io_b_sign (io_b_sign_0),\t// @[MulRecFN.scala:75:7]\n .io_b_sExp (io_b_sExp_0),\t// @[MulRecFN.scala:75:7]\n .io_b_sig (io_b_sig_0),\t// @[MulRecFN.scala:75:7]\n .io_invalidExc (io_invalidExc_0),\n .io_rawOut_isNaN (io_rawOut_isNaN_0),\n .io_rawOut_isInf (io_rawOut_isInf_0),\n .io_rawOut_isZero (io_rawOut_isZero_0),\n .io_rawOut_sign (io_rawOut_sign_0),\n .io_rawOut_sExp (io_rawOut_sExp_0),\n .io_rawOut_sig (_mulFullRaw_io_rawOut_sig)\n );\t// @[MulRecFN.scala:84:28]\n assign io_invalidExc = io_invalidExc_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_isNaN = io_rawOut_isNaN_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_isInf = io_rawOut_isInf_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_isZero = io_rawOut_isZero_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_sign = io_rawOut_sign_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_sExp = io_rawOut_sExp_0;\t// @[MulRecFN.scala:75:7]\n assign io_rawOut_sig = io_rawOut_sig_0;\t// @[MulRecFN.scala:75:7]\nendmodule"}}},{"rowIdx":35497,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_71 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_71(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35498,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_31 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<4>, q : UInt<4>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n node _output_T_2 = asAsyncReset(reset) \n node _output_T_3 = bits(io.d, 1, 1) \n inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294 \n connect output_chain_1.clock, clock\n\n connect output_chain_1.reset, _output_T_2\n\n connect output_chain_1.io.d, _output_T_3 \n wire output_1 : UInt<1> \n connect output_1, output_chain_1.io.q \n node _output_T_4 = asAsyncReset(reset) \n node _output_T_5 = bits(io.d, 2, 2) \n inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_295 \n connect output_chain_2.clock, clock\n\n connect output_chain_2.reset, _output_T_4\n\n connect output_chain_2.io.d, _output_T_5 \n wire output_2 : UInt<1> \n connect output_2, output_chain_2.io.q \n node _output_T_6 = asAsyncReset(reset) \n node _output_T_7 = bits(io.d, 3, 3) \n inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_296 \n connect output_chain_3.clock, clock\n\n connect output_chain_3.reset, _output_T_6\n\n connect output_chain_3.io.d, _output_T_7 \n wire output_3 : UInt<1> \n connect output_3, output_chain_3.io.q \n node io_q_lo = cat(output_1, output_0) \n node io_q_hi = cat(output_3, output_2) \n node _io_q_T = cat(io_q_hi, io_q_lo) \n connect io.q, _io_q_T"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w4_d3_i0_31(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input [3:0] io_d,\t// @[ShiftReg.scala:36:14]\n output [3:0] io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire [3:0] io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_2 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_4 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_6 = reset;\t// @[SynchronizerReg.scala:86:21]\n wire [3:0] _io_q_T;\t// @[SynchronizerReg.scala:90:14]\n wire [3:0] io_q_0;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T_1 = io_d_0[0];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire _output_T_3 = io_d_0[1];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_1;\t// @[ShiftReg.scala:48:24]\n wire _output_T_5 = io_d_0[2];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_2;\t// @[ShiftReg.scala:48:24]\n wire _output_T_7 = io_d_0[3];\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_3;\t// @[ShiftReg.scala:48:24]\n wire [1:0] io_q_lo = {output_1, output_0};\t// @[SynchronizerReg.scala:90:14]\n wire [1:0] io_q_hi = {output_3, output_2};\t// @[SynchronizerReg.scala:90:14]\n assign _io_q_T = {io_q_hi, io_q_lo};\t// @[SynchronizerReg.scala:90:14]\n assign io_q_0 = _io_q_T;\t// @[SynchronizerReg.scala:80:7, :90:14]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294 output_chain_1 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_2),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_3),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_1)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_295 output_chain_2 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_4),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_5),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_2)\n );\t// @[ShiftReg.scala:45:23]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_296 output_chain_3 (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T_6),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_7),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_3)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":35499,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_83 : \n input clock : Clock \n input reset : Reset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_167 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_83(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_167 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":354,"numItemsPerPage":100,"numTotalItems":35529,"offset":35400,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc0NzEwNzU4Mywic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NDcxMTExODMsImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.JyzuxBeqGtWSI51c8nCEyYX4GJ2ZmB_nIpF5t61rvFINsoNGDKZbuVs0OFTWgpQUDLOhRDCVMAdhYzYAFeNrAg","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h1f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<5>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 2, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 4, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h5))
node mask_sub_sub_sub_sub_size = bits(mask_sizeOH, 4, 4)
node mask_sub_sub_sub_sub_bit = bits(io.in.a.bits.address, 4, 4)
node mask_sub_sub_sub_sub_nbit = eq(mask_sub_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_nbit)
node _mask_sub_sub_sub_sub_acc_T = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_0_2)
node mask_sub_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T)
node mask_sub_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_sub_bit)
node _mask_sub_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_sub_size, mask_sub_sub_sub_sub_1_2)
node mask_sub_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_sub_acc_T_1)
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(mask_sub_sub_sub_sub_0_2, mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_sub_2_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_2_2)
node mask_sub_sub_sub_2_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_3_2 = and(mask_sub_sub_sub_sub_1_2, mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_3_2)
node mask_sub_sub_sub_3_1 = or(mask_sub_sub_sub_sub_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_sub_4_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size, mask_sub_sub_4_2)
node mask_sub_sub_4_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_5_2 = and(mask_sub_sub_sub_2_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size, mask_sub_sub_5_2)
node mask_sub_sub_5_1 = or(mask_sub_sub_sub_2_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_6_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size, mask_sub_sub_6_2)
node mask_sub_sub_6_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_7_2 = and(mask_sub_sub_sub_3_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size, mask_sub_sub_7_2)
node mask_sub_sub_7_1 = or(mask_sub_sub_sub_3_1, _mask_sub_sub_acc_T_7)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_sub_8_2 = and(mask_sub_sub_4_2, mask_sub_nbit)
node _mask_sub_acc_T_8 = and(mask_sub_size, mask_sub_8_2)
node mask_sub_8_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_8)
node mask_sub_9_2 = and(mask_sub_sub_4_2, mask_sub_bit)
node _mask_sub_acc_T_9 = and(mask_sub_size, mask_sub_9_2)
node mask_sub_9_1 = or(mask_sub_sub_4_1, _mask_sub_acc_T_9)
node mask_sub_10_2 = and(mask_sub_sub_5_2, mask_sub_nbit)
node _mask_sub_acc_T_10 = and(mask_sub_size, mask_sub_10_2)
node mask_sub_10_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_10)
node mask_sub_11_2 = and(mask_sub_sub_5_2, mask_sub_bit)
node _mask_sub_acc_T_11 = and(mask_sub_size, mask_sub_11_2)
node mask_sub_11_1 = or(mask_sub_sub_5_1, _mask_sub_acc_T_11)
node mask_sub_12_2 = and(mask_sub_sub_6_2, mask_sub_nbit)
node _mask_sub_acc_T_12 = and(mask_sub_size, mask_sub_12_2)
node mask_sub_12_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_12)
node mask_sub_13_2 = and(mask_sub_sub_6_2, mask_sub_bit)
node _mask_sub_acc_T_13 = and(mask_sub_size, mask_sub_13_2)
node mask_sub_13_1 = or(mask_sub_sub_6_1, _mask_sub_acc_T_13)
node mask_sub_14_2 = and(mask_sub_sub_7_2, mask_sub_nbit)
node _mask_sub_acc_T_14 = and(mask_sub_size, mask_sub_14_2)
node mask_sub_14_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_14)
node mask_sub_15_2 = and(mask_sub_sub_7_2, mask_sub_bit)
node _mask_sub_acc_T_15 = and(mask_sub_size, mask_sub_15_2)
node mask_sub_15_1 = or(mask_sub_sub_7_1, _mask_sub_acc_T_15)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_eq_16 = and(mask_sub_8_2, mask_nbit)
node _mask_acc_T_16 = and(mask_size, mask_eq_16)
node mask_acc_16 = or(mask_sub_8_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_8_2, mask_bit)
node _mask_acc_T_17 = and(mask_size, mask_eq_17)
node mask_acc_17 = or(mask_sub_8_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_9_2, mask_nbit)
node _mask_acc_T_18 = and(mask_size, mask_eq_18)
node mask_acc_18 = or(mask_sub_9_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_9_2, mask_bit)
node _mask_acc_T_19 = and(mask_size, mask_eq_19)
node mask_acc_19 = or(mask_sub_9_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_10_2, mask_nbit)
node _mask_acc_T_20 = and(mask_size, mask_eq_20)
node mask_acc_20 = or(mask_sub_10_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_10_2, mask_bit)
node _mask_acc_T_21 = and(mask_size, mask_eq_21)
node mask_acc_21 = or(mask_sub_10_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_11_2, mask_nbit)
node _mask_acc_T_22 = and(mask_size, mask_eq_22)
node mask_acc_22 = or(mask_sub_11_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_11_2, mask_bit)
node _mask_acc_T_23 = and(mask_size, mask_eq_23)
node mask_acc_23 = or(mask_sub_11_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_12_2, mask_nbit)
node _mask_acc_T_24 = and(mask_size, mask_eq_24)
node mask_acc_24 = or(mask_sub_12_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_12_2, mask_bit)
node _mask_acc_T_25 = and(mask_size, mask_eq_25)
node mask_acc_25 = or(mask_sub_12_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_13_2, mask_nbit)
node _mask_acc_T_26 = and(mask_size, mask_eq_26)
node mask_acc_26 = or(mask_sub_13_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_13_2, mask_bit)
node _mask_acc_T_27 = and(mask_size, mask_eq_27)
node mask_acc_27 = or(mask_sub_13_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_14_2, mask_nbit)
node _mask_acc_T_28 = and(mask_size, mask_eq_28)
node mask_acc_28 = or(mask_sub_14_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_14_2, mask_bit)
node _mask_acc_T_29 = and(mask_size, mask_eq_29)
node mask_acc_29 = or(mask_sub_14_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_15_2, mask_nbit)
node _mask_acc_T_30 = and(mask_size, mask_eq_30)
node mask_acc_30 = or(mask_sub_15_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_15_2, mask_bit)
node _mask_acc_T_31 = and(mask_size, mask_eq_31)
node mask_acc_31 = or(mask_sub_15_1, _mask_acc_T_31)
node mask_lo_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo_lo = cat(mask_lo_lo_lo_hi, mask_lo_lo_lo_lo)
node mask_lo_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_lo_hi = cat(mask_lo_lo_hi_hi, mask_lo_lo_hi_lo)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_lo_hi_lo = cat(mask_lo_hi_lo_hi, mask_lo_hi_lo_lo)
node mask_lo_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_lo_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_lo_hi_hi = cat(mask_lo_hi_hi_hi, mask_lo_hi_hi_lo)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo_lo = cat(mask_acc_17, mask_acc_16)
node mask_hi_lo_lo_hi = cat(mask_acc_19, mask_acc_18)
node mask_hi_lo_lo = cat(mask_hi_lo_lo_hi, mask_hi_lo_lo_lo)
node mask_hi_lo_hi_lo = cat(mask_acc_21, mask_acc_20)
node mask_hi_lo_hi_hi = cat(mask_acc_23, mask_acc_22)
node mask_hi_lo_hi = cat(mask_hi_lo_hi_hi, mask_hi_lo_hi_lo)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo_lo = cat(mask_acc_25, mask_acc_24)
node mask_hi_hi_lo_hi = cat(mask_acc_27, mask_acc_26)
node mask_hi_hi_lo = cat(mask_hi_hi_lo_hi, mask_hi_hi_lo_lo)
node mask_hi_hi_hi_lo = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_hi = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_hi = cat(mask_hi_hi_hi_hi, mask_hi_hi_hi_lo)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h1f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h1f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<14>(0h2000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_37, _T_42)
node _T_74 = or(_T_73, _T_47)
node _T_75 = or(_T_74, _T_52)
node _T_76 = or(_T_75, _T_57)
node _T_77 = or(_T_76, _T_62)
node _T_78 = or(_T_77, _T_67)
node _T_79 = or(_T_78, _T_72)
node _T_80 = and(_T_32, _T_79)
node _T_81 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_84 = cvt(_T_83)
node _T_85 = and(_T_84, asSInt(UInt<17>(0h10000)))
node _T_86 = asSInt(_T_85)
node _T_87 = eq(_T_86, asSInt(UInt<1>(0h0)))
node _T_88 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_89 = cvt(_T_88)
node _T_90 = and(_T_89, asSInt(UInt<29>(0h10000000)))
node _T_91 = asSInt(_T_90)
node _T_92 = eq(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = or(_T_87, _T_92)
node _T_94 = and(_T_82, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_80)
node _T_96 = or(_T_95, _T_94)
node _T_97 = and(_T_31, _T_96)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_97, UInt<1>(0h1), "") : assert_2
node _T_101 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_102 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<14>(0h2000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<18>(0h2f000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<13>(0h1000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<17>(0h10000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<27>(0h4000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<13>(0h1000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_151 = cvt(_T_150)
node _T_152 = and(_T_151, asSInt(UInt<29>(0h10000000)))
node _T_153 = asSInt(_T_152)
node _T_154 = eq(_T_153, asSInt(UInt<1>(0h0)))
node _T_155 = or(_T_109, _T_114)
node _T_156 = or(_T_155, _T_119)
node _T_157 = or(_T_156, _T_124)
node _T_158 = or(_T_157, _T_129)
node _T_159 = or(_T_158, _T_134)
node _T_160 = or(_T_159, _T_139)
node _T_161 = or(_T_160, _T_144)
node _T_162 = or(_T_161, _T_149)
node _T_163 = or(_T_162, _T_154)
node _T_164 = and(_T_104, _T_163)
node _T_165 = or(UInt<1>(0h0), _T_164)
node _T_166 = and(UInt<1>(0h0), _T_165)
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(_T_166, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_166, UInt<1>(0h1), "") : assert_3
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_173 = geq(io.in.a.bits.size, UInt<3>(0h5))
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_173, UInt<1>(0h1), "") : assert_5
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(is_aligned, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_180 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_180, UInt<1>(0h1), "") : assert_7
node _T_184 = not(io.in.a.bits.mask)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_185, UInt<1>(0h1), "") : assert_8
node _T_189 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_189, UInt<1>(0h1), "") : assert_9
node _T_193 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_193 :
node _T_194 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_195 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_197 = shr(io.in.a.bits.source, 5)
node _T_198 = eq(_T_197, UInt<1>(0h0))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_2, UInt<5>(0h1f))
node _T_202 = and(_T_200, _T_201)
node _T_203 = and(_T_196, _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_206 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<14>(0h2000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<17>(0h10000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<18>(0h2f000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<17>(0h10000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_232 = cvt(_T_231)
node _T_233 = and(_T_232, asSInt(UInt<13>(0h1000)))
node _T_234 = asSInt(_T_233)
node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0)))
node _T_236 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_237 = cvt(_T_236)
node _T_238 = and(_T_237, asSInt(UInt<27>(0h4000000)))
node _T_239 = asSInt(_T_238)
node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0)))
node _T_241 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<13>(0h1000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = or(_T_210, _T_215)
node _T_247 = or(_T_246, _T_220)
node _T_248 = or(_T_247, _T_225)
node _T_249 = or(_T_248, _T_230)
node _T_250 = or(_T_249, _T_235)
node _T_251 = or(_T_250, _T_240)
node _T_252 = or(_T_251, _T_245)
node _T_253 = and(_T_205, _T_252)
node _T_254 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_255 = or(UInt<1>(0h0), _T_254)
node _T_256 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<29>(0h10000000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = or(_T_260, _T_265)
node _T_267 = and(_T_255, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_253)
node _T_269 = or(_T_268, _T_267)
node _T_270 = and(_T_204, _T_269)
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_270, UInt<1>(0h1), "") : assert_10
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<14>(0h2000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<13>(0h1000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<18>(0h2f000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<27>(0h4000000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<29>(0h10000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = or(_T_282, _T_287)
node _T_329 = or(_T_328, _T_292)
node _T_330 = or(_T_329, _T_297)
node _T_331 = or(_T_330, _T_302)
node _T_332 = or(_T_331, _T_307)
node _T_333 = or(_T_332, _T_312)
node _T_334 = or(_T_333, _T_317)
node _T_335 = or(_T_334, _T_322)
node _T_336 = or(_T_335, _T_327)
node _T_337 = and(_T_277, _T_336)
node _T_338 = or(UInt<1>(0h0), _T_337)
node _T_339 = and(UInt<1>(0h0), _T_338)
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_339, UInt<1>(0h1), "") : assert_11
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_346 = geq(io.in.a.bits.size, UInt<3>(0h5))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_346, UInt<1>(0h1), "") : assert_13
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(is_aligned, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_353 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(_T_353, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_353, UInt<1>(0h1), "") : assert_15
node _T_357 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_357, UInt<1>(0h1), "") : assert_16
node _T_361 = not(io.in.a.bits.mask)
node _T_362 = eq(_T_361, UInt<1>(0h0))
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_362, UInt<1>(0h1), "") : assert_17
node _T_366 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_366, UInt<1>(0h1), "") : assert_18
node _T_370 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_370 :
node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_373 = and(_T_371, _T_372)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_374 = shr(io.in.a.bits.source, 5)
node _T_375 = eq(_T_374, UInt<1>(0h0))
node _T_376 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_377 = and(_T_375, _T_376)
node _T_378 = leq(uncommonBits_3, UInt<5>(0h1f))
node _T_379 = and(_T_377, _T_378)
node _T_380 = and(_T_373, _T_379)
node _T_381 = or(UInt<1>(0h0), _T_380)
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_381, UInt<1>(0h1), "") : assert_19
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = and(_T_388, _T_393)
node _T_395 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_396 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_397 = and(_T_395, _T_396)
node _T_398 = or(UInt<1>(0h0), _T_397)
node _T_399 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<14>(0h2000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<18>(0h2f000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<17>(0h10000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<13>(0h1000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<17>(0h10000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<27>(0h4000000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<13>(0h1000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<29>(0h10000000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = or(_T_403, _T_408)
node _T_445 = or(_T_444, _T_413)
node _T_446 = or(_T_445, _T_418)
node _T_447 = or(_T_446, _T_423)
node _T_448 = or(_T_447, _T_428)
node _T_449 = or(_T_448, _T_433)
node _T_450 = or(_T_449, _T_438)
node _T_451 = or(_T_450, _T_443)
node _T_452 = and(_T_398, _T_451)
node _T_453 = or(UInt<1>(0h0), _T_394)
node _T_454 = or(_T_453, _T_452)
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_454, UInt<1>(0h1), "") : assert_20
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(is_aligned, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_464 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_464, UInt<1>(0h1), "") : assert_23
node _T_468 = eq(io.in.a.bits.mask, mask)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_468, UInt<1>(0h1), "") : assert_24
node _T_472 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_472, UInt<1>(0h1), "") : assert_25
node _T_476 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_476 :
node _T_477 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_478 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_479 = and(_T_477, _T_478)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_480 = shr(io.in.a.bits.source, 5)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_483 = and(_T_481, _T_482)
node _T_484 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_485 = and(_T_483, _T_484)
node _T_486 = and(_T_479, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_489 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_490 = and(_T_488, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = and(_T_491, _T_496)
node _T_498 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_499 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_500 = and(_T_498, _T_499)
node _T_501 = or(UInt<1>(0h0), _T_500)
node _T_502 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<14>(0h2000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<18>(0h2f000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<17>(0h10000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_518 = cvt(_T_517)
node _T_519 = and(_T_518, asSInt(UInt<13>(0h1000)))
node _T_520 = asSInt(_T_519)
node _T_521 = eq(_T_520, asSInt(UInt<1>(0h0)))
node _T_522 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_523 = cvt(_T_522)
node _T_524 = and(_T_523, asSInt(UInt<17>(0h10000)))
node _T_525 = asSInt(_T_524)
node _T_526 = eq(_T_525, asSInt(UInt<1>(0h0)))
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<27>(0h4000000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<13>(0h1000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<29>(0h10000000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = or(_T_506, _T_511)
node _T_543 = or(_T_542, _T_516)
node _T_544 = or(_T_543, _T_521)
node _T_545 = or(_T_544, _T_526)
node _T_546 = or(_T_545, _T_531)
node _T_547 = or(_T_546, _T_536)
node _T_548 = or(_T_547, _T_541)
node _T_549 = and(_T_501, _T_548)
node _T_550 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<17>(0h10000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_497)
node _T_558 = or(_T_557, _T_549)
node _T_559 = or(_T_558, _T_556)
node _T_560 = and(_T_487, _T_559)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_560, UInt<1>(0h1), "") : assert_26
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(is_aligned, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_570 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_570, UInt<1>(0h1), "") : assert_29
node _T_574 = eq(io.in.a.bits.mask, mask)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_574, UInt<1>(0h1), "") : assert_30
node _T_578 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_578 :
node _T_579 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_580 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_582 = shr(io.in.a.bits.source, 5)
node _T_583 = eq(_T_582, UInt<1>(0h0))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_587 = and(_T_585, _T_586)
node _T_588 = and(_T_581, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = and(_T_593, _T_598)
node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_601 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_602 = and(_T_600, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_602)
node _T_604 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<14>(0h2000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<18>(0h2f000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<17>(0h10000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<27>(0h4000000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<13>(0h1000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<29>(0h10000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = or(_T_608, _T_613)
node _T_645 = or(_T_644, _T_618)
node _T_646 = or(_T_645, _T_623)
node _T_647 = or(_T_646, _T_628)
node _T_648 = or(_T_647, _T_633)
node _T_649 = or(_T_648, _T_638)
node _T_650 = or(_T_649, _T_643)
node _T_651 = and(_T_603, _T_650)
node _T_652 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_653 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<17>(0h10000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = and(_T_652, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_599)
node _T_660 = or(_T_659, _T_651)
node _T_661 = or(_T_660, _T_658)
node _T_662 = and(_T_589, _T_661)
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(_T_662, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_662, UInt<1>(0h1), "") : assert_31
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(is_aligned, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_672 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_673 = asUInt(reset)
node _T_674 = eq(_T_673, UInt<1>(0h0))
when _T_674 :
node _T_675 = eq(_T_672, UInt<1>(0h0))
when _T_675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_672, UInt<1>(0h1), "") : assert_34
node _T_676 = not(mask)
node _T_677 = and(io.in.a.bits.mask, _T_676)
node _T_678 = eq(_T_677, UInt<1>(0h0))
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_678, UInt<1>(0h1), "") : assert_35
node _T_682 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_686 = shr(io.in.a.bits.source, 5)
node _T_687 = eq(_T_686, UInt<1>(0h0))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_691 = and(_T_689, _T_690)
node _T_692 = and(_T_685, _T_691)
node _T_693 = or(UInt<1>(0h0), _T_692)
node _T_694 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_695 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_696 = and(_T_694, _T_695)
node _T_697 = or(UInt<1>(0h0), _T_696)
node _T_698 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<14>(0h2000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<18>(0h2f000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<17>(0h10000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<17>(0h10000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<27>(0h4000000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_739 = cvt(_T_738)
node _T_740 = and(_T_739, asSInt(UInt<29>(0h10000000)))
node _T_741 = asSInt(_T_740)
node _T_742 = eq(_T_741, asSInt(UInt<1>(0h0)))
node _T_743 = or(_T_702, _T_707)
node _T_744 = or(_T_743, _T_712)
node _T_745 = or(_T_744, _T_717)
node _T_746 = or(_T_745, _T_722)
node _T_747 = or(_T_746, _T_727)
node _T_748 = or(_T_747, _T_732)
node _T_749 = or(_T_748, _T_737)
node _T_750 = or(_T_749, _T_742)
node _T_751 = and(_T_697, _T_750)
node _T_752 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_753 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_754 = cvt(_T_753)
node _T_755 = and(_T_754, asSInt(UInt<17>(0h10000)))
node _T_756 = asSInt(_T_755)
node _T_757 = eq(_T_756, asSInt(UInt<1>(0h0)))
node _T_758 = and(_T_752, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_751)
node _T_760 = or(_T_759, _T_758)
node _T_761 = and(_T_693, _T_760)
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(_T_761, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_761, UInt<1>(0h1), "") : assert_36
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(is_aligned, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_771 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_771, UInt<1>(0h1), "") : assert_39
node _T_775 = eq(io.in.a.bits.mask, mask)
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(_T_775, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_775, UInt<1>(0h1), "") : assert_40
node _T_779 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_779 :
node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_783 = shr(io.in.a.bits.source, 5)
node _T_784 = eq(_T_783, UInt<1>(0h0))
node _T_785 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_786 = and(_T_784, _T_785)
node _T_787 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_788 = and(_T_786, _T_787)
node _T_789 = and(_T_782, _T_788)
node _T_790 = or(UInt<1>(0h0), _T_789)
node _T_791 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_792 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<14>(0h2000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<18>(0h2f000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<13>(0h1000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<17>(0h10000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<27>(0h4000000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<13>(0h1000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_836 = cvt(_T_835)
node _T_837 = and(_T_836, asSInt(UInt<29>(0h10000000)))
node _T_838 = asSInt(_T_837)
node _T_839 = eq(_T_838, asSInt(UInt<1>(0h0)))
node _T_840 = or(_T_799, _T_804)
node _T_841 = or(_T_840, _T_809)
node _T_842 = or(_T_841, _T_814)
node _T_843 = or(_T_842, _T_819)
node _T_844 = or(_T_843, _T_824)
node _T_845 = or(_T_844, _T_829)
node _T_846 = or(_T_845, _T_834)
node _T_847 = or(_T_846, _T_839)
node _T_848 = and(_T_794, _T_847)
node _T_849 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_850 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_851 = cvt(_T_850)
node _T_852 = and(_T_851, asSInt(UInt<17>(0h10000)))
node _T_853 = asSInt(_T_852)
node _T_854 = eq(_T_853, asSInt(UInt<1>(0h0)))
node _T_855 = and(_T_849, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_848)
node _T_857 = or(_T_856, _T_855)
node _T_858 = and(_T_790, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_858, UInt<1>(0h1), "") : assert_41
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_868 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_868, UInt<1>(0h1), "") : assert_44
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_872, UInt<1>(0h1), "") : assert_45
node _T_876 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_880 = shr(io.in.a.bits.source, 5)
node _T_881 = eq(_T_880, UInt<1>(0h0))
node _T_882 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_883 = and(_T_881, _T_882)
node _T_884 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_885 = and(_T_883, _T_884)
node _T_886 = and(_T_879, _T_885)
node _T_887 = or(UInt<1>(0h0), _T_886)
node _T_888 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_889 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_890 = and(_T_888, _T_889)
node _T_891 = or(UInt<1>(0h0), _T_890)
node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_893 = cvt(_T_892)
node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000)))
node _T_895 = asSInt(_T_894)
node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0)))
node _T_897 = and(_T_891, _T_896)
node _T_898 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_899 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<14>(0h2000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<17>(0h10000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<18>(0h2f000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_915 = cvt(_T_914)
node _T_916 = and(_T_915, asSInt(UInt<17>(0h10000)))
node _T_917 = asSInt(_T_916)
node _T_918 = eq(_T_917, asSInt(UInt<1>(0h0)))
node _T_919 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<13>(0h1000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<27>(0h4000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = or(_T_903, _T_908)
node _T_935 = or(_T_934, _T_913)
node _T_936 = or(_T_935, _T_918)
node _T_937 = or(_T_936, _T_923)
node _T_938 = or(_T_937, _T_928)
node _T_939 = or(_T_938, _T_933)
node _T_940 = and(_T_898, _T_939)
node _T_941 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_942 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_943 = and(_T_941, _T_942)
node _T_944 = or(UInt<1>(0h0), _T_943)
node _T_945 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<17>(0h10000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<29>(0h10000000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = or(_T_949, _T_954)
node _T_956 = and(_T_944, _T_955)
node _T_957 = or(UInt<1>(0h0), _T_897)
node _T_958 = or(_T_957, _T_940)
node _T_959 = or(_T_958, _T_956)
node _T_960 = and(_T_887, _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_960, UInt<1>(0h1), "") : assert_46
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(is_aligned, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_970 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_970, UInt<1>(0h1), "") : assert_49
node _T_974 = eq(io.in.a.bits.mask, mask)
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_974, UInt<1>(0h1), "") : assert_50
node _T_978 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_978, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_982 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_982, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h1f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_986 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_986 :
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_990 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_990, UInt<1>(0h1), "") : assert_54
node _T_994 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_994, UInt<1>(0h1), "") : assert_55
node _T_998 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_998, UInt<1>(0h1), "") : assert_56
node _T_1002 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_57
node _T_1006 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1006 :
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(sink_ok, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1013 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_60
node _T_1017 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_61
node _T_1021 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1022 = asUInt(reset)
node _T_1023 = eq(_T_1022, UInt<1>(0h0))
when _T_1023 :
node _T_1024 = eq(_T_1021, UInt<1>(0h0))
when _T_1024 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1021, UInt<1>(0h1), "") : assert_62
node _T_1025 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_63
node _T_1029 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1030 = or(UInt<1>(0h1), _T_1029)
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_64
node _T_1034 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1034 :
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(sink_ok, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1041 = geq(io.in.d.bits.size, UInt<3>(0h5))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_67
node _T_1045 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_68
node _T_1049 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_69
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_70
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_71
node _T_1063 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_73
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_74
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_75
node _T_1080 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1080 :
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1084 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_77
node _T_1088 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1089 = or(_T_1088, io.in.d.bits.corrupt)
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(_T_1089, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1089, UInt<1>(0h1), "") : assert_78
node _T_1093 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1094 = or(UInt<1>(0h1), _T_1093)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_79
node _T_1098 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1098 :
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1102 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_81
node _T_1106 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_82
node _T_1110 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1111 = or(UInt<1>(0h1), _T_1110)
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1115 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1119 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1123 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 5)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1127 = eq(a_first, UInt<1>(0h0))
node _T_1128 = and(io.in.a.valid, _T_1127)
when _T_1128 :
node _T_1129 = eq(io.in.a.bits.opcode, opcode)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_87
node _T_1133 = eq(io.in.a.bits.param, param)
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_88
node _T_1137 = eq(io.in.a.bits.size, size)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_89
node _T_1141 = eq(io.in.a.bits.source, source)
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_90
node _T_1145 = eq(io.in.a.bits.address, address)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_91
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(_T_1149, a_first)
when _T_1150 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 5)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1151 = eq(d_first, UInt<1>(0h0))
node _T_1152 = and(io.in.d.valid, _T_1151)
when _T_1152 :
node _T_1153 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_92
node _T_1157 = eq(io.in.d.bits.param, param_1)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_93
node _T_1161 = eq(io.in.d.bits.size, size_1)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_94
node _T_1165 = eq(io.in.d.bits.source, source_1)
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_95
node _T_1169 = eq(io.in.d.bits.sink, sink)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_96
node _T_1173 = eq(io.in.d.bits.denied, denied)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_97
node _T_1177 = and(io.in.d.ready, io.in.d.valid)
node _T_1178 = and(_T_1177, d_first)
when _T_1178 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 5)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 5)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<32>
connect a_set, UInt<32>(0h0)
wire a_set_wo_ready : UInt<32>
connect a_set_wo_ready, UInt<32>(0h0)
wire a_opcodes_set : UInt<128>
connect a_opcodes_set, UInt<128>(0h0)
wire a_sizes_set : UInt<256>
connect a_sizes_set, UInt<256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1179 = and(io.in.a.valid, a_first_1)
node _T_1180 = and(_T_1179, UInt<1>(0h1))
when _T_1180 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1181 = and(io.in.a.ready, io.in.a.valid)
node _T_1182 = and(_T_1181, a_first_1)
node _T_1183 = and(_T_1182, UInt<1>(0h1))
when _T_1183 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1184 = dshr(inflight, io.in.a.bits.source)
node _T_1185 = bits(_T_1184, 0, 0)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<32>
connect d_clr, UInt<32>(0h0)
wire d_clr_wo_ready : UInt<32>
connect d_clr_wo_ready, UInt<32>(0h0)
wire d_opcodes_clr : UInt<128>
connect d_opcodes_clr, UInt<128>(0h0)
wire d_sizes_clr : UInt<256>
connect d_sizes_clr, UInt<256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1190 = and(io.in.d.valid, d_first_1)
node _T_1191 = and(_T_1190, UInt<1>(0h1))
node _T_1192 = eq(d_release_ack, UInt<1>(0h0))
node _T_1193 = and(_T_1191, _T_1192)
when _T_1193 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1194 = and(io.in.d.ready, io.in.d.valid)
node _T_1195 = and(_T_1194, d_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
node _T_1197 = eq(d_release_ack, UInt<1>(0h0))
node _T_1198 = and(_T_1196, _T_1197)
when _T_1198 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1203 = dshr(inflight, io.in.d.bits.source)
node _T_1204 = bits(_T_1203, 0, 0)
node _T_1205 = or(_T_1204, same_cycle_resp)
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(_T_1205, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1205, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1209 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1210 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_100
node _T_1215 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_101
else :
node _T_1219 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1220 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1221 = or(_T_1219, _T_1220)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_102
node _T_1225 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_103
node _T_1229 = and(io.in.d.valid, d_first_1)
node _T_1230 = and(_T_1229, a_first_1)
node _T_1231 = and(_T_1230, io.in.a.valid)
node _T_1232 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1233 = and(_T_1231, _T_1232)
node _T_1234 = eq(d_release_ack, UInt<1>(0h0))
node _T_1235 = and(_T_1233, _T_1234)
when _T_1235 :
node _T_1236 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1237 = or(_T_1236, io.in.a.ready)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_104
node _T_1241 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1242 = orr(a_set_wo_ready)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1243)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_120
node _T_1248 = orr(inflight)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
node _T_1250 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1251 = or(_T_1249, _T_1250)
node _T_1252 = lt(watchdog, plusarg_reader.out)
node _T_1253 = or(_T_1251, _T_1252)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1257 = and(io.in.a.ready, io.in.a.valid)
node _T_1258 = and(io.in.d.ready, io.in.d.valid)
node _T_1259 = or(_T_1257, _T_1258)
when _T_1259 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<256>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<256>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 5)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<7>, clock, reset, UInt<7>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 5)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<7>, clock, reset, UInt<7>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<32>
connect c_set, UInt<32>(0h0)
wire c_set_wo_ready : UInt<32>
connect c_set_wo_ready, UInt<32>(0h0)
wire c_opcodes_set : UInt<128>
connect c_opcodes_set, UInt<128>(0h0)
wire c_sizes_set : UInt<256>
connect c_sizes_set, UInt<256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<256>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1260 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<256>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1261 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1262 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = and(_T_1260, _T_1263)
when _T_1264 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<256>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<256>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1265 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1266 = and(_T_1265, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<256>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1267 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1268 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = and(_T_1266, _T_1269)
when _T_1270 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<256>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<256>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<256>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<256>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1271 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1272 = bits(_T_1271, 0, 0)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<256>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<256>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<32>
connect d_clr_1, UInt<32>(0h0)
wire d_clr_wo_ready_1 : UInt<32>
connect d_clr_wo_ready_1, UInt<32>(0h0)
wire d_opcodes_clr_1 : UInt<128>
connect d_opcodes_clr_1, UInt<128>(0h0)
wire d_sizes_clr_1 : UInt<256>
connect d_sizes_clr_1, UInt<256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1277 = and(io.in.d.valid, d_first_2)
node _T_1278 = and(_T_1277, UInt<1>(0h1))
node _T_1279 = and(_T_1278, d_release_ack_1)
when _T_1279 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1280 = and(io.in.d.ready, io.in.d.valid)
node _T_1281 = and(_T_1280, d_first_2)
node _T_1282 = and(_T_1281, UInt<1>(0h1))
node _T_1283 = and(_T_1282, d_release_ack_1)
when _T_1283 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1284 = and(io.in.d.valid, d_first_2)
node _T_1285 = and(_T_1284, UInt<1>(0h1))
node _T_1286 = and(_T_1285, d_release_ack_1)
when _T_1286 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<256>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1287 = dshr(inflight_1, io.in.d.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = or(_T_1288, same_cycle_resp_1)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<256>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1293 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_109
else :
node _T_1297 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_110
node _T_1301 = and(io.in.d.valid, d_first_2)
node _T_1302 = and(_T_1301, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<256>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1303 = and(_T_1302, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<256>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1304 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1305 = and(_T_1303, _T_1304)
node _T_1306 = and(_T_1305, d_release_ack_1)
node _T_1307 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1308 = and(_T_1306, _T_1307)
when _T_1308 :
node _T_1309 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<256>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1310 = or(_T_1309, _WIRE_23.ready)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_111
node _T_1314 = orr(c_set_wo_ready)
when _T_1314 :
node _T_1315 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_121
node _T_1319 = orr(inflight_1)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
node _T_1321 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1322 = or(_T_1320, _T_1321)
node _T_1323 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1324 = or(_T_1322, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/compress-acc/src/main/scala/ZstdCompressor.scala:47:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<256>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1328 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1329 = and(io.in.d.ready, io.in.d.valid)
node _T_1330 = or(_T_1328, _T_1329)
when _T_1330 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [255:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [255:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [255:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [255:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [6:0] c_first_beats1_decode = 7'h0; // @[Edges.scala:220:59]
wire [6:0] c_first_beats1 = 7'h0; // @[Edges.scala:221:14]
wire [6:0] _c_first_count_T = 7'h0; // @[Edges.scala:234:27]
wire [6:0] c_first_count = 7'h0; // @[Edges.scala:234:25]
wire [6:0] _c_first_counter_T = 7'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [6:0] c_first_counter1 = 7'h7F; // @[Edges.scala:230:28]
wire [7:0] _c_first_counter1_T = 8'hFF; // @[Edges.scala:230:28]
wire [255:0] _c_first_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_first_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_first_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [255:0] _c_set_wo_ready_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_wo_ready_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_interm_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_interm_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_opcodes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_opcodes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_sizes_set_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_sizes_set_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _c_probe_ack_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _c_probe_ack_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_1_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_2_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_3_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [255:0] _same_cycle_resp_WIRE_4_bits_data = 256'h0; // @[Bundles.scala:265:74]
wire [255:0] _same_cycle_resp_WIRE_5_bits_data = 256'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [4:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [2:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[2:0]; // @[OneHot.scala:64:49]
wire [7:0] _mask_sizeOH_T_1 = 8'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [4:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[4:0]; // @[OneHot.scala:65:{12,27}]
wire [4:0] mask_sizeOH = {_mask_sizeOH_T_2[4:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h4; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_sub_size = mask_sizeOH[4]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_sub_bit = io_in_a_bits_address_0[4]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_sub_nbit = ~mask_sub_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_sub_acc_T = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_sub_size & mask_sub_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_sub_0_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_2_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size & mask_sub_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_2_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_sub_3_2 = mask_sub_sub_sub_sub_1_2 & mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size & mask_sub_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_3_1 = mask_sub_sub_sub_sub_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_4_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size & mask_sub_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_4_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_5_2 = mask_sub_sub_sub_2_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size & mask_sub_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_5_1 = mask_sub_sub_sub_2_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_6_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size & mask_sub_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_6_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_7_2 = mask_sub_sub_sub_3_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size & mask_sub_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_7_1 = mask_sub_sub_sub_3_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_sub_8_2 = mask_sub_sub_4_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_8 = mask_sub_size & mask_sub_8_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_8_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_sub_9_2 = mask_sub_sub_4_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_9 = mask_sub_size & mask_sub_9_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_9_1 = mask_sub_sub_4_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_sub_10_2 = mask_sub_sub_5_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_10 = mask_sub_size & mask_sub_10_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_10_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_sub_11_2 = mask_sub_sub_5_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_11 = mask_sub_size & mask_sub_11_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_11_1 = mask_sub_sub_5_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_sub_12_2 = mask_sub_sub_6_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_12 = mask_sub_size & mask_sub_12_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_12_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_sub_13_2 = mask_sub_sub_6_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_13 = mask_sub_size & mask_sub_13_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_13_1 = mask_sub_sub_6_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_sub_14_2 = mask_sub_sub_7_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_14 = mask_sub_size & mask_sub_14_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_14_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_sub_15_2 = mask_sub_sub_7_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_15 = mask_sub_size & mask_sub_15_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_15_1 = mask_sub_sub_7_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire mask_eq_16 = mask_sub_8_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_size & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_16 = mask_sub_8_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire mask_eq_17 = mask_sub_8_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_size & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_17 = mask_sub_8_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire mask_eq_18 = mask_sub_9_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_size & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_18 = mask_sub_9_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire mask_eq_19 = mask_sub_9_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_size & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_19 = mask_sub_9_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire mask_eq_20 = mask_sub_10_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_size & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_20 = mask_sub_10_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire mask_eq_21 = mask_sub_10_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_size & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_21 = mask_sub_10_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire mask_eq_22 = mask_sub_11_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_size & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_22 = mask_sub_11_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire mask_eq_23 = mask_sub_11_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_size & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_23 = mask_sub_11_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire mask_eq_24 = mask_sub_12_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_size & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_24 = mask_sub_12_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire mask_eq_25 = mask_sub_12_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_size & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_25 = mask_sub_12_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire mask_eq_26 = mask_sub_13_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_size & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_26 = mask_sub_13_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire mask_eq_27 = mask_sub_13_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_size & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_27 = mask_sub_13_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire mask_eq_28 = mask_sub_14_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_size & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_28 = mask_sub_14_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire mask_eq_29 = mask_sub_14_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_size & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_29 = mask_sub_14_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire mask_eq_30 = mask_sub_15_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_size & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_30 = mask_sub_15_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire mask_eq_31 = mask_sub_15_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_size & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_31 = mask_sub_15_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_lo = {mask_lo_lo_lo_hi, mask_lo_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo_hi = {mask_lo_lo_hi_hi, mask_lo_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_lo = {mask_lo_hi_lo_hi, mask_lo_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi_hi = {mask_lo_hi_hi_hi, mask_lo_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_lo = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_lo_hi = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_lo = {mask_hi_lo_lo_hi, mask_hi_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_lo = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi_hi = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo_hi = {mask_hi_lo_hi_hi, mask_hi_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_lo = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_lo_hi = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_lo = {mask_hi_hi_lo_hi, mask_hi_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_lo = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi_hi = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi_hi = {mask_hi_hi_hi_hi, mask_hi_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [31:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T = {1'h0, a_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1 = _a_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:5]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [6:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T = {1'h0, d_first_counter} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1 = _d_first_counter1_T[6:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [6:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 7'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [6:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] a_first_counter1_1 = _a_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_1 = _d_first_counter1_T_1[6:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [6:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:5]; // @[package.scala:243:46]
wire [6:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 7'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [6:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [7:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 8'h1; // @[Edges.scala:229:27, :230:28]
wire [6:0] d_first_counter1_2 = _d_first_counter1_T_2[6:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 7'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 7'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 7'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [6:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [6:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [6:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module BTB :
input clock : Clock
input reset : Reset
output io : { flip req : { valid : UInt<1>, bits : { addr : UInt<39>}}, resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, flip bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, flip bht_advance : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}, flip ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, ras_head : { valid : UInt<1>, bits : UInt<39>}, flip flush : UInt<1>}
reg idxs : UInt<13>[28], clock
reg idxPages : UInt<3>[28], clock
reg tgts : UInt<13>[28], clock
reg tgtPages : UInt<3>[28], clock
reg pages : UInt<25>[6], clock
regreset pageValid : UInt<6>, clock, reset, UInt<6>(0h0)
node _pagesMasked_T = bits(pageValid, 0, 0)
node _pagesMasked_T_1 = bits(pageValid, 1, 1)
node _pagesMasked_T_2 = bits(pageValid, 2, 2)
node _pagesMasked_T_3 = bits(pageValid, 3, 3)
node _pagesMasked_T_4 = bits(pageValid, 4, 4)
node _pagesMasked_T_5 = bits(pageValid, 5, 5)
node pagesMasked_0 = mux(_pagesMasked_T, pages[0], UInt<1>(0h0))
node pagesMasked_1 = mux(_pagesMasked_T_1, pages[1], UInt<1>(0h0))
node pagesMasked_2 = mux(_pagesMasked_T_2, pages[2], UInt<1>(0h0))
node pagesMasked_3 = mux(_pagesMasked_T_3, pages[3], UInt<1>(0h0))
node pagesMasked_4 = mux(_pagesMasked_T_4, pages[4], UInt<1>(0h0))
node pagesMasked_5 = mux(_pagesMasked_T_5, pages[5], UInt<1>(0h0))
regreset isValid : UInt<28>, clock, reset, UInt<28>(0h0)
reg cfiType : UInt<2>[28], clock
reg brIdx : UInt<1>[28], clock
regreset r_btb_update_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect r_btb_update_pipe_v, io.btb_update.valid
reg r_btb_update_pipe_b : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}, clock
when io.btb_update.valid :
connect r_btb_update_pipe_b, io.btb_update.bits
wire r_btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}
connect r_btb_update.valid, r_btb_update_pipe_v
connect r_btb_update.bits, r_btb_update_pipe_b
node pageHit_p = shr(io.req.bits.addr, 14)
node _pageHit_T = eq(pages[0], pageHit_p)
node _pageHit_T_1 = eq(pages[1], pageHit_p)
node _pageHit_T_2 = eq(pages[2], pageHit_p)
node _pageHit_T_3 = eq(pages[3], pageHit_p)
node _pageHit_T_4 = eq(pages[4], pageHit_p)
node _pageHit_T_5 = eq(pages[5], pageHit_p)
node pageHit_lo_hi = cat(_pageHit_T_2, _pageHit_T_1)
node pageHit_lo = cat(pageHit_lo_hi, _pageHit_T)
node pageHit_hi_hi = cat(_pageHit_T_5, _pageHit_T_4)
node pageHit_hi = cat(pageHit_hi_hi, _pageHit_T_3)
node _pageHit_T_6 = cat(pageHit_hi, pageHit_lo)
node pageHit = and(pageValid, _pageHit_T_6)
node idxHit_idx = bits(io.req.bits.addr, 13, 1)
node _idxHit_T = eq(idxs[0], idxHit_idx)
node _idxHit_T_1 = eq(idxs[1], idxHit_idx)
node _idxHit_T_2 = eq(idxs[2], idxHit_idx)
node _idxHit_T_3 = eq(idxs[3], idxHit_idx)
node _idxHit_T_4 = eq(idxs[4], idxHit_idx)
node _idxHit_T_5 = eq(idxs[5], idxHit_idx)
node _idxHit_T_6 = eq(idxs[6], idxHit_idx)
node _idxHit_T_7 = eq(idxs[7], idxHit_idx)
node _idxHit_T_8 = eq(idxs[8], idxHit_idx)
node _idxHit_T_9 = eq(idxs[9], idxHit_idx)
node _idxHit_T_10 = eq(idxs[10], idxHit_idx)
node _idxHit_T_11 = eq(idxs[11], idxHit_idx)
node _idxHit_T_12 = eq(idxs[12], idxHit_idx)
node _idxHit_T_13 = eq(idxs[13], idxHit_idx)
node _idxHit_T_14 = eq(idxs[14], idxHit_idx)
node _idxHit_T_15 = eq(idxs[15], idxHit_idx)
node _idxHit_T_16 = eq(idxs[16], idxHit_idx)
node _idxHit_T_17 = eq(idxs[17], idxHit_idx)
node _idxHit_T_18 = eq(idxs[18], idxHit_idx)
node _idxHit_T_19 = eq(idxs[19], idxHit_idx)
node _idxHit_T_20 = eq(idxs[20], idxHit_idx)
node _idxHit_T_21 = eq(idxs[21], idxHit_idx)
node _idxHit_T_22 = eq(idxs[22], idxHit_idx)
node _idxHit_T_23 = eq(idxs[23], idxHit_idx)
node _idxHit_T_24 = eq(idxs[24], idxHit_idx)
node _idxHit_T_25 = eq(idxs[25], idxHit_idx)
node _idxHit_T_26 = eq(idxs[26], idxHit_idx)
node _idxHit_T_27 = eq(idxs[27], idxHit_idx)
node idxHit_lo_lo_lo_hi = cat(_idxHit_T_2, _idxHit_T_1)
node idxHit_lo_lo_lo = cat(idxHit_lo_lo_lo_hi, _idxHit_T)
node idxHit_lo_lo_hi_lo = cat(_idxHit_T_4, _idxHit_T_3)
node idxHit_lo_lo_hi_hi = cat(_idxHit_T_6, _idxHit_T_5)
node idxHit_lo_lo_hi = cat(idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo)
node idxHit_lo_lo = cat(idxHit_lo_lo_hi, idxHit_lo_lo_lo)
node idxHit_lo_hi_lo_hi = cat(_idxHit_T_9, _idxHit_T_8)
node idxHit_lo_hi_lo = cat(idxHit_lo_hi_lo_hi, _idxHit_T_7)
node idxHit_lo_hi_hi_lo = cat(_idxHit_T_11, _idxHit_T_10)
node idxHit_lo_hi_hi_hi = cat(_idxHit_T_13, _idxHit_T_12)
node idxHit_lo_hi_hi = cat(idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo)
node idxHit_lo_hi = cat(idxHit_lo_hi_hi, idxHit_lo_hi_lo)
node idxHit_lo = cat(idxHit_lo_hi, idxHit_lo_lo)
node idxHit_hi_lo_lo_hi = cat(_idxHit_T_16, _idxHit_T_15)
node idxHit_hi_lo_lo = cat(idxHit_hi_lo_lo_hi, _idxHit_T_14)
node idxHit_hi_lo_hi_lo = cat(_idxHit_T_18, _idxHit_T_17)
node idxHit_hi_lo_hi_hi = cat(_idxHit_T_20, _idxHit_T_19)
node idxHit_hi_lo_hi = cat(idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo)
node idxHit_hi_lo = cat(idxHit_hi_lo_hi, idxHit_hi_lo_lo)
node idxHit_hi_hi_lo_hi = cat(_idxHit_T_23, _idxHit_T_22)
node idxHit_hi_hi_lo = cat(idxHit_hi_hi_lo_hi, _idxHit_T_21)
node idxHit_hi_hi_hi_lo = cat(_idxHit_T_25, _idxHit_T_24)
node idxHit_hi_hi_hi_hi = cat(_idxHit_T_27, _idxHit_T_26)
node idxHit_hi_hi_hi = cat(idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo)
node idxHit_hi_hi = cat(idxHit_hi_hi_hi, idxHit_hi_hi_lo)
node idxHit_hi = cat(idxHit_hi_hi, idxHit_hi_lo)
node _idxHit_T_28 = cat(idxHit_hi, idxHit_lo)
node idxHit = and(_idxHit_T_28, isValid)
node updatePageHit_p = shr(r_btb_update.bits.pc, 14)
node _updatePageHit_T = eq(pages[0], updatePageHit_p)
node _updatePageHit_T_1 = eq(pages[1], updatePageHit_p)
node _updatePageHit_T_2 = eq(pages[2], updatePageHit_p)
node _updatePageHit_T_3 = eq(pages[3], updatePageHit_p)
node _updatePageHit_T_4 = eq(pages[4], updatePageHit_p)
node _updatePageHit_T_5 = eq(pages[5], updatePageHit_p)
node updatePageHit_lo_hi = cat(_updatePageHit_T_2, _updatePageHit_T_1)
node updatePageHit_lo = cat(updatePageHit_lo_hi, _updatePageHit_T)
node updatePageHit_hi_hi = cat(_updatePageHit_T_5, _updatePageHit_T_4)
node updatePageHit_hi = cat(updatePageHit_hi_hi, _updatePageHit_T_3)
node _updatePageHit_T_6 = cat(updatePageHit_hi, updatePageHit_lo)
node updatePageHit = and(pageValid, _updatePageHit_T_6)
node updateHit = lt(r_btb_update.bits.prediction.entry, UInt<5>(0h1c))
node useUpdatePageHit = orr(updatePageHit)
node usePageHit = orr(pageHit)
node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>(0h0))
regreset nextPageRepl : UInt<3>, clock, reset, UInt<3>(0h0)
node _idxPageRepl_T = bits(pageHit, 4, 0)
node _idxPageRepl_T_1 = bits(pageHit, 5, 5)
node _idxPageRepl_T_2 = cat(_idxPageRepl_T, _idxPageRepl_T_1)
node _idxPageRepl_T_3 = dshl(UInt<1>(0h1), nextPageRepl)
node _idxPageRepl_T_4 = mux(usePageHit, UInt<1>(0h0), _idxPageRepl_T_3)
node idxPageRepl = or(_idxPageRepl_T_2, _idxPageRepl_T_4)
node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl)
node idxPageUpdate_hi = bits(idxPageUpdateOH, 7, 4)
node idxPageUpdate_lo = bits(idxPageUpdateOH, 3, 0)
node _idxPageUpdate_T = orr(idxPageUpdate_hi)
node _idxPageUpdate_T_1 = or(idxPageUpdate_hi, idxPageUpdate_lo)
node idxPageUpdate_hi_1 = bits(_idxPageUpdate_T_1, 3, 2)
node idxPageUpdate_lo_1 = bits(_idxPageUpdate_T_1, 1, 0)
node _idxPageUpdate_T_2 = orr(idxPageUpdate_hi_1)
node _idxPageUpdate_T_3 = or(idxPageUpdate_hi_1, idxPageUpdate_lo_1)
node _idxPageUpdate_T_4 = bits(_idxPageUpdate_T_3, 1, 1)
node _idxPageUpdate_T_5 = cat(_idxPageUpdate_T_2, _idxPageUpdate_T_4)
node idxPageUpdate = cat(_idxPageUpdate_T, _idxPageUpdate_T_5)
node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>(0h0))
node _samePage_T = shr(r_btb_update.bits.pc, 14)
node _samePage_T_1 = shr(io.req.bits.addr, 14)
node samePage = eq(_samePage_T, _samePage_T_1)
node _doTgtPageRepl_T = eq(samePage, UInt<1>(0h0))
node _doTgtPageRepl_T_1 = eq(usePageHit, UInt<1>(0h0))
node doTgtPageRepl = and(_doTgtPageRepl_T, _doTgtPageRepl_T_1)
node _tgtPageRepl_T = bits(idxPageUpdateOH, 4, 0)
node _tgtPageRepl_T_1 = bits(idxPageUpdateOH, 5, 5)
node _tgtPageRepl_T_2 = cat(_tgtPageRepl_T, _tgtPageRepl_T_1)
node tgtPageRepl = mux(samePage, idxPageUpdateOH, _tgtPageRepl_T_2)
node _tgtPageUpdate_T = mux(usePageHit, UInt<1>(0h0), tgtPageRepl)
node _tgtPageUpdate_T_1 = or(pageHit, _tgtPageUpdate_T)
node tgtPageUpdate_hi = bits(_tgtPageUpdate_T_1, 7, 4)
node tgtPageUpdate_lo = bits(_tgtPageUpdate_T_1, 3, 0)
node _tgtPageUpdate_T_2 = orr(tgtPageUpdate_hi)
node _tgtPageUpdate_T_3 = or(tgtPageUpdate_hi, tgtPageUpdate_lo)
node tgtPageUpdate_hi_1 = bits(_tgtPageUpdate_T_3, 3, 2)
node tgtPageUpdate_lo_1 = bits(_tgtPageUpdate_T_3, 1, 0)
node _tgtPageUpdate_T_4 = orr(tgtPageUpdate_hi_1)
node _tgtPageUpdate_T_5 = or(tgtPageUpdate_hi_1, tgtPageUpdate_lo_1)
node _tgtPageUpdate_T_6 = bits(_tgtPageUpdate_T_5, 1, 1)
node _tgtPageUpdate_T_7 = cat(_tgtPageUpdate_T_4, _tgtPageUpdate_T_6)
node tgtPageUpdate = cat(_tgtPageUpdate_T_2, _tgtPageUpdate_T_7)
node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>(0h0))
node _T = or(doIdxPageRepl, doTgtPageRepl)
node _T_1 = and(r_btb_update.valid, _T)
when _T_1 :
node both = and(doIdxPageRepl, doTgtPageRepl)
node _next_T = mux(both, UInt<2>(0h2), UInt<1>(0h1))
node _next_T_1 = add(nextPageRepl, _next_T)
node next = tail(_next_T_1, 1)
node _nextPageRepl_T = geq(next, UInt<3>(0h6))
node _nextPageRepl_T_1 = bits(next, 0, 0)
node _nextPageRepl_T_2 = mux(_nextPageRepl_T, _nextPageRepl_T_1, next)
connect nextPageRepl, _nextPageRepl_T_2
regreset state_reg : UInt<27>, clock, reset, UInt<27>(0h0)
node waddr_left_subtree_older = bits(state_reg, 26, 26)
node waddr_left_subtree_state = bits(state_reg, 25, 15)
node waddr_right_subtree_state = bits(state_reg, 14, 0)
node waddr_left_subtree_older_1 = bits(waddr_left_subtree_state, 10, 10)
node waddr_left_subtree_state_1 = bits(waddr_left_subtree_state, 9, 7)
node waddr_right_subtree_state_1 = bits(waddr_left_subtree_state, 6, 0)
node waddr_left_subtree_older_2 = bits(waddr_left_subtree_state_1, 2, 2)
node waddr_left_subtree_state_2 = bits(waddr_left_subtree_state_1, 1, 1)
node waddr_right_subtree_state_2 = bits(waddr_left_subtree_state_1, 0, 0)
node _waddr_T = bits(waddr_left_subtree_state_2, 0, 0)
node _waddr_T_1 = bits(waddr_right_subtree_state_2, 0, 0)
node _waddr_T_2 = mux(waddr_left_subtree_older_2, _waddr_T, _waddr_T_1)
node _waddr_T_3 = cat(waddr_left_subtree_older_2, _waddr_T_2)
node waddr_left_subtree_older_3 = bits(waddr_right_subtree_state_1, 6, 6)
node waddr_left_subtree_state_3 = bits(waddr_right_subtree_state_1, 5, 3)
node waddr_right_subtree_state_3 = bits(waddr_right_subtree_state_1, 2, 0)
node waddr_left_subtree_older_4 = bits(waddr_left_subtree_state_3, 2, 2)
node waddr_left_subtree_state_4 = bits(waddr_left_subtree_state_3, 1, 1)
node waddr_right_subtree_state_4 = bits(waddr_left_subtree_state_3, 0, 0)
node _waddr_T_4 = bits(waddr_left_subtree_state_4, 0, 0)
node _waddr_T_5 = bits(waddr_right_subtree_state_4, 0, 0)
node _waddr_T_6 = mux(waddr_left_subtree_older_4, _waddr_T_4, _waddr_T_5)
node _waddr_T_7 = cat(waddr_left_subtree_older_4, _waddr_T_6)
node waddr_left_subtree_older_5 = bits(waddr_right_subtree_state_3, 2, 2)
node waddr_left_subtree_state_5 = bits(waddr_right_subtree_state_3, 1, 1)
node waddr_right_subtree_state_5 = bits(waddr_right_subtree_state_3, 0, 0)
node _waddr_T_8 = bits(waddr_left_subtree_state_5, 0, 0)
node _waddr_T_9 = bits(waddr_right_subtree_state_5, 0, 0)
node _waddr_T_10 = mux(waddr_left_subtree_older_5, _waddr_T_8, _waddr_T_9)
node _waddr_T_11 = cat(waddr_left_subtree_older_5, _waddr_T_10)
node _waddr_T_12 = mux(waddr_left_subtree_older_3, _waddr_T_7, _waddr_T_11)
node _waddr_T_13 = cat(waddr_left_subtree_older_3, _waddr_T_12)
node _waddr_T_14 = mux(waddr_left_subtree_older_1, _waddr_T_3, _waddr_T_13)
node _waddr_T_15 = cat(waddr_left_subtree_older_1, _waddr_T_14)
node waddr_left_subtree_older_6 = bits(waddr_right_subtree_state, 14, 14)
node waddr_left_subtree_state_6 = bits(waddr_right_subtree_state, 13, 7)
node waddr_right_subtree_state_6 = bits(waddr_right_subtree_state, 6, 0)
node waddr_left_subtree_older_7 = bits(waddr_left_subtree_state_6, 6, 6)
node waddr_left_subtree_state_7 = bits(waddr_left_subtree_state_6, 5, 3)
node waddr_right_subtree_state_7 = bits(waddr_left_subtree_state_6, 2, 0)
node waddr_left_subtree_older_8 = bits(waddr_left_subtree_state_7, 2, 2)
node waddr_left_subtree_state_8 = bits(waddr_left_subtree_state_7, 1, 1)
node waddr_right_subtree_state_8 = bits(waddr_left_subtree_state_7, 0, 0)
node _waddr_T_16 = bits(waddr_left_subtree_state_8, 0, 0)
node _waddr_T_17 = bits(waddr_right_subtree_state_8, 0, 0)
node _waddr_T_18 = mux(waddr_left_subtree_older_8, _waddr_T_16, _waddr_T_17)
node _waddr_T_19 = cat(waddr_left_subtree_older_8, _waddr_T_18)
node waddr_left_subtree_older_9 = bits(waddr_right_subtree_state_7, 2, 2)
node waddr_left_subtree_state_9 = bits(waddr_right_subtree_state_7, 1, 1)
node waddr_right_subtree_state_9 = bits(waddr_right_subtree_state_7, 0, 0)
node _waddr_T_20 = bits(waddr_left_subtree_state_9, 0, 0)
node _waddr_T_21 = bits(waddr_right_subtree_state_9, 0, 0)
node _waddr_T_22 = mux(waddr_left_subtree_older_9, _waddr_T_20, _waddr_T_21)
node _waddr_T_23 = cat(waddr_left_subtree_older_9, _waddr_T_22)
node _waddr_T_24 = mux(waddr_left_subtree_older_7, _waddr_T_19, _waddr_T_23)
node _waddr_T_25 = cat(waddr_left_subtree_older_7, _waddr_T_24)
node waddr_left_subtree_older_10 = bits(waddr_right_subtree_state_6, 6, 6)
node waddr_left_subtree_state_10 = bits(waddr_right_subtree_state_6, 5, 3)
node waddr_right_subtree_state_10 = bits(waddr_right_subtree_state_6, 2, 0)
node waddr_left_subtree_older_11 = bits(waddr_left_subtree_state_10, 2, 2)
node waddr_left_subtree_state_11 = bits(waddr_left_subtree_state_10, 1, 1)
node waddr_right_subtree_state_11 = bits(waddr_left_subtree_state_10, 0, 0)
node _waddr_T_26 = bits(waddr_left_subtree_state_11, 0, 0)
node _waddr_T_27 = bits(waddr_right_subtree_state_11, 0, 0)
node _waddr_T_28 = mux(waddr_left_subtree_older_11, _waddr_T_26, _waddr_T_27)
node _waddr_T_29 = cat(waddr_left_subtree_older_11, _waddr_T_28)
node waddr_left_subtree_older_12 = bits(waddr_right_subtree_state_10, 2, 2)
node waddr_left_subtree_state_12 = bits(waddr_right_subtree_state_10, 1, 1)
node waddr_right_subtree_state_12 = bits(waddr_right_subtree_state_10, 0, 0)
node _waddr_T_30 = bits(waddr_left_subtree_state_12, 0, 0)
node _waddr_T_31 = bits(waddr_right_subtree_state_12, 0, 0)
node _waddr_T_32 = mux(waddr_left_subtree_older_12, _waddr_T_30, _waddr_T_31)
node _waddr_T_33 = cat(waddr_left_subtree_older_12, _waddr_T_32)
node _waddr_T_34 = mux(waddr_left_subtree_older_10, _waddr_T_29, _waddr_T_33)
node _waddr_T_35 = cat(waddr_left_subtree_older_10, _waddr_T_34)
node _waddr_T_36 = mux(waddr_left_subtree_older_6, _waddr_T_25, _waddr_T_35)
node _waddr_T_37 = cat(waddr_left_subtree_older_6, _waddr_T_36)
node _waddr_T_38 = mux(waddr_left_subtree_older, _waddr_T_15, _waddr_T_37)
node _waddr_T_39 = cat(waddr_left_subtree_older, _waddr_T_38)
node waddr = mux(updateHit, r_btb_update.bits.prediction.entry, _waddr_T_39)
regreset r_resp_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect r_resp_pipe_v, io.resp.valid
reg r_resp_pipe_b : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock
when io.resp.valid :
connect r_resp_pipe_b.bht.value, io.resp.bits.bht.value
connect r_resp_pipe_b.bht.history, io.resp.bits.bht.history
connect r_resp_pipe_b.entry, io.resp.bits.entry
connect r_resp_pipe_b.target, io.resp.bits.target
connect r_resp_pipe_b.bridx, io.resp.bits.bridx
connect r_resp_pipe_b.mask, io.resp.bits.mask
connect r_resp_pipe_b.taken, io.resp.bits.taken
connect r_resp_pipe_b.cfiType, io.resp.bits.cfiType
wire r_resp : { valid : UInt<1>, bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}}
connect r_resp.valid, r_resp_pipe_v
connect r_resp.bits, r_resp_pipe_b
node _T_2 = and(r_resp.valid, r_resp.bits.taken)
node _T_3 = or(_T_2, r_btb_update.valid)
when _T_3 :
node _T_4 = mux(r_btb_update.valid, waddr, r_resp.bits.entry)
node state_reg_touch_way_sized = bits(_T_4, 4, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 4, 4)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 25, 15)
node state_reg_right_subtree_state = bits(state_reg, 14, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 3, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 3, 3)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 9, 7)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 6, 0)
node _state_reg_T_1 = bits(_state_reg_T, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_1, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_left_subtree_state_1, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_left_subtree_state_1, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = bits(_state_reg_T_2, 0, 0)
node _state_reg_T_4 = eq(_state_reg_T_3, UInt<1>(0h0))
node _state_reg_T_5 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_4)
node _state_reg_T_6 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_7 = bits(_state_reg_T_6, 0, 0)
node _state_reg_T_8 = eq(_state_reg_T_7, UInt<1>(0h0))
node _state_reg_T_9 = mux(state_reg_set_left_older_2, _state_reg_T_8, state_reg_right_subtree_state_2)
node state_reg_hi = cat(state_reg_set_left_older_2, _state_reg_T_5)
node _state_reg_T_10 = cat(state_reg_hi, _state_reg_T_9)
node _state_reg_T_11 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_10)
node _state_reg_T_12 = bits(_state_reg_T, 2, 0)
node _state_reg_set_left_older_T_3 = bits(_state_reg_T_12, 2, 2)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg_right_subtree_state_1, 5, 3)
node state_reg_right_subtree_state_3 = bits(state_reg_right_subtree_state_1, 2, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 1, 0)
node _state_reg_set_left_older_T_4 = bits(_state_reg_T_13, 1, 1)
node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0))
node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0)
node _state_reg_T_14 = bits(_state_reg_T_13, 0, 0)
node _state_reg_T_15 = bits(_state_reg_T_14, 0, 0)
node _state_reg_T_16 = eq(_state_reg_T_15, UInt<1>(0h0))
node _state_reg_T_17 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_16)
node _state_reg_T_18 = bits(_state_reg_T_13, 0, 0)
node _state_reg_T_19 = bits(_state_reg_T_18, 0, 0)
node _state_reg_T_20 = eq(_state_reg_T_19, UInt<1>(0h0))
node _state_reg_T_21 = mux(state_reg_set_left_older_4, _state_reg_T_20, state_reg_right_subtree_state_4)
node state_reg_hi_1 = cat(state_reg_set_left_older_4, _state_reg_T_17)
node _state_reg_T_22 = cat(state_reg_hi_1, _state_reg_T_21)
node _state_reg_T_23 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_22)
node _state_reg_T_24 = bits(_state_reg_T_12, 1, 0)
node _state_reg_set_left_older_T_5 = bits(_state_reg_T_24, 1, 1)
node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0))
node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1)
node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0)
node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_26 = bits(_state_reg_T_25, 0, 0)
node _state_reg_T_27 = eq(_state_reg_T_26, UInt<1>(0h0))
node _state_reg_T_28 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_27)
node _state_reg_T_29 = bits(_state_reg_T_24, 0, 0)
node _state_reg_T_30 = bits(_state_reg_T_29, 0, 0)
node _state_reg_T_31 = eq(_state_reg_T_30, UInt<1>(0h0))
node _state_reg_T_32 = mux(state_reg_set_left_older_5, _state_reg_T_31, state_reg_right_subtree_state_5)
node state_reg_hi_2 = cat(state_reg_set_left_older_5, _state_reg_T_28)
node _state_reg_T_33 = cat(state_reg_hi_2, _state_reg_T_32)
node _state_reg_T_34 = mux(state_reg_set_left_older_3, _state_reg_T_33, state_reg_right_subtree_state_3)
node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_23)
node _state_reg_T_35 = cat(state_reg_hi_3, _state_reg_T_34)
node _state_reg_T_36 = mux(state_reg_set_left_older_1, _state_reg_T_35, state_reg_right_subtree_state_1)
node state_reg_hi_4 = cat(state_reg_set_left_older_1, _state_reg_T_11)
node _state_reg_T_37 = cat(state_reg_hi_4, _state_reg_T_36)
node _state_reg_T_38 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_37)
node _state_reg_T_39 = bits(state_reg_touch_way_sized, 3, 0)
node _state_reg_set_left_older_T_6 = bits(_state_reg_T_39, 3, 3)
node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0))
node state_reg_left_subtree_state_6 = bits(state_reg_right_subtree_state, 13, 7)
node state_reg_right_subtree_state_6 = bits(state_reg_right_subtree_state, 6, 0)
node _state_reg_T_40 = bits(_state_reg_T_39, 2, 0)
node _state_reg_set_left_older_T_7 = bits(_state_reg_T_40, 2, 2)
node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0))
node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 5, 3)
node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 2, 0)
node _state_reg_T_41 = bits(_state_reg_T_40, 1, 0)
node _state_reg_set_left_older_T_8 = bits(_state_reg_T_41, 1, 1)
node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0))
node state_reg_left_subtree_state_8 = bits(state_reg_left_subtree_state_7, 1, 1)
node state_reg_right_subtree_state_8 = bits(state_reg_left_subtree_state_7, 0, 0)
node _state_reg_T_42 = bits(_state_reg_T_41, 0, 0)
node _state_reg_T_43 = bits(_state_reg_T_42, 0, 0)
node _state_reg_T_44 = eq(_state_reg_T_43, UInt<1>(0h0))
node _state_reg_T_45 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_44)
node _state_reg_T_46 = bits(_state_reg_T_41, 0, 0)
node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0)
node _state_reg_T_48 = eq(_state_reg_T_47, UInt<1>(0h0))
node _state_reg_T_49 = mux(state_reg_set_left_older_8, _state_reg_T_48, state_reg_right_subtree_state_8)
node state_reg_hi_5 = cat(state_reg_set_left_older_8, _state_reg_T_45)
node _state_reg_T_50 = cat(state_reg_hi_5, _state_reg_T_49)
node _state_reg_T_51 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_50)
node _state_reg_T_52 = bits(_state_reg_T_40, 1, 0)
node _state_reg_set_left_older_T_9 = bits(_state_reg_T_52, 1, 1)
node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0))
node state_reg_left_subtree_state_9 = bits(state_reg_right_subtree_state_7, 1, 1)
node state_reg_right_subtree_state_9 = bits(state_reg_right_subtree_state_7, 0, 0)
node _state_reg_T_53 = bits(_state_reg_T_52, 0, 0)
node _state_reg_T_54 = bits(_state_reg_T_53, 0, 0)
node _state_reg_T_55 = eq(_state_reg_T_54, UInt<1>(0h0))
node _state_reg_T_56 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_55)
node _state_reg_T_57 = bits(_state_reg_T_52, 0, 0)
node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0)
node _state_reg_T_59 = eq(_state_reg_T_58, UInt<1>(0h0))
node _state_reg_T_60 = mux(state_reg_set_left_older_9, _state_reg_T_59, state_reg_right_subtree_state_9)
node state_reg_hi_6 = cat(state_reg_set_left_older_9, _state_reg_T_56)
node _state_reg_T_61 = cat(state_reg_hi_6, _state_reg_T_60)
node _state_reg_T_62 = mux(state_reg_set_left_older_7, _state_reg_T_61, state_reg_right_subtree_state_7)
node state_reg_hi_7 = cat(state_reg_set_left_older_7, _state_reg_T_51)
node _state_reg_T_63 = cat(state_reg_hi_7, _state_reg_T_62)
node _state_reg_T_64 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_63)
node _state_reg_T_65 = bits(_state_reg_T_39, 2, 0)
node _state_reg_set_left_older_T_10 = bits(_state_reg_T_65, 2, 2)
node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0))
node state_reg_left_subtree_state_10 = bits(state_reg_right_subtree_state_6, 5, 3)
node state_reg_right_subtree_state_10 = bits(state_reg_right_subtree_state_6, 2, 0)
node _state_reg_T_66 = bits(_state_reg_T_65, 1, 0)
node _state_reg_set_left_older_T_11 = bits(_state_reg_T_66, 1, 1)
node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0))
node state_reg_left_subtree_state_11 = bits(state_reg_left_subtree_state_10, 1, 1)
node state_reg_right_subtree_state_11 = bits(state_reg_left_subtree_state_10, 0, 0)
node _state_reg_T_67 = bits(_state_reg_T_66, 0, 0)
node _state_reg_T_68 = bits(_state_reg_T_67, 0, 0)
node _state_reg_T_69 = eq(_state_reg_T_68, UInt<1>(0h0))
node _state_reg_T_70 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_69)
node _state_reg_T_71 = bits(_state_reg_T_66, 0, 0)
node _state_reg_T_72 = bits(_state_reg_T_71, 0, 0)
node _state_reg_T_73 = eq(_state_reg_T_72, UInt<1>(0h0))
node _state_reg_T_74 = mux(state_reg_set_left_older_11, _state_reg_T_73, state_reg_right_subtree_state_11)
node state_reg_hi_8 = cat(state_reg_set_left_older_11, _state_reg_T_70)
node _state_reg_T_75 = cat(state_reg_hi_8, _state_reg_T_74)
node _state_reg_T_76 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_75)
node _state_reg_T_77 = bits(_state_reg_T_65, 1, 0)
node _state_reg_set_left_older_T_12 = bits(_state_reg_T_77, 1, 1)
node state_reg_set_left_older_12 = eq(_state_reg_set_left_older_T_12, UInt<1>(0h0))
node state_reg_left_subtree_state_12 = bits(state_reg_right_subtree_state_10, 1, 1)
node state_reg_right_subtree_state_12 = bits(state_reg_right_subtree_state_10, 0, 0)
node _state_reg_T_78 = bits(_state_reg_T_77, 0, 0)
node _state_reg_T_79 = bits(_state_reg_T_78, 0, 0)
node _state_reg_T_80 = eq(_state_reg_T_79, UInt<1>(0h0))
node _state_reg_T_81 = mux(state_reg_set_left_older_12, state_reg_left_subtree_state_12, _state_reg_T_80)
node _state_reg_T_82 = bits(_state_reg_T_77, 0, 0)
node _state_reg_T_83 = bits(_state_reg_T_82, 0, 0)
node _state_reg_T_84 = eq(_state_reg_T_83, UInt<1>(0h0))
node _state_reg_T_85 = mux(state_reg_set_left_older_12, _state_reg_T_84, state_reg_right_subtree_state_12)
node state_reg_hi_9 = cat(state_reg_set_left_older_12, _state_reg_T_81)
node _state_reg_T_86 = cat(state_reg_hi_9, _state_reg_T_85)
node _state_reg_T_87 = mux(state_reg_set_left_older_10, _state_reg_T_86, state_reg_right_subtree_state_10)
node state_reg_hi_10 = cat(state_reg_set_left_older_10, _state_reg_T_76)
node _state_reg_T_88 = cat(state_reg_hi_10, _state_reg_T_87)
node _state_reg_T_89 = mux(state_reg_set_left_older_6, _state_reg_T_88, state_reg_right_subtree_state_6)
node state_reg_hi_11 = cat(state_reg_set_left_older_6, _state_reg_T_64)
node _state_reg_T_90 = cat(state_reg_hi_11, _state_reg_T_89)
node _state_reg_T_91 = mux(state_reg_set_left_older, _state_reg_T_90, state_reg_right_subtree_state)
node state_reg_hi_12 = cat(state_reg_set_left_older, _state_reg_T_38)
node _state_reg_T_92 = cat(state_reg_hi_12, _state_reg_T_91)
connect state_reg, _state_reg_T_92
when r_btb_update.valid :
node mask = dshl(UInt<1>(0h1), waddr)
node _idxs_T = bits(r_btb_update.bits.pc, 13, 1)
connect idxs[waddr], _idxs_T
node _tgts_T = bits(io.req.bits.addr, 13, 1)
connect tgts[waddr], _tgts_T
node _idxPages_T = add(idxPageUpdate, UInt<1>(0h1))
connect idxPages[waddr], _idxPages_T
connect tgtPages[waddr], tgtPageUpdate
connect cfiType[waddr], r_btb_update.bits.cfiType
node _isValid_T = or(isValid, mask)
node _isValid_T_1 = not(mask)
node _isValid_T_2 = and(isValid, _isValid_T_1)
node _isValid_T_3 = mux(r_btb_update.bits.isValid, _isValid_T, _isValid_T_2)
connect isValid, _isValid_T_3
node _brIdx_T = shr(r_btb_update.bits.br_pc, 1)
connect brIdx[waddr], _brIdx_T
node _idxWritesEven_T = bits(idxPageUpdate, 0, 0)
node idxWritesEven = eq(_idxWritesEven_T, UInt<1>(0h0))
node _T_5 = mux(idxWritesEven, idxPageReplEn, tgtPageReplEn)
node _T_6 = shr(r_btb_update.bits.pc, 14)
node _T_7 = shr(io.req.bits.addr, 14)
node _T_8 = mux(idxWritesEven, _T_6, _T_7)
node _T_9 = bits(_T_5, 0, 0)
when _T_9 :
connect pages[0], _T_8
node _T_10 = bits(_T_5, 2, 2)
when _T_10 :
connect pages[2], _T_8
node _T_11 = bits(_T_5, 4, 4)
when _T_11 :
connect pages[4], _T_8
node _T_12 = mux(idxWritesEven, tgtPageReplEn, idxPageReplEn)
node _T_13 = shr(io.req.bits.addr, 14)
node _T_14 = shr(r_btb_update.bits.pc, 14)
node _T_15 = mux(idxWritesEven, _T_13, _T_14)
node _T_16 = bits(_T_12, 1, 1)
when _T_16 :
connect pages[1], _T_15
node _T_17 = bits(_T_12, 3, 3)
when _T_17 :
connect pages[3], _T_15
node _T_18 = bits(_T_12, 5, 5)
when _T_18 :
connect pages[5], _T_15
node _pageValid_T = or(pageValid, tgtPageReplEn)
node _pageValid_T_1 = or(_pageValid_T, idxPageReplEn)
connect pageValid, _pageValid_T_1
node _io_resp_valid_T = shl(pageHit, 1)
node _io_resp_valid_T_1 = bits(idxHit, 0, 0)
node _io_resp_valid_T_2 = bits(idxHit, 1, 1)
node _io_resp_valid_T_3 = bits(idxHit, 2, 2)
node _io_resp_valid_T_4 = bits(idxHit, 3, 3)
node _io_resp_valid_T_5 = bits(idxHit, 4, 4)
node _io_resp_valid_T_6 = bits(idxHit, 5, 5)
node _io_resp_valid_T_7 = bits(idxHit, 6, 6)
node _io_resp_valid_T_8 = bits(idxHit, 7, 7)
node _io_resp_valid_T_9 = bits(idxHit, 8, 8)
node _io_resp_valid_T_10 = bits(idxHit, 9, 9)
node _io_resp_valid_T_11 = bits(idxHit, 10, 10)
node _io_resp_valid_T_12 = bits(idxHit, 11, 11)
node _io_resp_valid_T_13 = bits(idxHit, 12, 12)
node _io_resp_valid_T_14 = bits(idxHit, 13, 13)
node _io_resp_valid_T_15 = bits(idxHit, 14, 14)
node _io_resp_valid_T_16 = bits(idxHit, 15, 15)
node _io_resp_valid_T_17 = bits(idxHit, 16, 16)
node _io_resp_valid_T_18 = bits(idxHit, 17, 17)
node _io_resp_valid_T_19 = bits(idxHit, 18, 18)
node _io_resp_valid_T_20 = bits(idxHit, 19, 19)
node _io_resp_valid_T_21 = bits(idxHit, 20, 20)
node _io_resp_valid_T_22 = bits(idxHit, 21, 21)
node _io_resp_valid_T_23 = bits(idxHit, 22, 22)
node _io_resp_valid_T_24 = bits(idxHit, 23, 23)
node _io_resp_valid_T_25 = bits(idxHit, 24, 24)
node _io_resp_valid_T_26 = bits(idxHit, 25, 25)
node _io_resp_valid_T_27 = bits(idxHit, 26, 26)
node _io_resp_valid_T_28 = bits(idxHit, 27, 27)
node _io_resp_valid_T_29 = mux(_io_resp_valid_T_1, idxPages[0], UInt<1>(0h0))
node _io_resp_valid_T_30 = mux(_io_resp_valid_T_2, idxPages[1], UInt<1>(0h0))
node _io_resp_valid_T_31 = mux(_io_resp_valid_T_3, idxPages[2], UInt<1>(0h0))
node _io_resp_valid_T_32 = mux(_io_resp_valid_T_4, idxPages[3], UInt<1>(0h0))
node _io_resp_valid_T_33 = mux(_io_resp_valid_T_5, idxPages[4], UInt<1>(0h0))
node _io_resp_valid_T_34 = mux(_io_resp_valid_T_6, idxPages[5], UInt<1>(0h0))
node _io_resp_valid_T_35 = mux(_io_resp_valid_T_7, idxPages[6], UInt<1>(0h0))
node _io_resp_valid_T_36 = mux(_io_resp_valid_T_8, idxPages[7], UInt<1>(0h0))
node _io_resp_valid_T_37 = mux(_io_resp_valid_T_9, idxPages[8], UInt<1>(0h0))
node _io_resp_valid_T_38 = mux(_io_resp_valid_T_10, idxPages[9], UInt<1>(0h0))
node _io_resp_valid_T_39 = mux(_io_resp_valid_T_11, idxPages[10], UInt<1>(0h0))
node _io_resp_valid_T_40 = mux(_io_resp_valid_T_12, idxPages[11], UInt<1>(0h0))
node _io_resp_valid_T_41 = mux(_io_resp_valid_T_13, idxPages[12], UInt<1>(0h0))
node _io_resp_valid_T_42 = mux(_io_resp_valid_T_14, idxPages[13], UInt<1>(0h0))
node _io_resp_valid_T_43 = mux(_io_resp_valid_T_15, idxPages[14], UInt<1>(0h0))
node _io_resp_valid_T_44 = mux(_io_resp_valid_T_16, idxPages[15], UInt<1>(0h0))
node _io_resp_valid_T_45 = mux(_io_resp_valid_T_17, idxPages[16], UInt<1>(0h0))
node _io_resp_valid_T_46 = mux(_io_resp_valid_T_18, idxPages[17], UInt<1>(0h0))
node _io_resp_valid_T_47 = mux(_io_resp_valid_T_19, idxPages[18], UInt<1>(0h0))
node _io_resp_valid_T_48 = mux(_io_resp_valid_T_20, idxPages[19], UInt<1>(0h0))
node _io_resp_valid_T_49 = mux(_io_resp_valid_T_21, idxPages[20], UInt<1>(0h0))
node _io_resp_valid_T_50 = mux(_io_resp_valid_T_22, idxPages[21], UInt<1>(0h0))
node _io_resp_valid_T_51 = mux(_io_resp_valid_T_23, idxPages[22], UInt<1>(0h0))
node _io_resp_valid_T_52 = mux(_io_resp_valid_T_24, idxPages[23], UInt<1>(0h0))
node _io_resp_valid_T_53 = mux(_io_resp_valid_T_25, idxPages[24], UInt<1>(0h0))
node _io_resp_valid_T_54 = mux(_io_resp_valid_T_26, idxPages[25], UInt<1>(0h0))
node _io_resp_valid_T_55 = mux(_io_resp_valid_T_27, idxPages[26], UInt<1>(0h0))
node _io_resp_valid_T_56 = mux(_io_resp_valid_T_28, idxPages[27], UInt<1>(0h0))
node _io_resp_valid_T_57 = or(_io_resp_valid_T_29, _io_resp_valid_T_30)
node _io_resp_valid_T_58 = or(_io_resp_valid_T_57, _io_resp_valid_T_31)
node _io_resp_valid_T_59 = or(_io_resp_valid_T_58, _io_resp_valid_T_32)
node _io_resp_valid_T_60 = or(_io_resp_valid_T_59, _io_resp_valid_T_33)
node _io_resp_valid_T_61 = or(_io_resp_valid_T_60, _io_resp_valid_T_34)
node _io_resp_valid_T_62 = or(_io_resp_valid_T_61, _io_resp_valid_T_35)
node _io_resp_valid_T_63 = or(_io_resp_valid_T_62, _io_resp_valid_T_36)
node _io_resp_valid_T_64 = or(_io_resp_valid_T_63, _io_resp_valid_T_37)
node _io_resp_valid_T_65 = or(_io_resp_valid_T_64, _io_resp_valid_T_38)
node _io_resp_valid_T_66 = or(_io_resp_valid_T_65, _io_resp_valid_T_39)
node _io_resp_valid_T_67 = or(_io_resp_valid_T_66, _io_resp_valid_T_40)
node _io_resp_valid_T_68 = or(_io_resp_valid_T_67, _io_resp_valid_T_41)
node _io_resp_valid_T_69 = or(_io_resp_valid_T_68, _io_resp_valid_T_42)
node _io_resp_valid_T_70 = or(_io_resp_valid_T_69, _io_resp_valid_T_43)
node _io_resp_valid_T_71 = or(_io_resp_valid_T_70, _io_resp_valid_T_44)
node _io_resp_valid_T_72 = or(_io_resp_valid_T_71, _io_resp_valid_T_45)
node _io_resp_valid_T_73 = or(_io_resp_valid_T_72, _io_resp_valid_T_46)
node _io_resp_valid_T_74 = or(_io_resp_valid_T_73, _io_resp_valid_T_47)
node _io_resp_valid_T_75 = or(_io_resp_valid_T_74, _io_resp_valid_T_48)
node _io_resp_valid_T_76 = or(_io_resp_valid_T_75, _io_resp_valid_T_49)
node _io_resp_valid_T_77 = or(_io_resp_valid_T_76, _io_resp_valid_T_50)
node _io_resp_valid_T_78 = or(_io_resp_valid_T_77, _io_resp_valid_T_51)
node _io_resp_valid_T_79 = or(_io_resp_valid_T_78, _io_resp_valid_T_52)
node _io_resp_valid_T_80 = or(_io_resp_valid_T_79, _io_resp_valid_T_53)
node _io_resp_valid_T_81 = or(_io_resp_valid_T_80, _io_resp_valid_T_54)
node _io_resp_valid_T_82 = or(_io_resp_valid_T_81, _io_resp_valid_T_55)
node _io_resp_valid_T_83 = or(_io_resp_valid_T_82, _io_resp_valid_T_56)
wire _io_resp_valid_WIRE : UInt<3>
connect _io_resp_valid_WIRE, _io_resp_valid_T_83
node _io_resp_valid_T_84 = dshr(_io_resp_valid_T, _io_resp_valid_WIRE)
node _io_resp_valid_T_85 = bits(_io_resp_valid_T_84, 0, 0)
connect io.resp.valid, _io_resp_valid_T_85
connect io.resp.bits.taken, UInt<1>(0h1)
node _io_resp_bits_target_T = bits(idxHit, 0, 0)
node _io_resp_bits_target_T_1 = bits(idxHit, 1, 1)
node _io_resp_bits_target_T_2 = bits(idxHit, 2, 2)
node _io_resp_bits_target_T_3 = bits(idxHit, 3, 3)
node _io_resp_bits_target_T_4 = bits(idxHit, 4, 4)
node _io_resp_bits_target_T_5 = bits(idxHit, 5, 5)
node _io_resp_bits_target_T_6 = bits(idxHit, 6, 6)
node _io_resp_bits_target_T_7 = bits(idxHit, 7, 7)
node _io_resp_bits_target_T_8 = bits(idxHit, 8, 8)
node _io_resp_bits_target_T_9 = bits(idxHit, 9, 9)
node _io_resp_bits_target_T_10 = bits(idxHit, 10, 10)
node _io_resp_bits_target_T_11 = bits(idxHit, 11, 11)
node _io_resp_bits_target_T_12 = bits(idxHit, 12, 12)
node _io_resp_bits_target_T_13 = bits(idxHit, 13, 13)
node _io_resp_bits_target_T_14 = bits(idxHit, 14, 14)
node _io_resp_bits_target_T_15 = bits(idxHit, 15, 15)
node _io_resp_bits_target_T_16 = bits(idxHit, 16, 16)
node _io_resp_bits_target_T_17 = bits(idxHit, 17, 17)
node _io_resp_bits_target_T_18 = bits(idxHit, 18, 18)
node _io_resp_bits_target_T_19 = bits(idxHit, 19, 19)
node _io_resp_bits_target_T_20 = bits(idxHit, 20, 20)
node _io_resp_bits_target_T_21 = bits(idxHit, 21, 21)
node _io_resp_bits_target_T_22 = bits(idxHit, 22, 22)
node _io_resp_bits_target_T_23 = bits(idxHit, 23, 23)
node _io_resp_bits_target_T_24 = bits(idxHit, 24, 24)
node _io_resp_bits_target_T_25 = bits(idxHit, 25, 25)
node _io_resp_bits_target_T_26 = bits(idxHit, 26, 26)
node _io_resp_bits_target_T_27 = bits(idxHit, 27, 27)
node _io_resp_bits_target_T_28 = mux(_io_resp_bits_target_T, tgtPages[0], UInt<1>(0h0))
node _io_resp_bits_target_T_29 = mux(_io_resp_bits_target_T_1, tgtPages[1], UInt<1>(0h0))
node _io_resp_bits_target_T_30 = mux(_io_resp_bits_target_T_2, tgtPages[2], UInt<1>(0h0))
node _io_resp_bits_target_T_31 = mux(_io_resp_bits_target_T_3, tgtPages[3], UInt<1>(0h0))
node _io_resp_bits_target_T_32 = mux(_io_resp_bits_target_T_4, tgtPages[4], UInt<1>(0h0))
node _io_resp_bits_target_T_33 = mux(_io_resp_bits_target_T_5, tgtPages[5], UInt<1>(0h0))
node _io_resp_bits_target_T_34 = mux(_io_resp_bits_target_T_6, tgtPages[6], UInt<1>(0h0))
node _io_resp_bits_target_T_35 = mux(_io_resp_bits_target_T_7, tgtPages[7], UInt<1>(0h0))
node _io_resp_bits_target_T_36 = mux(_io_resp_bits_target_T_8, tgtPages[8], UInt<1>(0h0))
node _io_resp_bits_target_T_37 = mux(_io_resp_bits_target_T_9, tgtPages[9], UInt<1>(0h0))
node _io_resp_bits_target_T_38 = mux(_io_resp_bits_target_T_10, tgtPages[10], UInt<1>(0h0))
node _io_resp_bits_target_T_39 = mux(_io_resp_bits_target_T_11, tgtPages[11], UInt<1>(0h0))
node _io_resp_bits_target_T_40 = mux(_io_resp_bits_target_T_12, tgtPages[12], UInt<1>(0h0))
node _io_resp_bits_target_T_41 = mux(_io_resp_bits_target_T_13, tgtPages[13], UInt<1>(0h0))
node _io_resp_bits_target_T_42 = mux(_io_resp_bits_target_T_14, tgtPages[14], UInt<1>(0h0))
node _io_resp_bits_target_T_43 = mux(_io_resp_bits_target_T_15, tgtPages[15], UInt<1>(0h0))
node _io_resp_bits_target_T_44 = mux(_io_resp_bits_target_T_16, tgtPages[16], UInt<1>(0h0))
node _io_resp_bits_target_T_45 = mux(_io_resp_bits_target_T_17, tgtPages[17], UInt<1>(0h0))
node _io_resp_bits_target_T_46 = mux(_io_resp_bits_target_T_18, tgtPages[18], UInt<1>(0h0))
node _io_resp_bits_target_T_47 = mux(_io_resp_bits_target_T_19, tgtPages[19], UInt<1>(0h0))
node _io_resp_bits_target_T_48 = mux(_io_resp_bits_target_T_20, tgtPages[20], UInt<1>(0h0))
node _io_resp_bits_target_T_49 = mux(_io_resp_bits_target_T_21, tgtPages[21], UInt<1>(0h0))
node _io_resp_bits_target_T_50 = mux(_io_resp_bits_target_T_22, tgtPages[22], UInt<1>(0h0))
node _io_resp_bits_target_T_51 = mux(_io_resp_bits_target_T_23, tgtPages[23], UInt<1>(0h0))
node _io_resp_bits_target_T_52 = mux(_io_resp_bits_target_T_24, tgtPages[24], UInt<1>(0h0))
node _io_resp_bits_target_T_53 = mux(_io_resp_bits_target_T_25, tgtPages[25], UInt<1>(0h0))
node _io_resp_bits_target_T_54 = mux(_io_resp_bits_target_T_26, tgtPages[26], UInt<1>(0h0))
node _io_resp_bits_target_T_55 = mux(_io_resp_bits_target_T_27, tgtPages[27], UInt<1>(0h0))
node _io_resp_bits_target_T_56 = or(_io_resp_bits_target_T_28, _io_resp_bits_target_T_29)
node _io_resp_bits_target_T_57 = or(_io_resp_bits_target_T_56, _io_resp_bits_target_T_30)
node _io_resp_bits_target_T_58 = or(_io_resp_bits_target_T_57, _io_resp_bits_target_T_31)
node _io_resp_bits_target_T_59 = or(_io_resp_bits_target_T_58, _io_resp_bits_target_T_32)
node _io_resp_bits_target_T_60 = or(_io_resp_bits_target_T_59, _io_resp_bits_target_T_33)
node _io_resp_bits_target_T_61 = or(_io_resp_bits_target_T_60, _io_resp_bits_target_T_34)
node _io_resp_bits_target_T_62 = or(_io_resp_bits_target_T_61, _io_resp_bits_target_T_35)
node _io_resp_bits_target_T_63 = or(_io_resp_bits_target_T_62, _io_resp_bits_target_T_36)
node _io_resp_bits_target_T_64 = or(_io_resp_bits_target_T_63, _io_resp_bits_target_T_37)
node _io_resp_bits_target_T_65 = or(_io_resp_bits_target_T_64, _io_resp_bits_target_T_38)
node _io_resp_bits_target_T_66 = or(_io_resp_bits_target_T_65, _io_resp_bits_target_T_39)
node _io_resp_bits_target_T_67 = or(_io_resp_bits_target_T_66, _io_resp_bits_target_T_40)
node _io_resp_bits_target_T_68 = or(_io_resp_bits_target_T_67, _io_resp_bits_target_T_41)
node _io_resp_bits_target_T_69 = or(_io_resp_bits_target_T_68, _io_resp_bits_target_T_42)
node _io_resp_bits_target_T_70 = or(_io_resp_bits_target_T_69, _io_resp_bits_target_T_43)
node _io_resp_bits_target_T_71 = or(_io_resp_bits_target_T_70, _io_resp_bits_target_T_44)
node _io_resp_bits_target_T_72 = or(_io_resp_bits_target_T_71, _io_resp_bits_target_T_45)
node _io_resp_bits_target_T_73 = or(_io_resp_bits_target_T_72, _io_resp_bits_target_T_46)
node _io_resp_bits_target_T_74 = or(_io_resp_bits_target_T_73, _io_resp_bits_target_T_47)
node _io_resp_bits_target_T_75 = or(_io_resp_bits_target_T_74, _io_resp_bits_target_T_48)
node _io_resp_bits_target_T_76 = or(_io_resp_bits_target_T_75, _io_resp_bits_target_T_49)
node _io_resp_bits_target_T_77 = or(_io_resp_bits_target_T_76, _io_resp_bits_target_T_50)
node _io_resp_bits_target_T_78 = or(_io_resp_bits_target_T_77, _io_resp_bits_target_T_51)
node _io_resp_bits_target_T_79 = or(_io_resp_bits_target_T_78, _io_resp_bits_target_T_52)
node _io_resp_bits_target_T_80 = or(_io_resp_bits_target_T_79, _io_resp_bits_target_T_53)
node _io_resp_bits_target_T_81 = or(_io_resp_bits_target_T_80, _io_resp_bits_target_T_54)
node _io_resp_bits_target_T_82 = or(_io_resp_bits_target_T_81, _io_resp_bits_target_T_55)
wire _io_resp_bits_target_WIRE : UInt<3>
connect _io_resp_bits_target_WIRE, _io_resp_bits_target_T_82
node _io_resp_bits_target_T_83 = eq(_io_resp_bits_target_WIRE, UInt<1>(0h1))
node _io_resp_bits_target_T_84 = mux(_io_resp_bits_target_T_83, pagesMasked_1, pagesMasked_0)
node _io_resp_bits_target_T_85 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h2))
node _io_resp_bits_target_T_86 = mux(_io_resp_bits_target_T_85, pagesMasked_2, _io_resp_bits_target_T_84)
node _io_resp_bits_target_T_87 = eq(_io_resp_bits_target_WIRE, UInt<2>(0h3))
node _io_resp_bits_target_T_88 = mux(_io_resp_bits_target_T_87, pagesMasked_3, _io_resp_bits_target_T_86)
node _io_resp_bits_target_T_89 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h4))
node _io_resp_bits_target_T_90 = mux(_io_resp_bits_target_T_89, pagesMasked_4, _io_resp_bits_target_T_88)
node _io_resp_bits_target_T_91 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h5))
node _io_resp_bits_target_T_92 = mux(_io_resp_bits_target_T_91, pagesMasked_5, _io_resp_bits_target_T_90)
node _io_resp_bits_target_T_93 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h6))
node _io_resp_bits_target_T_94 = mux(_io_resp_bits_target_T_93, pagesMasked_4, _io_resp_bits_target_T_92)
node _io_resp_bits_target_T_95 = eq(_io_resp_bits_target_WIRE, UInt<3>(0h7))
node _io_resp_bits_target_T_96 = mux(_io_resp_bits_target_T_95, pagesMasked_5, _io_resp_bits_target_T_94)
node _io_resp_bits_target_T_97 = bits(idxHit, 0, 0)
node _io_resp_bits_target_T_98 = bits(idxHit, 1, 1)
node _io_resp_bits_target_T_99 = bits(idxHit, 2, 2)
node _io_resp_bits_target_T_100 = bits(idxHit, 3, 3)
node _io_resp_bits_target_T_101 = bits(idxHit, 4, 4)
node _io_resp_bits_target_T_102 = bits(idxHit, 5, 5)
node _io_resp_bits_target_T_103 = bits(idxHit, 6, 6)
node _io_resp_bits_target_T_104 = bits(idxHit, 7, 7)
node _io_resp_bits_target_T_105 = bits(idxHit, 8, 8)
node _io_resp_bits_target_T_106 = bits(idxHit, 9, 9)
node _io_resp_bits_target_T_107 = bits(idxHit, 10, 10)
node _io_resp_bits_target_T_108 = bits(idxHit, 11, 11)
node _io_resp_bits_target_T_109 = bits(idxHit, 12, 12)
node _io_resp_bits_target_T_110 = bits(idxHit, 13, 13)
node _io_resp_bits_target_T_111 = bits(idxHit, 14, 14)
node _io_resp_bits_target_T_112 = bits(idxHit, 15, 15)
node _io_resp_bits_target_T_113 = bits(idxHit, 16, 16)
node _io_resp_bits_target_T_114 = bits(idxHit, 17, 17)
node _io_resp_bits_target_T_115 = bits(idxHit, 18, 18)
node _io_resp_bits_target_T_116 = bits(idxHit, 19, 19)
node _io_resp_bits_target_T_117 = bits(idxHit, 20, 20)
node _io_resp_bits_target_T_118 = bits(idxHit, 21, 21)
node _io_resp_bits_target_T_119 = bits(idxHit, 22, 22)
node _io_resp_bits_target_T_120 = bits(idxHit, 23, 23)
node _io_resp_bits_target_T_121 = bits(idxHit, 24, 24)
node _io_resp_bits_target_T_122 = bits(idxHit, 25, 25)
node _io_resp_bits_target_T_123 = bits(idxHit, 26, 26)
node _io_resp_bits_target_T_124 = bits(idxHit, 27, 27)
node _io_resp_bits_target_T_125 = mux(_io_resp_bits_target_T_97, tgts[0], UInt<1>(0h0))
node _io_resp_bits_target_T_126 = mux(_io_resp_bits_target_T_98, tgts[1], UInt<1>(0h0))
node _io_resp_bits_target_T_127 = mux(_io_resp_bits_target_T_99, tgts[2], UInt<1>(0h0))
node _io_resp_bits_target_T_128 = mux(_io_resp_bits_target_T_100, tgts[3], UInt<1>(0h0))
node _io_resp_bits_target_T_129 = mux(_io_resp_bits_target_T_101, tgts[4], UInt<1>(0h0))
node _io_resp_bits_target_T_130 = mux(_io_resp_bits_target_T_102, tgts[5], UInt<1>(0h0))
node _io_resp_bits_target_T_131 = mux(_io_resp_bits_target_T_103, tgts[6], UInt<1>(0h0))
node _io_resp_bits_target_T_132 = mux(_io_resp_bits_target_T_104, tgts[7], UInt<1>(0h0))
node _io_resp_bits_target_T_133 = mux(_io_resp_bits_target_T_105, tgts[8], UInt<1>(0h0))
node _io_resp_bits_target_T_134 = mux(_io_resp_bits_target_T_106, tgts[9], UInt<1>(0h0))
node _io_resp_bits_target_T_135 = mux(_io_resp_bits_target_T_107, tgts[10], UInt<1>(0h0))
node _io_resp_bits_target_T_136 = mux(_io_resp_bits_target_T_108, tgts[11], UInt<1>(0h0))
node _io_resp_bits_target_T_137 = mux(_io_resp_bits_target_T_109, tgts[12], UInt<1>(0h0))
node _io_resp_bits_target_T_138 = mux(_io_resp_bits_target_T_110, tgts[13], UInt<1>(0h0))
node _io_resp_bits_target_T_139 = mux(_io_resp_bits_target_T_111, tgts[14], UInt<1>(0h0))
node _io_resp_bits_target_T_140 = mux(_io_resp_bits_target_T_112, tgts[15], UInt<1>(0h0))
node _io_resp_bits_target_T_141 = mux(_io_resp_bits_target_T_113, tgts[16], UInt<1>(0h0))
node _io_resp_bits_target_T_142 = mux(_io_resp_bits_target_T_114, tgts[17], UInt<1>(0h0))
node _io_resp_bits_target_T_143 = mux(_io_resp_bits_target_T_115, tgts[18], UInt<1>(0h0))
node _io_resp_bits_target_T_144 = mux(_io_resp_bits_target_T_116, tgts[19], UInt<1>(0h0))
node _io_resp_bits_target_T_145 = mux(_io_resp_bits_target_T_117, tgts[20], UInt<1>(0h0))
node _io_resp_bits_target_T_146 = mux(_io_resp_bits_target_T_118, tgts[21], UInt<1>(0h0))
node _io_resp_bits_target_T_147 = mux(_io_resp_bits_target_T_119, tgts[22], UInt<1>(0h0))
node _io_resp_bits_target_T_148 = mux(_io_resp_bits_target_T_120, tgts[23], UInt<1>(0h0))
node _io_resp_bits_target_T_149 = mux(_io_resp_bits_target_T_121, tgts[24], UInt<1>(0h0))
node _io_resp_bits_target_T_150 = mux(_io_resp_bits_target_T_122, tgts[25], UInt<1>(0h0))
node _io_resp_bits_target_T_151 = mux(_io_resp_bits_target_T_123, tgts[26], UInt<1>(0h0))
node _io_resp_bits_target_T_152 = mux(_io_resp_bits_target_T_124, tgts[27], UInt<1>(0h0))
node _io_resp_bits_target_T_153 = or(_io_resp_bits_target_T_125, _io_resp_bits_target_T_126)
node _io_resp_bits_target_T_154 = or(_io_resp_bits_target_T_153, _io_resp_bits_target_T_127)
node _io_resp_bits_target_T_155 = or(_io_resp_bits_target_T_154, _io_resp_bits_target_T_128)
node _io_resp_bits_target_T_156 = or(_io_resp_bits_target_T_155, _io_resp_bits_target_T_129)
node _io_resp_bits_target_T_157 = or(_io_resp_bits_target_T_156, _io_resp_bits_target_T_130)
node _io_resp_bits_target_T_158 = or(_io_resp_bits_target_T_157, _io_resp_bits_target_T_131)
node _io_resp_bits_target_T_159 = or(_io_resp_bits_target_T_158, _io_resp_bits_target_T_132)
node _io_resp_bits_target_T_160 = or(_io_resp_bits_target_T_159, _io_resp_bits_target_T_133)
node _io_resp_bits_target_T_161 = or(_io_resp_bits_target_T_160, _io_resp_bits_target_T_134)
node _io_resp_bits_target_T_162 = or(_io_resp_bits_target_T_161, _io_resp_bits_target_T_135)
node _io_resp_bits_target_T_163 = or(_io_resp_bits_target_T_162, _io_resp_bits_target_T_136)
node _io_resp_bits_target_T_164 = or(_io_resp_bits_target_T_163, _io_resp_bits_target_T_137)
node _io_resp_bits_target_T_165 = or(_io_resp_bits_target_T_164, _io_resp_bits_target_T_138)
node _io_resp_bits_target_T_166 = or(_io_resp_bits_target_T_165, _io_resp_bits_target_T_139)
node _io_resp_bits_target_T_167 = or(_io_resp_bits_target_T_166, _io_resp_bits_target_T_140)
node _io_resp_bits_target_T_168 = or(_io_resp_bits_target_T_167, _io_resp_bits_target_T_141)
node _io_resp_bits_target_T_169 = or(_io_resp_bits_target_T_168, _io_resp_bits_target_T_142)
node _io_resp_bits_target_T_170 = or(_io_resp_bits_target_T_169, _io_resp_bits_target_T_143)
node _io_resp_bits_target_T_171 = or(_io_resp_bits_target_T_170, _io_resp_bits_target_T_144)
node _io_resp_bits_target_T_172 = or(_io_resp_bits_target_T_171, _io_resp_bits_target_T_145)
node _io_resp_bits_target_T_173 = or(_io_resp_bits_target_T_172, _io_resp_bits_target_T_146)
node _io_resp_bits_target_T_174 = or(_io_resp_bits_target_T_173, _io_resp_bits_target_T_147)
node _io_resp_bits_target_T_175 = or(_io_resp_bits_target_T_174, _io_resp_bits_target_T_148)
node _io_resp_bits_target_T_176 = or(_io_resp_bits_target_T_175, _io_resp_bits_target_T_149)
node _io_resp_bits_target_T_177 = or(_io_resp_bits_target_T_176, _io_resp_bits_target_T_150)
node _io_resp_bits_target_T_178 = or(_io_resp_bits_target_T_177, _io_resp_bits_target_T_151)
node _io_resp_bits_target_T_179 = or(_io_resp_bits_target_T_178, _io_resp_bits_target_T_152)
wire _io_resp_bits_target_WIRE_1 : UInt<13>
connect _io_resp_bits_target_WIRE_1, _io_resp_bits_target_T_179
node _io_resp_bits_target_T_180 = shl(_io_resp_bits_target_WIRE_1, 1)
node _io_resp_bits_target_T_181 = cat(_io_resp_bits_target_T_96, _io_resp_bits_target_T_180)
connect io.resp.bits.target, _io_resp_bits_target_T_181
node io_resp_bits_entry_hi = bits(idxHit, 27, 16)
node io_resp_bits_entry_lo = bits(idxHit, 15, 0)
node _io_resp_bits_entry_T = orr(io_resp_bits_entry_hi)
node _io_resp_bits_entry_T_1 = or(io_resp_bits_entry_hi, io_resp_bits_entry_lo)
node io_resp_bits_entry_hi_1 = bits(_io_resp_bits_entry_T_1, 15, 8)
node io_resp_bits_entry_lo_1 = bits(_io_resp_bits_entry_T_1, 7, 0)
node _io_resp_bits_entry_T_2 = orr(io_resp_bits_entry_hi_1)
node _io_resp_bits_entry_T_3 = or(io_resp_bits_entry_hi_1, io_resp_bits_entry_lo_1)
node io_resp_bits_entry_hi_2 = bits(_io_resp_bits_entry_T_3, 7, 4)
node io_resp_bits_entry_lo_2 = bits(_io_resp_bits_entry_T_3, 3, 0)
node _io_resp_bits_entry_T_4 = orr(io_resp_bits_entry_hi_2)
node _io_resp_bits_entry_T_5 = or(io_resp_bits_entry_hi_2, io_resp_bits_entry_lo_2)
node io_resp_bits_entry_hi_3 = bits(_io_resp_bits_entry_T_5, 3, 2)
node io_resp_bits_entry_lo_3 = bits(_io_resp_bits_entry_T_5, 1, 0)
node _io_resp_bits_entry_T_6 = orr(io_resp_bits_entry_hi_3)
node _io_resp_bits_entry_T_7 = or(io_resp_bits_entry_hi_3, io_resp_bits_entry_lo_3)
node _io_resp_bits_entry_T_8 = bits(_io_resp_bits_entry_T_7, 1, 1)
node _io_resp_bits_entry_T_9 = cat(_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8)
node _io_resp_bits_entry_T_10 = cat(_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9)
node _io_resp_bits_entry_T_11 = cat(_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10)
node _io_resp_bits_entry_T_12 = cat(_io_resp_bits_entry_T, _io_resp_bits_entry_T_11)
connect io.resp.bits.entry, _io_resp_bits_entry_T_12
node _io_resp_bits_bridx_T = bits(idxHit, 0, 0)
node _io_resp_bits_bridx_T_1 = bits(idxHit, 1, 1)
node _io_resp_bits_bridx_T_2 = bits(idxHit, 2, 2)
node _io_resp_bits_bridx_T_3 = bits(idxHit, 3, 3)
node _io_resp_bits_bridx_T_4 = bits(idxHit, 4, 4)
node _io_resp_bits_bridx_T_5 = bits(idxHit, 5, 5)
node _io_resp_bits_bridx_T_6 = bits(idxHit, 6, 6)
node _io_resp_bits_bridx_T_7 = bits(idxHit, 7, 7)
node _io_resp_bits_bridx_T_8 = bits(idxHit, 8, 8)
node _io_resp_bits_bridx_T_9 = bits(idxHit, 9, 9)
node _io_resp_bits_bridx_T_10 = bits(idxHit, 10, 10)
node _io_resp_bits_bridx_T_11 = bits(idxHit, 11, 11)
node _io_resp_bits_bridx_T_12 = bits(idxHit, 12, 12)
node _io_resp_bits_bridx_T_13 = bits(idxHit, 13, 13)
node _io_resp_bits_bridx_T_14 = bits(idxHit, 14, 14)
node _io_resp_bits_bridx_T_15 = bits(idxHit, 15, 15)
node _io_resp_bits_bridx_T_16 = bits(idxHit, 16, 16)
node _io_resp_bits_bridx_T_17 = bits(idxHit, 17, 17)
node _io_resp_bits_bridx_T_18 = bits(idxHit, 18, 18)
node _io_resp_bits_bridx_T_19 = bits(idxHit, 19, 19)
node _io_resp_bits_bridx_T_20 = bits(idxHit, 20, 20)
node _io_resp_bits_bridx_T_21 = bits(idxHit, 21, 21)
node _io_resp_bits_bridx_T_22 = bits(idxHit, 22, 22)
node _io_resp_bits_bridx_T_23 = bits(idxHit, 23, 23)
node _io_resp_bits_bridx_T_24 = bits(idxHit, 24, 24)
node _io_resp_bits_bridx_T_25 = bits(idxHit, 25, 25)
node _io_resp_bits_bridx_T_26 = bits(idxHit, 26, 26)
node _io_resp_bits_bridx_T_27 = bits(idxHit, 27, 27)
node _io_resp_bits_bridx_T_28 = mux(_io_resp_bits_bridx_T, brIdx[0], UInt<1>(0h0))
node _io_resp_bits_bridx_T_29 = mux(_io_resp_bits_bridx_T_1, brIdx[1], UInt<1>(0h0))
node _io_resp_bits_bridx_T_30 = mux(_io_resp_bits_bridx_T_2, brIdx[2], UInt<1>(0h0))
node _io_resp_bits_bridx_T_31 = mux(_io_resp_bits_bridx_T_3, brIdx[3], UInt<1>(0h0))
node _io_resp_bits_bridx_T_32 = mux(_io_resp_bits_bridx_T_4, brIdx[4], UInt<1>(0h0))
node _io_resp_bits_bridx_T_33 = mux(_io_resp_bits_bridx_T_5, brIdx[5], UInt<1>(0h0))
node _io_resp_bits_bridx_T_34 = mux(_io_resp_bits_bridx_T_6, brIdx[6], UInt<1>(0h0))
node _io_resp_bits_bridx_T_35 = mux(_io_resp_bits_bridx_T_7, brIdx[7], UInt<1>(0h0))
node _io_resp_bits_bridx_T_36 = mux(_io_resp_bits_bridx_T_8, brIdx[8], UInt<1>(0h0))
node _io_resp_bits_bridx_T_37 = mux(_io_resp_bits_bridx_T_9, brIdx[9], UInt<1>(0h0))
node _io_resp_bits_bridx_T_38 = mux(_io_resp_bits_bridx_T_10, brIdx[10], UInt<1>(0h0))
node _io_resp_bits_bridx_T_39 = mux(_io_resp_bits_bridx_T_11, brIdx[11], UInt<1>(0h0))
node _io_resp_bits_bridx_T_40 = mux(_io_resp_bits_bridx_T_12, brIdx[12], UInt<1>(0h0))
node _io_resp_bits_bridx_T_41 = mux(_io_resp_bits_bridx_T_13, brIdx[13], UInt<1>(0h0))
node _io_resp_bits_bridx_T_42 = mux(_io_resp_bits_bridx_T_14, brIdx[14], UInt<1>(0h0))
node _io_resp_bits_bridx_T_43 = mux(_io_resp_bits_bridx_T_15, brIdx[15], UInt<1>(0h0))
node _io_resp_bits_bridx_T_44 = mux(_io_resp_bits_bridx_T_16, brIdx[16], UInt<1>(0h0))
node _io_resp_bits_bridx_T_45 = mux(_io_resp_bits_bridx_T_17, brIdx[17], UInt<1>(0h0))
node _io_resp_bits_bridx_T_46 = mux(_io_resp_bits_bridx_T_18, brIdx[18], UInt<1>(0h0))
node _io_resp_bits_bridx_T_47 = mux(_io_resp_bits_bridx_T_19, brIdx[19], UInt<1>(0h0))
node _io_resp_bits_bridx_T_48 = mux(_io_resp_bits_bridx_T_20, brIdx[20], UInt<1>(0h0))
node _io_resp_bits_bridx_T_49 = mux(_io_resp_bits_bridx_T_21, brIdx[21], UInt<1>(0h0))
node _io_resp_bits_bridx_T_50 = mux(_io_resp_bits_bridx_T_22, brIdx[22], UInt<1>(0h0))
node _io_resp_bits_bridx_T_51 = mux(_io_resp_bits_bridx_T_23, brIdx[23], UInt<1>(0h0))
node _io_resp_bits_bridx_T_52 = mux(_io_resp_bits_bridx_T_24, brIdx[24], UInt<1>(0h0))
node _io_resp_bits_bridx_T_53 = mux(_io_resp_bits_bridx_T_25, brIdx[25], UInt<1>(0h0))
node _io_resp_bits_bridx_T_54 = mux(_io_resp_bits_bridx_T_26, brIdx[26], UInt<1>(0h0))
node _io_resp_bits_bridx_T_55 = mux(_io_resp_bits_bridx_T_27, brIdx[27], UInt<1>(0h0))
node _io_resp_bits_bridx_T_56 = or(_io_resp_bits_bridx_T_28, _io_resp_bits_bridx_T_29)
node _io_resp_bits_bridx_T_57 = or(_io_resp_bits_bridx_T_56, _io_resp_bits_bridx_T_30)
node _io_resp_bits_bridx_T_58 = or(_io_resp_bits_bridx_T_57, _io_resp_bits_bridx_T_31)
node _io_resp_bits_bridx_T_59 = or(_io_resp_bits_bridx_T_58, _io_resp_bits_bridx_T_32)
node _io_resp_bits_bridx_T_60 = or(_io_resp_bits_bridx_T_59, _io_resp_bits_bridx_T_33)
node _io_resp_bits_bridx_T_61 = or(_io_resp_bits_bridx_T_60, _io_resp_bits_bridx_T_34)
node _io_resp_bits_bridx_T_62 = or(_io_resp_bits_bridx_T_61, _io_resp_bits_bridx_T_35)
node _io_resp_bits_bridx_T_63 = or(_io_resp_bits_bridx_T_62, _io_resp_bits_bridx_T_36)
node _io_resp_bits_bridx_T_64 = or(_io_resp_bits_bridx_T_63, _io_resp_bits_bridx_T_37)
node _io_resp_bits_bridx_T_65 = or(_io_resp_bits_bridx_T_64, _io_resp_bits_bridx_T_38)
node _io_resp_bits_bridx_T_66 = or(_io_resp_bits_bridx_T_65, _io_resp_bits_bridx_T_39)
node _io_resp_bits_bridx_T_67 = or(_io_resp_bits_bridx_T_66, _io_resp_bits_bridx_T_40)
node _io_resp_bits_bridx_T_68 = or(_io_resp_bits_bridx_T_67, _io_resp_bits_bridx_T_41)
node _io_resp_bits_bridx_T_69 = or(_io_resp_bits_bridx_T_68, _io_resp_bits_bridx_T_42)
node _io_resp_bits_bridx_T_70 = or(_io_resp_bits_bridx_T_69, _io_resp_bits_bridx_T_43)
node _io_resp_bits_bridx_T_71 = or(_io_resp_bits_bridx_T_70, _io_resp_bits_bridx_T_44)
node _io_resp_bits_bridx_T_72 = or(_io_resp_bits_bridx_T_71, _io_resp_bits_bridx_T_45)
node _io_resp_bits_bridx_T_73 = or(_io_resp_bits_bridx_T_72, _io_resp_bits_bridx_T_46)
node _io_resp_bits_bridx_T_74 = or(_io_resp_bits_bridx_T_73, _io_resp_bits_bridx_T_47)
node _io_resp_bits_bridx_T_75 = or(_io_resp_bits_bridx_T_74, _io_resp_bits_bridx_T_48)
node _io_resp_bits_bridx_T_76 = or(_io_resp_bits_bridx_T_75, _io_resp_bits_bridx_T_49)
node _io_resp_bits_bridx_T_77 = or(_io_resp_bits_bridx_T_76, _io_resp_bits_bridx_T_50)
node _io_resp_bits_bridx_T_78 = or(_io_resp_bits_bridx_T_77, _io_resp_bits_bridx_T_51)
node _io_resp_bits_bridx_T_79 = or(_io_resp_bits_bridx_T_78, _io_resp_bits_bridx_T_52)
node _io_resp_bits_bridx_T_80 = or(_io_resp_bits_bridx_T_79, _io_resp_bits_bridx_T_53)
node _io_resp_bits_bridx_T_81 = or(_io_resp_bits_bridx_T_80, _io_resp_bits_bridx_T_54)
node _io_resp_bits_bridx_T_82 = or(_io_resp_bits_bridx_T_81, _io_resp_bits_bridx_T_55)
wire _io_resp_bits_bridx_WIRE : UInt<1>
connect _io_resp_bits_bridx_WIRE, _io_resp_bits_bridx_T_82
connect io.resp.bits.bridx, _io_resp_bits_bridx_WIRE
node _io_resp_bits_mask_T = not(io.resp.bits.bridx)
node _io_resp_bits_mask_T_1 = mux(io.resp.bits.taken, _io_resp_bits_mask_T, UInt<1>(0h0))
node _io_resp_bits_mask_T_2 = not(_io_resp_bits_mask_T_1)
node _io_resp_bits_mask_T_3 = dshl(UInt<1>(0h1), _io_resp_bits_mask_T_2)
node _io_resp_bits_mask_T_4 = sub(_io_resp_bits_mask_T_3, UInt<1>(0h1))
node _io_resp_bits_mask_T_5 = tail(_io_resp_bits_mask_T_4, 1)
node _io_resp_bits_mask_T_6 = cat(_io_resp_bits_mask_T_5, UInt<1>(0h1))
connect io.resp.bits.mask, _io_resp_bits_mask_T_6
node _io_resp_bits_cfiType_T = bits(idxHit, 0, 0)
node _io_resp_bits_cfiType_T_1 = bits(idxHit, 1, 1)
node _io_resp_bits_cfiType_T_2 = bits(idxHit, 2, 2)
node _io_resp_bits_cfiType_T_3 = bits(idxHit, 3, 3)
node _io_resp_bits_cfiType_T_4 = bits(idxHit, 4, 4)
node _io_resp_bits_cfiType_T_5 = bits(idxHit, 5, 5)
node _io_resp_bits_cfiType_T_6 = bits(idxHit, 6, 6)
node _io_resp_bits_cfiType_T_7 = bits(idxHit, 7, 7)
node _io_resp_bits_cfiType_T_8 = bits(idxHit, 8, 8)
node _io_resp_bits_cfiType_T_9 = bits(idxHit, 9, 9)
node _io_resp_bits_cfiType_T_10 = bits(idxHit, 10, 10)
node _io_resp_bits_cfiType_T_11 = bits(idxHit, 11, 11)
node _io_resp_bits_cfiType_T_12 = bits(idxHit, 12, 12)
node _io_resp_bits_cfiType_T_13 = bits(idxHit, 13, 13)
node _io_resp_bits_cfiType_T_14 = bits(idxHit, 14, 14)
node _io_resp_bits_cfiType_T_15 = bits(idxHit, 15, 15)
node _io_resp_bits_cfiType_T_16 = bits(idxHit, 16, 16)
node _io_resp_bits_cfiType_T_17 = bits(idxHit, 17, 17)
node _io_resp_bits_cfiType_T_18 = bits(idxHit, 18, 18)
node _io_resp_bits_cfiType_T_19 = bits(idxHit, 19, 19)
node _io_resp_bits_cfiType_T_20 = bits(idxHit, 20, 20)
node _io_resp_bits_cfiType_T_21 = bits(idxHit, 21, 21)
node _io_resp_bits_cfiType_T_22 = bits(idxHit, 22, 22)
node _io_resp_bits_cfiType_T_23 = bits(idxHit, 23, 23)
node _io_resp_bits_cfiType_T_24 = bits(idxHit, 24, 24)
node _io_resp_bits_cfiType_T_25 = bits(idxHit, 25, 25)
node _io_resp_bits_cfiType_T_26 = bits(idxHit, 26, 26)
node _io_resp_bits_cfiType_T_27 = bits(idxHit, 27, 27)
node _io_resp_bits_cfiType_T_28 = mux(_io_resp_bits_cfiType_T, cfiType[0], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_29 = mux(_io_resp_bits_cfiType_T_1, cfiType[1], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_30 = mux(_io_resp_bits_cfiType_T_2, cfiType[2], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_31 = mux(_io_resp_bits_cfiType_T_3, cfiType[3], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_32 = mux(_io_resp_bits_cfiType_T_4, cfiType[4], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_33 = mux(_io_resp_bits_cfiType_T_5, cfiType[5], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_34 = mux(_io_resp_bits_cfiType_T_6, cfiType[6], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_35 = mux(_io_resp_bits_cfiType_T_7, cfiType[7], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_36 = mux(_io_resp_bits_cfiType_T_8, cfiType[8], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_37 = mux(_io_resp_bits_cfiType_T_9, cfiType[9], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_38 = mux(_io_resp_bits_cfiType_T_10, cfiType[10], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_39 = mux(_io_resp_bits_cfiType_T_11, cfiType[11], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_40 = mux(_io_resp_bits_cfiType_T_12, cfiType[12], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_41 = mux(_io_resp_bits_cfiType_T_13, cfiType[13], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_42 = mux(_io_resp_bits_cfiType_T_14, cfiType[14], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_43 = mux(_io_resp_bits_cfiType_T_15, cfiType[15], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_44 = mux(_io_resp_bits_cfiType_T_16, cfiType[16], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_45 = mux(_io_resp_bits_cfiType_T_17, cfiType[17], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_46 = mux(_io_resp_bits_cfiType_T_18, cfiType[18], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_47 = mux(_io_resp_bits_cfiType_T_19, cfiType[19], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_48 = mux(_io_resp_bits_cfiType_T_20, cfiType[20], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_49 = mux(_io_resp_bits_cfiType_T_21, cfiType[21], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_50 = mux(_io_resp_bits_cfiType_T_22, cfiType[22], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_51 = mux(_io_resp_bits_cfiType_T_23, cfiType[23], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_52 = mux(_io_resp_bits_cfiType_T_24, cfiType[24], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_53 = mux(_io_resp_bits_cfiType_T_25, cfiType[25], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_54 = mux(_io_resp_bits_cfiType_T_26, cfiType[26], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_55 = mux(_io_resp_bits_cfiType_T_27, cfiType[27], UInt<1>(0h0))
node _io_resp_bits_cfiType_T_56 = or(_io_resp_bits_cfiType_T_28, _io_resp_bits_cfiType_T_29)
node _io_resp_bits_cfiType_T_57 = or(_io_resp_bits_cfiType_T_56, _io_resp_bits_cfiType_T_30)
node _io_resp_bits_cfiType_T_58 = or(_io_resp_bits_cfiType_T_57, _io_resp_bits_cfiType_T_31)
node _io_resp_bits_cfiType_T_59 = or(_io_resp_bits_cfiType_T_58, _io_resp_bits_cfiType_T_32)
node _io_resp_bits_cfiType_T_60 = or(_io_resp_bits_cfiType_T_59, _io_resp_bits_cfiType_T_33)
node _io_resp_bits_cfiType_T_61 = or(_io_resp_bits_cfiType_T_60, _io_resp_bits_cfiType_T_34)
node _io_resp_bits_cfiType_T_62 = or(_io_resp_bits_cfiType_T_61, _io_resp_bits_cfiType_T_35)
node _io_resp_bits_cfiType_T_63 = or(_io_resp_bits_cfiType_T_62, _io_resp_bits_cfiType_T_36)
node _io_resp_bits_cfiType_T_64 = or(_io_resp_bits_cfiType_T_63, _io_resp_bits_cfiType_T_37)
node _io_resp_bits_cfiType_T_65 = or(_io_resp_bits_cfiType_T_64, _io_resp_bits_cfiType_T_38)
node _io_resp_bits_cfiType_T_66 = or(_io_resp_bits_cfiType_T_65, _io_resp_bits_cfiType_T_39)
node _io_resp_bits_cfiType_T_67 = or(_io_resp_bits_cfiType_T_66, _io_resp_bits_cfiType_T_40)
node _io_resp_bits_cfiType_T_68 = or(_io_resp_bits_cfiType_T_67, _io_resp_bits_cfiType_T_41)
node _io_resp_bits_cfiType_T_69 = or(_io_resp_bits_cfiType_T_68, _io_resp_bits_cfiType_T_42)
node _io_resp_bits_cfiType_T_70 = or(_io_resp_bits_cfiType_T_69, _io_resp_bits_cfiType_T_43)
node _io_resp_bits_cfiType_T_71 = or(_io_resp_bits_cfiType_T_70, _io_resp_bits_cfiType_T_44)
node _io_resp_bits_cfiType_T_72 = or(_io_resp_bits_cfiType_T_71, _io_resp_bits_cfiType_T_45)
node _io_resp_bits_cfiType_T_73 = or(_io_resp_bits_cfiType_T_72, _io_resp_bits_cfiType_T_46)
node _io_resp_bits_cfiType_T_74 = or(_io_resp_bits_cfiType_T_73, _io_resp_bits_cfiType_T_47)
node _io_resp_bits_cfiType_T_75 = or(_io_resp_bits_cfiType_T_74, _io_resp_bits_cfiType_T_48)
node _io_resp_bits_cfiType_T_76 = or(_io_resp_bits_cfiType_T_75, _io_resp_bits_cfiType_T_49)
node _io_resp_bits_cfiType_T_77 = or(_io_resp_bits_cfiType_T_76, _io_resp_bits_cfiType_T_50)
node _io_resp_bits_cfiType_T_78 = or(_io_resp_bits_cfiType_T_77, _io_resp_bits_cfiType_T_51)
node _io_resp_bits_cfiType_T_79 = or(_io_resp_bits_cfiType_T_78, _io_resp_bits_cfiType_T_52)
node _io_resp_bits_cfiType_T_80 = or(_io_resp_bits_cfiType_T_79, _io_resp_bits_cfiType_T_53)
node _io_resp_bits_cfiType_T_81 = or(_io_resp_bits_cfiType_T_80, _io_resp_bits_cfiType_T_54)
node _io_resp_bits_cfiType_T_82 = or(_io_resp_bits_cfiType_T_81, _io_resp_bits_cfiType_T_55)
wire _io_resp_bits_cfiType_WIRE : UInt<2>
connect _io_resp_bits_cfiType_WIRE, _io_resp_bits_cfiType_T_82
connect io.resp.bits.cfiType, _io_resp_bits_cfiType_WIRE
node _T_19 = bits(idxHit, 13, 0)
node _T_20 = bits(_T_19, 6, 0)
node _T_21 = bits(_T_20, 2, 0)
node _T_22 = bits(_T_21, 0, 0)
node leftOne = bits(_T_22, 0, 0)
node _T_23 = bits(_T_21, 2, 1)
node _T_24 = bits(_T_23, 0, 0)
node leftOne_1 = bits(_T_24, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node rightOne = bits(_T_25, 0, 0)
node rightOne_1 = or(leftOne_1, rightOne)
node _T_26 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_27 = and(leftOne_1, rightOne)
node rightTwo = or(_T_26, _T_27)
node leftOne_2 = or(leftOne, rightOne_1)
node _T_28 = or(UInt<1>(0h0), rightTwo)
node _T_29 = and(leftOne, rightOne_1)
node leftTwo = or(_T_28, _T_29)
node _T_30 = bits(_T_20, 6, 3)
node _T_31 = bits(_T_30, 1, 0)
node _T_32 = bits(_T_31, 0, 0)
node leftOne_3 = bits(_T_32, 0, 0)
node _T_33 = bits(_T_31, 1, 1)
node rightOne_2 = bits(_T_33, 0, 0)
node leftOne_4 = or(leftOne_3, rightOne_2)
node _T_34 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_35 = and(leftOne_3, rightOne_2)
node leftTwo_1 = or(_T_34, _T_35)
node _T_36 = bits(_T_30, 3, 2)
node _T_37 = bits(_T_36, 0, 0)
node leftOne_5 = bits(_T_37, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node rightOne_3 = bits(_T_38, 0, 0)
node rightOne_4 = or(leftOne_5, rightOne_3)
node _T_39 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_40 = and(leftOne_5, rightOne_3)
node rightTwo_1 = or(_T_39, _T_40)
node rightOne_5 = or(leftOne_4, rightOne_4)
node _T_41 = or(leftTwo_1, rightTwo_1)
node _T_42 = and(leftOne_4, rightOne_4)
node rightTwo_2 = or(_T_41, _T_42)
node leftOne_6 = or(leftOne_2, rightOne_5)
node _T_43 = or(leftTwo, rightTwo_2)
node _T_44 = and(leftOne_2, rightOne_5)
node leftTwo_2 = or(_T_43, _T_44)
node _T_45 = bits(_T_19, 13, 7)
node _T_46 = bits(_T_45, 2, 0)
node _T_47 = bits(_T_46, 0, 0)
node leftOne_7 = bits(_T_47, 0, 0)
node _T_48 = bits(_T_46, 2, 1)
node _T_49 = bits(_T_48, 0, 0)
node leftOne_8 = bits(_T_49, 0, 0)
node _T_50 = bits(_T_48, 1, 1)
node rightOne_6 = bits(_T_50, 0, 0)
node rightOne_7 = or(leftOne_8, rightOne_6)
node _T_51 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_52 = and(leftOne_8, rightOne_6)
node rightTwo_3 = or(_T_51, _T_52)
node leftOne_9 = or(leftOne_7, rightOne_7)
node _T_53 = or(UInt<1>(0h0), rightTwo_3)
node _T_54 = and(leftOne_7, rightOne_7)
node leftTwo_3 = or(_T_53, _T_54)
node _T_55 = bits(_T_45, 6, 3)
node _T_56 = bits(_T_55, 1, 0)
node _T_57 = bits(_T_56, 0, 0)
node leftOne_10 = bits(_T_57, 0, 0)
node _T_58 = bits(_T_56, 1, 1)
node rightOne_8 = bits(_T_58, 0, 0)
node leftOne_11 = or(leftOne_10, rightOne_8)
node _T_59 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_60 = and(leftOne_10, rightOne_8)
node leftTwo_4 = or(_T_59, _T_60)
node _T_61 = bits(_T_55, 3, 2)
node _T_62 = bits(_T_61, 0, 0)
node leftOne_12 = bits(_T_62, 0, 0)
node _T_63 = bits(_T_61, 1, 1)
node rightOne_9 = bits(_T_63, 0, 0)
node rightOne_10 = or(leftOne_12, rightOne_9)
node _T_64 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_65 = and(leftOne_12, rightOne_9)
node rightTwo_4 = or(_T_64, _T_65)
node rightOne_11 = or(leftOne_11, rightOne_10)
node _T_66 = or(leftTwo_4, rightTwo_4)
node _T_67 = and(leftOne_11, rightOne_10)
node rightTwo_5 = or(_T_66, _T_67)
node rightOne_12 = or(leftOne_9, rightOne_11)
node _T_68 = or(leftTwo_3, rightTwo_5)
node _T_69 = and(leftOne_9, rightOne_11)
node rightTwo_6 = or(_T_68, _T_69)
node leftOne_13 = or(leftOne_6, rightOne_12)
node _T_70 = or(leftTwo_2, rightTwo_6)
node _T_71 = and(leftOne_6, rightOne_12)
node leftTwo_5 = or(_T_70, _T_71)
node _T_72 = bits(idxHit, 27, 14)
node _T_73 = bits(_T_72, 6, 0)
node _T_74 = bits(_T_73, 2, 0)
node _T_75 = bits(_T_74, 0, 0)
node leftOne_14 = bits(_T_75, 0, 0)
node _T_76 = bits(_T_74, 2, 1)
node _T_77 = bits(_T_76, 0, 0)
node leftOne_15 = bits(_T_77, 0, 0)
node _T_78 = bits(_T_76, 1, 1)
node rightOne_13 = bits(_T_78, 0, 0)
node rightOne_14 = or(leftOne_15, rightOne_13)
node _T_79 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_80 = and(leftOne_15, rightOne_13)
node rightTwo_7 = or(_T_79, _T_80)
node leftOne_16 = or(leftOne_14, rightOne_14)
node _T_81 = or(UInt<1>(0h0), rightTwo_7)
node _T_82 = and(leftOne_14, rightOne_14)
node leftTwo_6 = or(_T_81, _T_82)
node _T_83 = bits(_T_73, 6, 3)
node _T_84 = bits(_T_83, 1, 0)
node _T_85 = bits(_T_84, 0, 0)
node leftOne_17 = bits(_T_85, 0, 0)
node _T_86 = bits(_T_84, 1, 1)
node rightOne_15 = bits(_T_86, 0, 0)
node leftOne_18 = or(leftOne_17, rightOne_15)
node _T_87 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_88 = and(leftOne_17, rightOne_15)
node leftTwo_7 = or(_T_87, _T_88)
node _T_89 = bits(_T_83, 3, 2)
node _T_90 = bits(_T_89, 0, 0)
node leftOne_19 = bits(_T_90, 0, 0)
node _T_91 = bits(_T_89, 1, 1)
node rightOne_16 = bits(_T_91, 0, 0)
node rightOne_17 = or(leftOne_19, rightOne_16)
node _T_92 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_93 = and(leftOne_19, rightOne_16)
node rightTwo_8 = or(_T_92, _T_93)
node rightOne_18 = or(leftOne_18, rightOne_17)
node _T_94 = or(leftTwo_7, rightTwo_8)
node _T_95 = and(leftOne_18, rightOne_17)
node rightTwo_9 = or(_T_94, _T_95)
node leftOne_20 = or(leftOne_16, rightOne_18)
node _T_96 = or(leftTwo_6, rightTwo_9)
node _T_97 = and(leftOne_16, rightOne_18)
node leftTwo_8 = or(_T_96, _T_97)
node _T_98 = bits(_T_72, 13, 7)
node _T_99 = bits(_T_98, 2, 0)
node _T_100 = bits(_T_99, 0, 0)
node leftOne_21 = bits(_T_100, 0, 0)
node _T_101 = bits(_T_99, 2, 1)
node _T_102 = bits(_T_101, 0, 0)
node leftOne_22 = bits(_T_102, 0, 0)
node _T_103 = bits(_T_101, 1, 1)
node rightOne_19 = bits(_T_103, 0, 0)
node rightOne_20 = or(leftOne_22, rightOne_19)
node _T_104 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_105 = and(leftOne_22, rightOne_19)
node rightTwo_10 = or(_T_104, _T_105)
node leftOne_23 = or(leftOne_21, rightOne_20)
node _T_106 = or(UInt<1>(0h0), rightTwo_10)
node _T_107 = and(leftOne_21, rightOne_20)
node leftTwo_9 = or(_T_106, _T_107)
node _T_108 = bits(_T_98, 6, 3)
node _T_109 = bits(_T_108, 1, 0)
node _T_110 = bits(_T_109, 0, 0)
node leftOne_24 = bits(_T_110, 0, 0)
node _T_111 = bits(_T_109, 1, 1)
node rightOne_21 = bits(_T_111, 0, 0)
node leftOne_25 = or(leftOne_24, rightOne_21)
node _T_112 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_113 = and(leftOne_24, rightOne_21)
node leftTwo_10 = or(_T_112, _T_113)
node _T_114 = bits(_T_108, 3, 2)
node _T_115 = bits(_T_114, 0, 0)
node leftOne_26 = bits(_T_115, 0, 0)
node _T_116 = bits(_T_114, 1, 1)
node rightOne_22 = bits(_T_116, 0, 0)
node rightOne_23 = or(leftOne_26, rightOne_22)
node _T_117 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_118 = and(leftOne_26, rightOne_22)
node rightTwo_11 = or(_T_117, _T_118)
node rightOne_24 = or(leftOne_25, rightOne_23)
node _T_119 = or(leftTwo_10, rightTwo_11)
node _T_120 = and(leftOne_25, rightOne_23)
node rightTwo_12 = or(_T_119, _T_120)
node rightOne_25 = or(leftOne_23, rightOne_24)
node _T_121 = or(leftTwo_9, rightTwo_12)
node _T_122 = and(leftOne_23, rightOne_24)
node rightTwo_13 = or(_T_121, _T_122)
node rightOne_26 = or(leftOne_20, rightOne_25)
node _T_123 = or(leftTwo_8, rightTwo_13)
node _T_124 = and(leftOne_20, rightOne_25)
node rightTwo_14 = or(_T_123, _T_124)
node _T_125 = or(leftOne_13, rightOne_26)
node _T_126 = or(leftTwo_5, rightTwo_14)
node _T_127 = and(leftOne_13, rightOne_26)
node _T_128 = or(_T_126, _T_127)
when _T_128 :
node _isValid_T_4 = not(idxHit)
node _isValid_T_5 = and(isValid, _isValid_T_4)
connect isValid, _isValid_T_5
when io.flush :
connect isValid, UInt<1>(0h0)
cmem table : UInt<1> [512]
regreset history : UInt<8>, clock, reset, UInt<8>(0h0)
regreset reset_waddr : UInt<10>, clock, reset, UInt<10>(0h0)
node _resetting_T = bits(reset_waddr, 9, 9)
node resetting = eq(_resetting_T, UInt<1>(0h0))
wire wen : UInt<1>
connect wen, resetting
wire waddr_1 : UInt
connect waddr_1, reset_waddr
wire wdata : UInt
connect wdata, UInt<1>(0h0)
when resetting :
node _reset_waddr_T = add(reset_waddr, UInt<1>(0h1))
node _reset_waddr_T_1 = tail(_reset_waddr_T, 1)
connect reset_waddr, _reset_waddr_T_1
when wen :
node _T_129 = or(waddr_1, UInt<9>(0h0))
node _T_130 = bits(_T_129, 8, 0)
infer mport MPORT = table[_T_130], clock
connect MPORT, wdata
node _isBranch_T = eq(cfiType[0], UInt<1>(0h0))
node _isBranch_T_1 = eq(cfiType[1], UInt<1>(0h0))
node _isBranch_T_2 = eq(cfiType[2], UInt<1>(0h0))
node _isBranch_T_3 = eq(cfiType[3], UInt<1>(0h0))
node _isBranch_T_4 = eq(cfiType[4], UInt<1>(0h0))
node _isBranch_T_5 = eq(cfiType[5], UInt<1>(0h0))
node _isBranch_T_6 = eq(cfiType[6], UInt<1>(0h0))
node _isBranch_T_7 = eq(cfiType[7], UInt<1>(0h0))
node _isBranch_T_8 = eq(cfiType[8], UInt<1>(0h0))
node _isBranch_T_9 = eq(cfiType[9], UInt<1>(0h0))
node _isBranch_T_10 = eq(cfiType[10], UInt<1>(0h0))
node _isBranch_T_11 = eq(cfiType[11], UInt<1>(0h0))
node _isBranch_T_12 = eq(cfiType[12], UInt<1>(0h0))
node _isBranch_T_13 = eq(cfiType[13], UInt<1>(0h0))
node _isBranch_T_14 = eq(cfiType[14], UInt<1>(0h0))
node _isBranch_T_15 = eq(cfiType[15], UInt<1>(0h0))
node _isBranch_T_16 = eq(cfiType[16], UInt<1>(0h0))
node _isBranch_T_17 = eq(cfiType[17], UInt<1>(0h0))
node _isBranch_T_18 = eq(cfiType[18], UInt<1>(0h0))
node _isBranch_T_19 = eq(cfiType[19], UInt<1>(0h0))
node _isBranch_T_20 = eq(cfiType[20], UInt<1>(0h0))
node _isBranch_T_21 = eq(cfiType[21], UInt<1>(0h0))
node _isBranch_T_22 = eq(cfiType[22], UInt<1>(0h0))
node _isBranch_T_23 = eq(cfiType[23], UInt<1>(0h0))
node _isBranch_T_24 = eq(cfiType[24], UInt<1>(0h0))
node _isBranch_T_25 = eq(cfiType[25], UInt<1>(0h0))
node _isBranch_T_26 = eq(cfiType[26], UInt<1>(0h0))
node _isBranch_T_27 = eq(cfiType[27], UInt<1>(0h0))
node isBranch_lo_lo_lo_hi = cat(_isBranch_T_2, _isBranch_T_1)
node isBranch_lo_lo_lo = cat(isBranch_lo_lo_lo_hi, _isBranch_T)
node isBranch_lo_lo_hi_lo = cat(_isBranch_T_4, _isBranch_T_3)
node isBranch_lo_lo_hi_hi = cat(_isBranch_T_6, _isBranch_T_5)
node isBranch_lo_lo_hi = cat(isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo)
node isBranch_lo_lo = cat(isBranch_lo_lo_hi, isBranch_lo_lo_lo)
node isBranch_lo_hi_lo_hi = cat(_isBranch_T_9, _isBranch_T_8)
node isBranch_lo_hi_lo = cat(isBranch_lo_hi_lo_hi, _isBranch_T_7)
node isBranch_lo_hi_hi_lo = cat(_isBranch_T_11, _isBranch_T_10)
node isBranch_lo_hi_hi_hi = cat(_isBranch_T_13, _isBranch_T_12)
node isBranch_lo_hi_hi = cat(isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo)
node isBranch_lo_hi = cat(isBranch_lo_hi_hi, isBranch_lo_hi_lo)
node isBranch_lo = cat(isBranch_lo_hi, isBranch_lo_lo)
node isBranch_hi_lo_lo_hi = cat(_isBranch_T_16, _isBranch_T_15)
node isBranch_hi_lo_lo = cat(isBranch_hi_lo_lo_hi, _isBranch_T_14)
node isBranch_hi_lo_hi_lo = cat(_isBranch_T_18, _isBranch_T_17)
node isBranch_hi_lo_hi_hi = cat(_isBranch_T_20, _isBranch_T_19)
node isBranch_hi_lo_hi = cat(isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo)
node isBranch_hi_lo = cat(isBranch_hi_lo_hi, isBranch_hi_lo_lo)
node isBranch_hi_hi_lo_hi = cat(_isBranch_T_23, _isBranch_T_22)
node isBranch_hi_hi_lo = cat(isBranch_hi_hi_lo_hi, _isBranch_T_21)
node isBranch_hi_hi_hi_lo = cat(_isBranch_T_25, _isBranch_T_24)
node isBranch_hi_hi_hi_hi = cat(_isBranch_T_27, _isBranch_T_26)
node isBranch_hi_hi_hi = cat(isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo)
node isBranch_hi_hi = cat(isBranch_hi_hi_hi, isBranch_hi_hi_lo)
node isBranch_hi = cat(isBranch_hi_hi, isBranch_hi_lo)
node _isBranch_T_28 = cat(isBranch_hi, isBranch_lo)
node _isBranch_T_29 = and(idxHit, _isBranch_T_28)
node isBranch = orr(_isBranch_T_29)
wire res : { history : UInt<8>, value : UInt<1>}
node res_res_value_hi = shr(io.req.bits.addr, 2)
node _res_res_value_T = bits(res_res_value_hi, 8, 0)
node _res_res_value_T_1 = shr(res_res_value_hi, 9)
node _res_res_value_T_2 = bits(_res_res_value_T_1, 1, 0)
node _res_res_value_T_3 = xor(_res_res_value_T, _res_res_value_T_2)
node _res_res_value_T_4 = mul(UInt<8>(0hdd), history)
node _res_res_value_T_5 = bits(_res_res_value_T_4, 7, 5)
node _res_res_value_T_6 = shl(_res_res_value_T_5, 6)
node _res_res_value_T_7 = xor(_res_res_value_T_3, _res_res_value_T_6)
infer mport res_res_value_MPORT = table[_res_res_value_T_7], clock
node _res_res_value_T_8 = mux(resetting, UInt<1>(0h0), res_res_value_MPORT)
connect res.value, _res_res_value_T_8
connect res.history, history
when io.bht_advance.valid :
node _T_131 = bits(io.bht_advance.bits.bht.value, 0, 0)
node _history_T = shr(history, 1)
node _history_T_1 = cat(_T_131, _history_T)
connect history, _history_T_1
when io.bht_update.valid :
when io.bht_update.bits.branch :
connect wen, UInt<1>(0h1)
node _T_132 = eq(resetting, UInt<1>(0h0))
when _T_132 :
node waddr_hi = shr(io.bht_update.bits.pc, 2)
node _waddr_T_40 = bits(waddr_hi, 8, 0)
node _waddr_T_41 = shr(waddr_hi, 9)
node _waddr_T_42 = bits(_waddr_T_41, 1, 0)
node _waddr_T_43 = xor(_waddr_T_40, _waddr_T_42)
node _waddr_T_44 = mul(UInt<8>(0hdd), io.bht_update.bits.prediction.history)
node _waddr_T_45 = bits(_waddr_T_44, 7, 5)
node _waddr_T_46 = shl(_waddr_T_45, 6)
node _waddr_T_47 = xor(_waddr_T_43, _waddr_T_46)
connect waddr_1, _waddr_T_47
connect wdata, io.bht_update.bits.taken
when io.bht_update.bits.mispredict :
node _history_T_2 = shr(io.bht_update.bits.prediction.history, 1)
node _history_T_3 = cat(io.bht_update.bits.taken, _history_T_2)
connect history, _history_T_3
else :
when io.bht_update.bits.mispredict :
connect history, io.bht_update.bits.prediction.history
node _T_133 = bits(res.value, 0, 0)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = and(_T_134, isBranch)
when _T_135 :
connect io.resp.bits.taken, UInt<1>(0h0)
connect io.resp.bits.bht, res
regreset count : UInt<3>, clock, reset, UInt<3>(0h0)
regreset pos : UInt<3>, clock, reset, UInt<3>(0h0)
reg stack : UInt[6], clock
node _doPeek_T = eq(cfiType[0], UInt<2>(0h3))
node _doPeek_T_1 = eq(cfiType[1], UInt<2>(0h3))
node _doPeek_T_2 = eq(cfiType[2], UInt<2>(0h3))
node _doPeek_T_3 = eq(cfiType[3], UInt<2>(0h3))
node _doPeek_T_4 = eq(cfiType[4], UInt<2>(0h3))
node _doPeek_T_5 = eq(cfiType[5], UInt<2>(0h3))
node _doPeek_T_6 = eq(cfiType[6], UInt<2>(0h3))
node _doPeek_T_7 = eq(cfiType[7], UInt<2>(0h3))
node _doPeek_T_8 = eq(cfiType[8], UInt<2>(0h3))
node _doPeek_T_9 = eq(cfiType[9], UInt<2>(0h3))
node _doPeek_T_10 = eq(cfiType[10], UInt<2>(0h3))
node _doPeek_T_11 = eq(cfiType[11], UInt<2>(0h3))
node _doPeek_T_12 = eq(cfiType[12], UInt<2>(0h3))
node _doPeek_T_13 = eq(cfiType[13], UInt<2>(0h3))
node _doPeek_T_14 = eq(cfiType[14], UInt<2>(0h3))
node _doPeek_T_15 = eq(cfiType[15], UInt<2>(0h3))
node _doPeek_T_16 = eq(cfiType[16], UInt<2>(0h3))
node _doPeek_T_17 = eq(cfiType[17], UInt<2>(0h3))
node _doPeek_T_18 = eq(cfiType[18], UInt<2>(0h3))
node _doPeek_T_19 = eq(cfiType[19], UInt<2>(0h3))
node _doPeek_T_20 = eq(cfiType[20], UInt<2>(0h3))
node _doPeek_T_21 = eq(cfiType[21], UInt<2>(0h3))
node _doPeek_T_22 = eq(cfiType[22], UInt<2>(0h3))
node _doPeek_T_23 = eq(cfiType[23], UInt<2>(0h3))
node _doPeek_T_24 = eq(cfiType[24], UInt<2>(0h3))
node _doPeek_T_25 = eq(cfiType[25], UInt<2>(0h3))
node _doPeek_T_26 = eq(cfiType[26], UInt<2>(0h3))
node _doPeek_T_27 = eq(cfiType[27], UInt<2>(0h3))
node doPeek_lo_lo_lo_hi = cat(_doPeek_T_2, _doPeek_T_1)
node doPeek_lo_lo_lo = cat(doPeek_lo_lo_lo_hi, _doPeek_T)
node doPeek_lo_lo_hi_lo = cat(_doPeek_T_4, _doPeek_T_3)
node doPeek_lo_lo_hi_hi = cat(_doPeek_T_6, _doPeek_T_5)
node doPeek_lo_lo_hi = cat(doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo)
node doPeek_lo_lo = cat(doPeek_lo_lo_hi, doPeek_lo_lo_lo)
node doPeek_lo_hi_lo_hi = cat(_doPeek_T_9, _doPeek_T_8)
node doPeek_lo_hi_lo = cat(doPeek_lo_hi_lo_hi, _doPeek_T_7)
node doPeek_lo_hi_hi_lo = cat(_doPeek_T_11, _doPeek_T_10)
node doPeek_lo_hi_hi_hi = cat(_doPeek_T_13, _doPeek_T_12)
node doPeek_lo_hi_hi = cat(doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo)
node doPeek_lo_hi = cat(doPeek_lo_hi_hi, doPeek_lo_hi_lo)
node doPeek_lo = cat(doPeek_lo_hi, doPeek_lo_lo)
node doPeek_hi_lo_lo_hi = cat(_doPeek_T_16, _doPeek_T_15)
node doPeek_hi_lo_lo = cat(doPeek_hi_lo_lo_hi, _doPeek_T_14)
node doPeek_hi_lo_hi_lo = cat(_doPeek_T_18, _doPeek_T_17)
node doPeek_hi_lo_hi_hi = cat(_doPeek_T_20, _doPeek_T_19)
node doPeek_hi_lo_hi = cat(doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo)
node doPeek_hi_lo = cat(doPeek_hi_lo_hi, doPeek_hi_lo_lo)
node doPeek_hi_hi_lo_hi = cat(_doPeek_T_23, _doPeek_T_22)
node doPeek_hi_hi_lo = cat(doPeek_hi_hi_lo_hi, _doPeek_T_21)
node doPeek_hi_hi_hi_lo = cat(_doPeek_T_25, _doPeek_T_24)
node doPeek_hi_hi_hi_hi = cat(_doPeek_T_27, _doPeek_T_26)
node doPeek_hi_hi_hi = cat(doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo)
node doPeek_hi_hi = cat(doPeek_hi_hi_hi, doPeek_hi_hi_lo)
node doPeek_hi = cat(doPeek_hi_hi, doPeek_hi_lo)
node _doPeek_T_28 = cat(doPeek_hi, doPeek_lo)
node _doPeek_T_29 = and(idxHit, _doPeek_T_28)
node doPeek = orr(_doPeek_T_29)
node _io_ras_head_valid_T = eq(count, UInt<1>(0h0))
node _io_ras_head_valid_T_1 = eq(_io_ras_head_valid_T, UInt<1>(0h0))
connect io.ras_head.valid, _io_ras_head_valid_T_1
connect io.ras_head.bits, stack[pos]
node _T_136 = eq(count, UInt<1>(0h0))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = and(_T_137, doPeek)
when _T_138 :
connect io.resp.bits.target, stack[pos]
when io.ras_update.valid :
node _T_139 = eq(io.ras_update.bits.cfiType, UInt<2>(0h2))
when _T_139 :
node _T_140 = lt(count, UInt<3>(0h6))
when _T_140 :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
node _nextPos_T = lt(pos, UInt<3>(0h5))
node _nextPos_T_1 = or(UInt<1>(0h0), _nextPos_T)
node _nextPos_T_2 = add(pos, UInt<1>(0h1))
node _nextPos_T_3 = tail(_nextPos_T_2, 1)
node nextPos = mux(_nextPos_T_1, _nextPos_T_3, UInt<1>(0h0))
connect stack[nextPos], io.ras_update.bits.returnAddr
connect pos, nextPos
else :
node _T_141 = eq(io.ras_update.bits.cfiType, UInt<2>(0h3))
when _T_141 :
node _T_142 = eq(count, UInt<1>(0h0))
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _count_T_2 = sub(count, UInt<1>(0h1))
node _count_T_3 = tail(_count_T_2, 1)
connect count, _count_T_3
node _pos_T = gt(pos, UInt<1>(0h0))
node _pos_T_1 = or(UInt<1>(0h0), _pos_T)
node _pos_T_2 = sub(pos, UInt<1>(0h1))
node _pos_T_3 = tail(_pos_T_2, 1)
node _pos_T_4 = mux(_pos_T_1, _pos_T_3, UInt<3>(0h5))
connect pos, _pos_T_4 | module BTB( // @[BTB.scala:187:7]
input clock, // @[BTB.scala:187:7]
input reset, // @[BTB.scala:187:7]
input io_req_valid, // @[BTB.scala:188:14]
input [38:0] io_req_bits_addr, // @[BTB.scala:188:14]
output io_resp_valid, // @[BTB.scala:188:14]
output [1:0] io_resp_bits_cfiType, // @[BTB.scala:188:14]
output io_resp_bits_taken, // @[BTB.scala:188:14]
output [1:0] io_resp_bits_mask, // @[BTB.scala:188:14]
output io_resp_bits_bridx, // @[BTB.scala:188:14]
output [38:0] io_resp_bits_target, // @[BTB.scala:188:14]
output [4:0] io_resp_bits_entry, // @[BTB.scala:188:14]
output [7:0] io_resp_bits_bht_history, // @[BTB.scala:188:14]
output io_resp_bits_bht_value, // @[BTB.scala:188:14]
input io_btb_update_valid, // @[BTB.scala:188:14]
input [1:0] io_btb_update_bits_prediction_cfiType, // @[BTB.scala:188:14]
input io_btb_update_bits_prediction_taken, // @[BTB.scala:188:14]
input [1:0] io_btb_update_bits_prediction_mask, // @[BTB.scala:188:14]
input io_btb_update_bits_prediction_bridx, // @[BTB.scala:188:14]
input [38:0] io_btb_update_bits_prediction_target, // @[BTB.scala:188:14]
input [4:0] io_btb_update_bits_prediction_entry, // @[BTB.scala:188:14]
input [7:0] io_btb_update_bits_prediction_bht_history, // @[BTB.scala:188:14]
input io_btb_update_bits_prediction_bht_value, // @[BTB.scala:188:14]
input [38:0] io_btb_update_bits_pc, // @[BTB.scala:188:14]
input [38:0] io_btb_update_bits_target, // @[BTB.scala:188:14]
input io_btb_update_bits_isValid, // @[BTB.scala:188:14]
input [38:0] io_btb_update_bits_br_pc, // @[BTB.scala:188:14]
input [1:0] io_btb_update_bits_cfiType, // @[BTB.scala:188:14]
input io_bht_update_valid, // @[BTB.scala:188:14]
input [7:0] io_bht_update_bits_prediction_history, // @[BTB.scala:188:14]
input io_bht_update_bits_prediction_value, // @[BTB.scala:188:14]
input [38:0] io_bht_update_bits_pc, // @[BTB.scala:188:14]
input io_bht_update_bits_branch, // @[BTB.scala:188:14]
input io_bht_update_bits_taken, // @[BTB.scala:188:14]
input io_bht_update_bits_mispredict, // @[BTB.scala:188:14]
input io_bht_advance_valid, // @[BTB.scala:188:14]
input [1:0] io_bht_advance_bits_cfiType, // @[BTB.scala:188:14]
input io_bht_advance_bits_taken, // @[BTB.scala:188:14]
input [1:0] io_bht_advance_bits_mask, // @[BTB.scala:188:14]
input io_bht_advance_bits_bridx, // @[BTB.scala:188:14]
input [38:0] io_bht_advance_bits_target, // @[BTB.scala:188:14]
input [4:0] io_bht_advance_bits_entry, // @[BTB.scala:188:14]
input [7:0] io_bht_advance_bits_bht_history, // @[BTB.scala:188:14]
input io_bht_advance_bits_bht_value, // @[BTB.scala:188:14]
input io_ras_update_valid, // @[BTB.scala:188:14]
input [1:0] io_ras_update_bits_cfiType, // @[BTB.scala:188:14]
input [38:0] io_ras_update_bits_returnAddr, // @[BTB.scala:188:14]
output io_ras_head_valid, // @[BTB.scala:188:14]
output [38:0] io_ras_head_bits, // @[BTB.scala:188:14]
input io_flush // @[BTB.scala:188:14]
);
wire _table_ext_R0_data; // @[BTB.scala:116:26]
wire io_req_valid_0 = io_req_valid; // @[BTB.scala:187:7]
wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[BTB.scala:187:7]
wire io_btb_update_valid_0 = io_btb_update_valid; // @[BTB.scala:187:7]
wire [1:0] io_btb_update_bits_prediction_cfiType_0 = io_btb_update_bits_prediction_cfiType; // @[BTB.scala:187:7]
wire io_btb_update_bits_prediction_taken_0 = io_btb_update_bits_prediction_taken; // @[BTB.scala:187:7]
wire [1:0] io_btb_update_bits_prediction_mask_0 = io_btb_update_bits_prediction_mask; // @[BTB.scala:187:7]
wire io_btb_update_bits_prediction_bridx_0 = io_btb_update_bits_prediction_bridx; // @[BTB.scala:187:7]
wire [38:0] io_btb_update_bits_prediction_target_0 = io_btb_update_bits_prediction_target; // @[BTB.scala:187:7]
wire [4:0] io_btb_update_bits_prediction_entry_0 = io_btb_update_bits_prediction_entry; // @[BTB.scala:187:7]
wire [7:0] io_btb_update_bits_prediction_bht_history_0 = io_btb_update_bits_prediction_bht_history; // @[BTB.scala:187:7]
wire io_btb_update_bits_prediction_bht_value_0 = io_btb_update_bits_prediction_bht_value; // @[BTB.scala:187:7]
wire [38:0] io_btb_update_bits_pc_0 = io_btb_update_bits_pc; // @[BTB.scala:187:7]
wire [38:0] io_btb_update_bits_target_0 = io_btb_update_bits_target; // @[BTB.scala:187:7]
wire io_btb_update_bits_isValid_0 = io_btb_update_bits_isValid; // @[BTB.scala:187:7]
wire [38:0] io_btb_update_bits_br_pc_0 = io_btb_update_bits_br_pc; // @[BTB.scala:187:7]
wire [1:0] io_btb_update_bits_cfiType_0 = io_btb_update_bits_cfiType; // @[BTB.scala:187:7]
wire io_bht_update_valid_0 = io_bht_update_valid; // @[BTB.scala:187:7]
wire [7:0] io_bht_update_bits_prediction_history_0 = io_bht_update_bits_prediction_history; // @[BTB.scala:187:7]
wire io_bht_update_bits_prediction_value_0 = io_bht_update_bits_prediction_value; // @[BTB.scala:187:7]
wire [38:0] io_bht_update_bits_pc_0 = io_bht_update_bits_pc; // @[BTB.scala:187:7]
wire io_bht_update_bits_branch_0 = io_bht_update_bits_branch; // @[BTB.scala:187:7]
wire io_bht_update_bits_taken_0 = io_bht_update_bits_taken; // @[BTB.scala:187:7]
wire io_bht_update_bits_mispredict_0 = io_bht_update_bits_mispredict; // @[BTB.scala:187:7]
wire io_bht_advance_valid_0 = io_bht_advance_valid; // @[BTB.scala:187:7]
wire [1:0] io_bht_advance_bits_cfiType_0 = io_bht_advance_bits_cfiType; // @[BTB.scala:187:7]
wire io_bht_advance_bits_taken_0 = io_bht_advance_bits_taken; // @[BTB.scala:187:7]
wire [1:0] io_bht_advance_bits_mask_0 = io_bht_advance_bits_mask; // @[BTB.scala:187:7]
wire io_bht_advance_bits_bridx_0 = io_bht_advance_bits_bridx; // @[BTB.scala:187:7]
wire [38:0] io_bht_advance_bits_target_0 = io_bht_advance_bits_target; // @[BTB.scala:187:7]
wire [4:0] io_bht_advance_bits_entry_0 = io_bht_advance_bits_entry; // @[BTB.scala:187:7]
wire [7:0] io_bht_advance_bits_bht_history_0 = io_bht_advance_bits_bht_history; // @[BTB.scala:187:7]
wire io_bht_advance_bits_bht_value_0 = io_bht_advance_bits_bht_value; // @[BTB.scala:187:7]
wire io_ras_update_valid_0 = io_ras_update_valid; // @[BTB.scala:187:7]
wire [1:0] io_ras_update_bits_cfiType_0 = io_ras_update_bits_cfiType; // @[BTB.scala:187:7]
wire [38:0] io_ras_update_bits_returnAddr_0 = io_ras_update_bits_returnAddr; // @[BTB.scala:187:7]
wire io_flush_0 = io_flush; // @[BTB.scala:187:7]
wire io_btb_update_bits_taken = 1'h0; // @[BTB.scala:187:7]
wire r_btb_update_bits_taken = 1'h0; // @[Valid.scala:135:21]
wire _io_resp_valid_T_85; // @[BTB.scala:287:34]
wire [1:0] _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73]
wire [4:0] _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10]
wire [7:0] res_history; // @[BTB.scala:91:19]
wire res_value; // @[BTB.scala:91:19]
wire _io_ras_head_valid_T_1; // @[BTB.scala:327:26]
wire [7:0] io_resp_bits_bht_history_0; // @[BTB.scala:187:7]
wire io_resp_bits_bht_value_0; // @[BTB.scala:187:7]
wire [1:0] io_resp_bits_cfiType_0; // @[BTB.scala:187:7]
wire io_resp_bits_taken_0; // @[BTB.scala:187:7]
wire [1:0] io_resp_bits_mask_0; // @[BTB.scala:187:7]
wire io_resp_bits_bridx_0; // @[BTB.scala:187:7]
wire [38:0] io_resp_bits_target_0; // @[BTB.scala:187:7]
wire [4:0] io_resp_bits_entry_0; // @[BTB.scala:187:7]
wire io_resp_valid_0; // @[BTB.scala:187:7]
wire io_ras_head_valid_0; // @[BTB.scala:187:7]
wire [38:0] io_ras_head_bits_0; // @[BTB.scala:187:7]
reg [12:0] idxs_0; // @[BTB.scala:199:17]
reg [12:0] idxs_1; // @[BTB.scala:199:17]
reg [12:0] idxs_2; // @[BTB.scala:199:17]
reg [12:0] idxs_3; // @[BTB.scala:199:17]
reg [12:0] idxs_4; // @[BTB.scala:199:17]
reg [12:0] idxs_5; // @[BTB.scala:199:17]
reg [12:0] idxs_6; // @[BTB.scala:199:17]
reg [12:0] idxs_7; // @[BTB.scala:199:17]
reg [12:0] idxs_8; // @[BTB.scala:199:17]
reg [12:0] idxs_9; // @[BTB.scala:199:17]
reg [12:0] idxs_10; // @[BTB.scala:199:17]
reg [12:0] idxs_11; // @[BTB.scala:199:17]
reg [12:0] idxs_12; // @[BTB.scala:199:17]
reg [12:0] idxs_13; // @[BTB.scala:199:17]
reg [12:0] idxs_14; // @[BTB.scala:199:17]
reg [12:0] idxs_15; // @[BTB.scala:199:17]
reg [12:0] idxs_16; // @[BTB.scala:199:17]
reg [12:0] idxs_17; // @[BTB.scala:199:17]
reg [12:0] idxs_18; // @[BTB.scala:199:17]
reg [12:0] idxs_19; // @[BTB.scala:199:17]
reg [12:0] idxs_20; // @[BTB.scala:199:17]
reg [12:0] idxs_21; // @[BTB.scala:199:17]
reg [12:0] idxs_22; // @[BTB.scala:199:17]
reg [12:0] idxs_23; // @[BTB.scala:199:17]
reg [12:0] idxs_24; // @[BTB.scala:199:17]
reg [12:0] idxs_25; // @[BTB.scala:199:17]
reg [12:0] idxs_26; // @[BTB.scala:199:17]
reg [12:0] idxs_27; // @[BTB.scala:199:17]
reg [2:0] idxPages_0; // @[BTB.scala:200:21]
reg [2:0] idxPages_1; // @[BTB.scala:200:21]
reg [2:0] idxPages_2; // @[BTB.scala:200:21]
reg [2:0] idxPages_3; // @[BTB.scala:200:21]
reg [2:0] idxPages_4; // @[BTB.scala:200:21]
reg [2:0] idxPages_5; // @[BTB.scala:200:21]
reg [2:0] idxPages_6; // @[BTB.scala:200:21]
reg [2:0] idxPages_7; // @[BTB.scala:200:21]
reg [2:0] idxPages_8; // @[BTB.scala:200:21]
reg [2:0] idxPages_9; // @[BTB.scala:200:21]
reg [2:0] idxPages_10; // @[BTB.scala:200:21]
reg [2:0] idxPages_11; // @[BTB.scala:200:21]
reg [2:0] idxPages_12; // @[BTB.scala:200:21]
reg [2:0] idxPages_13; // @[BTB.scala:200:21]
reg [2:0] idxPages_14; // @[BTB.scala:200:21]
reg [2:0] idxPages_15; // @[BTB.scala:200:21]
reg [2:0] idxPages_16; // @[BTB.scala:200:21]
reg [2:0] idxPages_17; // @[BTB.scala:200:21]
reg [2:0] idxPages_18; // @[BTB.scala:200:21]
reg [2:0] idxPages_19; // @[BTB.scala:200:21]
reg [2:0] idxPages_20; // @[BTB.scala:200:21]
reg [2:0] idxPages_21; // @[BTB.scala:200:21]
reg [2:0] idxPages_22; // @[BTB.scala:200:21]
reg [2:0] idxPages_23; // @[BTB.scala:200:21]
reg [2:0] idxPages_24; // @[BTB.scala:200:21]
reg [2:0] idxPages_25; // @[BTB.scala:200:21]
reg [2:0] idxPages_26; // @[BTB.scala:200:21]
reg [2:0] idxPages_27; // @[BTB.scala:200:21]
reg [12:0] tgts_0; // @[BTB.scala:201:17]
reg [12:0] tgts_1; // @[BTB.scala:201:17]
reg [12:0] tgts_2; // @[BTB.scala:201:17]
reg [12:0] tgts_3; // @[BTB.scala:201:17]
reg [12:0] tgts_4; // @[BTB.scala:201:17]
reg [12:0] tgts_5; // @[BTB.scala:201:17]
reg [12:0] tgts_6; // @[BTB.scala:201:17]
reg [12:0] tgts_7; // @[BTB.scala:201:17]
reg [12:0] tgts_8; // @[BTB.scala:201:17]
reg [12:0] tgts_9; // @[BTB.scala:201:17]
reg [12:0] tgts_10; // @[BTB.scala:201:17]
reg [12:0] tgts_11; // @[BTB.scala:201:17]
reg [12:0] tgts_12; // @[BTB.scala:201:17]
reg [12:0] tgts_13; // @[BTB.scala:201:17]
reg [12:0] tgts_14; // @[BTB.scala:201:17]
reg [12:0] tgts_15; // @[BTB.scala:201:17]
reg [12:0] tgts_16; // @[BTB.scala:201:17]
reg [12:0] tgts_17; // @[BTB.scala:201:17]
reg [12:0] tgts_18; // @[BTB.scala:201:17]
reg [12:0] tgts_19; // @[BTB.scala:201:17]
reg [12:0] tgts_20; // @[BTB.scala:201:17]
reg [12:0] tgts_21; // @[BTB.scala:201:17]
reg [12:0] tgts_22; // @[BTB.scala:201:17]
reg [12:0] tgts_23; // @[BTB.scala:201:17]
reg [12:0] tgts_24; // @[BTB.scala:201:17]
reg [12:0] tgts_25; // @[BTB.scala:201:17]
reg [12:0] tgts_26; // @[BTB.scala:201:17]
reg [12:0] tgts_27; // @[BTB.scala:201:17]
reg [2:0] tgtPages_0; // @[BTB.scala:202:21]
reg [2:0] tgtPages_1; // @[BTB.scala:202:21]
reg [2:0] tgtPages_2; // @[BTB.scala:202:21]
reg [2:0] tgtPages_3; // @[BTB.scala:202:21]
reg [2:0] tgtPages_4; // @[BTB.scala:202:21]
reg [2:0] tgtPages_5; // @[BTB.scala:202:21]
reg [2:0] tgtPages_6; // @[BTB.scala:202:21]
reg [2:0] tgtPages_7; // @[BTB.scala:202:21]
reg [2:0] tgtPages_8; // @[BTB.scala:202:21]
reg [2:0] tgtPages_9; // @[BTB.scala:202:21]
reg [2:0] tgtPages_10; // @[BTB.scala:202:21]
reg [2:0] tgtPages_11; // @[BTB.scala:202:21]
reg [2:0] tgtPages_12; // @[BTB.scala:202:21]
reg [2:0] tgtPages_13; // @[BTB.scala:202:21]
reg [2:0] tgtPages_14; // @[BTB.scala:202:21]
reg [2:0] tgtPages_15; // @[BTB.scala:202:21]
reg [2:0] tgtPages_16; // @[BTB.scala:202:21]
reg [2:0] tgtPages_17; // @[BTB.scala:202:21]
reg [2:0] tgtPages_18; // @[BTB.scala:202:21]
reg [2:0] tgtPages_19; // @[BTB.scala:202:21]
reg [2:0] tgtPages_20; // @[BTB.scala:202:21]
reg [2:0] tgtPages_21; // @[BTB.scala:202:21]
reg [2:0] tgtPages_22; // @[BTB.scala:202:21]
reg [2:0] tgtPages_23; // @[BTB.scala:202:21]
reg [2:0] tgtPages_24; // @[BTB.scala:202:21]
reg [2:0] tgtPages_25; // @[BTB.scala:202:21]
reg [2:0] tgtPages_26; // @[BTB.scala:202:21]
reg [2:0] tgtPages_27; // @[BTB.scala:202:21]
reg [24:0] pages_0; // @[BTB.scala:203:18]
reg [24:0] pages_1; // @[BTB.scala:203:18]
reg [24:0] pages_2; // @[BTB.scala:203:18]
reg [24:0] pages_3; // @[BTB.scala:203:18]
reg [24:0] pages_4; // @[BTB.scala:203:18]
reg [24:0] pages_5; // @[BTB.scala:203:18]
reg [5:0] pageValid; // @[BTB.scala:204:26]
wire _pagesMasked_T = pageValid[0]; // @[BTB.scala:204:26, :205:32]
wire _pagesMasked_T_1 = pageValid[1]; // @[BTB.scala:204:26, :205:32]
wire _pagesMasked_T_2 = pageValid[2]; // @[BTB.scala:204:26, :205:32]
wire _pagesMasked_T_3 = pageValid[3]; // @[BTB.scala:204:26, :205:32]
wire _pagesMasked_T_4 = pageValid[4]; // @[BTB.scala:204:26, :205:32]
wire _pagesMasked_T_5 = pageValid[5]; // @[BTB.scala:204:26, :205:32]
wire [24:0] pagesMasked_0 = _pagesMasked_T ? pages_0 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
wire [24:0] pagesMasked_1 = _pagesMasked_T_1 ? pages_1 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
wire [24:0] pagesMasked_2 = _pagesMasked_T_2 ? pages_2 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
wire [24:0] pagesMasked_3 = _pagesMasked_T_3 ? pages_3 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
wire [24:0] pagesMasked_4 = _pagesMasked_T_4 ? pages_4 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
wire [24:0] pagesMasked_5 = _pagesMasked_T_5 ? pages_5 : 25'h0; // @[BTB.scala:203:18, :205:{32,75}]
reg [27:0] isValid; // @[BTB.scala:207:24]
reg [1:0] cfiType_0; // @[BTB.scala:208:20]
reg [1:0] cfiType_1; // @[BTB.scala:208:20]
reg [1:0] cfiType_2; // @[BTB.scala:208:20]
reg [1:0] cfiType_3; // @[BTB.scala:208:20]
reg [1:0] cfiType_4; // @[BTB.scala:208:20]
reg [1:0] cfiType_5; // @[BTB.scala:208:20]
reg [1:0] cfiType_6; // @[BTB.scala:208:20]
reg [1:0] cfiType_7; // @[BTB.scala:208:20]
reg [1:0] cfiType_8; // @[BTB.scala:208:20]
reg [1:0] cfiType_9; // @[BTB.scala:208:20]
reg [1:0] cfiType_10; // @[BTB.scala:208:20]
reg [1:0] cfiType_11; // @[BTB.scala:208:20]
reg [1:0] cfiType_12; // @[BTB.scala:208:20]
reg [1:0] cfiType_13; // @[BTB.scala:208:20]
reg [1:0] cfiType_14; // @[BTB.scala:208:20]
reg [1:0] cfiType_15; // @[BTB.scala:208:20]
reg [1:0] cfiType_16; // @[BTB.scala:208:20]
reg [1:0] cfiType_17; // @[BTB.scala:208:20]
reg [1:0] cfiType_18; // @[BTB.scala:208:20]
reg [1:0] cfiType_19; // @[BTB.scala:208:20]
reg [1:0] cfiType_20; // @[BTB.scala:208:20]
reg [1:0] cfiType_21; // @[BTB.scala:208:20]
reg [1:0] cfiType_22; // @[BTB.scala:208:20]
reg [1:0] cfiType_23; // @[BTB.scala:208:20]
reg [1:0] cfiType_24; // @[BTB.scala:208:20]
reg [1:0] cfiType_25; // @[BTB.scala:208:20]
reg [1:0] cfiType_26; // @[BTB.scala:208:20]
reg [1:0] cfiType_27; // @[BTB.scala:208:20]
reg brIdx_0; // @[BTB.scala:209:18]
reg brIdx_1; // @[BTB.scala:209:18]
reg brIdx_2; // @[BTB.scala:209:18]
reg brIdx_3; // @[BTB.scala:209:18]
reg brIdx_4; // @[BTB.scala:209:18]
reg brIdx_5; // @[BTB.scala:209:18]
reg brIdx_6; // @[BTB.scala:209:18]
reg brIdx_7; // @[BTB.scala:209:18]
reg brIdx_8; // @[BTB.scala:209:18]
reg brIdx_9; // @[BTB.scala:209:18]
reg brIdx_10; // @[BTB.scala:209:18]
reg brIdx_11; // @[BTB.scala:209:18]
reg brIdx_12; // @[BTB.scala:209:18]
reg brIdx_13; // @[BTB.scala:209:18]
reg brIdx_14; // @[BTB.scala:209:18]
reg brIdx_15; // @[BTB.scala:209:18]
reg brIdx_16; // @[BTB.scala:209:18]
reg brIdx_17; // @[BTB.scala:209:18]
reg brIdx_18; // @[BTB.scala:209:18]
reg brIdx_19; // @[BTB.scala:209:18]
reg brIdx_20; // @[BTB.scala:209:18]
reg brIdx_21; // @[BTB.scala:209:18]
reg brIdx_22; // @[BTB.scala:209:18]
reg brIdx_23; // @[BTB.scala:209:18]
reg brIdx_24; // @[BTB.scala:209:18]
reg brIdx_25; // @[BTB.scala:209:18]
reg brIdx_26; // @[BTB.scala:209:18]
reg brIdx_27; // @[BTB.scala:209:18]
reg r_btb_update_pipe_v; // @[Valid.scala:141:24]
wire r_btb_update_valid = r_btb_update_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [1:0] r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:142:26]
wire [1:0] r_btb_update_bits_prediction_cfiType = r_btb_update_pipe_b_prediction_cfiType; // @[Valid.scala:135:21, :142:26]
reg r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:142:26]
wire r_btb_update_bits_prediction_taken = r_btb_update_pipe_b_prediction_taken; // @[Valid.scala:135:21, :142:26]
reg [1:0] r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:142:26]
wire [1:0] r_btb_update_bits_prediction_mask = r_btb_update_pipe_b_prediction_mask; // @[Valid.scala:135:21, :142:26]
reg r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:142:26]
wire r_btb_update_bits_prediction_bridx = r_btb_update_pipe_b_prediction_bridx; // @[Valid.scala:135:21, :142:26]
reg [38:0] r_btb_update_pipe_b_prediction_target; // @[Valid.scala:142:26]
wire [38:0] r_btb_update_bits_prediction_target = r_btb_update_pipe_b_prediction_target; // @[Valid.scala:135:21, :142:26]
reg [4:0] r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:142:26]
wire [4:0] r_btb_update_bits_prediction_entry = r_btb_update_pipe_b_prediction_entry; // @[Valid.scala:135:21, :142:26]
reg [7:0] r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:142:26]
wire [7:0] r_btb_update_bits_prediction_bht_history = r_btb_update_pipe_b_prediction_bht_history; // @[Valid.scala:135:21, :142:26]
reg r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:142:26]
wire r_btb_update_bits_prediction_bht_value = r_btb_update_pipe_b_prediction_bht_value; // @[Valid.scala:135:21, :142:26]
reg [38:0] r_btb_update_pipe_b_pc; // @[Valid.scala:142:26]
wire [38:0] r_btb_update_bits_pc = r_btb_update_pipe_b_pc; // @[Valid.scala:135:21, :142:26]
reg [38:0] r_btb_update_pipe_b_target; // @[Valid.scala:142:26]
wire [38:0] r_btb_update_bits_target = r_btb_update_pipe_b_target; // @[Valid.scala:135:21, :142:26]
reg r_btb_update_pipe_b_isValid; // @[Valid.scala:142:26]
wire r_btb_update_bits_isValid = r_btb_update_pipe_b_isValid; // @[Valid.scala:135:21, :142:26]
reg [38:0] r_btb_update_pipe_b_br_pc; // @[Valid.scala:142:26]
wire [38:0] r_btb_update_bits_br_pc = r_btb_update_pipe_b_br_pc; // @[Valid.scala:135:21, :142:26]
reg [1:0] r_btb_update_pipe_b_cfiType; // @[Valid.scala:142:26]
wire [1:0] r_btb_update_bits_cfiType = r_btb_update_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26]
wire [24:0] pageHit_p = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39]
wire [24:0] _samePage_T_1 = io_req_bits_addr_0[38:14]; // @[BTB.scala:187:7, :211:39]
wire _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire [1:0] pageHit_lo_hi = {_pageHit_T_2, _pageHit_T_1}; // @[package.scala:45:27]
wire [2:0] pageHit_lo = {pageHit_lo_hi, _pageHit_T}; // @[package.scala:45:27]
wire [1:0] pageHit_hi_hi = {_pageHit_T_5, _pageHit_T_4}; // @[package.scala:45:27]
wire [2:0] pageHit_hi = {pageHit_hi_hi, _pageHit_T_3}; // @[package.scala:45:27]
wire [5:0] _pageHit_T_6 = {pageHit_hi, pageHit_lo}; // @[package.scala:45:27]
wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[package.scala:45:27]
wire [12:0] idxHit_idx = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19]
wire [12:0] _tgts_T = io_req_bits_addr_0[13:1]; // @[BTB.scala:187:7, :217:19, :265:33]
wire _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala:199:17, :217:19, :218:16]
wire [1:0] idxHit_lo_lo_lo_hi = {_idxHit_T_2, _idxHit_T_1}; // @[package.scala:45:27]
wire [2:0] idxHit_lo_lo_lo = {idxHit_lo_lo_lo_hi, _idxHit_T}; // @[package.scala:45:27]
wire [1:0] idxHit_lo_lo_hi_lo = {_idxHit_T_4, _idxHit_T_3}; // @[package.scala:45:27]
wire [1:0] idxHit_lo_lo_hi_hi = {_idxHit_T_6, _idxHit_T_5}; // @[package.scala:45:27]
wire [3:0] idxHit_lo_lo_hi = {idxHit_lo_lo_hi_hi, idxHit_lo_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] idxHit_lo_lo = {idxHit_lo_lo_hi, idxHit_lo_lo_lo}; // @[package.scala:45:27]
wire [1:0] idxHit_lo_hi_lo_hi = {_idxHit_T_9, _idxHit_T_8}; // @[package.scala:45:27]
wire [2:0] idxHit_lo_hi_lo = {idxHit_lo_hi_lo_hi, _idxHit_T_7}; // @[package.scala:45:27]
wire [1:0] idxHit_lo_hi_hi_lo = {_idxHit_T_11, _idxHit_T_10}; // @[package.scala:45:27]
wire [1:0] idxHit_lo_hi_hi_hi = {_idxHit_T_13, _idxHit_T_12}; // @[package.scala:45:27]
wire [3:0] idxHit_lo_hi_hi = {idxHit_lo_hi_hi_hi, idxHit_lo_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] idxHit_lo_hi = {idxHit_lo_hi_hi, idxHit_lo_hi_lo}; // @[package.scala:45:27]
wire [13:0] idxHit_lo = {idxHit_lo_hi, idxHit_lo_lo}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_lo_lo_hi = {_idxHit_T_16, _idxHit_T_15}; // @[package.scala:45:27]
wire [2:0] idxHit_hi_lo_lo = {idxHit_hi_lo_lo_hi, _idxHit_T_14}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_lo_hi_lo = {_idxHit_T_18, _idxHit_T_17}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_lo_hi_hi = {_idxHit_T_20, _idxHit_T_19}; // @[package.scala:45:27]
wire [3:0] idxHit_hi_lo_hi = {idxHit_hi_lo_hi_hi, idxHit_hi_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] idxHit_hi_lo = {idxHit_hi_lo_hi, idxHit_hi_lo_lo}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_hi_lo_hi = {_idxHit_T_23, _idxHit_T_22}; // @[package.scala:45:27]
wire [2:0] idxHit_hi_hi_lo = {idxHit_hi_hi_lo_hi, _idxHit_T_21}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_hi_hi_lo = {_idxHit_T_25, _idxHit_T_24}; // @[package.scala:45:27]
wire [1:0] idxHit_hi_hi_hi_hi = {_idxHit_T_27, _idxHit_T_26}; // @[package.scala:45:27]
wire [3:0] idxHit_hi_hi_hi = {idxHit_hi_hi_hi_hi, idxHit_hi_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] idxHit_hi_hi = {idxHit_hi_hi_hi, idxHit_hi_hi_lo}; // @[package.scala:45:27]
wire [13:0] idxHit_hi = {idxHit_hi_hi, idxHit_hi_lo}; // @[package.scala:45:27]
wire [27:0] _idxHit_T_28 = {idxHit_hi, idxHit_lo}; // @[package.scala:45:27]
wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[package.scala:45:27]
wire [24:0] updatePageHit_p = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21]
wire [24:0] _samePage_T = r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21]
wire _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala:203:18, :211:39, :214:29]
wire [1:0] updatePageHit_lo_hi = {_updatePageHit_T_2, _updatePageHit_T_1}; // @[package.scala:45:27]
wire [2:0] updatePageHit_lo = {updatePageHit_lo_hi, _updatePageHit_T}; // @[package.scala:45:27]
wire [1:0] updatePageHit_hi_hi = {_updatePageHit_T_5, _updatePageHit_T_4}; // @[package.scala:45:27]
wire [2:0] updatePageHit_hi = {updatePageHit_hi_hi, _updatePageHit_T_3}; // @[package.scala:45:27]
wire [5:0] _updatePageHit_T_6 = {updatePageHit_hi, updatePageHit_lo}; // @[package.scala:45:27]
wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[package.scala:45:27]
wire updateHit = r_btb_update_bits_prediction_entry[4:2] != 3'h7; // @[Valid.scala:135:21]
wire useUpdatePageHit = |updatePageHit; // @[BTB.scala:214:15, :234:40]
wire usePageHit = |pageHit; // @[BTB.scala:214:15, :235:28]
wire doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala:234:40, :236:23]
reg [2:0] nextPageRepl; // @[BTB.scala:237:29]
wire [4:0] _idxPageRepl_T = pageHit[4:0]; // @[BTB.scala:214:15, :238:32]
wire _idxPageRepl_T_1 = pageHit[5]; // @[BTB.scala:214:15, :238:53]
wire [5:0] _idxPageRepl_T_2 = {_idxPageRepl_T, _idxPageRepl_T_1}; // @[BTB.scala:238:{24,32,53}]
wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala:58:35]
wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[OneHot.scala:58:35]
wire [7:0] idxPageRepl = {2'h0, _idxPageRepl_T_2} | _idxPageRepl_T_4; // @[BTB.scala:238:{24,65,70}]
wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {2'h0, updatePageHit} : idxPageRepl; // @[BTB.scala:214:15, :234:40, :238:65, :239:28]
wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala:30:18]
wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala:31:18]
wire _idxPageUpdate_T = |idxPageUpdate_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi | idxPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _idxPageUpdate_T_2 = |idxPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 | idxPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _idxPageUpdate_T_4 = _idxPageUpdate_T_3[1]; // @[OneHot.scala:32:28]
wire [1:0] _idxPageUpdate_T_5 = {_idxPageUpdate_T_2, _idxPageUpdate_T_4}; // @[OneHot.scala:32:{10,14}]
wire [2:0] idxPageUpdate = {_idxPageUpdate_T, _idxPageUpdate_T_5}; // @[OneHot.scala:32:{10,14}]
wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala:236:23, :238:65, :241:26]
wire samePage = _samePage_T == _samePage_T_1; // @[BTB.scala:211:39, :243:45]
wire _doTgtPageRepl_T = ~samePage; // @[BTB.scala:243:45, :244:23]
wire _doTgtPageRepl_T_1 = ~usePageHit; // @[BTB.scala:235:28, :244:36]
wire doTgtPageRepl = _doTgtPageRepl_T & _doTgtPageRepl_T_1; // @[BTB.scala:244:{23,33,36}]
wire [4:0] _tgtPageRepl_T = idxPageUpdateOH[4:0]; // @[BTB.scala:239:28, :245:71]
wire _tgtPageRepl_T_1 = idxPageUpdateOH[5]; // @[BTB.scala:239:28, :245:100]
wire [5:0] _tgtPageRepl_T_2 = {_tgtPageRepl_T, _tgtPageRepl_T_1}; // @[BTB.scala:245:{55,71,100}]
wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {2'h0, _tgtPageRepl_T_2}; // @[BTB.scala:239:28, :243:45, :245:{24,55}]
wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala:235:28, :245:24, :246:45]
wire [7:0] _tgtPageUpdate_T_1 = {2'h0, pageHit} | _tgtPageUpdate_T; // @[BTB.scala:214:15, :246:{40,45}]
wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala:30:18]
wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala:31:18]
wire _tgtPageUpdate_T_2 = |tgtPageUpdate_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi | tgtPageUpdate_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _tgtPageUpdate_T_4 = |tgtPageUpdate_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 | tgtPageUpdate_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _tgtPageUpdate_T_6 = _tgtPageUpdate_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _tgtPageUpdate_T_7 = {_tgtPageUpdate_T_4, _tgtPageUpdate_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2, _tgtPageUpdate_T_7}; // @[OneHot.scala:32:{10,14}]
wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala:244:33, :245:24, :247:26]
wire both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala:236:23, :244:33, :250:30]
wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala:250:30, :251:40, :292:33]
wire [3:0] _next_T_1 = {1'h0, nextPageRepl} + {2'h0, _next_T}; // @[BTB.scala:237:29, :251:{29,40}]
wire [2:0] next = _next_T_1[2:0]; // @[BTB.scala:251:29]
wire _nextPageRepl_T = next > 3'h5; // @[BTB.scala:251:29, :252:30]
wire _nextPageRepl_T_1 = next[0]; // @[BTB.scala:251:29, :252:47]
wire [2:0] _nextPageRepl_T_2 = _nextPageRepl_T ? {2'h0, _nextPageRepl_T_1} : next; // @[BTB.scala:251:29, :252:{24,30,47}]
reg [26:0] state_reg; // @[Replacement.scala:168:70]
wire waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala:168:70, :243:38]
wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13]
wire [10:0] state_reg_left_subtree_state = state_reg[25:15]; // @[package.scala:163:13]
wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :245:38]
wire [14:0] state_reg_right_subtree_state = state_reg[14:0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[package.scala:163:13]
wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala:163:13]
wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[package.scala:163:13]
wire waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[package.scala:163:13]
wire waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala:163:13]
wire _waddr_T = waddr_left_subtree_state_2; // @[package.scala:163:13]
wire waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[package.scala:163:13]
wire _waddr_T_1 = waddr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_2 = waddr_left_subtree_older_2 ? _waddr_T : _waddr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2, _waddr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala:243:38, :245:38]
wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala:163:13]
wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala:245:38]
wire waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[package.scala:163:13]
wire waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala:163:13]
wire _waddr_T_4 = waddr_left_subtree_state_4; // @[package.scala:163:13]
wire waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _waddr_T_5 = waddr_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_6 = waddr_left_subtree_older_4 ? _waddr_T_4 : _waddr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4, _waddr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38]
wire waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala:163:13]
wire _waddr_T_8 = waddr_left_subtree_state_5; // @[package.scala:163:13]
wire waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala:245:38]
wire _waddr_T_9 = waddr_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_10 = waddr_left_subtree_older_5 ? _waddr_T_8 : _waddr_T_9; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5, _waddr_T_10}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3, _waddr_T_12}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {1'h0, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1, _waddr_T_14}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala:243:38, :245:38]
wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala:163:13]
wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala:245:38]
wire waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[package.scala:163:13]
wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala:163:13]
wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[package.scala:163:13]
wire waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[package.scala:163:13]
wire waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala:163:13]
wire _waddr_T_16 = waddr_left_subtree_state_8; // @[package.scala:163:13]
wire waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[package.scala:163:13]
wire _waddr_T_17 = waddr_right_subtree_state_8; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_18 = waddr_left_subtree_older_8 ? _waddr_T_16 : _waddr_T_17; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8, _waddr_T_18}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala:243:38, :245:38]
wire waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala:163:13]
wire _waddr_T_20 = waddr_left_subtree_state_9; // @[package.scala:163:13]
wire waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala:245:38]
wire _waddr_T_21 = waddr_right_subtree_state_9; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_22 = waddr_left_subtree_older_9 ? _waddr_T_20 : _waddr_T_21; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9, _waddr_T_22}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7, _waddr_T_24}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala:243:38, :245:38]
wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala:163:13]
wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala:245:38]
wire waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[package.scala:163:13]
wire waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala:163:13]
wire _waddr_T_26 = waddr_left_subtree_state_11; // @[package.scala:163:13]
wire waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[package.scala:163:13]
wire _waddr_T_27 = waddr_right_subtree_state_11; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_28 = waddr_left_subtree_older_11 ? _waddr_T_26 : _waddr_T_27; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11, _waddr_T_28}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala:243:38, :245:38]
wire waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala:163:13]
wire _waddr_T_30 = waddr_left_subtree_state_12; // @[package.scala:163:13]
wire waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala:245:38]
wire _waddr_T_31 = waddr_right_subtree_state_12; // @[Replacement.scala:245:38, :262:12]
wire _waddr_T_32 = waddr_left_subtree_older_12 ? _waddr_T_30 : _waddr_T_31; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12, _waddr_T_32}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10, _waddr_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6, _waddr_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [4:0] _waddr_T_39 = {waddr_left_subtree_older, _waddr_T_38}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [4:0] waddr = updateHit ? r_btb_update_bits_prediction_entry : _waddr_T_39; // @[Valid.scala:135:21]
reg r_resp_pipe_v; // @[Valid.scala:141:24]
wire r_resp_valid = r_resp_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [1:0] r_resp_pipe_b_cfiType; // @[Valid.scala:142:26]
wire [1:0] r_resp_bits_cfiType = r_resp_pipe_b_cfiType; // @[Valid.scala:135:21, :142:26]
reg r_resp_pipe_b_taken; // @[Valid.scala:142:26]
wire r_resp_bits_taken = r_resp_pipe_b_taken; // @[Valid.scala:135:21, :142:26]
reg [1:0] r_resp_pipe_b_mask; // @[Valid.scala:142:26]
wire [1:0] r_resp_bits_mask = r_resp_pipe_b_mask; // @[Valid.scala:135:21, :142:26]
reg r_resp_pipe_b_bridx; // @[Valid.scala:142:26]
wire r_resp_bits_bridx = r_resp_pipe_b_bridx; // @[Valid.scala:135:21, :142:26]
reg [38:0] r_resp_pipe_b_target; // @[Valid.scala:142:26]
wire [38:0] r_resp_bits_target = r_resp_pipe_b_target; // @[Valid.scala:135:21, :142:26]
reg [4:0] r_resp_pipe_b_entry; // @[Valid.scala:142:26]
wire [4:0] r_resp_bits_entry = r_resp_pipe_b_entry; // @[Valid.scala:135:21, :142:26]
reg [7:0] r_resp_pipe_b_bht_history; // @[Valid.scala:142:26]
wire [7:0] r_resp_bits_bht_history = r_resp_pipe_b_bht_history; // @[Valid.scala:135:21, :142:26]
reg r_resp_pipe_b_bht_value; // @[Valid.scala:142:26]
wire r_resp_bits_bht_value = r_resp_pipe_b_bht_value; // @[Valid.scala:135:21, :142:26]
wire [4:0] state_reg_touch_way_sized = r_btb_update_valid ? waddr : r_resp_bits_entry; // @[Valid.scala:135:21]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[4]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [3:0] _state_reg_T = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13]
wire [3:0] _state_reg_T_39 = state_reg_touch_way_sized[3:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[3]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_reg_left_subtree_state_1 = state_reg_left_subtree_state[9:7]; // @[package.scala:163:13]
wire [6:0] state_reg_right_subtree_state_1 = state_reg_left_subtree_state[6:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_1 = _state_reg_T[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_2 = _state_reg_T_1[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_2 = state_reg_left_subtree_state_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = state_reg_left_subtree_state_1[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1[0]; // @[package.scala:163:13]
wire _state_reg_T_6 = _state_reg_T_1[0]; // @[package.scala:163:13]
wire _state_reg_T_3 = _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_4 = ~_state_reg_T_3; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_5 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_4; // @[package.scala:163:13]
wire _state_reg_T_7 = _state_reg_T_6; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_8 = ~_state_reg_T_7; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_8 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_2, _state_reg_T_5}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_10 = {state_reg_hi, _state_reg_T_9}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_10; // @[package.scala:163:13]
wire [2:0] _state_reg_T_12 = _state_reg_T[2:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_3 = _state_reg_T_12[2]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_reg_left_subtree_state_3 = state_reg_right_subtree_state_1[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_right_subtree_state_3 = state_reg_right_subtree_state_1[2:0]; // @[Replacement.scala:198:38]
wire [1:0] _state_reg_T_13 = _state_reg_T_12[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_24 = _state_reg_T_12[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_4 = _state_reg_T_13[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13]
wire _state_reg_T_14 = _state_reg_T_13[0]; // @[package.scala:163:13]
wire _state_reg_T_18 = _state_reg_T_13[0]; // @[package.scala:163:13]
wire _state_reg_T_15 = _state_reg_T_14; // @[package.scala:163:13]
wire _state_reg_T_16 = ~_state_reg_T_15; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_17 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_16; // @[package.scala:163:13]
wire _state_reg_T_19 = _state_reg_T_18; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_20 = ~_state_reg_T_19; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_20 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_4, _state_reg_T_17}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_22 = {state_reg_hi_1, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_22; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_5 = _state_reg_T_24[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_25 = _state_reg_T_24[0]; // @[package.scala:163:13]
wire _state_reg_T_29 = _state_reg_T_24[0]; // @[package.scala:163:13]
wire _state_reg_T_26 = _state_reg_T_25; // @[package.scala:163:13]
wire _state_reg_T_27 = ~_state_reg_T_26; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_28 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_27; // @[package.scala:163:13]
wire _state_reg_T_30 = _state_reg_T_29; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_31 = ~_state_reg_T_30; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_32 = state_reg_set_left_older_5 ? _state_reg_T_31 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_2 = {state_reg_set_left_older_5, _state_reg_T_28}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_33 = {state_reg_hi_2, _state_reg_T_32}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_23}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_35 = {state_reg_hi_3, _state_reg_T_34}; // @[Replacement.scala:202:12, :206:16]
wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_4 = {state_reg_set_left_older_1, _state_reg_T_11}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [10:0] _state_reg_T_37 = {state_reg_hi_4, _state_reg_T_36}; // @[Replacement.scala:202:12, :206:16]
wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_37; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_6 = _state_reg_T_39[3]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}]
wire [6:0] state_reg_left_subtree_state_6 = state_reg_right_subtree_state[13:7]; // @[package.scala:163:13]
wire [6:0] state_reg_right_subtree_state_6 = state_reg_right_subtree_state[6:0]; // @[Replacement.scala:198:38]
wire [2:0] _state_reg_T_40 = _state_reg_T_39[2:0]; // @[package.scala:163:13]
wire [2:0] _state_reg_T_65 = _state_reg_T_39[2:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_7 = _state_reg_T_40[2]; // @[package.scala:163:13]
wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[2:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_41 = _state_reg_T_40[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_52 = _state_reg_T_40[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_8 = _state_reg_T_41[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_8 = state_reg_left_subtree_state_7[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_8 = state_reg_left_subtree_state_7[0]; // @[package.scala:163:13]
wire _state_reg_T_42 = _state_reg_T_41[0]; // @[package.scala:163:13]
wire _state_reg_T_46 = _state_reg_T_41[0]; // @[package.scala:163:13]
wire _state_reg_T_43 = _state_reg_T_42; // @[package.scala:163:13]
wire _state_reg_T_44 = ~_state_reg_T_43; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_45 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_44; // @[package.scala:163:13]
wire _state_reg_T_47 = _state_reg_T_46; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_48 = ~_state_reg_T_47; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_49 = state_reg_set_left_older_8 ? _state_reg_T_48 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_5 = {state_reg_set_left_older_8, _state_reg_T_45}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_50 = {state_reg_hi_5, _state_reg_T_49}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_51 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_50; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_9 = _state_reg_T_52[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_9 = ~_state_reg_set_left_older_T_9; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_9 = state_reg_right_subtree_state_7[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_9 = state_reg_right_subtree_state_7[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_53 = _state_reg_T_52[0]; // @[package.scala:163:13]
wire _state_reg_T_57 = _state_reg_T_52[0]; // @[package.scala:163:13]
wire _state_reg_T_54 = _state_reg_T_53; // @[package.scala:163:13]
wire _state_reg_T_55 = ~_state_reg_T_54; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_56 = state_reg_set_left_older_9 ? state_reg_left_subtree_state_9 : _state_reg_T_55; // @[package.scala:163:13]
wire _state_reg_T_58 = _state_reg_T_57; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_59 = ~_state_reg_T_58; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_60 = state_reg_set_left_older_9 ? _state_reg_T_59 : state_reg_right_subtree_state_9; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_9, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_61 = {state_reg_hi_6, _state_reg_T_60}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_62 = state_reg_set_left_older_7 ? _state_reg_T_61 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_7 = {state_reg_set_left_older_7, _state_reg_T_51}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_63 = {state_reg_hi_7, _state_reg_T_62}; // @[Replacement.scala:202:12, :206:16]
wire [6:0] _state_reg_T_64 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_63; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_10 = _state_reg_T_65[2]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_10 = ~_state_reg_set_left_older_T_10; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_reg_left_subtree_state_10 = state_reg_right_subtree_state_6[5:3]; // @[package.scala:163:13]
wire [2:0] state_reg_right_subtree_state_10 = state_reg_right_subtree_state_6[2:0]; // @[Replacement.scala:198:38]
wire [1:0] _state_reg_T_66 = _state_reg_T_65[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_77 = _state_reg_T_65[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_11 = _state_reg_T_66[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_11 = ~_state_reg_set_left_older_T_11; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_11 = state_reg_left_subtree_state_10[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_11 = state_reg_left_subtree_state_10[0]; // @[package.scala:163:13]
wire _state_reg_T_67 = _state_reg_T_66[0]; // @[package.scala:163:13]
wire _state_reg_T_71 = _state_reg_T_66[0]; // @[package.scala:163:13]
wire _state_reg_T_68 = _state_reg_T_67; // @[package.scala:163:13]
wire _state_reg_T_69 = ~_state_reg_T_68; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_70 = state_reg_set_left_older_11 ? state_reg_left_subtree_state_11 : _state_reg_T_69; // @[package.scala:163:13]
wire _state_reg_T_72 = _state_reg_T_71; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_73 = ~_state_reg_T_72; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_74 = state_reg_set_left_older_11 ? _state_reg_T_73 : state_reg_right_subtree_state_11; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_8 = {state_reg_set_left_older_11, _state_reg_T_70}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_75 = {state_reg_hi_8, _state_reg_T_74}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_76 = state_reg_set_left_older_10 ? state_reg_left_subtree_state_10 : _state_reg_T_75; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_12 = _state_reg_T_77[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_12 = ~_state_reg_set_left_older_T_12; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state_12 = state_reg_right_subtree_state_10[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state_12 = state_reg_right_subtree_state_10[0]; // @[Replacement.scala:198:38]
wire _state_reg_T_78 = _state_reg_T_77[0]; // @[package.scala:163:13]
wire _state_reg_T_82 = _state_reg_T_77[0]; // @[package.scala:163:13]
wire _state_reg_T_79 = _state_reg_T_78; // @[package.scala:163:13]
wire _state_reg_T_80 = ~_state_reg_T_79; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_81 = state_reg_set_left_older_12 ? state_reg_left_subtree_state_12 : _state_reg_T_80; // @[package.scala:163:13]
wire _state_reg_T_83 = _state_reg_T_82; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_84 = ~_state_reg_T_83; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_85 = state_reg_set_left_older_12 ? _state_reg_T_84 : state_reg_right_subtree_state_12; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi_9 = {state_reg_set_left_older_12, _state_reg_T_81}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_86 = {state_reg_hi_9, _state_reg_T_85}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_87 = state_reg_set_left_older_10 ? _state_reg_T_86 : state_reg_right_subtree_state_10; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_reg_hi_10 = {state_reg_set_left_older_10, _state_reg_T_76}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_88 = {state_reg_hi_10, _state_reg_T_87}; // @[Replacement.scala:202:12, :206:16]
wire [6:0] _state_reg_T_89 = state_reg_set_left_older_6 ? _state_reg_T_88 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [7:0] state_reg_hi_11 = {state_reg_set_left_older_6, _state_reg_T_64}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [14:0] _state_reg_T_90 = {state_reg_hi_11, _state_reg_T_89}; // @[Replacement.scala:202:12, :206:16]
wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [11:0] state_reg_hi_12 = {state_reg_set_left_older, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [26:0] _state_reg_T_92 = {state_reg_hi_12, _state_reg_T_91}; // @[Replacement.scala:202:12, :206:16]
wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala:58:35]
wire [12:0] _idxs_T = r_btb_update_bits_pc[13:1]; // @[Valid.scala:135:21]
wire [3:0] _idxPages_T = {1'h0, idxPageUpdate} + 4'h1; // @[OneHot.scala:32:10]
wire [31:0] _isValid_T = {4'h0, isValid} | mask; // @[OneHot.scala:32:14, :58:35]
wire [31:0] _isValid_T_1 = ~mask; // @[OneHot.scala:58:35]
wire [31:0] _isValid_T_2 = {4'h0, _isValid_T_1[27:0] & isValid}; // @[OneHot.scala:32:14]
wire [31:0] _isValid_T_3 = r_btb_update_bits_isValid ? _isValid_T : _isValid_T_2; // @[Valid.scala:135:21]
wire [37:0] _brIdx_T = r_btb_update_bits_br_pc[38:1]; // @[Valid.scala:135:21]
wire _idxWritesEven_T = idxPageUpdate[0]; // @[OneHot.scala:32:10]
wire idxWritesEven = ~_idxWritesEven_T; // @[BTB.scala:274:{25,39}]
wire [7:0] _pageValid_T = {2'h0, pageValid} | tgtPageReplEn; // @[BTB.scala:204:26, :247:26, :284:28]
wire [7:0] _pageValid_T_1 = _pageValid_T | idxPageReplEn; // @[BTB.scala:241:26, :284:{28,44}]
wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala:214:15, :287:29]
wire _io_resp_valid_T_1 = idxHit[0]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T = idxHit[0]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_97 = idxHit[0]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T = idxHit[0]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T = idxHit[0]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_2 = idxHit[1]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_1 = idxHit[1]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_98 = idxHit[1]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_1 = idxHit[1]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_1 = idxHit[1]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_3 = idxHit[2]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_2 = idxHit[2]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_99 = idxHit[2]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_2 = idxHit[2]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_2 = idxHit[2]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_4 = idxHit[3]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_3 = idxHit[3]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_100 = idxHit[3]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_3 = idxHit[3]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_3 = idxHit[3]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_5 = idxHit[4]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_4 = idxHit[4]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_101 = idxHit[4]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_4 = idxHit[4]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_4 = idxHit[4]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_6 = idxHit[5]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_5 = idxHit[5]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_102 = idxHit[5]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_5 = idxHit[5]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_5 = idxHit[5]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_7 = idxHit[6]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_6 = idxHit[6]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_103 = idxHit[6]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_6 = idxHit[6]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_6 = idxHit[6]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_8 = idxHit[7]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_7 = idxHit[7]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_104 = idxHit[7]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_7 = idxHit[7]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_7 = idxHit[7]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_9 = idxHit[8]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_8 = idxHit[8]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_105 = idxHit[8]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_8 = idxHit[8]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_8 = idxHit[8]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_10 = idxHit[9]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_9 = idxHit[9]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_106 = idxHit[9]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_9 = idxHit[9]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_9 = idxHit[9]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_11 = idxHit[10]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_10 = idxHit[10]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_107 = idxHit[10]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_10 = idxHit[10]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_10 = idxHit[10]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_12 = idxHit[11]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_11 = idxHit[11]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_108 = idxHit[11]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_11 = idxHit[11]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_11 = idxHit[11]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_13 = idxHit[12]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_12 = idxHit[12]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_109 = idxHit[12]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_12 = idxHit[12]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_12 = idxHit[12]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_14 = idxHit[13]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_13 = idxHit[13]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_110 = idxHit[13]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_13 = idxHit[13]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_13 = idxHit[13]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_15 = idxHit[14]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_14 = idxHit[14]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_111 = idxHit[14]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_14 = idxHit[14]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_14 = idxHit[14]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_16 = idxHit[15]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_15 = idxHit[15]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_112 = idxHit[15]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_15 = idxHit[15]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_15 = idxHit[15]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_17 = idxHit[16]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_16 = idxHit[16]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_113 = idxHit[16]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_16 = idxHit[16]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_16 = idxHit[16]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_18 = idxHit[17]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_17 = idxHit[17]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_114 = idxHit[17]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_17 = idxHit[17]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_17 = idxHit[17]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_19 = idxHit[18]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_18 = idxHit[18]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_115 = idxHit[18]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_18 = idxHit[18]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_18 = idxHit[18]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_20 = idxHit[19]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_19 = idxHit[19]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_116 = idxHit[19]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_19 = idxHit[19]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_19 = idxHit[19]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_21 = idxHit[20]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_20 = idxHit[20]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_117 = idxHit[20]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_20 = idxHit[20]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_20 = idxHit[20]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_22 = idxHit[21]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_21 = idxHit[21]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_118 = idxHit[21]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_21 = idxHit[21]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_21 = idxHit[21]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_23 = idxHit[22]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_22 = idxHit[22]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_119 = idxHit[22]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_22 = idxHit[22]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_22 = idxHit[22]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_24 = idxHit[23]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_23 = idxHit[23]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_120 = idxHit[23]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_23 = idxHit[23]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_23 = idxHit[23]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_25 = idxHit[24]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_24 = idxHit[24]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_121 = idxHit[24]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_24 = idxHit[24]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_24 = idxHit[24]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_26 = idxHit[25]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_25 = idxHit[25]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_122 = idxHit[25]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_25 = idxHit[25]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_25 = idxHit[25]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_27 = idxHit[26]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_26 = idxHit[26]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_123 = idxHit[26]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_26 = idxHit[26]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_26 = idxHit[26]; // @[Mux.scala:32:36]
wire _io_resp_valid_T_28 = idxHit[27]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_27 = idxHit[27]; // @[Mux.scala:32:36]
wire _io_resp_bits_target_T_124 = idxHit[27]; // @[Mux.scala:32:36]
wire _io_resp_bits_bridx_T_27 = idxHit[27]; // @[Mux.scala:32:36]
wire _io_resp_bits_cfiType_T_27 = idxHit[27]; // @[Mux.scala:32:36]
wire [2:0] _io_resp_valid_T_29 = _io_resp_valid_T_1 ? idxPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_30 = _io_resp_valid_T_2 ? idxPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_31 = _io_resp_valid_T_3 ? idxPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_32 = _io_resp_valid_T_4 ? idxPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_33 = _io_resp_valid_T_5 ? idxPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_34 = _io_resp_valid_T_6 ? idxPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_35 = _io_resp_valid_T_7 ? idxPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_36 = _io_resp_valid_T_8 ? idxPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_37 = _io_resp_valid_T_9 ? idxPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_38 = _io_resp_valid_T_10 ? idxPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_39 = _io_resp_valid_T_11 ? idxPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_40 = _io_resp_valid_T_12 ? idxPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_41 = _io_resp_valid_T_13 ? idxPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_42 = _io_resp_valid_T_14 ? idxPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_43 = _io_resp_valid_T_15 ? idxPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_44 = _io_resp_valid_T_16 ? idxPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_45 = _io_resp_valid_T_17 ? idxPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_46 = _io_resp_valid_T_18 ? idxPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_47 = _io_resp_valid_T_19 ? idxPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_48 = _io_resp_valid_T_20 ? idxPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_49 = _io_resp_valid_T_21 ? idxPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_50 = _io_resp_valid_T_22 ? idxPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_51 = _io_resp_valid_T_23 ? idxPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_52 = _io_resp_valid_T_24 ? idxPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_53 = _io_resp_valid_T_25 ? idxPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_54 = _io_resp_valid_T_26 ? idxPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_55 = _io_resp_valid_T_27 ? idxPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_56 = _io_resp_valid_T_28 ? idxPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 | _io_resp_valid_T_30; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 | _io_resp_valid_T_31; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 | _io_resp_valid_T_32; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 | _io_resp_valid_T_33; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 | _io_resp_valid_T_34; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 | _io_resp_valid_T_35; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 | _io_resp_valid_T_36; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 | _io_resp_valid_T_37; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 | _io_resp_valid_T_38; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 | _io_resp_valid_T_39; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 | _io_resp_valid_T_40; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 | _io_resp_valid_T_41; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 | _io_resp_valid_T_42; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 | _io_resp_valid_T_43; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 | _io_resp_valid_T_44; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 | _io_resp_valid_T_45; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 | _io_resp_valid_T_46; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 | _io_resp_valid_T_47; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 | _io_resp_valid_T_48; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 | _io_resp_valid_T_49; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 | _io_resp_valid_T_50; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 | _io_resp_valid_T_51; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 | _io_resp_valid_T_52; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 | _io_resp_valid_T_53; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 | _io_resp_valid_T_54; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 | _io_resp_valid_T_55; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 | _io_resp_valid_T_56; // @[Mux.scala:30:73]
wire [2:0] _io_resp_valid_WIRE = _io_resp_valid_T_83; // @[Mux.scala:30:73]
wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_WIRE; // @[Mux.scala:30:73]
assign _io_resp_valid_T_85 = _io_resp_valid_T_84[0]; // @[BTB.scala:287:34]
assign io_resp_valid_0 = _io_resp_valid_T_85; // @[BTB.scala:187:7, :287:34]
wire [2:0] _io_resp_bits_target_T_28 = _io_resp_bits_target_T ? tgtPages_0 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_29 = _io_resp_bits_target_T_1 ? tgtPages_1 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_30 = _io_resp_bits_target_T_2 ? tgtPages_2 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_31 = _io_resp_bits_target_T_3 ? tgtPages_3 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_32 = _io_resp_bits_target_T_4 ? tgtPages_4 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_33 = _io_resp_bits_target_T_5 ? tgtPages_5 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_34 = _io_resp_bits_target_T_6 ? tgtPages_6 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_35 = _io_resp_bits_target_T_7 ? tgtPages_7 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_36 = _io_resp_bits_target_T_8 ? tgtPages_8 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_37 = _io_resp_bits_target_T_9 ? tgtPages_9 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_38 = _io_resp_bits_target_T_10 ? tgtPages_10 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_39 = _io_resp_bits_target_T_11 ? tgtPages_11 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_40 = _io_resp_bits_target_T_12 ? tgtPages_12 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_41 = _io_resp_bits_target_T_13 ? tgtPages_13 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_42 = _io_resp_bits_target_T_14 ? tgtPages_14 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_43 = _io_resp_bits_target_T_15 ? tgtPages_15 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_44 = _io_resp_bits_target_T_16 ? tgtPages_16 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_45 = _io_resp_bits_target_T_17 ? tgtPages_17 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_46 = _io_resp_bits_target_T_18 ? tgtPages_18 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_47 = _io_resp_bits_target_T_19 ? tgtPages_19 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_48 = _io_resp_bits_target_T_20 ? tgtPages_20 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_49 = _io_resp_bits_target_T_21 ? tgtPages_21 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_50 = _io_resp_bits_target_T_22 ? tgtPages_22 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_51 = _io_resp_bits_target_T_23 ? tgtPages_23 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_52 = _io_resp_bits_target_T_24 ? tgtPages_24 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_53 = _io_resp_bits_target_T_25 ? tgtPages_25 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_54 = _io_resp_bits_target_T_26 ? tgtPages_26 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_55 = _io_resp_bits_target_T_27 ? tgtPages_27 : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 | _io_resp_bits_target_T_29; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 | _io_resp_bits_target_T_30; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 | _io_resp_bits_target_T_31; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 | _io_resp_bits_target_T_32; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 | _io_resp_bits_target_T_33; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 | _io_resp_bits_target_T_34; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 | _io_resp_bits_target_T_35; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 | _io_resp_bits_target_T_36; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 | _io_resp_bits_target_T_37; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 | _io_resp_bits_target_T_38; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 | _io_resp_bits_target_T_39; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 | _io_resp_bits_target_T_40; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 | _io_resp_bits_target_T_41; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 | _io_resp_bits_target_T_42; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 | _io_resp_bits_target_T_43; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 | _io_resp_bits_target_T_44; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 | _io_resp_bits_target_T_45; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 | _io_resp_bits_target_T_46; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 | _io_resp_bits_target_T_47; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 | _io_resp_bits_target_T_48; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 | _io_resp_bits_target_T_49; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 | _io_resp_bits_target_T_50; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 | _io_resp_bits_target_T_51; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 | _io_resp_bits_target_T_52; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 | _io_resp_bits_target_T_53; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 | _io_resp_bits_target_T_54; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 | _io_resp_bits_target_T_55; // @[Mux.scala:30:73]
wire [2:0] _io_resp_bits_target_WIRE = _io_resp_bits_target_T_82; // @[Mux.scala:30:73]
wire _io_resp_bits_target_T_83 = _io_resp_bits_target_WIRE == 3'h1; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_83 ? pagesMasked_1 : pagesMasked_0; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_85 = _io_resp_bits_target_WIRE == 3'h2; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_85 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_87 = _io_resp_bits_target_WIRE == 3'h3; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_87 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_89 = _io_resp_bits_target_WIRE == 3'h4; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_89 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_91 = _io_resp_bits_target_WIRE == 3'h5; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_91 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_93 = _io_resp_bits_target_WIRE == 3'h6; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_93 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala:39:{76,86}]
wire _io_resp_bits_target_T_95 = &_io_resp_bits_target_WIRE; // @[Mux.scala:30:73]
wire [24:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_95 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala:39:{76,86}]
wire [12:0] _io_resp_bits_target_T_125 = _io_resp_bits_target_T_97 ? tgts_0 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_126 = _io_resp_bits_target_T_98 ? tgts_1 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_127 = _io_resp_bits_target_T_99 ? tgts_2 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_128 = _io_resp_bits_target_T_100 ? tgts_3 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_129 = _io_resp_bits_target_T_101 ? tgts_4 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_130 = _io_resp_bits_target_T_102 ? tgts_5 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_131 = _io_resp_bits_target_T_103 ? tgts_6 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_132 = _io_resp_bits_target_T_104 ? tgts_7 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_133 = _io_resp_bits_target_T_105 ? tgts_8 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_134 = _io_resp_bits_target_T_106 ? tgts_9 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_135 = _io_resp_bits_target_T_107 ? tgts_10 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_136 = _io_resp_bits_target_T_108 ? tgts_11 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_137 = _io_resp_bits_target_T_109 ? tgts_12 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_138 = _io_resp_bits_target_T_110 ? tgts_13 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_139 = _io_resp_bits_target_T_111 ? tgts_14 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_140 = _io_resp_bits_target_T_112 ? tgts_15 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_141 = _io_resp_bits_target_T_113 ? tgts_16 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_142 = _io_resp_bits_target_T_114 ? tgts_17 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_143 = _io_resp_bits_target_T_115 ? tgts_18 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_144 = _io_resp_bits_target_T_116 ? tgts_19 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_145 = _io_resp_bits_target_T_117 ? tgts_20 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_146 = _io_resp_bits_target_T_118 ? tgts_21 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_147 = _io_resp_bits_target_T_119 ? tgts_22 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_148 = _io_resp_bits_target_T_120 ? tgts_23 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_149 = _io_resp_bits_target_T_121 ? tgts_24 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_150 = _io_resp_bits_target_T_122 ? tgts_25 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_151 = _io_resp_bits_target_T_123 ? tgts_26 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_152 = _io_resp_bits_target_T_124 ? tgts_27 : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 | _io_resp_bits_target_T_126; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 | _io_resp_bits_target_T_127; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 | _io_resp_bits_target_T_128; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 | _io_resp_bits_target_T_129; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 | _io_resp_bits_target_T_130; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 | _io_resp_bits_target_T_131; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 | _io_resp_bits_target_T_132; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 | _io_resp_bits_target_T_133; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 | _io_resp_bits_target_T_134; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 | _io_resp_bits_target_T_135; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 | _io_resp_bits_target_T_136; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 | _io_resp_bits_target_T_137; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 | _io_resp_bits_target_T_138; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 | _io_resp_bits_target_T_139; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 | _io_resp_bits_target_T_140; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 | _io_resp_bits_target_T_141; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 | _io_resp_bits_target_T_142; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 | _io_resp_bits_target_T_143; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 | _io_resp_bits_target_T_144; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 | _io_resp_bits_target_T_145; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 | _io_resp_bits_target_T_146; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 | _io_resp_bits_target_T_147; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 | _io_resp_bits_target_T_148; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 | _io_resp_bits_target_T_149; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 | _io_resp_bits_target_T_150; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 | _io_resp_bits_target_T_151; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 | _io_resp_bits_target_T_152; // @[Mux.scala:30:73]
wire [12:0] _io_resp_bits_target_WIRE_1 = _io_resp_bits_target_T_179; // @[Mux.scala:30:73]
wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_WIRE_1, 1'h0}; // @[Mux.scala:30:73]
wire [38:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96, _io_resp_bits_target_T_180}; // @[package.scala:39:76]
wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala:30:18]
wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala:31:18]
wire _io_resp_bits_entry_T = |io_resp_bits_entry_hi; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _io_resp_bits_entry_T_1 = {4'h0, io_resp_bits_entry_hi} | io_resp_bits_entry_lo; // @[OneHot.scala:30:18, :31:18, :32:{14,28}]
wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _io_resp_bits_entry_T_2 = |io_resp_bits_entry_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 | io_resp_bits_entry_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _io_resp_bits_entry_T_4 = |io_resp_bits_entry_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 | io_resp_bits_entry_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _io_resp_bits_entry_T_6 = |io_resp_bits_entry_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 | io_resp_bits_entry_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _io_resp_bits_entry_T_8 = _io_resp_bits_entry_T_7[1]; // @[OneHot.scala:32:28]
wire [1:0] _io_resp_bits_entry_T_9 = {_io_resp_bits_entry_T_6, _io_resp_bits_entry_T_8}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _io_resp_bits_entry_T_10 = {_io_resp_bits_entry_T_4, _io_resp_bits_entry_T_9}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2, _io_resp_bits_entry_T_10}; // @[OneHot.scala:32:{10,14}]
assign _io_resp_bits_entry_T_12 = {_io_resp_bits_entry_T, _io_resp_bits_entry_T_11}; // @[OneHot.scala:32:{10,14}]
assign io_resp_bits_entry_0 = _io_resp_bits_entry_T_12; // @[OneHot.scala:32:10]
wire _io_resp_bits_bridx_T_28 = _io_resp_bits_bridx_T & brIdx_0; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_29 = _io_resp_bits_bridx_T_1 & brIdx_1; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_30 = _io_resp_bits_bridx_T_2 & brIdx_2; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_31 = _io_resp_bits_bridx_T_3 & brIdx_3; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_32 = _io_resp_bits_bridx_T_4 & brIdx_4; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_33 = _io_resp_bits_bridx_T_5 & brIdx_5; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_34 = _io_resp_bits_bridx_T_6 & brIdx_6; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_35 = _io_resp_bits_bridx_T_7 & brIdx_7; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_36 = _io_resp_bits_bridx_T_8 & brIdx_8; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_37 = _io_resp_bits_bridx_T_9 & brIdx_9; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_38 = _io_resp_bits_bridx_T_10 & brIdx_10; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_39 = _io_resp_bits_bridx_T_11 & brIdx_11; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_40 = _io_resp_bits_bridx_T_12 & brIdx_12; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_41 = _io_resp_bits_bridx_T_13 & brIdx_13; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_42 = _io_resp_bits_bridx_T_14 & brIdx_14; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_43 = _io_resp_bits_bridx_T_15 & brIdx_15; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_44 = _io_resp_bits_bridx_T_16 & brIdx_16; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_45 = _io_resp_bits_bridx_T_17 & brIdx_17; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_46 = _io_resp_bits_bridx_T_18 & brIdx_18; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_47 = _io_resp_bits_bridx_T_19 & brIdx_19; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_48 = _io_resp_bits_bridx_T_20 & brIdx_20; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_49 = _io_resp_bits_bridx_T_21 & brIdx_21; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_50 = _io_resp_bits_bridx_T_22 & brIdx_22; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_51 = _io_resp_bits_bridx_T_23 & brIdx_23; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_52 = _io_resp_bits_bridx_T_24 & brIdx_24; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_53 = _io_resp_bits_bridx_T_25 & brIdx_25; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_54 = _io_resp_bits_bridx_T_26 & brIdx_26; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_55 = _io_resp_bits_bridx_T_27 & brIdx_27; // @[Mux.scala:30:73, :32:36]
wire _io_resp_bits_bridx_T_56 = _io_resp_bits_bridx_T_28 | _io_resp_bits_bridx_T_29; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_57 = _io_resp_bits_bridx_T_56 | _io_resp_bits_bridx_T_30; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_58 = _io_resp_bits_bridx_T_57 | _io_resp_bits_bridx_T_31; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_59 = _io_resp_bits_bridx_T_58 | _io_resp_bits_bridx_T_32; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_60 = _io_resp_bits_bridx_T_59 | _io_resp_bits_bridx_T_33; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_61 = _io_resp_bits_bridx_T_60 | _io_resp_bits_bridx_T_34; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_62 = _io_resp_bits_bridx_T_61 | _io_resp_bits_bridx_T_35; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_63 = _io_resp_bits_bridx_T_62 | _io_resp_bits_bridx_T_36; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_64 = _io_resp_bits_bridx_T_63 | _io_resp_bits_bridx_T_37; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_65 = _io_resp_bits_bridx_T_64 | _io_resp_bits_bridx_T_38; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_66 = _io_resp_bits_bridx_T_65 | _io_resp_bits_bridx_T_39; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_67 = _io_resp_bits_bridx_T_66 | _io_resp_bits_bridx_T_40; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_68 = _io_resp_bits_bridx_T_67 | _io_resp_bits_bridx_T_41; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_69 = _io_resp_bits_bridx_T_68 | _io_resp_bits_bridx_T_42; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_70 = _io_resp_bits_bridx_T_69 | _io_resp_bits_bridx_T_43; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_71 = _io_resp_bits_bridx_T_70 | _io_resp_bits_bridx_T_44; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_72 = _io_resp_bits_bridx_T_71 | _io_resp_bits_bridx_T_45; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_73 = _io_resp_bits_bridx_T_72 | _io_resp_bits_bridx_T_46; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_74 = _io_resp_bits_bridx_T_73 | _io_resp_bits_bridx_T_47; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_75 = _io_resp_bits_bridx_T_74 | _io_resp_bits_bridx_T_48; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_76 = _io_resp_bits_bridx_T_75 | _io_resp_bits_bridx_T_49; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_77 = _io_resp_bits_bridx_T_76 | _io_resp_bits_bridx_T_50; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_78 = _io_resp_bits_bridx_T_77 | _io_resp_bits_bridx_T_51; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_79 = _io_resp_bits_bridx_T_78 | _io_resp_bits_bridx_T_52; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_80 = _io_resp_bits_bridx_T_79 | _io_resp_bits_bridx_T_53; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_81 = _io_resp_bits_bridx_T_80 | _io_resp_bits_bridx_T_54; // @[Mux.scala:30:73]
wire _io_resp_bits_bridx_T_82 = _io_resp_bits_bridx_T_81 | _io_resp_bits_bridx_T_55; // @[Mux.scala:30:73]
assign _io_resp_bits_bridx_WIRE = _io_resp_bits_bridx_T_82; // @[Mux.scala:30:73]
assign io_resp_bits_bridx_0 = _io_resp_bits_bridx_WIRE; // @[Mux.scala:30:73]
wire _io_resp_bits_mask_T = ~io_resp_bits_bridx_0; // @[BTB.scala:187:7, :292:61]
wire _io_resp_bits_mask_T_1 = io_resp_bits_taken_0 & _io_resp_bits_mask_T; // @[BTB.scala:187:7, :292:{40,61}]
wire _io_resp_bits_mask_T_2 = ~_io_resp_bits_mask_T_1; // @[BTB.scala:292:{36,40}]
wire [1:0] _io_resp_bits_mask_T_3 = 2'h1 << _io_resp_bits_mask_T_2; // @[BTB.scala:292:{33,36}]
wire [2:0] _io_resp_bits_mask_T_4 = {1'h0, _io_resp_bits_mask_T_3} - 3'h1; // @[BTB.scala:292:{33,87}]
wire [1:0] _io_resp_bits_mask_T_5 = _io_resp_bits_mask_T_4[1:0]; // @[BTB.scala:292:87]
wire [2:0] _io_resp_bits_mask_T_6 = {_io_resp_bits_mask_T_5, 1'h1}; // @[BTB.scala:187:7, :292:{27,87}]
assign io_resp_bits_mask_0 = _io_resp_bits_mask_T_6[1:0]; // @[BTB.scala:187:7, :292:{21,27}]
wire [1:0] _io_resp_bits_cfiType_T_28 = _io_resp_bits_cfiType_T ? cfiType_0 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_29 = _io_resp_bits_cfiType_T_1 ? cfiType_1 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_30 = _io_resp_bits_cfiType_T_2 ? cfiType_2 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_31 = _io_resp_bits_cfiType_T_3 ? cfiType_3 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_32 = _io_resp_bits_cfiType_T_4 ? cfiType_4 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_33 = _io_resp_bits_cfiType_T_5 ? cfiType_5 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_34 = _io_resp_bits_cfiType_T_6 ? cfiType_6 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_35 = _io_resp_bits_cfiType_T_7 ? cfiType_7 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_36 = _io_resp_bits_cfiType_T_8 ? cfiType_8 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_37 = _io_resp_bits_cfiType_T_9 ? cfiType_9 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_38 = _io_resp_bits_cfiType_T_10 ? cfiType_10 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_39 = _io_resp_bits_cfiType_T_11 ? cfiType_11 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_40 = _io_resp_bits_cfiType_T_12 ? cfiType_12 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_41 = _io_resp_bits_cfiType_T_13 ? cfiType_13 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_42 = _io_resp_bits_cfiType_T_14 ? cfiType_14 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_43 = _io_resp_bits_cfiType_T_15 ? cfiType_15 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_44 = _io_resp_bits_cfiType_T_16 ? cfiType_16 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_45 = _io_resp_bits_cfiType_T_17 ? cfiType_17 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_46 = _io_resp_bits_cfiType_T_18 ? cfiType_18 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_47 = _io_resp_bits_cfiType_T_19 ? cfiType_19 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_48 = _io_resp_bits_cfiType_T_20 ? cfiType_20 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_49 = _io_resp_bits_cfiType_T_21 ? cfiType_21 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_50 = _io_resp_bits_cfiType_T_22 ? cfiType_22 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_51 = _io_resp_bits_cfiType_T_23 ? cfiType_23 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_52 = _io_resp_bits_cfiType_T_24 ? cfiType_24 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_53 = _io_resp_bits_cfiType_T_25 ? cfiType_25 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_54 = _io_resp_bits_cfiType_T_26 ? cfiType_26 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_55 = _io_resp_bits_cfiType_T_27 ? cfiType_27 : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _io_resp_bits_cfiType_T_56 = _io_resp_bits_cfiType_T_28 | _io_resp_bits_cfiType_T_29; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_57 = _io_resp_bits_cfiType_T_56 | _io_resp_bits_cfiType_T_30; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_58 = _io_resp_bits_cfiType_T_57 | _io_resp_bits_cfiType_T_31; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_59 = _io_resp_bits_cfiType_T_58 | _io_resp_bits_cfiType_T_32; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_60 = _io_resp_bits_cfiType_T_59 | _io_resp_bits_cfiType_T_33; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_61 = _io_resp_bits_cfiType_T_60 | _io_resp_bits_cfiType_T_34; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_62 = _io_resp_bits_cfiType_T_61 | _io_resp_bits_cfiType_T_35; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_63 = _io_resp_bits_cfiType_T_62 | _io_resp_bits_cfiType_T_36; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_64 = _io_resp_bits_cfiType_T_63 | _io_resp_bits_cfiType_T_37; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_65 = _io_resp_bits_cfiType_T_64 | _io_resp_bits_cfiType_T_38; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_66 = _io_resp_bits_cfiType_T_65 | _io_resp_bits_cfiType_T_39; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_67 = _io_resp_bits_cfiType_T_66 | _io_resp_bits_cfiType_T_40; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_68 = _io_resp_bits_cfiType_T_67 | _io_resp_bits_cfiType_T_41; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_69 = _io_resp_bits_cfiType_T_68 | _io_resp_bits_cfiType_T_42; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_70 = _io_resp_bits_cfiType_T_69 | _io_resp_bits_cfiType_T_43; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_71 = _io_resp_bits_cfiType_T_70 | _io_resp_bits_cfiType_T_44; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_72 = _io_resp_bits_cfiType_T_71 | _io_resp_bits_cfiType_T_45; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_73 = _io_resp_bits_cfiType_T_72 | _io_resp_bits_cfiType_T_46; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_74 = _io_resp_bits_cfiType_T_73 | _io_resp_bits_cfiType_T_47; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_75 = _io_resp_bits_cfiType_T_74 | _io_resp_bits_cfiType_T_48; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_76 = _io_resp_bits_cfiType_T_75 | _io_resp_bits_cfiType_T_49; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_77 = _io_resp_bits_cfiType_T_76 | _io_resp_bits_cfiType_T_50; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_78 = _io_resp_bits_cfiType_T_77 | _io_resp_bits_cfiType_T_51; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_79 = _io_resp_bits_cfiType_T_78 | _io_resp_bits_cfiType_T_52; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_80 = _io_resp_bits_cfiType_T_79 | _io_resp_bits_cfiType_T_53; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_81 = _io_resp_bits_cfiType_T_80 | _io_resp_bits_cfiType_T_54; // @[Mux.scala:30:73]
wire [1:0] _io_resp_bits_cfiType_T_82 = _io_resp_bits_cfiType_T_81 | _io_resp_bits_cfiType_T_55; // @[Mux.scala:30:73]
assign _io_resp_bits_cfiType_WIRE = _io_resp_bits_cfiType_T_82; // @[Mux.scala:30:73]
assign io_resp_bits_cfiType_0 = _io_resp_bits_cfiType_WIRE; // @[Mux.scala:30:73]
wire leftOne = idxHit[0]; // @[Misc.scala:178:18, :181:37]
wire leftOne_1 = idxHit[1]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne = idxHit[2]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala:178:18, :183:16]
wire rightTwo = leftOne_1 & rightOne; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_2 = leftOne | rightOne_1; // @[Misc.scala:178:18, :183:16]
wire leftTwo = rightTwo | leftOne & rightOne_1; // @[Misc.scala:178:18, :183:{16,49,61}]
wire leftOne_3 = idxHit[3]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_2 = idxHit[4]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala:178:18, :183:16]
wire leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_5 = idxHit[5]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_3 = idxHit[6]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala:178:18, :183:16]
wire rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala:178:18, :183:{49,61}]
wire rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala:183:16]
wire rightTwo_2 = leftTwo_1 | rightTwo_1 | leftOne_4 & rightOne_4; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala:183:16]
wire leftTwo_2 = leftTwo | rightTwo_2 | leftOne_2 & rightOne_5; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_7 = idxHit[7]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_8 = idxHit[8]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_6 = idxHit[9]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala:178:18, :183:16]
wire rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala:178:18, :183:16]
wire leftTwo_3 = rightTwo_3 | leftOne_7 & rightOne_7; // @[Misc.scala:178:18, :183:{16,49,61}]
wire leftOne_10 = idxHit[10]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_8 = idxHit[11]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala:178:18, :183:16]
wire leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_12 = idxHit[12]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_9 = idxHit[13]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala:178:18, :183:16]
wire rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala:178:18, :183:{49,61}]
wire rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala:183:16]
wire rightTwo_5 = leftTwo_4 | rightTwo_4 | leftOne_11 & rightOne_10; // @[Misc.scala:183:{16,37,49,61}]
wire rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala:183:16]
wire rightTwo_6 = leftTwo_3 | rightTwo_5 | leftOne_9 & rightOne_11; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_13 = leftOne_6 | rightOne_12; // @[Misc.scala:183:16]
wire leftTwo_5 = leftTwo_2 | rightTwo_6 | leftOne_6 & rightOne_12; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_14 = idxHit[14]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_15 = idxHit[15]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_13 = idxHit[16]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala:178:18, :183:16]
wire rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala:178:18, :183:16]
wire leftTwo_6 = rightTwo_7 | leftOne_14 & rightOne_14; // @[Misc.scala:178:18, :183:{16,49,61}]
wire leftOne_17 = idxHit[17]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_15 = idxHit[18]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala:178:18, :183:16]
wire leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_19 = idxHit[19]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_16 = idxHit[20]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala:178:18, :183:16]
wire rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala:178:18, :183:{49,61}]
wire rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala:183:16]
wire rightTwo_9 = leftTwo_7 | rightTwo_8 | leftOne_18 & rightOne_17; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala:183:16]
wire leftTwo_8 = leftTwo_6 | rightTwo_9 | leftOne_16 & rightOne_18; // @[Misc.scala:183:{16,37,49,61}]
wire leftOne_21 = idxHit[21]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_22 = idxHit[22]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_19 = idxHit[23]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala:178:18, :183:16]
wire rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala:178:18, :183:16]
wire leftTwo_9 = rightTwo_10 | leftOne_21 & rightOne_20; // @[Misc.scala:178:18, :183:{16,49,61}]
wire leftOne_24 = idxHit[24]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_21 = idxHit[25]; // @[Misc.scala:178:18, :181:37, :182:39]
wire leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala:178:18, :183:16]
wire leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala:178:18, :183:{49,61}]
wire leftOne_26 = idxHit[26]; // @[Misc.scala:178:18, :181:37, :182:39]
wire rightOne_22 = idxHit[27]; // @[Misc.scala:178:18, :182:39]
wire rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala:178:18, :183:16]
wire rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala:178:18, :183:{49,61}]
wire rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala:183:16]
wire rightTwo_12 = leftTwo_10 | rightTwo_11 | leftOne_25 & rightOne_23; // @[Misc.scala:183:{16,37,49,61}]
wire rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala:183:16]
wire rightTwo_13 = leftTwo_9 | rightTwo_12 | leftOne_23 & rightOne_24; // @[Misc.scala:183:{16,37,49,61}]
wire rightOne_26 = leftOne_20 | rightOne_25; // @[Misc.scala:183:16]
wire rightTwo_14 = leftTwo_8 | rightTwo_13 | leftOne_20 & rightOne_25; // @[Misc.scala:183:{16,37,49,61}]
wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala:218:32, :297:26]
wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala:207:24, :297:{24,26}]
reg [7:0] history; // @[BTB.scala:117:24]
assign res_history = history; // @[BTB.scala:91:19, :117:24]
reg [9:0] reset_waddr; // @[BTB.scala:119:36]
wire _resetting_T = reset_waddr[9]; // @[BTB.scala:119:36, :120:39]
wire resetting = ~_resetting_T; // @[BTB.scala:120:{27,39}]
wire wen; // @[BTB.scala:121:29]
wire [9:0] waddr_1; // @[BTB.scala:122:31]
wire wdata; // @[BTB.scala:123:31]
wire [10:0] _reset_waddr_T = {1'h0, reset_waddr} + 11'h1; // @[BTB.scala:119:36, :124:49]
wire [9:0] _reset_waddr_T_1 = _reset_waddr_T[9:0]; // @[BTB.scala:124:49]
wire _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala:208:20, :305:44]
wire [1:0] isBranch_lo_lo_lo_hi = {_isBranch_T_2, _isBranch_T_1}; // @[package.scala:45:27]
wire [2:0] isBranch_lo_lo_lo = {isBranch_lo_lo_lo_hi, _isBranch_T}; // @[package.scala:45:27]
wire [1:0] isBranch_lo_lo_hi_lo = {_isBranch_T_4, _isBranch_T_3}; // @[package.scala:45:27]
wire [1:0] isBranch_lo_lo_hi_hi = {_isBranch_T_6, _isBranch_T_5}; // @[package.scala:45:27]
wire [3:0] isBranch_lo_lo_hi = {isBranch_lo_lo_hi_hi, isBranch_lo_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] isBranch_lo_lo = {isBranch_lo_lo_hi, isBranch_lo_lo_lo}; // @[package.scala:45:27]
wire [1:0] isBranch_lo_hi_lo_hi = {_isBranch_T_9, _isBranch_T_8}; // @[package.scala:45:27]
wire [2:0] isBranch_lo_hi_lo = {isBranch_lo_hi_lo_hi, _isBranch_T_7}; // @[package.scala:45:27]
wire [1:0] isBranch_lo_hi_hi_lo = {_isBranch_T_11, _isBranch_T_10}; // @[package.scala:45:27]
wire [1:0] isBranch_lo_hi_hi_hi = {_isBranch_T_13, _isBranch_T_12}; // @[package.scala:45:27]
wire [3:0] isBranch_lo_hi_hi = {isBranch_lo_hi_hi_hi, isBranch_lo_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] isBranch_lo_hi = {isBranch_lo_hi_hi, isBranch_lo_hi_lo}; // @[package.scala:45:27]
wire [13:0] isBranch_lo = {isBranch_lo_hi, isBranch_lo_lo}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_lo_lo_hi = {_isBranch_T_16, _isBranch_T_15}; // @[package.scala:45:27]
wire [2:0] isBranch_hi_lo_lo = {isBranch_hi_lo_lo_hi, _isBranch_T_14}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_lo_hi_lo = {_isBranch_T_18, _isBranch_T_17}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_lo_hi_hi = {_isBranch_T_20, _isBranch_T_19}; // @[package.scala:45:27]
wire [3:0] isBranch_hi_lo_hi = {isBranch_hi_lo_hi_hi, isBranch_hi_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] isBranch_hi_lo = {isBranch_hi_lo_hi, isBranch_hi_lo_lo}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_hi_lo_hi = {_isBranch_T_23, _isBranch_T_22}; // @[package.scala:45:27]
wire [2:0] isBranch_hi_hi_lo = {isBranch_hi_hi_lo_hi, _isBranch_T_21}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_hi_hi_lo = {_isBranch_T_25, _isBranch_T_24}; // @[package.scala:45:27]
wire [1:0] isBranch_hi_hi_hi_hi = {_isBranch_T_27, _isBranch_T_26}; // @[package.scala:45:27]
wire [3:0] isBranch_hi_hi_hi = {isBranch_hi_hi_hi_hi, isBranch_hi_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] isBranch_hi_hi = {isBranch_hi_hi_hi, isBranch_hi_hi_lo}; // @[package.scala:45:27]
wire [13:0] isBranch_hi = {isBranch_hi_hi, isBranch_hi_lo}; // @[package.scala:45:27]
wire [27:0] _isBranch_T_28 = {isBranch_hi, isBranch_lo}; // @[package.scala:45:27]
wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[package.scala:45:27]
wire isBranch = |_isBranch_T_29; // @[BTB.scala:305:{28,72}]
assign io_resp_bits_bht_history_0 = res_history; // @[BTB.scala:91:19, :187:7]
wire _res_res_value_T_8; // @[BTB.scala:92:21]
assign io_resp_bits_bht_value_0 = res_value; // @[BTB.scala:91:19, :187:7]
wire [36:0] res_res_value_hi = io_req_bits_addr_0[38:2]; // @[BTB.scala:85:21, :187:7]
wire [8:0] _res_res_value_T = res_res_value_hi[8:0]; // @[BTB.scala:85:21, :86:9]
wire [27:0] _res_res_value_T_1 = res_res_value_hi[36:9]; // @[BTB.scala:85:21, :86:48]
wire [1:0] _res_res_value_T_2 = _res_res_value_T_1[1:0]; // @[BTB.scala:86:{48,77}]
wire [8:0] _res_res_value_T_3 = {_res_res_value_T[8:2], _res_res_value_T[1:0] ^ _res_res_value_T_2}; // @[BTB.scala:86:{9,42,77}]
wire [15:0] _res_res_value_T_4 = {8'h0, history} * 16'hDD; // @[BTB.scala:82:12, :117:24]
wire [2:0] _res_res_value_T_5 = _res_res_value_T_4[7:5]; // @[BTB.scala:82:{12,19}]
wire [8:0] _res_res_value_T_6 = {_res_res_value_T_5, 6'h0}; // @[BTB.scala:82:19, :88:44]
wire [8:0] _res_res_value_T_7 = _res_res_value_T_3 ^ _res_res_value_T_6; // @[BTB.scala:86:42, :88:{20,44}]
assign _res_res_value_T_8 = ~resetting & _table_ext_R0_data; // @[BTB.scala:92:21, :116:26, :120:27]
assign res_value = _res_res_value_T_8; // @[BTB.scala:91:19, :92:21]
wire [6:0] _history_T = history[7:1]; // @[BTB.scala:113:35, :117:24]
wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value_0, _history_T}; // @[BTB.scala:113:{19,35}, :187:7]
wire _GEN = io_bht_update_valid_0 & io_bht_update_bits_branch_0; // @[BTB.scala:97:9, :121:29, :187:7, :310:32, :311:40]
assign wen = _GEN | resetting; // @[BTB.scala:97:9, :120:27, :121:29, :310:32, :311:40]
wire [36:0] waddr_hi = io_bht_update_bits_pc_0[38:2]; // @[BTB.scala:85:21, :187:7]
wire [8:0] _waddr_T_40 = waddr_hi[8:0]; // @[BTB.scala:85:21, :86:9]
wire [27:0] _waddr_T_41 = waddr_hi[36:9]; // @[BTB.scala:85:21, :86:48]
wire [1:0] _waddr_T_42 = _waddr_T_41[1:0]; // @[BTB.scala:86:{48,77}]
wire [8:0] _waddr_T_43 = {_waddr_T_40[8:2], _waddr_T_40[1:0] ^ _waddr_T_42}; // @[BTB.scala:86:{9,42,77}]
wire [15:0] _waddr_T_44 = {8'h0, io_bht_update_bits_prediction_history_0} * 16'hDD; // @[BTB.scala:82:12, :187:7]
wire [2:0] _waddr_T_45 = _waddr_T_44[7:5]; // @[BTB.scala:82:{12,19}]
wire [8:0] _waddr_T_46 = {_waddr_T_45, 6'h0}; // @[BTB.scala:82:19, :88:44]
wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala:86:42, :88:{20,44}]
assign waddr_1 = io_bht_update_valid_0 & io_bht_update_bits_branch_0 & ~resetting ? {1'h0, _waddr_T_47} : reset_waddr; // @[BTB.scala:88:20, :98:{11,23}, :99:13, :119:36, :120:27, :122:31, :187:7, :310:32, :311:40]
assign wdata = _GEN & ~resetting & io_bht_update_bits_taken_0; // @[BTB.scala:97:9, :98:{11,23}, :100:13, :120:27, :121:29, :123:31, :187:7, :310:32, :311:40]
wire [6:0] _history_T_2 = io_bht_update_bits_prediction_history_0[7:1]; // @[BTB.scala:110:37, :187:7]
wire [7:0] _history_T_3 = {io_bht_update_bits_taken_0, _history_T_2}; // @[BTB.scala:110:{19,37}, :187:7]
assign io_resp_bits_taken_0 = ~(~res_value & isBranch); // @[BTB.scala:91:19, :187:7, :288:22, :305:72, :320:{11,22,35,56}]
reg [2:0] count; // @[BTB.scala:56:30]
reg [2:0] pos; // @[BTB.scala:57:28]
reg [38:0] stack_0; // @[BTB.scala:58:26]
reg [38:0] stack_1; // @[BTB.scala:58:26]
reg [38:0] stack_2; // @[BTB.scala:58:26]
reg [38:0] stack_3; // @[BTB.scala:58:26]
reg [38:0] stack_4; // @[BTB.scala:58:26]
reg [38:0] stack_5; // @[BTB.scala:58:26]
wire _doPeek_T = &cfiType_0; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_1 = &cfiType_1; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_2 = &cfiType_2; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_3 = &cfiType_3; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_4 = &cfiType_4; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_5 = &cfiType_5; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_6 = &cfiType_6; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_7 = &cfiType_7; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_8 = &cfiType_8; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_9 = &cfiType_9; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_10 = &cfiType_10; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_11 = &cfiType_11; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_12 = &cfiType_12; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_13 = &cfiType_13; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_14 = &cfiType_14; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_15 = &cfiType_15; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_16 = &cfiType_16; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_17 = &cfiType_17; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_18 = &cfiType_18; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_19 = &cfiType_19; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_20 = &cfiType_20; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_21 = &cfiType_21; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_22 = &cfiType_22; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_23 = &cfiType_23; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_24 = &cfiType_24; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_25 = &cfiType_25; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_26 = &cfiType_26; // @[BTB.scala:208:20, :326:42]
wire _doPeek_T_27 = &cfiType_27; // @[BTB.scala:208:20, :326:42]
wire [1:0] doPeek_lo_lo_lo_hi = {_doPeek_T_2, _doPeek_T_1}; // @[package.scala:45:27]
wire [2:0] doPeek_lo_lo_lo = {doPeek_lo_lo_lo_hi, _doPeek_T}; // @[package.scala:45:27]
wire [1:0] doPeek_lo_lo_hi_lo = {_doPeek_T_4, _doPeek_T_3}; // @[package.scala:45:27]
wire [1:0] doPeek_lo_lo_hi_hi = {_doPeek_T_6, _doPeek_T_5}; // @[package.scala:45:27]
wire [3:0] doPeek_lo_lo_hi = {doPeek_lo_lo_hi_hi, doPeek_lo_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] doPeek_lo_lo = {doPeek_lo_lo_hi, doPeek_lo_lo_lo}; // @[package.scala:45:27]
wire [1:0] doPeek_lo_hi_lo_hi = {_doPeek_T_9, _doPeek_T_8}; // @[package.scala:45:27]
wire [2:0] doPeek_lo_hi_lo = {doPeek_lo_hi_lo_hi, _doPeek_T_7}; // @[package.scala:45:27]
wire [1:0] doPeek_lo_hi_hi_lo = {_doPeek_T_11, _doPeek_T_10}; // @[package.scala:45:27]
wire [1:0] doPeek_lo_hi_hi_hi = {_doPeek_T_13, _doPeek_T_12}; // @[package.scala:45:27]
wire [3:0] doPeek_lo_hi_hi = {doPeek_lo_hi_hi_hi, doPeek_lo_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] doPeek_lo_hi = {doPeek_lo_hi_hi, doPeek_lo_hi_lo}; // @[package.scala:45:27]
wire [13:0] doPeek_lo = {doPeek_lo_hi, doPeek_lo_lo}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_lo_lo_hi = {_doPeek_T_16, _doPeek_T_15}; // @[package.scala:45:27]
wire [2:0] doPeek_hi_lo_lo = {doPeek_hi_lo_lo_hi, _doPeek_T_14}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_lo_hi_lo = {_doPeek_T_18, _doPeek_T_17}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_lo_hi_hi = {_doPeek_T_20, _doPeek_T_19}; // @[package.scala:45:27]
wire [3:0] doPeek_hi_lo_hi = {doPeek_hi_lo_hi_hi, doPeek_hi_lo_hi_lo}; // @[package.scala:45:27]
wire [6:0] doPeek_hi_lo = {doPeek_hi_lo_hi, doPeek_hi_lo_lo}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_hi_lo_hi = {_doPeek_T_23, _doPeek_T_22}; // @[package.scala:45:27]
wire [2:0] doPeek_hi_hi_lo = {doPeek_hi_hi_lo_hi, _doPeek_T_21}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_hi_hi_lo = {_doPeek_T_25, _doPeek_T_24}; // @[package.scala:45:27]
wire [1:0] doPeek_hi_hi_hi_hi = {_doPeek_T_27, _doPeek_T_26}; // @[package.scala:45:27]
wire [3:0] doPeek_hi_hi_hi = {doPeek_hi_hi_hi_hi, doPeek_hi_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] doPeek_hi_hi = {doPeek_hi_hi_hi, doPeek_hi_hi_lo}; // @[package.scala:45:27]
wire [13:0] doPeek_hi = {doPeek_hi_hi, doPeek_hi_lo}; // @[package.scala:45:27]
wire [27:0] _doPeek_T_28 = {doPeek_hi, doPeek_lo}; // @[package.scala:45:27]
wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[package.scala:45:27]
wire doPeek = |_doPeek_T_29; // @[BTB.scala:326:{26,67}]
wire _io_ras_head_valid_T = ~(|count); // @[BTB.scala:54:29, :56:30]
assign _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala:54:29, :327:26]
assign io_ras_head_valid_0 = _io_ras_head_valid_T_1; // @[BTB.scala:187:7, :327:26]
wire [7:0][38:0] _GEN_0 = {{stack_0}, {stack_0}, {stack_5}, {stack_4}, {stack_3}, {stack_2}, {stack_1}, {stack_0}}; // @[BTB.scala:58:26, :328:22]
assign io_ras_head_bits_0 = _GEN_0[pos]; // @[BTB.scala:57:28, :187:7, :328:22]
assign io_resp_bits_target_0 = (|count) & doPeek ? io_ras_head_bits_0 : _io_resp_bits_target_T_181; // @[BTB.scala:54:29, :56:30, :187:7, :289:{23,29}, :326:67, :329:{24,35}, :330:27]
wire [3:0] _GEN_1 = {1'h0, count}; // @[BTB.scala:43:44, :56:30]
wire [3:0] _count_T = _GEN_1 + 4'h1; // @[BTB.scala:43:44]
wire [2:0] _count_T_1 = _count_T[2:0]; // @[BTB.scala:43:44]
wire _nextPos_T = pos < 3'h5; // @[BTB.scala:44:47, :57:28]
wire _nextPos_T_1 = _nextPos_T; // @[BTB.scala:44:{40,47}]
wire [3:0] _GEN_2 = {1'h0, pos}; // @[BTB.scala:44:64, :57:28]
wire [3:0] _nextPos_T_2 = _GEN_2 + 4'h1; // @[BTB.scala:44:64]
wire [2:0] _nextPos_T_3 = _nextPos_T_2[2:0]; // @[BTB.scala:44:64]
wire [2:0] nextPos = _nextPos_T_1 ? _nextPos_T_3 : 3'h0; // @[BTB.scala:44:{22,40,64}, :51:40]
wire [3:0] _count_T_2 = _GEN_1 - 4'h1; // @[BTB.scala:43:44, :50:20]
wire [2:0] _count_T_3 = _count_T_2[2:0]; // @[BTB.scala:50:20]
wire _pos_T = |pos; // @[BTB.scala:51:40, :57:28]
wire _pos_T_1 = _pos_T; // @[BTB.scala:51:{33,40}]
wire [3:0] _pos_T_2 = _GEN_2 - 4'h1; // @[BTB.scala:44:64, :51:50]
wire [2:0] _pos_T_3 = _pos_T_2[2:0]; // @[BTB.scala:51:50]
wire [2:0] _pos_T_4 = _pos_T_1 ? _pos_T_3 : 3'h5; // @[BTB.scala:51:{15,33,50}]
wire [4:0] _T_5 = idxWritesEven ? idxPageReplEn[4:0] : tgtPageReplEn[4:0]; // @[BTB.scala:241:26, :247:26, :274:25, :280:24]
wire [24:0] _T_8 = idxWritesEven ? r_btb_update_bits_pc[38:14] : io_req_bits_addr_0[38:14]; // @[Valid.scala:135:21]
wire [4:0] _T_12 = idxWritesEven ? tgtPageReplEn[5:1] : idxPageReplEn[5:1]; // @[BTB.scala:241:26, :247:26, :274:25, :282:24]
wire [24:0] _T_15 = idxWritesEven ? io_req_bits_addr_0[38:14] : r_btb_update_bits_pc[38:14]; // @[Valid.scala:135:21]
wire _T_139 = io_ras_update_bits_cfiType_0 == 2'h2; // @[BTB.scala:187:7, :333:40]
always @(posedge clock) begin // @[BTB.scala:187:7]
if (r_btb_update_valid & waddr == 5'h0) begin // @[Valid.scala:135:21]
idxs_0 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_0 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_0 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_0 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_0 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h1) begin // @[Valid.scala:135:21]
idxs_1 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_1 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_1 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_1 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_1 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h2) begin // @[Valid.scala:135:21]
idxs_2 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_2 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_2 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_2 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_2 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h3) begin // @[Valid.scala:135:21]
idxs_3 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_3 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_3 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_3 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_3 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h4) begin // @[Valid.scala:135:21]
idxs_4 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_4 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_4 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_4 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_4 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h5) begin // @[Valid.scala:135:21]
idxs_5 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_5 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_5 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_5 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_5 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h6) begin // @[Valid.scala:135:21]
idxs_6 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_6 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_6 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_6 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_6 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h7) begin // @[Valid.scala:135:21]
idxs_7 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_7 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_7 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_7 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_7 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h8) begin // @[Valid.scala:135:21]
idxs_8 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_8 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_8 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_8 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_8 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h9) begin // @[Valid.scala:135:21]
idxs_9 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_9 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_9 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_9 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_9 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hA) begin // @[Valid.scala:135:21]
idxs_10 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_10 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_10 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_10 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_10 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hB) begin // @[Valid.scala:135:21]
idxs_11 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_11 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_11 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_11 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_11 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hC) begin // @[Valid.scala:135:21]
idxs_12 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_12 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_12 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_12 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_12 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hD) begin // @[Valid.scala:135:21]
idxs_13 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_13 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_13 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_13 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_13 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hE) begin // @[Valid.scala:135:21]
idxs_14 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_14 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_14 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_14 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_14 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'hF) begin // @[Valid.scala:135:21]
idxs_15 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_15 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_15 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_15 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_15 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h10) begin // @[Valid.scala:135:21]
idxs_16 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_16 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_16 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_16 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_16 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h11) begin // @[Valid.scala:135:21]
idxs_17 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_17 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_17 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_17 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_17 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h12) begin // @[Valid.scala:135:21]
idxs_18 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_18 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_18 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_18 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_18 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h13) begin // @[Valid.scala:135:21]
idxs_19 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_19 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_19 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_19 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_19 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h14) begin // @[Valid.scala:135:21]
idxs_20 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_20 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_20 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_20 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_20 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h15) begin // @[Valid.scala:135:21]
idxs_21 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_21 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_21 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_21 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_21 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h16) begin // @[Valid.scala:135:21]
idxs_22 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_22 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_22 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_22 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_22 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h17) begin // @[Valid.scala:135:21]
idxs_23 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_23 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_23 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_23 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_23 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h18) begin // @[Valid.scala:135:21]
idxs_24 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_24 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_24 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_24 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_24 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h19) begin // @[Valid.scala:135:21]
idxs_25 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_25 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_25 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_25 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_25 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h1A) begin // @[Valid.scala:135:21]
idxs_26 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_26 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_26 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_26 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_26 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & waddr == 5'h1B) begin // @[Valid.scala:135:21]
idxs_27 <= _idxs_T; // @[BTB.scala:199:17, :264:40]
idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala:200:21, :266:{21,38}]
tgts_27 <= _tgts_T; // @[BTB.scala:201:17, :265:33]
tgtPages_27 <= tgtPageUpdate; // @[OneHot.scala:32:10]
cfiType_27 <= r_btb_update_bits_cfiType; // @[Valid.scala:135:21]
brIdx_27 <= _brIdx_T[0]; // @[BTB.scala:209:18, :271:{20,47}]
end
if (r_btb_update_valid & _T_5[0]) // @[Valid.scala:135:21]
pages_0 <= _T_8; // @[BTB.scala:203:18, :281:10]
if (r_btb_update_valid & _T_12[0]) // @[Valid.scala:135:21]
pages_1 <= _T_15; // @[BTB.scala:203:18, :283:10]
if (r_btb_update_valid & _T_5[2]) // @[Valid.scala:135:21]
pages_2 <= _T_8; // @[BTB.scala:203:18, :281:10]
if (r_btb_update_valid & _T_12[2]) // @[Valid.scala:135:21]
pages_3 <= _T_15; // @[BTB.scala:203:18, :283:10]
if (r_btb_update_valid & _T_5[4]) // @[Valid.scala:135:21]
pages_4 <= _T_8; // @[BTB.scala:203:18, :281:10]
if (r_btb_update_valid & _T_12[4]) // @[Valid.scala:135:21]
pages_5 <= _T_15; // @[BTB.scala:203:18, :283:10]
if (io_btb_update_valid_0) begin // @[BTB.scala:187:7]
r_btb_update_pipe_b_prediction_cfiType <= io_btb_update_bits_prediction_cfiType_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_taken <= io_btb_update_bits_prediction_taken_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_mask <= io_btb_update_bits_prediction_mask_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_bridx <= io_btb_update_bits_prediction_bridx_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_target <= io_btb_update_bits_prediction_target_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_entry <= io_btb_update_bits_prediction_entry_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_bht_history <= io_btb_update_bits_prediction_bht_history_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_prediction_bht_value <= io_btb_update_bits_prediction_bht_value_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_pc <= io_btb_update_bits_pc_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_target <= io_btb_update_bits_target_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_isValid <= io_btb_update_bits_isValid_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_br_pc <= io_btb_update_bits_br_pc_0; // @[Valid.scala:142:26]
r_btb_update_pipe_b_cfiType <= io_btb_update_bits_cfiType_0; // @[Valid.scala:142:26]
end
if (io_resp_valid_0) begin // @[BTB.scala:187:7]
r_resp_pipe_b_cfiType <= io_resp_bits_cfiType_0; // @[Valid.scala:142:26]
r_resp_pipe_b_taken <= io_resp_bits_taken_0; // @[Valid.scala:142:26]
r_resp_pipe_b_mask <= io_resp_bits_mask_0; // @[Valid.scala:142:26]
r_resp_pipe_b_bridx <= io_resp_bits_bridx_0; // @[Valid.scala:142:26]
r_resp_pipe_b_target <= io_resp_bits_target_0; // @[Valid.scala:142:26]
r_resp_pipe_b_entry <= io_resp_bits_entry_0; // @[Valid.scala:142:26]
r_resp_pipe_b_bht_history <= io_resp_bits_bht_history_0; // @[Valid.scala:142:26]
r_resp_pipe_b_bht_value <= io_resp_bits_bht_value_0; // @[Valid.scala:142:26]
end
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h0) // @[BTB.scala:44:22, :45:20, :51:40, :58:26, :187:7, :332:32, :333:{40,58}]
stack_0 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h1) // @[package.scala:39:86]
stack_1 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h2) // @[package.scala:39:86]
stack_2 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h3) // @[package.scala:39:86]
stack_3 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h4) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}]
stack_4 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (io_ras_update_valid_0 & _T_139 & nextPos == 3'h5) // @[BTB.scala:44:22, :45:20, :58:26, :187:7, :332:32, :333:{40,58}]
stack_5 <= io_ras_update_bits_returnAddr_0; // @[BTB.scala:58:26, :187:7]
if (reset) begin // @[BTB.scala:187:7]
pageValid <= 6'h0; // @[BTB.scala:204:26]
isValid <= 28'h0; // @[BTB.scala:207:24]
r_btb_update_pipe_v <= 1'h0; // @[Valid.scala:141:24]
nextPageRepl <= 3'h0; // @[BTB.scala:51:40, :237:29]
state_reg <= 27'h0; // @[Replacement.scala:168:70]
r_resp_pipe_v <= 1'h0; // @[Valid.scala:141:24]
history <= 8'h0; // @[BTB.scala:117:24]
reset_waddr <= 10'h0; // @[BTB.scala:119:36]
count <= 3'h0; // @[BTB.scala:51:40, :56:30]
pos <= 3'h0; // @[BTB.scala:51:40, :57:28]
end
else begin // @[BTB.scala:187:7]
if (r_btb_update_valid) // @[Valid.scala:135:21]
pageValid <= _pageValid_T_1[5:0]; // @[BTB.scala:204:26, :284:{15,44}]
if (io_flush_0) // @[BTB.scala:187:7]
isValid <= 28'h0; // @[BTB.scala:207:24]
else if (leftTwo_5 | rightTwo_14 | leftOne_13 & rightOne_26) // @[Misc.scala:183:{16,37,49,61}]
isValid <= _isValid_T_5; // @[BTB.scala:207:24, :297:24]
else if (r_btb_update_valid) // @[Valid.scala:135:21]
isValid <= _isValid_T_3[27:0]; // @[BTB.scala:207:24, :269:{13,19}]
r_btb_update_pipe_v <= io_btb_update_valid_0; // @[Valid.scala:141:24]
if (r_btb_update_valid & (doIdxPageRepl | doTgtPageRepl)) // @[Valid.scala:135:21]
nextPageRepl <= _nextPageRepl_T_2; // @[BTB.scala:237:29, :252:24]
if (r_resp_valid & r_resp_bits_taken | r_btb_update_valid) // @[Valid.scala:135:21]
state_reg <= _state_reg_T_92; // @[Replacement.scala:168:70, :202:12]
r_resp_pipe_v <= io_resp_valid_0; // @[Valid.scala:141:24]
if (io_bht_update_valid_0 & io_bht_update_bits_mispredict_0) // @[BTB.scala:187:7, :307:33, :310:32, :311:40]
history <= io_bht_update_bits_branch_0 ? _history_T_3 : io_bht_update_bits_prediction_history_0; // @[BTB.scala:107:13, :110:{13,19}, :117:24, :187:7, :307:33, :313:46, :316:50]
else if (io_bht_advance_valid_0) // @[BTB.scala:187:7]
history <= _history_T_1; // @[BTB.scala:113:19, :117:24]
if (resetting) // @[BTB.scala:120:27]
reset_waddr <= _reset_waddr_T_1; // @[BTB.scala:119:36, :124:49]
if (io_ras_update_valid_0) begin // @[BTB.scala:187:7]
if (_T_139) begin // @[BTB.scala:333:40]
if (count[2:1] != 2'h3) // @[BTB.scala:43:17, :56:30]
count <= _count_T_1; // @[BTB.scala:43:44, :56:30]
pos <= nextPos; // @[BTB.scala:44:22, :57:28]
end
else if ((&io_ras_update_bits_cfiType_0) & (|count)) begin // @[BTB.scala:49:37, :50:11, :54:29, :56:30, :187:7, :335:{46,63}]
count <= _count_T_3; // @[BTB.scala:50:20, :56:30]
pos <= _pos_T_4; // @[BTB.scala:51:15, :57:28]
end
end
end
always @(posedge)
table_512x1 table_ext ( // @[BTB.scala:116:26]
.R0_addr (_res_res_value_T_7), // @[BTB.scala:88:20]
.R0_en (1'h1), // @[BTB.scala:187:7]
.R0_clk (clock),
.R0_data (_table_ext_R0_data),
.W0_addr (waddr_1[8:0]), // @[BTB.scala:122:31, :125:21]
.W0_en (wen), // @[BTB.scala:121:29]
.W0_clk (clock),
.W0_data (wdata) // @[BTB.scala:123:31]
); // @[BTB.scala:116:26]
assign io_resp_valid = io_resp_valid_0; // @[BTB.scala:187:7]
assign io_resp_bits_cfiType = io_resp_bits_cfiType_0; // @[BTB.scala:187:7]
assign io_resp_bits_taken = io_resp_bits_taken_0; // @[BTB.scala:187:7]
assign io_resp_bits_mask = io_resp_bits_mask_0; // @[BTB.scala:187:7]
assign io_resp_bits_bridx = io_resp_bits_bridx_0; // @[BTB.scala:187:7]
assign io_resp_bits_target = io_resp_bits_target_0; // @[BTB.scala:187:7]
assign io_resp_bits_entry = io_resp_bits_entry_0; // @[BTB.scala:187:7]
assign io_resp_bits_bht_history = io_resp_bits_bht_history_0; // @[BTB.scala:187:7]
assign io_resp_bits_bht_value = io_resp_bits_bht_value_0; // @[BTB.scala:187:7]
assign io_ras_head_valid = io_ras_head_valid_0; // @[BTB.scala:187:7]
assign io_ras_head_bits = io_ras_head_bits_0; // @[BTB.scala:187:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_47
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
invalidate nodeOut.e.safe.sink_reset_n
invalidate nodeOut.e.safe.source_reset_n
invalidate nodeOut.e.safe.widx_valid
invalidate nodeOut.e.safe.ridx_valid
invalidate nodeOut.e.widx
invalidate nodeOut.e.ridx
invalidate nodeOut.e.mem[0].sink
invalidate nodeOut.d.safe.sink_reset_n
invalidate nodeOut.d.safe.source_reset_n
invalidate nodeOut.d.safe.widx_valid
invalidate nodeOut.d.safe.ridx_valid
invalidate nodeOut.d.widx
invalidate nodeOut.d.ridx
invalidate nodeOut.d.mem[0].corrupt
invalidate nodeOut.d.mem[0].data
invalidate nodeOut.d.mem[0].denied
invalidate nodeOut.d.mem[0].sink
invalidate nodeOut.d.mem[0].source
invalidate nodeOut.d.mem[0].size
invalidate nodeOut.d.mem[0].param
invalidate nodeOut.d.mem[0].opcode
invalidate nodeOut.c.safe.sink_reset_n
invalidate nodeOut.c.safe.source_reset_n
invalidate nodeOut.c.safe.widx_valid
invalidate nodeOut.c.safe.ridx_valid
invalidate nodeOut.c.widx
invalidate nodeOut.c.ridx
invalidate nodeOut.c.mem[0].corrupt
invalidate nodeOut.c.mem[0].data
invalidate nodeOut.c.mem[0].address
invalidate nodeOut.c.mem[0].source
invalidate nodeOut.c.mem[0].size
invalidate nodeOut.c.mem[0].param
invalidate nodeOut.c.mem[0].opcode
invalidate nodeOut.b.safe.sink_reset_n
invalidate nodeOut.b.safe.source_reset_n
invalidate nodeOut.b.safe.widx_valid
invalidate nodeOut.b.safe.ridx_valid
invalidate nodeOut.b.widx
invalidate nodeOut.b.ridx
invalidate nodeOut.b.mem[0].corrupt
invalidate nodeOut.b.mem[0].data
invalidate nodeOut.b.mem[0].mask
invalidate nodeOut.b.mem[0].address
invalidate nodeOut.b.mem[0].source
invalidate nodeOut.b.mem[0].size
invalidate nodeOut.b.mem[0].param
invalidate nodeOut.b.mem[0].opcode
invalidate nodeOut.a.safe.sink_reset_n
invalidate nodeOut.a.safe.source_reset_n
invalidate nodeOut.a.safe.widx_valid
invalidate nodeOut.a.safe.ridx_valid
invalidate nodeOut.a.widx
invalidate nodeOut.a.ridx
invalidate nodeOut.a.mem[0].corrupt
invalidate nodeOut.a.mem[0].data
invalidate nodeOut.a.mem[0].mask
invalidate nodeOut.a.mem[0].address
invalidate nodeOut.a.mem[0].source
invalidate nodeOut.a.mem[0].size
invalidate nodeOut.a.mem[0].param
invalidate nodeOut.a.mem[0].opcode
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u
connect nodeOut_a_source.clock, clock
connect nodeOut_a_source.reset, reset
connect nodeOut_a_source.io.enq, nodeIn.a
connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n
connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n
connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid
connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid
connect nodeOut.a.widx, nodeOut_a_source.io.async.widx
connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx
connect nodeOut.a.mem, nodeOut_a_source.io.async.mem
inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u
connect nodeIn_d_sink.clock, clock
connect nodeIn_d_sink.reset, reset
connect nodeIn_d_sink.io.async, nodeOut.d
connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid
connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready
node _T = and(nodeIn.a.valid, nodeIn.a.ready)
node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0))
node _T_2 = and(nodeIn.a.valid, _T_1)
node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0))
node _T_4 = and(_T_3, nodeIn.a.ready)
node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0))
node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0))
node _T_7 = and(_T_5, _T_6)
node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready)
node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0))
node _T_10 = and(nodeIn.d.valid, _T_9)
node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0))
node _T_12 = and(_T_11, nodeIn.d.ready)
node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0))
node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0))
node _T_15 = and(_T_13, _T_14)
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect nodeOut.b.ridx, UInt<1>(0h0)
connect nodeOut.c.widx, UInt<1>(0h0)
connect nodeOut.e.widx, UInt<1>(0h0) | module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9]
input clock, // @[AsyncCrossing.scala:23:9]
input reset, // @[AsyncCrossing.scala:23:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25]
output auto_out_a_widx, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25]
input auto_out_d_widx, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25]
input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25]
output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9]
wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17]
wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9]
wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9]
wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17]
wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17]
wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17]
wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17]
wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17]
wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_widx; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17]
wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_ridx; // @[MixedNode.scala:542:17]
wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17]
wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9]
TLMonitor_47 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_async_mem_0_opcode (nodeOut_a_mem_0_opcode),
.io_async_mem_0_address (nodeOut_a_mem_0_address),
.io_async_mem_0_data (nodeOut_a_mem_0_data),
.io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17]
.io_async_widx (nodeOut_a_widx),
.io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_widx_valid (nodeOut_a_safe_widx_valid),
.io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n),
.io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17]
); // @[AsyncQueue.scala:220:24]
AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22]
.clock (clock),
.reset (reset),
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt),
.io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17]
.io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17]
.io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17]
.io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17]
.io_async_ridx (nodeOut_d_ridx),
.io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17]
.io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid),
.io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17]
.io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17]
.io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n)
); // @[AsyncQueue.scala:211:22]
assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9]
assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_pbus :
output auto : { flip pbus_clock_groups_in : { member : { pbus_0 : { clock : Clock, reset : Reset}}}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst pbus_clock_groups of ClockGroupAggregator_pbus
inst clockGroup of ClockGroup_1
inst fixedClockNode of FixedClockBroadcast_1
inst broadcast of BundleBridgeNexus_NoOutput_1
inst fixer of TLFIFOFixer_1
connect fixer.clock, childClock
connect fixer.reset, childReset
inst in_xbar of TLXbar_pbus_in_i0_o0_a1d8s1k1z1u
connect in_xbar.clock, childClock
connect in_xbar.reset, childReset
inst out_xbar of TLXbar_pbus_out_i0_o0_a1d8s1k1z1u
connect out_xbar.clock, childClock
connect out_xbar.reset, childReset
inst buffer of TLBuffer
connect buffer.clock, childClock
connect buffer.reset, childReset
inst atomics of TLAtomicAutomata_pbus
connect atomics.clock, childClock
connect atomics.reset, childReset
inst buffer_1 of TLBuffer_1
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
connect clockGroup.auto.in, pbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out
connect pbus_clock_groups.auto.in, auto.pbus_clock_groups_in
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module PeripheryBus_pbus( // @[ClockDomain.scala:14:9]
input auto_pbus_clock_groups_in_member_pbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_pbus_clock_groups_in_member_pbus_0_reset // @[LazyModuleImp.scala:107:25]
);
wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire auto_pbus_clock_groups_in_member_pbus_0_clock_0 = auto_pbus_clock_groups_in_member_pbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_pbus_clock_groups_in_member_pbus_0_reset_0 = auto_pbus_clock_groups_in_member_pbus_0_reset; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire pbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire pbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire pbus_clock_groups_auto_in_member_pbus_0_clock = auto_pbus_clock_groups_in_member_pbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_auto_in_member_pbus_0_reset = auto_pbus_clock_groups_in_member_pbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire pbus_clock_groups_nodeIn_member_pbus_0_clock = pbus_clock_groups_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire pbus_clock_groups_nodeIn_member_pbus_0_reset = pbus_clock_groups_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
wire pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_pbus_0_clock = pbus_clock_groups_auto_out_member_pbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_pbus_0_reset = pbus_clock_groups_auto_out_member_pbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_clock = pbus_clock_groups_nodeOut_member_pbus_0_clock; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_auto_out_member_pbus_0_reset = pbus_clock_groups_nodeOut_member_pbus_0_reset; // @[ClockGroup.scala:53:9]
assign pbus_clock_groups_nodeOut_member_pbus_0_clock = pbus_clock_groups_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign pbus_clock_groups_nodeOut_member_pbus_0_reset = pbus_clock_groups_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_pbus_0_clock = clockGroup_auto_in_member_pbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_pbus_0_reset = clockGroup_auto_in_member_pbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9]
wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
TLXbar_pbus_in_i0_o0_a1d8s1k1z1u in_xbar ( // @[PeripheryBus.scala:56:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[PeripheryBus.scala:56:29]
TLXbar_pbus_out_i0_o0_a1d8s1k1z1u out_xbar ( // @[PeripheryBus.scala:57:30]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[PeripheryBus.scala:57:30]
TLBuffer buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
TLAtomicAutomata_pbus atomics ( // @[AtomicAutomata.scala:289:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[AtomicAutomata.scala:289:29]
TLBuffer_1 buffer_1 ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset) // @[LazyModuleImp.scala:158:31]
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_9 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_9
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_9( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_9 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_10 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_10( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_35 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_70
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_71
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:143:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_35( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_74 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_74( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_110 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<12>, set : UInt<10>, clients : UInt<2>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset remain : UInt<2>, clock, reset, UInt<2>(0h0)
wire remain_set : UInt<2>
connect remain_set, UInt<2>(0h0)
wire remain_clr : UInt<2>
connect remain_clr, UInt<2>(0h0)
node _remain_T = or(remain, remain_set)
node _remain_T_1 = not(remain_clr)
node _remain_T_2 = and(_remain_T, _remain_T_1)
connect remain, _remain_T_2
node busy = orr(remain)
node todo = mux(busy, remain, io.req.bits.clients)
node _next_T = shl(todo, 1)
node _next_T_1 = bits(_next_T, 1, 0)
node _next_T_2 = or(todo, _next_T_1)
node _next_T_3 = bits(_next_T_2, 1, 0)
node _next_T_4 = shl(_next_T_3, 1)
node _next_T_5 = not(_next_T_4)
node next = and(_next_T_5, todo)
node _T = bits(remain, 0, 0)
node _T_1 = bits(remain, 1, 1)
node _T_2 = add(_T, _T_1)
node _T_3 = bits(_T_2, 1, 0)
node _T_4 = gt(_T_3, UInt<1>(0h1))
node _T_5 = eq(io.req.valid, UInt<1>(0h0))
node _T_6 = neq(io.req.bits.clients, UInt<1>(0h0))
node _T_7 = or(_T_5, _T_6)
node _T_8 = asUInt(reset)
node _T_9 = eq(_T_8, UInt<1>(0h0))
when _T_9 :
node _T_10 = eq(_T_7, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf
assert(clock, _T_7, UInt<1>(0h1), "") : assert
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _T_11 = and(io.req.ready, io.req.valid)
when _T_11 :
connect remain_set, io.req.bits.clients
wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect io.b, b
node _b_valid_T = or(busy, io.req.valid)
connect b.valid, _b_valid_T
node _T_12 = and(b.ready, b.valid)
when _T_12 :
connect remain_clr, next
node _T_13 = eq(b.ready, UInt<1>(0h0))
node _T_14 = and(b.valid, _T_13)
node _tag_T = eq(busy, UInt<1>(0h0))
node _tag_T_1 = and(io.req.ready, io.req.valid)
reg tag_r : UInt<12>, clock
when _tag_T_1 :
connect tag_r, io.req.bits.tag
node tag = mux(_tag_T, io.req.bits.tag, tag_r)
node _set_T = eq(busy, UInt<1>(0h0))
node _set_T_1 = and(io.req.ready, io.req.valid)
reg set_r : UInt<10>, clock
when _set_T_1 :
connect set_r, io.req.bits.set
node set = mux(_set_T, io.req.bits.set, set_r)
node _param_T = eq(busy, UInt<1>(0h0))
node _param_T_1 = and(io.req.ready, io.req.valid)
reg param_r : UInt<3>, clock
when _param_T_1 :
connect param_r, io.req.bits.param
node param = mux(_param_T, io.req.bits.param, param_r)
connect b.bits.opcode, UInt<3>(0h6)
connect b.bits.param, param
connect b.bits.size, UInt<3>(0h6)
node _b_bits_source_T = bits(next, 0, 0)
node _b_bits_source_T_1 = bits(next, 1, 1)
node _b_bits_source_T_2 = mux(_b_bits_source_T, UInt<5>(0h10), UInt<1>(0h0))
node _b_bits_source_T_3 = mux(_b_bits_source_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _b_bits_source_T_4 = or(_b_bits_source_T_2, _b_bits_source_T_3)
wire _b_bits_source_WIRE : UInt<5>
connect _b_bits_source_WIRE, _b_bits_source_T_4
connect b.bits.source, _b_bits_source_WIRE
node b_bits_address_base_y = or(tag, UInt<12>(0h0))
node _b_bits_address_base_T = shr(b_bits_address_base_y, 12)
node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0))
node _b_bits_address_base_T_2 = asUInt(reset)
node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0))
when _b_bits_address_base_T_3 :
node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0))
when _b_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf
assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert
node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 11, 0)
node b_bits_address_base_y_1 = or(set, UInt<10>(0h0))
node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10)
node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0))
node _b_bits_address_base_T_8 = asUInt(reset)
node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0))
when _b_bits_address_base_T_9 :
node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0))
when _b_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1
assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1
node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0)
node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6)
node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0))
node _b_bits_address_base_T_14 = asUInt(reset)
node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0))
when _b_bits_address_base_T_15 :
node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0))
when _b_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2
assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2
node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0)
node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11)
node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17)
node _b_bits_address_T = bits(b_bits_address_base, 0, 0)
node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1)
node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2)
node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3)
node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4)
node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5)
node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6)
node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7)
node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8)
node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9)
node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10)
node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11)
node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12)
node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13)
node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14)
node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15)
node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16)
node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17)
node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18)
node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19)
node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20)
node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21)
node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22)
node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23)
node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24)
node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25)
node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26)
node _b_bits_address_T_27 = bits(b_bits_address_base, 27, 27)
node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T)
node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2)
node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo)
node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4)
node b_bits_address_lo_lo_hi_hi = cat(_b_bits_address_T_7, _b_bits_address_T_6)
node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo)
node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo)
node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_9, _b_bits_address_T_8)
node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_11, _b_bits_address_T_10)
node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo)
node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_13, _b_bits_address_T_12)
node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_15, _b_bits_address_T_14)
node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo)
node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo)
node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo)
node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_17, _b_bits_address_T_16)
node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_19, _b_bits_address_T_18)
node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo)
node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_21, _b_bits_address_T_20)
node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_23, _b_bits_address_T_22)
node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo)
node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo)
node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_25, _b_bits_address_T_24)
node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_27, _b_bits_address_T_26)
node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo)
node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node b_bits_address_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo)
node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo)
node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo)
node _b_bits_address_T_28 = cat(b_bits_address_hi, b_bits_address_lo)
connect b.bits.address, _b_bits_address_T_28
node _b_bits_mask_T = not(UInt<8>(0h0))
connect b.bits.mask, _b_bits_mask_T
connect b.bits.data, UInt<1>(0h0)
connect b.bits.corrupt, UInt<1>(0h0) | module SourceB( // @[SourceB.scala:33:7]
input clock, // @[SourceB.scala:33:7]
input reset, // @[SourceB.scala:33:7]
output io_req_ready, // @[SourceB.scala:35:14]
input io_req_valid, // @[SourceB.scala:35:14]
input [2:0] io_req_bits_param, // @[SourceB.scala:35:14]
input [11:0] io_req_bits_tag, // @[SourceB.scala:35:14]
input [9:0] io_req_bits_set, // @[SourceB.scala:35:14]
input [1:0] io_req_bits_clients, // @[SourceB.scala:35:14]
input io_b_ready, // @[SourceB.scala:35:14]
output io_b_valid, // @[SourceB.scala:35:14]
output [1:0] io_b_bits_param, // @[SourceB.scala:35:14]
output [4:0] io_b_bits_source, // @[SourceB.scala:35:14]
output [31:0] io_b_bits_address // @[SourceB.scala:35:14]
);
wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7]
wire [11:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7]
wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7]
wire [1:0] io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7]
wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7]
wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12]
wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12]
wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12]
wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7]
wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7]
wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17]
wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17]
wire [7:0] io_b_bits_mask = 8'hFF; // @[SourceB.scala:33:7]
wire [7:0] b_bits_mask = 8'hFF; // @[SourceB.scala:65:17]
wire [7:0] _b_bits_mask_T = 8'hFF; // @[SourceB.scala:81:23]
wire [63:0] io_b_bits_data = 64'h0; // @[SourceB.scala:33:7]
wire [63:0] b_bits_data = 64'h0; // @[SourceB.scala:65:17]
wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7]
wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17]
wire _b_bits_source_T_3 = 1'h0; // @[Mux.scala:30:73]
wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15]
wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12]
wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15]
wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12]
wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15]
wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12]
wire [3:0] b_bits_address_hi_hi_hi = 4'h0; // @[Parameters.scala:230:8]
wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8]
wire [1:0] b_bits_address_hi_hi_hi_hi = 2'h0; // @[Parameters.scala:230:8]
wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15]
wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6]
wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24]
wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24]
wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24]
wire _io_req_ready_T; // @[SourceB.scala:61:21]
wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17]
wire b_valid; // @[SourceB.scala:65:17]
wire [1:0] b_bits_param; // @[SourceB.scala:65:17]
wire [4:0] b_bits_source; // @[SourceB.scala:65:17]
wire [31:0] b_bits_address; // @[SourceB.scala:65:17]
wire io_req_ready_0; // @[SourceB.scala:33:7]
wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7]
wire [4:0] io_b_bits_source_0; // @[SourceB.scala:33:7]
wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7]
wire io_b_valid_0; // @[SourceB.scala:33:7]
reg [1:0] remain; // @[SourceB.scala:46:25]
wire [1:0] remain_set; // @[SourceB.scala:47:30]
wire [1:0] remain_clr; // @[SourceB.scala:48:30]
wire [1:0] _remain_T = remain | remain_set; // @[SourceB.scala:46:25, :47:30, :49:23]
wire [1:0] _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39]
wire [1:0] _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}]
wire busy = |remain; // @[SourceB.scala:46:25, :51:23]
wire [1:0] todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19]
wire [2:0] _next_T = {todo, 1'h0}; // @[package.scala:253:48]
wire [1:0] _next_T_1 = _next_T[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _next_T_2 = todo | _next_T_1; // @[package.scala:253:{43,53}]
wire [1:0] _next_T_3 = _next_T_2; // @[package.scala:253:43, :254:17]
wire [2:0] _next_T_4 = {_next_T_3, 1'h0}; // @[package.scala:254:17]
wire [2:0] _next_T_5 = ~_next_T_4; // @[SourceB.scala:53:{16,31}]
wire [2:0] next = {1'h0, _next_T_5[1:0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_42 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_42( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_Phit_12 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire sink_ready : UInt<1>
connect sink_ready, UInt<1>(0h1)
reg mem : { phit : UInt<32>}[8], clock
node _widx_T = asAsyncReset(reset)
node _widx_T_1 = and(io.enq.ready, io.enq.valid)
node _widx_T_2 = eq(sink_ready, UInt<1>(0h0))
wire widx_incremented : UInt<4>
regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0)
connect widx_widx_bin, widx_incremented
node _widx_incremented_T = add(widx_widx_bin, _widx_T_1)
node _widx_incremented_T_1 = tail(_widx_incremented_T, 1)
node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1)
connect widx_incremented, _widx_incremented_T_2
node _widx_T_3 = shr(widx_incremented, 1)
node widx = xor(widx_incremented, _widx_T_3)
inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_24
connect ridx_ridx_gray.clock, clock
connect ridx_ridx_gray.reset, reset
connect ridx_ridx_gray.io.d, io.async.ridx
wire ridx : UInt<4>
connect ridx, ridx_ridx_gray.io.q
node _ready_T = xor(ridx, UInt<4>(0hc))
node _ready_T_1 = neq(widx, _ready_T)
node ready = and(sink_ready, _ready_T_1)
node _index_T = bits(io.async.widx, 2, 0)
node _index_T_1 = bits(io.async.widx, 3, 3)
node _index_T_2 = shl(_index_T_1, 2)
node index = xor(_index_T, _index_T_2)
node _T = and(io.enq.ready, io.enq.valid)
when _T :
connect mem[index], io.enq.bits
node _ready_reg_T = asAsyncReset(reset)
regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0)
connect ready_reg, ready
node _io_enq_ready_T = and(ready_reg, sink_ready)
connect io.enq.ready, _io_enq_ready_T
node _widx_reg_T = asAsyncReset(reset)
regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0)
connect widx_gray, widx
connect io.async.widx, widx_gray
connect io.async.mem, mem
inst source_valid_0 of AsyncValidSync_120
inst source_valid_1 of AsyncValidSync_121
inst sink_extend of AsyncValidSync_122
inst sink_valid of AsyncValidSync_123
node _source_valid_0_reset_T = asUInt(reset)
node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1)
node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2)
connect source_valid_0.reset, _source_valid_0_reset_T_3
node _source_valid_1_reset_T = asUInt(reset)
node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1)
node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2)
connect source_valid_1.reset, _source_valid_1_reset_T_3
node _sink_extend_reset_T = asUInt(reset)
node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0))
node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1)
node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2)
connect sink_extend.reset, _sink_extend_reset_T_3
node _sink_valid_reset_T = asAsyncReset(reset)
connect sink_valid.reset, _sink_valid_reset_T
connect source_valid_0.clock, clock
connect source_valid_1.clock, clock
connect sink_extend.clock, clock
connect sink_valid.clock, clock
connect source_valid_0.io.in, UInt<1>(0h1)
connect source_valid_1.io.in, source_valid_0.io.out
connect io.async.safe.widx_valid, source_valid_1.io.out
connect sink_extend.io.in, io.async.safe.ridx_valid
connect sink_valid.io.in, sink_extend.io.out
connect sink_ready, sink_valid.io.out
node _io_async_safe_source_reset_n_T = asUInt(reset)
node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0))
connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1 | module AsyncQueueSource_Phit_12( // @[AsyncQueue.scala:70:7]
input clock, // @[AsyncQueue.scala:70:7]
input reset, // @[AsyncQueue.scala:70:7]
output io_enq_ready, // @[AsyncQueue.scala:73:14]
input io_enq_valid, // @[AsyncQueue.scala:73:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14]
output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14]
input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14]
output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14]
input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14]
output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14]
input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14]
);
wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30]
wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7]
wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7]
wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7]
wire _widx_T = reset; // @[AsyncQueue.scala:83:30]
wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35]
wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34]
wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36]
wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36]
wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36]
wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35]
wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34]
wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29]
wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27]
wire io_enq_ready_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7]
wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7]
wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7]
wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7]
wire sink_ready; // @[AsyncQueue.scala:81:28]
reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16]
reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16]
assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16]
wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77]
wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77]
assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] ridx; // @[ShiftReg.scala:48:24]
wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24]
wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}]
wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}]
wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52]
wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}]
reg ready_reg; // @[AsyncQueue.scala:90:56]
assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29]
assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29]
reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55]
assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55]
wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46]
wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}]
wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}]
wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46]
wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}]
wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}]
wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46]
wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}]
wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}]
assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}]
assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27]
always @(posedge clock) begin // @[AsyncQueue.scala:70:7]
if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35]
mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35]
mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35]
mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35]
mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35]
mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35]
mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35]
mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35]
mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16]
always @(posedge)
always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30]
if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30]
widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:70:7]
widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35]
if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35]
ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56]
else // @[AsyncQueue.scala:70:7]
ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56]
always @(posedge, posedge)
always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34]
if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34]
widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55]
else // @[AsyncQueue.scala:70:7]
widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_110
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_111
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/BankedCoherenceParams.scala:74:103)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_55( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_cbus :
output auto : { coupler_to_prci_ctrl_fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bootrom_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_sodor_tile_tl_slave_clock_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, coupler_to_debug_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_plic_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_clint_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_pbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
input custom_boot : UInt<1>
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst cbus_clock_groups of ClockGroupAggregator_cbus
inst clockGroup of ClockGroup_3
inst fixedClockNode of FixedClockBroadcast_7
inst broadcast of BundleBridgeNexus_NoOutput_3
inst fixer of TLFIFOFixer_2
connect fixer.clock, childClock
connect fixer.reset, childReset
inst in_xbar of TLXbar_cbus_in_i2_o1_a32d64s7k1z4u
connect in_xbar.clock, childClock
connect in_xbar.reset, childReset
inst out_xbar of TLXbar_cbus_out_i1_o8_a32d64s7k1z4u
connect out_xbar.clock, childClock
connect out_xbar.reset, childReset
inst buffer of TLBuffer_a32d64s7k1z4u
connect buffer.clock, childClock
connect buffer.reset, childReset
inst atomics of TLAtomicAutomata_cbus
connect atomics.clock, childClock
connect atomics.reset, childReset
inst wrapped_error_device of ErrorDeviceWrapper
connect wrapped_error_device.clock, childClock
connect wrapped_error_device.reset, childReset
inst buffer_1 of TLBuffer_a32d64s6k1z4u
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus
connect coupler_to_bus_named_pbus.clock, childClock
connect coupler_to_bus_named_pbus.reset, childReset
inst coupler_to_clint of TLInterconnectCoupler_cbus_to_clint
connect coupler_to_clint.clock, childClock
connect coupler_to_clint.reset, childReset
inst coupler_to_plic of TLInterconnectCoupler_cbus_to_plic
connect coupler_to_plic.clock, childClock
connect coupler_to_plic.reset, childReset
inst coupler_to_debug of TLInterconnectCoupler_cbus_to_debug
connect coupler_to_debug.clock, childClock
connect coupler_to_debug.reset, childReset
inst coupler_to_sodor_tile of TLInterconnectCoupler_cbus_to_sodor_tile
connect coupler_to_sodor_tile.clock, childClock
connect coupler_to_sodor_tile.reset, childReset
inst coupler_to_bootrom of TLInterconnectCoupler_cbus_to_bootrom
connect coupler_to_bootrom.clock, childClock
connect coupler_to_bootrom.reset, childReset
inst coupler_from_port_named_custom_boot_pin of TLInterconnectCoupler_cbus_from_port_named_custom_boot_pin
connect coupler_from_port_named_custom_boot_pin.clock, childClock
connect coupler_from_port_named_custom_boot_pin.reset, childReset
inst coupler_to_prci_ctrl of TLInterconnectCoupler_cbus_to_prci_ctrl
connect coupler_to_prci_ctrl.clock, childClock
connect coupler_to_prci_ctrl.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect clockGroup.auto.in, cbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect out_xbar.auto.anon_in, fixer.auto.anon_out
connect atomics.auto.in, in_xbar.auto.anon_out
connect wrapped_error_device.auto.buffer_in, out_xbar.auto.anon_out_0
connect coupler_to_bus_named_pbus.auto.widget_anon_in, out_xbar.auto.anon_out_1
connect coupler_to_clint.auto.tl_in, out_xbar.auto.anon_out_2
connect coupler_to_plic.auto.tl_in, out_xbar.auto.anon_out_3
connect coupler_to_debug.auto.tl_in, out_xbar.auto.anon_out_4
connect coupler_to_sodor_tile.auto.tl_in, out_xbar.auto.anon_out_5
connect coupler_to_bootrom.auto.tl_in, out_xbar.auto.anon_out_6
connect coupler_to_prci_ctrl.auto.tl_in, out_xbar.auto.anon_out_7
connect fixer.auto.anon_in, buffer.auto.out
connect buffer.auto.in, atomics.auto.out
connect in_xbar.auto.anon_in_0, buffer_1.auto.out
connect buffer_1.auto.in, bus_xingOut
connect coupler_from_port_named_custom_boot_pin.auto.tl_in, nodeOut
connect in_xbar.auto.anon_in_1, coupler_from_port_named_custom_boot_pin.auto.tl_out
connect bus_xingIn, auto.bus_xing_in
connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4
connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5
connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6
connect coupler_to_bus_named_pbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_pbus_bus_xing_out.d
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.bits, coupler_to_bus_named_pbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.valid, coupler_to_bus_named_pbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_pbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_pbus_bus_xing_out.a.ready
connect coupler_to_clint.auto.fragmenter_anon_out.d, auto.coupler_to_clint_fragmenter_anon_out.d
connect auto.coupler_to_clint_fragmenter_anon_out.a.bits, coupler_to_clint.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_clint_fragmenter_anon_out.a.valid, coupler_to_clint.auto.fragmenter_anon_out.a.valid
connect coupler_to_clint.auto.fragmenter_anon_out.a.ready, auto.coupler_to_clint_fragmenter_anon_out.a.ready
connect coupler_to_plic.auto.fragmenter_anon_out.d, auto.coupler_to_plic_fragmenter_anon_out.d
connect auto.coupler_to_plic_fragmenter_anon_out.a.bits, coupler_to_plic.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_plic_fragmenter_anon_out.a.valid, coupler_to_plic.auto.fragmenter_anon_out.a.valid
connect coupler_to_plic.auto.fragmenter_anon_out.a.ready, auto.coupler_to_plic_fragmenter_anon_out.a.ready
connect coupler_to_debug.auto.fragmenter_anon_out.d, auto.coupler_to_debug_fragmenter_anon_out.d
connect auto.coupler_to_debug_fragmenter_anon_out.a.bits, coupler_to_debug.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_debug_fragmenter_anon_out.a.valid, coupler_to_debug.auto.fragmenter_anon_out.a.valid
connect coupler_to_debug.auto.fragmenter_anon_out.a.ready, auto.coupler_to_debug_fragmenter_anon_out.a.ready
connect coupler_to_sodor_tile.auto.tl_slave_clock_xing_out.d, auto.coupler_to_sodor_tile_tl_slave_clock_xing_out.d
connect auto.coupler_to_sodor_tile_tl_slave_clock_xing_out.a.bits, coupler_to_sodor_tile.auto.tl_slave_clock_xing_out.a.bits
connect auto.coupler_to_sodor_tile_tl_slave_clock_xing_out.a.valid, coupler_to_sodor_tile.auto.tl_slave_clock_xing_out.a.valid
connect coupler_to_sodor_tile.auto.tl_slave_clock_xing_out.a.ready, auto.coupler_to_sodor_tile_tl_slave_clock_xing_out.a.ready
connect coupler_to_bootrom.auto.fragmenter_anon_out.d, auto.coupler_to_bootrom_fragmenter_anon_out.d
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.bits, coupler_to_bootrom.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.valid, coupler_to_bootrom.auto.fragmenter_anon_out.a.valid
connect coupler_to_bootrom.auto.fragmenter_anon_out.a.ready, auto.coupler_to_bootrom_fragmenter_anon_out.a.ready
connect coupler_to_prci_ctrl.auto.fixer_anon_out.d, auto.coupler_to_prci_ctrl_fixer_anon_out.d
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.bits, coupler_to_prci_ctrl.auto.fixer_anon_out.a.bits
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.valid, coupler_to_prci_ctrl.auto.fixer_anon_out.a.valid
connect coupler_to_prci_ctrl.auto.fixer_anon_out.a.ready, auto.coupler_to_prci_ctrl_fixer_anon_out.a.ready
regreset state : UInt<3>, childClock, childReset, UInt<3>(0h0)
connect nodeOut.a.valid, UInt<1>(0h0)
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
connect nodeOut.d.ready, UInt<1>(0h1)
node _T = eq(UInt<3>(0h0), state)
when _T :
when custom_boot :
connect state, UInt<3>(0h1)
else :
node _T_1 = eq(UInt<3>(0h1), state)
when _T_1 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_1 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_2 = and(_nodeOut_a_bits_legal_T, _nodeOut_a_bits_legal_T_1)
node _nodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_2)
node _nodeOut_a_bits_legal_T_4 = xor(UInt<13>(0h1000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_5 = cvt(_nodeOut_a_bits_legal_T_4)
node _nodeOut_a_bits_legal_T_6 = and(_nodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h8a113000)))
node _nodeOut_a_bits_legal_T_7 = asSInt(_nodeOut_a_bits_legal_T_6)
node _nodeOut_a_bits_legal_T_8 = eq(_nodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_9 = and(_nodeOut_a_bits_legal_T_3, _nodeOut_a_bits_legal_T_8)
node _nodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_11 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_12 = and(_nodeOut_a_bits_legal_T_10, _nodeOut_a_bits_legal_T_11)
node _nodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_12)
node _nodeOut_a_bits_legal_T_14 = xor(UInt<13>(0h1000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_15 = cvt(_nodeOut_a_bits_legal_T_14)
node _nodeOut_a_bits_legal_T_16 = and(_nodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h8a112000)))
node _nodeOut_a_bits_legal_T_17 = asSInt(_nodeOut_a_bits_legal_T_16)
node _nodeOut_a_bits_legal_T_18 = eq(_nodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_19 = xor(UInt<13>(0h1000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_20 = cvt(_nodeOut_a_bits_legal_T_19)
node _nodeOut_a_bits_legal_T_21 = and(_nodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h8a103000)))
node _nodeOut_a_bits_legal_T_22 = asSInt(_nodeOut_a_bits_legal_T_21)
node _nodeOut_a_bits_legal_T_23 = eq(_nodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_24 = xor(UInt<13>(0h1000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_25 = cvt(_nodeOut_a_bits_legal_T_24)
node _nodeOut_a_bits_legal_T_26 = and(_nodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h8a110000)))
node _nodeOut_a_bits_legal_T_27 = asSInt(_nodeOut_a_bits_legal_T_26)
node _nodeOut_a_bits_legal_T_28 = eq(_nodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_29 = xor(UInt<13>(0h1000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_30 = cvt(_nodeOut_a_bits_legal_T_29)
node _nodeOut_a_bits_legal_T_31 = and(_nodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h88000000)))
node _nodeOut_a_bits_legal_T_32 = asSInt(_nodeOut_a_bits_legal_T_31)
node _nodeOut_a_bits_legal_T_33 = eq(_nodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_34 = xor(UInt<13>(0h1000), UInt<32>(0h80000000))
node _nodeOut_a_bits_legal_T_35 = cvt(_nodeOut_a_bits_legal_T_34)
node _nodeOut_a_bits_legal_T_36 = and(_nodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h8a100000)))
node _nodeOut_a_bits_legal_T_37 = asSInt(_nodeOut_a_bits_legal_T_36)
node _nodeOut_a_bits_legal_T_38 = eq(_nodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_39 = or(_nodeOut_a_bits_legal_T_18, _nodeOut_a_bits_legal_T_23)
node _nodeOut_a_bits_legal_T_40 = or(_nodeOut_a_bits_legal_T_39, _nodeOut_a_bits_legal_T_28)
node _nodeOut_a_bits_legal_T_41 = or(_nodeOut_a_bits_legal_T_40, _nodeOut_a_bits_legal_T_33)
node _nodeOut_a_bits_legal_T_42 = or(_nodeOut_a_bits_legal_T_41, _nodeOut_a_bits_legal_T_38)
node _nodeOut_a_bits_legal_T_43 = and(_nodeOut_a_bits_legal_T_13, _nodeOut_a_bits_legal_T_42)
node _nodeOut_a_bits_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_45 = xor(UInt<13>(0h1000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_46 = cvt(_nodeOut_a_bits_legal_T_45)
node _nodeOut_a_bits_legal_T_47 = and(_nodeOut_a_bits_legal_T_46, asSInt(UInt<33>(0h8a110000)))
node _nodeOut_a_bits_legal_T_48 = asSInt(_nodeOut_a_bits_legal_T_47)
node _nodeOut_a_bits_legal_T_49 = eq(_nodeOut_a_bits_legal_T_48, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_50 = and(_nodeOut_a_bits_legal_T_44, _nodeOut_a_bits_legal_T_49)
node _nodeOut_a_bits_legal_T_51 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_9)
node _nodeOut_a_bits_legal_T_52 = or(_nodeOut_a_bits_legal_T_51, _nodeOut_a_bits_legal_T_43)
node nodeOut_a_bits_legal = or(_nodeOut_a_bits_legal_T_52, _nodeOut_a_bits_legal_T_50)
wire nodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a.param, UInt<1>(0h0)
connect nodeOut_a_bits_a.size, UInt<2>(0h2)
connect nodeOut_a_bits_a.source, UInt<1>(0h0)
connect nodeOut_a_bits_a.address, UInt<13>(0h1000)
node _nodeOut_a_bits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_nodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _nodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH = or(_nodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_0_2)
node nodeOut_a_bits_a_mask_sub_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_1_2)
node nodeOut_a_bits_a_mask_sub_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_0_2)
node nodeOut_a_bits_a_mask_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_1_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_1_2)
node nodeOut_a_bits_a_mask_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_2_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_2_2)
node nodeOut_a_bits_a_mask_sub_2_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_3_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_3_2)
node nodeOut_a_bits_a_mask_sub_3_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_3)
node nodeOut_a_bits_a_mask_size = bits(nodeOut_a_bits_a_mask_sizeOH, 0, 0)
node nodeOut_a_bits_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq = and(nodeOut_a_bits_a_mask_sub_0_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq)
node nodeOut_a_bits_a_mask_acc = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T)
node nodeOut_a_bits_a_mask_eq_1 = and(nodeOut_a_bits_a_mask_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_1 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_1)
node nodeOut_a_bits_a_mask_acc_1 = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T_1)
node nodeOut_a_bits_a_mask_eq_2 = and(nodeOut_a_bits_a_mask_sub_1_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_2 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_2)
node nodeOut_a_bits_a_mask_acc_2 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_2)
node nodeOut_a_bits_a_mask_eq_3 = and(nodeOut_a_bits_a_mask_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_3 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_3)
node nodeOut_a_bits_a_mask_acc_3 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_3)
node nodeOut_a_bits_a_mask_eq_4 = and(nodeOut_a_bits_a_mask_sub_2_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_4 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_4)
node nodeOut_a_bits_a_mask_acc_4 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_4)
node nodeOut_a_bits_a_mask_eq_5 = and(nodeOut_a_bits_a_mask_sub_2_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_5 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_5)
node nodeOut_a_bits_a_mask_acc_5 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_5)
node nodeOut_a_bits_a_mask_eq_6 = and(nodeOut_a_bits_a_mask_sub_3_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_6 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_6)
node nodeOut_a_bits_a_mask_acc_6 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_6)
node nodeOut_a_bits_a_mask_eq_7 = and(nodeOut_a_bits_a_mask_sub_3_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_7 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_7)
node nodeOut_a_bits_a_mask_acc_7 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_7)
node nodeOut_a_bits_a_mask_lo_lo = cat(nodeOut_a_bits_a_mask_acc_1, nodeOut_a_bits_a_mask_acc)
node nodeOut_a_bits_a_mask_lo_hi = cat(nodeOut_a_bits_a_mask_acc_3, nodeOut_a_bits_a_mask_acc_2)
node nodeOut_a_bits_a_mask_lo = cat(nodeOut_a_bits_a_mask_lo_hi, nodeOut_a_bits_a_mask_lo_lo)
node nodeOut_a_bits_a_mask_hi_lo = cat(nodeOut_a_bits_a_mask_acc_5, nodeOut_a_bits_a_mask_acc_4)
node nodeOut_a_bits_a_mask_hi_hi = cat(nodeOut_a_bits_a_mask_acc_7, nodeOut_a_bits_a_mask_acc_6)
node nodeOut_a_bits_a_mask_hi = cat(nodeOut_a_bits_a_mask_hi_hi, nodeOut_a_bits_a_mask_hi_lo)
node _nodeOut_a_bits_a_mask_T = cat(nodeOut_a_bits_a_mask_hi, nodeOut_a_bits_a_mask_lo)
connect nodeOut_a_bits_a.mask, _nodeOut_a_bits_a_mask_T
connect nodeOut_a_bits_a.data, UInt<32>(0h80000000)
connect nodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a
node _T_2 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_2 :
connect state, UInt<3>(0h2)
else :
node _T_3 = eq(UInt<3>(0h2), state)
when _T_3 :
node _T_4 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_4 :
connect state, UInt<3>(0h3)
else :
node _T_5 = eq(UInt<3>(0h3), state)
when _T_5 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T_53 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_54 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_55 = and(_nodeOut_a_bits_legal_T_53, _nodeOut_a_bits_legal_T_54)
node _nodeOut_a_bits_legal_T_56 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_55)
node _nodeOut_a_bits_legal_T_57 = xor(UInt<26>(0h2000000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_58 = cvt(_nodeOut_a_bits_legal_T_57)
node _nodeOut_a_bits_legal_T_59 = and(_nodeOut_a_bits_legal_T_58, asSInt(UInt<33>(0h8a113000)))
node _nodeOut_a_bits_legal_T_60 = asSInt(_nodeOut_a_bits_legal_T_59)
node _nodeOut_a_bits_legal_T_61 = eq(_nodeOut_a_bits_legal_T_60, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_62 = and(_nodeOut_a_bits_legal_T_56, _nodeOut_a_bits_legal_T_61)
node _nodeOut_a_bits_legal_T_63 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_64 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_65 = and(_nodeOut_a_bits_legal_T_63, _nodeOut_a_bits_legal_T_64)
node _nodeOut_a_bits_legal_T_66 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_65)
node _nodeOut_a_bits_legal_T_67 = xor(UInt<26>(0h2000000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_68 = cvt(_nodeOut_a_bits_legal_T_67)
node _nodeOut_a_bits_legal_T_69 = and(_nodeOut_a_bits_legal_T_68, asSInt(UInt<33>(0h8a112000)))
node _nodeOut_a_bits_legal_T_70 = asSInt(_nodeOut_a_bits_legal_T_69)
node _nodeOut_a_bits_legal_T_71 = eq(_nodeOut_a_bits_legal_T_70, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_72 = xor(UInt<26>(0h2000000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_73 = cvt(_nodeOut_a_bits_legal_T_72)
node _nodeOut_a_bits_legal_T_74 = and(_nodeOut_a_bits_legal_T_73, asSInt(UInt<33>(0h8a103000)))
node _nodeOut_a_bits_legal_T_75 = asSInt(_nodeOut_a_bits_legal_T_74)
node _nodeOut_a_bits_legal_T_76 = eq(_nodeOut_a_bits_legal_T_75, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_77 = xor(UInt<26>(0h2000000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_78 = cvt(_nodeOut_a_bits_legal_T_77)
node _nodeOut_a_bits_legal_T_79 = and(_nodeOut_a_bits_legal_T_78, asSInt(UInt<33>(0h8a110000)))
node _nodeOut_a_bits_legal_T_80 = asSInt(_nodeOut_a_bits_legal_T_79)
node _nodeOut_a_bits_legal_T_81 = eq(_nodeOut_a_bits_legal_T_80, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_82 = xor(UInt<26>(0h2000000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_83 = cvt(_nodeOut_a_bits_legal_T_82)
node _nodeOut_a_bits_legal_T_84 = and(_nodeOut_a_bits_legal_T_83, asSInt(UInt<33>(0h88000000)))
node _nodeOut_a_bits_legal_T_85 = asSInt(_nodeOut_a_bits_legal_T_84)
node _nodeOut_a_bits_legal_T_86 = eq(_nodeOut_a_bits_legal_T_85, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_87 = xor(UInt<26>(0h2000000), UInt<32>(0h80000000))
node _nodeOut_a_bits_legal_T_88 = cvt(_nodeOut_a_bits_legal_T_87)
node _nodeOut_a_bits_legal_T_89 = and(_nodeOut_a_bits_legal_T_88, asSInt(UInt<33>(0h8a100000)))
node _nodeOut_a_bits_legal_T_90 = asSInt(_nodeOut_a_bits_legal_T_89)
node _nodeOut_a_bits_legal_T_91 = eq(_nodeOut_a_bits_legal_T_90, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_92 = or(_nodeOut_a_bits_legal_T_71, _nodeOut_a_bits_legal_T_76)
node _nodeOut_a_bits_legal_T_93 = or(_nodeOut_a_bits_legal_T_92, _nodeOut_a_bits_legal_T_81)
node _nodeOut_a_bits_legal_T_94 = or(_nodeOut_a_bits_legal_T_93, _nodeOut_a_bits_legal_T_86)
node _nodeOut_a_bits_legal_T_95 = or(_nodeOut_a_bits_legal_T_94, _nodeOut_a_bits_legal_T_91)
node _nodeOut_a_bits_legal_T_96 = and(_nodeOut_a_bits_legal_T_66, _nodeOut_a_bits_legal_T_95)
node _nodeOut_a_bits_legal_T_97 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_98 = xor(UInt<26>(0h2000000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_99 = cvt(_nodeOut_a_bits_legal_T_98)
node _nodeOut_a_bits_legal_T_100 = and(_nodeOut_a_bits_legal_T_99, asSInt(UInt<33>(0h8a110000)))
node _nodeOut_a_bits_legal_T_101 = asSInt(_nodeOut_a_bits_legal_T_100)
node _nodeOut_a_bits_legal_T_102 = eq(_nodeOut_a_bits_legal_T_101, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_103 = and(_nodeOut_a_bits_legal_T_97, _nodeOut_a_bits_legal_T_102)
node _nodeOut_a_bits_legal_T_104 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_62)
node _nodeOut_a_bits_legal_T_105 = or(_nodeOut_a_bits_legal_T_104, _nodeOut_a_bits_legal_T_96)
node nodeOut_a_bits_legal_1 = or(_nodeOut_a_bits_legal_T_105, _nodeOut_a_bits_legal_T_103)
wire nodeOut_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a_1.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.param, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.size, UInt<2>(0h2)
connect nodeOut_a_bits_a_1.source, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.address, UInt<26>(0h2000000)
node _nodeOut_a_bits_a_mask_sizeOH_T_3 = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_3, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1)
node _nodeOut_a_bits_a_mask_sizeOH_T_5 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_4, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH_1 = or(_nodeOut_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_3)
node nodeOut_a_bits_a_mask_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_4 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_4)
node nodeOut_a_bits_a_mask_sub_1_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_5 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_5)
node nodeOut_a_bits_a_mask_sub_2_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_6 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_2_2_1)
node nodeOut_a_bits_a_mask_sub_2_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_6)
node nodeOut_a_bits_a_mask_sub_3_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_7 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_3_2_1)
node nodeOut_a_bits_a_mask_sub_3_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_7)
node nodeOut_a_bits_a_mask_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 0, 0)
node nodeOut_a_bits_a_mask_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq_8 = and(nodeOut_a_bits_a_mask_sub_0_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_8 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_8)
node nodeOut_a_bits_a_mask_acc_8 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_8)
node nodeOut_a_bits_a_mask_eq_9 = and(nodeOut_a_bits_a_mask_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_9 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_9)
node nodeOut_a_bits_a_mask_acc_9 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_9)
node nodeOut_a_bits_a_mask_eq_10 = and(nodeOut_a_bits_a_mask_sub_1_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_10 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_10)
node nodeOut_a_bits_a_mask_acc_10 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_10)
node nodeOut_a_bits_a_mask_eq_11 = and(nodeOut_a_bits_a_mask_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_11 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_11)
node nodeOut_a_bits_a_mask_acc_11 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_11)
node nodeOut_a_bits_a_mask_eq_12 = and(nodeOut_a_bits_a_mask_sub_2_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_12 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_12)
node nodeOut_a_bits_a_mask_acc_12 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_12)
node nodeOut_a_bits_a_mask_eq_13 = and(nodeOut_a_bits_a_mask_sub_2_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_13 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_13)
node nodeOut_a_bits_a_mask_acc_13 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_13)
node nodeOut_a_bits_a_mask_eq_14 = and(nodeOut_a_bits_a_mask_sub_3_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_14 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_14)
node nodeOut_a_bits_a_mask_acc_14 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_14)
node nodeOut_a_bits_a_mask_eq_15 = and(nodeOut_a_bits_a_mask_sub_3_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_15 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_15)
node nodeOut_a_bits_a_mask_acc_15 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_15)
node nodeOut_a_bits_a_mask_lo_lo_1 = cat(nodeOut_a_bits_a_mask_acc_9, nodeOut_a_bits_a_mask_acc_8)
node nodeOut_a_bits_a_mask_lo_hi_1 = cat(nodeOut_a_bits_a_mask_acc_11, nodeOut_a_bits_a_mask_acc_10)
node nodeOut_a_bits_a_mask_lo_1 = cat(nodeOut_a_bits_a_mask_lo_hi_1, nodeOut_a_bits_a_mask_lo_lo_1)
node nodeOut_a_bits_a_mask_hi_lo_1 = cat(nodeOut_a_bits_a_mask_acc_13, nodeOut_a_bits_a_mask_acc_12)
node nodeOut_a_bits_a_mask_hi_hi_1 = cat(nodeOut_a_bits_a_mask_acc_15, nodeOut_a_bits_a_mask_acc_14)
node nodeOut_a_bits_a_mask_hi_1 = cat(nodeOut_a_bits_a_mask_hi_hi_1, nodeOut_a_bits_a_mask_hi_lo_1)
node _nodeOut_a_bits_a_mask_T_1 = cat(nodeOut_a_bits_a_mask_hi_1, nodeOut_a_bits_a_mask_lo_1)
connect nodeOut_a_bits_a_1.mask, _nodeOut_a_bits_a_mask_T_1
connect nodeOut_a_bits_a_1.data, UInt<1>(0h1)
connect nodeOut_a_bits_a_1.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a_1
node _T_6 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_6 :
connect state, UInt<3>(0h4)
else :
node _T_7 = eq(UInt<3>(0h4), state)
when _T_7 :
node _T_8 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_8 :
connect state, UInt<3>(0h5)
else :
node _T_9 = eq(UInt<3>(0h5), state)
when _T_9 :
node _T_10 = eq(custom_boot, UInt<1>(0h0))
when _T_10 :
connect state, UInt<3>(0h0)
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module PeripheryBus_cbus( // @[ClockDomain.scala:14:9]
input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input custom_boot // @[CustomBootPin.scala:36:29]
);
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_sodor_tile_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_sodor_tile_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_sodor_tile_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_sodor_tile_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_sodor_tile_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_sodor_tile_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_sodor_tile_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_sodor_tile_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_sodor_tile_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_sodor_tile_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [6:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29]
wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29]
wire [31:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [31:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [11:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [27:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_2_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_2_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_2_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_2_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_2_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [25:0] _out_xbar_auto_anon_out_2_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_2_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_2_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_2_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_2_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30]
wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29]
wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29]
wire [6:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29]
wire [31:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29]
wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29]
wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29]
wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29]
wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_ready_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_valid_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_opcode_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_param_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_size_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_source_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_sink_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_denied_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_data_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_corrupt_0 = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_51 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21]
wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29]
wire _nodeOut_a_bits_legal_T_61 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_62 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_71 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_76 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_86 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_91 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_104 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21]
wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17]
wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17]
wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10]
wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17]
wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17]
wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17]
wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17]
wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17]
wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_39 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_40 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_41 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_42 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_43 = 1'h1; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_52 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _nodeOut_a_bits_legal_T_53 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_54 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_55 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_56 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_63 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_64 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_65 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_66 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_81 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_93 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_94 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_95 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_96 = 1'h1; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17]
wire [31:0] nodeOut_a_bits_a_1_address = 32'h2000000; // @[Edges.scala:480:17]
wire [32:0] _nodeOut_a_bits_legal_T_100 = 33'h2010000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_101 = 33'h2010000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_99 = 27'h2010000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_88 = 33'h82000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_89 = 33'h82000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_90 = 33'h82000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_31 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_32 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_84 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_85 = 33'h8000000; // @[Parameters.scala:137:46]
wire [28:0] _nodeOut_a_bits_legal_T_83 = 29'hA000000; // @[Parameters.scala:137:41]
wire [32:0] fixer__a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_16 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_79 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_80 = 33'h0; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_78 = 27'h0; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_74 = 33'h2100000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_75 = 33'h2100000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_73 = 27'h2100000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_26 = 33'h2000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_27 = 33'h2000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_69 = 33'h2000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_70 = 33'h2000000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_68 = 27'h2000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_59 = 33'h2003000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_60 = 33'h2003000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_58 = 27'h2003000; // @[Parameters.scala:137:41]
wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17]
wire [31:0] nodeOut_a_bits_a_address = 32'h1000; // @[Edges.scala:480:17]
wire [32:0] _nodeOut_a_bits_legal_T_47 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_48 = 33'h10000; // @[Parameters.scala:137:46]
wire [17:0] _nodeOut_a_bits_legal_T_46 = 18'h11000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_36 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_37 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_35 = 33'h80001000; // @[Parameters.scala:137:41]
wire [28:0] _nodeOut_a_bits_legal_T_30 = 29'h8001000; // @[Parameters.scala:137:41]
wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_21 = 33'h101000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_22 = 33'h101000; // @[Parameters.scala:137:46]
wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41]
wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_a_bits_legal_T_6 = 33'h2000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_legal_T_7 = 33'h2000; // @[Parameters.scala:137:46]
wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41]
wire [64:0] fixer__allIDs_FIFOed_T = 65'h1FFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [25:0] _nodeOut_a_bits_legal_T_98 = 26'h2010000; // @[Parameters.scala:137:31]
wire [31:0] _nodeOut_a_bits_legal_T_87 = 32'h82000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_a_bits_legal_T_82 = 28'hA000000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_77 = 26'h0; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_72 = 26'h2100000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_57 = 26'h2003000; // @[Parameters.scala:137:31]
wire [16:0] _nodeOut_a_bits_legal_T_45 = 17'h11000; // @[Parameters.scala:137:31]
wire [31:0] _nodeOut_a_bits_legal_T_34 = 32'h80001000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_a_bits_legal_T_29 = 28'h8001000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31]
wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31]
wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34]
wire [25:0] _nodeOut_a_bits_legal_T_67 = 26'h2000000; // @[Parameters.scala:137:31]
wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [6:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46]
wire fixer__a_id_T_4 = fixer__a_id_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[31:13], fixer_anonIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46]
wire fixer__a_id_T_9 = fixer__a_id_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_10 = {fixer_anonIn_a_bits_address[31:29], fixer_anonIn_a_bits_address[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_12 = fixer__a_id_T_11 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_13 = fixer__a_id_T_12; // @[Parameters.scala:137:46]
wire fixer__a_id_T_14 = fixer__a_id_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_15 = fixer__a_id_T_9 | fixer__a_id_T_14; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_id_T_16 = {fixer_anonIn_a_bits_address[31:14], fixer_anonIn_a_bits_address[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_17 = {1'h0, fixer__a_id_T_16}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_18 = fixer__a_id_T_17 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_19 = fixer__a_id_T_18; // @[Parameters.scala:137:46]
wire fixer__a_id_T_20 = fixer__a_id_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_48 = fixer__a_id_T_20; // @[Mux.scala:30:73]
wire [31:0] fixer__a_id_T_21 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_22 = {1'h0, fixer__a_id_T_21}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_23 = fixer__a_id_T_22 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_24 = fixer__a_id_T_23; // @[Parameters.scala:137:46]
wire fixer__a_id_T_25 = fixer__a_id_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_26 = {fixer_anonIn_a_bits_address[31:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_27 = {1'h0, fixer__a_id_T_26}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_28 = fixer__a_id_T_27 & 33'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_29 = fixer__a_id_T_28; // @[Parameters.scala:137:46]
wire fixer__a_id_T_30 = fixer__a_id_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_31 = {fixer_anonIn_a_bits_address[31:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_32 = {1'h0, fixer__a_id_T_31}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_33 = fixer__a_id_T_32 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_34 = fixer__a_id_T_33; // @[Parameters.scala:137:46]
wire fixer__a_id_T_35 = fixer__a_id_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_36 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_37 = {1'h0, fixer__a_id_T_36}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_38 = fixer__a_id_T_37 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_39 = fixer__a_id_T_38; // @[Parameters.scala:137:46]
wire fixer__a_id_T_40 = fixer__a_id_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_id_T_41 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_id_T_42 = {1'h0, fixer__a_id_T_41}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_id_T_43 = fixer__a_id_T_42 & 33'h9A100000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_id_T_44 = fixer__a_id_T_43; // @[Parameters.scala:137:46]
wire fixer__a_id_T_45 = fixer__a_id_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [3:0] fixer__a_id_T_46 = {fixer__a_id_T_4, 3'h0}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_47 = {2{fixer__a_id_T_15}}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_49 = {fixer__a_id_T_25, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_50 = fixer__a_id_T_30 ? 3'h6 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_51 = fixer__a_id_T_35 ? 3'h5 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_52 = {3{fixer__a_id_T_40}}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_53 = {fixer__a_id_T_45, 1'h0}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_54 = {fixer__a_id_T_46[3:2], fixer__a_id_T_46[1:0] | fixer__a_id_T_47}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_55 = {fixer__a_id_T_54[3:1], fixer__a_id_T_54[0] | fixer__a_id_T_48}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_56 = {fixer__a_id_T_55[3], fixer__a_id_T_55[2:0] | fixer__a_id_T_49}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_57 = {fixer__a_id_T_56[3], fixer__a_id_T_56[2:0] | fixer__a_id_T_50}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_58 = {fixer__a_id_T_57[3], fixer__a_id_T_57[2:0] | fixer__a_id_T_51}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_59 = {fixer__a_id_T_58[3], fixer__a_id_T_58[2:0] | fixer__a_id_T_52}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_60 = {fixer__a_id_T_59[3:2], fixer__a_id_T_59[1:0] | fixer__a_id_T_53}; // @[Mux.scala:30:73]
wire [3:0] fixer_a_id = fixer__a_id_T_60; // @[Mux.scala:30:73]
wire fixer_a_noDomain = fixer_a_id == 4'h0; // @[Mux.scala:30:73]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_31; // @[FIFOFixer.scala:79:27]
reg fixer_flight_32; // @[FIFOFixer.scala:79:27]
reg fixer_flight_33; // @[FIFOFixer.scala:79:27]
reg fixer_flight_34; // @[FIFOFixer.scala:79:27]
reg fixer_flight_35; // @[FIFOFixer.scala:79:27]
reg fixer_flight_36; // @[FIFOFixer.scala:79:27]
reg fixer_flight_37; // @[FIFOFixer.scala:79:27]
reg fixer_flight_38; // @[FIFOFixer.scala:79:27]
reg fixer_flight_39; // @[FIFOFixer.scala:79:27]
reg fixer_flight_40; // @[FIFOFixer.scala:79:27]
reg fixer_flight_41; // @[FIFOFixer.scala:79:27]
reg fixer_flight_42; // @[FIFOFixer.scala:79:27]
reg fixer_flight_43; // @[FIFOFixer.scala:79:27]
reg fixer_flight_44; // @[FIFOFixer.scala:79:27]
reg fixer_flight_45; // @[FIFOFixer.scala:79:27]
reg fixer_flight_46; // @[FIFOFixer.scala:79:27]
reg fixer_flight_47; // @[FIFOFixer.scala:79:27]
reg fixer_flight_48; // @[FIFOFixer.scala:79:27]
reg fixer_flight_49; // @[FIFOFixer.scala:79:27]
reg fixer_flight_50; // @[FIFOFixer.scala:79:27]
reg fixer_flight_51; // @[FIFOFixer.scala:79:27]
reg fixer_flight_52; // @[FIFOFixer.scala:79:27]
reg fixer_flight_53; // @[FIFOFixer.scala:79:27]
reg fixer_flight_54; // @[FIFOFixer.scala:79:27]
reg fixer_flight_55; // @[FIFOFixer.scala:79:27]
reg fixer_flight_56; // @[FIFOFixer.scala:79:27]
reg fixer_flight_57; // @[FIFOFixer.scala:79:27]
reg fixer_flight_58; // @[FIFOFixer.scala:79:27]
reg fixer_flight_59; // @[FIFOFixer.scala:79:27]
reg fixer_flight_60; // @[FIFOFixer.scala:79:27]
reg fixer_flight_61; // @[FIFOFixer.scala:79:27]
reg fixer_flight_62; // @[FIFOFixer.scala:79:27]
reg fixer_flight_63; // @[FIFOFixer.scala:79:27]
reg fixer_flight_64; // @[FIFOFixer.scala:79:27]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [64:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [64:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [64:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [127:0] fixer__SourceIdSet_T = 128'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [127:0] fixer__SourceIdClear_T = 128'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [64:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [5:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [5:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [5:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9]
assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
reg [2:0] state; // @[CustomBootPin.scala:39:28]
wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24]
assign nodeOut_a_valid = (|state) & (_T_1 | state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24]
assign nodeOut_a_bits_address = _T_1 ? 32'h1000 : 32'h2000000; // @[CustomBootPin.scala:43:24, :47:23]
assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}]
wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 65'h0; // @[FIFOFixer.scala:115:35]
state <= 3'h0; // @[CustomBootPin.scala:39:28]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 7'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 7'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50]
end
always @(posedge)
FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0),
.auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0),
.auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0),
.auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0),
.auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0),
.auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0),
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_cbus_in_i2_o1_a32d64s7k1z4u in_xbar ( // @[PeripheryBus.scala:56:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready),
.auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid),
.auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param),
.auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready),
.auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid),
.auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode),
.auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param),
.auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size),
.auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source),
.auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink),
.auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied),
.auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt),
.auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29]
); // @[PeripheryBus.scala:56:29]
TLXbar_cbus_out_i1_o8_a32d64s7k1z4u out_xbar ( // @[PeripheryBus.scala:57:30]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (fixer_auto_anon_out_a_ready),
.auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_valid (fixer_auto_anon_out_d_valid),
.auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode),
.auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param),
.auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size),
.auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source),
.auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink),
.auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied),
.auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data),
.auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt),
.auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid),
.auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode),
.auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param),
.auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size),
.auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source),
.auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address),
.auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask),
.auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data),
.auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt),
.auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready),
.auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid),
.auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode),
.auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param),
.auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size),
.auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source),
.auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address),
.auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask),
.auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data),
.auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt),
.auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready),
.auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_5_a_ready (_coupler_to_sodor_tile_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid),
.auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode),
.auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param),
.auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size),
.auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source),
.auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address),
.auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask),
.auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data),
.auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt),
.auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready),
.auto_anon_out_5_d_valid (_coupler_to_sodor_tile_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_opcode (_coupler_to_sodor_tile_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_param (_coupler_to_sodor_tile_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_size (_coupler_to_sodor_tile_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_source (_coupler_to_sodor_tile_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_sink (_coupler_to_sodor_tile_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_denied (_coupler_to_sodor_tile_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_data (_coupler_to_sodor_tile_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_corrupt (_coupler_to_sodor_tile_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_out_4_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid),
.auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode),
.auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param),
.auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size),
.auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source),
.auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address),
.auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask),
.auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data),
.auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt),
.auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready),
.auto_anon_out_4_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_3_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid),
.auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode),
.auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param),
.auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size),
.auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source),
.auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address),
.auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask),
.auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data),
.auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt),
.auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready),
.auto_anon_out_3_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_2_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_2_a_valid (_out_xbar_auto_anon_out_2_a_valid),
.auto_anon_out_2_a_bits_opcode (_out_xbar_auto_anon_out_2_a_bits_opcode),
.auto_anon_out_2_a_bits_param (_out_xbar_auto_anon_out_2_a_bits_param),
.auto_anon_out_2_a_bits_size (_out_xbar_auto_anon_out_2_a_bits_size),
.auto_anon_out_2_a_bits_source (_out_xbar_auto_anon_out_2_a_bits_source),
.auto_anon_out_2_a_bits_address (_out_xbar_auto_anon_out_2_a_bits_address),
.auto_anon_out_2_a_bits_mask (_out_xbar_auto_anon_out_2_a_bits_mask),
.auto_anon_out_2_a_bits_data (_out_xbar_auto_anon_out_2_a_bits_data),
.auto_anon_out_2_a_bits_corrupt (_out_xbar_auto_anon_out_2_a_bits_corrupt),
.auto_anon_out_2_d_ready (_out_xbar_auto_anon_out_2_d_ready),
.auto_anon_out_2_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_2_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_2_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_2_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_2_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_1_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid),
.auto_anon_out_1_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_1_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param),
.auto_anon_out_1_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size),
.auto_anon_out_1_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source),
.auto_anon_out_1_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address),
.auto_anon_out_1_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_1_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_1_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready),
.auto_anon_out_1_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[PeripheryBus.scala:57:30]
TLBuffer_a32d64s7k1z4u buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29]
.auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9]
.auto_out_a_valid (fixer_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (fixer_auto_anon_in_d_ready),
.auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_param (fixer_auto_anon_in_d_bits_param), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_sink (fixer_auto_anon_in_d_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_denied (fixer_auto_anon_in_d_bits_denied), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_corrupt (fixer_auto_anon_in_d_bits_corrupt) // @[FIFOFixer.scala:50:9]
); // @[Buffer.scala:75:28]
TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_atomics_auto_in_a_ready),
.auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29]
.auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29]
.auto_in_d_valid (_atomics_auto_in_d_valid),
.auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_atomics_auto_in_d_bits_param),
.auto_in_d_bits_size (_atomics_auto_in_d_bits_size),
.auto_in_d_bits_source (_atomics_auto_in_d_bits_source),
.auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied),
.auto_in_d_bits_data (_atomics_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_atomics_auto_out_a_valid),
.auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_atomics_auto_out_a_bits_param),
.auto_out_a_bits_size (_atomics_auto_out_a_bits_size),
.auto_out_a_bits_source (_atomics_auto_out_a_bits_source),
.auto_out_a_bits_address (_atomics_auto_out_a_bits_address),
.auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask),
.auto_out_a_bits_data (_atomics_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt),
.auto_out_d_ready (_atomics_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28]
); // @[AtomicAutomata.scala:289:29]
ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready),
.auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid),
.auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode),
.auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param),
.auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size),
.auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source),
.auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink),
.auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied),
.auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data),
.auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_2_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_2_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_2_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_2_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_2_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_2_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_2_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_2_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_2_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_2_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_sodor_tile coupler_to_sodor_tile ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_tl_slave_clock_xing_out_a_ready (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_a_valid (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid_0),
.auto_tl_slave_clock_xing_out_a_bits_opcode (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode_0),
.auto_tl_slave_clock_xing_out_a_bits_param (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param_0),
.auto_tl_slave_clock_xing_out_a_bits_size (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size_0),
.auto_tl_slave_clock_xing_out_a_bits_source (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source_0),
.auto_tl_slave_clock_xing_out_a_bits_address (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address_0),
.auto_tl_slave_clock_xing_out_a_bits_mask (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask_0),
.auto_tl_slave_clock_xing_out_a_bits_data (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data_0),
.auto_tl_slave_clock_xing_out_a_bits_corrupt (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt_0),
.auto_tl_slave_clock_xing_out_d_ready (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready_0),
.auto_tl_slave_clock_xing_out_d_valid (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_opcode (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_param (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_size (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_source (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_sink (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_denied (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_data (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_slave_clock_xing_out_d_bits_corrupt (auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_sodor_tile_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_sodor_tile_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_sodor_tile_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_param (_coupler_to_sodor_tile_auto_tl_in_d_bits_param),
.auto_tl_in_d_bits_size (_coupler_to_sodor_tile_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_sodor_tile_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_sink (_coupler_to_sodor_tile_auto_tl_in_d_bits_sink),
.auto_tl_in_d_bits_denied (_coupler_to_sodor_tile_auto_tl_in_d_bits_denied),
.auto_tl_in_d_bits_data (_coupler_to_sodor_tile_auto_tl_in_d_bits_data),
.auto_tl_in_d_bits_corrupt (_coupler_to_sodor_tile_auto_tl_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid),
.auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0),
.auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0),
.auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0),
.auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0),
.auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0),
.auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0),
.auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0),
.auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0),
.auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0),
.auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0),
.auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param),
.auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink),
.auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied),
.auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data),
.auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready = auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_113 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_123
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_113( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_123 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAToNoC_2 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst q of Queue1_TLBundleA_a32d64s6k5z4c_2
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node _head_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node head_beats1_opdata = eq(_head_beats1_opdata_T, UInt<1>(0h0))
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node _tail_beats1_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node tail_beats1_opdata = eq(_tail_beats1_opdata_T, UInt<1>(0h0))
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body_hi = cat(q.io.deq.bits.mask, q.io.deq.bits.data)
node body = cat(body_hi, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = xor(q.io.deq.bits.address, UInt<17>(0h10000))
node _io_flit_bits_egress_id_requestOH_T_6 = cvt(_io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_7 = and(_io_flit_bits_egress_id_requestOH_T_6, asSInt(UInt<33>(0h8c011000)))
node _io_flit_bits_egress_id_requestOH_T_8 = asSInt(_io_flit_bits_egress_id_requestOH_T_7)
node _io_flit_bits_egress_id_requestOH_T_9 = eq(_io_flit_bits_egress_id_requestOH_T_8, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_10 = xor(q.io.deq.bits.address, UInt<28>(0hc000000))
node _io_flit_bits_egress_id_requestOH_T_11 = cvt(_io_flit_bits_egress_id_requestOH_T_10)
node _io_flit_bits_egress_id_requestOH_T_12 = and(_io_flit_bits_egress_id_requestOH_T_11, asSInt(UInt<33>(0h8c000000)))
node _io_flit_bits_egress_id_requestOH_T_13 = asSInt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = eq(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_15 = or(_io_flit_bits_egress_id_requestOH_T_4, _io_flit_bits_egress_id_requestOH_T_9)
node _io_flit_bits_egress_id_requestOH_T_16 = or(_io_flit_bits_egress_id_requestOH_T_15, _io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<28>(0h8000000))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = xor(q.io.deq.bits.address, UInt<32>(0h80000000))
node _io_flit_bits_egress_id_requestOH_T_24 = cvt(_io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_25 = and(_io_flit_bits_egress_id_requestOH_T_24, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_26 = asSInt(_io_flit_bits_egress_id_requestOH_T_25)
node _io_flit_bits_egress_id_requestOH_T_27 = eq(_io_flit_bits_egress_id_requestOH_T_26, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_28 = or(_io_flit_bits_egress_id_requestOH_T_22, _io_flit_bits_egress_id_requestOH_T_27)
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_requestOH_T_30 = xor(q.io.deq.bits.address, UInt<28>(0h8000040))
node _io_flit_bits_egress_id_requestOH_T_31 = cvt(_io_flit_bits_egress_id_requestOH_T_30)
node _io_flit_bits_egress_id_requestOH_T_32 = and(_io_flit_bits_egress_id_requestOH_T_31, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_33 = asSInt(_io_flit_bits_egress_id_requestOH_T_32)
node _io_flit_bits_egress_id_requestOH_T_34 = eq(_io_flit_bits_egress_id_requestOH_T_33, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_35 = xor(q.io.deq.bits.address, UInt<32>(0h80000040))
node _io_flit_bits_egress_id_requestOH_T_36 = cvt(_io_flit_bits_egress_id_requestOH_T_35)
node _io_flit_bits_egress_id_requestOH_T_37 = and(_io_flit_bits_egress_id_requestOH_T_36, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_38 = asSInt(_io_flit_bits_egress_id_requestOH_T_37)
node _io_flit_bits_egress_id_requestOH_T_39 = eq(_io_flit_bits_egress_id_requestOH_T_38, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_40 = or(_io_flit_bits_egress_id_requestOH_T_34, _io_flit_bits_egress_id_requestOH_T_39)
node _io_flit_bits_egress_id_requestOH_T_41 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_40)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_41)
node _io_flit_bits_egress_id_requestOH_T_42 = xor(q.io.deq.bits.address, UInt<28>(0h8000080))
node _io_flit_bits_egress_id_requestOH_T_43 = cvt(_io_flit_bits_egress_id_requestOH_T_42)
node _io_flit_bits_egress_id_requestOH_T_44 = and(_io_flit_bits_egress_id_requestOH_T_43, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_45 = asSInt(_io_flit_bits_egress_id_requestOH_T_44)
node _io_flit_bits_egress_id_requestOH_T_46 = eq(_io_flit_bits_egress_id_requestOH_T_45, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_47 = xor(q.io.deq.bits.address, UInt<32>(0h80000080))
node _io_flit_bits_egress_id_requestOH_T_48 = cvt(_io_flit_bits_egress_id_requestOH_T_47)
node _io_flit_bits_egress_id_requestOH_T_49 = and(_io_flit_bits_egress_id_requestOH_T_48, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_50 = asSInt(_io_flit_bits_egress_id_requestOH_T_49)
node _io_flit_bits_egress_id_requestOH_T_51 = eq(_io_flit_bits_egress_id_requestOH_T_50, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_52 = or(_io_flit_bits_egress_id_requestOH_T_46, _io_flit_bits_egress_id_requestOH_T_51)
node _io_flit_bits_egress_id_requestOH_T_53 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_52)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_53)
node _io_flit_bits_egress_id_requestOH_T_54 = xor(q.io.deq.bits.address, UInt<28>(0h80000c0))
node _io_flit_bits_egress_id_requestOH_T_55 = cvt(_io_flit_bits_egress_id_requestOH_T_54)
node _io_flit_bits_egress_id_requestOH_T_56 = and(_io_flit_bits_egress_id_requestOH_T_55, asSInt(UInt<33>(0h8c0100c0)))
node _io_flit_bits_egress_id_requestOH_T_57 = asSInt(_io_flit_bits_egress_id_requestOH_T_56)
node _io_flit_bits_egress_id_requestOH_T_58 = eq(_io_flit_bits_egress_id_requestOH_T_57, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_59 = xor(q.io.deq.bits.address, UInt<32>(0h800000c0))
node _io_flit_bits_egress_id_requestOH_T_60 = cvt(_io_flit_bits_egress_id_requestOH_T_59)
node _io_flit_bits_egress_id_requestOH_T_61 = and(_io_flit_bits_egress_id_requestOH_T_60, asSInt(UInt<33>(0h800000c0)))
node _io_flit_bits_egress_id_requestOH_T_62 = asSInt(_io_flit_bits_egress_id_requestOH_T_61)
node _io_flit_bits_egress_id_requestOH_T_63 = eq(_io_flit_bits_egress_id_requestOH_T_62, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_64 = or(_io_flit_bits_egress_id_requestOH_T_58, _io_flit_bits_egress_id_requestOH_T_63)
node _io_flit_bits_egress_id_requestOH_T_65 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_64)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_65)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0ha), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0hd), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h10), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h13), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node _has_body_opdata_T = bits(q.io.deq.bits.opcode, 2, 2)
node has_body_opdata = eq(_has_body_opdata_T, UInt<1>(0h0))
node _has_body_T = not(q.io.deq.bits.mask)
node _has_body_T_1 = neq(_has_body_T, UInt<1>(0h0))
node _has_body_T_2 = or(has_body_opdata, _has_body_T_1)
connect has_body, _has_body_T_2
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<6>(0h28))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLAToNoC_2( // @[TilelinkAdapters.scala:112:7]
input clock, // @[TilelinkAdapters.scala:112:7]
input reset, // @[TilelinkAdapters.scala:112:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [7:0] io_protocol_bits_mask, // @[TilelinkAdapters.scala:19:14]
input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [72:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire [8:0] _GEN; // @[TilelinkAdapters.scala:119:{45,69}]
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [7:0] _q_io_deq_bits_mask; // @[TilelinkAdapters.scala:26:17]
wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3]); // @[package.scala:243:{46,71,76}]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire _io_flit_bits_tail_T = _GEN == 9'h0; // @[TilelinkAdapters.scala:119:{45,69}]
wire q_io_deq_ready = io_flit_ready & (is_body | _io_flit_bits_tail_T); // @[TilelinkAdapters.scala:39:24, :41:{35,47}, :119:{45,69}]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 9'h1 | tail_beats1 == 9'h0) & (is_body | _io_flit_bits_tail_T); // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [21:0] _GEN_0 = _q_io_deq_bits_address[27:6] ^ 22'h200001; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_35 = _q_io_deq_bits_address[31:6] ^ 26'h2000001; // @[Parameters.scala:137:31]
wire [21:0] _GEN_1 = _q_io_deq_bits_address[27:6] ^ 22'h200002; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_47 = _q_io_deq_bits_address[31:6] ^ 26'h2000002; // @[Parameters.scala:137:31]
wire [21:0] _GEN_2 = _q_io_deq_bits_address[27:6] ^ 22'h200003; // @[Parameters.scala:137:31]
wire [25:0] _io_flit_bits_egress_id_requestOH_T_59 = _q_io_deq_bits_address[31:6] ^ 26'h2000003; // @[Parameters.scala:137:31]
assign _GEN = {~(_q_io_deq_bits_opcode[2]), ~_q_io_deq_bits_mask}; // @[Edges.scala:92:{28,37}]
wire _GEN_3 = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:112:7]
if (reset) begin // @[TilelinkAdapters.scala:112:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :112:7]
end
else begin // @[TilelinkAdapters.scala:112:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[2] ? 9'h0 : ~(_tail_beats1_decode_T[11:3])) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN_3 & io_flit_bits_tail_0) & (_GEN_3 & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_42 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_42
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_42
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h17))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_9 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_13 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_14 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_15 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_16 :
connect states[7].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_30 = and(io.router_req.ready, io.router_req.valid)
when _T_30 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_32 = or(_T_31, vcalloc_vals[2])
node _T_33 = or(_T_32, vcalloc_vals[3])
node _T_34 = or(_T_33, vcalloc_vals[4])
node _T_35 = or(_T_34, vcalloc_vals[5])
node _T_36 = or(_T_35, vcalloc_vals[6])
node _T_37 = or(_T_36, vcalloc_vals[7])
when _T_37 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_38 = bits(vcalloc_sel, 0, 0)
node _T_39 = and(vcalloc_vals[0], _T_38)
node _T_40 = and(_T_39, io.vcalloc_req.ready)
when _T_40 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_41 = bits(vcalloc_sel, 1, 1)
node _T_42 = and(vcalloc_vals[1], _T_41)
node _T_43 = and(_T_42, io.vcalloc_req.ready)
when _T_43 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_44 = bits(vcalloc_sel, 2, 2)
node _T_45 = and(vcalloc_vals[2], _T_44)
node _T_46 = and(_T_45, io.vcalloc_req.ready)
when _T_46 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_47 = bits(vcalloc_sel, 3, 3)
node _T_48 = and(vcalloc_vals[3], _T_47)
node _T_49 = and(_T_48, io.vcalloc_req.ready)
when _T_49 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_50 = bits(vcalloc_sel, 4, 4)
node _T_51 = and(vcalloc_vals[4], _T_50)
node _T_52 = and(_T_51, io.vcalloc_req.ready)
when _T_52 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_53 = bits(vcalloc_sel, 5, 5)
node _T_54 = and(vcalloc_vals[5], _T_53)
node _T_55 = and(_T_54, io.vcalloc_req.ready)
when _T_55 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_56 = bits(vcalloc_sel, 6, 6)
node _T_57 = and(vcalloc_vals[6], _T_56)
node _T_58 = and(_T_57, io.vcalloc_req.ready)
when _T_58 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_59 = bits(vcalloc_sel, 7, 7)
node _T_60 = and(vcalloc_vals[7], _T_59)
node _T_61 = and(_T_60, io.vcalloc_req.ready)
when _T_61 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_62 :
node _T_63 = bits(vcalloc_sel, 0, 0)
when _T_63 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_64 = eq(states[0].g, UInt<3>(0h2))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _T_68 = bits(vcalloc_sel, 1, 1)
when _T_68 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_69 = eq(states[1].g, UInt<3>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_69, UInt<1>(0h1), "") : assert_4
node _T_73 = bits(vcalloc_sel, 2, 2)
when _T_73 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_74 = eq(states[2].g, UInt<3>(0h2))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = bits(vcalloc_sel, 3, 3)
when _T_78 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_79 = eq(states[3].g, UInt<3>(0h2))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = bits(vcalloc_sel, 4, 4)
when _T_83 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_84 = eq(states[4].g, UInt<3>(0h2))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_84, UInt<1>(0h1), "") : assert_7
node _T_88 = bits(vcalloc_sel, 5, 5)
when _T_88 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_89 = eq(states[5].g, UInt<3>(0h2))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_89, UInt<1>(0h1), "") : assert_8
node _T_93 = bits(vcalloc_sel, 6, 6)
when _T_93 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_94 = eq(states[6].g, UInt<3>(0h2))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = bits(vcalloc_sel, 7, 7)
when _T_98 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_99 = eq(states[7].g, UInt<3>(0h2))
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_117
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail)
when _T_104 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail)
when _T_106 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail)
when _T_108 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail)
when _T_110 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail)
when _T_112 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail)
when _T_114 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail)
when _T_116 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56)
node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56)
node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70)
node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57)
node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57)
node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71)
node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58)
node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58)
node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72)
node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59)
node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59)
node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73)
node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77)
node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79)
node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74)
node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60)
node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60)
node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75)
node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61)
node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61)
node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76)
node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62)
node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62)
node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77)
node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63)
node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63)
node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78)
node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82)
node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84)
node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79)
node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86)
node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail)
when _T_118 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_119 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[0].vc_sel.`0`[4], UInt<1>(0h0)
connect states[0].vc_sel.`0`[5], UInt<1>(0h0)
connect states[0].vc_sel.`0`[6], UInt<1>(0h0)
connect states[0].vc_sel.`0`[7], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[2], UInt<1>(0h0)
connect states[0].vc_sel.`1`[3], UInt<1>(0h0)
connect states[0].vc_sel.`1`[4], UInt<1>(0h0)
connect states[0].vc_sel.`1`[5], UInt<1>(0h0)
connect states[0].vc_sel.`1`[6], UInt<1>(0h0)
connect states[0].vc_sel.`1`[7], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[1].vc_sel.`0`[6], UInt<1>(0h0)
connect states[1].vc_sel.`0`[7], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
node _T_120 = asUInt(reset)
when _T_120 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_42( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_13 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = or(_T_100, _T_105)
node _T_137 = or(_T_136, _T_110)
node _T_138 = or(_T_137, _T_115)
node _T_139 = or(_T_138, _T_120)
node _T_140 = or(_T_139, _T_125)
node _T_141 = or(_T_140, _T_130)
node _T_142 = or(_T_141, _T_135)
node _T_143 = and(_T_95, _T_142)
node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_150, _T_155)
node _T_157 = and(_T_145, _T_156)
node _T_158 = or(UInt<1>(0h0), _T_143)
node _T_159 = or(_T_158, _T_157)
node _T_160 = and(_T_94, _T_159)
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_160, UInt<1>(0h1), "") : assert_2
node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_166 = and(_T_164, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = or(_T_172, _T_177)
node _T_219 = or(_T_218, _T_182)
node _T_220 = or(_T_219, _T_187)
node _T_221 = or(_T_220, _T_192)
node _T_222 = or(_T_221, _T_197)
node _T_223 = or(_T_222, _T_202)
node _T_224 = or(_T_223, _T_207)
node _T_225 = or(_T_224, _T_212)
node _T_226 = or(_T_225, _T_217)
node _T_227 = and(_T_167, _T_226)
node _T_228 = or(UInt<1>(0h0), _T_227)
node _T_229 = and(UInt<1>(0h0), _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_229, UInt<1>(0h1), "") : assert_3
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(source_ok, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_236, UInt<1>(0h1), "") : assert_5
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(is_aligned, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_243, UInt<1>(0h1), "") : assert_7
node _T_247 = not(io.in.a.bits.mask)
node _T_248 = eq(_T_247, UInt<1>(0h0))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_248, UInt<1>(0h1), "") : assert_8
node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_252, UInt<1>(0h1), "") : assert_9
node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_256 :
node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h1))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<2>(0h2))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h3))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _T_284 = or(_T_265, _T_271)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_283)
node _T_287 = and(_T_259, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_287)
node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = or(_T_294, _T_299)
node _T_331 = or(_T_330, _T_304)
node _T_332 = or(_T_331, _T_309)
node _T_333 = or(_T_332, _T_314)
node _T_334 = or(_T_333, _T_319)
node _T_335 = or(_T_334, _T_324)
node _T_336 = or(_T_335, _T_329)
node _T_337 = and(_T_289, _T_336)
node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = or(_T_344, _T_349)
node _T_351 = and(_T_339, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_337)
node _T_353 = or(_T_352, _T_351)
node _T_354 = and(_T_288, _T_353)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_354, UInt<1>(0h1), "") : assert_10
node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_388 = cvt(_T_387)
node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000)))
node _T_390 = asSInt(_T_389)
node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0)))
node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_393 = cvt(_T_392)
node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000)))
node _T_395 = asSInt(_T_394)
node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0)))
node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_398 = cvt(_T_397)
node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000)))
node _T_400 = asSInt(_T_399)
node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0)))
node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = or(_T_366, _T_371)
node _T_413 = or(_T_412, _T_376)
node _T_414 = or(_T_413, _T_381)
node _T_415 = or(_T_414, _T_386)
node _T_416 = or(_T_415, _T_391)
node _T_417 = or(_T_416, _T_396)
node _T_418 = or(_T_417, _T_401)
node _T_419 = or(_T_418, _T_406)
node _T_420 = or(_T_419, _T_411)
node _T_421 = and(_T_361, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = and(UInt<1>(0h0), _T_422)
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_423, UInt<1>(0h1), "") : assert_11
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(source_ok, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_430, UInt<1>(0h1), "") : assert_13
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(is_aligned, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_437, UInt<1>(0h1), "") : assert_15
node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_441, UInt<1>(0h1), "") : assert_16
node _T_445 = not(io.in.a.bits.mask)
node _T_446 = eq(_T_445, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_446, UInt<1>(0h1), "") : assert_17
node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_450, UInt<1>(0h1), "") : assert_18
node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_454 :
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_458 = shr(io.in.a.bits.source, 2)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_461 = and(_T_459, _T_460)
node _T_462 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_463 = and(_T_461, _T_462)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_464 = shr(io.in.a.bits.source, 2)
node _T_465 = eq(_T_464, UInt<1>(0h1))
node _T_466 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_467 = and(_T_465, _T_466)
node _T_468 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_469 = and(_T_467, _T_468)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_470 = shr(io.in.a.bits.source, 2)
node _T_471 = eq(_T_470, UInt<2>(0h2))
node _T_472 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_473 = and(_T_471, _T_472)
node _T_474 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_475 = and(_T_473, _T_474)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_476 = shr(io.in.a.bits.source, 2)
node _T_477 = eq(_T_476, UInt<2>(0h3))
node _T_478 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_479 = and(_T_477, _T_478)
node _T_480 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_481 = and(_T_479, _T_480)
node _T_482 = or(_T_463, _T_469)
node _T_483 = or(_T_482, _T_475)
node _T_484 = or(_T_483, _T_481)
node _T_485 = and(_T_457, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_486, UInt<1>(0h1), "") : assert_19
node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_492 = and(_T_490, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = and(_T_493, _T_498)
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = or(_T_508, _T_513)
node _T_550 = or(_T_549, _T_518)
node _T_551 = or(_T_550, _T_523)
node _T_552 = or(_T_551, _T_528)
node _T_553 = or(_T_552, _T_533)
node _T_554 = or(_T_553, _T_538)
node _T_555 = or(_T_554, _T_543)
node _T_556 = or(_T_555, _T_548)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_499)
node _T_559 = or(_T_558, _T_557)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_559, UInt<1>(0h1), "") : assert_20
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(source_ok, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(is_aligned, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_569, UInt<1>(0h1), "") : assert_23
node _T_573 = eq(io.in.a.bits.mask, mask)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_573, UInt<1>(0h1), "") : assert_24
node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_577, UInt<1>(0h1), "") : assert_25
node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_581 :
node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<2>(0h2))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<2>(0h3))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(_T_590, _T_596)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_608)
node _T_612 = and(_T_584, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = and(_T_617, _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_649 = cvt(_T_648)
node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000)))
node _T_651 = asSInt(_T_650)
node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0)))
node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = or(_T_632, _T_637)
node _T_669 = or(_T_668, _T_642)
node _T_670 = or(_T_669, _T_647)
node _T_671 = or(_T_670, _T_652)
node _T_672 = or(_T_671, _T_657)
node _T_673 = or(_T_672, _T_662)
node _T_674 = or(_T_673, _T_667)
node _T_675 = and(_T_627, _T_674)
node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_678 = cvt(_T_677)
node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000)))
node _T_680 = asSInt(_T_679)
node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0)))
node _T_682 = and(_T_676, _T_681)
node _T_683 = or(UInt<1>(0h0), _T_623)
node _T_684 = or(_T_683, _T_675)
node _T_685 = or(_T_684, _T_682)
node _T_686 = and(_T_613, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_686, UInt<1>(0h1), "") : assert_26
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(source_ok, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(is_aligned, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_696, UInt<1>(0h1), "") : assert_29
node _T_700 = eq(io.in.a.bits.mask, mask)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_700, UInt<1>(0h1), "") : assert_30
node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_704 :
node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_707 = and(_T_705, _T_706)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_708 = shr(io.in.a.bits.source, 2)
node _T_709 = eq(_T_708, UInt<1>(0h0))
node _T_710 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_711 = and(_T_709, _T_710)
node _T_712 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_713 = and(_T_711, _T_712)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_714 = shr(io.in.a.bits.source, 2)
node _T_715 = eq(_T_714, UInt<1>(0h1))
node _T_716 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_717 = and(_T_715, _T_716)
node _T_718 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_719 = and(_T_717, _T_718)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_720 = shr(io.in.a.bits.source, 2)
node _T_721 = eq(_T_720, UInt<2>(0h2))
node _T_722 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_723 = and(_T_721, _T_722)
node _T_724 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_725 = and(_T_723, _T_724)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_726 = shr(io.in.a.bits.source, 2)
node _T_727 = eq(_T_726, UInt<2>(0h3))
node _T_728 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_729 = and(_T_727, _T_728)
node _T_730 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(_T_713, _T_719)
node _T_733 = or(_T_732, _T_725)
node _T_734 = or(_T_733, _T_731)
node _T_735 = and(_T_707, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = and(_T_740, _T_745)
node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_772 = cvt(_T_771)
node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000)))
node _T_774 = asSInt(_T_773)
node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0)))
node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_787 = cvt(_T_786)
node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000)))
node _T_789 = asSInt(_T_788)
node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0)))
node _T_791 = or(_T_755, _T_760)
node _T_792 = or(_T_791, _T_765)
node _T_793 = or(_T_792, _T_770)
node _T_794 = or(_T_793, _T_775)
node _T_795 = or(_T_794, _T_780)
node _T_796 = or(_T_795, _T_785)
node _T_797 = or(_T_796, _T_790)
node _T_798 = and(_T_750, _T_797)
node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = and(_T_799, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_746)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_805)
node _T_809 = and(_T_736, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_809, UInt<1>(0h1), "") : assert_31
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_819, UInt<1>(0h1), "") : assert_34
node _T_823 = not(mask)
node _T_824 = and(io.in.a.bits.mask, _T_823)
node _T_825 = eq(_T_824, UInt<1>(0h0))
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_T_825, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_825, UInt<1>(0h1), "") : assert_35
node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_829 :
node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_832 = and(_T_830, _T_831)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<1>(0h1))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<2>(0h2))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<2>(0h3))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = or(_T_838, _T_844)
node _T_858 = or(_T_857, _T_850)
node _T_859 = or(_T_858, _T_856)
node _T_860 = and(_T_832, _T_859)
node _T_861 = or(UInt<1>(0h0), _T_860)
node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _T_865 = or(UInt<1>(0h0), _T_864)
node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_882 = cvt(_T_881)
node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000)))
node _T_884 = asSInt(_T_883)
node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0)))
node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<17>(0h10000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<27>(0h4000000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<29>(0h10000000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = or(_T_870, _T_875)
node _T_912 = or(_T_911, _T_880)
node _T_913 = or(_T_912, _T_885)
node _T_914 = or(_T_913, _T_890)
node _T_915 = or(_T_914, _T_895)
node _T_916 = or(_T_915, _T_900)
node _T_917 = or(_T_916, _T_905)
node _T_918 = or(_T_917, _T_910)
node _T_919 = and(_T_865, _T_918)
node _T_920 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_921 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = and(_T_920, _T_925)
node _T_927 = or(UInt<1>(0h0), _T_919)
node _T_928 = or(_T_927, _T_926)
node _T_929 = and(_T_861, _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_929, UInt<1>(0h1), "") : assert_36
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(source_ok, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(is_aligned, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_939 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_939, UInt<1>(0h1), "") : assert_39
node _T_943 = eq(io.in.a.bits.mask, mask)
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_943, UInt<1>(0h1), "") : assert_40
node _T_947 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_947 :
node _T_948 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_949 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_951 = shr(io.in.a.bits.source, 2)
node _T_952 = eq(_T_951, UInt<1>(0h0))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_956 = and(_T_954, _T_955)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_957 = shr(io.in.a.bits.source, 2)
node _T_958 = eq(_T_957, UInt<1>(0h1))
node _T_959 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_960 = and(_T_958, _T_959)
node _T_961 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_962 = and(_T_960, _T_961)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_963 = shr(io.in.a.bits.source, 2)
node _T_964 = eq(_T_963, UInt<2>(0h2))
node _T_965 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_966 = and(_T_964, _T_965)
node _T_967 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_968 = and(_T_966, _T_967)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_969 = shr(io.in.a.bits.source, 2)
node _T_970 = eq(_T_969, UInt<2>(0h3))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_974 = and(_T_972, _T_973)
node _T_975 = or(_T_956, _T_962)
node _T_976 = or(_T_975, _T_968)
node _T_977 = or(_T_976, _T_974)
node _T_978 = and(_T_950, _T_977)
node _T_979 = or(UInt<1>(0h0), _T_978)
node _T_980 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_981 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_982 = and(_T_980, _T_981)
node _T_983 = or(UInt<1>(0h0), _T_982)
node _T_984 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<14>(0h2000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<13>(0h1000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<18>(0h2f000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<17>(0h10000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<17>(0h10000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1025 = cvt(_T_1024)
node _T_1026 = and(_T_1025, asSInt(UInt<29>(0h10000000)))
node _T_1027 = asSInt(_T_1026)
node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0)))
node _T_1029 = or(_T_988, _T_993)
node _T_1030 = or(_T_1029, _T_998)
node _T_1031 = or(_T_1030, _T_1003)
node _T_1032 = or(_T_1031, _T_1008)
node _T_1033 = or(_T_1032, _T_1013)
node _T_1034 = or(_T_1033, _T_1018)
node _T_1035 = or(_T_1034, _T_1023)
node _T_1036 = or(_T_1035, _T_1028)
node _T_1037 = and(_T_983, _T_1036)
node _T_1038 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1039 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1040 = cvt(_T_1039)
node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000)))
node _T_1042 = asSInt(_T_1041)
node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0)))
node _T_1044 = and(_T_1038, _T_1043)
node _T_1045 = or(UInt<1>(0h0), _T_1037)
node _T_1046 = or(_T_1045, _T_1044)
node _T_1047 = and(_T_979, _T_1046)
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(_T_1047, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1047, UInt<1>(0h1), "") : assert_41
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(is_aligned, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1057 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_44
node _T_1061 = eq(io.in.a.bits.mask, mask)
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_45
node _T_1065 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1065 :
node _T_1066 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1067 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1068 = and(_T_1066, _T_1067)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1069 = shr(io.in.a.bits.source, 2)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
node _T_1071 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1074 = and(_T_1072, _T_1073)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1075 = shr(io.in.a.bits.source, 2)
node _T_1076 = eq(_T_1075, UInt<1>(0h1))
node _T_1077 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1080 = and(_T_1078, _T_1079)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1081 = shr(io.in.a.bits.source, 2)
node _T_1082 = eq(_T_1081, UInt<2>(0h2))
node _T_1083 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1086 = and(_T_1084, _T_1085)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1087 = shr(io.in.a.bits.source, 2)
node _T_1088 = eq(_T_1087, UInt<2>(0h3))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = or(_T_1074, _T_1080)
node _T_1094 = or(_T_1093, _T_1086)
node _T_1095 = or(_T_1094, _T_1092)
node _T_1096 = and(_T_1068, _T_1095)
node _T_1097 = or(UInt<1>(0h0), _T_1096)
node _T_1098 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1099 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = or(UInt<1>(0h0), _T_1100)
node _T_1102 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1103 = cvt(_T_1102)
node _T_1104 = and(_T_1103, asSInt(UInt<13>(0h1000)))
node _T_1105 = asSInt(_T_1104)
node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0)))
node _T_1107 = and(_T_1101, _T_1106)
node _T_1108 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1110 = cvt(_T_1109)
node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000)))
node _T_1112 = asSInt(_T_1111)
node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0)))
node _T_1114 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1115 = cvt(_T_1114)
node _T_1116 = and(_T_1115, asSInt(UInt<17>(0h10000)))
node _T_1117 = asSInt(_T_1116)
node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0)))
node _T_1119 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<18>(0h2f000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<13>(0h1000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<27>(0h4000000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = or(_T_1113, _T_1118)
node _T_1145 = or(_T_1144, _T_1123)
node _T_1146 = or(_T_1145, _T_1128)
node _T_1147 = or(_T_1146, _T_1133)
node _T_1148 = or(_T_1147, _T_1138)
node _T_1149 = or(_T_1148, _T_1143)
node _T_1150 = and(_T_1108, _T_1149)
node _T_1151 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1152 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = or(UInt<1>(0h0), _T_1153)
node _T_1155 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1156 = cvt(_T_1155)
node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000)))
node _T_1158 = asSInt(_T_1157)
node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0)))
node _T_1160 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1161 = cvt(_T_1160)
node _T_1162 = and(_T_1161, asSInt(UInt<29>(0h10000000)))
node _T_1163 = asSInt(_T_1162)
node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0)))
node _T_1165 = or(_T_1159, _T_1164)
node _T_1166 = and(_T_1154, _T_1165)
node _T_1167 = or(UInt<1>(0h0), _T_1107)
node _T_1168 = or(_T_1167, _T_1150)
node _T_1169 = or(_T_1168, _T_1166)
node _T_1170 = and(_T_1097, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_46
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1180 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_49
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_50
node _T_1188 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1192 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_1196 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1196 :
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(source_ok_1, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1200 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1201 = asUInt(reset)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
when _T_1202 :
node _T_1203 = eq(_T_1200, UInt<1>(0h0))
when _T_1203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1200, UInt<1>(0h1), "") : assert_54
node _T_1204 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_55
node _T_1208 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_56
node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_57
node _T_1216 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1216 :
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(source_ok_1, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(sink_ok, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1223 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_60
node _T_1227 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_61
node _T_1231 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_62
node _T_1235 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_63
node _T_1239 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1240 = or(UInt<1>(0h1), _T_1239)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_64
node _T_1244 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1244 :
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(source_ok_1, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(sink_ok, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1251 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_67
node _T_1255 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_68
node _T_1259 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_69
node _T_1263 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1264 = or(_T_1263, io.in.d.bits.corrupt)
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_70
node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1269 = or(UInt<1>(0h1), _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_71
node _T_1273 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1273 :
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(source_ok_1, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1277 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_73
node _T_1281 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(_T_1281, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1281, UInt<1>(0h1), "") : assert_74
node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1286 = or(UInt<1>(0h1), _T_1285)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_75
node _T_1290 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1290 :
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(source_ok_1, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1294 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_77
node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1299 = or(_T_1298, io.in.d.bits.corrupt)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_78
node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1304 = or(UInt<1>(0h1), _T_1303)
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_79
node _T_1308 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1308 :
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(source_ok_1, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_81
node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_82
node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1321 = or(UInt<1>(0h1), _T_1320)
node _T_1322 = asUInt(reset)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
when _T_1323 :
node _T_1324 = eq(_T_1321, UInt<1>(0h0))
when _T_1324 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1321, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1325 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1329 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1330 = asUInt(reset)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
when _T_1331 :
node _T_1332 = eq(_T_1329, UInt<1>(0h0))
when _T_1332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1329, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1333 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1337 = eq(a_first, UInt<1>(0h0))
node _T_1338 = and(io.in.a.valid, _T_1337)
when _T_1338 :
node _T_1339 = eq(io.in.a.bits.opcode, opcode)
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_87
node _T_1343 = eq(io.in.a.bits.param, param)
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_88
node _T_1347 = eq(io.in.a.bits.size, size)
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_89
node _T_1351 = eq(io.in.a.bits.source, source)
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_90
node _T_1355 = eq(io.in.a.bits.address, address)
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_91
node _T_1359 = and(io.in.a.ready, io.in.a.valid)
node _T_1360 = and(_T_1359, a_first)
when _T_1360 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1361 = eq(d_first, UInt<1>(0h0))
node _T_1362 = and(io.in.d.valid, _T_1361)
when _T_1362 :
node _T_1363 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1364 = asUInt(reset)
node _T_1365 = eq(_T_1364, UInt<1>(0h0))
when _T_1365 :
node _T_1366 = eq(_T_1363, UInt<1>(0h0))
when _T_1366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1363, UInt<1>(0h1), "") : assert_92
node _T_1367 = eq(io.in.d.bits.param, param_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_93
node _T_1371 = eq(io.in.d.bits.size, size_1)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_94
node _T_1375 = eq(io.in.d.bits.source, source_1)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_95
node _T_1379 = eq(io.in.d.bits.sink, sink)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_96
node _T_1383 = eq(io.in.d.bits.denied, denied)
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_97
node _T_1387 = and(io.in.d.ready, io.in.d.valid)
node _T_1388 = and(_T_1387, d_first)
when _T_1388 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1389 = and(io.in.a.valid, a_first_1)
node _T_1390 = and(_T_1389, UInt<1>(0h1))
when _T_1390 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1391 = and(io.in.a.ready, io.in.a.valid)
node _T_1392 = and(_T_1391, a_first_1)
node _T_1393 = and(_T_1392, UInt<1>(0h1))
when _T_1393 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1394 = dshr(inflight, io.in.a.bits.source)
node _T_1395 = bits(_T_1394, 0, 0)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1400 = and(io.in.d.valid, d_first_1)
node _T_1401 = and(_T_1400, UInt<1>(0h1))
node _T_1402 = eq(d_release_ack, UInt<1>(0h0))
node _T_1403 = and(_T_1401, _T_1402)
when _T_1403 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1404 = and(io.in.d.ready, io.in.d.valid)
node _T_1405 = and(_T_1404, d_first_1)
node _T_1406 = and(_T_1405, UInt<1>(0h1))
node _T_1407 = eq(d_release_ack, UInt<1>(0h0))
node _T_1408 = and(_T_1406, _T_1407)
when _T_1408 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1409 = and(io.in.d.valid, d_first_1)
node _T_1410 = and(_T_1409, UInt<1>(0h1))
node _T_1411 = eq(d_release_ack, UInt<1>(0h0))
node _T_1412 = and(_T_1410, _T_1411)
when _T_1412 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1413 = dshr(inflight, io.in.d.bits.source)
node _T_1414 = bits(_T_1413, 0, 0)
node _T_1415 = or(_T_1414, same_cycle_resp)
node _T_1416 = asUInt(reset)
node _T_1417 = eq(_T_1416, UInt<1>(0h0))
when _T_1417 :
node _T_1418 = eq(_T_1415, UInt<1>(0h0))
when _T_1418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1415, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1419 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1420 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1421 = or(_T_1419, _T_1420)
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_100
node _T_1425 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_101
else :
node _T_1429 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1431 = or(_T_1429, _T_1430)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_102
node _T_1435 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_103
node _T_1439 = and(io.in.d.valid, d_first_1)
node _T_1440 = and(_T_1439, a_first_1)
node _T_1441 = and(_T_1440, io.in.a.valid)
node _T_1442 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1443 = and(_T_1441, _T_1442)
node _T_1444 = eq(d_release_ack, UInt<1>(0h0))
node _T_1445 = and(_T_1443, _T_1444)
when _T_1445 :
node _T_1446 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1447 = or(_T_1446, io.in.a.ready)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_104
node _T_1451 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1452 = orr(a_set_wo_ready)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
node _T_1454 = or(_T_1451, _T_1453)
node _T_1455 = asUInt(reset)
node _T_1456 = eq(_T_1455, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = eq(_T_1454, UInt<1>(0h0))
when _T_1457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1454, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_35
node _T_1458 = orr(inflight)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
node _T_1460 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1461 = or(_T_1459, _T_1460)
node _T_1462 = lt(watchdog, plusarg_reader.out)
node _T_1463 = or(_T_1461, _T_1462)
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1467 = and(io.in.a.ready, io.in.a.valid)
node _T_1468 = and(io.in.d.ready, io.in.d.valid)
node _T_1469 = or(_T_1467, _T_1468)
when _T_1469 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1470 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1471 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1472 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1473 = and(_T_1471, _T_1472)
node _T_1474 = and(_T_1470, _T_1473)
when _T_1474 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1475 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1476 = and(_T_1475, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1477 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1478 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1479 = and(_T_1477, _T_1478)
node _T_1480 = and(_T_1476, _T_1479)
when _T_1480 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1481 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1482 = bits(_T_1481, 0, 0)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1487 = and(io.in.d.valid, d_first_2)
node _T_1488 = and(_T_1487, UInt<1>(0h1))
node _T_1489 = and(_T_1488, d_release_ack_1)
when _T_1489 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1490 = and(io.in.d.ready, io.in.d.valid)
node _T_1491 = and(_T_1490, d_first_2)
node _T_1492 = and(_T_1491, UInt<1>(0h1))
node _T_1493 = and(_T_1492, d_release_ack_1)
when _T_1493 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1494 = and(io.in.d.valid, d_first_2)
node _T_1495 = and(_T_1494, UInt<1>(0h1))
node _T_1496 = and(_T_1495, d_release_ack_1)
when _T_1496 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1497 = dshr(inflight_1, io.in.d.bits.source)
node _T_1498 = bits(_T_1497, 0, 0)
node _T_1499 = or(_T_1498, same_cycle_resp_1)
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1503 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_109
else :
node _T_1507 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_110
node _T_1511 = and(io.in.d.valid, d_first_2)
node _T_1512 = and(_T_1511, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1513 = and(_T_1512, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1514 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1515 = and(_T_1513, _T_1514)
node _T_1516 = and(_T_1515, d_release_ack_1)
node _T_1517 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1518 = and(_T_1516, _T_1517)
when _T_1518 :
node _T_1519 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1520 = or(_T_1519, _WIRE_23.ready)
node _T_1521 = asUInt(reset)
node _T_1522 = eq(_T_1521, UInt<1>(0h0))
when _T_1522 :
node _T_1523 = eq(_T_1520, UInt<1>(0h0))
when _T_1523 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1520, UInt<1>(0h1), "") : assert_111
node _T_1524 = orr(c_set_wo_ready)
when _T_1524 :
node _T_1525 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_36
node _T_1529 = orr(inflight_1)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
node _T_1531 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1532 = or(_T_1530, _T_1531)
node _T_1533 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1534 = or(_T_1532, _T_1533)
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1538 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1539 = and(io.in.d.ready, io.in.d.valid)
node _T_1540 = or(_T_1538, _T_1539)
when _T_1540 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_13( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_CLINT :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_41
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0)
reg dOrig : UInt, clock
regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0)
node dFragnum = bits(anonOut.d.bits.source, 2, 0)
node dFirst = eq(acknum, UInt<1>(0h0))
node dLast = eq(dFragnum, UInt<1>(0h0))
node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0)
node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount)
node dsizeOH = bits(_dsizeOH_T, 3, 0)
node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size)
node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0)
node dsizeOH1 = not(_dsizeOH1_T_1)
node dHasData = bits(anonOut.d.bits.opcode, 0, 0)
node acknum_fragment = shl(dFragnum, 0)
node acknum_size = shr(dsizeOH1, 3)
node _T = eq(anonOut.d.valid, UInt<1>(0h0))
node _T_1 = and(acknum_fragment, acknum_size)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = or(_T, _T_2)
node _T_4 = asUInt(reset)
node _T_5 = eq(_T_4, UInt<1>(0h0))
when _T_5 :
node _T_6 = eq(_T_3, UInt<1>(0h0))
when _T_6 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf
assert(clock, _T_3, UInt<1>(0h1), "") : assert
node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0))
node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T)
node _ack_decrement_T = shr(dsizeOH, 3)
node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T)
node _dFirst_size_T = shl(dFragnum, 3)
node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1)
node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1)
node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1))
node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1)
node _dFirst_size_T_5 = not(_dFirst_size_T_4)
node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5)
node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4)
node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0)
node _dFirst_size_T_7 = orr(dFirst_size_hi)
node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo)
node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2)
node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0)
node _dFirst_size_T_9 = orr(dFirst_size_hi_1)
node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1)
node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1)
node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11)
node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12)
node _T_7 = and(anonOut.d.ready, anonOut.d.valid)
when _T_7 :
node _acknum_T = sub(acknum, ack_decrement)
node _acknum_T_1 = tail(_acknum_T, 1)
node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1)
connect acknum, _acknum_T_2
when dFirst :
connect dOrig, dFirst_size
node _dToggle_T = bits(anonOut.d.bits.source, 3, 3)
connect dToggle, _dToggle_T
node _drop_T = eq(dHasData, UInt<1>(0h0))
node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast)
node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0))
node drop = and(_drop_T, _drop_T_2)
node _anonOut_d_ready_T = or(anonIn.d.ready, drop)
connect anonOut.d.ready, _anonOut_d_ready_T
node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0))
node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T)
connect anonIn.d.valid, _anonIn_d_valid_T_1
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig)
connect anonIn.d.bits.size, _anonIn_d_bits_size_T
inst repeater of Repeater_TLBundleA_a26d64s10k1z3u_1
connect repeater.clock, clock
connect repeater.reset, reset
connect repeater.io.enq, anonIn.a
node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0))
node _find_T_1 = cvt(_find_T)
node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0)))
node _find_T_3 = asSInt(_find_T_2)
node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0)))
wire find : UInt<1>[1]
connect find[0], _find_T_4
node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode)
node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3))
node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode)
node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1)
node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode)
node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3)
node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode)
node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5)
node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode)
node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7)
node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode)
node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9)
node _aFrag_T = gt(repeater.io.deq.bits.size, limit)
node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size)
node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size)
node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0)
node aOrigOH1 = not(_aOrigOH1_T_1)
node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag)
node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0)
node aFragOH1 = not(_aFragOH1_T_1)
node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2)
node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0))
node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1)
regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0)
node aFirst = eq(gennum, UInt<1>(0h0))
node _old_gennum1_T = shr(aOrigOH1, 3)
node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1))
node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1)
node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2)
node _new_gennum_T = not(old_gennum1)
node _new_gennum_T_1 = shr(aMask, 3)
node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1)
node new_gennum = not(_new_gennum_T_2)
node _aFragnum_T = shr(old_gennum1, 0)
node _aFragnum_T_1 = not(_aFragnum_T)
node _aFragnum_T_2 = shr(aFragOH1, 3)
node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2)
node aFragnum = not(_aFragnum_T_3)
node aLast = eq(aFragnum, UInt<1>(0h0))
reg aToggle_r : UInt<1>, clock
when aFirst :
connect aToggle_r, dToggle
node _aToggle_T = mux(aFirst, dToggle, aToggle_r)
node aToggle = eq(_aToggle_T, UInt<1>(0h0))
node _T_8 = and(anonOut.a.ready, anonOut.a.valid)
when _T_8 :
connect gennum, new_gennum
node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0))
node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0))
node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1)
connect repeater.io.repeat, _repeater_io_repeat_T_2
connect anonOut.a.bits, repeater.io.deq.bits
connect anonOut.a.valid, repeater.io.deq.valid
connect repeater.io.deq.ready, anonOut.a.ready
node _anonOut_a_bits_address_T = shl(old_gennum1, 3)
node _anonOut_a_bits_address_T_1 = not(aOrigOH1)
node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1)
node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1)
node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7))
node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4)
node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5)
connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6
node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle)
node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum)
connect anonOut.a.bits.source, _anonOut_a_bits_source_T
connect anonOut.a.bits.size, aFrag
node _T_9 = eq(repeater.io.full, UInt<1>(0h0))
node _T_10 = eq(aHasData, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
connect anonOut.a.bits.data, anonIn.a.bits.data
node _T_15 = eq(repeater.io.full, UInt<1>(0h0))
node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff))
node _T_17 = or(_T_15, _T_16)
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T
wire anonOut_a_bits_user_out : { }
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<26>(0h0)
connect _WIRE.bits.source, UInt<10>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<26>(0h0)
connect _WIRE_2.bits.source, UInt<10>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<14>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<26>(0h0)
connect _WIRE_8.bits.source, UInt<14>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLFragmenter_CLINT( // @[Fragmenter.scala:92:9]
input clock, // @[Fragmenter.scala:92:9]
input reset, // @[Fragmenter.scala:92:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire _repeater_io_full; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30]
wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30]
wire [9:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30]
wire [25:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30]
wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Fragmenter.scala:92:9]
wire [9:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Fragmenter.scala:92:9]
wire [25:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Fragmenter.scala:92:9]
wire [13:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_in_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_d_bits_param = 2'h0; // @[Fragmenter.scala:92:9]
wire [1:0] anonIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire auto_anon_in_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_sink = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_denied = 1'h0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_bits_corrupt = 1'h0; // @[Fragmenter.scala:92:9]
wire anonIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire anonOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire acknum_size = 1'h0; // @[Fragmenter.scala:213:36]
wire _dFirst_acknum_T = 1'h0; // @[Fragmenter.scala:215:50]
wire _new_gennum_T_1 = 1'h0; // @[Fragmenter.scala:306:50]
wire _aFragnum_T_2 = 1'h0; // @[Fragmenter.scala:307:84]
wire [1:0] _limit_T_1 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_3 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_5 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_7 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] _limit_T_9 = 2'h3; // @[Fragmenter.scala:288:49]
wire [1:0] limit = 2'h3; // @[Fragmenter.scala:288:49]
wire _find_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire find_0 = 1'h1; // @[Parameters.scala:616:12]
wire [26:0] _find_T_2 = 27'h0; // @[Parameters.scala:137:46]
wire [26:0] _find_T_3 = 27'h0; // @[Parameters.scala:137:46]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [9:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [25:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Fragmenter.scala:92:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [9:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Fragmenter.scala:92:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [13:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [25:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [1:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [13:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_a_ready_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_in_d_bits_size_0; // @[Fragmenter.scala:92:9]
wire [9:0] auto_anon_in_d_bits_source_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_in_d_valid_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Fragmenter.scala:92:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Fragmenter.scala:92:9]
wire [1:0] auto_anon_out_a_bits_size_0; // @[Fragmenter.scala:92:9]
wire [13:0] auto_anon_out_a_bits_source_0; // @[Fragmenter.scala:92:9]
wire [25:0] auto_anon_out_a_bits_address_0; // @[Fragmenter.scala:92:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[Fragmenter.scala:92:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_a_valid_0; // @[Fragmenter.scala:92:9]
wire auto_anon_out_d_ready_0; // @[Fragmenter.scala:92:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Fragmenter.scala:92:9]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Fragmenter.scala:92:9]
wire [2:0] _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Fragmenter.scala:92:9]
wire [9:0] _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Fragmenter.scala:92:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Fragmenter.scala:92:9]
wire [13:0] _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Fragmenter.scala:92:9]
wire [25:0] _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Fragmenter.scala:92:9]
wire [7:0] _anonOut_a_bits_mask_T; // @[Fragmenter.scala:325:31]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Fragmenter.scala:92:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Fragmenter.scala:92:9]
wire _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Fragmenter.scala:92:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] dsizeOH_shiftAmount = anonOut_d_bits_size; // @[OneHot.scala:64:49]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
reg [2:0] acknum; // @[Fragmenter.scala:201:29]
reg [2:0] dOrig; // @[Fragmenter.scala:202:24]
reg dToggle; // @[Fragmenter.scala:203:30]
wire [2:0] dFragnum = anonOut_d_bits_source[2:0]; // @[Fragmenter.scala:204:41]
wire [2:0] acknum_fragment = dFragnum; // @[Fragmenter.scala:204:41, :212:40]
wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29]
wire dLast = dFragnum == 3'h0; // @[Fragmenter.scala:204:41, :206:30]
wire _drop_T_1 = dLast; // @[Fragmenter.scala:206:30, :234:37]
wire [3:0] _dsizeOH_T = 4'h1 << dsizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] dsizeOH = _dsizeOH_T; // @[OneHot.scala:65:{12,27}]
wire [5:0] _dsizeOH1_T = 6'h7 << anonOut_d_bits_size; // @[package.scala:243:71]
wire [2:0] _dsizeOH1_T_1 = _dsizeOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] dsizeOH1 = ~_dsizeOH1_T_1; // @[package.scala:243:{46,76}]
wire dHasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [2:0] dFirst_acknum = acknum_fragment; // @[Fragmenter.scala:212:40, :215:45]
wire _ack_decrement_T = dsizeOH[3]; // @[OneHot.scala:65:27]
wire ack_decrement = dHasData | _ack_decrement_T; // @[Fragmenter.scala:216:{32,56}]
wire [5:0] _dFirst_size_T = {dFragnum, 3'h0}; // @[Fragmenter.scala:204:41, :218:47]
wire [5:0] _dFirst_size_T_1 = {_dFirst_size_T[5:3], _dFirst_size_T[2:0] | dsizeOH1}; // @[package.scala:243:46]
wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala:241:35]
wire [6:0] _dFirst_size_T_3 = {_dFirst_size_T_2[6:1], 1'h1}; // @[package.scala:241:{35,40}]
wire [6:0] _dFirst_size_T_4 = {1'h0, _dFirst_size_T_1}; // @[package.scala:241:53]
wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala:241:{49,53}]
wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala:241:{40,47,49}]
wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala:30:18]
wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala:31:18]
wire _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi} | dFirst_size_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _dFirst_size_T_11 = _dFirst_size_T_10[1]; // @[OneHot.scala:32:28]
wire [1:0] _dFirst_size_T_12 = {_dFirst_size_T_9, _dFirst_size_T_11}; // @[OneHot.scala:32:{10,14}]
wire [2:0] dFirst_size = {_dFirst_size_T_7, _dFirst_size_T_12}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _acknum_T = {1'h0, acknum} - {3'h0, ack_decrement}; // @[Fragmenter.scala:201:29, :216:32, :221:55]
wire [2:0] _acknum_T_1 = _acknum_T[2:0]; // @[Fragmenter.scala:221:55]
wire [2:0] _acknum_T_2 = dFirst ? dFirst_acknum : _acknum_T_1; // @[Fragmenter.scala:205:29, :215:45, :221:{24,55}]
wire _dToggle_T = anonOut_d_bits_source[3]; // @[Fragmenter.scala:224:41]
wire _drop_T = ~dHasData; // @[Fragmenter.scala:234:20]
wire _drop_T_2 = ~_drop_T_1; // @[Fragmenter.scala:234:{33,37}]
wire drop = _drop_T & _drop_T_2; // @[Fragmenter.scala:234:{20,30,33}]
assign _anonOut_d_ready_T = anonIn_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35]
assign anonOut_d_ready = _anonOut_d_ready_T; // @[Fragmenter.scala:235:35]
wire _anonIn_d_valid_T = ~drop; // @[Fragmenter.scala:234:30, :236:39]
assign _anonIn_d_valid_T_1 = anonOut_d_valid & _anonIn_d_valid_T; // @[Fragmenter.scala:236:{36,39}]
assign anonIn_d_valid = _anonIn_d_valid_T_1; // @[Fragmenter.scala:236:36]
assign _anonIn_d_bits_source_T = anonOut_d_bits_source[13:4]; // @[Fragmenter.scala:238:47]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Fragmenter.scala:238:47]
assign _anonIn_d_bits_size_T = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10]
assign anonIn_d_bits_size = _anonIn_d_bits_size_T; // @[Fragmenter.scala:239:32]
wire [25:0] _find_T; // @[Parameters.scala:137:31]
wire [26:0] _find_T_1 = {1'h0, _find_T}; // @[Parameters.scala:137:{31,41}]
wire _limit_T = _repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_2 = _repeater_io_deq_bits_opcode == 3'h1; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_4 = _repeater_io_deq_bits_opcode == 3'h2; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_6 = _repeater_io_deq_bits_opcode == 3'h3; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_8 = _repeater_io_deq_bits_opcode == 3'h4; // @[Fragmenter.scala:274:30, :288:49]
wire _limit_T_10 = _repeater_io_deq_bits_opcode == 3'h5; // @[Fragmenter.scala:274:30, :288:49]
wire _aFrag_T = _repeater_io_deq_bits_size[2]; // @[Fragmenter.scala:274:30, :297:31]
wire [2:0] aFrag = _aFrag_T ? 3'h3 : _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30, :297:{24,31}]
wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71]
wire [5:0] _aOrigOH1_T_1 = _aOrigOH1_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1; // @[package.scala:243:{46,76}]
wire [9:0] _aFragOH1_T = 10'h7 << aFrag; // @[package.scala:243:71]
wire [2:0] _aFragOH1_T_1 = _aFragOH1_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] aFragOH1 = ~_aFragOH1_T_1; // @[package.scala:243:{46,76}]
wire _aHasData_opdata_T = _repeater_io_deq_bits_opcode[2]; // @[Fragmenter.scala:274:30]
wire aHasData = ~_aHasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] aMask = aHasData ? 3'h0 : aFragOH1; // @[package.scala:243:46]
reg [2:0] gennum; // @[Fragmenter.scala:303:29]
wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29]
wire [2:0] _old_gennum1_T = aOrigOH1[5:3]; // @[package.scala:243:46]
wire [3:0] _old_gennum1_T_1 = {1'h0, gennum} - 4'h1; // @[Fragmenter.scala:303:29, :305:79]
wire [2:0] _old_gennum1_T_2 = _old_gennum1_T_1[2:0]; // @[Fragmenter.scala:305:79]
wire [2:0] old_gennum1 = aFirst ? _old_gennum1_T : _old_gennum1_T_2; // @[Fragmenter.scala:304:29, :305:{30,48,79}]
wire [2:0] _aFragnum_T = old_gennum1; // @[Fragmenter.scala:305:30, :307:40]
wire [2:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala:305:30, :306:28]
wire [2:0] _new_gennum_T_2 = _new_gennum_T; // @[Fragmenter.scala:306:{28,41}]
wire [2:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala:306:{26,41}]
wire [2:0] _aFragnum_T_1 = ~_aFragnum_T; // @[Fragmenter.scala:307:{26,40}]
wire [2:0] _aFragnum_T_3 = _aFragnum_T_1; // @[Fragmenter.scala:307:{26,72}]
wire [2:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala:307:{24,72}]
wire aLast = ~(|aFragnum); // @[Fragmenter.scala:307:24, :308:30]
reg aToggle_r; // @[Fragmenter.scala:309:54]
wire _aToggle_T = aFirst ? dToggle : aToggle_r; // @[Fragmenter.scala:203:30, :304:29, :309:{27,54}]
wire aToggle = ~_aToggle_T; // @[Fragmenter.scala:309:{23,27}]
wire _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala:314:31]
wire _repeater_io_repeat_T_1 = |aFragnum; // @[Fragmenter.scala:307:24, :308:30, :314:53]
wire _repeater_io_repeat_T_2 = _repeater_io_repeat_T & _repeater_io_repeat_T_1; // @[Fragmenter.scala:314:{31,41,53}]
wire [5:0] _anonOut_a_bits_address_T = {old_gennum1, 3'h0}; // @[Fragmenter.scala:305:30, :316:65]
wire [5:0] _anonOut_a_bits_address_T_1 = ~aOrigOH1; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_2 = _anonOut_a_bits_address_T | _anonOut_a_bits_address_T_1; // @[Fragmenter.scala:316:{65,88,90}]
wire [5:0] _anonOut_a_bits_address_T_3 = {_anonOut_a_bits_address_T_2[5:3], _anonOut_a_bits_address_T_2[2:0] | aFragOH1}; // @[package.scala:243:46]
wire [5:0] _anonOut_a_bits_address_T_4 = {_anonOut_a_bits_address_T_3[5:3], 3'h7}; // @[Fragmenter.scala:316:{100,111}]
wire [5:0] _anonOut_a_bits_address_T_5 = ~_anonOut_a_bits_address_T_4; // @[Fragmenter.scala:316:{51,111}]
assign _anonOut_a_bits_address_T_6 = {_repeater_io_deq_bits_address[25:6], _repeater_io_deq_bits_address[5:0] | _anonOut_a_bits_address_T_5}; // @[Fragmenter.scala:274:30, :316:{49,51}]
assign anonOut_a_bits_address = _anonOut_a_bits_address_T_6; // @[Fragmenter.scala:316:49]
wire [10:0] anonOut_a_bits_source_hi = {_repeater_io_deq_bits_source, aToggle}; // @[Fragmenter.scala:274:30, :309:23, :317:33]
assign _anonOut_a_bits_source_T = {anonOut_a_bits_source_hi, aFragnum}; // @[Fragmenter.scala:307:24, :317:33]
assign anonOut_a_bits_source = _anonOut_a_bits_source_T; // @[Fragmenter.scala:317:33]
assign anonOut_a_bits_size = aFrag[1:0]; // @[Fragmenter.scala:297:24, :318:25] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_135 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_135( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLROM :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_54
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
wire rom : UInt<64>[1024]
connect rom[0], UInt<64>(0h405051300000517)
connect rom[1], UInt<64>(0h301022f330551073)
connect rom[2], UInt<64>(0h12f2934122d293)
connect rom[3], UInt<64>(0h3030107300028863)
connect rom[4], UInt<64>(0h3445307322200513)
connect rom[5], UInt<64>(0h3045107300800513)
connect rom[6], UInt<64>(0h1050007330052073)
connect rom[7], UInt<64>(0hffdff06f)
connect rom[8], UInt<64>(0hf1402573020005b7)
connect rom[9], UInt<64>(0h380006f00050463)
connect rom[10], UInt<64>(0h10069300458613)
connect rom[11], UInt<64>(0h46061300d62023)
connect rom[12], UInt<64>(0hfe069ae3ffc62683)
connect rom[13], UInt<64>(0h2c0006f)
connect rom[14], UInt<64>(0h0)
connect rom[15], UInt<64>(0h0)
connect rom[16], UInt<64>(0h5a283f81ff06f)
connect rom[17], UInt<64>(0h251513fe029ee3)
connect rom[18], UInt<64>(0h5a02300b505b3)
connect rom[19], UInt<64>(0h5350300001537)
connect rom[20], UInt<64>(0hf140257334151073)
connect rom[21], UInt<64>(0h185859300000597)
connect rom[22], UInt<64>(0h3006307308000613)
connect rom[23], UInt<64>(0h1330200073)
connect rom[24], UInt<64>(0h38100000edfe0dd0)
connect rom[25], UInt<64>(0hd80d000038000000)
connect rom[26], UInt<64>(0h1100000028000000)
connect rom[27], UInt<64>(0h10000000)
connect rom[28], UInt<64>(0ha00d000060020000)
connect rom[29], UInt<64>(0h0)
connect rom[30], UInt<64>(0h0)
connect rom[31], UInt<64>(0h1000000)
connect rom[32], UInt<64>(0h400000003000000)
connect rom[33], UInt<64>(0h100000000000000)
connect rom[34], UInt<64>(0h400000003000000)
connect rom[35], UInt<64>(0h10000000f000000)
connect rom[36], UInt<64>(0h1500000003000000)
connect rom[37], UInt<64>(0h2d6263751b000000)
connect rom[38], UInt<64>(0h706968632c726162)
connect rom[39], UInt<64>(0h7665642d64726179)
connect rom[40], UInt<64>(0h300000000000000)
connect rom[41], UInt<64>(0h2600000011000000)
connect rom[42], UInt<64>(0h2c7261622d626375)
connect rom[43], UInt<64>(0h6472617970696863)
connect rom[44], UInt<64>(0h100000000000000)
connect rom[45], UInt<64>(0h73657361696c61)
connect rom[46], UInt<64>(0h1500000003000000)
connect rom[47], UInt<64>(0h636f732f2c000000)
connect rom[48], UInt<64>(0h406c61697265732f)
connect rom[49], UInt<64>(0h3030303032303031)
connect rom[50], UInt<64>(0h200000000000000)
connect rom[51], UInt<64>(0h736f686301000000)
connect rom[52], UInt<64>(0h300000000006e65)
connect rom[53], UInt<64>(0h3400000015000000)
connect rom[54], UInt<64>(0h7265732f636f732f)
connect rom[55], UInt<64>(0h32303031406c6169)
connect rom[56], UInt<64>(0h30303030)
connect rom[57], UInt<64>(0h100000002000000)
connect rom[58], UInt<64>(0h73757063)
connect rom[59], UInt<64>(0h400000003000000)
connect rom[60], UInt<64>(0h100000000000000)
connect rom[61], UInt<64>(0h400000003000000)
connect rom[62], UInt<64>(0hf000000)
connect rom[63], UInt<64>(0h400000003000000)
connect rom[64], UInt<64>(0h20a1070040000000)
connect rom[65], UInt<64>(0h4075706301000000)
connect rom[66], UInt<64>(0h300000000000030)
connect rom[67], UInt<64>(0h5300000004000000)
connect rom[68], UInt<64>(0h300000000000000)
connect rom[69], UInt<64>(0h1b00000014000000)
connect rom[70], UInt<64>(0h2c7261622d626375)
connect rom[71], UInt<64>(0h697200306d6f6f62)
connect rom[72], UInt<64>(0h300000000766373)
connect rom[73], UInt<64>(0h6300000004000000)
connect rom[74], UInt<64>(0h300000040000000)
connect rom[75], UInt<64>(0h7600000004000000)
connect rom[76], UInt<64>(0h300000040000000)
connect rom[77], UInt<64>(0h8300000004000000)
connect rom[78], UInt<64>(0h300000000400000)
connect rom[79], UInt<64>(0h9000000004000000)
connect rom[80], UInt<64>(0h300000001000000)
connect rom[81], UInt<64>(0h9b00000004000000)
connect rom[82], UInt<64>(0h300000008000000)
connect rom[83], UInt<64>(0ha600000004000000)
connect rom[84], UInt<64>(0h300000000757063)
connect rom[85], UInt<64>(0hb200000004000000)
connect rom[86], UInt<64>(0h300000000000000)
connect rom[87], UInt<64>(0hd100000004000000)
connect rom[88], UInt<64>(0h300000040000000)
connect rom[89], UInt<64>(0he400000004000000)
connect rom[90], UInt<64>(0h300000040000000)
connect rom[91], UInt<64>(0hf100000004000000)
connect rom[92], UInt<64>(0h300000000400000)
connect rom[93], UInt<64>(0hfe00000004000000)
connect rom[94], UInt<64>(0h300000001000000)
connect rom[95], UInt<64>(0h901000004000000)
connect rom[96], UInt<64>(0h300000020000000)
connect rom[97], UInt<64>(0h140100000b000000)
connect rom[98], UInt<64>(0h76732c7663736972)
connect rom[99], UInt<64>(0h300000000003933)
connect rom[100], UInt<64>(0h1d01000004000000)
connect rom[101], UInt<64>(0h300000001000000)
connect rom[102], UInt<64>(0h2e01000004000000)
connect rom[103], UInt<64>(0h300000000000000)
connect rom[104], UInt<64>(0h320100001f000000)
connect rom[105], UInt<64>(0h66616d6934367672)
connect rom[106], UInt<64>(0h5f727363697a6364)
connect rom[107], UInt<64>(0h6965636e6566697a)
connect rom[108], UInt<64>(0h6d7068697a5f)
connect rom[109], UInt<64>(0h400000003000000)
connect rom[110], UInt<64>(0h40000003c010000)
connect rom[111], UInt<64>(0h400000003000000)
connect rom[112], UInt<64>(0h800000051010000)
connect rom[113], UInt<64>(0h500000003000000)
connect rom[114], UInt<64>(0h79616b6f62010000)
connect rom[115], UInt<64>(0h300000000000000)
connect rom[116], UInt<64>(0h4000000004000000)
connect rom[117], UInt<64>(0h300000020a10700)
connect rom[118], UInt<64>(0h6901000000000000)
connect rom[119], UInt<64>(0h65746e6901000000)
connect rom[120], UInt<64>(0h6f632d7470757272)
connect rom[121], UInt<64>(0h72656c6c6f72746e)
connect rom[122], UInt<64>(0h300000000000000)
connect rom[123], UInt<64>(0h7301000004000000)
connect rom[124], UInt<64>(0h300000001000000)
connect rom[125], UInt<64>(0h1b0000000f000000)
connect rom[126], UInt<64>(0h70632c7663736972)
connect rom[127], UInt<64>(0h63746e692d75)
connect rom[128], UInt<64>(0h3000000)
connect rom[129], UInt<64>(0h300000084010000)
connect rom[130], UInt<64>(0h9901000004000000)
connect rom[131], UInt<64>(0h200000004000000)
connect rom[132], UInt<64>(0h100000002000000)
connect rom[133], UInt<64>(0h3140757063)
connect rom[134], UInt<64>(0h400000003000000)
connect rom[135], UInt<64>(0h53000000)
connect rom[136], UInt<64>(0h1400000003000000)
connect rom[137], UInt<64>(0h2d6263751b000000)
connect rom[138], UInt<64>(0h6d6f6f622c726162)
connect rom[139], UInt<64>(0h76637369720030)
connect rom[140], UInt<64>(0h400000003000000)
connect rom[141], UInt<64>(0h4000000063000000)
connect rom[142], UInt<64>(0h400000003000000)
connect rom[143], UInt<64>(0h4000000076000000)
connect rom[144], UInt<64>(0h400000003000000)
connect rom[145], UInt<64>(0h40000083000000)
connect rom[146], UInt<64>(0h400000003000000)
connect rom[147], UInt<64>(0h100000090000000)
connect rom[148], UInt<64>(0h400000003000000)
connect rom[149], UInt<64>(0h80000009b000000)
connect rom[150], UInt<64>(0h400000003000000)
connect rom[151], UInt<64>(0h757063a6000000)
connect rom[152], UInt<64>(0h400000003000000)
connect rom[153], UInt<64>(0hb2000000)
connect rom[154], UInt<64>(0h400000003000000)
connect rom[155], UInt<64>(0h40000000d1000000)
connect rom[156], UInt<64>(0h400000003000000)
connect rom[157], UInt<64>(0h40000000e4000000)
connect rom[158], UInt<64>(0h400000003000000)
connect rom[159], UInt<64>(0h400000f1000000)
connect rom[160], UInt<64>(0h400000003000000)
connect rom[161], UInt<64>(0h1000000fe000000)
connect rom[162], UInt<64>(0h400000003000000)
connect rom[163], UInt<64>(0h2000000009010000)
connect rom[164], UInt<64>(0hb00000003000000)
connect rom[165], UInt<64>(0h6373697214010000)
connect rom[166], UInt<64>(0h393376732c76)
connect rom[167], UInt<64>(0h400000003000000)
connect rom[168], UInt<64>(0h10000001d010000)
connect rom[169], UInt<64>(0h400000003000000)
connect rom[170], UInt<64>(0h10000002e010000)
connect rom[171], UInt<64>(0h1f00000003000000)
connect rom[172], UInt<64>(0h3436767232010000)
connect rom[173], UInt<64>(0h697a636466616d69)
connect rom[174], UInt<64>(0h6566697a5f727363)
connect rom[175], UInt<64>(0h68697a5f6965636e)
connect rom[176], UInt<64>(0h300000000006d70)
connect rom[177], UInt<64>(0h3c01000004000000)
connect rom[178], UInt<64>(0h300000004000000)
connect rom[179], UInt<64>(0h5101000004000000)
connect rom[180], UInt<64>(0h300000008000000)
connect rom[181], UInt<64>(0h6201000005000000)
connect rom[182], UInt<64>(0h79616b6f)
connect rom[183], UInt<64>(0h400000003000000)
connect rom[184], UInt<64>(0h20a1070040000000)
connect rom[185], UInt<64>(0h3000000)
connect rom[186], UInt<64>(0h100000069010000)
connect rom[187], UInt<64>(0h7075727265746e69)
connect rom[188], UInt<64>(0h6f72746e6f632d74)
connect rom[189], UInt<64>(0h72656c6c)
connect rom[190], UInt<64>(0h400000003000000)
connect rom[191], UInt<64>(0h100000073010000)
connect rom[192], UInt<64>(0hf00000003000000)
connect rom[193], UInt<64>(0h637369721b000000)
connect rom[194], UInt<64>(0h6e692d7570632c76)
connect rom[195], UInt<64>(0h300000000006374)
connect rom[196], UInt<64>(0h8401000000000000)
connect rom[197], UInt<64>(0h400000003000000)
connect rom[198], UInt<64>(0h500000099010000)
connect rom[199], UInt<64>(0h200000002000000)
connect rom[200], UInt<64>(0h100000002000000)
connect rom[201], UInt<64>(0h66697468)
connect rom[202], UInt<64>(0ha00000003000000)
connect rom[203], UInt<64>(0h2c6263751b000000)
connect rom[204], UInt<64>(0h3066697468)
connect rom[205], UInt<64>(0h100000002000000)
connect rom[206], UInt<64>(0h384079726f6d656d)
connect rom[207], UInt<64>(0h303030303030)
connect rom[208], UInt<64>(0h700000003000000)
connect rom[209], UInt<64>(0h6f6d656da6000000)
connect rom[210], UInt<64>(0h300000000007972)
connect rom[211], UInt<64>(0h2e01000008000000)
connect rom[212], UInt<64>(0h10000000008)
connect rom[213], UInt<64>(0h900000003000000)
connect rom[214], UInt<64>(0h6173696462010000)
connect rom[215], UInt<64>(0h64656c62)
connect rom[216], UInt<64>(0h400000003000000)
connect rom[217], UInt<64>(0h300000099010000)
connect rom[218], UInt<64>(0h100000002000000)
connect rom[219], UInt<64>(0h384079726f6d656d)
connect rom[220], UInt<64>(0h30303030303030)
connect rom[221], UInt<64>(0h700000003000000)
connect rom[222], UInt<64>(0h6f6d656da6000000)
connect rom[223], UInt<64>(0h300000000007972)
connect rom[224], UInt<64>(0h2e01000008000000)
connect rom[225], UInt<64>(0h1000000080)
connect rom[226], UInt<64>(0h400000003000000)
connect rom[227], UInt<64>(0h200000099010000)
connect rom[228], UInt<64>(0h100000002000000)
connect rom[229], UInt<64>(0h300000000636f73)
connect rom[230], UInt<64>(0h4000000)
connect rom[231], UInt<64>(0h300000001000000)
connect rom[232], UInt<64>(0hf00000004000000)
connect rom[233], UInt<64>(0h300000001000000)
connect rom[234], UInt<64>(0h1b00000020000000)
connect rom[235], UInt<64>(0h2c7261622d626375)
connect rom[236], UInt<64>(0h6472617970696863)
connect rom[237], UInt<64>(0h6d697300636f732d)
connect rom[238], UInt<64>(0h7375622d656c70)
connect rom[239], UInt<64>(0h3000000)
connect rom[240], UInt<64>(0h1000000a1010000)
connect rom[241], UInt<64>(0h6464612d746f6f62)
connect rom[242], UInt<64>(0h6765722d73736572)
connect rom[243], UInt<64>(0h3030303140)
connect rom[244], UInt<64>(0h800000003000000)
connect rom[245], UInt<64>(0h1000002e010000)
connect rom[246], UInt<64>(0h300000000100000)
connect rom[247], UInt<64>(0ha801000008000000)
connect rom[248], UInt<64>(0h6c6f72746e6f63)
connect rom[249], UInt<64>(0h100000002000000)
connect rom[250], UInt<64>(0h6f632d6568636163)
connect rom[251], UInt<64>(0h72656c6c6f72746e)
connect rom[252], UInt<64>(0h3030303031303240)
connect rom[253], UInt<64>(0h300000000000000)
connect rom[254], UInt<64>(0h6500000004000000)
connect rom[255], UInt<64>(0h300000040000000)
connect rom[256], UInt<64>(0hb201000004000000)
connect rom[257], UInt<64>(0h300000002000000)
connect rom[258], UInt<64>(0h7800000004000000)
connect rom[259], UInt<64>(0h300000000040000)
connect rom[260], UInt<64>(0h8500000004000000)
connect rom[261], UInt<64>(0h300000000000800)
connect rom[262], UInt<64>(0hbe01000000000000)
connect rom[263], UInt<64>(0h1d00000003000000)
connect rom[264], UInt<64>(0h696669731b000000)
connect rom[265], UInt<64>(0h756c636e692c6576)
connect rom[266], UInt<64>(0h6863616365766973)
connect rom[267], UInt<64>(0h6568636163003065)
connect rom[268], UInt<64>(0h300000000000000)
connect rom[269], UInt<64>(0h1d01000008000000)
connect rom[270], UInt<64>(0h300000002000000)
connect rom[271], UInt<64>(0h800000003000000)
connect rom[272], UInt<64>(0h1022e010000)
connect rom[273], UInt<64>(0h300000000100000)
connect rom[274], UInt<64>(0ha801000008000000)
connect rom[275], UInt<64>(0h6c6f72746e6f63)
connect rom[276], UInt<64>(0h400000003000000)
connect rom[277], UInt<64>(0h7000000cc010000)
connect rom[278], UInt<64>(0h400000003000000)
connect rom[279], UInt<64>(0h100000099010000)
connect rom[280], UInt<64>(0h100000002000000)
connect rom[281], UInt<64>(0h6f6c635f73756263)
connect rom[282], UInt<64>(0h300000000006b63)
connect rom[283], UInt<64>(0hde01000004000000)
connect rom[284], UInt<64>(0h300000000000000)
connect rom[285], UInt<64>(0h5300000004000000)
connect rom[286], UInt<64>(0h30000000065cd1d)
connect rom[287], UInt<64>(0heb0100000b000000)
connect rom[288], UInt<64>(0h6f6c635f73756263)
connect rom[289], UInt<64>(0h300000000006b63)
connect rom[290], UInt<64>(0h1b0000000c000000)
connect rom[291], UInt<64>(0h6c632d6465786966)
connect rom[292], UInt<64>(0h2000000006b636f)
connect rom[293], UInt<64>(0h6e696c6301000000)
connect rom[294], UInt<64>(0h3030303030324074)
connect rom[295], UInt<64>(0h300000000000030)
connect rom[296], UInt<64>(0h1b0000000d000000)
connect rom[297], UInt<64>(0h6c632c7663736972)
connect rom[298], UInt<64>(0h30746e69)
connect rom[299], UInt<64>(0h2000000003000000)
connect rom[300], UInt<64>(0h4000000fe010000)
connect rom[301], UInt<64>(0h400000003000000)
connect rom[302], UInt<64>(0h500000007000000)
connect rom[303], UInt<64>(0h500000003000000)
connect rom[304], UInt<64>(0h300000007000000)
connect rom[305], UInt<64>(0h2e01000008000000)
connect rom[306], UInt<64>(0h10000000002)
connect rom[307], UInt<64>(0h800000003000000)
connect rom[308], UInt<64>(0h746e6f63a8010000)
connect rom[309], UInt<64>(0h2000000006c6f72)
connect rom[310], UInt<64>(0h636f6c6301000000)
connect rom[311], UInt<64>(0h4072657461672d6b)
connect rom[312], UInt<64>(0h303030303031)
connect rom[313], UInt<64>(0h800000003000000)
connect rom[314], UInt<64>(0h10002e010000)
connect rom[315], UInt<64>(0h300000000100000)
connect rom[316], UInt<64>(0ha801000008000000)
connect rom[317], UInt<64>(0h6c6f72746e6f63)
connect rom[318], UInt<64>(0h100000002000000)
connect rom[319], UInt<64>(0h6f632d6775626564)
connect rom[320], UInt<64>(0h72656c6c6f72746e)
connect rom[321], UInt<64>(0h300000000003040)
connect rom[322], UInt<64>(0h1b00000021000000)
connect rom[323], UInt<64>(0h642c657669666973)
connect rom[324], UInt<64>(0h3331302d67756265)
connect rom[325], UInt<64>(0h642c766373697200)
connect rom[326], UInt<64>(0h3331302d67756265)
connect rom[327], UInt<64>(0h300000000000000)
connect rom[328], UInt<64>(0h1202000005000000)
connect rom[329], UInt<64>(0h6761746a)
connect rom[330], UInt<64>(0h1000000003000000)
connect rom[331], UInt<64>(0h4000000fe010000)
connect rom[332], UInt<64>(0h5000000ffff0000)
connect rom[333], UInt<64>(0h3000000ffff0000)
connect rom[334], UInt<64>(0h2e01000008000000)
connect rom[335], UInt<64>(0h10000000000000)
connect rom[336], UInt<64>(0h800000003000000)
connect rom[337], UInt<64>(0h746e6f63a8010000)
connect rom[338], UInt<64>(0h2000000006c6f72)
connect rom[339], UInt<64>(0h6f72726501000000)
connect rom[340], UInt<64>(0h6563697665642d72)
connect rom[341], UInt<64>(0h3030303340)
connect rom[342], UInt<64>(0he00000003000000)
connect rom[343], UInt<64>(0h696669731b000000)
connect rom[344], UInt<64>(0h726f7272652c6576)
connect rom[345], UInt<64>(0h300000000000030)
connect rom[346], UInt<64>(0h2e01000008000000)
connect rom[347], UInt<64>(0h10000000300000)
connect rom[348], UInt<64>(0h100000002000000)
connect rom[349], UInt<64>(0h6f6c635f73756266)
connect rom[350], UInt<64>(0h300000000006b63)
connect rom[351], UInt<64>(0hde01000004000000)
connect rom[352], UInt<64>(0h300000000000000)
connect rom[353], UInt<64>(0h5300000004000000)
connect rom[354], UInt<64>(0h30000000065cd1d)
connect rom[355], UInt<64>(0heb0100000b000000)
connect rom[356], UInt<64>(0h6f6c635f73756266)
connect rom[357], UInt<64>(0h300000000006b63)
connect rom[358], UInt<64>(0h1b0000000c000000)
connect rom[359], UInt<64>(0h6c632d6465786966)
connect rom[360], UInt<64>(0h2000000006b636f)
connect rom[361], UInt<64>(0h65746e6901000000)
connect rom[362], UInt<64>(0h6f632d7470757272)
connect rom[363], UInt<64>(0h72656c6c6f72746e)
connect rom[364], UInt<64>(0h3030303030306340)
connect rom[365], UInt<64>(0h300000000000000)
connect rom[366], UInt<64>(0h7301000004000000)
connect rom[367], UInt<64>(0h300000001000000)
connect rom[368], UInt<64>(0h1b0000000c000000)
connect rom[369], UInt<64>(0h6c702c7663736972)
connect rom[370], UInt<64>(0h300000000306369)
connect rom[371], UInt<64>(0h8401000000000000)
connect rom[372], UInt<64>(0h2000000003000000)
connect rom[373], UInt<64>(0h4000000fe010000)
connect rom[374], UInt<64>(0h40000000b000000)
connect rom[375], UInt<64>(0h500000009000000)
connect rom[376], UInt<64>(0h50000000b000000)
connect rom[377], UInt<64>(0h300000009000000)
connect rom[378], UInt<64>(0h2e01000008000000)
connect rom[379], UInt<64>(0h40000000c)
connect rom[380], UInt<64>(0h800000003000000)
connect rom[381], UInt<64>(0h746e6f63a8010000)
connect rom[382], UInt<64>(0h3000000006c6f72)
connect rom[383], UInt<64>(0h1f02000004000000)
connect rom[384], UInt<64>(0h300000001000000)
connect rom[385], UInt<64>(0h3202000004000000)
connect rom[386], UInt<64>(0h300000001000000)
connect rom[387], UInt<64>(0h9901000004000000)
connect rom[388], UInt<64>(0h200000007000000)
connect rom[389], UInt<64>(0h7375626d01000000)
connect rom[390], UInt<64>(0h6b636f6c635f)
connect rom[391], UInt<64>(0h400000003000000)
connect rom[392], UInt<64>(0hde010000)
connect rom[393], UInt<64>(0h400000003000000)
connect rom[394], UInt<64>(0h65cd1d53000000)
connect rom[395], UInt<64>(0hb00000003000000)
connect rom[396], UInt<64>(0h7375626deb010000)
connect rom[397], UInt<64>(0h6b636f6c635f)
connect rom[398], UInt<64>(0hc00000003000000)
connect rom[399], UInt<64>(0h657869661b000000)
connect rom[400], UInt<64>(0h6b636f6c632d64)
connect rom[401], UInt<64>(0h100000002000000)
connect rom[402], UInt<64>(0h6f6c635f73756270)
connect rom[403], UInt<64>(0h300000000006b63)
connect rom[404], UInt<64>(0hde01000004000000)
connect rom[405], UInt<64>(0h300000000000000)
connect rom[406], UInt<64>(0h5300000004000000)
connect rom[407], UInt<64>(0h30000000065cd1d)
connect rom[408], UInt<64>(0heb0100000b000000)
connect rom[409], UInt<64>(0h6f6c635f73756270)
connect rom[410], UInt<64>(0h300000000006b63)
connect rom[411], UInt<64>(0h1b0000000c000000)
connect rom[412], UInt<64>(0h6c632d6465786966)
connect rom[413], UInt<64>(0h3000000006b636f)
connect rom[414], UInt<64>(0h9901000004000000)
connect rom[415], UInt<64>(0h200000006000000)
connect rom[416], UInt<64>(0h406d6f7201000000)
connect rom[417], UInt<64>(0h3030303031)
connect rom[418], UInt<64>(0hc00000003000000)
connect rom[419], UInt<64>(0h696669731b000000)
connect rom[420], UInt<64>(0h306d6f722c6576)
connect rom[421], UInt<64>(0h800000003000000)
connect rom[422], UInt<64>(0h1002e010000)
connect rom[423], UInt<64>(0h300000000000100)
connect rom[424], UInt<64>(0ha801000004000000)
connect rom[425], UInt<64>(0h2000000006d656d)
connect rom[426], UInt<64>(0h7375627301000000)
connect rom[427], UInt<64>(0h6b636f6c635f)
connect rom[428], UInt<64>(0h400000003000000)
connect rom[429], UInt<64>(0hde010000)
connect rom[430], UInt<64>(0h400000003000000)
connect rom[431], UInt<64>(0h65cd1d53000000)
connect rom[432], UInt<64>(0hb00000003000000)
connect rom[433], UInt<64>(0h73756273eb010000)
connect rom[434], UInt<64>(0h6b636f6c635f)
connect rom[435], UInt<64>(0hc00000003000000)
connect rom[436], UInt<64>(0h657869661b000000)
connect rom[437], UInt<64>(0h6b636f6c632d64)
connect rom[438], UInt<64>(0h100000002000000)
connect rom[439], UInt<64>(0h31406c6169726573)
connect rom[440], UInt<64>(0h30303030323030)
connect rom[441], UInt<64>(0h400000003000000)
connect rom[442], UInt<64>(0h60000003d020000)
connect rom[443], UInt<64>(0hd00000003000000)
connect rom[444], UInt<64>(0h696669731b000000)
connect rom[445], UInt<64>(0h30747261752c6576)
connect rom[446], UInt<64>(0h300000000000000)
connect rom[447], UInt<64>(0h4402000004000000)
connect rom[448], UInt<64>(0h300000007000000)
connect rom[449], UInt<64>(0h5502000004000000)
connect rom[450], UInt<64>(0h300000001000000)
connect rom[451], UInt<64>(0h2e01000008000000)
connect rom[452], UInt<64>(0h10000000000210)
connect rom[453], UInt<64>(0h800000003000000)
connect rom[454], UInt<64>(0h746e6f63a8010000)
connect rom[455], UInt<64>(0h2000000006c6f72)
connect rom[456], UInt<64>(0h656c697401000000)
connect rom[457], UInt<64>(0h732d74657365722d)
connect rom[458], UInt<64>(0h3131407265747465)
connect rom[459], UInt<64>(0h30303030)
connect rom[460], UInt<64>(0h800000003000000)
connect rom[461], UInt<64>(0h11002e010000)
connect rom[462], UInt<64>(0h300000000100000)
connect rom[463], UInt<64>(0ha801000008000000)
connect rom[464], UInt<64>(0h6c6f72746e6f63)
connect rom[465], UInt<64>(0h200000002000000)
connect rom[466], UInt<64>(0h900000002000000)
connect rom[467], UInt<64>(0h7373657264646123)
connect rom[468], UInt<64>(0h2300736c6c65632d)
connect rom[469], UInt<64>(0h6c65632d657a6973)
connect rom[470], UInt<64>(0h61706d6f6300736c)
connect rom[471], UInt<64>(0h6f6d00656c626974)
connect rom[472], UInt<64>(0h69726573006c6564)
connect rom[473], UInt<64>(0h6f64747300306c61)
connect rom[474], UInt<64>(0h687461702d7475)
connect rom[475], UInt<64>(0h65736162656d6974)
connect rom[476], UInt<64>(0h6e6575716572662d)
connect rom[477], UInt<64>(0h6b636f6c63007963)
connect rom[478], UInt<64>(0h6e6575716572662d)
connect rom[479], UInt<64>(0h6361632d64007963)
connect rom[480], UInt<64>(0h6b636f6c622d6568)
connect rom[481], UInt<64>(0h2d6400657a69732d)
connect rom[482], UInt<64>(0h65732d6568636163)
connect rom[483], UInt<64>(0h6361632d64007374)
connect rom[484], UInt<64>(0h657a69732d6568)
connect rom[485], UInt<64>(0h65732d626c742d64)
connect rom[486], UInt<64>(0h626c742d64007374)
connect rom[487], UInt<64>(0h656400657a69732d)
connect rom[488], UInt<64>(0h7079745f65636976)
connect rom[489], UInt<64>(0h6177647261680065)
connect rom[490], UInt<64>(0h2d636578652d6572)
connect rom[491], UInt<64>(0h696f706b61657262)
connect rom[492], UInt<64>(0h746e756f632d746e)
connect rom[493], UInt<64>(0h65686361632d6900)
connect rom[494], UInt<64>(0h732d6b636f6c622d)
connect rom[495], UInt<64>(0h61632d6900657a69)
connect rom[496], UInt<64>(0h737465732d656863)
connect rom[497], UInt<64>(0h65686361632d6900)
connect rom[498], UInt<64>(0h2d6900657a69732d)
connect rom[499], UInt<64>(0h737465732d626c74)
connect rom[500], UInt<64>(0h732d626c742d6900)
connect rom[501], UInt<64>(0h2d756d6d00657a69)
connect rom[502], UInt<64>(0h78656e0065707974)
connect rom[503], UInt<64>(0h2d6c6576656c2d74)
connect rom[504], UInt<64>(0h6572006568636163)
connect rom[505], UInt<64>(0h2c76637369720067)
connect rom[506], UInt<64>(0h6373697200617369)
connect rom[507], UInt<64>(0h617267706d702c76)
connect rom[508], UInt<64>(0h79746972616c756e)
connect rom[509], UInt<64>(0h702c766373697200)
connect rom[510], UInt<64>(0h6e6f69676572706d)
connect rom[511], UInt<64>(0h7375746174730073)
connect rom[512], UInt<64>(0h6c70732d626c7400)
connect rom[513], UInt<64>(0h65746e6923007469)
connect rom[514], UInt<64>(0h65632d7470757272)
connect rom[515], UInt<64>(0h65746e6900736c6c)
connect rom[516], UInt<64>(0h6f632d7470757272)
connect rom[517], UInt<64>(0h72656c6c6f72746e)
connect rom[518], UInt<64>(0h656c646e61687000)
connect rom[519], UInt<64>(0h7365676e617200)
connect rom[520], UInt<64>(0h656d616e2d676572)
connect rom[521], UInt<64>(0h2d65686361630073)
connect rom[522], UInt<64>(0h6163006c6576656c)
connect rom[523], UInt<64>(0h66696e752d656863)
connect rom[524], UInt<64>(0h6966697300646569)
connect rom[525], UInt<64>(0h2d7268736d2c6576)
connect rom[526], UInt<64>(0h632300746e756f63)
connect rom[527], UInt<64>(0h6c65632d6b636f6c)
connect rom[528], UInt<64>(0h6b636f6c6300736c)
connect rom[529], UInt<64>(0h2d74757074756f2d)
connect rom[530], UInt<64>(0h6e690073656d616e)
connect rom[531], UInt<64>(0h7374707572726574)
connect rom[532], UInt<64>(0h65646e657478652d)
connect rom[533], UInt<64>(0h2d67756265640064)
connect rom[534], UInt<64>(0h7200686361747461)
connect rom[535], UInt<64>(0h78616d2c76637369)
connect rom[536], UInt<64>(0h7469726f6972702d)
connect rom[537], UInt<64>(0h2c76637369720079)
connect rom[538], UInt<64>(0h6f6c63007665646e)
connect rom[539], UInt<64>(0h65746e6900736b63)
connect rom[540], UInt<64>(0h61702d7470757272)
connect rom[541], UInt<64>(0h746e6900746e6572)
connect rom[542], UInt<64>(0h73747075727265)
connect rom[543], UInt<64>(0h0)
connect rom[544], UInt<64>(0h0)
connect rom[545], UInt<64>(0h0)
connect rom[546], UInt<64>(0h0)
connect rom[547], UInt<64>(0h0)
connect rom[548], UInt<64>(0h0)
connect rom[549], UInt<64>(0h0)
connect rom[550], UInt<64>(0h0)
connect rom[551], UInt<64>(0h0)
connect rom[552], UInt<64>(0h0)
connect rom[553], UInt<64>(0h0)
connect rom[554], UInt<64>(0h0)
connect rom[555], UInt<64>(0h0)
connect rom[556], UInt<64>(0h0)
connect rom[557], UInt<64>(0h0)
connect rom[558], UInt<64>(0h0)
connect rom[559], UInt<64>(0h0)
connect rom[560], UInt<64>(0h0)
connect rom[561], UInt<64>(0h0)
connect rom[562], UInt<64>(0h0)
connect rom[563], UInt<64>(0h0)
connect rom[564], UInt<64>(0h0)
connect rom[565], UInt<64>(0h0)
connect rom[566], UInt<64>(0h0)
connect rom[567], UInt<64>(0h0)
connect rom[568], UInt<64>(0h0)
connect rom[569], UInt<64>(0h0)
connect rom[570], UInt<64>(0h0)
connect rom[571], UInt<64>(0h0)
connect rom[572], UInt<64>(0h0)
connect rom[573], UInt<64>(0h0)
connect rom[574], UInt<64>(0h0)
connect rom[575], UInt<64>(0h0)
connect rom[576], UInt<64>(0h0)
connect rom[577], UInt<64>(0h0)
connect rom[578], UInt<64>(0h0)
connect rom[579], UInt<64>(0h0)
connect rom[580], UInt<64>(0h0)
connect rom[581], UInt<64>(0h0)
connect rom[582], UInt<64>(0h0)
connect rom[583], UInt<64>(0h0)
connect rom[584], UInt<64>(0h0)
connect rom[585], UInt<64>(0h0)
connect rom[586], UInt<64>(0h0)
connect rom[587], UInt<64>(0h0)
connect rom[588], UInt<64>(0h0)
connect rom[589], UInt<64>(0h0)
connect rom[590], UInt<64>(0h0)
connect rom[591], UInt<64>(0h0)
connect rom[592], UInt<64>(0h0)
connect rom[593], UInt<64>(0h0)
connect rom[594], UInt<64>(0h0)
connect rom[595], UInt<64>(0h0)
connect rom[596], UInt<64>(0h0)
connect rom[597], UInt<64>(0h0)
connect rom[598], UInt<64>(0h0)
connect rom[599], UInt<64>(0h0)
connect rom[600], UInt<64>(0h0)
connect rom[601], UInt<64>(0h0)
connect rom[602], UInt<64>(0h0)
connect rom[603], UInt<64>(0h0)
connect rom[604], UInt<64>(0h0)
connect rom[605], UInt<64>(0h0)
connect rom[606], UInt<64>(0h0)
connect rom[607], UInt<64>(0h0)
connect rom[608], UInt<64>(0h0)
connect rom[609], UInt<64>(0h0)
connect rom[610], UInt<64>(0h0)
connect rom[611], UInt<64>(0h0)
connect rom[612], UInt<64>(0h0)
connect rom[613], UInt<64>(0h0)
connect rom[614], UInt<64>(0h0)
connect rom[615], UInt<64>(0h0)
connect rom[616], UInt<64>(0h0)
connect rom[617], UInt<64>(0h0)
connect rom[618], UInt<64>(0h0)
connect rom[619], UInt<64>(0h0)
connect rom[620], UInt<64>(0h0)
connect rom[621], UInt<64>(0h0)
connect rom[622], UInt<64>(0h0)
connect rom[623], UInt<64>(0h0)
connect rom[624], UInt<64>(0h0)
connect rom[625], UInt<64>(0h0)
connect rom[626], UInt<64>(0h0)
connect rom[627], UInt<64>(0h0)
connect rom[628], UInt<64>(0h0)
connect rom[629], UInt<64>(0h0)
connect rom[630], UInt<64>(0h0)
connect rom[631], UInt<64>(0h0)
connect rom[632], UInt<64>(0h0)
connect rom[633], UInt<64>(0h0)
connect rom[634], UInt<64>(0h0)
connect rom[635], UInt<64>(0h0)
connect rom[636], UInt<64>(0h0)
connect rom[637], UInt<64>(0h0)
connect rom[638], UInt<64>(0h0)
connect rom[639], UInt<64>(0h0)
connect rom[640], UInt<64>(0h0)
connect rom[641], UInt<64>(0h0)
connect rom[642], UInt<64>(0h0)
connect rom[643], UInt<64>(0h0)
connect rom[644], UInt<64>(0h0)
connect rom[645], UInt<64>(0h0)
connect rom[646], UInt<64>(0h0)
connect rom[647], UInt<64>(0h0)
connect rom[648], UInt<64>(0h0)
connect rom[649], UInt<64>(0h0)
connect rom[650], UInt<64>(0h0)
connect rom[651], UInt<64>(0h0)
connect rom[652], UInt<64>(0h0)
connect rom[653], UInt<64>(0h0)
connect rom[654], UInt<64>(0h0)
connect rom[655], UInt<64>(0h0)
connect rom[656], UInt<64>(0h0)
connect rom[657], UInt<64>(0h0)
connect rom[658], UInt<64>(0h0)
connect rom[659], UInt<64>(0h0)
connect rom[660], UInt<64>(0h0)
connect rom[661], UInt<64>(0h0)
connect rom[662], UInt<64>(0h0)
connect rom[663], UInt<64>(0h0)
connect rom[664], UInt<64>(0h0)
connect rom[665], UInt<64>(0h0)
connect rom[666], UInt<64>(0h0)
connect rom[667], UInt<64>(0h0)
connect rom[668], UInt<64>(0h0)
connect rom[669], UInt<64>(0h0)
connect rom[670], UInt<64>(0h0)
connect rom[671], UInt<64>(0h0)
connect rom[672], UInt<64>(0h0)
connect rom[673], UInt<64>(0h0)
connect rom[674], UInt<64>(0h0)
connect rom[675], UInt<64>(0h0)
connect rom[676], UInt<64>(0h0)
connect rom[677], UInt<64>(0h0)
connect rom[678], UInt<64>(0h0)
connect rom[679], UInt<64>(0h0)
connect rom[680], UInt<64>(0h0)
connect rom[681], UInt<64>(0h0)
connect rom[682], UInt<64>(0h0)
connect rom[683], UInt<64>(0h0)
connect rom[684], UInt<64>(0h0)
connect rom[685], UInt<64>(0h0)
connect rom[686], UInt<64>(0h0)
connect rom[687], UInt<64>(0h0)
connect rom[688], UInt<64>(0h0)
connect rom[689], UInt<64>(0h0)
connect rom[690], UInt<64>(0h0)
connect rom[691], UInt<64>(0h0)
connect rom[692], UInt<64>(0h0)
connect rom[693], UInt<64>(0h0)
connect rom[694], UInt<64>(0h0)
connect rom[695], UInt<64>(0h0)
connect rom[696], UInt<64>(0h0)
connect rom[697], UInt<64>(0h0)
connect rom[698], UInt<64>(0h0)
connect rom[699], UInt<64>(0h0)
connect rom[700], UInt<64>(0h0)
connect rom[701], UInt<64>(0h0)
connect rom[702], UInt<64>(0h0)
connect rom[703], UInt<64>(0h0)
connect rom[704], UInt<64>(0h0)
connect rom[705], UInt<64>(0h0)
connect rom[706], UInt<64>(0h0)
connect rom[707], UInt<64>(0h0)
connect rom[708], UInt<64>(0h0)
connect rom[709], UInt<64>(0h0)
connect rom[710], UInt<64>(0h0)
connect rom[711], UInt<64>(0h0)
connect rom[712], UInt<64>(0h0)
connect rom[713], UInt<64>(0h0)
connect rom[714], UInt<64>(0h0)
connect rom[715], UInt<64>(0h0)
connect rom[716], UInt<64>(0h0)
connect rom[717], UInt<64>(0h0)
connect rom[718], UInt<64>(0h0)
connect rom[719], UInt<64>(0h0)
connect rom[720], UInt<64>(0h0)
connect rom[721], UInt<64>(0h0)
connect rom[722], UInt<64>(0h0)
connect rom[723], UInt<64>(0h0)
connect rom[724], UInt<64>(0h0)
connect rom[725], UInt<64>(0h0)
connect rom[726], UInt<64>(0h0)
connect rom[727], UInt<64>(0h0)
connect rom[728], UInt<64>(0h0)
connect rom[729], UInt<64>(0h0)
connect rom[730], UInt<64>(0h0)
connect rom[731], UInt<64>(0h0)
connect rom[732], UInt<64>(0h0)
connect rom[733], UInt<64>(0h0)
connect rom[734], UInt<64>(0h0)
connect rom[735], UInt<64>(0h0)
connect rom[736], UInt<64>(0h0)
connect rom[737], UInt<64>(0h0)
connect rom[738], UInt<64>(0h0)
connect rom[739], UInt<64>(0h0)
connect rom[740], UInt<64>(0h0)
connect rom[741], UInt<64>(0h0)
connect rom[742], UInt<64>(0h0)
connect rom[743], UInt<64>(0h0)
connect rom[744], UInt<64>(0h0)
connect rom[745], UInt<64>(0h0)
connect rom[746], UInt<64>(0h0)
connect rom[747], UInt<64>(0h0)
connect rom[748], UInt<64>(0h0)
connect rom[749], UInt<64>(0h0)
connect rom[750], UInt<64>(0h0)
connect rom[751], UInt<64>(0h0)
connect rom[752], UInt<64>(0h0)
connect rom[753], UInt<64>(0h0)
connect rom[754], UInt<64>(0h0)
connect rom[755], UInt<64>(0h0)
connect rom[756], UInt<64>(0h0)
connect rom[757], UInt<64>(0h0)
connect rom[758], UInt<64>(0h0)
connect rom[759], UInt<64>(0h0)
connect rom[760], UInt<64>(0h0)
connect rom[761], UInt<64>(0h0)
connect rom[762], UInt<64>(0h0)
connect rom[763], UInt<64>(0h0)
connect rom[764], UInt<64>(0h0)
connect rom[765], UInt<64>(0h0)
connect rom[766], UInt<64>(0h0)
connect rom[767], UInt<64>(0h0)
connect rom[768], UInt<64>(0h0)
connect rom[769], UInt<64>(0h0)
connect rom[770], UInt<64>(0h0)
connect rom[771], UInt<64>(0h0)
connect rom[772], UInt<64>(0h0)
connect rom[773], UInt<64>(0h0)
connect rom[774], UInt<64>(0h0)
connect rom[775], UInt<64>(0h0)
connect rom[776], UInt<64>(0h0)
connect rom[777], UInt<64>(0h0)
connect rom[778], UInt<64>(0h0)
connect rom[779], UInt<64>(0h0)
connect rom[780], UInt<64>(0h0)
connect rom[781], UInt<64>(0h0)
connect rom[782], UInt<64>(0h0)
connect rom[783], UInt<64>(0h0)
connect rom[784], UInt<64>(0h0)
connect rom[785], UInt<64>(0h0)
connect rom[786], UInt<64>(0h0)
connect rom[787], UInt<64>(0h0)
connect rom[788], UInt<64>(0h0)
connect rom[789], UInt<64>(0h0)
connect rom[790], UInt<64>(0h0)
connect rom[791], UInt<64>(0h0)
connect rom[792], UInt<64>(0h0)
connect rom[793], UInt<64>(0h0)
connect rom[794], UInt<64>(0h0)
connect rom[795], UInt<64>(0h0)
connect rom[796], UInt<64>(0h0)
connect rom[797], UInt<64>(0h0)
connect rom[798], UInt<64>(0h0)
connect rom[799], UInt<64>(0h0)
connect rom[800], UInt<64>(0h0)
connect rom[801], UInt<64>(0h0)
connect rom[802], UInt<64>(0h0)
connect rom[803], UInt<64>(0h0)
connect rom[804], UInt<64>(0h0)
connect rom[805], UInt<64>(0h0)
connect rom[806], UInt<64>(0h0)
connect rom[807], UInt<64>(0h0)
connect rom[808], UInt<64>(0h0)
connect rom[809], UInt<64>(0h0)
connect rom[810], UInt<64>(0h0)
connect rom[811], UInt<64>(0h0)
connect rom[812], UInt<64>(0h0)
connect rom[813], UInt<64>(0h0)
connect rom[814], UInt<64>(0h0)
connect rom[815], UInt<64>(0h0)
connect rom[816], UInt<64>(0h0)
connect rom[817], UInt<64>(0h0)
connect rom[818], UInt<64>(0h0)
connect rom[819], UInt<64>(0h0)
connect rom[820], UInt<64>(0h0)
connect rom[821], UInt<64>(0h0)
connect rom[822], UInt<64>(0h0)
connect rom[823], UInt<64>(0h0)
connect rom[824], UInt<64>(0h0)
connect rom[825], UInt<64>(0h0)
connect rom[826], UInt<64>(0h0)
connect rom[827], UInt<64>(0h0)
connect rom[828], UInt<64>(0h0)
connect rom[829], UInt<64>(0h0)
connect rom[830], UInt<64>(0h0)
connect rom[831], UInt<64>(0h0)
connect rom[832], UInt<64>(0h0)
connect rom[833], UInt<64>(0h0)
connect rom[834], UInt<64>(0h0)
connect rom[835], UInt<64>(0h0)
connect rom[836], UInt<64>(0h0)
connect rom[837], UInt<64>(0h0)
connect rom[838], UInt<64>(0h0)
connect rom[839], UInt<64>(0h0)
connect rom[840], UInt<64>(0h0)
connect rom[841], UInt<64>(0h0)
connect rom[842], UInt<64>(0h0)
connect rom[843], UInt<64>(0h0)
connect rom[844], UInt<64>(0h0)
connect rom[845], UInt<64>(0h0)
connect rom[846], UInt<64>(0h0)
connect rom[847], UInt<64>(0h0)
connect rom[848], UInt<64>(0h0)
connect rom[849], UInt<64>(0h0)
connect rom[850], UInt<64>(0h0)
connect rom[851], UInt<64>(0h0)
connect rom[852], UInt<64>(0h0)
connect rom[853], UInt<64>(0h0)
connect rom[854], UInt<64>(0h0)
connect rom[855], UInt<64>(0h0)
connect rom[856], UInt<64>(0h0)
connect rom[857], UInt<64>(0h0)
connect rom[858], UInt<64>(0h0)
connect rom[859], UInt<64>(0h0)
connect rom[860], UInt<64>(0h0)
connect rom[861], UInt<64>(0h0)
connect rom[862], UInt<64>(0h0)
connect rom[863], UInt<64>(0h0)
connect rom[864], UInt<64>(0h0)
connect rom[865], UInt<64>(0h0)
connect rom[866], UInt<64>(0h0)
connect rom[867], UInt<64>(0h0)
connect rom[868], UInt<64>(0h0)
connect rom[869], UInt<64>(0h0)
connect rom[870], UInt<64>(0h0)
connect rom[871], UInt<64>(0h0)
connect rom[872], UInt<64>(0h0)
connect rom[873], UInt<64>(0h0)
connect rom[874], UInt<64>(0h0)
connect rom[875], UInt<64>(0h0)
connect rom[876], UInt<64>(0h0)
connect rom[877], UInt<64>(0h0)
connect rom[878], UInt<64>(0h0)
connect rom[879], UInt<64>(0h0)
connect rom[880], UInt<64>(0h0)
connect rom[881], UInt<64>(0h0)
connect rom[882], UInt<64>(0h0)
connect rom[883], UInt<64>(0h0)
connect rom[884], UInt<64>(0h0)
connect rom[885], UInt<64>(0h0)
connect rom[886], UInt<64>(0h0)
connect rom[887], UInt<64>(0h0)
connect rom[888], UInt<64>(0h0)
connect rom[889], UInt<64>(0h0)
connect rom[890], UInt<64>(0h0)
connect rom[891], UInt<64>(0h0)
connect rom[892], UInt<64>(0h0)
connect rom[893], UInt<64>(0h0)
connect rom[894], UInt<64>(0h0)
connect rom[895], UInt<64>(0h0)
connect rom[896], UInt<64>(0h0)
connect rom[897], UInt<64>(0h0)
connect rom[898], UInt<64>(0h0)
connect rom[899], UInt<64>(0h0)
connect rom[900], UInt<64>(0h0)
connect rom[901], UInt<64>(0h0)
connect rom[902], UInt<64>(0h0)
connect rom[903], UInt<64>(0h0)
connect rom[904], UInt<64>(0h0)
connect rom[905], UInt<64>(0h0)
connect rom[906], UInt<64>(0h0)
connect rom[907], UInt<64>(0h0)
connect rom[908], UInt<64>(0h0)
connect rom[909], UInt<64>(0h0)
connect rom[910], UInt<64>(0h0)
connect rom[911], UInt<64>(0h0)
connect rom[912], UInt<64>(0h0)
connect rom[913], UInt<64>(0h0)
connect rom[914], UInt<64>(0h0)
connect rom[915], UInt<64>(0h0)
connect rom[916], UInt<64>(0h0)
connect rom[917], UInt<64>(0h0)
connect rom[918], UInt<64>(0h0)
connect rom[919], UInt<64>(0h0)
connect rom[920], UInt<64>(0h0)
connect rom[921], UInt<64>(0h0)
connect rom[922], UInt<64>(0h0)
connect rom[923], UInt<64>(0h0)
connect rom[924], UInt<64>(0h0)
connect rom[925], UInt<64>(0h0)
connect rom[926], UInt<64>(0h0)
connect rom[927], UInt<64>(0h0)
connect rom[928], UInt<64>(0h0)
connect rom[929], UInt<64>(0h0)
connect rom[930], UInt<64>(0h0)
connect rom[931], UInt<64>(0h0)
connect rom[932], UInt<64>(0h0)
connect rom[933], UInt<64>(0h0)
connect rom[934], UInt<64>(0h0)
connect rom[935], UInt<64>(0h0)
connect rom[936], UInt<64>(0h0)
connect rom[937], UInt<64>(0h0)
connect rom[938], UInt<64>(0h0)
connect rom[939], UInt<64>(0h0)
connect rom[940], UInt<64>(0h0)
connect rom[941], UInt<64>(0h0)
connect rom[942], UInt<64>(0h0)
connect rom[943], UInt<64>(0h0)
connect rom[944], UInt<64>(0h0)
connect rom[945], UInt<64>(0h0)
connect rom[946], UInt<64>(0h0)
connect rom[947], UInt<64>(0h0)
connect rom[948], UInt<64>(0h0)
connect rom[949], UInt<64>(0h0)
connect rom[950], UInt<64>(0h0)
connect rom[951], UInt<64>(0h0)
connect rom[952], UInt<64>(0h0)
connect rom[953], UInt<64>(0h0)
connect rom[954], UInt<64>(0h0)
connect rom[955], UInt<64>(0h0)
connect rom[956], UInt<64>(0h0)
connect rom[957], UInt<64>(0h0)
connect rom[958], UInt<64>(0h0)
connect rom[959], UInt<64>(0h0)
connect rom[960], UInt<64>(0h0)
connect rom[961], UInt<64>(0h0)
connect rom[962], UInt<64>(0h0)
connect rom[963], UInt<64>(0h0)
connect rom[964], UInt<64>(0h0)
connect rom[965], UInt<64>(0h0)
connect rom[966], UInt<64>(0h0)
connect rom[967], UInt<64>(0h0)
connect rom[968], UInt<64>(0h0)
connect rom[969], UInt<64>(0h0)
connect rom[970], UInt<64>(0h0)
connect rom[971], UInt<64>(0h0)
connect rom[972], UInt<64>(0h0)
connect rom[973], UInt<64>(0h0)
connect rom[974], UInt<64>(0h0)
connect rom[975], UInt<64>(0h0)
connect rom[976], UInt<64>(0h0)
connect rom[977], UInt<64>(0h0)
connect rom[978], UInt<64>(0h0)
connect rom[979], UInt<64>(0h0)
connect rom[980], UInt<64>(0h0)
connect rom[981], UInt<64>(0h0)
connect rom[982], UInt<64>(0h0)
connect rom[983], UInt<64>(0h0)
connect rom[984], UInt<64>(0h0)
connect rom[985], UInt<64>(0h0)
connect rom[986], UInt<64>(0h0)
connect rom[987], UInt<64>(0h0)
connect rom[988], UInt<64>(0h0)
connect rom[989], UInt<64>(0h0)
connect rom[990], UInt<64>(0h0)
connect rom[991], UInt<64>(0h0)
connect rom[992], UInt<64>(0h0)
connect rom[993], UInt<64>(0h0)
connect rom[994], UInt<64>(0h0)
connect rom[995], UInt<64>(0h0)
connect rom[996], UInt<64>(0h0)
connect rom[997], UInt<64>(0h0)
connect rom[998], UInt<64>(0h0)
connect rom[999], UInt<64>(0h0)
connect rom[1000], UInt<64>(0h0)
connect rom[1001], UInt<64>(0h0)
connect rom[1002], UInt<64>(0h0)
connect rom[1003], UInt<64>(0h0)
connect rom[1004], UInt<64>(0h0)
connect rom[1005], UInt<64>(0h0)
connect rom[1006], UInt<64>(0h0)
connect rom[1007], UInt<64>(0h0)
connect rom[1008], UInt<64>(0h0)
connect rom[1009], UInt<64>(0h0)
connect rom[1010], UInt<64>(0h0)
connect rom[1011], UInt<64>(0h0)
connect rom[1012], UInt<64>(0h0)
connect rom[1013], UInt<64>(0h0)
connect rom[1014], UInt<64>(0h0)
connect rom[1015], UInt<64>(0h0)
connect rom[1016], UInt<64>(0h0)
connect rom[1017], UInt<64>(0h0)
connect rom[1018], UInt<64>(0h0)
connect rom[1019], UInt<64>(0h0)
connect rom[1020], UInt<64>(0h0)
connect rom[1021], UInt<64>(0h0)
connect rom[1022], UInt<64>(0h0)
connect rom[1023], UInt<64>(0h0)
connect nodeIn.d.valid, nodeIn.a.valid
connect nodeIn.a.ready, nodeIn.d.ready
node index = bits(nodeIn.a.bits.address, 12, 3)
node high = bits(nodeIn.a.bits.address, 15, 13)
node _nodeIn_d_bits_T = orr(high)
node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index])
wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeIn_d_bits_d.opcode, UInt<1>(0h1)
connect nodeIn_d_bits_d.param, UInt<1>(0h0)
connect nodeIn_d_bits_d.size, nodeIn.a.bits.size
connect nodeIn_d_bits_d.source, nodeIn.a.bits.source
connect nodeIn_d_bits_d.sink, UInt<1>(0h0)
connect nodeIn_d_bits_d.denied, UInt<1>(0h0)
connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1
connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt
connect nodeIn.d.bits.data, nodeIn_d_bits_d.data
connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied
connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink
connect nodeIn.d.bits.source, nodeIn_d_bits_d.source
connect nodeIn.d.bits.size, nodeIn_d_bits_d.size
connect nodeIn.d.bits.param, nodeIn_d_bits_d.param
connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLROM( // @[BootROM.scala:41:9]
input clock, // @[BootROM.scala:41:9]
input reset, // @[BootROM.scala:41:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9]
wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9]
wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9]
wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9]
wire [1023:0][63:0] _GEN =
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64'h0,
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64'h642C657669666973,
64'h1B00000021000000,
64'h300000000003040,
64'h72656C6C6F72746E,
64'h6F632D6775626564,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h10002E010000,
64'h800000003000000,
64'h303030303031,
64'h4072657461672D6B,
64'h636F6C6301000000,
64'h2000000006C6F72,
64'h746E6F63A8010000,
64'h800000003000000,
64'h10000000002,
64'h2E01000008000000,
64'h300000007000000,
64'h500000003000000,
64'h500000007000000,
64'h400000003000000,
64'h4000000FE010000,
64'h2000000003000000,
64'h30746E69,
64'h6C632C7663736972,
64'h1B0000000D000000,
64'h300000000000030,
64'h3030303030324074,
64'h6E696C6301000000,
64'h2000000006B636F,
64'h6C632D6465786966,
64'h1B0000000C000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'hEB0100000B000000,
64'h30000000065CD1D,
64'h5300000004000000,
64'h300000000000000,
64'hDE01000004000000,
64'h300000000006B63,
64'h6F6C635F73756263,
64'h100000002000000,
64'h100000099010000,
64'h400000003000000,
64'h7000000CC010000,
64'h400000003000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1022E010000,
64'h800000003000000,
64'h300000002000000,
64'h1D01000008000000,
64'h300000000000000,
64'h6568636163003065,
64'h6863616365766973,
64'h756C636E692C6576,
64'h696669731B000000,
64'h1D00000003000000,
64'hBE01000000000000,
64'h300000000000800,
64'h8500000004000000,
64'h300000000040000,
64'h7800000004000000,
64'h300000002000000,
64'hB201000004000000,
64'h300000040000000,
64'h6500000004000000,
64'h300000000000000,
64'h3030303031303240,
64'h72656C6C6F72746E,
64'h6F632D6568636163,
64'h100000002000000,
64'h6C6F72746E6F63,
64'hA801000008000000,
64'h300000000100000,
64'h1000002E010000,
64'h800000003000000,
64'h3030303140,
64'h6765722D73736572,
64'h6464612D746F6F62,
64'h1000000A1010000,
64'h3000000,
64'h7375622D656C70,
64'h6D697300636F732D,
64'h6472617970696863,
64'h2C7261622D626375,
64'h1B00000020000000,
64'h300000001000000,
64'hF00000004000000,
64'h300000001000000,
64'h4000000,
64'h300000000636F73,
64'h100000002000000,
64'h200000099010000,
64'h400000003000000,
64'h1000000080,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h30303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h300000099010000,
64'h400000003000000,
64'h64656C62,
64'h6173696462010000,
64'h900000003000000,
64'h10000000008,
64'h2E01000008000000,
64'h300000000007972,
64'h6F6D656DA6000000,
64'h700000003000000,
64'h303030303030,
64'h384079726F6D656D,
64'h100000002000000,
64'h3066697468,
64'h2C6263751B000000,
64'hA00000003000000,
64'h66697468,
64'h100000002000000,
64'h200000002000000,
64'h500000099010000,
64'h400000003000000,
64'h8401000000000000,
64'h300000000006374,
64'h6E692D7570632C76,
64'h637369721B000000,
64'hF00000003000000,
64'h100000073010000,
64'h400000003000000,
64'h72656C6C,
64'h6F72746E6F632D74,
64'h7075727265746E69,
64'h100000069010000,
64'h3000000,
64'h20A1070040000000,
64'h400000003000000,
64'h79616B6F,
64'h6201000005000000,
64'h300000008000000,
64'h5101000004000000,
64'h300000004000000,
64'h3C01000004000000,
64'h300000000006D70,
64'h68697A5F6965636E,
64'h6566697A5F727363,
64'h697A636466616D69,
64'h3436767232010000,
64'h1F00000003000000,
64'h10000002E010000,
64'h400000003000000,
64'h10000001D010000,
64'h400000003000000,
64'h393376732C76,
64'h6373697214010000,
64'hB00000003000000,
64'h2000000009010000,
64'h400000003000000,
64'h1000000FE000000,
64'h400000003000000,
64'h400000F1000000,
64'h400000003000000,
64'h40000000E4000000,
64'h400000003000000,
64'h40000000D1000000,
64'h400000003000000,
64'hB2000000,
64'h400000003000000,
64'h757063A6000000,
64'h400000003000000,
64'h80000009B000000,
64'h400000003000000,
64'h100000090000000,
64'h400000003000000,
64'h40000083000000,
64'h400000003000000,
64'h4000000076000000,
64'h400000003000000,
64'h4000000063000000,
64'h400000003000000,
64'h76637369720030,
64'h6D6F6F622C726162,
64'h2D6263751B000000,
64'h1400000003000000,
64'h53000000,
64'h400000003000000,
64'h3140757063,
64'h100000002000000,
64'h200000004000000,
64'h9901000004000000,
64'h300000084010000,
64'h3000000,
64'h63746E692D75,
64'h70632C7663736972,
64'h1B0000000F000000,
64'h300000001000000,
64'h7301000004000000,
64'h300000000000000,
64'h72656C6C6F72746E,
64'h6F632D7470757272,
64'h65746E6901000000,
64'h6901000000000000,
64'h300000020A10700,
64'h4000000004000000,
64'h300000000000000,
64'h79616B6F62010000,
64'h500000003000000,
64'h800000051010000,
64'h400000003000000,
64'h40000003C010000,
64'h400000003000000,
64'h6D7068697A5F,
64'h6965636E6566697A,
64'h5F727363697A6364,
64'h66616D6934367672,
64'h320100001F000000,
64'h300000000000000,
64'h2E01000004000000,
64'h300000001000000,
64'h1D01000004000000,
64'h300000000003933,
64'h76732C7663736972,
64'h140100000B000000,
64'h300000020000000,
64'h901000004000000,
64'h300000001000000,
64'hFE00000004000000,
64'h300000000400000,
64'hF100000004000000,
64'h300000040000000,
64'hE400000004000000,
64'h300000040000000,
64'hD100000004000000,
64'h300000000000000,
64'hB200000004000000,
64'h300000000757063,
64'hA600000004000000,
64'h300000008000000,
64'h9B00000004000000,
64'h300000001000000,
64'h9000000004000000,
64'h300000000400000,
64'h8300000004000000,
64'h300000040000000,
64'h7600000004000000,
64'h300000040000000,
64'h6300000004000000,
64'h300000000766373,
64'h697200306D6F6F62,
64'h2C7261622D626375,
64'h1B00000014000000,
64'h300000000000000,
64'h5300000004000000,
64'h300000000000030,
64'h4075706301000000,
64'h20A1070040000000,
64'h400000003000000,
64'hF000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h73757063,
64'h100000002000000,
64'h30303030,
64'h32303031406C6169,
64'h7265732F636F732F,
64'h3400000015000000,
64'h300000000006E65,
64'h736F686301000000,
64'h200000000000000,
64'h3030303032303031,
64'h406C61697265732F,
64'h636F732F2C000000,
64'h1500000003000000,
64'h73657361696C61,
64'h100000000000000,
64'h6472617970696863,
64'h2C7261622D626375,
64'h2600000011000000,
64'h300000000000000,
64'h7665642D64726179,
64'h706968632C726162,
64'h2D6263751B000000,
64'h1500000003000000,
64'h10000000F000000,
64'h400000003000000,
64'h100000000000000,
64'h400000003000000,
64'h1000000,
64'h0,
64'h0,
64'hA00D000060020000,
64'h10000000,
64'h1100000028000000,
64'hD80D000038000000,
64'h38100000EDFE0DD0,
64'h1330200073,
64'h3006307308000613,
64'h185859300000597,
64'hF140257334151073,
64'h5350300001537,
64'h5A02300B505B3,
64'h251513FE029EE3,
64'h5A283F81FF06F,
64'h0,
64'h0,
64'h2C0006F,
64'hFE069AE3FFC62683,
64'h46061300D62023,
64'h10069300458613,
64'h380006F00050463,
64'hF1402573020005B7,
64'hFFDFF06F,
64'h1050007330052073,
64'h3045107300800513,
64'h3445307322200513,
64'h3030107300028863,
64'h12F2934122D293,
64'h301022F330551073,
64'h405051300000517};
wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22]
wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22]
wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22]
wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22]
wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22]
wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22]
wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22]
wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22]
wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22]
wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22]
wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22]
wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22]
wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22]
wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22]
wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22]
wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22]
wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22]
wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22]
wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22]
wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22]
wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22]
wire [63:0] rom_24 = 64'h38100000EDFE0DD0; // @[BootROM.scala:50:22]
wire [63:0] rom_25 = 64'hD80D000038000000; // @[BootROM.scala:50:22]
wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22]
wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22]
wire [63:0] rom_28 = 64'hA00D000060020000; // @[BootROM.scala:50:22]
wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22]
wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22]
wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22]
wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22]
wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22]
wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22]
wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22]
wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22]
wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22]
wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22]
wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22]
wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_69 = 64'h1B00000014000000; // @[BootROM.scala:50:22]
wire [63:0] rom_71 = 64'h697200306D6F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_72 = 64'h300000000766373; // @[BootROM.scala:50:22]
wire [63:0] rom_73 = 64'h6300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_75 = 64'h7600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_77 = 64'h8300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_79 = 64'h9000000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_81 = 64'h9B00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_83 = 64'hA600000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_84 = 64'h300000000757063; // @[BootROM.scala:50:22]
wire [63:0] rom_85 = 64'hB200000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_87 = 64'hD100000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_89 = 64'hE400000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_91 = 64'hF100000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_78 = 64'h300000000400000; // @[BootROM.scala:50:22]
wire [63:0] rom_92 = 64'h300000000400000; // @[BootROM.scala:50:22]
wire [63:0] rom_93 = 64'hFE00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_95 = 64'h901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_96 = 64'h300000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_97 = 64'h140100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_98 = 64'h76732C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_99 = 64'h300000000003933; // @[BootROM.scala:50:22]
wire [63:0] rom_100 = 64'h1D01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_102 = 64'h2E01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_104 = 64'h320100001F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_105 = 64'h66616D6934367672; // @[BootROM.scala:50:22]
wire [63:0] rom_106 = 64'h5F727363697A6364; // @[BootROM.scala:50:22]
wire [63:0] rom_107 = 64'h6965636E6566697A; // @[BootROM.scala:50:22]
wire [63:0] rom_108 = 64'h6D7068697A5F; // @[BootROM.scala:50:22]
wire [63:0] rom_110 = 64'h40000003C010000; // @[BootROM.scala:50:22]
wire [63:0] rom_112 = 64'h800000051010000; // @[BootROM.scala:50:22]
wire [63:0] rom_114 = 64'h79616B6F62010000; // @[BootROM.scala:50:22]
wire [63:0] rom_116 = 64'h4000000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_117 = 64'h300000020A10700; // @[BootROM.scala:50:22]
wire [63:0] rom_118 = 64'h6901000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_125 = 64'h1B0000000F000000; // @[BootROM.scala:50:22]
wire [63:0] rom_126 = 64'h70632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_127 = 64'h63746E692D75; // @[BootROM.scala:50:22]
wire [63:0] rom_129 = 64'h300000084010000; // @[BootROM.scala:50:22]
wire [63:0] rom_131 = 64'h200000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_133 = 64'h3140757063; // @[BootROM.scala:50:22]
wire [63:0] rom_135 = 64'h53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_136 = 64'h1400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_137 = 64'h2D6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_138 = 64'h6D6F6F622C726162; // @[BootROM.scala:50:22]
wire [63:0] rom_139 = 64'h76637369720030; // @[BootROM.scala:50:22]
wire [63:0] rom_141 = 64'h4000000063000000; // @[BootROM.scala:50:22]
wire [63:0] rom_143 = 64'h4000000076000000; // @[BootROM.scala:50:22]
wire [63:0] rom_145 = 64'h40000083000000; // @[BootROM.scala:50:22]
wire [63:0] rom_147 = 64'h100000090000000; // @[BootROM.scala:50:22]
wire [63:0] rom_149 = 64'h80000009B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_151 = 64'h757063A6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_153 = 64'hB2000000; // @[BootROM.scala:50:22]
wire [63:0] rom_155 = 64'h40000000D1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_157 = 64'h40000000E4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_159 = 64'h400000F1000000; // @[BootROM.scala:50:22]
wire [63:0] rom_161 = 64'h1000000FE000000; // @[BootROM.scala:50:22]
wire [63:0] rom_163 = 64'h2000000009010000; // @[BootROM.scala:50:22]
wire [63:0] rom_165 = 64'h6373697214010000; // @[BootROM.scala:50:22]
wire [63:0] rom_166 = 64'h393376732C76; // @[BootROM.scala:50:22]
wire [63:0] rom_168 = 64'h10000001D010000; // @[BootROM.scala:50:22]
wire [63:0] rom_170 = 64'h10000002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_171 = 64'h1F00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_172 = 64'h3436767232010000; // @[BootROM.scala:50:22]
wire [63:0] rom_173 = 64'h697A636466616D69; // @[BootROM.scala:50:22]
wire [63:0] rom_174 = 64'h6566697A5F727363; // @[BootROM.scala:50:22]
wire [63:0] rom_175 = 64'h68697A5F6965636E; // @[BootROM.scala:50:22]
wire [63:0] rom_176 = 64'h300000000006D70; // @[BootROM.scala:50:22]
wire [63:0] rom_177 = 64'h3C01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_178 = 64'h300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_179 = 64'h5101000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_82 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_180 = 64'h300000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_181 = 64'h6201000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_182 = 64'h79616B6F; // @[BootROM.scala:50:22]
wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_184 = 64'h20A1070040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_186 = 64'h100000069010000; // @[BootROM.scala:50:22]
wire [63:0] rom_187 = 64'h7075727265746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_188 = 64'h6F72746E6F632D74; // @[BootROM.scala:50:22]
wire [63:0] rom_189 = 64'h72656C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_191 = 64'h100000073010000; // @[BootROM.scala:50:22]
wire [63:0] rom_192 = 64'hF00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_193 = 64'h637369721B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_194 = 64'h6E692D7570632C76; // @[BootROM.scala:50:22]
wire [63:0] rom_195 = 64'h300000000006374; // @[BootROM.scala:50:22]
wire [63:0] rom_198 = 64'h500000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_201 = 64'h66697468; // @[BootROM.scala:50:22]
wire [63:0] rom_202 = 64'hA00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_203 = 64'h2C6263751B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_204 = 64'h3066697468; // @[BootROM.scala:50:22]
wire [63:0] rom_207 = 64'h303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_212 = 64'h10000000008; // @[BootROM.scala:50:22]
wire [63:0] rom_213 = 64'h900000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_214 = 64'h6173696462010000; // @[BootROM.scala:50:22]
wire [63:0] rom_215 = 64'h64656C62; // @[BootROM.scala:50:22]
wire [63:0] rom_217 = 64'h300000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_206 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_219 = 64'h384079726F6D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_220 = 64'h30303030303030; // @[BootROM.scala:50:22]
wire [63:0] rom_208 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_221 = 64'h700000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_209 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_222 = 64'h6F6D656DA6000000; // @[BootROM.scala:50:22]
wire [63:0] rom_210 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_223 = 64'h300000000007972; // @[BootROM.scala:50:22]
wire [63:0] rom_225 = 64'h1000000080; // @[BootROM.scala:50:22]
wire [63:0] rom_227 = 64'h200000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_229 = 64'h300000000636F73; // @[BootROM.scala:50:22]
wire [63:0] rom_230 = 64'h4000000; // @[BootROM.scala:50:22]
wire [63:0] rom_232 = 64'hF00000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_234 = 64'h1B00000020000000; // @[BootROM.scala:50:22]
wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_70 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_235 = 64'h2C7261622D626375; // @[BootROM.scala:50:22]
wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_236 = 64'h6472617970696863; // @[BootROM.scala:50:22]
wire [63:0] rom_237 = 64'h6D697300636F732D; // @[BootROM.scala:50:22]
wire [63:0] rom_238 = 64'h7375622D656C70; // @[BootROM.scala:50:22]
wire [63:0] rom_128 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_185 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_239 = 64'h3000000; // @[BootROM.scala:50:22]
wire [63:0] rom_240 = 64'h1000000A1010000; // @[BootROM.scala:50:22]
wire [63:0] rom_241 = 64'h6464612D746F6F62; // @[BootROM.scala:50:22]
wire [63:0] rom_242 = 64'h6765722D73736572; // @[BootROM.scala:50:22]
wire [63:0] rom_243 = 64'h3030303140; // @[BootROM.scala:50:22]
wire [63:0] rom_245 = 64'h1000002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_250 = 64'h6F632D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_252 = 64'h3030303031303240; // @[BootROM.scala:50:22]
wire [63:0] rom_254 = 64'h6500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_74 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_76 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_88 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_90 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_255 = 64'h300000040000000; // @[BootROM.scala:50:22]
wire [63:0] rom_256 = 64'hB201000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_258 = 64'h7800000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_259 = 64'h300000000040000; // @[BootROM.scala:50:22]
wire [63:0] rom_260 = 64'h8500000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_261 = 64'h300000000000800; // @[BootROM.scala:50:22]
wire [63:0] rom_262 = 64'hBE01000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_263 = 64'h1D00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_265 = 64'h756C636E692C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_266 = 64'h6863616365766973; // @[BootROM.scala:50:22]
wire [63:0] rom_267 = 64'h6568636163003065; // @[BootROM.scala:50:22]
wire [63:0] rom_269 = 64'h1D01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_257 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_270 = 64'h300000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_272 = 64'h1022E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_277 = 64'h7000000CC010000; // @[BootROM.scala:50:22]
wire [63:0] rom_279 = 64'h100000099010000; // @[BootROM.scala:50:22]
wire [63:0] rom_281 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_288 = 64'h6F6C635F73756263; // @[BootROM.scala:50:22]
wire [63:0] rom_293 = 64'h6E696C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_294 = 64'h3030303030324074; // @[BootROM.scala:50:22]
wire [63:0] rom_296 = 64'h1B0000000D000000; // @[BootROM.scala:50:22]
wire [63:0] rom_297 = 64'h6C632C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_298 = 64'h30746E69; // @[BootROM.scala:50:22]
wire [63:0] rom_302 = 64'h500000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_113 = 64'h500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_303 = 64'h500000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_306 = 64'h10000000002; // @[BootROM.scala:50:22]
wire [63:0] rom_310 = 64'h636F6C6301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_311 = 64'h4072657461672D6B; // @[BootROM.scala:50:22]
wire [63:0] rom_312 = 64'h303030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_314 = 64'h10002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_319 = 64'h6F632D6775626564; // @[BootROM.scala:50:22]
wire [63:0] rom_321 = 64'h300000000003040; // @[BootROM.scala:50:22]
wire [63:0] rom_322 = 64'h1B00000021000000; // @[BootROM.scala:50:22]
wire [63:0] rom_323 = 64'h642C657669666973; // @[BootROM.scala:50:22]
wire [63:0] rom_325 = 64'h642C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_324 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_326 = 64'h3331302D67756265; // @[BootROM.scala:50:22]
wire [63:0] rom_328 = 64'h1202000005000000; // @[BootROM.scala:50:22]
wire [63:0] rom_329 = 64'h6761746A; // @[BootROM.scala:50:22]
wire [63:0] rom_330 = 64'h1000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_332 = 64'h5000000FFFF0000; // @[BootROM.scala:50:22]
wire [63:0] rom_333 = 64'h3000000FFFF0000; // @[BootROM.scala:50:22]
wire [63:0] rom_335 = 64'h10000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_339 = 64'h6F72726501000000; // @[BootROM.scala:50:22]
wire [63:0] rom_340 = 64'h6563697665642D72; // @[BootROM.scala:50:22]
wire [63:0] rom_341 = 64'h3030303340; // @[BootROM.scala:50:22]
wire [63:0] rom_342 = 64'hE00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_344 = 64'h726F7272652C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_295 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_345 = 64'h300000000000030; // @[BootROM.scala:50:22]
wire [63:0] rom_347 = 64'h10000000300000; // @[BootROM.scala:50:22]
wire [63:0] rom_349 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_356 = 64'h6F6C635F73756266; // @[BootROM.scala:50:22]
wire [63:0] rom_292 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_360 = 64'h2000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_119 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_361 = 64'h65746E6901000000; // @[BootROM.scala:50:22]
wire [63:0] rom_364 = 64'h3030303030306340; // @[BootROM.scala:50:22]
wire [63:0] rom_123 = 64'h7301000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_366 = 64'h7301000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_369 = 64'h6C702C7663736972; // @[BootROM.scala:50:22]
wire [63:0] rom_370 = 64'h300000000306369; // @[BootROM.scala:50:22]
wire [63:0] rom_196 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_371 = 64'h8401000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_299 = 64'h2000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_372 = 64'h2000000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_300 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_331 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_373 = 64'h4000000FE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_374 = 64'h40000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_375 = 64'h500000009000000; // @[BootROM.scala:50:22]
wire [63:0] rom_376 = 64'h50000000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_377 = 64'h300000009000000; // @[BootROM.scala:50:22]
wire [63:0] rom_379 = 64'h40000000C; // @[BootROM.scala:50:22]
wire [63:0] rom_382 = 64'h3000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_383 = 64'h1F02000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_385 = 64'h3202000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_388 = 64'h200000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_389 = 64'h7375626D01000000; // @[BootROM.scala:50:22]
wire [63:0] rom_396 = 64'h7375626DEB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_283 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_351 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_404 = 64'hDE01000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_285 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_353 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_406 = 64'h5300000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_286 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_354 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_407 = 64'h30000000065CD1D; // @[BootROM.scala:50:22]
wire [63:0] rom_287 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_355 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_408 = 64'hEB0100000B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_402 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_409 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22]
wire [63:0] rom_282 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_289 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_350 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_357 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_403 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_410 = 64'h300000000006B63; // @[BootROM.scala:50:22]
wire [63:0] rom_290 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_358 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_368 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_411 = 64'h1B0000000C000000; // @[BootROM.scala:50:22]
wire [63:0] rom_291 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_359 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_412 = 64'h6C632D6465786966; // @[BootROM.scala:50:22]
wire [63:0] rom_413 = 64'h3000000006B636F; // @[BootROM.scala:50:22]
wire [63:0] rom_130 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_387 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_414 = 64'h9901000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_415 = 64'h200000006000000; // @[BootROM.scala:50:22]
wire [63:0] rom_416 = 64'h406D6F7201000000; // @[BootROM.scala:50:22]
wire [63:0] rom_417 = 64'h3030303031; // @[BootROM.scala:50:22]
wire [63:0] rom_420 = 64'h306D6F722C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_422 = 64'h1002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_423 = 64'h300000000000100; // @[BootROM.scala:50:22]
wire [63:0] rom_424 = 64'hA801000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_425 = 64'h2000000006D656D; // @[BootROM.scala:50:22]
wire [63:0] rom_426 = 64'h7375627301000000; // @[BootROM.scala:50:22]
wire [63:0] rom_392 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_429 = 64'hDE010000; // @[BootROM.scala:50:22]
wire [63:0] rom_394 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_431 = 64'h65CD1D53000000; // @[BootROM.scala:50:22]
wire [63:0] rom_164 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_395 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_432 = 64'hB00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_433 = 64'h73756273EB010000; // @[BootROM.scala:50:22]
wire [63:0] rom_390 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_397 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_427 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_434 = 64'h6B636F6C635F; // @[BootROM.scala:50:22]
wire [63:0] rom_398 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_418 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_435 = 64'hC00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_399 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_436 = 64'h657869661B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_400 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_437 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22]
wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_132 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_200 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_205 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_218 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_228 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_249 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_280 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_318 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_348 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_401 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_438 = 64'h100000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_439 = 64'h31406C6169726573; // @[BootROM.scala:50:22]
wire [63:0] rom_440 = 64'h30303030323030; // @[BootROM.scala:50:22]
wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_109 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_111 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_134 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_140 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_142 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_144 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_146 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_148 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_150 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_152 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_154 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_156 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_158 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_160 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_167 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_169 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_183 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_190 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_197 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_216 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_226 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_276 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_278 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_301 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_391 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_393 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_428 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_430 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_441 = 64'h400000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_442 = 64'h60000003D020000; // @[BootROM.scala:50:22]
wire [63:0] rom_443 = 64'hD00000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_264 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_343 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_419 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_444 = 64'h696669731B000000; // @[BootROM.scala:50:22]
wire [63:0] rom_445 = 64'h30747261752C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_86 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_103 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_115 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_122 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_253 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_268 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_284 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_327 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_352 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_365 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_405 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_446 = 64'h300000000000000; // @[BootROM.scala:50:22]
wire [63:0] rom_447 = 64'h4402000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_304 = 64'h300000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_448 = 64'h300000007000000; // @[BootROM.scala:50:22]
wire [63:0] rom_449 = 64'h5502000004000000; // @[BootROM.scala:50:22]
wire [63:0] rom_80 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_94 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_101 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_124 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_231 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_233 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_367 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_384 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_386 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_450 = 64'h300000001000000; // @[BootROM.scala:50:22]
wire [63:0] rom_211 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_224 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_305 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_334 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_346 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_378 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_451 = 64'h2E01000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_452 = 64'h10000000000210; // @[BootROM.scala:50:22]
wire [63:0] rom_308 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_337 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_381 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_454 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22]
wire [63:0] rom_309 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_338 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_455 = 64'h2000000006C6F72; // @[BootROM.scala:50:22]
wire [63:0] rom_456 = 64'h656C697401000000; // @[BootROM.scala:50:22]
wire [63:0] rom_457 = 64'h732D74657365722D; // @[BootROM.scala:50:22]
wire [63:0] rom_458 = 64'h3131407265747465; // @[BootROM.scala:50:22]
wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_459 = 64'h30303030; // @[BootROM.scala:50:22]
wire [63:0] rom_244 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_271 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_307 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_313 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_336 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_380 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_421 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_453 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_460 = 64'h800000003000000; // @[BootROM.scala:50:22]
wire [63:0] rom_461 = 64'h11002E010000; // @[BootROM.scala:50:22]
wire [63:0] rom_246 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_273 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_315 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_462 = 64'h300000000100000; // @[BootROM.scala:50:22]
wire [63:0] rom_247 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_274 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_316 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_463 = 64'hA801000008000000; // @[BootROM.scala:50:22]
wire [63:0] rom_248 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_275 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_317 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_464 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22]
wire [63:0] rom_199 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_465 = 64'h200000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_466 = 64'h900000002000000; // @[BootROM.scala:50:22]
wire [63:0] rom_467 = 64'h7373657264646123; // @[BootROM.scala:50:22]
wire [63:0] rom_468 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22]
wire [63:0] rom_469 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22]
wire [63:0] rom_470 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_471 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22]
wire [63:0] rom_472 = 64'h69726573006C6564; // @[BootROM.scala:50:22]
wire [63:0] rom_473 = 64'h6F64747300306C61; // @[BootROM.scala:50:22]
wire [63:0] rom_474 = 64'h687461702D7475; // @[BootROM.scala:50:22]
wire [63:0] rom_475 = 64'h65736162656D6974; // @[BootROM.scala:50:22]
wire [63:0] rom_477 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22]
wire [63:0] rom_476 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_478 = 64'h6E6575716572662D; // @[BootROM.scala:50:22]
wire [63:0] rom_479 = 64'h6361632D64007963; // @[BootROM.scala:50:22]
wire [63:0] rom_480 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_481 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_482 = 64'h65732D6568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_483 = 64'h6361632D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_484 = 64'h657A69732D6568; // @[BootROM.scala:50:22]
wire [63:0] rom_485 = 64'h65732D626C742D64; // @[BootROM.scala:50:22]
wire [63:0] rom_486 = 64'h626C742D64007374; // @[BootROM.scala:50:22]
wire [63:0] rom_487 = 64'h656400657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_488 = 64'h7079745F65636976; // @[BootROM.scala:50:22]
wire [63:0] rom_489 = 64'h6177647261680065; // @[BootROM.scala:50:22]
wire [63:0] rom_490 = 64'h2D636578652D6572; // @[BootROM.scala:50:22]
wire [63:0] rom_491 = 64'h696F706B61657262; // @[BootROM.scala:50:22]
wire [63:0] rom_492 = 64'h746E756F632D746E; // @[BootROM.scala:50:22]
wire [63:0] rom_494 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22]
wire [63:0] rom_495 = 64'h61632D6900657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_496 = 64'h737465732D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_493 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_497 = 64'h65686361632D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_498 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22]
wire [63:0] rom_499 = 64'h737465732D626C74; // @[BootROM.scala:50:22]
wire [63:0] rom_500 = 64'h732D626C742D6900; // @[BootROM.scala:50:22]
wire [63:0] rom_501 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22]
wire [63:0] rom_502 = 64'h78656E0065707974; // @[BootROM.scala:50:22]
wire [63:0] rom_503 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22]
wire [63:0] rom_504 = 64'h6572006568636163; // @[BootROM.scala:50:22]
wire [63:0] rom_505 = 64'h2C76637369720067; // @[BootROM.scala:50:22]
wire [63:0] rom_506 = 64'h6373697200617369; // @[BootROM.scala:50:22]
wire [63:0] rom_507 = 64'h617267706D702C76; // @[BootROM.scala:50:22]
wire [63:0] rom_508 = 64'h79746972616C756E; // @[BootROM.scala:50:22]
wire [63:0] rom_509 = 64'h702C766373697200; // @[BootROM.scala:50:22]
wire [63:0] rom_510 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22]
wire [63:0] rom_511 = 64'h7375746174730073; // @[BootROM.scala:50:22]
wire [63:0] rom_512 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22]
wire [63:0] rom_513 = 64'h65746E6923007469; // @[BootROM.scala:50:22]
wire [63:0] rom_514 = 64'h65632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_515 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22]
wire [63:0] rom_120 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_362 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_516 = 64'h6F632D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_121 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_251 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_320 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_363 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_517 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22]
wire [63:0] rom_518 = 64'h656C646E61687000; // @[BootROM.scala:50:22]
wire [63:0] rom_519 = 64'h7365676E617200; // @[BootROM.scala:50:22]
wire [63:0] rom_520 = 64'h656D616E2D676572; // @[BootROM.scala:50:22]
wire [63:0] rom_521 = 64'h2D65686361630073; // @[BootROM.scala:50:22]
wire [63:0] rom_522 = 64'h6163006C6576656C; // @[BootROM.scala:50:22]
wire [63:0] rom_523 = 64'h66696E752D656863; // @[BootROM.scala:50:22]
wire [63:0] rom_524 = 64'h6966697300646569; // @[BootROM.scala:50:22]
wire [63:0] rom_525 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22]
wire [63:0] rom_526 = 64'h632300746E756F63; // @[BootROM.scala:50:22]
wire [63:0] rom_527 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22]
wire [63:0] rom_528 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22]
wire [63:0] rom_529 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22]
wire [63:0] rom_530 = 64'h6E690073656D616E; // @[BootROM.scala:50:22]
wire [63:0] rom_531 = 64'h7374707572726574; // @[BootROM.scala:50:22]
wire [63:0] rom_532 = 64'h65646E657478652D; // @[BootROM.scala:50:22]
wire [63:0] rom_533 = 64'h2D67756265640064; // @[BootROM.scala:50:22]
wire [63:0] rom_534 = 64'h7200686361747461; // @[BootROM.scala:50:22]
wire [63:0] rom_535 = 64'h78616D2C76637369; // @[BootROM.scala:50:22]
wire [63:0] rom_536 = 64'h7469726F6972702D; // @[BootROM.scala:50:22]
wire [63:0] rom_537 = 64'h2C76637369720079; // @[BootROM.scala:50:22]
wire [63:0] rom_538 = 64'h6F6C63007665646E; // @[BootROM.scala:50:22]
wire [63:0] rom_539 = 64'h65746E6900736B63; // @[BootROM.scala:50:22]
wire [63:0] rom_540 = 64'h61702D7470757272; // @[BootROM.scala:50:22]
wire [63:0] rom_541 = 64'h746E6900746E6572; // @[BootROM.scala:50:22]
wire [63:0] rom_542 = 64'h73747075727265; // @[BootROM.scala:50:22]
wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_543 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_544 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_545 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_546 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_547 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_548 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_549 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_550 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_551 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_552 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_553 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_554 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_555 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_556 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_557 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_558 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_559 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_560 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_561 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_562 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_563 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_564 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_565 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_566 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_567 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_568 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_569 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_570 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_571 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_572 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_573 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_574 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_575 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_576 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_577 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_578 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_579 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_580 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_581 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_582 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_583 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_584 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_585 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_586 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_587 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_588 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_589 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_590 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_591 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_592 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_593 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_594 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_595 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_596 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_597 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_598 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_599 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_600 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_601 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_602 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_603 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_604 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_605 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_606 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_607 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_608 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_609 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_610 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_611 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_612 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_613 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_614 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_615 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_616 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_617 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_618 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_619 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_620 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_621 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_622 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_623 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_624 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_625 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_626 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_627 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_628 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_629 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_630 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_631 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_632 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_633 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_634 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_635 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_636 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_637 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_638 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_639 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_640 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_641 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_642 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_643 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_644 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_645 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_646 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_647 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_648 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_649 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_650 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_651 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_652 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_653 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_654 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_655 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_656 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_657 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_658 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_659 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_660 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_661 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_662 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_663 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_664 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_665 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_666 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_667 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_668 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_669 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_670 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_671 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_672 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_673 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_674 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_675 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_676 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_677 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_678 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_679 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_680 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_681 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_682 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_683 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_684 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_685 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_686 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_687 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_688 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_689 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_690 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_691 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_692 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_693 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_694 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_695 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_696 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_697 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_698 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_699 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_700 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_701 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_702 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_703 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_704 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_705 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_706 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_707 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_708 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_709 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_710 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_711 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_712 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_713 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_714 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_715 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_716 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_717 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_718 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_719 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_720 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_721 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_722 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_723 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_724 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_725 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_726 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_727 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_728 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_729 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_730 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_731 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_732 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_733 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_734 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_735 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_736 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_737 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_738 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_739 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_740 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_741 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_742 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_743 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_744 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_745 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_746 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_747 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_748 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_749 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_750 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_751 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_752 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_753 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_754 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_755 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_756 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_757 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_758 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_759 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_760 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_761 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_762 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_763 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_764 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_765 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_766 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_767 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_768 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_769 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_770 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_771 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_772 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_773 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_774 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_775 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_776 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_777 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_778 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_779 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_780 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_781 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_782 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_783 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_784 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_785 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_786 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_787 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_788 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_789 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_790 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_791 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_792 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_793 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_794 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_795 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_796 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_797 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_798 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_799 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_800 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_801 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_802 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_803 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_804 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_805 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_806 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_807 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_808 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_809 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_810 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_811 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_812 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_813 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_814 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_815 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_816 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_817 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_818 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_819 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_820 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_821 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_822 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_823 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_824 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_825 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_826 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_827 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_828 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_829 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_830 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_831 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_832 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_833 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_834 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_835 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_836 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_837 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_838 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_839 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_840 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_841 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_842 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_843 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_844 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_845 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_846 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_847 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_848 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_849 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_850 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_851 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_852 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_853 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_854 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_855 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_856 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_857 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_858 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_859 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_860 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_861 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_862 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_863 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_864 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_865 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_866 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_867 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_868 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_869 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_870 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_871 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_872 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_873 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_874 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_875 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_876 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_877 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_878 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_879 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_880 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_881 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_882 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_883 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_884 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_885 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_886 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_887 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_888 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_889 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_890 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_891 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_892 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_893 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_894 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_895 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_896 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_897 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_898 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_899 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_900 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_901 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_902 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_903 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_904 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_905 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_906 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_907 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_908 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_909 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_910 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_911 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_912 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_913 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_914 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_915 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_916 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_917 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_918 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_919 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_920 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_921 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_922 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_923 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_924 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_925 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_926 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_927 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_928 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_929 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_930 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_931 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_932 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_933 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_934 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_935 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_936 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_937 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_938 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_939 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_940 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_941 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_942 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_943 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_944 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_945 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_946 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_947 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_948 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_949 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_950 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_951 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_952 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_953 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_954 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_955 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_956 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_957 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_958 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_959 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_960 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_961 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_962 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_963 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_964 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_965 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_966 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_967 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_968 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_969 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_970 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_971 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_972 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_973 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_974 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_975 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_976 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_977 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_978 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_979 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_980 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_981 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_982 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_983 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_984 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_985 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_986 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_987 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_988 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_989 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_990 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_991 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_992 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_993 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_994 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_995 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_996 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_997 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_998 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_999 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1000 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1001 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1002 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1003 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1004 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1005 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1006 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1007 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1008 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1009 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1010 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1011 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1012 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1013 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1014 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1015 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1016 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1017 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1018 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1019 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1020 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1021 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1022 = 64'h0; // @[BootROM.scala:50:22]
wire [63:0] rom_1023 = 64'h0; // @[BootROM.scala:50:22]
wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9]
wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17]
wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17]
wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9]
wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9]
wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[BootROM.scala:41:9]
wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
wire [10:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
wire auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9]
assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17]
wire [10:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17]
assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9]
wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9]
wire [9:0] index = nodeIn_a_bits_address[12:3]; // @[BootROM.scala:55:34]
wire [2:0] high = nodeIn_a_bits_address[15:13]; // @[BootROM.scala:56:64]
wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53]
wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}]
assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17]
assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17]
assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17]
assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17]
TLMonitor_54 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLUART :
input clock : Clock
input reset : Reset
output auto : { int_xing_out : { sync : UInt<1>[1]}, flip control_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, io_out : { txd : UInt<1>, flip rxd : UInt<1>}}
inst buffer of TLBuffer_a29d64s12k1z2u
connect buffer.clock, clock
connect buffer.reset, reset
inst intsource of IntSyncCrossingSource_n1x1_5
connect intsource.clock, clock
connect intsource.reset, reset
wire ioNodeOut : { txd : UInt<1>, flip rxd : UInt<1>}
invalidate ioNodeOut.rxd
invalidate ioNodeOut.txd
wire intnodeOut : UInt<1>[1]
invalidate intnodeOut[0]
wire controlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlNodeIn.d.bits.corrupt
invalidate controlNodeIn.d.bits.data
invalidate controlNodeIn.d.bits.denied
invalidate controlNodeIn.d.bits.sink
invalidate controlNodeIn.d.bits.source
invalidate controlNodeIn.d.bits.size
invalidate controlNodeIn.d.bits.param
invalidate controlNodeIn.d.bits.opcode
invalidate controlNodeIn.d.valid
invalidate controlNodeIn.d.ready
invalidate controlNodeIn.a.bits.corrupt
invalidate controlNodeIn.a.bits.data
invalidate controlNodeIn.a.bits.mask
invalidate controlNodeIn.a.bits.address
invalidate controlNodeIn.a.bits.source
invalidate controlNodeIn.a.bits.size
invalidate controlNodeIn.a.bits.param
invalidate controlNodeIn.a.bits.opcode
invalidate controlNodeIn.a.valid
invalidate controlNodeIn.a.ready
inst monitor of TLMonitor_63
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, controlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, controlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, controlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, controlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, controlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, controlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, controlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, controlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, controlNodeIn.d.valid
connect monitor.io.in.d.ready, controlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, controlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, controlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, controlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, controlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, controlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, controlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, controlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, controlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, controlNodeIn.a.valid
connect monitor.io.in.a.ready, controlNodeIn.a.ready
wire controlXingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingOut.d.bits.corrupt
invalidate controlXingOut.d.bits.data
invalidate controlXingOut.d.bits.denied
invalidate controlXingOut.d.bits.sink
invalidate controlXingOut.d.bits.source
invalidate controlXingOut.d.bits.size
invalidate controlXingOut.d.bits.param
invalidate controlXingOut.d.bits.opcode
invalidate controlXingOut.d.valid
invalidate controlXingOut.d.ready
invalidate controlXingOut.a.bits.corrupt
invalidate controlXingOut.a.bits.data
invalidate controlXingOut.a.bits.mask
invalidate controlXingOut.a.bits.address
invalidate controlXingOut.a.bits.source
invalidate controlXingOut.a.bits.size
invalidate controlXingOut.a.bits.param
invalidate controlXingOut.a.bits.opcode
invalidate controlXingOut.a.valid
invalidate controlXingOut.a.ready
wire controlXingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate controlXingIn.d.bits.corrupt
invalidate controlXingIn.d.bits.data
invalidate controlXingIn.d.bits.denied
invalidate controlXingIn.d.bits.sink
invalidate controlXingIn.d.bits.source
invalidate controlXingIn.d.bits.size
invalidate controlXingIn.d.bits.param
invalidate controlXingIn.d.bits.opcode
invalidate controlXingIn.d.valid
invalidate controlXingIn.d.ready
invalidate controlXingIn.a.bits.corrupt
invalidate controlXingIn.a.bits.data
invalidate controlXingIn.a.bits.mask
invalidate controlXingIn.a.bits.address
invalidate controlXingIn.a.bits.source
invalidate controlXingIn.a.bits.size
invalidate controlXingIn.a.bits.param
invalidate controlXingIn.a.bits.opcode
invalidate controlXingIn.a.valid
invalidate controlXingIn.a.ready
connect controlXingOut, controlXingIn
wire intXingOut : { sync : UInt<1>[1]}
invalidate intXingOut.sync[0]
wire intXingIn : { sync : UInt<1>[1]}
invalidate intXingIn.sync[0]
connect intXingOut, intXingIn
connect intsource.auto.in[0], intnodeOut[0]
connect buffer.auto.out.d, controlNodeIn.d
connect controlNodeIn.a.bits, buffer.auto.out.a.bits
connect controlNodeIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, controlNodeIn.a.ready
connect buffer.auto.in, controlXingOut
connect intXingIn, intsource.auto.out
connect auto.io_out, ioNodeOut
connect controlXingIn, auto.control_xing_in
connect auto.int_xing_out, intXingOut
inst txm of UARTTx
connect txm.clock, clock
connect txm.reset, reset
inst txq of Queue8_UInt8
connect txq.clock, clock
connect txq.reset, reset
inst rxm of UARTRx
connect rxm.clock, clock
connect rxm.reset, reset
inst rxq of Queue8_UInt8_1
connect rxq.clock, clock
connect rxq.reset, reset
regreset div : UInt<16>, clock, reset, UInt<16>(0h10f4)
regreset txen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset rxen : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enwire4 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset invpol : UInt<1>, clock, reset, UInt<1>(0h0)
regreset enparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset parity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errorparity : UInt<1>, clock, reset, UInt<1>(0h0)
regreset errie : UInt<1>, clock, reset, UInt<1>(0h0)
regreset txwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset rxwm : UInt<4>, clock, reset, UInt<4>(0h0)
regreset nstop : UInt<1>, clock, reset, UInt<1>(0h0)
regreset data8or9 : UInt<1>, clock, reset, UInt<1>(0h1)
connect txm.io.en, txen
connect txm.io.in, txq.io.deq
connect txm.io.div, div
connect txm.io.nstop, nstop
connect ioNodeOut.txd, txm.io.out
connect rxm.io.en, rxen
connect rxm.io.in, ioNodeOut.rxd
connect rxq.io.enq.valid, rxm.io.out.valid
connect rxq.io.enq.bits, rxm.io.out.bits
connect rxm.io.div, div
node _tx_busy_T = orr(txq.io.count)
node _tx_busy_T_1 = or(txm.io.tx_busy, _tx_busy_T)
node tx_busy = and(_tx_busy_T_1, txen)
wire _ie_WIRE : { rxwm : UInt<1>, txwm : UInt<1>}
connect _ie_WIRE.txwm, UInt<1>(0h0)
connect _ie_WIRE.rxwm, UInt<1>(0h0)
regreset ie : { rxwm : UInt<1>, txwm : UInt<1>}, clock, reset, _ie_WIRE
wire ip : { rxwm : UInt<1>, txwm : UInt<1>}
node _ip_txwm_T = lt(txq.io.count, txwm)
connect ip.txwm, _ip_txwm_T
node _ip_rxwm_T = gt(rxq.io.count, rxwm)
connect ip.rxwm, _ip_rxwm_T
node _intnodeOut_0_T = and(ip.txwm, ie.txwm)
node _intnodeOut_0_T_1 = and(ip.rxwm, ie.rxwm)
node _intnodeOut_0_T_2 = or(_intnodeOut_0_T, _intnodeOut_0_T_1)
connect intnodeOut[0], _intnodeOut_0_T_2
wire quash : UInt<1>
node _T = eq(txq.io.enq.ready, UInt<1>(0h0))
node _T_1 = eq(rxq.io.deq.valid, UInt<1>(0h0))
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
node _in_bits_read_T = eq(controlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(controlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, controlNodeIn.a.bits.data
connect in.bits.mask, controlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, controlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, controlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<12>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h3))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
node _out_T_2 = eq(out_findex, UInt<9>(0h0))
node _out_T_3 = eq(out_bindex, UInt<9>(0h0))
node _out_T_4 = eq(out_findex, UInt<9>(0h0))
node _out_T_5 = eq(out_bindex, UInt<9>(0h0))
node _out_T_6 = eq(out_findex, UInt<9>(0h0))
node _out_T_7 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[16]
wire out_wivalid : UInt<1>[16]
wire out_roready : UInt<1>[16]
wire out_woready : UInt<1>[16]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 7, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 7, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 7, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 7, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_8 = bits(out_front.bits.data, 7, 0)
node _out_txq_io_enq_valid_T = eq(quash, UInt<1>(0h0))
node _out_txq_io_enq_valid_T_1 = and(out_f_woready, _out_txq_io_enq_valid_T)
connect txq.io.enq.valid, _out_txq_io_enq_valid_T_1
connect txq.io.enq.bits, _out_T_8
node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1))
node _out_T_10 = and(UInt<1>(0h1), out_f_woready)
node _out_T_11 = eq(out_rimask, UInt<1>(0h0))
node _out_T_12 = eq(out_wimask, UInt<1>(0h0))
node _out_T_13 = eq(out_romask, UInt<1>(0h0))
node _out_T_14 = eq(out_womask, UInt<1>(0h0))
node _out_T_15 = or(UInt<1>(0h0), UInt<8>(0h0))
node _out_T_16 = bits(_out_T_15, 7, 0)
node _out_rimask_T_1 = bits(out_frontMask, 30, 8)
node out_rimask_1 = orr(_out_rimask_T_1)
node _out_wimask_T_1 = bits(out_frontMask, 30, 8)
node out_wimask_1 = andr(_out_wimask_T_1)
node _out_romask_T_1 = bits(out_backMask, 30, 8)
node out_romask_1 = orr(_out_romask_T_1)
node _out_womask_T_1 = bits(out_backMask, 30, 8)
node out_womask_1 = andr(_out_womask_T_1)
node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1)
node out_f_roready_1 = and(out_roready[1], out_romask_1)
node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1)
node out_f_woready_1 = and(out_woready[1], out_womask_1)
node _out_T_17 = bits(out_front.bits.data, 30, 8)
node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1))
node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1)
node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0))
node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0))
node _out_T_22 = eq(out_romask_1, UInt<1>(0h0))
node _out_T_23 = eq(out_womask_1, UInt<1>(0h0))
node _out_prepend_T = or(_out_T_16, UInt<8>(0h0))
node out_prepend = cat(UInt<1>(0h0), _out_prepend_T)
node _out_T_24 = or(out_prepend, UInt<31>(0h0))
node _out_T_25 = bits(_out_T_24, 30, 0)
node _out_rimask_T_2 = bits(out_frontMask, 31, 31)
node out_rimask_2 = orr(_out_rimask_T_2)
node _out_wimask_T_2 = bits(out_frontMask, 31, 31)
node out_wimask_2 = andr(_out_wimask_T_2)
node _out_romask_T_2 = bits(out_backMask, 31, 31)
node out_romask_2 = orr(_out_romask_T_2)
node _out_womask_T_2 = bits(out_backMask, 31, 31)
node out_womask_2 = andr(_out_womask_T_2)
node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2)
node out_f_roready_2 = and(out_roready[2], out_romask_2)
node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2)
node out_f_woready_2 = and(out_woready[2], out_womask_2)
node _out_T_26 = bits(out_front.bits.data, 31, 31)
node _out_quash_T = bits(_out_T_26, 0, 0)
node _out_quash_T_1 = and(out_f_woready_2, _out_quash_T)
connect quash, _out_quash_T_1
node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1))
node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2)
node _out_T_29 = eq(out_rimask_2, UInt<1>(0h0))
node _out_T_30 = eq(out_wimask_2, UInt<1>(0h0))
node _out_T_31 = eq(out_romask_2, UInt<1>(0h0))
node _out_T_32 = eq(out_womask_2, UInt<1>(0h0))
node _out_prepend_T_1 = or(_out_T_25, UInt<31>(0h0))
node out_prepend_1 = cat(_T, _out_prepend_T_1)
node _out_T_33 = or(out_prepend_1, UInt<32>(0h0))
node _out_T_34 = bits(_out_T_33, 31, 0)
node _out_rimask_T_3 = bits(out_frontMask, 39, 32)
node out_rimask_3 = orr(_out_rimask_T_3)
node _out_wimask_T_3 = bits(out_frontMask, 39, 32)
node out_wimask_3 = andr(_out_wimask_T_3)
node _out_romask_T_3 = bits(out_backMask, 39, 32)
node out_romask_3 = orr(_out_romask_T_3)
node _out_womask_T_3 = bits(out_backMask, 39, 32)
node out_womask_3 = andr(_out_womask_T_3)
node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3)
node out_f_roready_3 = and(out_roready[3], out_romask_3)
node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3)
node out_f_woready_3 = and(out_woready[3], out_womask_3)
connect rxq.io.deq.ready, out_f_roready_3
node _out_T_35 = bits(out_front.bits.data, 39, 32)
node _out_T_36 = and(out_f_rivalid_3, UInt<1>(0h1))
node _out_T_37 = and(UInt<1>(0h1), out_f_roready_3)
node _out_T_38 = eq(out_rimask_3, UInt<1>(0h0))
node _out_T_39 = eq(out_wimask_3, UInt<1>(0h0))
node _out_T_40 = eq(out_romask_3, UInt<1>(0h0))
node _out_T_41 = eq(out_womask_3, UInt<1>(0h0))
node _out_prepend_T_2 = or(_out_T_34, UInt<32>(0h0))
node out_prepend_2 = cat(rxq.io.deq.bits, _out_prepend_T_2)
node _out_T_42 = or(out_prepend_2, UInt<40>(0h0))
node _out_T_43 = bits(_out_T_42, 39, 0)
node _out_rimask_T_4 = bits(out_frontMask, 62, 40)
node out_rimask_4 = orr(_out_rimask_T_4)
node _out_wimask_T_4 = bits(out_frontMask, 62, 40)
node out_wimask_4 = andr(_out_wimask_T_4)
node _out_romask_T_4 = bits(out_backMask, 62, 40)
node out_romask_4 = orr(_out_romask_T_4)
node _out_womask_T_4 = bits(out_backMask, 62, 40)
node out_womask_4 = andr(_out_womask_T_4)
node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4)
node out_f_roready_4 = and(out_roready[4], out_romask_4)
node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4)
node out_f_woready_4 = and(out_woready[4], out_womask_4)
node _out_T_44 = bits(out_front.bits.data, 62, 40)
node _out_T_45 = and(out_f_rivalid_4, UInt<1>(0h1))
node _out_T_46 = and(UInt<1>(0h1), out_f_roready_4)
node _out_T_47 = eq(out_rimask_4, UInt<1>(0h0))
node _out_T_48 = eq(out_wimask_4, UInt<1>(0h0))
node _out_T_49 = eq(out_romask_4, UInt<1>(0h0))
node _out_T_50 = eq(out_womask_4, UInt<1>(0h0))
node _out_prepend_T_3 = or(_out_T_43, UInt<40>(0h0))
node out_prepend_3 = cat(UInt<1>(0h0), _out_prepend_T_3)
node _out_T_51 = or(out_prepend_3, UInt<63>(0h0))
node _out_T_52 = bits(_out_T_51, 62, 0)
node _out_rimask_T_5 = bits(out_frontMask, 63, 63)
node out_rimask_5 = orr(_out_rimask_T_5)
node _out_wimask_T_5 = bits(out_frontMask, 63, 63)
node out_wimask_5 = andr(_out_wimask_T_5)
node _out_romask_T_5 = bits(out_backMask, 63, 63)
node out_romask_5 = orr(_out_romask_T_5)
node _out_womask_T_5 = bits(out_backMask, 63, 63)
node out_womask_5 = andr(_out_womask_T_5)
node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5)
node out_f_roready_5 = and(out_roready[5], out_romask_5)
node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5)
node out_f_woready_5 = and(out_woready[5], out_womask_5)
node _out_T_53 = bits(out_front.bits.data, 63, 63)
node _out_T_54 = and(out_f_rivalid_5, UInt<1>(0h1))
node _out_T_55 = and(UInt<1>(0h1), out_f_roready_5)
node _out_T_56 = eq(out_rimask_5, UInt<1>(0h0))
node _out_T_57 = eq(out_wimask_5, UInt<1>(0h0))
node _out_T_58 = eq(out_romask_5, UInt<1>(0h0))
node _out_T_59 = eq(out_womask_5, UInt<1>(0h0))
node _out_prepend_T_4 = or(_out_T_52, UInt<63>(0h0))
node out_prepend_4 = cat(_T_1, _out_prepend_T_4)
node _out_T_60 = or(out_prepend_4, UInt<64>(0h0))
node _out_T_61 = bits(_out_T_60, 63, 0)
node _out_rimask_T_6 = bits(out_frontMask, 0, 0)
node out_rimask_6 = orr(_out_rimask_T_6)
node _out_wimask_T_6 = bits(out_frontMask, 0, 0)
node out_wimask_6 = andr(_out_wimask_T_6)
node _out_romask_T_6 = bits(out_backMask, 0, 0)
node out_romask_6 = orr(_out_romask_T_6)
node _out_womask_T_6 = bits(out_backMask, 0, 0)
node out_womask_6 = andr(_out_womask_T_6)
node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6)
node out_f_roready_6 = and(out_roready[6], out_romask_6)
node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6)
node out_f_woready_6 = and(out_woready[6], out_womask_6)
node _out_T_62 = bits(out_front.bits.data, 0, 0)
when out_f_woready_6 :
connect txen, _out_T_62
node _out_T_63 = and(out_f_rivalid_6, UInt<1>(0h1))
node _out_T_64 = and(UInt<1>(0h1), out_f_roready_6)
node _out_T_65 = and(out_f_wivalid_6, UInt<1>(0h1))
node _out_T_66 = and(UInt<1>(0h1), out_f_woready_6)
node _out_T_67 = eq(out_rimask_6, UInt<1>(0h0))
node _out_T_68 = eq(out_wimask_6, UInt<1>(0h0))
node _out_T_69 = eq(out_romask_6, UInt<1>(0h0))
node _out_T_70 = eq(out_womask_6, UInt<1>(0h0))
node _out_T_71 = or(txen, UInt<1>(0h0))
node _out_T_72 = bits(_out_T_71, 0, 0)
node _out_rimask_T_7 = bits(out_frontMask, 1, 1)
node out_rimask_7 = orr(_out_rimask_T_7)
node _out_wimask_T_7 = bits(out_frontMask, 1, 1)
node out_wimask_7 = andr(_out_wimask_T_7)
node _out_romask_T_7 = bits(out_backMask, 1, 1)
node out_romask_7 = orr(_out_romask_T_7)
node _out_womask_T_7 = bits(out_backMask, 1, 1)
node out_womask_7 = andr(_out_womask_T_7)
node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7)
node out_f_roready_7 = and(out_roready[7], out_romask_7)
node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7)
node out_f_woready_7 = and(out_woready[7], out_womask_7)
node _out_T_73 = bits(out_front.bits.data, 1, 1)
when out_f_woready_7 :
connect nstop, _out_T_73
node _out_T_74 = and(out_f_rivalid_7, UInt<1>(0h1))
node _out_T_75 = and(UInt<1>(0h1), out_f_roready_7)
node _out_T_76 = and(out_f_wivalid_7, UInt<1>(0h1))
node _out_T_77 = and(UInt<1>(0h1), out_f_woready_7)
node _out_T_78 = eq(out_rimask_7, UInt<1>(0h0))
node _out_T_79 = eq(out_wimask_7, UInt<1>(0h0))
node _out_T_80 = eq(out_romask_7, UInt<1>(0h0))
node _out_T_81 = eq(out_womask_7, UInt<1>(0h0))
node _out_prepend_T_5 = or(_out_T_72, UInt<1>(0h0))
node out_prepend_5 = cat(nstop, _out_prepend_T_5)
node _out_T_82 = or(out_prepend_5, UInt<2>(0h0))
node _out_T_83 = bits(_out_T_82, 1, 0)
node _out_rimask_T_8 = bits(out_frontMask, 19, 16)
node out_rimask_8 = orr(_out_rimask_T_8)
node _out_wimask_T_8 = bits(out_frontMask, 19, 16)
node out_wimask_8 = andr(_out_wimask_T_8)
node _out_romask_T_8 = bits(out_backMask, 19, 16)
node out_romask_8 = orr(_out_romask_T_8)
node _out_womask_T_8 = bits(out_backMask, 19, 16)
node out_womask_8 = andr(_out_womask_T_8)
node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8)
node out_f_roready_8 = and(out_roready[8], out_romask_8)
node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8)
node out_f_woready_8 = and(out_woready[8], out_womask_8)
node _out_T_84 = bits(out_front.bits.data, 19, 16)
when out_f_woready_8 :
connect txwm, _out_T_84
node _out_T_85 = and(out_f_rivalid_8, UInt<1>(0h1))
node _out_T_86 = and(UInt<1>(0h1), out_f_roready_8)
node _out_T_87 = and(out_f_wivalid_8, UInt<1>(0h1))
node _out_T_88 = and(UInt<1>(0h1), out_f_woready_8)
node _out_T_89 = eq(out_rimask_8, UInt<1>(0h0))
node _out_T_90 = eq(out_wimask_8, UInt<1>(0h0))
node _out_T_91 = eq(out_romask_8, UInt<1>(0h0))
node _out_T_92 = eq(out_womask_8, UInt<1>(0h0))
node _out_prepend_T_6 = or(_out_T_83, UInt<16>(0h0))
node out_prepend_6 = cat(txwm, _out_prepend_T_6)
node _out_T_93 = or(out_prepend_6, UInt<20>(0h0))
node _out_T_94 = bits(_out_T_93, 19, 0)
node _out_rimask_T_9 = bits(out_frontMask, 32, 32)
node out_rimask_9 = orr(_out_rimask_T_9)
node _out_wimask_T_9 = bits(out_frontMask, 32, 32)
node out_wimask_9 = andr(_out_wimask_T_9)
node _out_romask_T_9 = bits(out_backMask, 32, 32)
node out_romask_9 = orr(_out_romask_T_9)
node _out_womask_T_9 = bits(out_backMask, 32, 32)
node out_womask_9 = andr(_out_womask_T_9)
node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9)
node out_f_roready_9 = and(out_roready[9], out_romask_9)
node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9)
node out_f_woready_9 = and(out_woready[9], out_womask_9)
node _out_T_95 = bits(out_front.bits.data, 32, 32)
when out_f_woready_9 :
connect rxen, _out_T_95
node _out_T_96 = and(out_f_rivalid_9, UInt<1>(0h1))
node _out_T_97 = and(UInt<1>(0h1), out_f_roready_9)
node _out_T_98 = and(out_f_wivalid_9, UInt<1>(0h1))
node _out_T_99 = and(UInt<1>(0h1), out_f_woready_9)
node _out_T_100 = eq(out_rimask_9, UInt<1>(0h0))
node _out_T_101 = eq(out_wimask_9, UInt<1>(0h0))
node _out_T_102 = eq(out_romask_9, UInt<1>(0h0))
node _out_T_103 = eq(out_womask_9, UInt<1>(0h0))
node _out_prepend_T_7 = or(_out_T_94, UInt<32>(0h0))
node out_prepend_7 = cat(rxen, _out_prepend_T_7)
node _out_T_104 = or(out_prepend_7, UInt<33>(0h0))
node _out_T_105 = bits(_out_T_104, 32, 0)
node _out_rimask_T_10 = bits(out_frontMask, 51, 48)
node out_rimask_10 = orr(_out_rimask_T_10)
node _out_wimask_T_10 = bits(out_frontMask, 51, 48)
node out_wimask_10 = andr(_out_wimask_T_10)
node _out_romask_T_10 = bits(out_backMask, 51, 48)
node out_romask_10 = orr(_out_romask_T_10)
node _out_womask_T_10 = bits(out_backMask, 51, 48)
node out_womask_10 = andr(_out_womask_T_10)
node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10)
node out_f_roready_10 = and(out_roready[10], out_romask_10)
node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10)
node out_f_woready_10 = and(out_woready[10], out_womask_10)
node _out_T_106 = bits(out_front.bits.data, 51, 48)
when out_f_woready_10 :
connect rxwm, _out_T_106
node _out_T_107 = and(out_f_rivalid_10, UInt<1>(0h1))
node _out_T_108 = and(UInt<1>(0h1), out_f_roready_10)
node _out_T_109 = and(out_f_wivalid_10, UInt<1>(0h1))
node _out_T_110 = and(UInt<1>(0h1), out_f_woready_10)
node _out_T_111 = eq(out_rimask_10, UInt<1>(0h0))
node _out_T_112 = eq(out_wimask_10, UInt<1>(0h0))
node _out_T_113 = eq(out_romask_10, UInt<1>(0h0))
node _out_T_114 = eq(out_womask_10, UInt<1>(0h0))
node _out_prepend_T_8 = or(_out_T_105, UInt<48>(0h0))
node out_prepend_8 = cat(rxwm, _out_prepend_T_8)
node _out_T_115 = or(out_prepend_8, UInt<52>(0h0))
node _out_T_116 = bits(_out_T_115, 51, 0)
node _out_rimask_T_11 = bits(out_frontMask, 0, 0)
node out_rimask_11 = orr(_out_rimask_T_11)
node _out_wimask_T_11 = bits(out_frontMask, 0, 0)
node out_wimask_11 = andr(_out_wimask_T_11)
node _out_romask_T_11 = bits(out_backMask, 0, 0)
node out_romask_11 = orr(_out_romask_T_11)
node _out_womask_T_11 = bits(out_backMask, 0, 0)
node out_womask_11 = andr(_out_womask_T_11)
node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11)
node out_f_roready_11 = and(out_roready[11], out_romask_11)
node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11)
node out_f_woready_11 = and(out_woready[11], out_womask_11)
node _out_T_117 = bits(out_front.bits.data, 0, 0)
when out_f_woready_11 :
connect ie.txwm, _out_T_117
node _out_T_118 = and(out_f_rivalid_11, UInt<1>(0h1))
node _out_T_119 = and(UInt<1>(0h1), out_f_roready_11)
node _out_T_120 = and(out_f_wivalid_11, UInt<1>(0h1))
node _out_T_121 = and(UInt<1>(0h1), out_f_woready_11)
node _out_T_122 = eq(out_rimask_11, UInt<1>(0h0))
node _out_T_123 = eq(out_wimask_11, UInt<1>(0h0))
node _out_T_124 = eq(out_romask_11, UInt<1>(0h0))
node _out_T_125 = eq(out_womask_11, UInt<1>(0h0))
node _out_T_126 = or(ie.txwm, UInt<1>(0h0))
node _out_T_127 = bits(_out_T_126, 0, 0)
node _out_rimask_T_12 = bits(out_frontMask, 1, 1)
node out_rimask_12 = orr(_out_rimask_T_12)
node _out_wimask_T_12 = bits(out_frontMask, 1, 1)
node out_wimask_12 = andr(_out_wimask_T_12)
node _out_romask_T_12 = bits(out_backMask, 1, 1)
node out_romask_12 = orr(_out_romask_T_12)
node _out_womask_T_12 = bits(out_backMask, 1, 1)
node out_womask_12 = andr(_out_womask_T_12)
node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12)
node out_f_roready_12 = and(out_roready[12], out_romask_12)
node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12)
node out_f_woready_12 = and(out_woready[12], out_womask_12)
node _out_T_128 = bits(out_front.bits.data, 1, 1)
when out_f_woready_12 :
connect ie.rxwm, _out_T_128
node _out_T_129 = and(out_f_rivalid_12, UInt<1>(0h1))
node _out_T_130 = and(UInt<1>(0h1), out_f_roready_12)
node _out_T_131 = and(out_f_wivalid_12, UInt<1>(0h1))
node _out_T_132 = and(UInt<1>(0h1), out_f_woready_12)
node _out_T_133 = eq(out_rimask_12, UInt<1>(0h0))
node _out_T_134 = eq(out_wimask_12, UInt<1>(0h0))
node _out_T_135 = eq(out_romask_12, UInt<1>(0h0))
node _out_T_136 = eq(out_womask_12, UInt<1>(0h0))
node _out_prepend_T_9 = or(_out_T_127, UInt<1>(0h0))
node out_prepend_9 = cat(ie.rxwm, _out_prepend_T_9)
node _out_T_137 = or(out_prepend_9, UInt<2>(0h0))
node _out_T_138 = bits(_out_T_137, 1, 0)
node _out_rimask_T_13 = bits(out_frontMask, 32, 32)
node out_rimask_13 = orr(_out_rimask_T_13)
node _out_wimask_T_13 = bits(out_frontMask, 32, 32)
node out_wimask_13 = andr(_out_wimask_T_13)
node _out_romask_T_13 = bits(out_backMask, 32, 32)
node out_romask_13 = orr(_out_romask_T_13)
node _out_womask_T_13 = bits(out_backMask, 32, 32)
node out_womask_13 = andr(_out_womask_T_13)
node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13)
node out_f_roready_13 = and(out_roready[13], out_romask_13)
node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13)
node out_f_woready_13 = and(out_woready[13], out_womask_13)
node _out_T_139 = bits(out_front.bits.data, 32, 32)
node _out_T_140 = and(out_f_rivalid_13, UInt<1>(0h1))
node _out_T_141 = and(UInt<1>(0h1), out_f_roready_13)
node _out_T_142 = eq(out_rimask_13, UInt<1>(0h0))
node _out_T_143 = eq(out_wimask_13, UInt<1>(0h0))
node _out_T_144 = eq(out_romask_13, UInt<1>(0h0))
node _out_T_145 = eq(out_womask_13, UInt<1>(0h0))
node _out_prepend_T_10 = or(_out_T_138, UInt<32>(0h0))
node out_prepend_10 = cat(ip.txwm, _out_prepend_T_10)
node _out_T_146 = or(out_prepend_10, UInt<33>(0h0))
node _out_T_147 = bits(_out_T_146, 32, 0)
node _out_rimask_T_14 = bits(out_frontMask, 33, 33)
node out_rimask_14 = orr(_out_rimask_T_14)
node _out_wimask_T_14 = bits(out_frontMask, 33, 33)
node out_wimask_14 = andr(_out_wimask_T_14)
node _out_romask_T_14 = bits(out_backMask, 33, 33)
node out_romask_14 = orr(_out_romask_T_14)
node _out_womask_T_14 = bits(out_backMask, 33, 33)
node out_womask_14 = andr(_out_womask_T_14)
node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14)
node out_f_roready_14 = and(out_roready[14], out_romask_14)
node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14)
node out_f_woready_14 = and(out_woready[14], out_womask_14)
node _out_T_148 = bits(out_front.bits.data, 33, 33)
node _out_T_149 = and(out_f_rivalid_14, UInt<1>(0h1))
node _out_T_150 = and(UInt<1>(0h1), out_f_roready_14)
node _out_T_151 = eq(out_rimask_14, UInt<1>(0h0))
node _out_T_152 = eq(out_wimask_14, UInt<1>(0h0))
node _out_T_153 = eq(out_romask_14, UInt<1>(0h0))
node _out_T_154 = eq(out_womask_14, UInt<1>(0h0))
node _out_prepend_T_11 = or(_out_T_147, UInt<33>(0h0))
node out_prepend_11 = cat(ip.rxwm, _out_prepend_T_11)
node _out_T_155 = or(out_prepend_11, UInt<34>(0h0))
node _out_T_156 = bits(_out_T_155, 33, 0)
node _out_rimask_T_15 = bits(out_frontMask, 15, 0)
node out_rimask_15 = orr(_out_rimask_T_15)
node _out_wimask_T_15 = bits(out_frontMask, 15, 0)
node out_wimask_15 = andr(_out_wimask_T_15)
node _out_romask_T_15 = bits(out_backMask, 15, 0)
node out_romask_15 = orr(_out_romask_T_15)
node _out_womask_T_15 = bits(out_backMask, 15, 0)
node out_womask_15 = andr(_out_womask_T_15)
node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15)
node out_f_roready_15 = and(out_roready[15], out_romask_15)
node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15)
node out_f_woready_15 = and(out_woready[15], out_womask_15)
node _out_T_157 = bits(out_front.bits.data, 15, 0)
when out_f_woready_15 :
connect div, _out_T_157
node _out_T_158 = and(out_f_rivalid_15, UInt<1>(0h1))
node _out_T_159 = and(UInt<1>(0h1), out_f_roready_15)
node _out_T_160 = and(out_f_wivalid_15, UInt<1>(0h1))
node _out_T_161 = and(UInt<1>(0h1), out_f_woready_15)
node _out_T_162 = eq(out_rimask_15, UInt<1>(0h0))
node _out_T_163 = eq(out_wimask_15, UInt<1>(0h0))
node _out_T_164 = eq(out_romask_15, UInt<1>(0h0))
node _out_T_165 = eq(out_womask_15, UInt<1>(0h0))
node _out_T_166 = or(div, UInt<16>(0h0))
node _out_T_167 = bits(_out_T_166, 15, 0)
node _out_iindex_T = bits(out_front.bits.index, 0, 0)
node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_iindex = cat(_out_iindex_T_1, _out_iindex_T)
node _out_oindex_T = bits(out_front.bits.index, 0, 0)
node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1)
node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2)
node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3)
node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4)
node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5)
node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6)
node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7)
node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8)
node out_oindex = cat(_out_oindex_T_1, _out_oindex_T)
node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex)
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node out_frontSel_2 = bits(_out_frontSel_T, 2, 2)
node out_frontSel_3 = bits(_out_frontSel_T, 3, 3)
node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex)
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node out_backSel_2 = bits(_out_backSel_T, 2, 2)
node out_backSel_3 = bits(_out_backSel_T, 3, 3)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[5], _out_rifireMux_T_3
connect out_rivalid[4], _out_rifireMux_T_3
connect out_rivalid[3], _out_rifireMux_T_3
connect out_rivalid[2], _out_rifireMux_T_3
connect out_rivalid[1], _out_rifireMux_T_3
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
wire out_rifireMux_out_1 : UInt<1>
node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1)
node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_2)
connect out_rifireMux_out_1, UInt<1>(0h1)
connect out_rivalid[10], _out_rifireMux_T_7
connect out_rivalid[9], _out_rifireMux_T_7
connect out_rivalid[8], _out_rifireMux_T_7
connect out_rivalid[7], _out_rifireMux_T_7
connect out_rivalid[6], _out_rifireMux_T_7
node _out_rifireMux_T_8 = eq(_out_T_2, UInt<1>(0h0))
node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8)
wire out_rifireMux_out_2 : UInt<1>
node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2)
node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_4)
connect out_rifireMux_out_2, UInt<1>(0h1)
connect out_rivalid[14], _out_rifireMux_T_11
connect out_rivalid[13], _out_rifireMux_T_11
connect out_rivalid[12], _out_rifireMux_T_11
connect out_rivalid[11], _out_rifireMux_T_11
node _out_rifireMux_T_12 = eq(_out_T_4, UInt<1>(0h0))
node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12)
wire out_rifireMux_out_3 : UInt<1>
node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3)
node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, _out_T_6)
connect out_rifireMux_out_3, UInt<1>(0h1)
connect out_rivalid[15], _out_rifireMux_T_15
node _out_rifireMux_T_16 = eq(_out_T_6, UInt<1>(0h0))
node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16)
node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4))
wire _out_rifireMux_WIRE : UInt<1>[4]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9
connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13
connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17
node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[5], _out_wifireMux_T_4
connect out_wivalid[4], _out_wifireMux_T_4
connect out_wivalid[3], _out_wifireMux_T_4
connect out_wivalid[2], _out_wifireMux_T_4
connect out_wivalid[1], _out_wifireMux_T_4
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
wire out_wifireMux_out_1 : UInt<1>
node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1)
node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_2)
connect out_wifireMux_out_1, UInt<1>(0h1)
connect out_wivalid[10], _out_wifireMux_T_8
connect out_wivalid[9], _out_wifireMux_T_8
connect out_wivalid[8], _out_wifireMux_T_8
connect out_wivalid[7], _out_wifireMux_T_8
connect out_wivalid[6], _out_wifireMux_T_8
node _out_wifireMux_T_9 = eq(_out_T_2, UInt<1>(0h0))
node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9)
wire out_wifireMux_out_2 : UInt<1>
node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2)
node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_4)
connect out_wifireMux_out_2, UInt<1>(0h1)
connect out_wivalid[14], _out_wifireMux_T_12
connect out_wivalid[13], _out_wifireMux_T_12
connect out_wivalid[12], _out_wifireMux_T_12
connect out_wivalid[11], _out_wifireMux_T_12
node _out_wifireMux_T_13 = eq(_out_T_4, UInt<1>(0h0))
node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13)
wire out_wifireMux_out_3 : UInt<1>
node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3)
node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, _out_T_6)
connect out_wifireMux_out_3, UInt<1>(0h1)
connect out_wivalid[15], _out_wifireMux_T_16
node _out_wifireMux_T_17 = eq(_out_T_6, UInt<1>(0h0))
node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17)
node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4))
wire _out_wifireMux_WIRE : UInt<1>[4]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10
connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14
connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18
node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[5], _out_rofireMux_T_3
connect out_roready[4], _out_rofireMux_T_3
connect out_roready[3], _out_rofireMux_T_3
connect out_roready[2], _out_rofireMux_T_3
connect out_roready[1], _out_rofireMux_T_3
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
wire out_rofireMux_out_1 : UInt<1>
node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1)
node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_3)
connect out_rofireMux_out_1, UInt<1>(0h1)
connect out_roready[10], _out_rofireMux_T_7
connect out_roready[9], _out_rofireMux_T_7
connect out_roready[8], _out_rofireMux_T_7
connect out_roready[7], _out_rofireMux_T_7
connect out_roready[6], _out_rofireMux_T_7
node _out_rofireMux_T_8 = eq(_out_T_3, UInt<1>(0h0))
node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8)
wire out_rofireMux_out_2 : UInt<1>
node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2)
node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_5)
connect out_rofireMux_out_2, UInt<1>(0h1)
connect out_roready[14], _out_rofireMux_T_11
connect out_roready[13], _out_rofireMux_T_11
connect out_roready[12], _out_rofireMux_T_11
connect out_roready[11], _out_rofireMux_T_11
node _out_rofireMux_T_12 = eq(_out_T_5, UInt<1>(0h0))
node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12)
wire out_rofireMux_out_3 : UInt<1>
node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3)
node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, _out_T_7)
connect out_rofireMux_out_3, UInt<1>(0h1)
connect out_roready[15], _out_rofireMux_T_15
node _out_rofireMux_T_16 = eq(_out_T_7, UInt<1>(0h0))
node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16)
node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4))
wire _out_rofireMux_WIRE : UInt<1>[4]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9
connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13
connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17
node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[5], _out_wofireMux_T_4
connect out_woready[4], _out_wofireMux_T_4
connect out_woready[3], _out_wofireMux_T_4
connect out_woready[2], _out_wofireMux_T_4
connect out_woready[1], _out_wofireMux_T_4
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
wire out_wofireMux_out_1 : UInt<1>
node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1)
node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_3)
connect out_wofireMux_out_1, UInt<1>(0h1)
connect out_woready[10], _out_wofireMux_T_8
connect out_woready[9], _out_wofireMux_T_8
connect out_woready[8], _out_wofireMux_T_8
connect out_woready[7], _out_wofireMux_T_8
connect out_woready[6], _out_wofireMux_T_8
node _out_wofireMux_T_9 = eq(_out_T_3, UInt<1>(0h0))
node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9)
wire out_wofireMux_out_2 : UInt<1>
node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2)
node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_5)
connect out_wofireMux_out_2, UInt<1>(0h1)
connect out_woready[14], _out_wofireMux_T_12
connect out_woready[13], _out_wofireMux_T_12
connect out_woready[12], _out_wofireMux_T_12
connect out_woready[11], _out_wofireMux_T_12
node _out_wofireMux_T_13 = eq(_out_T_5, UInt<1>(0h0))
node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13)
wire out_wofireMux_out_3 : UInt<1>
node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3)
node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, _out_T_7)
connect out_wofireMux_out_3, UInt<1>(0h1)
connect out_woready[15], _out_wofireMux_T_16
node _out_wofireMux_T_17 = eq(_out_T_7, UInt<1>(0h0))
node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17)
node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4))
wire _out_wofireMux_WIRE : UInt<1>[4]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10
connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14
connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18
node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE : UInt<1>[4]
connect _out_out_bits_data_WIRE[0], _out_T_1
connect _out_out_bits_data_WIRE[1], _out_T_3
connect _out_out_bits_data_WIRE[2], _out_T_5
connect _out_out_bits_data_WIRE[3], _out_T_7
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex])
node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4))
wire _out_out_bits_data_WIRE_1 : UInt<64>[4]
connect _out_out_bits_data_WIRE_1[0], _out_T_61
connect _out_out_bits_data_WIRE_1[1], _out_T_116
connect _out_out_bits_data_WIRE_1[2], _out_T_156
connect _out_out_bits_data_WIRE_1[3], _out_T_167
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, controlNodeIn.a.valid
connect controlNodeIn.a.ready, in.ready
connect controlNodeIn.d.valid, out.valid
connect out.ready, controlNodeIn.d.ready
wire controlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect controlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect controlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect controlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect controlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate controlNodeIn_d_bits_d.data
connect controlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect controlNodeIn.d.bits.corrupt, controlNodeIn_d_bits_d.corrupt
connect controlNodeIn.d.bits.data, controlNodeIn_d_bits_d.data
connect controlNodeIn.d.bits.denied, controlNodeIn_d_bits_d.denied
connect controlNodeIn.d.bits.sink, controlNodeIn_d_bits_d.sink
connect controlNodeIn.d.bits.source, controlNodeIn_d_bits_d.source
connect controlNodeIn.d.bits.size, controlNodeIn_d_bits_d.size
connect controlNodeIn.d.bits.param, controlNodeIn_d_bits_d.param
connect controlNodeIn.d.bits.opcode, controlNodeIn_d_bits_d.opcode
connect controlNodeIn.d.bits.data, out.bits.data
node _controlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect controlNodeIn.d.bits.opcode, _controlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1) | module TLUART( // @[UART.scala:127:25]
input clock, // @[UART.scala:127:25]
input reset, // @[UART.scala:127:25]
output auto_int_xing_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_control_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_control_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_control_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_control_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_control_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_control_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_control_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_control_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_control_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_control_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_control_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_control_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_io_out_txd, // @[LazyModuleImp.scala:107:25]
input auto_io_out_rxd // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [11:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire [11:0] buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [11:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire [11:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [11:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire _rxq_io_deq_valid; // @[UART.scala:133:19]
wire [7:0] _rxq_io_deq_bits; // @[UART.scala:133:19]
wire [3:0] _rxq_io_count; // @[UART.scala:133:19]
wire _rxm_io_out_valid; // @[UART.scala:132:19]
wire [7:0] _rxm_io_out_bits; // @[UART.scala:132:19]
wire _txq_io_enq_ready; // @[UART.scala:130:19]
wire _txq_io_deq_valid; // @[UART.scala:130:19]
wire [7:0] _txq_io_deq_bits; // @[UART.scala:130:19]
wire [3:0] _txq_io_count; // @[UART.scala:130:19]
wire _txm_io_in_ready; // @[UART.scala:129:19]
wire _txm_io_tx_busy; // @[UART.scala:129:19]
wire auto_control_xing_in_a_valid_0 = auto_control_xing_in_a_valid; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_opcode_0 = auto_control_xing_in_a_bits_opcode; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_a_bits_param_0 = auto_control_xing_in_a_bits_param; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_a_bits_size_0 = auto_control_xing_in_a_bits_size; // @[UART.scala:127:25]
wire [11:0] auto_control_xing_in_a_bits_source_0 = auto_control_xing_in_a_bits_source; // @[UART.scala:127:25]
wire [28:0] auto_control_xing_in_a_bits_address_0 = auto_control_xing_in_a_bits_address; // @[UART.scala:127:25]
wire [7:0] auto_control_xing_in_a_bits_mask_0 = auto_control_xing_in_a_bits_mask; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_a_bits_data_0 = auto_control_xing_in_a_bits_data; // @[UART.scala:127:25]
wire auto_control_xing_in_a_bits_corrupt_0 = auto_control_xing_in_a_bits_corrupt; // @[UART.scala:127:25]
wire auto_control_xing_in_d_ready_0 = auto_control_xing_in_d_ready; // @[UART.scala:127:25]
wire auto_io_out_rxd_0 = auto_io_out_rxd; // @[UART.scala:127:25]
wire [8:0] out_maskMatch = 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_16 = 8'h0; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h0; // @[RegisterRouter.scala:87:24]
wire [8:0] out_prepend = 9'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_24 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_T_25 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [30:0] _out_prepend_T_1 = 31'h0; // @[RegisterRouter.scala:87:24]
wire [2:0] controlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] controlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_control_xing_in_d_bits_sink = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_denied = 1'h0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_bits_corrupt = 1'h0; // @[UART.scala:127:25]
wire buffer_auto_in_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_sink = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_denied = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingOut_d_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire controlXingIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire controlXingIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _ie_WIRE_rxwm = 1'h0; // @[UART.scala:186:32]
wire _ie_WIRE_txwm = 1'h0; // @[UART.scala:186:32]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire controlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire controlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_control_xing_in_d_bits_param = 2'h0; // @[UART.scala:127:25]
wire [1:0] buffer_auto_in_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] controlXingIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] controlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire controlXingIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingIn_a_valid = auto_control_xing_in_a_valid_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_opcode = auto_control_xing_in_a_bits_opcode_0; // @[UART.scala:127:25]
wire [2:0] controlXingIn_a_bits_param = auto_control_xing_in_a_bits_param_0; // @[UART.scala:127:25]
wire [1:0] controlXingIn_a_bits_size = auto_control_xing_in_a_bits_size_0; // @[UART.scala:127:25]
wire [11:0] controlXingIn_a_bits_source = auto_control_xing_in_a_bits_source_0; // @[UART.scala:127:25]
wire [28:0] controlXingIn_a_bits_address = auto_control_xing_in_a_bits_address_0; // @[UART.scala:127:25]
wire [7:0] controlXingIn_a_bits_mask = auto_control_xing_in_a_bits_mask_0; // @[UART.scala:127:25]
wire [63:0] controlXingIn_a_bits_data = auto_control_xing_in_a_bits_data_0; // @[UART.scala:127:25]
wire controlXingIn_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt_0; // @[UART.scala:127:25]
wire controlXingIn_d_ready = auto_control_xing_in_d_ready_0; // @[UART.scala:127:25]
wire controlXingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] controlXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] controlXingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] controlXingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] controlXingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire ioNodeOut_txd; // @[MixedNode.scala:542:17]
wire ioNodeOut_rxd = auto_io_out_rxd_0; // @[UART.scala:127:25]
wire auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
wire auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
wire [2:0] auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
wire [1:0] auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
wire [11:0] auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
wire [63:0] auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
wire auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
wire auto_io_out_txd_0; // @[UART.scala:127:25]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire controlXingOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire controlXingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [1:0] controlXingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [11:0] controlXingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [11:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] controlXingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] controlXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] controlXingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire controlXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = buffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlXingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire controlXingOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlXingOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [11:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [1:0] controlXingOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [11:0] controlXingOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] controlXingOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire controlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_valid = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] controlNodeIn_a_bits_param = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [11:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [1:0] controlNodeIn_a_bits_size = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [28:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [11:0] controlNodeIn_a_bits_source = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [7:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] controlNodeIn_a_bits_address = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [63:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] controlNodeIn_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] controlNodeIn_a_bits_data = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire controlNodeIn_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire controlNodeIn_d_ready = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire controlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] controlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [11:0] controlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [11:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] controlNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_corrupt = buffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_corrupt = buffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_io_out_txd_0 = ioNodeOut_txd; // @[UART.scala:127:25]
wire _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire intnodeOut_0; // @[MixedNode.scala:542:17]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign buffer_auto_out_a_ready = controlNodeIn_a_ready; // @[Buffer.scala:40:9]
wire in_valid = controlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = controlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [11:0] in_bits_extra_tlrr_extra_source = controlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = controlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = controlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = controlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_valid = controlNodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_bits_opcode = controlNodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_size = controlNodeIn_d_bits_size; // @[Buffer.scala:40:9]
wire [11:0] controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign buffer_auto_out_d_bits_source = controlNodeIn_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign buffer_auto_out_d_bits_data = controlNodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign controlXingIn_a_ready = controlXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = controlXingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = controlXingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = controlXingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = controlXingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = controlXingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = controlXingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = controlXingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = controlXingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_corrupt = controlXingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = controlXingOut_d_ready; // @[Buffer.scala:40:9]
assign controlXingIn_d_valid = controlXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_opcode = controlXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_size = controlXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_source = controlXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingIn_d_bits_data = controlXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_a_ready_0 = controlXingIn_a_ready; // @[UART.scala:127:25]
assign controlXingOut_a_valid = controlXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_opcode = controlXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_param = controlXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_size = controlXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_source = controlXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_address = controlXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_mask = controlXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_data = controlXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_a_bits_corrupt = controlXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign controlXingOut_d_ready = controlXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_control_xing_in_d_valid_0 = controlXingIn_d_valid; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode_0 = controlXingIn_d_bits_opcode; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size_0 = controlXingIn_d_bits_size; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source_0 = controlXingIn_d_bits_source; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data_0 = controlXingIn_d_bits_data; // @[UART.scala:127:25]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
assign auto_int_xing_out_sync_0_0 = intXingOut_sync_0; // @[UART.scala:127:25]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
reg [15:0] div; // @[UART.scala:135:20]
wire [15:0] _out_T_166 = div; // @[RegisterRouter.scala:87:24]
reg txen; // @[UART.scala:141:21]
wire _out_T_71 = txen; // @[RegisterRouter.scala:87:24]
reg rxen; // @[UART.scala:142:21]
reg [3:0] txwm; // @[UART.scala:149:21]
reg [3:0] rxwm; // @[UART.scala:150:21]
reg nstop; // @[UART.scala:151:22]
wire _tx_busy_T = |_txq_io_count; // @[UART.scala:130:19, :175:49]
wire _tx_busy_T_1 = _txm_io_tx_busy | _tx_busy_T; // @[UART.scala:129:19, :175:{33,49}]
wire tx_busy = _tx_busy_T_1 & txen; // @[UART.scala:141:21, :175:{33,54}]
reg ie_rxwm; // @[UART.scala:186:19]
reg ie_txwm; // @[UART.scala:186:19]
wire _out_T_126 = ie_txwm; // @[RegisterRouter.scala:87:24]
wire _ip_rxwm_T; // @[UART.scala:190:28]
wire _ip_txwm_T; // @[UART.scala:189:28]
wire ip_rxwm; // @[UART.scala:187:16]
wire ip_txwm; // @[UART.scala:187:16]
assign _ip_txwm_T = _txq_io_count < txwm; // @[UART.scala:130:19, :149:21, :189:28]
assign ip_txwm = _ip_txwm_T; // @[UART.scala:187:16, :189:28]
assign _ip_rxwm_T = _rxq_io_count > rxwm; // @[UART.scala:133:19, :150:21, :190:28]
assign ip_rxwm = _ip_rxwm_T; // @[UART.scala:187:16, :190:28]
wire _intnodeOut_0_T = ip_txwm & ie_txwm; // @[UART.scala:186:19, :187:16, :191:29]
wire _intnodeOut_0_T_1 = ip_rxwm & ie_rxwm; // @[UART.scala:186:19, :187:16, :191:53]
assign _intnodeOut_0_T_2 = _intnodeOut_0_T | _intnodeOut_0_T_1; // @[UART.scala:191:{29,41,53}]
assign intnodeOut_0 = _intnodeOut_0_T_2; // @[UART.scala:191:41]
wire _out_quash_T_1; // @[RegMapFIFO.scala:26:26]
wire quash; // @[RegMapFIFO.scala:11:21]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [11:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = controlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [25:0] _in_bits_index_T = controlNodeIn_a_bits_address[28:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _controlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign controlNodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire [8:0] _GEN = out_front_bits_index & 9'h1FC; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex; // @[RegisterRouter.scala:87:24]
assign out_findex = _GEN; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex; // @[RegisterRouter.scala:87:24]
assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_6; // @[RegisterRouter.scala:87:24]
assign _out_T_6 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_7; // @[RegisterRouter.scala:87:24]
assign _out_T_7 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_7; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_rivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire out_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_wivalid_13; // @[RegisterRouter.scala:87:24]
wire out_wivalid_14; // @[RegisterRouter.scala:87:24]
wire out_wivalid_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire out_roready_6; // @[RegisterRouter.scala:87:24]
wire out_roready_7; // @[RegisterRouter.scala:87:24]
wire out_roready_8; // @[RegisterRouter.scala:87:24]
wire out_roready_9; // @[RegisterRouter.scala:87:24]
wire out_roready_10; // @[RegisterRouter.scala:87:24]
wire out_roready_11; // @[RegisterRouter.scala:87:24]
wire out_roready_12; // @[RegisterRouter.scala:87:24]
wire out_roready_13; // @[RegisterRouter.scala:87:24]
wire out_roready_14; // @[RegisterRouter.scala:87:24]
wire out_roready_15; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire out_woready_6; // @[RegisterRouter.scala:87:24]
wire out_woready_7; // @[RegisterRouter.scala:87:24]
wire out_woready_8; // @[RegisterRouter.scala:87:24]
wire out_woready_9; // @[RegisterRouter.scala:87:24]
wire out_woready_10; // @[RegisterRouter.scala:87:24]
wire out_woready_11; // @[RegisterRouter.scala:87:24]
wire out_woready_12; // @[RegisterRouter.scala:87:24]
wire out_woready_13; // @[RegisterRouter.scala:87:24]
wire out_woready_14; // @[RegisterRouter.scala:87:24]
wire out_woready_15; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_8 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_txq_io_enq_valid_T = ~quash; // @[RegMapFIFO.scala:11:21, :18:33]
wire _out_txq_io_enq_valid_T_1 = out_f_woready & _out_txq_io_enq_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_1 = out_frontMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_1 = out_backMask[30:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_17 = out_front_bits_data[30:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_2 = out_frontMask[31]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_2 = out_backMask[31]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_front_bits_data[31]; // @[RegisterRouter.scala:87:24]
wire _out_quash_T = _out_T_26; // @[RegisterRouter.scala:87:24]
assign _out_quash_T_1 = out_f_woready_2 & _out_quash_T; // @[RegisterRouter.scala:87:24]
assign quash = _out_quash_T_1; // @[RegMapFIFO.scala:11:21, :26:26]
wire _out_T_29 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_31 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_32 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [31:0] out_prepend_1 = {~_txq_io_enq_ready, 31'h0}; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_33 = out_prepend_1; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_34 = _out_T_33; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_2 = _out_T_34; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_35 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_40 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_41 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire [39:0] out_prepend_2 = {_rxq_io_deq_bits, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_42 = out_prepend_2; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_T_43 = _out_T_42; // @[RegisterRouter.scala:87:24]
wire [39:0] _out_prepend_T_3 = _out_T_43; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_rimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_wimask_T_4 = out_frontMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_romask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_womask_T_4 = out_backMask[62:40]; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_45 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = out_f_roready_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire [22:0] _out_T_44 = out_front_bits_data[62:40]; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire [40:0] out_prepend_3 = {1'h0, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_51 = {22'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_T_52 = _out_T_51; // @[RegisterRouter.scala:87:24]
wire [62:0] _out_prepend_T_4 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_5 = out_frontMask[63]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = _out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = _out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_5 = out_backMask[63]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = _out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = _out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_54 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_55 = out_f_roready_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_53 = out_front_bits_data[63]; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_57 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_58 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire [63:0] out_prepend_4 = {~_rxq_io_deq_valid, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_60 = out_prepend_4; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_61 = _out_T_60; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = _out_T_61; // @[MuxLiteral.scala:49:48]
wire _out_rimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_6 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_11 = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_6 = _out_rimask_T_6; // @[RegisterRouter.scala:87:24]
wire out_wimask_6 = _out_wimask_T_6; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_6 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_11 = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask_6 = _out_romask_T_6; // @[RegisterRouter.scala:87:24]
wire out_womask_6 = _out_womask_T_6; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = out_f_roready_6; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24]
wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_66 = out_f_woready_6; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_117 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_67 = ~out_rimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_68 = ~out_wimask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_69 = ~out_romask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_70 = ~out_womask_6; // @[RegisterRouter.scala:87:24]
wire _out_T_72 = _out_T_71; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_5 = _out_T_72; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_7 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_12 = out_frontMask[1]; // @[RegisterRouter.scala:87:24]
wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24]
wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_7 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_12 = out_backMask[1]; // @[RegisterRouter.scala:87:24]
wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24]
wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_74 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_75 = out_f_roready_7; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_76 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24]
wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_77 = out_f_woready_7; // @[RegisterRouter.scala:87:24]
wire _out_T_73 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_128 = out_front_bits_data[1]; // @[RegisterRouter.scala:87:24]
wire _out_T_78 = ~out_rimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_79 = ~out_wimask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_80 = ~out_romask_7; // @[RegisterRouter.scala:87:24]
wire _out_T_81 = ~out_womask_7; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_5 = {nstop, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_82 = out_prepend_5; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_83 = _out_T_82; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_8 = out_frontMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24]
wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_8 = out_backMask[19:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24]
wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_85 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_86 = out_f_roready_8; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_87 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24]
wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_88 = out_f_woready_8; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_84 = out_front_bits_data[19:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_89 = ~out_rimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_90 = ~out_wimask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_91 = ~out_romask_8; // @[RegisterRouter.scala:87:24]
wire _out_T_92 = ~out_womask_8; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_6 = {14'h0, _out_T_83}; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_6 = {txwm, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_93 = out_prepend_6; // @[RegisterRouter.scala:87:24]
wire [19:0] _out_T_94 = _out_T_93; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_9 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_13 = out_frontMask[32]; // @[RegisterRouter.scala:87:24]
wire out_rimask_9 = _out_rimask_T_9; // @[RegisterRouter.scala:87:24]
wire out_wimask_9 = _out_wimask_T_9; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_9 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_13 = out_backMask[32]; // @[RegisterRouter.scala:87:24]
wire out_romask_9 = _out_romask_T_9; // @[RegisterRouter.scala:87:24]
wire out_womask_9 = _out_womask_T_9; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_96 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_97 = out_f_roready_9; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_98 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24]
wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_99 = out_f_woready_9; // @[RegisterRouter.scala:87:24]
wire _out_T_95 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_139 = out_front_bits_data[32]; // @[RegisterRouter.scala:87:24]
wire _out_T_100 = ~out_rimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_101 = ~out_wimask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_102 = ~out_romask_9; // @[RegisterRouter.scala:87:24]
wire _out_T_103 = ~out_womask_9; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_7 = {12'h0, _out_T_94}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_7 = {rxen, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_104 = out_prepend_7; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_rimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_wimask_T_10 = out_frontMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24]
wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_romask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_womask_T_10 = out_backMask[51:48]; // @[RegisterRouter.scala:87:24]
wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24]
wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_107 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_108 = out_f_roready_10; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_109 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24]
wire out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_110 = out_f_woready_10; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_T_106 = out_front_bits_data[51:48]; // @[RegisterRouter.scala:87:24]
wire _out_T_111 = ~out_rimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_112 = ~out_wimask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_113 = ~out_romask_10; // @[RegisterRouter.scala:87:24]
wire _out_T_114 = ~out_womask_10; // @[RegisterRouter.scala:87:24]
wire [47:0] _out_prepend_T_8 = {15'h0, _out_T_105}; // @[RegisterRouter.scala:87:24]
wire [51:0] out_prepend_8 = {rxwm, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_115 = out_prepend_8; // @[RegisterRouter.scala:87:24]
wire [51:0] _out_T_116 = _out_T_115; // @[RegisterRouter.scala:87:24]
wire out_rimask_11 = _out_rimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_wimask_11 = _out_wimask_T_11; // @[RegisterRouter.scala:87:24]
wire out_romask_11 = _out_romask_T_11; // @[RegisterRouter.scala:87:24]
wire out_womask_11 = _out_womask_T_11; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_118 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_119 = out_f_roready_11; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_120 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24]
wire out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_121 = out_f_woready_11; // @[RegisterRouter.scala:87:24]
wire _out_T_122 = ~out_rimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_123 = ~out_wimask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_124 = ~out_romask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_125 = ~out_womask_11; // @[RegisterRouter.scala:87:24]
wire _out_T_127 = _out_T_126; // @[RegisterRouter.scala:87:24]
wire _out_prepend_T_9 = _out_T_127; // @[RegisterRouter.scala:87:24]
wire out_rimask_12 = _out_rimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_wimask_12 = _out_wimask_T_12; // @[RegisterRouter.scala:87:24]
wire out_romask_12 = _out_romask_T_12; // @[RegisterRouter.scala:87:24]
wire out_womask_12 = _out_womask_T_12; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_129 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_130 = out_f_roready_12; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_131 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24]
wire out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_132 = out_f_woready_12; // @[RegisterRouter.scala:87:24]
wire _out_T_133 = ~out_rimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_134 = ~out_wimask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_135 = ~out_romask_12; // @[RegisterRouter.scala:87:24]
wire _out_T_136 = ~out_womask_12; // @[RegisterRouter.scala:87:24]
wire [1:0] out_prepend_9 = {ie_rxwm, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_137 = out_prepend_9; // @[RegisterRouter.scala:87:24]
wire [1:0] _out_T_138 = _out_T_137; // @[RegisterRouter.scala:87:24]
wire out_rimask_13 = _out_rimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_wimask_13 = _out_wimask_T_13; // @[RegisterRouter.scala:87:24]
wire out_romask_13 = _out_romask_T_13; // @[RegisterRouter.scala:87:24]
wire out_womask_13 = _out_womask_T_13; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_140 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24]
wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_141 = out_f_roready_13; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24]
wire out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_142 = ~out_rimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_143 = ~out_wimask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_144 = ~out_romask_13; // @[RegisterRouter.scala:87:24]
wire _out_T_145 = ~out_womask_13; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_prepend_T_10 = {30'h0, _out_T_138}; // @[RegisterRouter.scala:87:24]
wire [32:0] out_prepend_10 = {ip_txwm, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_146 = out_prepend_10; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_T_147 = _out_T_146; // @[RegisterRouter.scala:87:24]
wire [32:0] _out_prepend_T_11 = _out_T_147; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T_14 = out_frontMask[33]; // @[RegisterRouter.scala:87:24]
wire out_rimask_14 = _out_rimask_T_14; // @[RegisterRouter.scala:87:24]
wire out_wimask_14 = _out_wimask_T_14; // @[RegisterRouter.scala:87:24]
wire _out_romask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T_14 = out_backMask[33]; // @[RegisterRouter.scala:87:24]
wire out_romask_14 = _out_romask_T_14; // @[RegisterRouter.scala:87:24]
wire out_womask_14 = _out_womask_T_14; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_149 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24]
wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_150 = out_f_roready_14; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24]
wire out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_148 = out_front_bits_data[33]; // @[RegisterRouter.scala:87:24]
wire _out_T_151 = ~out_rimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_152 = ~out_wimask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_153 = ~out_romask_14; // @[RegisterRouter.scala:87:24]
wire _out_T_154 = ~out_womask_14; // @[RegisterRouter.scala:87:24]
wire [33:0] out_prepend_11 = {ip_rxwm, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_155 = out_prepend_11; // @[RegisterRouter.scala:87:24]
wire [33:0] _out_T_156 = _out_T_155; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_rimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_wimask_T_15 = out_frontMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24]
wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_romask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_womask_T_15 = out_backMask[15:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24]
wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_158 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_159 = out_f_roready_15; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_160 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24]
wire out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_161 = out_f_woready_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_157 = out_front_bits_data[15:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_162 = ~out_rimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_163 = ~out_wimask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_164 = ~out_romask_15; // @[RegisterRouter.scala:87:24]
wire _out_T_165 = ~out_womask_15; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_167 = _out_T_166; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_1, _out_iindex_T}; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_1, _out_oindex_T}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_6 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_7 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_8 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_9 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_8 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_11 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_12 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_13 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_rivalid_14 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_rivalid_15 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_6 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_7 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_8 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_9 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_9 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_11 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_12 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_13 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_wivalid_14 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_13 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_6; // @[RegisterRouter.scala:87:24]
assign out_wivalid_15 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_17 = ~_out_T_6; // @[RegisterRouter.scala:87:24]
wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_6 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_7 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_8 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_9 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_8 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_11 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_12 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_13 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
assign out_roready_14 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_roready_15 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_6 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_7 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_8 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_9 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_9 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_11 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_12 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_13 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
assign out_woready_14 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_13 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_7; // @[RegisterRouter.scala:87:24]
assign out_woready_15 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_17 = ~_out_T_7; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_4 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_WIRE_1_1 = {12'h0, _out_T_116}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = {30'h0, _out_T_156}; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = {48'h0, _out_T_167}; // @[MuxLiteral.scala:49:48]
wire [3:0][63:0] _GEN_5 = {{_out_out_bits_data_WIRE_1_3}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign controlNodeIn_d_bits_size = controlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_source = controlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign controlNodeIn_d_bits_opcode = {2'h0, _controlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
always @(posedge clock) begin // @[UART.scala:127:25]
if (reset) begin // @[UART.scala:127:25]
div <= 16'h10F4; // @[UART.scala:135:20]
txen <= 1'h0; // @[UART.scala:141:21]
rxen <= 1'h0; // @[UART.scala:142:21]
txwm <= 4'h0; // @[UART.scala:149:21]
rxwm <= 4'h0; // @[UART.scala:150:21]
nstop <= 1'h0; // @[UART.scala:151:22]
ie_rxwm <= 1'h0; // @[UART.scala:186:19]
ie_txwm <= 1'h0; // @[UART.scala:186:19]
end
else begin // @[UART.scala:127:25]
if (out_f_woready_15) // @[RegisterRouter.scala:87:24]
div <= _out_T_157; // @[RegisterRouter.scala:87:24]
if (out_f_woready_6) // @[RegisterRouter.scala:87:24]
txen <= _out_T_62; // @[RegisterRouter.scala:87:24]
if (out_f_woready_9) // @[RegisterRouter.scala:87:24]
rxen <= _out_T_95; // @[RegisterRouter.scala:87:24]
if (out_f_woready_8) // @[RegisterRouter.scala:87:24]
txwm <= _out_T_84; // @[RegisterRouter.scala:87:24]
if (out_f_woready_10) // @[RegisterRouter.scala:87:24]
rxwm <= _out_T_106; // @[RegisterRouter.scala:87:24]
if (out_f_woready_7) // @[RegisterRouter.scala:87:24]
nstop <= _out_T_73; // @[RegisterRouter.scala:87:24]
if (out_f_woready_12) // @[RegisterRouter.scala:87:24]
ie_rxwm <= _out_T_128; // @[RegisterRouter.scala:87:24]
if (out_f_woready_11) // @[RegisterRouter.scala:87:24]
ie_txwm <= _out_T_117; // @[RegisterRouter.scala:87:24]
end
always @(posedge)
IntSyncCrossingSource_n1x1_5 intsource ( // @[Crossing.scala:29:31]
.clock (clock),
.reset (reset),
.auto_in_0 (intnodeOut_0), // @[MixedNode.scala:542:17]
.auto_out_sync_0 (intXingIn_sync_0)
); // @[Crossing.scala:29:31]
TLMonitor_63 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (controlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (controlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (controlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (controlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (controlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (controlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (controlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (controlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (controlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (controlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (controlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (controlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (controlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (controlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (controlNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (controlNodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
UARTTx txm ( // @[UART.scala:129:19]
.clock (clock),
.reset (reset),
.io_en (txen), // @[UART.scala:141:21]
.io_in_ready (_txm_io_in_ready),
.io_in_valid (_txq_io_deq_valid), // @[UART.scala:130:19]
.io_in_bits (_txq_io_deq_bits), // @[UART.scala:130:19]
.io_out (ioNodeOut_txd),
.io_div (div), // @[UART.scala:135:20]
.io_nstop (nstop), // @[UART.scala:151:22]
.io_tx_busy (_txm_io_tx_busy)
); // @[UART.scala:129:19]
Queue8_UInt8 txq ( // @[UART.scala:130:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_txq_io_enq_ready),
.io_enq_valid (_out_txq_io_enq_valid_T_1), // @[RegMapFIFO.scala:18:30]
.io_enq_bits (_out_T_8), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_txm_io_in_ready), // @[UART.scala:129:19]
.io_deq_valid (_txq_io_deq_valid),
.io_deq_bits (_txq_io_deq_bits),
.io_count (_txq_io_count)
); // @[UART.scala:130:19]
UARTRx rxm ( // @[UART.scala:132:19]
.clock (clock),
.reset (reset),
.io_en (rxen), // @[UART.scala:142:21]
.io_in (ioNodeOut_rxd), // @[MixedNode.scala:542:17]
.io_out_valid (_rxm_io_out_valid),
.io_out_bits (_rxm_io_out_bits),
.io_div (div) // @[UART.scala:135:20]
); // @[UART.scala:132:19]
Queue8_UInt8_1 rxq ( // @[UART.scala:133:19]
.clock (clock),
.reset (reset),
.io_enq_valid (_rxm_io_out_valid), // @[UART.scala:132:19]
.io_enq_bits (_rxm_io_out_bits), // @[UART.scala:132:19]
.io_deq_ready (out_f_roready_3), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_rxq_io_deq_valid),
.io_deq_bits (_rxq_io_deq_bits),
.io_count (_rxq_io_count)
); // @[UART.scala:133:19]
assign auto_int_xing_out_sync_0 = auto_int_xing_out_sync_0_0; // @[UART.scala:127:25]
assign auto_control_xing_in_a_ready = auto_control_xing_in_a_ready_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_valid = auto_control_xing_in_d_valid_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_opcode = auto_control_xing_in_d_bits_opcode_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_size = auto_control_xing_in_d_bits_size_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_source = auto_control_xing_in_d_bits_source_0; // @[UART.scala:127:25]
assign auto_control_xing_in_d_bits_data = auto_control_xing_in_d_bits_data_0; // @[UART.scala:127:25]
assign auto_io_out_txd = auto_io_out_txd_0; // @[UART.scala:127:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_6 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 3)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<2>(0h2))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<3>(0h7))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 3)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<2>(0h3))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<3>(0h7))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<1>(0h0))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h1))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 2)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<2>(0h3))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[10]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8])
node source_ok = or(_source_ok_T_47, _source_ok_WIRE[9])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits = bits(_uncommonBits_T, 2, 0)
node _T_12 = shr(io.in.a.bits.source, 3)
node _T_13 = eq(_T_12, UInt<2>(0h2))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<3>(0h7))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0)
node _T_25 = shr(io.in.a.bits.source, 3)
node _T_26 = eq(_T_25, UInt<2>(0h3))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<3>(0h7))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<1>(0h0))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<1>(0h1))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_77 = shr(io.in.a.bits.source, 2)
node _T_78 = eq(_T_77, UInt<2>(0h3))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = and(_T_11, _T_24)
node _T_115 = and(_T_114, _T_37)
node _T_116 = and(_T_115, _T_50)
node _T_117 = and(_T_116, _T_63)
node _T_118 = and(_T_117, _T_76)
node _T_119 = and(_T_118, _T_89)
node _T_120 = and(_T_119, _T_97)
node _T_121 = and(_T_120, _T_105)
node _T_122 = and(_T_121, _T_113)
node _T_123 = asUInt(reset)
node _T_124 = eq(_T_123, UInt<1>(0h0))
when _T_124 :
node _T_125 = eq(_T_122, UInt<1>(0h0))
when _T_125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_122, UInt<1>(0h1), "") : assert_1
node _T_126 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_126 :
node _T_127 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_128 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_131 = shr(io.in.a.bits.source, 3)
node _T_132 = eq(_T_131, UInt<2>(0h2))
node _T_133 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_134 = and(_T_132, _T_133)
node _T_135 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_136 = and(_T_134, _T_135)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0)
node _T_137 = shr(io.in.a.bits.source, 3)
node _T_138 = eq(_T_137, UInt<2>(0h3))
node _T_139 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_140 = and(_T_138, _T_139)
node _T_141 = leq(uncommonBits_7, UInt<3>(0h7))
node _T_142 = and(_T_140, _T_141)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_143 = shr(io.in.a.bits.source, 2)
node _T_144 = eq(_T_143, UInt<1>(0h0))
node _T_145 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_146 = and(_T_144, _T_145)
node _T_147 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_148 = and(_T_146, _T_147)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_149 = shr(io.in.a.bits.source, 2)
node _T_150 = eq(_T_149, UInt<1>(0h1))
node _T_151 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_152 = and(_T_150, _T_151)
node _T_153 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_154 = and(_T_152, _T_153)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_155 = shr(io.in.a.bits.source, 2)
node _T_156 = eq(_T_155, UInt<2>(0h2))
node _T_157 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_158 = and(_T_156, _T_157)
node _T_159 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_160 = and(_T_158, _T_159)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_161 = shr(io.in.a.bits.source, 2)
node _T_162 = eq(_T_161, UInt<2>(0h3))
node _T_163 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_164 = and(_T_162, _T_163)
node _T_165 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_168 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_169 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_170 = or(_T_130, _T_136)
node _T_171 = or(_T_170, _T_142)
node _T_172 = or(_T_171, _T_148)
node _T_173 = or(_T_172, _T_154)
node _T_174 = or(_T_173, _T_160)
node _T_175 = or(_T_174, _T_166)
node _T_176 = or(_T_175, _T_167)
node _T_177 = or(_T_176, _T_168)
node _T_178 = or(_T_177, _T_169)
node _T_179 = and(_T_129, _T_178)
node _T_180 = or(UInt<1>(0h0), _T_179)
node _T_181 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_182 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<13>(0h1000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_188 = cvt(_T_187)
node _T_189 = and(_T_188, asSInt(UInt<13>(0h1000)))
node _T_190 = asSInt(_T_189)
node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0)))
node _T_192 = or(_T_186, _T_191)
node _T_193 = and(_T_181, _T_192)
node _T_194 = or(UInt<1>(0h0), _T_193)
node _T_195 = and(_T_180, _T_194)
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(_T_195, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_195, UInt<1>(0h1), "") : assert_2
node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_201 = and(_T_199, _T_200)
node _T_202 = or(UInt<1>(0h0), _T_201)
node _T_203 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<13>(0h1000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = or(_T_207, _T_212)
node _T_214 = and(_T_202, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_216, UInt<1>(0h1), "") : assert_3
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(source_ok, UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_223, UInt<1>(0h1), "") : assert_5
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_230, UInt<1>(0h1), "") : assert_7
node _T_234 = not(io.in.a.bits.mask)
node _T_235 = eq(_T_234, UInt<1>(0h0))
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_235, UInt<1>(0h1), "") : assert_8
node _T_239 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_239, UInt<1>(0h1), "") : assert_9
node _T_243 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_243 :
node _T_244 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_245 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_248 = shr(io.in.a.bits.source, 3)
node _T_249 = eq(_T_248, UInt<2>(0h2))
node _T_250 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_251 = and(_T_249, _T_250)
node _T_252 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_253 = and(_T_251, _T_252)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_254 = shr(io.in.a.bits.source, 3)
node _T_255 = eq(_T_254, UInt<2>(0h3))
node _T_256 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_257 = and(_T_255, _T_256)
node _T_258 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h1))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<2>(0h2))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h3))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_285 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_286 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_287 = or(_T_247, _T_253)
node _T_288 = or(_T_287, _T_259)
node _T_289 = or(_T_288, _T_265)
node _T_290 = or(_T_289, _T_271)
node _T_291 = or(_T_290, _T_277)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_284)
node _T_294 = or(_T_293, _T_285)
node _T_295 = or(_T_294, _T_286)
node _T_296 = and(_T_246, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_299 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_300 = cvt(_T_299)
node _T_301 = and(_T_300, asSInt(UInt<13>(0h1000)))
node _T_302 = asSInt(_T_301)
node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0)))
node _T_304 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_305 = cvt(_T_304)
node _T_306 = and(_T_305, asSInt(UInt<13>(0h1000)))
node _T_307 = asSInt(_T_306)
node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0)))
node _T_309 = or(_T_303, _T_308)
node _T_310 = and(_T_298, _T_309)
node _T_311 = or(UInt<1>(0h0), _T_310)
node _T_312 = and(_T_297, _T_311)
node _T_313 = asUInt(reset)
node _T_314 = eq(_T_313, UInt<1>(0h0))
when _T_314 :
node _T_315 = eq(_T_312, UInt<1>(0h0))
when _T_315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_312, UInt<1>(0h1), "") : assert_10
node _T_316 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_317 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_318 = and(_T_316, _T_317)
node _T_319 = or(UInt<1>(0h0), _T_318)
node _T_320 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<13>(0h1000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = or(_T_324, _T_329)
node _T_331 = and(_T_319, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = and(UInt<1>(0h0), _T_332)
node _T_334 = asUInt(reset)
node _T_335 = eq(_T_334, UInt<1>(0h0))
when _T_335 :
node _T_336 = eq(_T_333, UInt<1>(0h0))
when _T_336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_333, UInt<1>(0h1), "") : assert_11
node _T_337 = asUInt(reset)
node _T_338 = eq(_T_337, UInt<1>(0h0))
when _T_338 :
node _T_339 = eq(source_ok, UInt<1>(0h0))
when _T_339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_340 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_T_340, UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_340, UInt<1>(0h1), "") : assert_13
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_347 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_347, UInt<1>(0h1), "") : assert_15
node _T_351 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_351, UInt<1>(0h1), "") : assert_16
node _T_355 = not(io.in.a.bits.mask)
node _T_356 = eq(_T_355, UInt<1>(0h0))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_356, UInt<1>(0h1), "") : assert_17
node _T_360 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_361 = asUInt(reset)
node _T_362 = eq(_T_361, UInt<1>(0h0))
when _T_362 :
node _T_363 = eq(_T_360, UInt<1>(0h0))
when _T_363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_360, UInt<1>(0h1), "") : assert_18
node _T_364 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_364 :
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_369 = shr(io.in.a.bits.source, 3)
node _T_370 = eq(_T_369, UInt<2>(0h2))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_375 = shr(io.in.a.bits.source, 3)
node _T_376 = eq(_T_375, UInt<2>(0h3))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<1>(0h0))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<1>(0h1))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<2>(0h2))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<2>(0h3))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _T_405 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_406 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_407 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_408 = or(_T_368, _T_374)
node _T_409 = or(_T_408, _T_380)
node _T_410 = or(_T_409, _T_386)
node _T_411 = or(_T_410, _T_392)
node _T_412 = or(_T_411, _T_398)
node _T_413 = or(_T_412, _T_404)
node _T_414 = or(_T_413, _T_405)
node _T_415 = or(_T_414, _T_406)
node _T_416 = or(_T_415, _T_407)
node _T_417 = and(_T_367, _T_416)
node _T_418 = or(UInt<1>(0h0), _T_417)
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_418, UInt<1>(0h1), "") : assert_19
node _T_422 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_423 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_424 = and(_T_422, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<13>(0h1000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = or(_T_430, _T_435)
node _T_437 = and(_T_425, _T_436)
node _T_438 = or(UInt<1>(0h0), _T_437)
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_T_438, UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_438, UInt<1>(0h1), "") : assert_20
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(source_ok, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(is_aligned, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_448 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_448, UInt<1>(0h1), "") : assert_23
node _T_452 = eq(io.in.a.bits.mask, mask)
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_452, UInt<1>(0h1), "") : assert_24
node _T_456 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_456, UInt<1>(0h1), "") : assert_25
node _T_460 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_460 :
node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_462 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0)
node _T_465 = shr(io.in.a.bits.source, 3)
node _T_466 = eq(_T_465, UInt<2>(0h2))
node _T_467 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_468 = and(_T_466, _T_467)
node _T_469 = leq(uncommonBits_24, UInt<3>(0h7))
node _T_470 = and(_T_468, _T_469)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_471 = shr(io.in.a.bits.source, 3)
node _T_472 = eq(_T_471, UInt<2>(0h3))
node _T_473 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_474 = and(_T_472, _T_473)
node _T_475 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_476 = and(_T_474, _T_475)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_477 = shr(io.in.a.bits.source, 2)
node _T_478 = eq(_T_477, UInt<1>(0h0))
node _T_479 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_480 = and(_T_478, _T_479)
node _T_481 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_482 = and(_T_480, _T_481)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_483 = shr(io.in.a.bits.source, 2)
node _T_484 = eq(_T_483, UInt<1>(0h1))
node _T_485 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_486 = and(_T_484, _T_485)
node _T_487 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_488 = and(_T_486, _T_487)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_489 = shr(io.in.a.bits.source, 2)
node _T_490 = eq(_T_489, UInt<2>(0h2))
node _T_491 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_492 = and(_T_490, _T_491)
node _T_493 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_494 = and(_T_492, _T_493)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<2>(0h3))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _T_501 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_502 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_503 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_504 = or(_T_464, _T_470)
node _T_505 = or(_T_504, _T_476)
node _T_506 = or(_T_505, _T_482)
node _T_507 = or(_T_506, _T_488)
node _T_508 = or(_T_507, _T_494)
node _T_509 = or(_T_508, _T_500)
node _T_510 = or(_T_509, _T_501)
node _T_511 = or(_T_510, _T_502)
node _T_512 = or(_T_511, _T_503)
node _T_513 = and(_T_463, _T_512)
node _T_514 = or(UInt<1>(0h0), _T_513)
node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_517 = and(_T_515, _T_516)
node _T_518 = or(UInt<1>(0h0), _T_517)
node _T_519 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<13>(0h1000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = or(_T_523, _T_528)
node _T_530 = and(_T_518, _T_529)
node _T_531 = or(UInt<1>(0h0), _T_530)
node _T_532 = and(_T_514, _T_531)
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_532, UInt<1>(0h1), "") : assert_26
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(source_ok, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(is_aligned, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_542 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_542, UInt<1>(0h1), "") : assert_29
node _T_546 = eq(io.in.a.bits.mask, mask)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_546, UInt<1>(0h1), "") : assert_30
node _T_550 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_550 :
node _T_551 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_552 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_553 = and(_T_551, _T_552)
node _T_554 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 2, 0)
node _T_555 = shr(io.in.a.bits.source, 3)
node _T_556 = eq(_T_555, UInt<2>(0h2))
node _T_557 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_558 = and(_T_556, _T_557)
node _T_559 = leq(uncommonBits_30, UInt<3>(0h7))
node _T_560 = and(_T_558, _T_559)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 2, 0)
node _T_561 = shr(io.in.a.bits.source, 3)
node _T_562 = eq(_T_561, UInt<2>(0h3))
node _T_563 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_564 = and(_T_562, _T_563)
node _T_565 = leq(uncommonBits_31, UInt<3>(0h7))
node _T_566 = and(_T_564, _T_565)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_567 = shr(io.in.a.bits.source, 2)
node _T_568 = eq(_T_567, UInt<1>(0h0))
node _T_569 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_570 = and(_T_568, _T_569)
node _T_571 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_572 = and(_T_570, _T_571)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_573 = shr(io.in.a.bits.source, 2)
node _T_574 = eq(_T_573, UInt<1>(0h1))
node _T_575 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_576 = and(_T_574, _T_575)
node _T_577 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_578 = and(_T_576, _T_577)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_579 = shr(io.in.a.bits.source, 2)
node _T_580 = eq(_T_579, UInt<2>(0h2))
node _T_581 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_582 = and(_T_580, _T_581)
node _T_583 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<2>(0h3))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_592 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_593 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_594 = or(_T_554, _T_560)
node _T_595 = or(_T_594, _T_566)
node _T_596 = or(_T_595, _T_572)
node _T_597 = or(_T_596, _T_578)
node _T_598 = or(_T_597, _T_584)
node _T_599 = or(_T_598, _T_590)
node _T_600 = or(_T_599, _T_591)
node _T_601 = or(_T_600, _T_592)
node _T_602 = or(_T_601, _T_593)
node _T_603 = and(_T_553, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_603)
node _T_605 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_606 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_607 = and(_T_605, _T_606)
node _T_608 = or(UInt<1>(0h0), _T_607)
node _T_609 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<13>(0h1000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<13>(0h1000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = or(_T_613, _T_618)
node _T_620 = and(_T_608, _T_619)
node _T_621 = or(UInt<1>(0h0), _T_620)
node _T_622 = and(_T_604, _T_621)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_622, UInt<1>(0h1), "") : assert_31
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(source_ok, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(is_aligned, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_632, UInt<1>(0h1), "") : assert_34
node _T_636 = not(mask)
node _T_637 = and(io.in.a.bits.mask, _T_636)
node _T_638 = eq(_T_637, UInt<1>(0h0))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_638, UInt<1>(0h1), "") : assert_35
node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_642 :
node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_645 = and(_T_643, _T_644)
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 2, 0)
node _T_647 = shr(io.in.a.bits.source, 3)
node _T_648 = eq(_T_647, UInt<2>(0h2))
node _T_649 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_650 = and(_T_648, _T_649)
node _T_651 = leq(uncommonBits_36, UInt<3>(0h7))
node _T_652 = and(_T_650, _T_651)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 2, 0)
node _T_653 = shr(io.in.a.bits.source, 3)
node _T_654 = eq(_T_653, UInt<2>(0h3))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_37, UInt<3>(0h7))
node _T_658 = and(_T_656, _T_657)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_659 = shr(io.in.a.bits.source, 2)
node _T_660 = eq(_T_659, UInt<1>(0h0))
node _T_661 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_662 = and(_T_660, _T_661)
node _T_663 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_664 = and(_T_662, _T_663)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_665 = shr(io.in.a.bits.source, 2)
node _T_666 = eq(_T_665, UInt<1>(0h1))
node _T_667 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_668 = and(_T_666, _T_667)
node _T_669 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_670 = and(_T_668, _T_669)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_671 = shr(io.in.a.bits.source, 2)
node _T_672 = eq(_T_671, UInt<2>(0h2))
node _T_673 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_674 = and(_T_672, _T_673)
node _T_675 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_676 = and(_T_674, _T_675)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_677 = shr(io.in.a.bits.source, 2)
node _T_678 = eq(_T_677, UInt<2>(0h3))
node _T_679 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_680 = and(_T_678, _T_679)
node _T_681 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_682 = and(_T_680, _T_681)
node _T_683 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_684 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_685 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_686 = or(_T_646, _T_652)
node _T_687 = or(_T_686, _T_658)
node _T_688 = or(_T_687, _T_664)
node _T_689 = or(_T_688, _T_670)
node _T_690 = or(_T_689, _T_676)
node _T_691 = or(_T_690, _T_682)
node _T_692 = or(_T_691, _T_683)
node _T_693 = or(_T_692, _T_684)
node _T_694 = or(_T_693, _T_685)
node _T_695 = and(_T_645, _T_694)
node _T_696 = or(UInt<1>(0h0), _T_695)
node _T_697 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_698 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<13>(0h1000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = or(_T_702, _T_707)
node _T_709 = and(_T_697, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_696, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 2, 0)
node _T_734 = shr(io.in.a.bits.source, 3)
node _T_735 = eq(_T_734, UInt<2>(0h2))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_42, UInt<3>(0h7))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 2, 0)
node _T_740 = shr(io.in.a.bits.source, 3)
node _T_741 = eq(_T_740, UInt<2>(0h3))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_43, UInt<3>(0h7))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<1>(0h0))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<1>(0h1))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<2>(0h2))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_764 = shr(io.in.a.bits.source, 2)
node _T_765 = eq(_T_764, UInt<2>(0h3))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_769 = and(_T_767, _T_768)
node _T_770 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_771 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_772 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_773 = or(_T_733, _T_739)
node _T_774 = or(_T_773, _T_745)
node _T_775 = or(_T_774, _T_751)
node _T_776 = or(_T_775, _T_757)
node _T_777 = or(_T_776, _T_763)
node _T_778 = or(_T_777, _T_769)
node _T_779 = or(_T_778, _T_770)
node _T_780 = or(_T_779, _T_771)
node _T_781 = or(_T_780, _T_772)
node _T_782 = and(_T_732, _T_781)
node _T_783 = or(UInt<1>(0h0), _T_782)
node _T_784 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_785 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = or(_T_789, _T_794)
node _T_796 = and(_T_784, _T_795)
node _T_797 = or(UInt<1>(0h0), _T_796)
node _T_798 = and(_T_783, _T_797)
node _T_799 = asUInt(reset)
node _T_800 = eq(_T_799, UInt<1>(0h0))
when _T_800 :
node _T_801 = eq(_T_798, UInt<1>(0h0))
when _T_801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_798, UInt<1>(0h1), "") : assert_41
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(source_ok, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_805 = asUInt(reset)
node _T_806 = eq(_T_805, UInt<1>(0h0))
when _T_806 :
node _T_807 = eq(is_aligned, UInt<1>(0h0))
when _T_807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_808 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_809 = asUInt(reset)
node _T_810 = eq(_T_809, UInt<1>(0h0))
when _T_810 :
node _T_811 = eq(_T_808, UInt<1>(0h0))
when _T_811 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_808, UInt<1>(0h1), "") : assert_44
node _T_812 = eq(io.in.a.bits.mask, mask)
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(_T_812, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_812, UInt<1>(0h1), "") : assert_45
node _T_816 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_816 :
node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_818 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_819 = and(_T_817, _T_818)
node _T_820 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_821 = shr(io.in.a.bits.source, 3)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0)
node _T_827 = shr(io.in.a.bits.source, 3)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_49, UInt<3>(0h7))
node _T_832 = and(_T_830, _T_831)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<1>(0h1))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<2>(0h2))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<2>(0h3))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_858 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_859 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_860 = or(_T_820, _T_826)
node _T_861 = or(_T_860, _T_832)
node _T_862 = or(_T_861, _T_838)
node _T_863 = or(_T_862, _T_844)
node _T_864 = or(_T_863, _T_850)
node _T_865 = or(_T_864, _T_856)
node _T_866 = or(_T_865, _T_857)
node _T_867 = or(_T_866, _T_858)
node _T_868 = or(_T_867, _T_859)
node _T_869 = and(_T_819, _T_868)
node _T_870 = or(UInt<1>(0h0), _T_869)
node _T_871 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_872 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<13>(0h1000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = or(_T_876, _T_881)
node _T_883 = and(_T_871, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = and(_T_870, _T_884)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_885, UInt<1>(0h1), "") : assert_46
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(source_ok, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(is_aligned, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_895 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_895, UInt<1>(0h1), "") : assert_49
node _T_899 = eq(io.in.a.bits.mask, mask)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_899, UInt<1>(0h1), "") : assert_50
node _T_903 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_903, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_907 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_907, UInt<1>(0h1), "") : assert_52
node _source_ok_T_48 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 3)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<2>(0h2))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 2, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 3)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h3))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_7, UInt<3>(0h7))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<1>(0h0))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_67 = shr(io.in.d.bits.source, 2)
node _source_ok_T_68 = eq(_source_ok_T_67, UInt<1>(0h1))
node _source_ok_T_69 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_73 = shr(io.in.d.bits.source, 2)
node _source_ok_T_74 = eq(_source_ok_T_73, UInt<2>(0h2))
node _source_ok_T_75 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_T_77 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 1, 0)
node _source_ok_T_79 = shr(io.in.d.bits.source, 2)
node _source_ok_T_80 = eq(_source_ok_T_79, UInt<2>(0h3))
node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = leq(source_ok_uncommonBits_11, UInt<2>(0h3))
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[10]
connect _source_ok_WIRE_1[0], _source_ok_T_48
connect _source_ok_WIRE_1[1], _source_ok_T_54
connect _source_ok_WIRE_1[2], _source_ok_T_60
connect _source_ok_WIRE_1[3], _source_ok_T_66
connect _source_ok_WIRE_1[4], _source_ok_T_72
connect _source_ok_WIRE_1[5], _source_ok_T_78
connect _source_ok_WIRE_1[6], _source_ok_T_84
connect _source_ok_WIRE_1[7], _source_ok_T_85
connect _source_ok_WIRE_1[8], _source_ok_T_86
connect _source_ok_WIRE_1[9], _source_ok_T_87
node _source_ok_T_88 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[2])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[3])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[4])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[5])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[6])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[7])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[8])
node source_ok_1 = or(_source_ok_T_95, _source_ok_WIRE_1[9])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_911 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_911 :
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(source_ok_1, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_915 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_916 = asUInt(reset)
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(_T_915, UInt<1>(0h0))
when _T_918 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_915, UInt<1>(0h1), "") : assert_54
node _T_919 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_920 = asUInt(reset)
node _T_921 = eq(_T_920, UInt<1>(0h0))
when _T_921 :
node _T_922 = eq(_T_919, UInt<1>(0h0))
when _T_922 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_919, UInt<1>(0h1), "") : assert_55
node _T_923 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_924 = asUInt(reset)
node _T_925 = eq(_T_924, UInt<1>(0h0))
when _T_925 :
node _T_926 = eq(_T_923, UInt<1>(0h0))
when _T_926 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_923, UInt<1>(0h1), "") : assert_56
node _T_927 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_928 = asUInt(reset)
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(_T_927, UInt<1>(0h0))
when _T_930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_927, UInt<1>(0h1), "") : assert_57
node _T_931 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_931 :
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(source_ok_1, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(sink_ok, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_938 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_938, UInt<1>(0h1), "") : assert_60
node _T_942 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_942, UInt<1>(0h1), "") : assert_61
node _T_946 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_946, UInt<1>(0h1), "") : assert_62
node _T_950 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_951 = asUInt(reset)
node _T_952 = eq(_T_951, UInt<1>(0h0))
when _T_952 :
node _T_953 = eq(_T_950, UInt<1>(0h0))
when _T_953 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_950, UInt<1>(0h1), "") : assert_63
node _T_954 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_955 = or(UInt<1>(0h0), _T_954)
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_955, UInt<1>(0h1), "") : assert_64
node _T_959 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_959 :
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(source_ok_1, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(sink_ok, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_966 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_966, UInt<1>(0h1), "") : assert_67
node _T_970 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_970, UInt<1>(0h1), "") : assert_68
node _T_974 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_974, UInt<1>(0h1), "") : assert_69
node _T_978 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_979 = or(_T_978, io.in.d.bits.corrupt)
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(_T_979, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_979, UInt<1>(0h1), "") : assert_70
node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = asUInt(reset)
node _T_986 = eq(_T_985, UInt<1>(0h0))
when _T_986 :
node _T_987 = eq(_T_984, UInt<1>(0h0))
when _T_987 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_984, UInt<1>(0h1), "") : assert_71
node _T_988 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_988 :
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(source_ok_1, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_992 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_993 = asUInt(reset)
node _T_994 = eq(_T_993, UInt<1>(0h0))
when _T_994 :
node _T_995 = eq(_T_992, UInt<1>(0h0))
when _T_995 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_992, UInt<1>(0h1), "") : assert_73
node _T_996 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(_T_996, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_996, UInt<1>(0h1), "") : assert_74
node _T_1000 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1001 = or(UInt<1>(0h0), _T_1000)
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_75
node _T_1005 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1005 :
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok_1, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1009 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_77
node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1014 = or(_T_1013, io.in.d.bits.corrupt)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_78
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_79
node _T_1023 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1023 :
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(source_ok_1, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1027 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_81
node _T_1031 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(_T_1031, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1031, UInt<1>(0h1), "") : assert_82
node _T_1035 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1036 = or(UInt<1>(0h0), _T_1035)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1040 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1044 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1048 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1052 = eq(a_first, UInt<1>(0h0))
node _T_1053 = and(io.in.a.valid, _T_1052)
when _T_1053 :
node _T_1054 = eq(io.in.a.bits.opcode, opcode)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_87
node _T_1058 = eq(io.in.a.bits.param, param)
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_88
node _T_1062 = eq(io.in.a.bits.size, size)
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_89
node _T_1066 = eq(io.in.a.bits.source, source)
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_90
node _T_1070 = eq(io.in.a.bits.address, address)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_91
node _T_1074 = and(io.in.a.ready, io.in.a.valid)
node _T_1075 = and(_T_1074, a_first)
when _T_1075 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1076 = eq(d_first, UInt<1>(0h0))
node _T_1077 = and(io.in.d.valid, _T_1076)
when _T_1077 :
node _T_1078 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_92
node _T_1082 = eq(io.in.d.bits.param, param_1)
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_93
node _T_1086 = eq(io.in.d.bits.size, size_1)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_94
node _T_1090 = eq(io.in.d.bits.source, source_1)
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(_T_1090, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1090, UInt<1>(0h1), "") : assert_95
node _T_1094 = eq(io.in.d.bits.sink, sink)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_96
node _T_1098 = eq(io.in.d.bits.denied, denied)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_97
node _T_1102 = and(io.in.d.ready, io.in.d.valid)
node _T_1103 = and(_T_1102, d_first)
when _T_1103 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1104 = and(io.in.a.valid, a_first_1)
node _T_1105 = and(_T_1104, UInt<1>(0h1))
when _T_1105 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1106 = and(io.in.a.ready, io.in.a.valid)
node _T_1107 = and(_T_1106, a_first_1)
node _T_1108 = and(_T_1107, UInt<1>(0h1))
when _T_1108 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1109 = dshr(inflight, io.in.a.bits.source)
node _T_1110 = bits(_T_1109, 0, 0)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1115 = and(io.in.d.valid, d_first_1)
node _T_1116 = and(_T_1115, UInt<1>(0h1))
node _T_1117 = eq(d_release_ack, UInt<1>(0h0))
node _T_1118 = and(_T_1116, _T_1117)
when _T_1118 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1119 = and(io.in.d.ready, io.in.d.valid)
node _T_1120 = and(_T_1119, d_first_1)
node _T_1121 = and(_T_1120, UInt<1>(0h1))
node _T_1122 = eq(d_release_ack, UInt<1>(0h0))
node _T_1123 = and(_T_1121, _T_1122)
when _T_1123 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1124 = and(io.in.d.valid, d_first_1)
node _T_1125 = and(_T_1124, UInt<1>(0h1))
node _T_1126 = eq(d_release_ack, UInt<1>(0h0))
node _T_1127 = and(_T_1125, _T_1126)
when _T_1127 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1128 = dshr(inflight, io.in.d.bits.source)
node _T_1129 = bits(_T_1128, 0, 0)
node _T_1130 = or(_T_1129, same_cycle_resp)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1134 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1135 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1136 = or(_T_1134, _T_1135)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_100
node _T_1140 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_101
else :
node _T_1144 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1145 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1146 = or(_T_1144, _T_1145)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_102
node _T_1150 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_103
node _T_1154 = and(io.in.d.valid, d_first_1)
node _T_1155 = and(_T_1154, a_first_1)
node _T_1156 = and(_T_1155, io.in.a.valid)
node _T_1157 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1158 = and(_T_1156, _T_1157)
node _T_1159 = eq(d_release_ack, UInt<1>(0h0))
node _T_1160 = and(_T_1158, _T_1159)
when _T_1160 :
node _T_1161 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1162 = or(_T_1161, io.in.a.ready)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_12
node _T_1166 = orr(inflight)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
node _T_1168 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1169 = or(_T_1167, _T_1168)
node _T_1170 = lt(watchdog, plusarg_reader.out)
node _T_1171 = or(_T_1169, _T_1170)
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1175 = and(io.in.a.ready, io.in.a.valid)
node _T_1176 = and(io.in.d.ready, io.in.d.valid)
node _T_1177 = or(_T_1175, _T_1176)
when _T_1177 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1178 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1179 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1180 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1181 = and(_T_1179, _T_1180)
node _T_1182 = and(_T_1178, _T_1181)
when _T_1182 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1183 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1184 = and(_T_1183, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1185 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1186 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1187 = and(_T_1185, _T_1186)
node _T_1188 = and(_T_1184, _T_1187)
when _T_1188 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1189 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1190 = bits(_T_1189, 0, 0)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1195 = and(io.in.d.valid, d_first_2)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
node _T_1197 = and(_T_1196, d_release_ack_1)
when _T_1197 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1198 = and(io.in.d.ready, io.in.d.valid)
node _T_1199 = and(_T_1198, d_first_2)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = and(_T_1200, d_release_ack_1)
when _T_1201 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1202 = and(io.in.d.valid, d_first_2)
node _T_1203 = and(_T_1202, UInt<1>(0h1))
node _T_1204 = and(_T_1203, d_release_ack_1)
when _T_1204 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1205 = dshr(inflight_1, io.in.d.bits.source)
node _T_1206 = bits(_T_1205, 0, 0)
node _T_1207 = or(_T_1206, same_cycle_resp_1)
node _T_1208 = asUInt(reset)
node _T_1209 = eq(_T_1208, UInt<1>(0h0))
when _T_1209 :
node _T_1210 = eq(_T_1207, UInt<1>(0h0))
when _T_1210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1207, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1211 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_108
else :
node _T_1215 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1216 = asUInt(reset)
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(_T_1215, UInt<1>(0h0))
when _T_1218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1215, UInt<1>(0h1), "") : assert_109
node _T_1219 = and(io.in.d.valid, d_first_2)
node _T_1220 = and(_T_1219, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1221 = and(_T_1220, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1222 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1223 = and(_T_1221, _T_1222)
node _T_1224 = and(_T_1223, d_release_ack_1)
node _T_1225 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
node _T_1227 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1228 = or(_T_1227, _WIRE_23.ready)
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_13
node _T_1232 = orr(inflight_1)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
node _T_1234 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1235 = or(_T_1233, _T_1234)
node _T_1236 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1241 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1242 = and(io.in.d.ready, io.in.d.valid)
node _T_1243 = or(_T_1241, _T_1242)
when _T_1243 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_6( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_25 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_31 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_73 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_79 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_62 = _source_ok_T_61 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1175 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1175; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1175; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1243 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1243; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1243; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1243; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1108 = _T_1175 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1108 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1108 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1108 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1108 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1108 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1154 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1154 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1123 = _T_1243 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1123 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1123 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1123 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1219 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1219 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1201 = _T_1243 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1201 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1201 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1201 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module FixedClockBroadcast_3 :
output auto : { flip anon_in : { clock : Clock, reset : Reset}, anon_out_2 : { clock : Clock, reset : Reset}, anon_out_1 : { clock : Clock, reset : Reset}, anon_out_0 : { clock : Clock, reset : Reset}}
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
wire anonIn : { clock : Clock, reset : Reset}
invalidate anonIn.reset
invalidate anonIn.clock
wire anonOut : { clock : Clock, reset : Reset}
invalidate anonOut.reset
invalidate anonOut.clock
wire x1_anonOut : { clock : Clock, reset : Reset}
invalidate x1_anonOut.reset
invalidate x1_anonOut.clock
wire x1_anonOut_1 : { clock : Clock, reset : Reset}
invalidate x1_anonOut_1.reset
invalidate x1_anonOut_1.clock
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect auto.anon_out_2, x1_anonOut_1
connect anonIn, auto.anon_in
connect anonOut, anonIn
connect x1_anonOut, anonIn
connect x1_anonOut_1, anonIn | module FixedClockBroadcast_3( // @[ClockGroup.scala:104:9]
input auto_anon_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_reset // @[LazyModuleImp.scala:107:25]
);
assign auto_anon_out_2_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_1_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_clock = auto_anon_in_clock; // @[ClockGroup.scala:104:9]
assign auto_anon_out_0_reset = auto_anon_in_reset; // @[ClockGroup.scala:104:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e5_s11_2 :
output io : { flip op : UInt<2>, flip a : UInt<17>, flip b : UInt<17>, flip c : UInt<17>, mulAddA : UInt<11>, mulAddB : UInt<11>, mulAddC : UInt<22>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 15, 10)
node _rawA_isZero_T = bits(rawA_exp, 5, 3)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 5, 4)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawA_out_isNaN_T = bits(rawA_exp, 3, 3)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 3, 3)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 16, 16)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 9, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 15, 10)
node _rawB_isZero_T = bits(rawB_exp, 5, 3)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 5, 4)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawB_out_isNaN_T = bits(rawB_exp, 3, 3)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 3, 3)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 16, 16)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 9, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 15, 10)
node _rawC_isZero_T = bits(rawC_exp, 5, 3)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 5, 4)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}
node _rawC_out_isNaN_T = bits(rawC_exp, 3, 3)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 3, 3)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 16, 16)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 9, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<6>(0h2e)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 6, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<4>(0hb))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<6>(0h23))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 5, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<6>(0h23))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<27>(0h7ffffff), UInt<27>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 0)
wire reduced4CExtra_reducedVec : UInt<1>[3]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node reduced4CExtra_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_reducedVec[0])
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 9, 8)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 0, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_3, 1, 1)
node _reduced4CExtra_T_6 = cat(_reduced4CExtra_T_4, _reduced4CExtra_T_5)
node _reduced4CExtra_T_7 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_6)
node reduced4CExtra = orr(_reduced4CExtra_T_7)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 22, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 9, 9)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<5>(0hb)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 3, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 35, 23)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e5_s11_2( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [16:0] io_a, // @[MulAddRecFN.scala:74:16]
input [16:0] io_b, // @[MulAddRecFN.scala:74:16]
input [16:0] io_c, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [21:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [6:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [3:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [16:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [21:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [3:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [12:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [6:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [3:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [12:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [10:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [21:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [5:0] rawA_exp = io_a_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawA_out_sig_T_2 = io_a_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawB_exp = io_b_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawB_out_sig_T_2 = io_b_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [5:0] rawC_exp = io_c_0[15:10]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [6:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [11:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [6:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[16]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [9:0] _rawC_out_sig_T_2 = io_c_0[9:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49]
assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [7:0] _sExpAlignedProd_T = {rawA_sExp[6], rawA_sExp} + {rawB_sExp[6], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [8:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[7], _sExpAlignedProd_T} - 9'h12; // @[MulAddRecFN.scala:100:{19,32}]
wire [7:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[7:0]; // @[MulAddRecFN.scala:100:32]
wire [7:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49]
assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [8:0] _GEN = {sExpAlignedProd[7], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [8:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[6]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [7:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[7:0]; // @[MulAddRecFN.scala:106:42]
wire [7:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [6:0] posNatCAlignDist = sNatCAlignDist[6:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 8'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 7'hC; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 7'h23; // @[MulAddRecFN.scala:107:42, :114:34]
wire [5:0] _CAlignDist_T_1 = posNatCAlignDist[5:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [5:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 6'h23; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [11:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [26:0] _mainAlignedSigC_T_2 = {27{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [38:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [38:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [38:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [3:0] _reduced4CExtra_T_2 = CAlignDist[5:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [1:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[9:8]; // @[primitives.scala:76:56, :78:22]
wire _reduced4CExtra_T_4 = _reduced4CExtra_T_3[0]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_5 = _reduced4CExtra_T_3[1]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_6 = {_reduced4CExtra_T_4, _reduced4CExtra_T_5}; // @[primitives.scala:77:20]
wire [2:0] _reduced4CExtra_T_7 = {1'h0, _reduced4CExtra_T_1[1:0] & _reduced4CExtra_T_6}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_7; // @[MulAddRecFN.scala:122:68, :130:11]
wire [35:0] _alignedSigC_T = mainAlignedSigC[38:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [35:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [36:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[10:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[22:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[9]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [8:0] _io_toPostMul_sExpSum_T = _GEN - 9'hB; // @[MulAddRecFN.scala:106:42, :158:53]
wire [7:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[7:0]; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [7:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[6], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[6:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[3:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[35:23]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a29d64s7k1z3u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.user.amba_prot.fetch
invalidate nodeIn.a.bits.user.amba_prot.secure
invalidate nodeIn.a.bits.user.amba_prot.privileged
invalidate nodeIn.a.bits.user.amba_prot.writealloc
invalidate nodeIn.a.bits.user.amba_prot.readalloc
invalidate nodeIn.a.bits.user.amba_prot.modifiable
invalidate nodeIn.a.bits.user.amba_prot.bufferable
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_5
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch
connect monitor.io.in.a.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure
connect monitor.io.in.a.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged
connect monitor.io.in.a.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc
connect monitor.io.in.a.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc
connect monitor.io.in.a.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable
connect monitor.io.in.a.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.user.amba_prot.fetch
invalidate nodeOut.a.bits.user.amba_prot.secure
invalidate nodeOut.a.bits.user.amba_prot.privileged
invalidate nodeOut.a.bits.user.amba_prot.writealloc
invalidate nodeOut.a.bits.user.amba_prot.readalloc
invalidate nodeOut.a.bits.user.amba_prot.modifiable
invalidate nodeOut.a.bits.user.amba_prot.bufferable
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a29d64s7k1z3u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.user.amba_prot.fetch, nodeIn.a.bits.user.amba_prot.fetch
connect nodeOut_a_q.io.enq.bits.user.amba_prot.secure, nodeIn.a.bits.user.amba_prot.secure
connect nodeOut_a_q.io.enq.bits.user.amba_prot.privileged, nodeIn.a.bits.user.amba_prot.privileged
connect nodeOut_a_q.io.enq.bits.user.amba_prot.writealloc, nodeIn.a.bits.user.amba_prot.writealloc
connect nodeOut_a_q.io.enq.bits.user.amba_prot.readalloc, nodeIn.a.bits.user.amba_prot.readalloc
connect nodeOut_a_q.io.enq.bits.user.amba_prot.modifiable, nodeIn.a.bits.user.amba_prot.modifiable
connect nodeOut_a_q.io.enq.bits.user.amba_prot.bufferable, nodeIn.a.bits.user.amba_prot.bufferable
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a29d64s7k1z3u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_12 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_13 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a29d64s7k1z3u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [6:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_5 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s7k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_user_amba_prot_bufferable (auto_in_a_bits_user_amba_prot_bufferable),
.io_enq_bits_user_amba_prot_modifiable (auto_in_a_bits_user_amba_prot_modifiable),
.io_enq_bits_user_amba_prot_readalloc (auto_in_a_bits_user_amba_prot_readalloc),
.io_enq_bits_user_amba_prot_writealloc (auto_in_a_bits_user_amba_prot_writealloc),
.io_enq_bits_user_amba_prot_privileged (auto_in_a_bits_user_amba_prot_privileged),
.io_enq_bits_user_amba_prot_secure (auto_in_a_bits_user_amba_prot_secure),
.io_enq_bits_user_amba_prot_fetch (auto_in_a_bits_user_amba_prot_fetch),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_user_amba_prot_bufferable (auto_out_a_bits_user_amba_prot_bufferable),
.io_deq_bits_user_amba_prot_modifiable (auto_out_a_bits_user_amba_prot_modifiable),
.io_deq_bits_user_amba_prot_readalloc (auto_out_a_bits_user_amba_prot_readalloc),
.io_deq_bits_user_amba_prot_writealloc (auto_out_a_bits_user_amba_prot_writealloc),
.io_deq_bits_user_amba_prot_privileged (auto_out_a_bits_user_amba_prot_privileged),
.io_deq_bits_user_amba_prot_secure (auto_out_a_bits_user_amba_prot_secure),
.io_deq_bits_user_amba_prot_fetch (auto_out_a_bits_user_amba_prot_fetch),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s7k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_60 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = and(_T_11, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_24 :
node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_35 = cvt(_T_34)
node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000)))
node _T_37 = asSInt(_T_36)
node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0)))
node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_40 = cvt(_T_39)
node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000)))
node _T_42 = asSInt(_T_41)
node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0)))
node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_45 = cvt(_T_44)
node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000)))
node _T_47 = asSInt(_T_46)
node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0)))
node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_50 = cvt(_T_49)
node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000)))
node _T_52 = asSInt(_T_51)
node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0)))
node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = or(_T_38, _T_43)
node _T_75 = or(_T_74, _T_48)
node _T_76 = or(_T_75, _T_53)
node _T_77 = or(_T_76, _T_58)
node _T_78 = or(_T_77, _T_63)
node _T_79 = or(_T_78, _T_68)
node _T_80 = or(_T_79, _T_73)
node _T_81 = and(_T_33, _T_80)
node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_83 = or(UInt<1>(0h0), _T_82)
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_88, _T_93)
node _T_95 = and(_T_83, _T_94)
node _T_96 = or(UInt<1>(0h0), _T_81)
node _T_97 = or(_T_96, _T_95)
node _T_98 = and(_T_32, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_98, UInt<1>(0h1), "") : assert_2
node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE : UInt<1>[2]
connect _WIRE[0], _T_102
connect _WIRE[1], _T_103
node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0))
node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = or(_T_105, _T_106)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_107
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = or(UInt<1>(0h0), _T_110)
node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = or(_T_116, _T_121)
node _T_163 = or(_T_162, _T_126)
node _T_164 = or(_T_163, _T_131)
node _T_165 = or(_T_164, _T_136)
node _T_166 = or(_T_165, _T_141)
node _T_167 = or(_T_166, _T_146)
node _T_168 = or(_T_167, _T_151)
node _T_169 = or(_T_168, _T_156)
node _T_170 = or(_T_169, _T_161)
node _T_171 = and(_T_111, _T_170)
node _T_172 = or(UInt<1>(0h0), _T_171)
node _T_173 = and(_WIRE_1, _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_173, UInt<1>(0h1), "") : assert_3
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(source_ok, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_180, UInt<1>(0h1), "") : assert_5
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(is_aligned, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_187, UInt<1>(0h1), "") : assert_7
node _T_191 = not(io.in.a.bits.mask)
node _T_192 = eq(_T_191, UInt<1>(0h0))
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_T_192, UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_192, UInt<1>(0h1), "") : assert_8
node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_197 = asUInt(reset)
node _T_198 = eq(_T_197, UInt<1>(0h0))
when _T_198 :
node _T_199 = eq(_T_196, UInt<1>(0h0))
when _T_199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_196, UInt<1>(0h1), "") : assert_9
node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_200 :
node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_206 = or(_T_204, _T_205)
node _T_207 = and(_T_203, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_241 = cvt(_T_240)
node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000)))
node _T_243 = asSInt(_T_242)
node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = or(_T_214, _T_219)
node _T_251 = or(_T_250, _T_224)
node _T_252 = or(_T_251, _T_229)
node _T_253 = or(_T_252, _T_234)
node _T_254 = or(_T_253, _T_239)
node _T_255 = or(_T_254, _T_244)
node _T_256 = or(_T_255, _T_249)
node _T_257 = and(_T_209, _T_256)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = or(UInt<1>(0h0), _T_258)
node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = or(_T_264, _T_269)
node _T_271 = and(_T_259, _T_270)
node _T_272 = or(UInt<1>(0h0), _T_257)
node _T_273 = or(_T_272, _T_271)
node _T_274 = and(_T_208, _T_273)
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_274, UInt<1>(0h1), "") : assert_10
node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE_2 : UInt<1>[2]
connect _WIRE_2[0], _T_278
connect _WIRE_2[1], _T_279
node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0))
node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = or(_T_281, _T_282)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_283
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = or(_T_292, _T_297)
node _T_339 = or(_T_338, _T_302)
node _T_340 = or(_T_339, _T_307)
node _T_341 = or(_T_340, _T_312)
node _T_342 = or(_T_341, _T_317)
node _T_343 = or(_T_342, _T_322)
node _T_344 = or(_T_343, _T_327)
node _T_345 = or(_T_344, _T_332)
node _T_346 = or(_T_345, _T_337)
node _T_347 = and(_T_287, _T_346)
node _T_348 = or(UInt<1>(0h0), _T_347)
node _T_349 = and(_WIRE_3, _T_348)
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(_T_349, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_349, UInt<1>(0h1), "") : assert_11
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(source_ok, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_356, UInt<1>(0h1), "") : assert_13
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(is_aligned, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_363, UInt<1>(0h1), "") : assert_15
node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_367, UInt<1>(0h1), "") : assert_16
node _T_371 = not(io.in.a.bits.mask)
node _T_372 = eq(_T_371, UInt<1>(0h0))
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_372, UInt<1>(0h1), "") : assert_17
node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_376, UInt<1>(0h1), "") : assert_18
node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_380 :
node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_386 = or(_T_384, _T_385)
node _T_387 = and(_T_383, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(_T_388, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_388, UInt<1>(0h1), "") : assert_19
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = or(UInt<1>(0h0), _T_394)
node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_397 = cvt(_T_396)
node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000)))
node _T_399 = asSInt(_T_398)
node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0)))
node _T_401 = and(_T_395, _T_400)
node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_404 = and(_T_402, _T_403)
node _T_405 = or(UInt<1>(0h0), _T_404)
node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_407 = cvt(_T_406)
node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000)))
node _T_409 = asSInt(_T_408)
node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0)))
node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_412 = cvt(_T_411)
node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000)))
node _T_414 = asSInt(_T_413)
node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0)))
node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_417 = cvt(_T_416)
node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000)))
node _T_419 = asSInt(_T_418)
node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0)))
node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_422 = cvt(_T_421)
node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000)))
node _T_424 = asSInt(_T_423)
node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0)))
node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = or(_T_410, _T_415)
node _T_452 = or(_T_451, _T_420)
node _T_453 = or(_T_452, _T_425)
node _T_454 = or(_T_453, _T_430)
node _T_455 = or(_T_454, _T_435)
node _T_456 = or(_T_455, _T_440)
node _T_457 = or(_T_456, _T_445)
node _T_458 = or(_T_457, _T_450)
node _T_459 = and(_T_405, _T_458)
node _T_460 = or(UInt<1>(0h0), _T_401)
node _T_461 = or(_T_460, _T_459)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_461, UInt<1>(0h1), "") : assert_20
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(source_ok, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(is_aligned, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_471, UInt<1>(0h1), "") : assert_23
node _T_475 = eq(io.in.a.bits.mask, mask)
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_475, UInt<1>(0h1), "") : assert_24
node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_479, UInt<1>(0h1), "") : assert_25
node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_483 :
node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_489 = or(_T_487, _T_488)
node _T_490 = and(_T_486, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_494 = and(_T_492, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_497 = cvt(_T_496)
node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000)))
node _T_499 = asSInt(_T_498)
node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0)))
node _T_501 = and(_T_495, _T_500)
node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_504 = and(_T_502, _T_503)
node _T_505 = or(UInt<1>(0h0), _T_504)
node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_507 = cvt(_T_506)
node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000)))
node _T_509 = asSInt(_T_508)
node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0)))
node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_542 = cvt(_T_541)
node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000)))
node _T_544 = asSInt(_T_543)
node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0)))
node _T_546 = or(_T_510, _T_515)
node _T_547 = or(_T_546, _T_520)
node _T_548 = or(_T_547, _T_525)
node _T_549 = or(_T_548, _T_530)
node _T_550 = or(_T_549, _T_535)
node _T_551 = or(_T_550, _T_540)
node _T_552 = or(_T_551, _T_545)
node _T_553 = and(_T_505, _T_552)
node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = or(UInt<1>(0h0), _T_501)
node _T_562 = or(_T_561, _T_553)
node _T_563 = or(_T_562, _T_560)
node _T_564 = and(_T_491, _T_563)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_564, UInt<1>(0h1), "") : assert_26
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(source_ok, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(is_aligned, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_574, UInt<1>(0h1), "") : assert_29
node _T_578 = eq(io.in.a.bits.mask, mask)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_578, UInt<1>(0h1), "") : assert_30
node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_582 :
node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_585 = and(_T_583, _T_584)
node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(_T_585, _T_588)
node _T_590 = or(UInt<1>(0h0), _T_589)
node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_593 = and(_T_591, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = and(_T_594, _T_599)
node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_603 = and(_T_601, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_603)
node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_606 = cvt(_T_605)
node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000)))
node _T_608 = asSInt(_T_607)
node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0)))
node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = or(_T_609, _T_614)
node _T_646 = or(_T_645, _T_619)
node _T_647 = or(_T_646, _T_624)
node _T_648 = or(_T_647, _T_629)
node _T_649 = or(_T_648, _T_634)
node _T_650 = or(_T_649, _T_639)
node _T_651 = or(_T_650, _T_644)
node _T_652 = and(_T_604, _T_651)
node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_655 = cvt(_T_654)
node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000)))
node _T_657 = asSInt(_T_656)
node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0)))
node _T_659 = and(_T_653, _T_658)
node _T_660 = or(UInt<1>(0h0), _T_600)
node _T_661 = or(_T_660, _T_652)
node _T_662 = or(_T_661, _T_659)
node _T_663 = and(_T_590, _T_662)
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(_T_663, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_663, UInt<1>(0h1), "") : assert_31
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(source_ok, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(is_aligned, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_673, UInt<1>(0h1), "") : assert_34
node _T_677 = not(mask)
node _T_678 = and(io.in.a.bits.mask, _T_677)
node _T_679 = eq(_T_678, UInt<1>(0h0))
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_679, UInt<1>(0h1), "") : assert_35
node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_683 :
node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_689 = or(_T_687, _T_688)
node _T_690 = and(_T_686, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(UInt<1>(0h0), _T_694)
node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_702 = cvt(_T_701)
node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000)))
node _T_704 = asSInt(_T_703)
node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0)))
node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = or(_T_700, _T_705)
node _T_742 = or(_T_741, _T_710)
node _T_743 = or(_T_742, _T_715)
node _T_744 = or(_T_743, _T_720)
node _T_745 = or(_T_744, _T_725)
node _T_746 = or(_T_745, _T_730)
node _T_747 = or(_T_746, _T_735)
node _T_748 = or(_T_747, _T_740)
node _T_749 = and(_T_695, _T_748)
node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = and(_T_750, _T_755)
node _T_757 = or(UInt<1>(0h0), _T_749)
node _T_758 = or(_T_757, _T_756)
node _T_759 = and(_T_691, _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_759, UInt<1>(0h1), "") : assert_36
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(source_ok, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(is_aligned, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_T_769, UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_769, UInt<1>(0h1), "") : assert_39
node _T_773 = eq(io.in.a.bits.mask, mask)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_773, UInt<1>(0h1), "") : assert_40
node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_777 :
node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_783 = or(_T_781, _T_782)
node _T_784 = and(_T_780, _T_783)
node _T_785 = or(UInt<1>(0h0), _T_784)
node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = or(_T_794, _T_799)
node _T_836 = or(_T_835, _T_804)
node _T_837 = or(_T_836, _T_809)
node _T_838 = or(_T_837, _T_814)
node _T_839 = or(_T_838, _T_819)
node _T_840 = or(_T_839, _T_824)
node _T_841 = or(_T_840, _T_829)
node _T_842 = or(_T_841, _T_834)
node _T_843 = and(_T_789, _T_842)
node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_846 = cvt(_T_845)
node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000)))
node _T_848 = asSInt(_T_847)
node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0)))
node _T_850 = and(_T_844, _T_849)
node _T_851 = or(UInt<1>(0h0), _T_843)
node _T_852 = or(_T_851, _T_850)
node _T_853 = and(_T_785, _T_852)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_853, UInt<1>(0h1), "") : assert_41
node _T_857 = asUInt(reset)
node _T_858 = eq(_T_857, UInt<1>(0h0))
when _T_858 :
node _T_859 = eq(source_ok, UInt<1>(0h0))
when _T_859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(is_aligned, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_863, UInt<1>(0h1), "") : assert_44
node _T_867 = eq(io.in.a.bits.mask, mask)
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(_T_867, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_867, UInt<1>(0h1), "") : assert_45
node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_871 :
node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_877 = or(_T_875, _T_876)
node _T_878 = and(_T_874, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_882 = and(_T_880, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_882)
node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = and(_T_883, _T_888)
node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_912 = cvt(_T_911)
node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000)))
node _T_914 = asSInt(_T_913)
node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_895, _T_900)
node _T_927 = or(_T_926, _T_905)
node _T_928 = or(_T_927, _T_910)
node _T_929 = or(_T_928, _T_915)
node _T_930 = or(_T_929, _T_920)
node _T_931 = or(_T_930, _T_925)
node _T_932 = and(_T_890, _T_931)
node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_935 = and(_T_933, _T_934)
node _T_936 = or(UInt<1>(0h0), _T_935)
node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = or(_T_941, _T_946)
node _T_948 = and(_T_936, _T_947)
node _T_949 = or(UInt<1>(0h0), _T_889)
node _T_950 = or(_T_949, _T_932)
node _T_951 = or(_T_950, _T_948)
node _T_952 = and(_T_879, _T_951)
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_952, UInt<1>(0h1), "") : assert_46
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(is_aligned, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(_T_962, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_962, UInt<1>(0h1), "") : assert_49
node _T_966 = eq(io.in.a.bits.mask, mask)
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_966, UInt<1>(0h1), "") : assert_50
node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_970, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_974, UInt<1>(0h1), "") : assert_52
node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_2
connect _source_ok_WIRE_1[1], _source_ok_T_3
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_978 :
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(source_ok_1, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_982, UInt<1>(0h1), "") : assert_54
node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_986, UInt<1>(0h1), "") : assert_55
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_990, UInt<1>(0h1), "") : assert_56
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_994, UInt<1>(0h1), "") : assert_57
node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_998 :
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(source_ok_1, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(sink_ok, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60
node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61
node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62
node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63
node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1022 = or(UInt<1>(0h1), _T_1021)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64
node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1026 :
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(source_ok_1, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(sink_ok, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67
node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68
node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(_T_1045, io.in.d.bits.corrupt)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70
node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1051 = or(UInt<1>(0h1), _T_1050)
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71
node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(source_ok_1, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73
node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h1), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = or(_T_1080, io.in.d.bits.corrupt)
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78
node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1086 = or(UInt<1>(0h1), _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79
node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1090 :
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(source_ok_1, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81
node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h1), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84
node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1114 = cvt(_T_1113)
node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0)))
node _T_1116 = asSInt(_T_1115)
node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0)))
node _T_1118 = or(_T_1112, _T_1117)
node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1122 = cvt(_T_1121)
node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = asSInt(_T_1123)
node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0)))
node _T_1126 = or(_T_1120, _T_1125)
node _T_1127 = and(_T_1118, _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0h8000040))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<28>(0h8000080))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<28>(0h80000c0))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_61 = cvt(_address_ok_T_60)
node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_63 = asSInt(_address_ok_T_62)
node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0)))
node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_66 = cvt(_address_ok_T_65)
node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<13>(0h1000)))
node _address_ok_T_68 = asSInt(_address_ok_T_67)
node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0)))
node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<32>(0h80000040))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000080))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.b.bits.address, UInt<32>(0h800000c0))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[18]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
connect _address_ok_WIRE[12], _address_ok_T_64
connect _address_ok_WIRE[13], _address_ok_T_69
connect _address_ok_WIRE[14], _address_ok_T_74
connect _address_ok_WIRE[15], _address_ok_T_79
connect _address_ok_WIRE[16], _address_ok_T_84
connect _address_ok_WIRE[17], _address_ok_T_89
node _address_ok_T_90 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[2])
node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[3])
node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[4])
node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[5])
node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[6])
node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[7])
node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[8])
node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[9])
node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[10])
node _address_ok_T_100 = or(_address_ok_T_99, _address_ok_WIRE[11])
node _address_ok_T_101 = or(_address_ok_T_100, _address_ok_WIRE[12])
node _address_ok_T_102 = or(_address_ok_T_101, _address_ok_WIRE[13])
node _address_ok_T_103 = or(_address_ok_T_102, _address_ok_WIRE[14])
node _address_ok_T_104 = or(_address_ok_T_103, _address_ok_WIRE[15])
node _address_ok_T_105 = or(_address_ok_T_104, _address_ok_WIRE[16])
node address_ok = or(_address_ok_T_105, _address_ok_WIRE[17])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _legal_source_WIRE : UInt<1>[2]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3)
wire _legal_source_WIRE_1 : UInt<1>
connect _legal_source_WIRE_1, _legal_source_T_4
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1131 :
node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _WIRE_4 : UInt<1>[2]
connect _WIRE_4[0], _T_1132
connect _WIRE_4[1], _T_1133
node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0))
node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1137 = or(_T_1135, _T_1136)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1137
node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1140 = and(_T_1138, _T_1139)
node _T_1141 = or(UInt<1>(0h0), _T_1140)
node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1158 = cvt(_T_1157)
node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000)))
node _T_1160 = asSInt(_T_1159)
node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1163 = cvt(_T_1162)
node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000)))
node _T_1165 = asSInt(_T_1164)
node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0)))
node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1168 = cvt(_T_1167)
node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000)))
node _T_1170 = asSInt(_T_1169)
node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0)))
node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1173 = cvt(_T_1172)
node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000)))
node _T_1175 = asSInt(_T_1174)
node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0)))
node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1178 = cvt(_T_1177)
node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000)))
node _T_1180 = asSInt(_T_1179)
node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0)))
node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1183 = cvt(_T_1182)
node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000)))
node _T_1185 = asSInt(_T_1184)
node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0)))
node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1188 = cvt(_T_1187)
node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000)))
node _T_1190 = asSInt(_T_1189)
node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0)))
node _T_1192 = or(_T_1146, _T_1151)
node _T_1193 = or(_T_1192, _T_1156)
node _T_1194 = or(_T_1193, _T_1161)
node _T_1195 = or(_T_1194, _T_1166)
node _T_1196 = or(_T_1195, _T_1171)
node _T_1197 = or(_T_1196, _T_1176)
node _T_1198 = or(_T_1197, _T_1181)
node _T_1199 = or(_T_1198, _T_1186)
node _T_1200 = or(_T_1199, _T_1191)
node _T_1201 = and(_T_1141, _T_1200)
node _T_1202 = or(UInt<1>(0h0), _T_1201)
node _T_1203 = and(_WIRE_5, _T_1202)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(address_ok, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(legal_source, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90
node _T_1220 = eq(io.in.b.bits.mask, mask_1)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91
node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92
node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1228 :
node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1231 = and(_T_1229, _T_1230)
node _T_1232 = or(UInt<1>(0h0), _T_1231)
node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1234 = cvt(_T_1233)
node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000)))
node _T_1236 = asSInt(_T_1235)
node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0)))
node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1239 = cvt(_T_1238)
node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000)))
node _T_1241 = asSInt(_T_1240)
node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1244 = cvt(_T_1243)
node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000)))
node _T_1246 = asSInt(_T_1245)
node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0)))
node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1259 = cvt(_T_1258)
node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000)))
node _T_1261 = asSInt(_T_1260)
node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0)))
node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1264 = cvt(_T_1263)
node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000)))
node _T_1266 = asSInt(_T_1265)
node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0)))
node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1269 = cvt(_T_1268)
node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000)))
node _T_1271 = asSInt(_T_1270)
node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0)))
node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1274 = cvt(_T_1273)
node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000)))
node _T_1276 = asSInt(_T_1275)
node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0)))
node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1279 = cvt(_T_1278)
node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000)))
node _T_1281 = asSInt(_T_1280)
node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = or(_T_1237, _T_1242)
node _T_1284 = or(_T_1283, _T_1247)
node _T_1285 = or(_T_1284, _T_1252)
node _T_1286 = or(_T_1285, _T_1257)
node _T_1287 = or(_T_1286, _T_1262)
node _T_1288 = or(_T_1287, _T_1267)
node _T_1289 = or(_T_1288, _T_1272)
node _T_1290 = or(_T_1289, _T_1277)
node _T_1291 = or(_T_1290, _T_1282)
node _T_1292 = and(_T_1232, _T_1291)
node _T_1293 = or(UInt<1>(0h0), _T_1292)
node _T_1294 = and(UInt<1>(0h0), _T_1293)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(address_ok, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(legal_source, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97
node _T_1311 = eq(io.in.b.bits.mask, mask_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98
node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99
node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = or(UInt<1>(0h0), _T_1322)
node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1330 = cvt(_T_1329)
node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000)))
node _T_1332 = asSInt(_T_1331)
node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0)))
node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1335 = cvt(_T_1334)
node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000)))
node _T_1337 = asSInt(_T_1336)
node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0)))
node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1340 = cvt(_T_1339)
node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000)))
node _T_1342 = asSInt(_T_1341)
node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0)))
node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1345 = cvt(_T_1344)
node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000)))
node _T_1347 = asSInt(_T_1346)
node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0)))
node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1350 = cvt(_T_1349)
node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000)))
node _T_1352 = asSInt(_T_1351)
node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0)))
node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1355 = cvt(_T_1354)
node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000)))
node _T_1357 = asSInt(_T_1356)
node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0)))
node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1360 = cvt(_T_1359)
node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000)))
node _T_1362 = asSInt(_T_1361)
node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0)))
node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1365 = cvt(_T_1364)
node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000)))
node _T_1367 = asSInt(_T_1366)
node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0)))
node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1370 = cvt(_T_1369)
node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000)))
node _T_1372 = asSInt(_T_1371)
node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0)))
node _T_1374 = or(_T_1328, _T_1333)
node _T_1375 = or(_T_1374, _T_1338)
node _T_1376 = or(_T_1375, _T_1343)
node _T_1377 = or(_T_1376, _T_1348)
node _T_1378 = or(_T_1377, _T_1353)
node _T_1379 = or(_T_1378, _T_1358)
node _T_1380 = or(_T_1379, _T_1363)
node _T_1381 = or(_T_1380, _T_1368)
node _T_1382 = or(_T_1381, _T_1373)
node _T_1383 = and(_T_1323, _T_1382)
node _T_1384 = or(UInt<1>(0h0), _T_1383)
node _T_1385 = and(UInt<1>(0h0), _T_1384)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(address_ok, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(legal_source, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104
node _T_1402 = eq(io.in.b.bits.mask, mask_1)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105
node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1406 :
node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1409 = and(_T_1407, _T_1408)
node _T_1410 = or(UInt<1>(0h0), _T_1409)
node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1427 = cvt(_T_1426)
node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000)))
node _T_1429 = asSInt(_T_1428)
node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0)))
node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1432 = cvt(_T_1431)
node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000)))
node _T_1434 = asSInt(_T_1433)
node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0)))
node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1437 = cvt(_T_1436)
node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000)))
node _T_1439 = asSInt(_T_1438)
node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0)))
node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1442 = cvt(_T_1441)
node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000)))
node _T_1444 = asSInt(_T_1443)
node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0)))
node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1447 = cvt(_T_1446)
node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000)))
node _T_1449 = asSInt(_T_1448)
node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0)))
node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1452 = cvt(_T_1451)
node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000)))
node _T_1454 = asSInt(_T_1453)
node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0)))
node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1457 = cvt(_T_1456)
node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000)))
node _T_1459 = asSInt(_T_1458)
node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0)))
node _T_1461 = or(_T_1415, _T_1420)
node _T_1462 = or(_T_1461, _T_1425)
node _T_1463 = or(_T_1462, _T_1430)
node _T_1464 = or(_T_1463, _T_1435)
node _T_1465 = or(_T_1464, _T_1440)
node _T_1466 = or(_T_1465, _T_1445)
node _T_1467 = or(_T_1466, _T_1450)
node _T_1468 = or(_T_1467, _T_1455)
node _T_1469 = or(_T_1468, _T_1460)
node _T_1470 = and(_T_1410, _T_1469)
node _T_1471 = or(UInt<1>(0h0), _T_1470)
node _T_1472 = and(UInt<1>(0h0), _T_1471)
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(address_ok, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(legal_source, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110
node _T_1489 = not(mask_1)
node _T_1490 = and(io.in.b.bits.mask, _T_1489)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111
node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1495 :
node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1498 = and(_T_1496, _T_1497)
node _T_1499 = or(UInt<1>(0h0), _T_1498)
node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1501 = cvt(_T_1500)
node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000)))
node _T_1503 = asSInt(_T_1502)
node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0)))
node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1506 = cvt(_T_1505)
node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000)))
node _T_1508 = asSInt(_T_1507)
node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0)))
node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1511 = cvt(_T_1510)
node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000)))
node _T_1513 = asSInt(_T_1512)
node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0)))
node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1516 = cvt(_T_1515)
node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000)))
node _T_1518 = asSInt(_T_1517)
node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0)))
node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1521 = cvt(_T_1520)
node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000)))
node _T_1523 = asSInt(_T_1522)
node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0)))
node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1526 = cvt(_T_1525)
node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000)))
node _T_1528 = asSInt(_T_1527)
node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0)))
node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1531 = cvt(_T_1530)
node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000)))
node _T_1533 = asSInt(_T_1532)
node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0)))
node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1536 = cvt(_T_1535)
node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000)))
node _T_1538 = asSInt(_T_1537)
node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0)))
node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1541 = cvt(_T_1540)
node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000)))
node _T_1543 = asSInt(_T_1542)
node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0)))
node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1546 = cvt(_T_1545)
node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000)))
node _T_1548 = asSInt(_T_1547)
node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0)))
node _T_1550 = or(_T_1504, _T_1509)
node _T_1551 = or(_T_1550, _T_1514)
node _T_1552 = or(_T_1551, _T_1519)
node _T_1553 = or(_T_1552, _T_1524)
node _T_1554 = or(_T_1553, _T_1529)
node _T_1555 = or(_T_1554, _T_1534)
node _T_1556 = or(_T_1555, _T_1539)
node _T_1557 = or(_T_1556, _T_1544)
node _T_1558 = or(_T_1557, _T_1549)
node _T_1559 = and(_T_1499, _T_1558)
node _T_1560 = or(UInt<1>(0h0), _T_1559)
node _T_1561 = and(UInt<1>(0h0), _T_1560)
node _T_1562 = asUInt(reset)
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
when _T_1563 :
node _T_1564 = eq(_T_1561, UInt<1>(0h0))
when _T_1564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(address_ok, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(legal_source, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116
node _T_1578 = eq(io.in.b.bits.mask, mask_1)
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117
node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1582 :
node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1585 = and(_T_1583, _T_1584)
node _T_1586 = or(UInt<1>(0h0), _T_1585)
node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1588 = cvt(_T_1587)
node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000)))
node _T_1590 = asSInt(_T_1589)
node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0)))
node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1593 = cvt(_T_1592)
node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000)))
node _T_1595 = asSInt(_T_1594)
node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0)))
node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1598 = cvt(_T_1597)
node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000)))
node _T_1600 = asSInt(_T_1599)
node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0)))
node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1608 = cvt(_T_1607)
node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000)))
node _T_1610 = asSInt(_T_1609)
node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0)))
node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1613 = cvt(_T_1612)
node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000)))
node _T_1615 = asSInt(_T_1614)
node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0)))
node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1618 = cvt(_T_1617)
node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000)))
node _T_1620 = asSInt(_T_1619)
node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0)))
node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1623 = cvt(_T_1622)
node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000)))
node _T_1625 = asSInt(_T_1624)
node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0)))
node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1628 = cvt(_T_1627)
node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000)))
node _T_1630 = asSInt(_T_1629)
node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1633 = cvt(_T_1632)
node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000)))
node _T_1635 = asSInt(_T_1634)
node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0)))
node _T_1637 = or(_T_1591, _T_1596)
node _T_1638 = or(_T_1637, _T_1601)
node _T_1639 = or(_T_1638, _T_1606)
node _T_1640 = or(_T_1639, _T_1611)
node _T_1641 = or(_T_1640, _T_1616)
node _T_1642 = or(_T_1641, _T_1621)
node _T_1643 = or(_T_1642, _T_1626)
node _T_1644 = or(_T_1643, _T_1631)
node _T_1645 = or(_T_1644, _T_1636)
node _T_1646 = and(_T_1586, _T_1645)
node _T_1647 = or(UInt<1>(0h0), _T_1646)
node _T_1648 = and(UInt<1>(0h0), _T_1647)
node _T_1649 = asUInt(reset)
node _T_1650 = eq(_T_1649, UInt<1>(0h0))
when _T_1650 :
node _T_1651 = eq(_T_1648, UInt<1>(0h0))
when _T_1651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(address_ok, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(legal_source, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1658 = asUInt(reset)
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
when _T_1659 :
node _T_1660 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1662 = asUInt(reset)
node _T_1663 = eq(_T_1662, UInt<1>(0h0))
when _T_1663 :
node _T_1664 = eq(_T_1661, UInt<1>(0h0))
when _T_1664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122
node _T_1665 = eq(io.in.b.bits.mask, mask_1)
node _T_1666 = asUInt(reset)
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
when _T_1667 :
node _T_1668 = eq(_T_1665, UInt<1>(0h0))
when _T_1668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123
node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1669 :
node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1672 = and(_T_1670, _T_1671)
node _T_1673 = or(UInt<1>(0h0), _T_1672)
node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1675 = cvt(_T_1674)
node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000)))
node _T_1677 = asSInt(_T_1676)
node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0)))
node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1680 = cvt(_T_1679)
node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000)))
node _T_1682 = asSInt(_T_1681)
node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0)))
node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1685 = cvt(_T_1684)
node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000)))
node _T_1687 = asSInt(_T_1686)
node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0)))
node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1690 = cvt(_T_1689)
node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000)))
node _T_1692 = asSInt(_T_1691)
node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1695 = cvt(_T_1694)
node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000)))
node _T_1697 = asSInt(_T_1696)
node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0)))
node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1700 = cvt(_T_1699)
node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000)))
node _T_1702 = asSInt(_T_1701)
node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0)))
node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1705 = cvt(_T_1704)
node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000)))
node _T_1707 = asSInt(_T_1706)
node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0)))
node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1710 = cvt(_T_1709)
node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000)))
node _T_1712 = asSInt(_T_1711)
node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0)))
node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1715 = cvt(_T_1714)
node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000)))
node _T_1717 = asSInt(_T_1716)
node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0)))
node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1720 = cvt(_T_1719)
node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000)))
node _T_1722 = asSInt(_T_1721)
node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0)))
node _T_1724 = or(_T_1678, _T_1683)
node _T_1725 = or(_T_1724, _T_1688)
node _T_1726 = or(_T_1725, _T_1693)
node _T_1727 = or(_T_1726, _T_1698)
node _T_1728 = or(_T_1727, _T_1703)
node _T_1729 = or(_T_1728, _T_1708)
node _T_1730 = or(_T_1729, _T_1713)
node _T_1731 = or(_T_1730, _T_1718)
node _T_1732 = or(_T_1731, _T_1723)
node _T_1733 = and(_T_1673, _T_1732)
node _T_1734 = or(UInt<1>(0h0), _T_1733)
node _T_1735 = and(UInt<1>(0h0), _T_1734)
node _T_1736 = asUInt(reset)
node _T_1737 = eq(_T_1736, UInt<1>(0h0))
when _T_1737 :
node _T_1738 = eq(_T_1735, UInt<1>(0h0))
when _T_1738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124
node _T_1739 = asUInt(reset)
node _T_1740 = eq(_T_1739, UInt<1>(0h0))
when _T_1740 :
node _T_1741 = eq(address_ok, UInt<1>(0h0))
when _T_1741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1742 = asUInt(reset)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(legal_source, UInt<1>(0h0))
when _T_1744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1745 = asUInt(reset)
node _T_1746 = eq(_T_1745, UInt<1>(0h0))
when _T_1746 :
node _T_1747 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1748 = eq(io.in.b.bits.mask, mask_1)
node _T_1749 = asUInt(reset)
node _T_1750 = eq(_T_1749, UInt<1>(0h0))
when _T_1750 :
node _T_1751 = eq(_T_1748, UInt<1>(0h0))
when _T_1751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128
node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130
node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_2 : UInt<1>[2]
connect _source_ok_WIRE_2[0], _source_ok_T_4
connect _source_ok_WIRE_2[1], _source_ok_T_5
node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_106 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_107 = cvt(_address_ok_T_106)
node _address_ok_T_108 = and(_address_ok_T_107, asSInt(UInt<13>(0h1000)))
node _address_ok_T_109 = asSInt(_address_ok_T_108)
node _address_ok_T_110 = eq(_address_ok_T_109, asSInt(UInt<1>(0h0)))
node _address_ok_T_111 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_112 = cvt(_address_ok_T_111)
node _address_ok_T_113 = and(_address_ok_T_112, asSInt(UInt<13>(0h1000)))
node _address_ok_T_114 = asSInt(_address_ok_T_113)
node _address_ok_T_115 = eq(_address_ok_T_114, asSInt(UInt<1>(0h0)))
node _address_ok_T_116 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_117 = cvt(_address_ok_T_116)
node _address_ok_T_118 = and(_address_ok_T_117, asSInt(UInt<13>(0h1000)))
node _address_ok_T_119 = asSInt(_address_ok_T_118)
node _address_ok_T_120 = eq(_address_ok_T_119, asSInt(UInt<1>(0h0)))
node _address_ok_T_121 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_122 = cvt(_address_ok_T_121)
node _address_ok_T_123 = and(_address_ok_T_122, asSInt(UInt<17>(0h10000)))
node _address_ok_T_124 = asSInt(_address_ok_T_123)
node _address_ok_T_125 = eq(_address_ok_T_124, asSInt(UInt<1>(0h0)))
node _address_ok_T_126 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_127 = cvt(_address_ok_T_126)
node _address_ok_T_128 = and(_address_ok_T_127, asSInt(UInt<13>(0h1000)))
node _address_ok_T_129 = asSInt(_address_ok_T_128)
node _address_ok_T_130 = eq(_address_ok_T_129, asSInt(UInt<1>(0h0)))
node _address_ok_T_131 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_132 = cvt(_address_ok_T_131)
node _address_ok_T_133 = and(_address_ok_T_132, asSInt(UInt<13>(0h1000)))
node _address_ok_T_134 = asSInt(_address_ok_T_133)
node _address_ok_T_135 = eq(_address_ok_T_134, asSInt(UInt<1>(0h0)))
node _address_ok_T_136 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_137 = cvt(_address_ok_T_136)
node _address_ok_T_138 = and(_address_ok_T_137, asSInt(UInt<17>(0h10000)))
node _address_ok_T_139 = asSInt(_address_ok_T_138)
node _address_ok_T_140 = eq(_address_ok_T_139, asSInt(UInt<1>(0h0)))
node _address_ok_T_141 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_142 = cvt(_address_ok_T_141)
node _address_ok_T_143 = and(_address_ok_T_142, asSInt(UInt<13>(0h1000)))
node _address_ok_T_144 = asSInt(_address_ok_T_143)
node _address_ok_T_145 = eq(_address_ok_T_144, asSInt(UInt<1>(0h0)))
node _address_ok_T_146 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_147 = cvt(_address_ok_T_146)
node _address_ok_T_148 = and(_address_ok_T_147, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_149 = asSInt(_address_ok_T_148)
node _address_ok_T_150 = eq(_address_ok_T_149, asSInt(UInt<1>(0h0)))
node _address_ok_T_151 = xor(io.in.c.bits.address, UInt<28>(0h8000040))
node _address_ok_T_152 = cvt(_address_ok_T_151)
node _address_ok_T_153 = and(_address_ok_T_152, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_154 = asSInt(_address_ok_T_153)
node _address_ok_T_155 = eq(_address_ok_T_154, asSInt(UInt<1>(0h0)))
node _address_ok_T_156 = xor(io.in.c.bits.address, UInt<28>(0h8000080))
node _address_ok_T_157 = cvt(_address_ok_T_156)
node _address_ok_T_158 = and(_address_ok_T_157, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_159 = asSInt(_address_ok_T_158)
node _address_ok_T_160 = eq(_address_ok_T_159, asSInt(UInt<1>(0h0)))
node _address_ok_T_161 = xor(io.in.c.bits.address, UInt<28>(0h80000c0))
node _address_ok_T_162 = cvt(_address_ok_T_161)
node _address_ok_T_163 = and(_address_ok_T_162, asSInt(UInt<17>(0h100c0)))
node _address_ok_T_164 = asSInt(_address_ok_T_163)
node _address_ok_T_165 = eq(_address_ok_T_164, asSInt(UInt<1>(0h0)))
node _address_ok_T_166 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_167 = cvt(_address_ok_T_166)
node _address_ok_T_168 = and(_address_ok_T_167, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_169 = asSInt(_address_ok_T_168)
node _address_ok_T_170 = eq(_address_ok_T_169, asSInt(UInt<1>(0h0)))
node _address_ok_T_171 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_172 = cvt(_address_ok_T_171)
node _address_ok_T_173 = and(_address_ok_T_172, asSInt(UInt<13>(0h1000)))
node _address_ok_T_174 = asSInt(_address_ok_T_173)
node _address_ok_T_175 = eq(_address_ok_T_174, asSInt(UInt<1>(0h0)))
node _address_ok_T_176 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_177 = cvt(_address_ok_T_176)
node _address_ok_T_178 = and(_address_ok_T_177, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_179 = asSInt(_address_ok_T_178)
node _address_ok_T_180 = eq(_address_ok_T_179, asSInt(UInt<1>(0h0)))
node _address_ok_T_181 = xor(io.in.c.bits.address, UInt<32>(0h80000040))
node _address_ok_T_182 = cvt(_address_ok_T_181)
node _address_ok_T_183 = and(_address_ok_T_182, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_184 = asSInt(_address_ok_T_183)
node _address_ok_T_185 = eq(_address_ok_T_184, asSInt(UInt<1>(0h0)))
node _address_ok_T_186 = xor(io.in.c.bits.address, UInt<32>(0h80000080))
node _address_ok_T_187 = cvt(_address_ok_T_186)
node _address_ok_T_188 = and(_address_ok_T_187, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_189 = asSInt(_address_ok_T_188)
node _address_ok_T_190 = eq(_address_ok_T_189, asSInt(UInt<1>(0h0)))
node _address_ok_T_191 = xor(io.in.c.bits.address, UInt<32>(0h800000c0))
node _address_ok_T_192 = cvt(_address_ok_T_191)
node _address_ok_T_193 = and(_address_ok_T_192, asSInt(UInt<29>(0h100000c0)))
node _address_ok_T_194 = asSInt(_address_ok_T_193)
node _address_ok_T_195 = eq(_address_ok_T_194, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[18]
connect _address_ok_WIRE_1[0], _address_ok_T_110
connect _address_ok_WIRE_1[1], _address_ok_T_115
connect _address_ok_WIRE_1[2], _address_ok_T_120
connect _address_ok_WIRE_1[3], _address_ok_T_125
connect _address_ok_WIRE_1[4], _address_ok_T_130
connect _address_ok_WIRE_1[5], _address_ok_T_135
connect _address_ok_WIRE_1[6], _address_ok_T_140
connect _address_ok_WIRE_1[7], _address_ok_T_145
connect _address_ok_WIRE_1[8], _address_ok_T_150
connect _address_ok_WIRE_1[9], _address_ok_T_155
connect _address_ok_WIRE_1[10], _address_ok_T_160
connect _address_ok_WIRE_1[11], _address_ok_T_165
connect _address_ok_WIRE_1[12], _address_ok_T_170
connect _address_ok_WIRE_1[13], _address_ok_T_175
connect _address_ok_WIRE_1[14], _address_ok_T_180
connect _address_ok_WIRE_1[15], _address_ok_T_185
connect _address_ok_WIRE_1[16], _address_ok_T_190
connect _address_ok_WIRE_1[17], _address_ok_T_195
node _address_ok_T_196 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[2])
node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[3])
node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[4])
node _address_ok_T_200 = or(_address_ok_T_199, _address_ok_WIRE_1[5])
node _address_ok_T_201 = or(_address_ok_T_200, _address_ok_WIRE_1[6])
node _address_ok_T_202 = or(_address_ok_T_201, _address_ok_WIRE_1[7])
node _address_ok_T_203 = or(_address_ok_T_202, _address_ok_WIRE_1[8])
node _address_ok_T_204 = or(_address_ok_T_203, _address_ok_WIRE_1[9])
node _address_ok_T_205 = or(_address_ok_T_204, _address_ok_WIRE_1[10])
node _address_ok_T_206 = or(_address_ok_T_205, _address_ok_WIRE_1[11])
node _address_ok_T_207 = or(_address_ok_T_206, _address_ok_WIRE_1[12])
node _address_ok_T_208 = or(_address_ok_T_207, _address_ok_WIRE_1[13])
node _address_ok_T_209 = or(_address_ok_T_208, _address_ok_WIRE_1[14])
node _address_ok_T_210 = or(_address_ok_T_209, _address_ok_WIRE_1[15])
node _address_ok_T_211 = or(_address_ok_T_210, _address_ok_WIRE_1[16])
node address_ok_1 = or(_address_ok_T_211, _address_ok_WIRE_1[17])
node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1761, _T_1766)
node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1771 = cvt(_T_1770)
node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0)))
node _T_1773 = asSInt(_T_1772)
node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0)))
node _T_1775 = or(_T_1769, _T_1774)
node _T_1776 = and(_T_1767, _T_1775)
node _T_1777 = asUInt(reset)
node _T_1778 = eq(_T_1777, UInt<1>(0h0))
when _T_1778 :
node _T_1779 = eq(_T_1776, UInt<1>(0h0))
when _T_1779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131
node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1780 :
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(address_ok_1, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1784 = asUInt(reset)
node _T_1785 = eq(_T_1784, UInt<1>(0h0))
when _T_1785 :
node _T_1786 = eq(source_ok_2, UInt<1>(0h0))
when _T_1786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(_T_1787, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134
node _T_1791 = asUInt(reset)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
when _T_1792 :
node _T_1793 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(_T_1794, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136
node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137
node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1802 :
node _T_1803 = asUInt(reset)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
when _T_1804 :
node _T_1805 = eq(address_ok_1, UInt<1>(0h0))
when _T_1805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1806 = asUInt(reset)
node _T_1807 = eq(_T_1806, UInt<1>(0h0))
when _T_1807 :
node _T_1808 = eq(source_ok_2, UInt<1>(0h0))
when _T_1808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1810 = asUInt(reset)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
when _T_1811 :
node _T_1812 = eq(_T_1809, UInt<1>(0h0))
when _T_1812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(_T_1816, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142
node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1820 :
node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1823 = and(_T_1821, _T_1822)
node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1826 = or(_T_1824, _T_1825)
node _T_1827 = and(_T_1823, _T_1826)
node _T_1828 = or(UInt<1>(0h0), _T_1827)
node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1831 = cvt(_T_1830)
node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000)))
node _T_1833 = asSInt(_T_1832)
node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0)))
node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1836 = cvt(_T_1835)
node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000)))
node _T_1838 = asSInt(_T_1837)
node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0)))
node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1841 = cvt(_T_1840)
node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000)))
node _T_1843 = asSInt(_T_1842)
node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0)))
node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1846 = cvt(_T_1845)
node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000)))
node _T_1848 = asSInt(_T_1847)
node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0)))
node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1851 = cvt(_T_1850)
node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000)))
node _T_1853 = asSInt(_T_1852)
node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0)))
node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1856 = cvt(_T_1855)
node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000)))
node _T_1858 = asSInt(_T_1857)
node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0)))
node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1861 = cvt(_T_1860)
node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000)))
node _T_1863 = asSInt(_T_1862)
node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0)))
node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1866 = cvt(_T_1865)
node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000)))
node _T_1868 = asSInt(_T_1867)
node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0)))
node _T_1870 = or(_T_1834, _T_1839)
node _T_1871 = or(_T_1870, _T_1844)
node _T_1872 = or(_T_1871, _T_1849)
node _T_1873 = or(_T_1872, _T_1854)
node _T_1874 = or(_T_1873, _T_1859)
node _T_1875 = or(_T_1874, _T_1864)
node _T_1876 = or(_T_1875, _T_1869)
node _T_1877 = and(_T_1829, _T_1876)
node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1879 = or(UInt<1>(0h0), _T_1878)
node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1881 = cvt(_T_1880)
node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000)))
node _T_1883 = asSInt(_T_1882)
node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0)))
node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1886 = cvt(_T_1885)
node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000)))
node _T_1888 = asSInt(_T_1887)
node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0)))
node _T_1890 = or(_T_1884, _T_1889)
node _T_1891 = and(_T_1879, _T_1890)
node _T_1892 = or(UInt<1>(0h0), _T_1877)
node _T_1893 = or(_T_1892, _T_1891)
node _T_1894 = and(_T_1828, _T_1893)
node _T_1895 = asUInt(reset)
node _T_1896 = eq(_T_1895, UInt<1>(0h0))
when _T_1896 :
node _T_1897 = eq(_T_1894, UInt<1>(0h0))
when _T_1897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143
node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_6 : UInt<1>[2]
connect _WIRE_6[0], _T_1898
connect _WIRE_6[1], _T_1899
node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0))
node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1903 = or(_T_1901, _T_1902)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1903
node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1906 = and(_T_1904, _T_1905)
node _T_1907 = or(UInt<1>(0h0), _T_1906)
node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1909 = cvt(_T_1908)
node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000)))
node _T_1911 = asSInt(_T_1910)
node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0)))
node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1914 = cvt(_T_1913)
node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000)))
node _T_1916 = asSInt(_T_1915)
node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0)))
node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1919 = cvt(_T_1918)
node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000)))
node _T_1921 = asSInt(_T_1920)
node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0)))
node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1924 = cvt(_T_1923)
node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000)))
node _T_1926 = asSInt(_T_1925)
node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0)))
node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1929 = cvt(_T_1928)
node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000)))
node _T_1931 = asSInt(_T_1930)
node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0)))
node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1934 = cvt(_T_1933)
node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000)))
node _T_1936 = asSInt(_T_1935)
node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0)))
node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1939 = cvt(_T_1938)
node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000)))
node _T_1941 = asSInt(_T_1940)
node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0)))
node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1944 = cvt(_T_1943)
node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000)))
node _T_1946 = asSInt(_T_1945)
node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0)))
node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1949 = cvt(_T_1948)
node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000)))
node _T_1951 = asSInt(_T_1950)
node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0)))
node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1954 = cvt(_T_1953)
node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000)))
node _T_1956 = asSInt(_T_1955)
node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0)))
node _T_1958 = or(_T_1912, _T_1917)
node _T_1959 = or(_T_1958, _T_1922)
node _T_1960 = or(_T_1959, _T_1927)
node _T_1961 = or(_T_1960, _T_1932)
node _T_1962 = or(_T_1961, _T_1937)
node _T_1963 = or(_T_1962, _T_1942)
node _T_1964 = or(_T_1963, _T_1947)
node _T_1965 = or(_T_1964, _T_1952)
node _T_1966 = or(_T_1965, _T_1957)
node _T_1967 = and(_T_1907, _T_1966)
node _T_1968 = or(UInt<1>(0h0), _T_1967)
node _T_1969 = and(_WIRE_7, _T_1968)
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(_T_1969, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(source_ok_2, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146
node _T_1980 = asUInt(reset)
node _T_1981 = eq(_T_1980, UInt<1>(0h0))
when _T_1981 :
node _T_1982 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(_T_1983, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148
node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1988 = asUInt(reset)
node _T_1989 = eq(_T_1988, UInt<1>(0h0))
when _T_1989 :
node _T_1990 = eq(_T_1987, UInt<1>(0h0))
when _T_1990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149
node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1991 :
node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1994 = and(_T_1992, _T_1993)
node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1997 = or(_T_1995, _T_1996)
node _T_1998 = and(_T_1994, _T_1997)
node _T_1999 = or(UInt<1>(0h0), _T_1998)
node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2002 = cvt(_T_2001)
node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000)))
node _T_2004 = asSInt(_T_2003)
node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0)))
node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2007 = cvt(_T_2006)
node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000)))
node _T_2009 = asSInt(_T_2008)
node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0)))
node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2012 = cvt(_T_2011)
node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000)))
node _T_2014 = asSInt(_T_2013)
node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0)))
node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2017 = cvt(_T_2016)
node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000)))
node _T_2019 = asSInt(_T_2018)
node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0)))
node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2022 = cvt(_T_2021)
node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000)))
node _T_2024 = asSInt(_T_2023)
node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0)))
node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2027 = cvt(_T_2026)
node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000)))
node _T_2029 = asSInt(_T_2028)
node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0)))
node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2032 = cvt(_T_2031)
node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000)))
node _T_2034 = asSInt(_T_2033)
node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0)))
node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2037 = cvt(_T_2036)
node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000)))
node _T_2039 = asSInt(_T_2038)
node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0)))
node _T_2041 = or(_T_2005, _T_2010)
node _T_2042 = or(_T_2041, _T_2015)
node _T_2043 = or(_T_2042, _T_2020)
node _T_2044 = or(_T_2043, _T_2025)
node _T_2045 = or(_T_2044, _T_2030)
node _T_2046 = or(_T_2045, _T_2035)
node _T_2047 = or(_T_2046, _T_2040)
node _T_2048 = and(_T_2000, _T_2047)
node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2050 = or(UInt<1>(0h0), _T_2049)
node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2052 = cvt(_T_2051)
node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000)))
node _T_2054 = asSInt(_T_2053)
node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0)))
node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2057 = cvt(_T_2056)
node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000)))
node _T_2059 = asSInt(_T_2058)
node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0)))
node _T_2061 = or(_T_2055, _T_2060)
node _T_2062 = and(_T_2050, _T_2061)
node _T_2063 = or(UInt<1>(0h0), _T_2048)
node _T_2064 = or(_T_2063, _T_2062)
node _T_2065 = and(_T_1999, _T_2064)
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150
node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_8 : UInt<1>[2]
connect _WIRE_8[0], _T_2069
connect _WIRE_8[1], _T_2070
node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0))
node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2074 = or(_T_2072, _T_2073)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2074
node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2077 = and(_T_2075, _T_2076)
node _T_2078 = or(UInt<1>(0h0), _T_2077)
node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2080 = cvt(_T_2079)
node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000)))
node _T_2082 = asSInt(_T_2081)
node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0)))
node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2085 = cvt(_T_2084)
node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000)))
node _T_2087 = asSInt(_T_2086)
node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0)))
node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2090 = cvt(_T_2089)
node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000)))
node _T_2092 = asSInt(_T_2091)
node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0)))
node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2095 = cvt(_T_2094)
node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000)))
node _T_2097 = asSInt(_T_2096)
node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0)))
node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2100 = cvt(_T_2099)
node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000)))
node _T_2102 = asSInt(_T_2101)
node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0)))
node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2105 = cvt(_T_2104)
node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000)))
node _T_2107 = asSInt(_T_2106)
node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0)))
node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2110 = cvt(_T_2109)
node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000)))
node _T_2112 = asSInt(_T_2111)
node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0)))
node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2115 = cvt(_T_2114)
node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000)))
node _T_2117 = asSInt(_T_2116)
node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0)))
node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2120 = cvt(_T_2119)
node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000)))
node _T_2122 = asSInt(_T_2121)
node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0)))
node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2125 = cvt(_T_2124)
node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000)))
node _T_2127 = asSInt(_T_2126)
node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0)))
node _T_2129 = or(_T_2083, _T_2088)
node _T_2130 = or(_T_2129, _T_2093)
node _T_2131 = or(_T_2130, _T_2098)
node _T_2132 = or(_T_2131, _T_2103)
node _T_2133 = or(_T_2132, _T_2108)
node _T_2134 = or(_T_2133, _T_2113)
node _T_2135 = or(_T_2134, _T_2118)
node _T_2136 = or(_T_2135, _T_2123)
node _T_2137 = or(_T_2136, _T_2128)
node _T_2138 = and(_T_2078, _T_2137)
node _T_2139 = or(UInt<1>(0h0), _T_2138)
node _T_2140 = and(_WIRE_9, _T_2139)
node _T_2141 = asUInt(reset)
node _T_2142 = eq(_T_2141, UInt<1>(0h0))
when _T_2142 :
node _T_2143 = eq(_T_2140, UInt<1>(0h0))
when _T_2143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151
node _T_2144 = asUInt(reset)
node _T_2145 = eq(_T_2144, UInt<1>(0h0))
when _T_2145 :
node _T_2146 = eq(source_ok_2, UInt<1>(0h0))
when _T_2146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2148 = asUInt(reset)
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
when _T_2149 :
node _T_2150 = eq(_T_2147, UInt<1>(0h0))
when _T_2150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153
node _T_2151 = asUInt(reset)
node _T_2152 = eq(_T_2151, UInt<1>(0h0))
when _T_2152 :
node _T_2153 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2155 = asUInt(reset)
node _T_2156 = eq(_T_2155, UInt<1>(0h0))
when _T_2156 :
node _T_2157 = eq(_T_2154, UInt<1>(0h0))
when _T_2157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155
node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2158 :
node _T_2159 = asUInt(reset)
node _T_2160 = eq(_T_2159, UInt<1>(0h0))
when _T_2160 :
node _T_2161 = eq(address_ok_1, UInt<1>(0h0))
when _T_2161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(source_ok_2, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2165 = asUInt(reset)
node _T_2166 = eq(_T_2165, UInt<1>(0h0))
when _T_2166 :
node _T_2167 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2169 = asUInt(reset)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
when _T_2170 :
node _T_2171 = eq(_T_2168, UInt<1>(0h0))
when _T_2171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159
node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2173 = asUInt(reset)
node _T_2174 = eq(_T_2173, UInt<1>(0h0))
when _T_2174 :
node _T_2175 = eq(_T_2172, UInt<1>(0h0))
when _T_2175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160
node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2176 :
node _T_2177 = asUInt(reset)
node _T_2178 = eq(_T_2177, UInt<1>(0h0))
when _T_2178 :
node _T_2179 = eq(address_ok_1, UInt<1>(0h0))
when _T_2179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2180 = asUInt(reset)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
when _T_2181 :
node _T_2182 = eq(source_ok_2, UInt<1>(0h0))
when _T_2182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2183 = asUInt(reset)
node _T_2184 = eq(_T_2183, UInt<1>(0h0))
when _T_2184 :
node _T_2185 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2187 = asUInt(reset)
node _T_2188 = eq(_T_2187, UInt<1>(0h0))
when _T_2188 :
node _T_2189 = eq(_T_2186, UInt<1>(0h0))
when _T_2189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164
node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2190 :
node _T_2191 = asUInt(reset)
node _T_2192 = eq(_T_2191, UInt<1>(0h0))
when _T_2192 :
node _T_2193 = eq(address_ok_1, UInt<1>(0h0))
when _T_2193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2194 = asUInt(reset)
node _T_2195 = eq(_T_2194, UInt<1>(0h0))
when _T_2195 :
node _T_2196 = eq(source_ok_2, UInt<1>(0h0))
when _T_2196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2197 = asUInt(reset)
node _T_2198 = eq(_T_2197, UInt<1>(0h0))
when _T_2198 :
node _T_2199 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2201 = asUInt(reset)
node _T_2202 = eq(_T_2201, UInt<1>(0h0))
when _T_2202 :
node _T_2203 = eq(_T_2200, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168
node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2205 = asUInt(reset)
node _T_2206 = eq(_T_2205, UInt<1>(0h0))
when _T_2206 :
node _T_2207 = eq(_T_2204, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<6>(0h20))
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
node _T_2210 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2211 = eq(a_first, UInt<1>(0h0))
node _T_2212 = and(io.in.a.valid, _T_2211)
when _T_2212 :
node _T_2213 = eq(io.in.a.bits.opcode, opcode)
node _T_2214 = asUInt(reset)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
when _T_2215 :
node _T_2216 = eq(_T_2213, UInt<1>(0h0))
when _T_2216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171
node _T_2217 = eq(io.in.a.bits.param, param)
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
node _T_2220 = eq(_T_2217, UInt<1>(0h0))
when _T_2220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172
node _T_2221 = eq(io.in.a.bits.size, size)
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
node _T_2224 = eq(_T_2221, UInt<1>(0h0))
when _T_2224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173
node _T_2225 = eq(io.in.a.bits.source, source)
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(_T_2225, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174
node _T_2229 = eq(io.in.a.bits.address, address)
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(_T_2229, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175
node _T_2233 = and(io.in.a.ready, io.in.a.valid)
node _T_2234 = and(_T_2233, a_first)
when _T_2234 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2235 = eq(d_first, UInt<1>(0h0))
node _T_2236 = and(io.in.d.valid, _T_2235)
when _T_2236 :
node _T_2237 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
node _T_2240 = eq(_T_2237, UInt<1>(0h0))
when _T_2240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176
node _T_2241 = eq(io.in.d.bits.param, param_1)
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(_T_2241, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177
node _T_2245 = eq(io.in.d.bits.size, size_1)
node _T_2246 = asUInt(reset)
node _T_2247 = eq(_T_2246, UInt<1>(0h0))
when _T_2247 :
node _T_2248 = eq(_T_2245, UInt<1>(0h0))
when _T_2248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178
node _T_2249 = eq(io.in.d.bits.source, source_1)
node _T_2250 = asUInt(reset)
node _T_2251 = eq(_T_2250, UInt<1>(0h0))
when _T_2251 :
node _T_2252 = eq(_T_2249, UInt<1>(0h0))
when _T_2252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179
node _T_2253 = eq(io.in.d.bits.sink, sink)
node _T_2254 = asUInt(reset)
node _T_2255 = eq(_T_2254, UInt<1>(0h0))
when _T_2255 :
node _T_2256 = eq(_T_2253, UInt<1>(0h0))
when _T_2256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180
node _T_2257 = eq(io.in.d.bits.denied, denied)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181
node _T_2261 = and(io.in.d.ready, io.in.d.valid)
node _T_2262 = and(_T_2261, d_first)
when _T_2262 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2263 = eq(b_first, UInt<1>(0h0))
node _T_2264 = and(io.in.b.valid, _T_2263)
when _T_2264 :
node _T_2265 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
node _T_2268 = eq(_T_2265, UInt<1>(0h0))
when _T_2268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182
node _T_2269 = eq(io.in.b.bits.param, param_2)
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(_T_2269, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183
node _T_2273 = eq(io.in.b.bits.size, size_2)
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
node _T_2276 = eq(_T_2273, UInt<1>(0h0))
when _T_2276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184
node _T_2277 = eq(io.in.b.bits.source, source_2)
node _T_2278 = asUInt(reset)
node _T_2279 = eq(_T_2278, UInt<1>(0h0))
when _T_2279 :
node _T_2280 = eq(_T_2277, UInt<1>(0h0))
when _T_2280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185
node _T_2281 = eq(io.in.b.bits.address, address_1)
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
node _T_2284 = eq(_T_2281, UInt<1>(0h0))
when _T_2284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186
node _T_2285 = and(io.in.b.ready, io.in.b.valid)
node _T_2286 = and(_T_2285, b_first)
when _T_2286 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2287 = eq(c_first, UInt<1>(0h0))
node _T_2288 = and(io.in.c.valid, _T_2287)
when _T_2288 :
node _T_2289 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2290 = asUInt(reset)
node _T_2291 = eq(_T_2290, UInt<1>(0h0))
when _T_2291 :
node _T_2292 = eq(_T_2289, UInt<1>(0h0))
when _T_2292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187
node _T_2293 = eq(io.in.c.bits.param, param_3)
node _T_2294 = asUInt(reset)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
when _T_2295 :
node _T_2296 = eq(_T_2293, UInt<1>(0h0))
when _T_2296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188
node _T_2297 = eq(io.in.c.bits.size, size_3)
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
node _T_2300 = eq(_T_2297, UInt<1>(0h0))
when _T_2300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189
node _T_2301 = eq(io.in.c.bits.source, source_3)
node _T_2302 = asUInt(reset)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
when _T_2303 :
node _T_2304 = eq(_T_2301, UInt<1>(0h0))
when _T_2304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190
node _T_2305 = eq(io.in.c.bits.address, address_2)
node _T_2306 = asUInt(reset)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
when _T_2307 :
node _T_2308 = eq(_T_2305, UInt<1>(0h0))
when _T_2308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191
node _T_2309 = and(io.in.c.ready, io.in.c.valid)
node _T_2310 = and(_T_2309, c_first)
when _T_2310 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2>
connect a_set, UInt<2>(0h0)
wire a_set_wo_ready : UInt<2>
connect a_set_wo_ready, UInt<2>(0h0)
wire a_opcodes_set : UInt<8>
connect a_opcodes_set, UInt<8>(0h0)
wire a_sizes_set : UInt<16>
connect a_sizes_set, UInt<16>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2311 = and(io.in.a.valid, a_first_1)
node _T_2312 = and(_T_2311, UInt<1>(0h1))
when _T_2312 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2313 = and(io.in.a.ready, io.in.a.valid)
node _T_2314 = and(_T_2313, a_first_1)
node _T_2315 = and(_T_2314, UInt<1>(0h1))
when _T_2315 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2316 = dshr(inflight, io.in.a.bits.source)
node _T_2317 = bits(_T_2316, 0, 0)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
node _T_2319 = asUInt(reset)
node _T_2320 = eq(_T_2319, UInt<1>(0h0))
when _T_2320 :
node _T_2321 = eq(_T_2318, UInt<1>(0h0))
when _T_2321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<2>
connect d_clr, UInt<2>(0h0)
wire d_clr_wo_ready : UInt<2>
connect d_clr_wo_ready, UInt<2>(0h0)
wire d_opcodes_clr : UInt<8>
connect d_opcodes_clr, UInt<8>(0h0)
wire d_sizes_clr : UInt<16>
connect d_sizes_clr, UInt<16>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2322 = and(io.in.d.valid, d_first_1)
node _T_2323 = and(_T_2322, UInt<1>(0h1))
node _T_2324 = eq(d_release_ack, UInt<1>(0h0))
node _T_2325 = and(_T_2323, _T_2324)
when _T_2325 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2326 = and(io.in.d.ready, io.in.d.valid)
node _T_2327 = and(_T_2326, d_first_1)
node _T_2328 = and(_T_2327, UInt<1>(0h1))
node _T_2329 = eq(d_release_ack, UInt<1>(0h0))
node _T_2330 = and(_T_2328, _T_2329)
when _T_2330 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2331 = and(io.in.d.valid, d_first_1)
node _T_2332 = and(_T_2331, UInt<1>(0h1))
node _T_2333 = eq(d_release_ack, UInt<1>(0h0))
node _T_2334 = and(_T_2332, _T_2333)
when _T_2334 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2335 = dshr(inflight, io.in.d.bits.source)
node _T_2336 = bits(_T_2335, 0, 0)
node _T_2337 = or(_T_2336, same_cycle_resp)
node _T_2338 = asUInt(reset)
node _T_2339 = eq(_T_2338, UInt<1>(0h0))
when _T_2339 :
node _T_2340 = eq(_T_2337, UInt<1>(0h0))
when _T_2340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2343 = or(_T_2341, _T_2342)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194
node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2348 = asUInt(reset)
node _T_2349 = eq(_T_2348, UInt<1>(0h0))
when _T_2349 :
node _T_2350 = eq(_T_2347, UInt<1>(0h0))
when _T_2350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195
else :
node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2353 = or(_T_2351, _T_2352)
node _T_2354 = asUInt(reset)
node _T_2355 = eq(_T_2354, UInt<1>(0h0))
when _T_2355 :
node _T_2356 = eq(_T_2353, UInt<1>(0h0))
when _T_2356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196
node _T_2357 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2358 = asUInt(reset)
node _T_2359 = eq(_T_2358, UInt<1>(0h0))
when _T_2359 :
node _T_2360 = eq(_T_2357, UInt<1>(0h0))
when _T_2360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197
node _T_2361 = and(io.in.d.valid, d_first_1)
node _T_2362 = and(_T_2361, a_first_1)
node _T_2363 = and(_T_2362, io.in.a.valid)
node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2365 = and(_T_2363, _T_2364)
node _T_2366 = eq(d_release_ack, UInt<1>(0h0))
node _T_2367 = and(_T_2365, _T_2366)
when _T_2367 :
node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2369 = or(_T_2368, io.in.a.ready)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198
node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2374 = orr(a_set_wo_ready)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
node _T_2376 = or(_T_2373, _T_2375)
node _T_2377 = asUInt(reset)
node _T_2378 = eq(_T_2377, UInt<1>(0h0))
when _T_2378 :
node _T_2379 = eq(_T_2376, UInt<1>(0h0))
when _T_2379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_146
node _T_2380 = orr(inflight)
node _T_2381 = eq(_T_2380, UInt<1>(0h0))
node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2383 = or(_T_2381, _T_2382)
node _T_2384 = lt(watchdog, plusarg_reader.out)
node _T_2385 = or(_T_2383, _T_2384)
node _T_2386 = asUInt(reset)
node _T_2387 = eq(_T_2386, UInt<1>(0h0))
when _T_2387 :
node _T_2388 = eq(_T_2385, UInt<1>(0h0))
when _T_2388 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2389 = and(io.in.a.ready, io.in.a.valid)
node _T_2390 = and(io.in.d.ready, io.in.d.valid)
node _T_2391 = or(_T_2389, _T_2390)
when _T_2391 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2>
connect c_set, UInt<2>(0h0)
wire c_set_wo_ready : UInt<2>
connect c_set_wo_ready, UInt<2>(0h0)
wire c_opcodes_set : UInt<8>
connect c_opcodes_set, UInt<8>(0h0)
wire c_sizes_set : UInt<16>
connect c_sizes_set, UInt<16>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2392 = and(io.in.c.valid, c_first_1)
node _T_2393 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2394 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2395 = and(_T_2393, _T_2394)
node _T_2396 = and(_T_2392, _T_2395)
when _T_2396 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2397 = and(io.in.c.ready, io.in.c.valid)
node _T_2398 = and(_T_2397, c_first_1)
node _T_2399 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2400 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2401 = and(_T_2399, _T_2400)
node _T_2402 = and(_T_2398, _T_2401)
when _T_2402 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2403 = dshr(inflight_1, io.in.c.bits.source)
node _T_2404 = bits(_T_2403, 0, 0)
node _T_2405 = eq(_T_2404, UInt<1>(0h0))
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2>
connect d_clr_1, UInt<2>(0h0)
wire d_clr_wo_ready_1 : UInt<2>
connect d_clr_wo_ready_1, UInt<2>(0h0)
wire d_opcodes_clr_1 : UInt<8>
connect d_opcodes_clr_1, UInt<8>(0h0)
wire d_sizes_clr_1 : UInt<16>
connect d_sizes_clr_1, UInt<16>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2409 = and(io.in.d.valid, d_first_2)
node _T_2410 = and(_T_2409, UInt<1>(0h1))
node _T_2411 = and(_T_2410, d_release_ack_1)
when _T_2411 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2412 = and(io.in.d.ready, io.in.d.valid)
node _T_2413 = and(_T_2412, d_first_2)
node _T_2414 = and(_T_2413, UInt<1>(0h1))
node _T_2415 = and(_T_2414, d_release_ack_1)
when _T_2415 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2416 = and(io.in.d.valid, d_first_2)
node _T_2417 = and(_T_2416, UInt<1>(0h1))
node _T_2418 = and(_T_2417, d_release_ack_1)
when _T_2418 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2419 = dshr(inflight_1, io.in.d.bits.source)
node _T_2420 = bits(_T_2419, 0, 0)
node _T_2421 = or(_T_2420, same_cycle_resp_1)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203
else :
node _T_2429 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204
node _T_2433 = and(io.in.d.valid, d_first_2)
node _T_2434 = and(_T_2433, c_first_1)
node _T_2435 = and(_T_2434, io.in.c.valid)
node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2437 = and(_T_2435, _T_2436)
node _T_2438 = and(_T_2437, d_release_ack_1)
node _T_2439 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2440 = and(_T_2438, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2442 = or(_T_2441, io.in.c.ready)
node _T_2443 = asUInt(reset)
node _T_2444 = eq(_T_2443, UInt<1>(0h0))
when _T_2444 :
node _T_2445 = eq(_T_2442, UInt<1>(0h0))
when _T_2445 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205
node _T_2446 = orr(c_set_wo_ready)
when _T_2446 :
node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_147
node _T_2451 = orr(inflight_1)
node _T_2452 = eq(_T_2451, UInt<1>(0h0))
node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2454 = or(_T_2452, _T_2453)
node _T_2455 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2456 = or(_T_2454, _T_2455)
node _T_2457 = asUInt(reset)
node _T_2458 = eq(_T_2457, UInt<1>(0h0))
when _T_2458 :
node _T_2459 = eq(_T_2456, UInt<1>(0h0))
when _T_2459 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2460 = and(io.in.c.ready, io.in.c.valid)
node _T_2461 = and(io.in.d.ready, io.in.d.valid)
node _T_2462 = or(_T_2460, _T_2461)
when _T_2462 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<32>, clock, reset, UInt<32>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<32>
connect d_set, UInt<32>(0h0)
node _T_2463 = and(io.in.d.ready, io.in.d.valid)
node _T_2464 = and(_T_2463, d_first_3)
node _T_2465 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2466 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = and(_T_2465, _T_2467)
node _T_2469 = and(_T_2464, _T_2468)
when _T_2469 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2470 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2471 = bits(_T_2470, 0, 0)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(_T_2472, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<32>
connect e_clr, UInt<32>(0h0)
node _T_2476 = and(io.in.e.ready, io.in.e.valid)
node _T_2477 = and(_T_2476, UInt<1>(0h1))
node _T_2478 = and(_T_2477, UInt<1>(0h1))
when _T_2478 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2479 = or(d_set, inflight_2)
node _T_2480 = dshr(_T_2479, io.in.e.bits.sink)
node _T_2481 = bits(_T_2480, 0, 0)
node _T_2482 = asUInt(reset)
node _T_2483 = eq(_T_2482, UInt<1>(0h0))
when _T_2483 :
node _T_2484 = eq(_T_2481, UInt<1>(0h0))
when _T_2484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_148 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_149 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_60( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [4:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [15:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [1:0] _GEN_1 = {1'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [1:0] _GEN_6 = {1'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [31:0] inflight_2; // @[Monitor.scala:828:27]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [31:0] _GEN_9 = {27'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [31:0] d_set = _GEN_8 ? 32'h1 << _GEN_9 : 32'h0; // @[OneHot.scala:58:35]
wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35]
wire [31:0] _GEN_11 = {27'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module LoopMatmul :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, rob_id : { valid : UInt<1>, bits : UInt<6>}, from_matmul_fsm : UInt<1>, from_conv_fsm : UInt<1>}}, flip ld_completed : UInt<6>, flip st_completed : UInt<6>, flip ex_completed : UInt<6>, busy : UInt<1>}
reg loops : { max_k : UInt<16>, max_j : UInt<16>, max_i : UInt<16>, pad_k : UInt<16>, pad_j : UInt<16>, pad_i : UInt<16>, a_dram_addr : UInt<40>, b_dram_addr : UInt<40>, d_dram_addr : UInt<40>, c_dram_addr : UInt<40>, a_dram_stride : UInt<40>, b_dram_stride : UInt<40>, d_dram_stride : UInt<40>, c_dram_stride : UInt<40>, a_transpose : UInt<1>, b_transpose : UInt<1>, act : UInt<3>, low_d : UInt<1>, full_c : UInt<1>, ex_accumulate : UInt<1>, a_ex_spad_id : UInt<2>, b_ex_spad_id : UInt<2>, configured : UInt<1>, running : UInt<1>, lda_started : UInt<1>, ldb_started : UInt<1>, ex_started : UInt<1>, ldd_started : UInt<1>, st_started : UInt<1>, lda_completed : UInt<1>, ldb_completed : UInt<1>, ex_completed : UInt<1>, ldd_completed : UInt<1>, st_completed : UInt<1>, a_addr_start : UInt<14>, b_addr_end : UInt<15>, resadd_addr_start : UInt<10>}[2], clock
reg head_loop_id : UInt<1>, clock
node tail_loop_id = not(head_loop_id)
node loop_configured = or(loops[0].configured, loops[1].configured)
node loop_being_configured_id = mux(loops[head_loop_id].configured, tail_loop_id, head_loop_id)
regreset is_resadd : UInt<1>, clock, reset, UInt<1>(0h0)
inst ldA of LoopMatmulLdA
connect ldA.clock, clock
connect ldA.reset, reset
inst ldB of LoopMatmulLdB
connect ldB.clock, clock
connect ldB.reset, reset
inst ldD of LoopMatmulLdD
connect ldD.clock, clock
connect ldD.reset, reset
inst ex of LoopMatmulExecute
connect ex.clock, clock
connect ex.reset, reset
inst stC of LoopMatmulStC
connect stC.clock, clock
connect stC.reset, reset
inst cmd_q of Queue2_GemminiCmd_2
connect cmd_q.clock, clock
connect cmd_q.reset, reset
connect cmd_q.io.enq.valid, io.in.valid
connect cmd_q.io.enq.bits.from_conv_fsm, io.in.bits.from_conv_fsm
connect cmd_q.io.enq.bits.from_matmul_fsm, io.in.bits.from_matmul_fsm
connect cmd_q.io.enq.bits.rob_id.bits, io.in.bits.rob_id.bits
connect cmd_q.io.enq.bits.rob_id.valid, io.in.bits.rob_id.valid
connect cmd_q.io.enq.bits.cmd.status.uie, io.in.bits.cmd.status.uie
connect cmd_q.io.enq.bits.cmd.status.sie, io.in.bits.cmd.status.sie
connect cmd_q.io.enq.bits.cmd.status.hie, io.in.bits.cmd.status.hie
connect cmd_q.io.enq.bits.cmd.status.mie, io.in.bits.cmd.status.mie
connect cmd_q.io.enq.bits.cmd.status.upie, io.in.bits.cmd.status.upie
connect cmd_q.io.enq.bits.cmd.status.spie, io.in.bits.cmd.status.spie
connect cmd_q.io.enq.bits.cmd.status.ube, io.in.bits.cmd.status.ube
connect cmd_q.io.enq.bits.cmd.status.mpie, io.in.bits.cmd.status.mpie
connect cmd_q.io.enq.bits.cmd.status.spp, io.in.bits.cmd.status.spp
connect cmd_q.io.enq.bits.cmd.status.vs, io.in.bits.cmd.status.vs
connect cmd_q.io.enq.bits.cmd.status.mpp, io.in.bits.cmd.status.mpp
connect cmd_q.io.enq.bits.cmd.status.fs, io.in.bits.cmd.status.fs
connect cmd_q.io.enq.bits.cmd.status.xs, io.in.bits.cmd.status.xs
connect cmd_q.io.enq.bits.cmd.status.mprv, io.in.bits.cmd.status.mprv
connect cmd_q.io.enq.bits.cmd.status.sum, io.in.bits.cmd.status.sum
connect cmd_q.io.enq.bits.cmd.status.mxr, io.in.bits.cmd.status.mxr
connect cmd_q.io.enq.bits.cmd.status.tvm, io.in.bits.cmd.status.tvm
connect cmd_q.io.enq.bits.cmd.status.tw, io.in.bits.cmd.status.tw
connect cmd_q.io.enq.bits.cmd.status.tsr, io.in.bits.cmd.status.tsr
connect cmd_q.io.enq.bits.cmd.status.zero1, io.in.bits.cmd.status.zero1
connect cmd_q.io.enq.bits.cmd.status.sd_rv32, io.in.bits.cmd.status.sd_rv32
connect cmd_q.io.enq.bits.cmd.status.uxl, io.in.bits.cmd.status.uxl
connect cmd_q.io.enq.bits.cmd.status.sxl, io.in.bits.cmd.status.sxl
connect cmd_q.io.enq.bits.cmd.status.sbe, io.in.bits.cmd.status.sbe
connect cmd_q.io.enq.bits.cmd.status.mbe, io.in.bits.cmd.status.mbe
connect cmd_q.io.enq.bits.cmd.status.gva, io.in.bits.cmd.status.gva
connect cmd_q.io.enq.bits.cmd.status.mpv, io.in.bits.cmd.status.mpv
connect cmd_q.io.enq.bits.cmd.status.zero2, io.in.bits.cmd.status.zero2
connect cmd_q.io.enq.bits.cmd.status.sd, io.in.bits.cmd.status.sd
connect cmd_q.io.enq.bits.cmd.status.v, io.in.bits.cmd.status.v
connect cmd_q.io.enq.bits.cmd.status.prv, io.in.bits.cmd.status.prv
connect cmd_q.io.enq.bits.cmd.status.dv, io.in.bits.cmd.status.dv
connect cmd_q.io.enq.bits.cmd.status.dprv, io.in.bits.cmd.status.dprv
connect cmd_q.io.enq.bits.cmd.status.isa, io.in.bits.cmd.status.isa
connect cmd_q.io.enq.bits.cmd.status.wfi, io.in.bits.cmd.status.wfi
connect cmd_q.io.enq.bits.cmd.status.cease, io.in.bits.cmd.status.cease
connect cmd_q.io.enq.bits.cmd.status.debug, io.in.bits.cmd.status.debug
connect cmd_q.io.enq.bits.cmd.rs2, io.in.bits.cmd.rs2
connect cmd_q.io.enq.bits.cmd.rs1, io.in.bits.cmd.rs1
connect cmd_q.io.enq.bits.cmd.inst.opcode, io.in.bits.cmd.inst.opcode
connect cmd_q.io.enq.bits.cmd.inst.rd, io.in.bits.cmd.inst.rd
connect cmd_q.io.enq.bits.cmd.inst.xs2, io.in.bits.cmd.inst.xs2
connect cmd_q.io.enq.bits.cmd.inst.xs1, io.in.bits.cmd.inst.xs1
connect cmd_q.io.enq.bits.cmd.inst.xd, io.in.bits.cmd.inst.xd
connect cmd_q.io.enq.bits.cmd.inst.rs1, io.in.bits.cmd.inst.rs1
connect cmd_q.io.enq.bits.cmd.inst.rs2, io.in.bits.cmd.inst.rs2
connect cmd_q.io.enq.bits.cmd.inst.funct, io.in.bits.cmd.inst.funct
connect io.in.ready, cmd_q.io.enq.ready
node _io_busy_T = or(cmd_q.io.deq.valid, loop_configured)
connect io.busy, _io_busy_T
inst ldab_arb of WeightedArbiter
connect ldab_arb.clock, clock
connect ldab_arb.reset, reset
connect ldab_arb.io.inA, ldA.io.cmd
connect ldab_arb.io.inB, ldB.io.cmd
node ab_loads_on_same_loop = eq(ldA.io.loop_id, ldB.io.loop_id)
node _forceA_T = eq(ab_loads_on_same_loop, UInt<1>(0h0))
node _forceA_T_1 = eq(ldA.io.loop_id, head_loop_id)
node forceA = and(_forceA_T, _forceA_T_1)
node _forceB_T = eq(ab_loads_on_same_loop, UInt<1>(0h0))
node _forceB_T_1 = eq(ldB.io.loop_id, head_loop_id)
node forceB = and(_forceB_T, _forceB_T_1)
node _ldab_arb_io_forceA_T = eq(ldA.io.idle, UInt<1>(0h0))
node _ldab_arb_io_forceA_T_1 = and(ab_loads_on_same_loop, _ldab_arb_io_forceA_T)
node _ldab_arb_io_forceA_T_2 = mux(is_resadd, _ldab_arb_io_forceA_T_1, forceA)
connect ldab_arb.io.forceA, _ldab_arb_io_forceA_T_2
node _ldab_arb_io_forceB_T = or(forceB, ldA.io.idle)
node _ldab_arb_io_forceB_T_1 = mux(is_resadd, _ldab_arb_io_forceB_T, forceB)
connect ldab_arb.io.forceB, _ldab_arb_io_forceB_T_1
connect ldab_arb.io.weightA, UInt<1>(0h0)
connect ldab_arb.io.inA_idle, ldA.io.idle
connect ldab_arb.io.inB_idle, ldB.io.idle
connect ldab_arb.io.inA_k, ldA.io.k
connect ldab_arb.io.inA_i, ldA.io.i
connect ldab_arb.io.inB_k, ldB.io.k
connect ldab_arb.io.inB_j, ldB.io.j
inst arb of Arbiter4_RoCCCommand
connect arb.clock, clock
connect arb.reset, reset
connect arb.io.in[0], stC.io.cmd
connect arb.io.in[1], ex.io.cmd
connect arb.io.in[2], ldD.io.cmd
connect arb.io.in[3], ldab_arb.io.out
regreset ld_utilization : UInt<4>, clock, reset, UInt<4>(0h0)
regreset st_utilization : UInt<3>, clock, reset, UInt<3>(0h0)
regreset ex_utilization : UInt<5>, clock, reset, UInt<5>(0h0)
node _ld_utilization_T = and(ldA.io.cmd.ready, ldA.io.cmd.valid)
node _ld_utilization_T_1 = and(ldB.io.cmd.ready, ldB.io.cmd.valid)
node _ld_utilization_T_2 = or(_ld_utilization_T, _ld_utilization_T_1)
node _ld_utilization_T_3 = and(ldD.io.cmd.ready, ldD.io.cmd.valid)
node _ld_utilization_T_4 = or(_ld_utilization_T_2, _ld_utilization_T_3)
node _ld_utilization_T_5 = add(ld_utilization, _ld_utilization_T_4)
node _ld_utilization_T_6 = sub(_ld_utilization_T_5, io.ld_completed)
node _ld_utilization_T_7 = asUInt(_ld_utilization_T_6)
connect ld_utilization, _ld_utilization_T_7
node _st_utilization_T = and(stC.io.cmd.ready, stC.io.cmd.valid)
node _st_utilization_T_1 = add(st_utilization, _st_utilization_T)
node _st_utilization_T_2 = sub(_st_utilization_T_1, io.st_completed)
node _st_utilization_T_3 = asUInt(_st_utilization_T_2)
connect st_utilization, _st_utilization_T_3
node _ex_utilization_T = and(ex.io.cmd.ready, ex.io.cmd.valid)
node _ex_utilization_T_1 = add(ex_utilization, _ex_utilization_T)
node _ex_utilization_T_2 = sub(_ex_utilization_T_1, io.ex_completed)
node _ex_utilization_T_3 = asUInt(_ex_utilization_T_2)
connect ex_utilization, _ex_utilization_T_3
node _T = geq(ld_utilization, io.ld_completed)
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: ld utilization underflow\n at LoopMatmul.scala:846 assert(ld_utilization >= io.ld_completed, \"ld utilization underflow\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _T_4 = geq(st_utilization, io.st_completed)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: st utilization underflow\n at LoopMatmul.scala:847 assert(st_utilization >= io.st_completed, \"st utilization underflow\")\n") : printf_1
assert(clock, _T_4, UInt<1>(0h1), "") : assert_1
node _T_8 = geq(ex_utilization, io.ex_completed)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed: ex utilization underflow\n at LoopMatmul.scala:848 assert(ex_utilization >= io.ex_completed, \"ex utilization underflow\")\n") : printf_2
assert(clock, _T_8, UInt<1>(0h1), "") : assert_2
node is_loop_run_cmd = eq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<4>(0h8))
node _is_loop_config_cmd_T = geq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<4>(0h9))
node _is_loop_config_cmd_T_1 = leq(cmd_q.io.deq.bits.cmd.inst.funct, UInt<4>(0hd))
node is_loop_config_cmd = and(_is_loop_config_cmd_T, _is_loop_config_cmd_T_1)
node is_loop_cmd = or(is_loop_run_cmd, is_loop_config_cmd)
node _io_out_bits_cmd_T = mux(loop_configured, arb.io.out.bits, cmd_q.io.deq.bits.cmd)
connect io.out.bits.cmd, _io_out_bits_cmd_T
connect io.out.bits.cmd.status, cmd_q.io.deq.bits.cmd.status
invalidate io.out.bits.rob_id.bits
invalidate io.out.bits.rob_id.valid
node _io_out_bits_from_matmul_fsm_T = mux(loop_configured, UInt<1>(0h1), cmd_q.io.deq.bits.from_matmul_fsm)
connect io.out.bits.from_matmul_fsm, _io_out_bits_from_matmul_fsm_T
node _io_out_bits_from_conv_fsm_T = mux(loop_configured, UInt<1>(0h0), cmd_q.io.deq.bits.from_conv_fsm)
connect io.out.bits.from_conv_fsm, _io_out_bits_from_conv_fsm_T
node _io_out_valid_T = eq(is_loop_config_cmd, UInt<1>(0h0))
node _io_out_valid_T_1 = and(cmd_q.io.deq.valid, _io_out_valid_T)
node _io_out_valid_T_2 = eq(is_loop_run_cmd, UInt<1>(0h0))
node _io_out_valid_T_3 = and(_io_out_valid_T_1, _io_out_valid_T_2)
node _io_out_valid_T_4 = mux(loop_configured, arb.io.out.valid, _io_out_valid_T_3)
connect io.out.valid, _io_out_valid_T_4
node _q_io_deq_ready_T = eq(loops[loop_being_configured_id].configured, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = eq(loop_configured, UInt<1>(0h0))
node _q_io_deq_ready_T_2 = and(_q_io_deq_ready_T_1, io.out.ready)
node _q_io_deq_ready_T_3 = mux(is_loop_cmd, _q_io_deq_ready_T, _q_io_deq_ready_T_2)
connect cmd_q.io.deq.ready, _q_io_deq_ready_T_3
connect arb.io.out.ready, io.out.ready
node _ldA_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ldA.io.rob_overloaded, _ldA_io_rob_overloaded_T
node _ldB_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ldB.io.rob_overloaded, _ldB_io_rob_overloaded_T
node _ex_io_rob_overloaded_T = geq(ex_utilization, UInt<5>(0h10))
connect ex.io.rob_overloaded, _ex_io_rob_overloaded_T
node _ldD_io_rob_overloaded_T = geq(ld_utilization, UInt<4>(0h8))
connect ldD.io.rob_overloaded, _ldD_io_rob_overloaded_T
node _stC_io_rob_overloaded_T = geq(st_utilization, UInt<3>(0h4))
connect stC.io.rob_overloaded, _stC_io_rob_overloaded_T
node _ex_io_lda_completed_T = neq(ldA.io.loop_id, ex.io.loop_id)
node _ex_io_lda_completed_T_1 = or(_ex_io_lda_completed_T, ldA.io.idle)
connect ex.io.lda_completed, _ex_io_lda_completed_T_1
node _ex_io_ldb_completed_T = neq(ldB.io.loop_id, ex.io.loop_id)
node _ex_io_ldb_completed_T_1 = or(_ex_io_ldb_completed_T, ldB.io.idle)
connect ex.io.ldb_completed, _ex_io_ldb_completed_T_1
node _ex_io_ldd_completed_T = neq(ldD.io.loop_id, ex.io.loop_id)
node _ex_io_ldd_completed_T_1 = or(_ex_io_ldd_completed_T, ldD.io.idle)
connect ex.io.ldd_completed, _ex_io_ldd_completed_T_1
connect ex.io.ld_ka, ldA.io.k
connect ex.io.ld_kb, ldB.io.k
connect ex.io.ld_j, ldB.io.j
connect ex.io.ld_i, ldA.io.i
node _stC_io_ex_completed_T = neq(ex.io.loop_id, stC.io.loop_id)
node _stC_io_ex_completed_T_1 = or(_stC_io_ex_completed_T, ex.io.idle)
connect stC.io.ex_completed, _stC_io_ex_completed_T_1
connect stC.io.ex_k, ex.io.k
connect stC.io.ex_j, ex.io.j
connect stC.io.ex_i, ex.io.i
when is_resadd :
node _stC_io_ex_completed_T_2 = neq(ldA.io.loop_id, stC.io.loop_id)
node _stC_io_ex_completed_T_3 = or(_stC_io_ex_completed_T_2, ldA.io.idle)
node _stC_io_ex_completed_T_4 = neq(ldB.io.loop_id, stC.io.loop_id)
node _stC_io_ex_completed_T_5 = or(_stC_io_ex_completed_T_4, ldB.io.idle)
node _stC_io_ex_completed_T_6 = and(_stC_io_ex_completed_T_3, _stC_io_ex_completed_T_5)
connect stC.io.ex_completed, _stC_io_ex_completed_T_6
connect stC.io.ex_k, UInt<1>(0h0)
connect stC.io.ex_j, ldB.io.j
connect stC.io.ex_i, ldB.io.k
regreset loops_configured : UInt<16>, clock, reset, UInt<16>(0h0)
node _T_12 = and(cmd_q.io.deq.valid, is_loop_cmd)
node _T_13 = eq(loops[loop_being_configured_id].configured, UInt<1>(0h0))
node _T_14 = and(_T_12, _T_13)
when _T_14 :
node _T_15 = eq(UInt<4>(0h9), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_15 :
node _loops_max_k_T = bits(cmd_q.io.deq.bits.cmd.rs2, 47, 32)
connect loops[loop_being_configured_id].max_k, _loops_max_k_T
node _loops_max_j_T = bits(cmd_q.io.deq.bits.cmd.rs2, 31, 16)
connect loops[loop_being_configured_id].max_j, _loops_max_j_T
node _loops_max_i_T = bits(cmd_q.io.deq.bits.cmd.rs2, 15, 0)
connect loops[loop_being_configured_id].max_i, _loops_max_i_T
node _loops_pad_k_T = bits(cmd_q.io.deq.bits.cmd.rs1, 47, 32)
connect loops[loop_being_configured_id].pad_k, _loops_pad_k_T
node _loops_pad_j_T = bits(cmd_q.io.deq.bits.cmd.rs1, 31, 16)
connect loops[loop_being_configured_id].pad_j, _loops_pad_j_T
node _loops_pad_i_T = bits(cmd_q.io.deq.bits.cmd.rs1, 15, 0)
connect loops[loop_being_configured_id].pad_i, _loops_pad_i_T
else :
node _T_16 = eq(UInt<4>(0ha), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_16 :
connect loops[loop_being_configured_id].a_dram_addr, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].b_dram_addr, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_17 = eq(UInt<4>(0hb), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_17 :
connect loops[loop_being_configured_id].d_dram_addr, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].c_dram_addr, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_18 = eq(UInt<4>(0hc), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_18 :
connect loops[loop_being_configured_id].a_dram_stride, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].b_dram_stride, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_19 = eq(UInt<4>(0hd), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_19 :
connect loops[loop_being_configured_id].d_dram_stride, cmd_q.io.deq.bits.cmd.rs1
connect loops[loop_being_configured_id].c_dram_stride, cmd_q.io.deq.bits.cmd.rs2
else :
node _T_20 = eq(UInt<4>(0h8), cmd_q.io.deq.bits.cmd.inst.funct)
when _T_20 :
node _loops_ex_accumulate_T = bits(cmd_q.io.deq.bits.cmd.rs1, 0, 0)
connect loops[loop_being_configured_id].ex_accumulate, _loops_ex_accumulate_T
node _loops_full_c_T = bits(cmd_q.io.deq.bits.cmd.rs1, 1, 1)
connect loops[loop_being_configured_id].full_c, _loops_full_c_T
node _loops_low_d_T = bits(cmd_q.io.deq.bits.cmd.rs1, 2, 2)
connect loops[loop_being_configured_id].low_d, _loops_low_d_T
node _loops_act_T = bits(cmd_q.io.deq.bits.cmd.rs1, 10, 8)
connect loops[loop_being_configured_id].act, _loops_act_T
node _loops_a_ex_spad_id_T = bits(cmd_q.io.deq.bits.cmd.rs1, 19, 18)
connect loops[loop_being_configured_id].a_ex_spad_id, _loops_a_ex_spad_id_T
node _loops_b_ex_spad_id_T = bits(cmd_q.io.deq.bits.cmd.rs1, 17, 16)
connect loops[loop_being_configured_id].b_ex_spad_id, _loops_b_ex_spad_id_T
node _loops_a_transpose_T = bits(cmd_q.io.deq.bits.cmd.rs2, 0, 0)
connect loops[loop_being_configured_id].a_transpose, _loops_a_transpose_T
node _loops_b_transpose_T = bits(cmd_q.io.deq.bits.cmd.rs2, 1, 1)
connect loops[loop_being_configured_id].b_transpose, _loops_b_transpose_T
node _is_resadd_T = bits(cmd_q.io.deq.bits.cmd.rs2, 2, 2)
connect is_resadd, _is_resadd_T
connect loops[loop_being_configured_id].configured, UInt<1>(0h1)
node _loops_configured_T = add(loops_configured, UInt<1>(0h1))
node _loops_configured_T_1 = tail(_loops_configured_T, 1)
connect loops_configured, _loops_configured_T_1
regreset ld_d_addr_start : UInt<10>, clock, reset, UInt<10>(0h0)
regreset ex_c_addr_start : UInt<10>, clock, reset, UInt<10>(0h0)
regreset st_c_addr_start : UInt<10>, clock, reset, UInt<10>(0h0)
node loop_requesting_ldA_id = mux(loops[head_loop_id].lda_started, tail_loop_id, head_loop_id)
node _ldA_io_req_bits_max_k_T = mux(is_resadd, loops[loop_requesting_ldA_id].max_j, loops[loop_requesting_ldA_id].max_k)
connect ldA.io.req.bits.max_k, _ldA_io_req_bits_max_k_T
connect ldA.io.req.bits.max_i, loops[loop_requesting_ldA_id].max_i
node _ldA_io_req_bits_pad_k_T = mux(is_resadd, loops[loop_requesting_ldA_id].pad_j, loops[loop_requesting_ldA_id].pad_k)
connect ldA.io.req.bits.pad_k, _ldA_io_req_bits_pad_k_T
connect ldA.io.req.bits.pad_i, loops[loop_requesting_ldA_id].pad_i
connect ldA.io.req.bits.dram_addr, loops[loop_requesting_ldA_id].a_dram_addr
connect ldA.io.req.bits.dram_stride, loops[loop_requesting_ldA_id].a_dram_stride
connect ldA.io.req.bits.transpose, loops[loop_requesting_ldA_id].a_transpose
node _ldA_io_req_bits_addr_start_T = eq(loops[loop_requesting_ldA_id].a_ex_spad_id, UInt<1>(0h0))
node _ldA_io_req_bits_addr_start_T_1 = sub(loops[loop_requesting_ldA_id].a_ex_spad_id, UInt<1>(0h1))
node _ldA_io_req_bits_addr_start_T_2 = tail(_ldA_io_req_bits_addr_start_T_1, 1)
node _ldA_io_req_bits_addr_start_T_3 = mul(_ldA_io_req_bits_addr_start_T_2, UInt<14>(0h2000))
node _ldA_io_req_bits_addr_start_T_4 = mux(_ldA_io_req_bits_addr_start_T, loops[loop_requesting_ldA_id].a_addr_start, _ldA_io_req_bits_addr_start_T_3)
connect ldA.io.req.bits.addr_start, _ldA_io_req_bits_addr_start_T_4
connect ldA.io.req.bits.loop_id, loop_requesting_ldA_id
connect ldA.io.req.bits.is_resadd, is_resadd
node _ldA_io_req_valid_T = eq(loops[loop_requesting_ldA_id].lda_started, UInt<1>(0h0))
node _ldA_io_req_valid_T_1 = and(_ldA_io_req_valid_T, loops[loop_requesting_ldA_id].configured)
connect ldA.io.req.valid, _ldA_io_req_valid_T_1
node _T_21 = and(ldA.io.req.ready, ldA.io.req.valid)
when _T_21 :
connect loops[loop_requesting_ldA_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ldA_id].lda_started, UInt<1>(0h1)
node loop_requesting_ldB_id = mux(loops[head_loop_id].ldb_started, tail_loop_id, head_loop_id)
connect ldB.io.req.bits.max_j, loops[loop_requesting_ldB_id].max_j
node _ldB_io_req_bits_max_k_T = mux(is_resadd, loops[loop_requesting_ldB_id].max_i, loops[loop_requesting_ldB_id].max_k)
connect ldB.io.req.bits.max_k, _ldB_io_req_bits_max_k_T
connect ldB.io.req.bits.pad_j, loops[loop_requesting_ldB_id].pad_j
node _ldB_io_req_bits_pad_k_T = mux(is_resadd, loops[loop_requesting_ldB_id].pad_i, loops[loop_requesting_ldB_id].pad_k)
connect ldB.io.req.bits.pad_k, _ldB_io_req_bits_pad_k_T
connect ldB.io.req.bits.dram_addr, loops[loop_requesting_ldB_id].b_dram_addr
connect ldB.io.req.bits.dram_stride, loops[loop_requesting_ldB_id].b_dram_stride
connect ldB.io.req.bits.transpose, loops[loop_requesting_ldB_id].b_transpose
node _ldB_io_req_bits_addr_end_T = eq(loops[loop_requesting_ldB_id].b_ex_spad_id, UInt<1>(0h0))
node _ldB_io_req_bits_addr_end_T_1 = mul(loops[loop_requesting_ldB_id].b_ex_spad_id, UInt<14>(0h2000))
node _ldB_io_req_bits_addr_end_T_2 = mux(_ldB_io_req_bits_addr_end_T, loops[loop_requesting_ldB_id].b_addr_end, _ldB_io_req_bits_addr_end_T_1)
connect ldB.io.req.bits.addr_end, _ldB_io_req_bits_addr_end_T_2
connect ldB.io.req.bits.loop_id, loop_requesting_ldB_id
connect ldB.io.req.bits.is_resadd, is_resadd
node _ldB_io_req_valid_T = eq(loops[loop_requesting_ldB_id].ldb_started, UInt<1>(0h0))
node _ldB_io_req_valid_T_1 = and(_ldB_io_req_valid_T, loops[loop_requesting_ldB_id].configured)
connect ldB.io.req.valid, _ldB_io_req_valid_T_1
node _T_22 = and(ldB.io.req.ready, ldB.io.req.valid)
when _T_22 :
connect loops[loop_requesting_ldB_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ldB_id].ldb_started, UInt<1>(0h1)
node loop_requesting_ex_id = mux(loops[head_loop_id].ex_started, tail_loop_id, head_loop_id)
connect ex.io.req.bits.max_j, loops[loop_requesting_ex_id].max_j
connect ex.io.req.bits.max_k, loops[loop_requesting_ex_id].max_k
connect ex.io.req.bits.max_i, loops[loop_requesting_ex_id].max_i
connect ex.io.req.bits.pad_j, loops[loop_requesting_ex_id].pad_j
connect ex.io.req.bits.pad_k, loops[loop_requesting_ex_id].pad_k
connect ex.io.req.bits.pad_i, loops[loop_requesting_ex_id].pad_i
connect ex.io.req.bits.accumulate, loops[loop_requesting_ex_id].ex_accumulate
node _ex_io_req_bits_a_addr_start_T = eq(loops[loop_requesting_ex_id].a_ex_spad_id, UInt<1>(0h0))
node _ex_io_req_bits_a_addr_start_T_1 = sub(loops[loop_requesting_ex_id].a_ex_spad_id, UInt<1>(0h1))
node _ex_io_req_bits_a_addr_start_T_2 = tail(_ex_io_req_bits_a_addr_start_T_1, 1)
node _ex_io_req_bits_a_addr_start_T_3 = mul(_ex_io_req_bits_a_addr_start_T_2, UInt<14>(0h2000))
node _ex_io_req_bits_a_addr_start_T_4 = mux(_ex_io_req_bits_a_addr_start_T, loops[loop_requesting_ex_id].a_addr_start, _ex_io_req_bits_a_addr_start_T_3)
connect ex.io.req.bits.a_addr_start, _ex_io_req_bits_a_addr_start_T_4
node _ex_io_req_bits_b_addr_end_T = eq(loops[loop_requesting_ex_id].b_ex_spad_id, UInt<1>(0h0))
node _ex_io_req_bits_b_addr_end_T_1 = mul(loops[loop_requesting_ex_id].b_ex_spad_id, UInt<14>(0h2000))
node _ex_io_req_bits_b_addr_end_T_2 = mux(_ex_io_req_bits_b_addr_end_T, loops[loop_requesting_ex_id].b_addr_end, _ex_io_req_bits_b_addr_end_T_1)
connect ex.io.req.bits.b_addr_end, _ex_io_req_bits_b_addr_end_T_2
connect ex.io.req.bits.a_tranpose, loops[loop_requesting_ex_id].a_transpose
connect ex.io.req.bits.b_tranpose, loops[loop_requesting_ex_id].b_transpose
connect ex.io.req.bits.c_addr_start, ex_c_addr_start
connect ex.io.req.bits.loop_id, loop_requesting_ex_id
connect ex.io.req.bits.skip, is_resadd
node _ex_io_req_valid_T = eq(loops[loop_requesting_ex_id].ex_started, UInt<1>(0h0))
node _ex_io_req_valid_T_1 = and(_ex_io_req_valid_T, loops[loop_requesting_ex_id].lda_started)
node _ex_io_req_valid_T_2 = and(_ex_io_req_valid_T_1, loops[loop_requesting_ex_id].ldb_started)
node _ex_io_req_valid_T_3 = and(_ex_io_req_valid_T_2, loops[loop_requesting_ex_id].ldd_started)
node _ex_io_req_valid_T_4 = and(_ex_io_req_valid_T_3, loops[loop_requesting_ex_id].configured)
connect ex.io.req.valid, _ex_io_req_valid_T_4
node _T_23 = and(ex.io.req.ready, ex.io.req.valid)
when _T_23 :
connect loops[loop_requesting_ex_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ex_id].ex_started, UInt<1>(0h1)
node _T_24 = neq(loops[loop_requesting_ex_id].c_dram_addr, UInt<1>(0h0))
when _T_24 :
node _ex_c_addr_start_max_T = sub(UInt<11>(0h400), UInt<1>(0h1))
node ex_c_addr_start_max = tail(_ex_c_addr_start_max_T, 1)
node _ex_c_addr_start_T = add(ex_c_addr_start, UInt<10>(0h200))
node _ex_c_addr_start_T_1 = tail(_ex_c_addr_start_T, 1)
node _ex_c_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _ex_c_addr_start_T_3 = add(ex_c_addr_start, UInt<10>(0h200))
node _ex_c_addr_start_T_4 = gt(_ex_c_addr_start_T_3, ex_c_addr_start_max)
node _ex_c_addr_start_T_5 = mux(_ex_c_addr_start_T_4, UInt<1>(0h0), _ex_c_addr_start_T_1)
node _ex_c_addr_start_T_6 = mux(_ex_c_addr_start_T_2, ex_c_addr_start, _ex_c_addr_start_T_5)
connect ex_c_addr_start, _ex_c_addr_start_T_6
node loop_requesting_ldD_id = mux(loops[head_loop_id].ldd_started, tail_loop_id, head_loop_id)
connect ldD.io.req.bits.max_j, loops[loop_requesting_ldD_id].max_j
connect ldD.io.req.bits.max_i, loops[loop_requesting_ldD_id].max_i
connect ldD.io.req.bits.pad_j, loops[loop_requesting_ldD_id].pad_j
connect ldD.io.req.bits.pad_i, loops[loop_requesting_ldD_id].pad_i
connect ldD.io.req.bits.dram_addr, loops[loop_requesting_ldD_id].d_dram_addr
connect ldD.io.req.bits.dram_stride, loops[loop_requesting_ldD_id].d_dram_stride
connect ldD.io.req.bits.low_d, loops[loop_requesting_ldD_id].low_d
connect ldD.io.req.bits.addr_start, ld_d_addr_start
connect ldD.io.req.bits.loop_id, loop_requesting_ldD_id
node _ldD_io_req_valid_T = eq(loops[loop_requesting_ldD_id].ldd_started, UInt<1>(0h0))
node _ldD_io_req_valid_T_1 = and(_ldD_io_req_valid_T, loops[loop_requesting_ldD_id].configured)
connect ldD.io.req.valid, _ldD_io_req_valid_T_1
node _T_25 = and(ldD.io.req.ready, ldD.io.req.valid)
when _T_25 :
connect loops[loop_requesting_ldD_id].running, UInt<1>(0h1)
connect loops[loop_requesting_ldD_id].ldd_started, UInt<1>(0h1)
node _T_26 = neq(loops[loop_requesting_ldD_id].c_dram_addr, UInt<1>(0h0))
when _T_26 :
node _ld_d_addr_start_max_T = sub(UInt<11>(0h400), UInt<1>(0h1))
node ld_d_addr_start_max = tail(_ld_d_addr_start_max_T, 1)
node _ld_d_addr_start_T = add(ld_d_addr_start, UInt<10>(0h200))
node _ld_d_addr_start_T_1 = tail(_ld_d_addr_start_T, 1)
node _ld_d_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _ld_d_addr_start_T_3 = add(ld_d_addr_start, UInt<10>(0h200))
node _ld_d_addr_start_T_4 = gt(_ld_d_addr_start_T_3, ld_d_addr_start_max)
node _ld_d_addr_start_T_5 = mux(_ld_d_addr_start_T_4, UInt<1>(0h0), _ld_d_addr_start_T_1)
node _ld_d_addr_start_T_6 = mux(_ld_d_addr_start_T_2, ld_d_addr_start, _ld_d_addr_start_T_5)
connect ld_d_addr_start, _ld_d_addr_start_T_6
node loop_requesting_st_id = mux(loops[head_loop_id].st_started, tail_loop_id, head_loop_id)
node _stC_io_req_bits_max_k_T = mux(is_resadd, UInt<1>(0h1), loops[loop_requesting_st_id].max_k)
connect stC.io.req.bits.max_k, _stC_io_req_bits_max_k_T
connect stC.io.req.bits.max_j, loops[loop_requesting_st_id].max_j
connect stC.io.req.bits.max_i, loops[loop_requesting_st_id].max_i
connect stC.io.req.bits.pad_j, loops[loop_requesting_st_id].pad_j
connect stC.io.req.bits.pad_i, loops[loop_requesting_st_id].pad_i
connect stC.io.req.bits.dram_addr, loops[loop_requesting_st_id].c_dram_addr
connect stC.io.req.bits.dram_stride, loops[loop_requesting_st_id].c_dram_stride
connect stC.io.req.bits.full_c, loops[loop_requesting_st_id].full_c
connect stC.io.req.bits.act, loops[loop_requesting_st_id].act
connect stC.io.req.bits.addr_start, st_c_addr_start
connect stC.io.req.bits.loop_id, loop_requesting_st_id
connect stC.io.req.bits.is_resadd, is_resadd
node _stC_io_req_valid_T = eq(loops[loop_requesting_st_id].st_started, UInt<1>(0h0))
node _stC_io_req_valid_T_1 = and(_stC_io_req_valid_T, loops[loop_requesting_st_id].ex_started)
node _stC_io_req_valid_T_2 = and(_stC_io_req_valid_T_1, loops[loop_requesting_st_id].configured)
connect stC.io.req.valid, _stC_io_req_valid_T_2
node _T_27 = and(stC.io.req.ready, stC.io.req.valid)
when _T_27 :
connect loops[loop_requesting_st_id].running, UInt<1>(0h1)
connect loops[loop_requesting_st_id].st_started, UInt<1>(0h1)
node _T_28 = neq(loops[loop_requesting_st_id].c_dram_addr, UInt<1>(0h0))
when _T_28 :
node _st_c_addr_start_max_T = sub(UInt<11>(0h400), UInt<1>(0h1))
node st_c_addr_start_max = tail(_st_c_addr_start_max_T, 1)
node _st_c_addr_start_T = add(st_c_addr_start, UInt<10>(0h200))
node _st_c_addr_start_T_1 = tail(_st_c_addr_start_T, 1)
node _st_c_addr_start_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _st_c_addr_start_T_3 = add(st_c_addr_start, UInt<10>(0h200))
node _st_c_addr_start_T_4 = gt(_st_c_addr_start_T_3, st_c_addr_start_max)
node _st_c_addr_start_T_5 = mux(_st_c_addr_start_T_4, UInt<1>(0h0), _st_c_addr_start_T_1)
node _st_c_addr_start_T_6 = mux(_st_c_addr_start_T_2, st_c_addr_start, _st_c_addr_start_T_5)
connect st_c_addr_start, _st_c_addr_start_T_6
when is_resadd :
connect ldA.io.req.bits.addr_start, loops[loop_requesting_ldA_id].resadd_addr_start
connect ldB.io.req.bits.addr_end, loops[loop_requesting_ldB_id].resadd_addr_start
connect stC.io.req.bits.addr_start, loops[loop_requesting_st_id].resadd_addr_start
node _stC_io_req_valid_T_3 = eq(loops[loop_requesting_st_id].st_started, UInt<1>(0h0))
node _stC_io_req_valid_T_4 = and(_stC_io_req_valid_T_3, loops[loop_requesting_st_id].configured)
connect stC.io.req.valid, _stC_io_req_valid_T_4
node _T_29 = and(ldA.io.idle, loops[ldA.io.loop_id].running)
node _T_30 = and(_T_29, loops[ldA.io.loop_id].lda_started)
when _T_30 :
connect loops[ldA.io.loop_id].lda_completed, UInt<1>(0h1)
node _T_31 = and(ldB.io.idle, loops[ldB.io.loop_id].running)
node _T_32 = and(_T_31, loops[ldB.io.loop_id].ldb_started)
when _T_32 :
connect loops[ldB.io.loop_id].ldb_completed, UInt<1>(0h1)
node _T_33 = and(ex.io.idle, loops[ex.io.loop_id].running)
node _T_34 = and(_T_33, loops[ex.io.loop_id].ex_started)
when _T_34 :
connect loops[ex.io.loop_id].ex_completed, UInt<1>(0h1)
node _T_35 = and(ldD.io.idle, loops[ldD.io.loop_id].running)
node _T_36 = and(_T_35, loops[ldD.io.loop_id].ldd_started)
when _T_36 :
connect loops[ldD.io.loop_id].ldd_completed, UInt<1>(0h1)
node _T_37 = and(stC.io.idle, loops[stC.io.loop_id].running)
node _T_38 = and(_T_37, loops[stC.io.loop_id].st_started)
when _T_38 :
connect loops[stC.io.loop_id].st_completed, UInt<1>(0h1)
node _T_39 = and(loops[head_loop_id].lda_completed, loops[head_loop_id].ldb_completed)
node _T_40 = and(_T_39, loops[head_loop_id].ldd_completed)
node _T_41 = and(_T_40, loops[head_loop_id].ex_completed)
node _T_42 = and(_T_41, loops[head_loop_id].st_completed)
node _T_43 = and(loops[head_loop_id].running, _T_42)
when _T_43 :
connect loops[head_loop_id].configured, UInt<1>(0h0)
connect loops[head_loop_id].running, UInt<1>(0h0)
connect loops[head_loop_id].lda_started, UInt<1>(0h0)
connect loops[head_loop_id].ldb_started, UInt<1>(0h0)
connect loops[head_loop_id].ex_started, UInt<1>(0h0)
connect loops[head_loop_id].ldd_started, UInt<1>(0h0)
connect loops[head_loop_id].st_started, UInt<1>(0h0)
connect loops[head_loop_id].lda_completed, UInt<1>(0h0)
connect loops[head_loop_id].ldb_completed, UInt<1>(0h0)
connect loops[head_loop_id].ex_completed, UInt<1>(0h0)
connect loops[head_loop_id].ldd_completed, UInt<1>(0h0)
connect loops[head_loop_id].st_completed, UInt<1>(0h0)
node _head_loop_id_T = not(head_loop_id)
connect head_loop_id, _head_loop_id_T
node _T_44 = asUInt(reset)
when _T_44 :
connect loops[0].configured, UInt<1>(0h0)
connect loops[0].running, UInt<1>(0h0)
connect loops[0].lda_started, UInt<1>(0h0)
connect loops[0].ldb_started, UInt<1>(0h0)
connect loops[0].ex_started, UInt<1>(0h0)
connect loops[0].ldd_started, UInt<1>(0h0)
connect loops[0].st_started, UInt<1>(0h0)
connect loops[0].lda_completed, UInt<1>(0h0)
connect loops[0].ldb_completed, UInt<1>(0h0)
connect loops[0].ex_completed, UInt<1>(0h0)
connect loops[0].ldd_completed, UInt<1>(0h0)
connect loops[0].st_completed, UInt<1>(0h0)
connect loops[0].a_addr_start, UInt<1>(0h0)
connect loops[0].b_addr_end, UInt<14>(0h2000)
connect loops[0].resadd_addr_start, UInt<1>(0h0)
connect loops[1].configured, UInt<1>(0h0)
connect loops[1].running, UInt<1>(0h0)
connect loops[1].lda_started, UInt<1>(0h0)
connect loops[1].ldb_started, UInt<1>(0h0)
connect loops[1].ex_started, UInt<1>(0h0)
connect loops[1].ldd_started, UInt<1>(0h0)
connect loops[1].st_started, UInt<1>(0h0)
connect loops[1].lda_completed, UInt<1>(0h0)
connect loops[1].ldb_completed, UInt<1>(0h0)
connect loops[1].ex_completed, UInt<1>(0h0)
connect loops[1].ldd_completed, UInt<1>(0h0)
connect loops[1].st_completed, UInt<1>(0h0)
connect loops[1].a_addr_start, UInt<14>(0h2000)
connect loops[1].b_addr_end, UInt<15>(0h4000)
connect loops[1].resadd_addr_start, UInt<10>(0h200) | module LoopMatmul( // @[LoopMatmul.scala:766:7]
input clock, // @[LoopMatmul.scala:766:7]
input reset, // @[LoopMatmul.scala:766:7]
output io_in_ready, // @[LoopMatmul.scala:775:14]
input io_in_valid, // @[LoopMatmul.scala:775:14]
input [6:0] io_in_bits_cmd_inst_funct, // @[LoopMatmul.scala:775:14]
input [4:0] io_in_bits_cmd_inst_rs2, // @[LoopMatmul.scala:775:14]
input [4:0] io_in_bits_cmd_inst_rs1, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_inst_xd, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_inst_xs1, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_inst_xs2, // @[LoopMatmul.scala:775:14]
input [4:0] io_in_bits_cmd_inst_rd, // @[LoopMatmul.scala:775:14]
input [6:0] io_in_bits_cmd_inst_opcode, // @[LoopMatmul.scala:775:14]
input [63:0] io_in_bits_cmd_rs1, // @[LoopMatmul.scala:775:14]
input [63:0] io_in_bits_cmd_rs2, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_debug, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_cease, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_wfi, // @[LoopMatmul.scala:775:14]
input [31:0] io_in_bits_cmd_status_isa, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_dprv, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_dv, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_prv, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_v, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_sd, // @[LoopMatmul.scala:775:14]
input [22:0] io_in_bits_cmd_status_zero2, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mpv, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_gva, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mbe, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_sbe, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_sxl, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_uxl, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_sd_rv32, // @[LoopMatmul.scala:775:14]
input [7:0] io_in_bits_cmd_status_zero1, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_tsr, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_tw, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_tvm, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mxr, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_sum, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mprv, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_xs, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_fs, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_mpp, // @[LoopMatmul.scala:775:14]
input [1:0] io_in_bits_cmd_status_vs, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_spp, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mpie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_ube, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_spie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_upie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_mie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_hie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_sie, // @[LoopMatmul.scala:775:14]
input io_in_bits_cmd_status_uie, // @[LoopMatmul.scala:775:14]
input io_in_bits_from_matmul_fsm, // @[LoopMatmul.scala:775:14]
input io_in_bits_from_conv_fsm, // @[LoopMatmul.scala:775:14]
input io_out_ready, // @[LoopMatmul.scala:775:14]
output io_out_valid, // @[LoopMatmul.scala:775:14]
output [6:0] io_out_bits_cmd_inst_funct, // @[LoopMatmul.scala:775:14]
output [4:0] io_out_bits_cmd_inst_rs2, // @[LoopMatmul.scala:775:14]
output [4:0] io_out_bits_cmd_inst_rs1, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_inst_xd, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_inst_xs1, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_inst_xs2, // @[LoopMatmul.scala:775:14]
output [4:0] io_out_bits_cmd_inst_rd, // @[LoopMatmul.scala:775:14]
output [6:0] io_out_bits_cmd_inst_opcode, // @[LoopMatmul.scala:775:14]
output [63:0] io_out_bits_cmd_rs1, // @[LoopMatmul.scala:775:14]
output [63:0] io_out_bits_cmd_rs2, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_debug, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_cease, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_wfi, // @[LoopMatmul.scala:775:14]
output [31:0] io_out_bits_cmd_status_isa, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_dprv, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_dv, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_prv, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_v, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_sd, // @[LoopMatmul.scala:775:14]
output [22:0] io_out_bits_cmd_status_zero2, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mpv, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_gva, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mbe, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_sbe, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_sxl, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_uxl, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_sd_rv32, // @[LoopMatmul.scala:775:14]
output [7:0] io_out_bits_cmd_status_zero1, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_tsr, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_tw, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_tvm, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mxr, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_sum, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mprv, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_xs, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_fs, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_mpp, // @[LoopMatmul.scala:775:14]
output [1:0] io_out_bits_cmd_status_vs, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_spp, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mpie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_ube, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_spie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_upie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_mie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_hie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_sie, // @[LoopMatmul.scala:775:14]
output io_out_bits_cmd_status_uie, // @[LoopMatmul.scala:775:14]
output io_out_bits_from_matmul_fsm, // @[LoopMatmul.scala:775:14]
output io_out_bits_from_conv_fsm, // @[LoopMatmul.scala:775:14]
input [5:0] io_ld_completed, // @[LoopMatmul.scala:775:14]
input [5:0] io_st_completed, // @[LoopMatmul.scala:775:14]
input [5:0] io_ex_completed, // @[LoopMatmul.scala:775:14]
output io_busy // @[LoopMatmul.scala:775:14]
);
wire _arb_io_in_0_ready; // @[LoopMatmul.scala:830:19]
wire _arb_io_in_1_ready; // @[LoopMatmul.scala:830:19]
wire _arb_io_in_2_ready; // @[LoopMatmul.scala:830:19]
wire _arb_io_in_3_ready; // @[LoopMatmul.scala:830:19]
wire _arb_io_out_valid; // @[LoopMatmul.scala:830:19]
wire [6:0] _arb_io_out_bits_inst_funct; // @[LoopMatmul.scala:830:19]
wire [63:0] _arb_io_out_bits_rs1; // @[LoopMatmul.scala:830:19]
wire [63:0] _arb_io_out_bits_rs2; // @[LoopMatmul.scala:830:19]
wire _ldab_arb_io_inA_ready; // @[LoopMatmul.scala:813:24]
wire _ldab_arb_io_inB_ready; // @[LoopMatmul.scala:813:24]
wire _ldab_arb_io_out_valid; // @[LoopMatmul.scala:813:24]
wire [6:0] _ldab_arb_io_out_bits_inst_funct; // @[LoopMatmul.scala:813:24]
wire [63:0] _ldab_arb_io_out_bits_rs1; // @[LoopMatmul.scala:813:24]
wire [63:0] _ldab_arb_io_out_bits_rs2; // @[LoopMatmul.scala:813:24]
wire _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [6:0] _cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rs2; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rs1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xd; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xs1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_inst_xs2; // @[Decoupled.scala:362:21]
wire [4:0] _cmd_q_io_deq_bits_cmd_inst_rd; // @[Decoupled.scala:362:21]
wire [6:0] _cmd_q_io_deq_bits_cmd_inst_opcode; // @[Decoupled.scala:362:21]
wire [63:0] _cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21]
wire [63:0] _cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_debug; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_cease; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_wfi; // @[Decoupled.scala:362:21]
wire [31:0] _cmd_q_io_deq_bits_cmd_status_isa; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_dprv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_dv; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_prv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_v; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sd; // @[Decoupled.scala:362:21]
wire [22:0] _cmd_q_io_deq_bits_cmd_status_zero2; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mpv; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_gva; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mbe; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sbe; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_sxl; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_uxl; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sd_rv32; // @[Decoupled.scala:362:21]
wire [7:0] _cmd_q_io_deq_bits_cmd_status_zero1; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tsr; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tw; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_tvm; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mxr; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sum; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mprv; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_xs; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_fs; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_mpp; // @[Decoupled.scala:362:21]
wire [1:0] _cmd_q_io_deq_bits_cmd_status_vs; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_spp; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mpie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_ube; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_spie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_upie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_mie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_hie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_sie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_cmd_status_uie; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_from_matmul_fsm; // @[Decoupled.scala:362:21]
wire _cmd_q_io_deq_bits_from_conv_fsm; // @[Decoupled.scala:362:21]
wire _stC_io_req_ready; // @[LoopMatmul.scala:805:19]
wire _stC_io_cmd_valid; // @[LoopMatmul.scala:805:19]
wire [6:0] _stC_io_cmd_bits_inst_funct; // @[LoopMatmul.scala:805:19]
wire [63:0] _stC_io_cmd_bits_rs1; // @[LoopMatmul.scala:805:19]
wire [63:0] _stC_io_cmd_bits_rs2; // @[LoopMatmul.scala:805:19]
wire _stC_io_idle; // @[LoopMatmul.scala:805:19]
wire _stC_io_loop_id; // @[LoopMatmul.scala:805:19]
wire _ex_io_req_ready; // @[LoopMatmul.scala:804:18]
wire _ex_io_cmd_valid; // @[LoopMatmul.scala:804:18]
wire [6:0] _ex_io_cmd_bits_inst_funct; // @[LoopMatmul.scala:804:18]
wire [63:0] _ex_io_cmd_bits_rs1; // @[LoopMatmul.scala:804:18]
wire [63:0] _ex_io_cmd_bits_rs2; // @[LoopMatmul.scala:804:18]
wire [15:0] _ex_io_k; // @[LoopMatmul.scala:804:18]
wire [15:0] _ex_io_j; // @[LoopMatmul.scala:804:18]
wire [15:0] _ex_io_i; // @[LoopMatmul.scala:804:18]
wire _ex_io_idle; // @[LoopMatmul.scala:804:18]
wire _ex_io_loop_id; // @[LoopMatmul.scala:804:18]
wire _ldD_io_req_ready; // @[LoopMatmul.scala:803:19]
wire _ldD_io_cmd_valid; // @[LoopMatmul.scala:803:19]
wire [63:0] _ldD_io_cmd_bits_rs1; // @[LoopMatmul.scala:803:19]
wire [63:0] _ldD_io_cmd_bits_rs2; // @[LoopMatmul.scala:803:19]
wire _ldD_io_idle; // @[LoopMatmul.scala:803:19]
wire _ldD_io_loop_id; // @[LoopMatmul.scala:803:19]
wire _ldB_io_req_ready; // @[LoopMatmul.scala:802:19]
wire _ldB_io_cmd_valid; // @[LoopMatmul.scala:802:19]
wire [63:0] _ldB_io_cmd_bits_rs1; // @[LoopMatmul.scala:802:19]
wire [63:0] _ldB_io_cmd_bits_rs2; // @[LoopMatmul.scala:802:19]
wire [15:0] _ldB_io_k; // @[LoopMatmul.scala:802:19]
wire [15:0] _ldB_io_j; // @[LoopMatmul.scala:802:19]
wire _ldB_io_idle; // @[LoopMatmul.scala:802:19]
wire _ldB_io_loop_id; // @[LoopMatmul.scala:802:19]
wire _ldA_io_req_ready; // @[LoopMatmul.scala:801:19]
wire _ldA_io_cmd_valid; // @[LoopMatmul.scala:801:19]
wire [63:0] _ldA_io_cmd_bits_rs1; // @[LoopMatmul.scala:801:19]
wire [63:0] _ldA_io_cmd_bits_rs2; // @[LoopMatmul.scala:801:19]
wire [15:0] _ldA_io_i; // @[LoopMatmul.scala:801:19]
wire [15:0] _ldA_io_k; // @[LoopMatmul.scala:801:19]
wire _ldA_io_idle; // @[LoopMatmul.scala:801:19]
wire _ldA_io_loop_id; // @[LoopMatmul.scala:801:19]
wire io_in_valid_0 = io_in_valid; // @[LoopMatmul.scala:766:7]
wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[LoopMatmul.scala:766:7]
wire [4:0] io_in_bits_cmd_inst_rs2_0 = io_in_bits_cmd_inst_rs2; // @[LoopMatmul.scala:766:7]
wire [4:0] io_in_bits_cmd_inst_rs1_0 = io_in_bits_cmd_inst_rs1; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_inst_xd_0 = io_in_bits_cmd_inst_xd; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_inst_xs1_0 = io_in_bits_cmd_inst_xs1; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_inst_xs2_0 = io_in_bits_cmd_inst_xs2; // @[LoopMatmul.scala:766:7]
wire [4:0] io_in_bits_cmd_inst_rd_0 = io_in_bits_cmd_inst_rd; // @[LoopMatmul.scala:766:7]
wire [6:0] io_in_bits_cmd_inst_opcode_0 = io_in_bits_cmd_inst_opcode; // @[LoopMatmul.scala:766:7]
wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[LoopMatmul.scala:766:7]
wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_debug_0 = io_in_bits_cmd_status_debug; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_cease_0 = io_in_bits_cmd_status_cease; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_wfi_0 = io_in_bits_cmd_status_wfi; // @[LoopMatmul.scala:766:7]
wire [31:0] io_in_bits_cmd_status_isa_0 = io_in_bits_cmd_status_isa; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_dprv_0 = io_in_bits_cmd_status_dprv; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_dv_0 = io_in_bits_cmd_status_dv; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_prv_0 = io_in_bits_cmd_status_prv; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_v_0 = io_in_bits_cmd_status_v; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_sd_0 = io_in_bits_cmd_status_sd; // @[LoopMatmul.scala:766:7]
wire [22:0] io_in_bits_cmd_status_zero2_0 = io_in_bits_cmd_status_zero2; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mpv_0 = io_in_bits_cmd_status_mpv; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_gva_0 = io_in_bits_cmd_status_gva; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mbe_0 = io_in_bits_cmd_status_mbe; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_sbe_0 = io_in_bits_cmd_status_sbe; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_sxl_0 = io_in_bits_cmd_status_sxl; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_uxl_0 = io_in_bits_cmd_status_uxl; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_sd_rv32_0 = io_in_bits_cmd_status_sd_rv32; // @[LoopMatmul.scala:766:7]
wire [7:0] io_in_bits_cmd_status_zero1_0 = io_in_bits_cmd_status_zero1; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_tsr_0 = io_in_bits_cmd_status_tsr; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_tw_0 = io_in_bits_cmd_status_tw; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_tvm_0 = io_in_bits_cmd_status_tvm; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mxr_0 = io_in_bits_cmd_status_mxr; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_sum_0 = io_in_bits_cmd_status_sum; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mprv_0 = io_in_bits_cmd_status_mprv; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_xs_0 = io_in_bits_cmd_status_xs; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_fs_0 = io_in_bits_cmd_status_fs; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_mpp_0 = io_in_bits_cmd_status_mpp; // @[LoopMatmul.scala:766:7]
wire [1:0] io_in_bits_cmd_status_vs_0 = io_in_bits_cmd_status_vs; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_spp_0 = io_in_bits_cmd_status_spp; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mpie_0 = io_in_bits_cmd_status_mpie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_ube_0 = io_in_bits_cmd_status_ube; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_spie_0 = io_in_bits_cmd_status_spie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_upie_0 = io_in_bits_cmd_status_upie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_mie_0 = io_in_bits_cmd_status_mie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_hie_0 = io_in_bits_cmd_status_hie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_sie_0 = io_in_bits_cmd_status_sie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_cmd_status_uie_0 = io_in_bits_cmd_status_uie; // @[LoopMatmul.scala:766:7]
wire io_in_bits_from_matmul_fsm_0 = io_in_bits_from_matmul_fsm; // @[LoopMatmul.scala:766:7]
wire io_in_bits_from_conv_fsm_0 = io_in_bits_from_conv_fsm; // @[LoopMatmul.scala:766:7]
wire io_out_ready_0 = io_out_ready; // @[LoopMatmul.scala:766:7]
wire [5:0] io_ld_completed_0 = io_ld_completed; // @[LoopMatmul.scala:766:7]
wire [5:0] io_st_completed_0 = io_st_completed; // @[LoopMatmul.scala:766:7]
wire [5:0] io_ex_completed_0 = io_ex_completed; // @[LoopMatmul.scala:766:7]
wire io_in_bits_rob_id_valid = 1'h0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_rob_id_valid = 1'h0; // @[LoopMatmul.scala:766:7]
wire _ex_c_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire _ld_d_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire _st_c_addr_start_T_2 = 1'h0; // @[Util.scala:42:8]
wire [5:0] io_in_bits_rob_id_bits = 6'h0; // @[LoopMatmul.scala:766:7]
wire [5:0] io_out_bits_rob_id_bits = 6'h0; // @[LoopMatmul.scala:766:7]
wire [10:0] ex_c_addr_start_max = 11'h3FF; // @[Util.scala:39:28]
wire [10:0] ld_d_addr_start_max = 11'h3FF; // @[Util.scala:39:28]
wire [10:0] st_c_addr_start_max = 11'h3FF; // @[Util.scala:39:28]
wire [11:0] _ex_c_addr_start_max_T = 12'h3FF; // @[Util.scala:39:28]
wire [11:0] _ld_d_addr_start_max_T = 12'h3FF; // @[Util.scala:39:28]
wire [11:0] _st_c_addr_start_max_T = 12'h3FF; // @[Util.scala:39:28]
wire _io_out_valid_T_4; // @[LoopMatmul.scala:860:22]
wire [6:0] _io_out_bits_cmd_T_inst_funct; // @[LoopMatmul.scala:855:25]
wire [4:0] _io_out_bits_cmd_T_inst_rs2; // @[LoopMatmul.scala:855:25]
wire [4:0] _io_out_bits_cmd_T_inst_rs1; // @[LoopMatmul.scala:855:25]
wire _io_out_bits_cmd_T_inst_xd; // @[LoopMatmul.scala:855:25]
wire _io_out_bits_cmd_T_inst_xs1; // @[LoopMatmul.scala:855:25]
wire _io_out_bits_cmd_T_inst_xs2; // @[LoopMatmul.scala:855:25]
wire [4:0] _io_out_bits_cmd_T_inst_rd; // @[LoopMatmul.scala:855:25]
wire [6:0] _io_out_bits_cmd_T_inst_opcode; // @[LoopMatmul.scala:855:25]
wire [63:0] _io_out_bits_cmd_T_rs1; // @[LoopMatmul.scala:855:25]
wire [63:0] _io_out_bits_cmd_T_rs2; // @[LoopMatmul.scala:855:25]
wire _io_out_bits_from_matmul_fsm_T; // @[LoopMatmul.scala:858:37]
wire _io_out_bits_from_conv_fsm_T; // @[LoopMatmul.scala:859:35]
wire _io_busy_T; // @[LoopMatmul.scala:810:24]
wire io_in_ready_0; // @[LoopMatmul.scala:766:7]
wire [6:0] io_out_bits_cmd_inst_funct_0; // @[LoopMatmul.scala:766:7]
wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[LoopMatmul.scala:766:7]
wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_inst_xd_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_inst_xs1_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_inst_xs2_0; // @[LoopMatmul.scala:766:7]
wire [4:0] io_out_bits_cmd_inst_rd_0; // @[LoopMatmul.scala:766:7]
wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_debug_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_cease_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_wfi_0; // @[LoopMatmul.scala:766:7]
wire [31:0] io_out_bits_cmd_status_isa_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_dprv_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_dv_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_prv_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_v_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_sd_0; // @[LoopMatmul.scala:766:7]
wire [22:0] io_out_bits_cmd_status_zero2_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mpv_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_gva_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mbe_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_sbe_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_sxl_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_uxl_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_sd_rv32_0; // @[LoopMatmul.scala:766:7]
wire [7:0] io_out_bits_cmd_status_zero1_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_tsr_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_tw_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_tvm_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mxr_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_sum_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mprv_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_xs_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_fs_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_mpp_0; // @[LoopMatmul.scala:766:7]
wire [1:0] io_out_bits_cmd_status_vs_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_spp_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mpie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_ube_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_spie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_upie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_mie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_hie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_sie_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_cmd_status_uie_0; // @[LoopMatmul.scala:766:7]
wire [63:0] io_out_bits_cmd_rs1_0; // @[LoopMatmul.scala:766:7]
wire [63:0] io_out_bits_cmd_rs2_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_from_matmul_fsm_0; // @[LoopMatmul.scala:766:7]
wire io_out_bits_from_conv_fsm_0; // @[LoopMatmul.scala:766:7]
wire io_out_valid_0; // @[LoopMatmul.scala:766:7]
wire io_busy_0; // @[LoopMatmul.scala:766:7]
reg [15:0] loops_0_max_k; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_0_max_j; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_0_max_i; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_0_pad_k; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_0_pad_j; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_0_pad_i; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_a_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_b_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_d_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_c_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_a_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_b_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_d_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_0_c_dram_stride; // @[LoopMatmul.scala:786:18]
reg loops_0_a_transpose; // @[LoopMatmul.scala:786:18]
reg loops_0_b_transpose; // @[LoopMatmul.scala:786:18]
reg [2:0] loops_0_act; // @[LoopMatmul.scala:786:18]
reg loops_0_low_d; // @[LoopMatmul.scala:786:18]
reg loops_0_full_c; // @[LoopMatmul.scala:786:18]
reg loops_0_ex_accumulate; // @[LoopMatmul.scala:786:18]
reg [1:0] loops_0_a_ex_spad_id; // @[LoopMatmul.scala:786:18]
reg [1:0] loops_0_b_ex_spad_id; // @[LoopMatmul.scala:786:18]
reg loops_0_configured; // @[LoopMatmul.scala:786:18]
reg loops_0_running; // @[LoopMatmul.scala:786:18]
reg loops_0_lda_started; // @[LoopMatmul.scala:786:18]
reg loops_0_ldb_started; // @[LoopMatmul.scala:786:18]
reg loops_0_ex_started; // @[LoopMatmul.scala:786:18]
reg loops_0_ldd_started; // @[LoopMatmul.scala:786:18]
reg loops_0_st_started; // @[LoopMatmul.scala:786:18]
reg loops_0_lda_completed; // @[LoopMatmul.scala:786:18]
reg loops_0_ldb_completed; // @[LoopMatmul.scala:786:18]
reg loops_0_ex_completed; // @[LoopMatmul.scala:786:18]
reg loops_0_ldd_completed; // @[LoopMatmul.scala:786:18]
reg loops_0_st_completed; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_max_k; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_max_j; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_max_i; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_pad_k; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_pad_j; // @[LoopMatmul.scala:786:18]
reg [15:0] loops_1_pad_i; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_a_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_b_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_d_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_c_dram_addr; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_a_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_b_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_d_dram_stride; // @[LoopMatmul.scala:786:18]
reg [39:0] loops_1_c_dram_stride; // @[LoopMatmul.scala:786:18]
reg loops_1_a_transpose; // @[LoopMatmul.scala:786:18]
reg loops_1_b_transpose; // @[LoopMatmul.scala:786:18]
reg [2:0] loops_1_act; // @[LoopMatmul.scala:786:18]
reg loops_1_low_d; // @[LoopMatmul.scala:786:18]
reg loops_1_full_c; // @[LoopMatmul.scala:786:18]
reg loops_1_ex_accumulate; // @[LoopMatmul.scala:786:18]
reg [1:0] loops_1_a_ex_spad_id; // @[LoopMatmul.scala:786:18]
reg [1:0] loops_1_b_ex_spad_id; // @[LoopMatmul.scala:786:18]
reg loops_1_configured; // @[LoopMatmul.scala:786:18]
reg loops_1_running; // @[LoopMatmul.scala:786:18]
reg loops_1_lda_started; // @[LoopMatmul.scala:786:18]
reg loops_1_ldb_started; // @[LoopMatmul.scala:786:18]
reg loops_1_ex_started; // @[LoopMatmul.scala:786:18]
reg loops_1_ldd_started; // @[LoopMatmul.scala:786:18]
reg loops_1_st_started; // @[LoopMatmul.scala:786:18]
reg loops_1_lda_completed; // @[LoopMatmul.scala:786:18]
reg loops_1_ldb_completed; // @[LoopMatmul.scala:786:18]
reg loops_1_ex_completed; // @[LoopMatmul.scala:786:18]
reg loops_1_ldd_completed; // @[LoopMatmul.scala:786:18]
reg loops_1_st_completed; // @[LoopMatmul.scala:786:18]
reg head_loop_id; // @[LoopMatmul.scala:787:25]
wire tail_loop_id = ~head_loop_id; // @[LoopMatmul.scala:787:25, :788:23]
wire loop_configured = loops_0_configured | loops_1_configured; // @[LoopMatmul.scala:786:18, :792:58]
wire loop_being_configured_id = (head_loop_id ? loops_1_configured : loops_0_configured) ? tail_loop_id : head_loop_id; // @[LoopMatmul.scala:786:18, :787:25, :788:23, :794:37]
reg is_resadd; // @[LoopMatmul.scala:797:26]
assign _io_busy_T = _cmd_q_io_deq_valid | loop_configured; // @[Decoupled.scala:362:21]
assign io_busy_0 = _io_busy_T; // @[LoopMatmul.scala:766:7, :810:24]
wire ab_loads_on_same_loop = _ldA_io_loop_id == _ldB_io_loop_id; // @[LoopMatmul.scala:801:19, :802:19, :816:46]
wire _forceA_T = ~ab_loads_on_same_loop; // @[LoopMatmul.scala:816:46, :817:16]
wire _forceA_T_1 = _ldA_io_loop_id == head_loop_id; // @[LoopMatmul.scala:787:25, :801:19, :817:57]
wire forceA = _forceA_T & _forceA_T_1; // @[LoopMatmul.scala:817:{16,39,57}]
wire _forceB_T = ~ab_loads_on_same_loop; // @[LoopMatmul.scala:816:46, :817:16, :818:16]
wire _forceB_T_1 = _ldB_io_loop_id == head_loop_id; // @[LoopMatmul.scala:787:25, :802:19, :818:57]
wire forceB = _forceB_T & _forceB_T_1; // @[LoopMatmul.scala:818:{16,39,57}]
wire _ldab_arb_io_forceA_T = ~_ldA_io_idle; // @[LoopMatmul.scala:801:19, :819:65]
wire _ldab_arb_io_forceA_T_1 = ab_loads_on_same_loop & _ldab_arb_io_forceA_T; // @[LoopMatmul.scala:816:46, :819:{62,65}]
wire _ldab_arb_io_forceA_T_2 = is_resadd ? _ldab_arb_io_forceA_T_1 : forceA; // @[LoopMatmul.scala:797:26, :817:39, :819:{28,62}]
wire _ldab_arb_io_forceB_T = forceB | _ldA_io_idle; // @[LoopMatmul.scala:801:19, :818:39, :820:47]
wire _ldab_arb_io_forceB_T_1 = is_resadd ? _ldab_arb_io_forceB_T : forceB; // @[LoopMatmul.scala:797:26, :818:39, :820:{28,47}]
reg [3:0] ld_utilization; // @[LoopMatmul.scala:838:31]
reg [2:0] st_utilization; // @[LoopMatmul.scala:839:31]
reg [4:0] ex_utilization; // @[LoopMatmul.scala:840:31]
wire _ld_utilization_T = _ldab_arb_io_inA_ready & _ldA_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_1 = _ldab_arb_io_inB_ready & _ldB_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_2 = _ld_utilization_T | _ld_utilization_T_1; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_3 = _arb_io_in_2_ready & _ldD_io_cmd_valid; // @[Decoupled.scala:51:35]
wire _ld_utilization_T_4 = _ld_utilization_T_2 | _ld_utilization_T_3; // @[Decoupled.scala:51:35]
wire [4:0] _ld_utilization_T_5 = {1'h0, ld_utilization} + {4'h0, _ld_utilization_T_4}; // @[LoopMatmul.scala:838:31, :842:{36,75}]
wire [6:0] _ld_utilization_T_6 = {2'h0, _ld_utilization_T_5} - {1'h0, io_ld_completed_0}; // @[LoopMatmul.scala:766:7, :842:{36,95}]
wire [6:0] _ld_utilization_T_7 = _ld_utilization_T_6; // @[LoopMatmul.scala:842:95]
wire _st_utilization_T = _arb_io_in_0_ready & _stC_io_cmd_valid; // @[Decoupled.scala:51:35]
wire [3:0] _st_utilization_T_1 = {1'h0, st_utilization} + {3'h0, _st_utilization_T}; // @[Decoupled.scala:51:35]
wire [6:0] _st_utilization_T_2 = {3'h0, _st_utilization_T_1} - {1'h0, io_st_completed_0}; // @[LoopMatmul.scala:766:7, :843:{36,55}]
wire [6:0] _st_utilization_T_3 = _st_utilization_T_2; // @[LoopMatmul.scala:843:55]
wire _ex_utilization_T = _arb_io_in_1_ready & _ex_io_cmd_valid; // @[Decoupled.scala:51:35]
wire [5:0] _GEN = {1'h0, ex_utilization}; // @[LoopMatmul.scala:840:31, :844:36]
wire [5:0] _ex_utilization_T_1 = _GEN + {5'h0, _ex_utilization_T}; // @[Decoupled.scala:51:35]
wire [6:0] _ex_utilization_T_2 = {1'h0, _ex_utilization_T_1} - {1'h0, io_ex_completed_0}; // @[LoopMatmul.scala:766:7, :844:{36,54}]
wire [6:0] _ex_utilization_T_3 = _ex_utilization_T_2; // @[LoopMatmul.scala:844:54] |
Generate the Verilog code corresponding to this FIRRTL code module NBDTLB_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}[1], miss_rdy : UInt<1>, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<33>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
invalidate io.ptw.gstatus.uie
invalidate io.ptw.gstatus.sie
invalidate io.ptw.gstatus.hie
invalidate io.ptw.gstatus.mie
invalidate io.ptw.gstatus.upie
invalidate io.ptw.gstatus.spie
invalidate io.ptw.gstatus.ube
invalidate io.ptw.gstatus.mpie
invalidate io.ptw.gstatus.spp
invalidate io.ptw.gstatus.vs
invalidate io.ptw.gstatus.mpp
invalidate io.ptw.gstatus.fs
invalidate io.ptw.gstatus.xs
invalidate io.ptw.gstatus.mprv
invalidate io.ptw.gstatus.sum
invalidate io.ptw.gstatus.mxr
invalidate io.ptw.gstatus.tvm
invalidate io.ptw.gstatus.tw
invalidate io.ptw.gstatus.tsr
invalidate io.ptw.gstatus.zero1
invalidate io.ptw.gstatus.sd_rv32
invalidate io.ptw.gstatus.uxl
invalidate io.ptw.gstatus.sxl
invalidate io.ptw.gstatus.sbe
invalidate io.ptw.gstatus.mbe
invalidate io.ptw.gstatus.gva
invalidate io.ptw.gstatus.mpv
invalidate io.ptw.gstatus.zero2
invalidate io.ptw.gstatus.sd
invalidate io.ptw.gstatus.v
invalidate io.ptw.gstatus.prv
invalidate io.ptw.gstatus.dv
invalidate io.ptw.gstatus.dprv
invalidate io.ptw.gstatus.isa
invalidate io.ptw.gstatus.wfi
invalidate io.ptw.gstatus.cease
invalidate io.ptw.gstatus.debug
invalidate io.ptw.hstatus.zero1
invalidate io.ptw.hstatus.vsbe
invalidate io.ptw.hstatus.gva
invalidate io.ptw.hstatus.spv
invalidate io.ptw.hstatus.spvp
invalidate io.ptw.hstatus.hu
invalidate io.ptw.hstatus.zero2
invalidate io.ptw.hstatus.vgein
invalidate io.ptw.hstatus.zero3
invalidate io.ptw.hstatus.vtvm
invalidate io.ptw.hstatus.vtw
invalidate io.ptw.hstatus.vtsr
invalidate io.ptw.hstatus.zero5
invalidate io.ptw.hstatus.vsxl
invalidate io.ptw.hstatus.zero6
invalidate io.ptw.status.uie
invalidate io.ptw.status.sie
invalidate io.ptw.status.hie
invalidate io.ptw.status.mie
invalidate io.ptw.status.upie
invalidate io.ptw.status.spie
invalidate io.ptw.status.ube
invalidate io.ptw.status.mpie
invalidate io.ptw.status.spp
invalidate io.ptw.status.vs
invalidate io.ptw.status.mpp
invalidate io.ptw.status.fs
invalidate io.ptw.status.xs
invalidate io.ptw.status.mprv
invalidate io.ptw.status.sum
invalidate io.ptw.status.mxr
invalidate io.ptw.status.tvm
invalidate io.ptw.status.tw
invalidate io.ptw.status.tsr
invalidate io.ptw.status.zero1
invalidate io.ptw.status.sd_rv32
invalidate io.ptw.status.uxl
invalidate io.ptw.status.sxl
invalidate io.ptw.status.sbe
invalidate io.ptw.status.mbe
invalidate io.ptw.status.gva
invalidate io.ptw.status.mpv
invalidate io.ptw.status.zero2
invalidate io.ptw.status.sd
invalidate io.ptw.status.v
invalidate io.ptw.status.prv
invalidate io.ptw.status.dv
invalidate io.ptw.status.dprv
invalidate io.ptw.status.isa
invalidate io.ptw.status.wfi
invalidate io.ptw.status.cease
invalidate io.ptw.status.debug
invalidate io.ptw.vsatp.ppn
invalidate io.ptw.vsatp.asid
invalidate io.ptw.vsatp.mode
invalidate io.ptw.hgatp.ppn
invalidate io.ptw.hgatp.asid
invalidate io.ptw.hgatp.mode
invalidate io.ptw.ptbr.ppn
invalidate io.ptw.ptbr.asid
invalidate io.ptw.ptbr.mode
invalidate io.ptw.resp.bits.gpa_is_pte
invalidate io.ptw.resp.bits.gpa.bits
invalidate io.ptw.resp.bits.gpa.valid
invalidate io.ptw.resp.bits.homogeneous
invalidate io.ptw.resp.bits.fragmented_superpage
invalidate io.ptw.resp.bits.level
invalidate io.ptw.resp.bits.pte.v
invalidate io.ptw.resp.bits.pte.r
invalidate io.ptw.resp.bits.pte.w
invalidate io.ptw.resp.bits.pte.x
invalidate io.ptw.resp.bits.pte.u
invalidate io.ptw.resp.bits.pte.g
invalidate io.ptw.resp.bits.pte.a
invalidate io.ptw.resp.bits.pte.d
invalidate io.ptw.resp.bits.pte.reserved_for_software
invalidate io.ptw.resp.bits.pte.ppn
invalidate io.ptw.resp.bits.pte.reserved_for_future
invalidate io.ptw.resp.bits.hx
invalidate io.ptw.resp.bits.hw
invalidate io.ptw.resp.bits.hr
invalidate io.ptw.resp.bits.gf
invalidate io.ptw.resp.bits.pf
invalidate io.ptw.resp.bits.ae_final
invalidate io.ptw.resp.bits.ae_ptw
invalidate io.ptw.resp.valid
invalidate io.ptw.req.bits.bits.stage2
invalidate io.ptw.req.bits.bits.vstage1
invalidate io.ptw.req.bits.bits.need_gpa
invalidate io.ptw.req.bits.bits.addr
invalidate io.ptw.req.bits.valid
invalidate io.ptw.req.valid
invalidate io.ptw.req.ready
invalidate io.resp[0].cmd
invalidate io.resp[0].size
invalidate io.resp[0].prefetchable
invalidate io.resp[0].must_alloc
invalidate io.resp[0].cacheable
invalidate io.resp[0].ma.inst
invalidate io.resp[0].ma.st
invalidate io.resp[0].ma.ld
invalidate io.resp[0].ae.inst
invalidate io.resp[0].ae.st
invalidate io.resp[0].ae.ld
invalidate io.resp[0].gf.inst
invalidate io.resp[0].gf.st
invalidate io.resp[0].gf.ld
invalidate io.resp[0].pf.inst
invalidate io.resp[0].pf.st
invalidate io.resp[0].pf.ld
invalidate io.resp[0].gpa_is_pte
invalidate io.resp[0].gpa
invalidate io.resp[0].paddr
invalidate io.resp[0].miss
reg sectored_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[4], valid : UInt<1>[4]}[8], clock
reg superpage_entries : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag : UInt<21>, data : UInt<34>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<21>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit_addr : UInt<3>, clock
reg r_sectored_hit : UInt<1>, clock
node priv_s = bits(io.ptw.status.dprv, 0, 0)
node priv_uses_vm = leq(io.ptw.status.dprv, UInt<1>(0h1))
node _vm_enabled_T = bits(io.ptw.ptbr.mode, 3, 3)
node _vm_enabled_T_1 = and(UInt<1>(0h0), _vm_enabled_T)
node _vm_enabled_T_2 = and(_vm_enabled_T_1, priv_uses_vm)
node _vm_enabled_T_3 = eq(io.req[0].bits.passthrough, UInt<1>(0h0))
node _vm_enabled_T_4 = and(_vm_enabled_T_2, _vm_enabled_T_3)
wire vm_enabled : UInt<1>[1]
connect vm_enabled[0], _vm_enabled_T_4
node _vpn_T = bits(io.req[0].bits.vaddr, 32, 12)
wire vpn : UInt<21>[1]
connect vpn[0], _vpn_T
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h0), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled[0], UInt<1>(0h1))
wire _mpu_ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_data_WIRE_1 : UInt<34>
connect _mpu_ppn_data_WIRE_1, special_entry.data[0]
node _mpu_ppn_data_T = bits(_mpu_ppn_data_WIRE_1, 0, 0)
connect _mpu_ppn_data_WIRE.fragmented_superpage, _mpu_ppn_data_T
node _mpu_ppn_data_T_1 = bits(_mpu_ppn_data_WIRE_1, 1, 1)
connect _mpu_ppn_data_WIRE.c, _mpu_ppn_data_T_1
node _mpu_ppn_data_T_2 = bits(_mpu_ppn_data_WIRE_1, 2, 2)
connect _mpu_ppn_data_WIRE.eff, _mpu_ppn_data_T_2
node _mpu_ppn_data_T_3 = bits(_mpu_ppn_data_WIRE_1, 3, 3)
connect _mpu_ppn_data_WIRE.paa, _mpu_ppn_data_T_3
node _mpu_ppn_data_T_4 = bits(_mpu_ppn_data_WIRE_1, 4, 4)
connect _mpu_ppn_data_WIRE.pal, _mpu_ppn_data_T_4
node _mpu_ppn_data_T_5 = bits(_mpu_ppn_data_WIRE_1, 5, 5)
connect _mpu_ppn_data_WIRE.pr, _mpu_ppn_data_T_5
node _mpu_ppn_data_T_6 = bits(_mpu_ppn_data_WIRE_1, 6, 6)
connect _mpu_ppn_data_WIRE.px, _mpu_ppn_data_T_6
node _mpu_ppn_data_T_7 = bits(_mpu_ppn_data_WIRE_1, 7, 7)
connect _mpu_ppn_data_WIRE.pw, _mpu_ppn_data_T_7
node _mpu_ppn_data_T_8 = bits(_mpu_ppn_data_WIRE_1, 8, 8)
connect _mpu_ppn_data_WIRE.sr, _mpu_ppn_data_T_8
node _mpu_ppn_data_T_9 = bits(_mpu_ppn_data_WIRE_1, 9, 9)
connect _mpu_ppn_data_WIRE.sx, _mpu_ppn_data_T_9
node _mpu_ppn_data_T_10 = bits(_mpu_ppn_data_WIRE_1, 10, 10)
connect _mpu_ppn_data_WIRE.sw, _mpu_ppn_data_T_10
node _mpu_ppn_data_T_11 = bits(_mpu_ppn_data_WIRE_1, 11, 11)
connect _mpu_ppn_data_WIRE.ae, _mpu_ppn_data_T_11
node _mpu_ppn_data_T_12 = bits(_mpu_ppn_data_WIRE_1, 12, 12)
connect _mpu_ppn_data_WIRE.g, _mpu_ppn_data_T_12
node _mpu_ppn_data_T_13 = bits(_mpu_ppn_data_WIRE_1, 13, 13)
connect _mpu_ppn_data_WIRE.u, _mpu_ppn_data_T_13
node _mpu_ppn_data_T_14 = bits(_mpu_ppn_data_WIRE_1, 33, 14)
connect _mpu_ppn_data_WIRE.ppn, _mpu_ppn_data_T_14
inst mpu_ppn_data_barrier of OptimizationBarrier_EntryData_39
connect mpu_ppn_data_barrier.clock, clock
connect mpu_ppn_data_barrier.reset, reset
connect mpu_ppn_data_barrier.io.x.fragmented_superpage, _mpu_ppn_data_WIRE.fragmented_superpage
connect mpu_ppn_data_barrier.io.x.c, _mpu_ppn_data_WIRE.c
connect mpu_ppn_data_barrier.io.x.eff, _mpu_ppn_data_WIRE.eff
connect mpu_ppn_data_barrier.io.x.paa, _mpu_ppn_data_WIRE.paa
connect mpu_ppn_data_barrier.io.x.pal, _mpu_ppn_data_WIRE.pal
connect mpu_ppn_data_barrier.io.x.pr, _mpu_ppn_data_WIRE.pr
connect mpu_ppn_data_barrier.io.x.px, _mpu_ppn_data_WIRE.px
connect mpu_ppn_data_barrier.io.x.pw, _mpu_ppn_data_WIRE.pw
connect mpu_ppn_data_barrier.io.x.sr, _mpu_ppn_data_WIRE.sr
connect mpu_ppn_data_barrier.io.x.sx, _mpu_ppn_data_WIRE.sx
connect mpu_ppn_data_barrier.io.x.sw, _mpu_ppn_data_WIRE.sw
connect mpu_ppn_data_barrier.io.x.ae, _mpu_ppn_data_WIRE.ae
connect mpu_ppn_data_barrier.io.x.g, _mpu_ppn_data_WIRE.g
connect mpu_ppn_data_barrier.io.x.u, _mpu_ppn_data_WIRE.u
connect mpu_ppn_data_barrier.io.x.ppn, _mpu_ppn_data_WIRE.ppn
node _mpu_ppn_T_1 = shr(io.req[0].bits.vaddr, 12)
node _mpu_ppn_T_2 = mux(_mpu_ppn_T, mpu_ppn_data_barrier.io.y.ppn, _mpu_ppn_T_1)
node _mpu_ppn_T_3 = mux(do_refill, refill_ppn, _mpu_ppn_T_2)
wire mpu_ppn : UInt<22>[1]
connect mpu_ppn[0], _mpu_ppn_T_3
node _mpu_physaddr_T = bits(io.req[0].bits.vaddr, 11, 0)
node _mpu_physaddr_T_1 = cat(mpu_ppn[0], _mpu_physaddr_T)
wire mpu_physaddr : UInt<34>[1]
connect mpu_physaddr[0], _mpu_physaddr_T_1
inst pmp_0 of PMPChecker_s3_1
connect pmp_0.clock, clock
connect pmp_0.reset, reset
connect pmp_0.io.addr, mpu_physaddr[0]
connect pmp_0.io.size, io.req[0].bits.size
node _pmp_0_io_prv_T = or(do_refill, io.req[0].bits.passthrough)
node _pmp_0_io_prv_T_1 = and(UInt<1>(0h0), _pmp_0_io_prv_T)
node _pmp_0_io_prv_T_2 = mux(_pmp_0_io_prv_T_1, UInt<1>(0h1), io.ptw.status.dprv)
connect pmp_0.io.prv, _pmp_0_io_prv_T_2
node _legal_address_T = xor(mpu_physaddr[0], UInt<14>(0h3000))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(mpu_physaddr[0], UInt<21>(0h110000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(mpu_physaddr[0], UInt<26>(0h2010000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<13>(0h1000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[5]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
node _legal_address_T_25 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_26 = or(_legal_address_T_25, _legal_address_WIRE[2])
node _legal_address_T_27 = or(_legal_address_T_26, _legal_address_WIRE[3])
node _legal_address_T_28 = or(_legal_address_T_27, _legal_address_WIRE[4])
wire legal_address : UInt<1>[1]
connect legal_address[0], _legal_address_T_28
node _cacheable_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _cacheable_T_1 = cvt(_cacheable_T)
node _cacheable_T_2 = and(_cacheable_T_1, asSInt(UInt<33>(0h80000000)))
node _cacheable_T_3 = asSInt(_cacheable_T_2)
node _cacheable_T_4 = eq(_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _cacheable_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _cacheable_T_6 = cvt(_cacheable_T_5)
node _cacheable_T_7 = and(_cacheable_T_6, asSInt(UInt<33>(0h80000000)))
node _cacheable_T_8 = asSInt(_cacheable_T_7)
node _cacheable_T_9 = eq(_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _cacheable_T_10 = mux(_cacheable_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _cacheable_T_11 = mux(_cacheable_T_9, UInt<1>(0h1), UInt<1>(0h0))
node _cacheable_T_12 = or(_cacheable_T_10, _cacheable_T_11)
wire _cacheable_WIRE : UInt<1>
connect _cacheable_WIRE, _cacheable_T_12
node _cacheable_T_13 = and(legal_address[0], _cacheable_WIRE)
node _cacheable_T_14 = and(_cacheable_T_13, UInt<1>(0h1))
wire cacheable : UInt<1>[1]
connect cacheable[0], _cacheable_T_14
node _homogeneous_T = xor(mpu_physaddr[0], UInt<14>(0h3000))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr[0], UInt<21>(0h100000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr[0], UInt<26>(0h2010000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_21 = or(_homogeneous_T_20, _homogeneous_T_9)
node _homogeneous_T_22 = or(_homogeneous_T_21, _homogeneous_T_14)
node _homogeneous_T_23 = or(_homogeneous_T_22, _homogeneous_T_19)
node _homogeneous_T_24 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_25 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_26 = xor(mpu_physaddr[0], UInt<1>(0h0))
node _homogeneous_T_27 = cvt(_homogeneous_T_26)
node _homogeneous_T_28 = and(_homogeneous_T_27, asSInt(UInt<33>(0h80002000)))
node _homogeneous_T_29 = asSInt(_homogeneous_T_28)
node _homogeneous_T_30 = eq(_homogeneous_T_29, asSInt(UInt<1>(0h0)))
node _homogeneous_T_31 = or(UInt<1>(0h0), _homogeneous_T_30)
node _homogeneous_T_32 = eq(_homogeneous_T_31, UInt<1>(0h0))
node _homogeneous_T_33 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _homogeneous_T_34 = cvt(_homogeneous_T_33)
node _homogeneous_T_35 = and(_homogeneous_T_34, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_36 = asSInt(_homogeneous_T_35)
node _homogeneous_T_37 = eq(_homogeneous_T_36, asSInt(UInt<1>(0h0)))
node _homogeneous_T_38 = or(UInt<1>(0h0), _homogeneous_T_37)
node _homogeneous_T_39 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_40 = eq(UInt<1>(0h0), UInt<1>(0h0))
wire homogeneous : UInt<1>[1]
connect homogeneous[0], _homogeneous_T_23
node _prot_r_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_r_T_1 = cvt(_prot_r_T)
node _prot_r_T_2 = and(_prot_r_T_1, asSInt(UInt<1>(0h0)))
node _prot_r_T_3 = asSInt(_prot_r_T_2)
node _prot_r_T_4 = eq(_prot_r_T_3, asSInt(UInt<1>(0h0)))
node _prot_r_T_5 = and(legal_address[0], UInt<1>(0h1))
node _prot_r_T_6 = and(_prot_r_T_5, pmp_0.io.r)
wire prot_r : UInt<1>[1]
connect prot_r[0], _prot_r_T_6
node _prot_w_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_w_T_1 = cvt(_prot_w_T)
node _prot_w_T_2 = and(_prot_w_T_1, asSInt(UInt<1>(0h0)))
node _prot_w_T_3 = asSInt(_prot_w_T_2)
node _prot_w_T_4 = eq(_prot_w_T_3, asSInt(UInt<1>(0h0)))
node _prot_w_T_5 = and(legal_address[0], UInt<1>(0h1))
node _prot_w_T_6 = and(_prot_w_T_5, pmp_0.io.w)
wire prot_w : UInt<1>[1]
connect prot_w[0], _prot_w_T_6
node _prot_al_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_al_T_1 = cvt(_prot_al_T)
node _prot_al_T_2 = and(_prot_al_T_1, asSInt(UInt<1>(0h0)))
node _prot_al_T_3 = asSInt(_prot_al_T_2)
node _prot_al_T_4 = eq(_prot_al_T_3, asSInt(UInt<1>(0h0)))
node _prot_al_T_5 = and(legal_address[0], UInt<1>(0h1))
wire prot_al : UInt<1>[1]
connect prot_al[0], _prot_al_T_5
node _prot_aa_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_aa_T_1 = cvt(_prot_aa_T)
node _prot_aa_T_2 = and(_prot_aa_T_1, asSInt(UInt<1>(0h0)))
node _prot_aa_T_3 = asSInt(_prot_aa_T_2)
node _prot_aa_T_4 = eq(_prot_aa_T_3, asSInt(UInt<1>(0h0)))
node _prot_aa_T_5 = and(legal_address[0], UInt<1>(0h1))
wire prot_aa : UInt<1>[1]
connect prot_aa[0], _prot_aa_T_5
node _prot_x_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_x_T_1 = cvt(_prot_x_T)
node _prot_x_T_2 = and(_prot_x_T_1, asSInt(UInt<33>(0h80110000)))
node _prot_x_T_3 = asSInt(_prot_x_T_2)
node _prot_x_T_4 = eq(_prot_x_T_3, asSInt(UInt<1>(0h0)))
node _prot_x_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _prot_x_T_6 = cvt(_prot_x_T_5)
node _prot_x_T_7 = and(_prot_x_T_6, asSInt(UInt<33>(0h80000000)))
node _prot_x_T_8 = asSInt(_prot_x_T_7)
node _prot_x_T_9 = eq(_prot_x_T_8, asSInt(UInt<1>(0h0)))
node _prot_x_T_10 = or(_prot_x_T_4, _prot_x_T_9)
node _prot_x_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000))
node _prot_x_T_12 = cvt(_prot_x_T_11)
node _prot_x_T_13 = and(_prot_x_T_12, asSInt(UInt<33>(0h80110000)))
node _prot_x_T_14 = asSInt(_prot_x_T_13)
node _prot_x_T_15 = eq(_prot_x_T_14, asSInt(UInt<1>(0h0)))
node _prot_x_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000))
node _prot_x_T_17 = cvt(_prot_x_T_16)
node _prot_x_T_18 = and(_prot_x_T_17, asSInt(UInt<33>(0h80100000)))
node _prot_x_T_19 = asSInt(_prot_x_T_18)
node _prot_x_T_20 = eq(_prot_x_T_19, asSInt(UInt<1>(0h0)))
node _prot_x_T_21 = or(_prot_x_T_15, _prot_x_T_20)
node _prot_x_T_22 = mux(_prot_x_T_10, UInt<1>(0h1), UInt<1>(0h0))
node _prot_x_T_23 = mux(_prot_x_T_21, UInt<1>(0h0), UInt<1>(0h0))
node _prot_x_T_24 = or(_prot_x_T_22, _prot_x_T_23)
wire _prot_x_WIRE : UInt<1>
connect _prot_x_WIRE, _prot_x_T_24
node _prot_x_T_25 = and(legal_address[0], _prot_x_WIRE)
node _prot_x_T_26 = and(_prot_x_T_25, pmp_0.io.x)
wire prot_x : UInt<1>[1]
connect prot_x[0], _prot_x_T_26
node _prot_eff_T = xor(mpu_physaddr[0], UInt<1>(0h0))
node _prot_eff_T_1 = cvt(_prot_eff_T)
node _prot_eff_T_2 = and(_prot_eff_T_1, asSInt(UInt<33>(0h80110000)))
node _prot_eff_T_3 = asSInt(_prot_eff_T_2)
node _prot_eff_T_4 = eq(_prot_eff_T_3, asSInt(UInt<1>(0h0)))
node _prot_eff_T_5 = xor(mpu_physaddr[0], UInt<32>(0h80000000))
node _prot_eff_T_6 = cvt(_prot_eff_T_5)
node _prot_eff_T_7 = and(_prot_eff_T_6, asSInt(UInt<33>(0h80000000)))
node _prot_eff_T_8 = asSInt(_prot_eff_T_7)
node _prot_eff_T_9 = eq(_prot_eff_T_8, asSInt(UInt<1>(0h0)))
node _prot_eff_T_10 = or(_prot_eff_T_4, _prot_eff_T_9)
node _prot_eff_T_11 = xor(mpu_physaddr[0], UInt<17>(0h10000))
node _prot_eff_T_12 = cvt(_prot_eff_T_11)
node _prot_eff_T_13 = and(_prot_eff_T_12, asSInt(UInt<33>(0h80110000)))
node _prot_eff_T_14 = asSInt(_prot_eff_T_13)
node _prot_eff_T_15 = eq(_prot_eff_T_14, asSInt(UInt<1>(0h0)))
node _prot_eff_T_16 = xor(mpu_physaddr[0], UInt<21>(0h100000))
node _prot_eff_T_17 = cvt(_prot_eff_T_16)
node _prot_eff_T_18 = and(_prot_eff_T_17, asSInt(UInt<33>(0h80100000)))
node _prot_eff_T_19 = asSInt(_prot_eff_T_18)
node _prot_eff_T_20 = eq(_prot_eff_T_19, asSInt(UInt<1>(0h0)))
node _prot_eff_T_21 = or(_prot_eff_T_15, _prot_eff_T_20)
node _prot_eff_T_22 = mux(_prot_eff_T_10, UInt<1>(0h0), UInt<1>(0h0))
node _prot_eff_T_23 = mux(_prot_eff_T_21, UInt<1>(0h1), UInt<1>(0h0))
node _prot_eff_T_24 = or(_prot_eff_T_22, _prot_eff_T_23)
wire _prot_eff_WIRE : UInt<1>
connect _prot_eff_WIRE, _prot_eff_T_24
node _prot_eff_T_25 = and(legal_address[0], _prot_eff_WIRE)
wire prot_eff : UInt<1>[1]
connect prot_eff[0], _prot_eff_T_25
node _sector_hits_T = or(sectored_entries[0].valid[0], sectored_entries[0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0].tag, vpn[0])
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = and(_sector_hits_T_2, _sector_hits_T_5)
node _sector_hits_T_7 = or(sectored_entries[1].valid[0], sectored_entries[1].valid[1])
node _sector_hits_T_8 = or(_sector_hits_T_7, sectored_entries[1].valid[2])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[1].valid[3])
node _sector_hits_T_10 = xor(sectored_entries[1].tag, vpn[0])
node _sector_hits_T_11 = shr(_sector_hits_T_10, 2)
node _sector_hits_T_12 = eq(_sector_hits_T_11, UInt<1>(0h0))
node _sector_hits_T_13 = and(_sector_hits_T_9, _sector_hits_T_12)
node _sector_hits_T_14 = or(sectored_entries[2].valid[0], sectored_entries[2].valid[1])
node _sector_hits_T_15 = or(_sector_hits_T_14, sectored_entries[2].valid[2])
node _sector_hits_T_16 = or(_sector_hits_T_15, sectored_entries[2].valid[3])
node _sector_hits_T_17 = xor(sectored_entries[2].tag, vpn[0])
node _sector_hits_T_18 = shr(_sector_hits_T_17, 2)
node _sector_hits_T_19 = eq(_sector_hits_T_18, UInt<1>(0h0))
node _sector_hits_T_20 = and(_sector_hits_T_16, _sector_hits_T_19)
node _sector_hits_T_21 = or(sectored_entries[3].valid[0], sectored_entries[3].valid[1])
node _sector_hits_T_22 = or(_sector_hits_T_21, sectored_entries[3].valid[2])
node _sector_hits_T_23 = or(_sector_hits_T_22, sectored_entries[3].valid[3])
node _sector_hits_T_24 = xor(sectored_entries[3].tag, vpn[0])
node _sector_hits_T_25 = shr(_sector_hits_T_24, 2)
node _sector_hits_T_26 = eq(_sector_hits_T_25, UInt<1>(0h0))
node _sector_hits_T_27 = and(_sector_hits_T_23, _sector_hits_T_26)
node _sector_hits_T_28 = or(sectored_entries[4].valid[0], sectored_entries[4].valid[1])
node _sector_hits_T_29 = or(_sector_hits_T_28, sectored_entries[4].valid[2])
node _sector_hits_T_30 = or(_sector_hits_T_29, sectored_entries[4].valid[3])
node _sector_hits_T_31 = xor(sectored_entries[4].tag, vpn[0])
node _sector_hits_T_32 = shr(_sector_hits_T_31, 2)
node _sector_hits_T_33 = eq(_sector_hits_T_32, UInt<1>(0h0))
node _sector_hits_T_34 = and(_sector_hits_T_30, _sector_hits_T_33)
node _sector_hits_T_35 = or(sectored_entries[5].valid[0], sectored_entries[5].valid[1])
node _sector_hits_T_36 = or(_sector_hits_T_35, sectored_entries[5].valid[2])
node _sector_hits_T_37 = or(_sector_hits_T_36, sectored_entries[5].valid[3])
node _sector_hits_T_38 = xor(sectored_entries[5].tag, vpn[0])
node _sector_hits_T_39 = shr(_sector_hits_T_38, 2)
node _sector_hits_T_40 = eq(_sector_hits_T_39, UInt<1>(0h0))
node _sector_hits_T_41 = and(_sector_hits_T_37, _sector_hits_T_40)
node _sector_hits_T_42 = or(sectored_entries[6].valid[0], sectored_entries[6].valid[1])
node _sector_hits_T_43 = or(_sector_hits_T_42, sectored_entries[6].valid[2])
node _sector_hits_T_44 = or(_sector_hits_T_43, sectored_entries[6].valid[3])
node _sector_hits_T_45 = xor(sectored_entries[6].tag, vpn[0])
node _sector_hits_T_46 = shr(_sector_hits_T_45, 2)
node _sector_hits_T_47 = eq(_sector_hits_T_46, UInt<1>(0h0))
node _sector_hits_T_48 = and(_sector_hits_T_44, _sector_hits_T_47)
node _sector_hits_T_49 = or(sectored_entries[7].valid[0], sectored_entries[7].valid[1])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[7].valid[2])
node _sector_hits_T_51 = or(_sector_hits_T_50, sectored_entries[7].valid[3])
node _sector_hits_T_52 = xor(sectored_entries[7].tag, vpn[0])
node _sector_hits_T_53 = shr(_sector_hits_T_52, 2)
node _sector_hits_T_54 = eq(_sector_hits_T_53, UInt<1>(0h0))
node _sector_hits_T_55 = and(_sector_hits_T_51, _sector_hits_T_54)
wire _sector_hits_WIRE : UInt<1>[8]
connect _sector_hits_WIRE[0], _sector_hits_T_6
connect _sector_hits_WIRE[1], _sector_hits_T_13
connect _sector_hits_WIRE[2], _sector_hits_T_20
connect _sector_hits_WIRE[3], _sector_hits_T_27
connect _sector_hits_WIRE[4], _sector_hits_T_34
connect _sector_hits_WIRE[5], _sector_hits_T_41
connect _sector_hits_WIRE[6], _sector_hits_T_48
connect _sector_hits_WIRE[7], _sector_hits_T_55
wire sector_hits : UInt<1>[8][1]
connect sector_hits[0], _sector_hits_WIRE
node _superpage_hits_T = xor(superpage_entries[0].tag, vpn[0])
node _superpage_hits_T_1 = shr(_superpage_hits_T, 0)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = and(superpage_entries[0].valid[0], _superpage_hits_T_2)
node _superpage_hits_T_4 = xor(superpage_entries[1].tag, vpn[0])
node _superpage_hits_T_5 = shr(_superpage_hits_T_4, 0)
node _superpage_hits_T_6 = eq(_superpage_hits_T_5, UInt<1>(0h0))
node _superpage_hits_T_7 = and(superpage_entries[1].valid[0], _superpage_hits_T_6)
node _superpage_hits_T_8 = xor(superpage_entries[2].tag, vpn[0])
node _superpage_hits_T_9 = shr(_superpage_hits_T_8, 0)
node _superpage_hits_T_10 = eq(_superpage_hits_T_9, UInt<1>(0h0))
node _superpage_hits_T_11 = and(superpage_entries[2].valid[0], _superpage_hits_T_10)
node _superpage_hits_T_12 = xor(superpage_entries[3].tag, vpn[0])
node _superpage_hits_T_13 = shr(_superpage_hits_T_12, 0)
node _superpage_hits_T_14 = eq(_superpage_hits_T_13, UInt<1>(0h0))
node _superpage_hits_T_15 = and(superpage_entries[3].valid[0], _superpage_hits_T_14)
wire _superpage_hits_WIRE : UInt<1>[4]
connect _superpage_hits_WIRE[0], _superpage_hits_T_3
connect _superpage_hits_WIRE[1], _superpage_hits_T_7
connect _superpage_hits_WIRE[2], _superpage_hits_T_11
connect _superpage_hits_WIRE[3], _superpage_hits_T_15
wire superpage_hits : UInt<1>[4][1]
connect superpage_hits[0], _superpage_hits_WIRE
node hitsVec_idx = bits(vpn[0], 1, 0)
node _hitsVec_T = xor(sectored_entries[0].tag, vpn[0])
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = and(sectored_entries[0].valid[hitsVec_idx], _hitsVec_T_2)
node _hitsVec_T_4 = and(vm_enabled[0], _hitsVec_T_3)
node hitsVec_idx_1 = bits(vpn[0], 1, 0)
node _hitsVec_T_5 = xor(sectored_entries[1].tag, vpn[0])
node _hitsVec_T_6 = shr(_hitsVec_T_5, 2)
node _hitsVec_T_7 = eq(_hitsVec_T_6, UInt<1>(0h0))
node _hitsVec_T_8 = and(sectored_entries[1].valid[hitsVec_idx_1], _hitsVec_T_7)
node _hitsVec_T_9 = and(vm_enabled[0], _hitsVec_T_8)
node hitsVec_idx_2 = bits(vpn[0], 1, 0)
node _hitsVec_T_10 = xor(sectored_entries[2].tag, vpn[0])
node _hitsVec_T_11 = shr(_hitsVec_T_10, 2)
node _hitsVec_T_12 = eq(_hitsVec_T_11, UInt<1>(0h0))
node _hitsVec_T_13 = and(sectored_entries[2].valid[hitsVec_idx_2], _hitsVec_T_12)
node _hitsVec_T_14 = and(vm_enabled[0], _hitsVec_T_13)
node hitsVec_idx_3 = bits(vpn[0], 1, 0)
node _hitsVec_T_15 = xor(sectored_entries[3].tag, vpn[0])
node _hitsVec_T_16 = shr(_hitsVec_T_15, 2)
node _hitsVec_T_17 = eq(_hitsVec_T_16, UInt<1>(0h0))
node _hitsVec_T_18 = and(sectored_entries[3].valid[hitsVec_idx_3], _hitsVec_T_17)
node _hitsVec_T_19 = and(vm_enabled[0], _hitsVec_T_18)
node hitsVec_idx_4 = bits(vpn[0], 1, 0)
node _hitsVec_T_20 = xor(sectored_entries[4].tag, vpn[0])
node _hitsVec_T_21 = shr(_hitsVec_T_20, 2)
node _hitsVec_T_22 = eq(_hitsVec_T_21, UInt<1>(0h0))
node _hitsVec_T_23 = and(sectored_entries[4].valid[hitsVec_idx_4], _hitsVec_T_22)
node _hitsVec_T_24 = and(vm_enabled[0], _hitsVec_T_23)
node hitsVec_idx_5 = bits(vpn[0], 1, 0)
node _hitsVec_T_25 = xor(sectored_entries[5].tag, vpn[0])
node _hitsVec_T_26 = shr(_hitsVec_T_25, 2)
node _hitsVec_T_27 = eq(_hitsVec_T_26, UInt<1>(0h0))
node _hitsVec_T_28 = and(sectored_entries[5].valid[hitsVec_idx_5], _hitsVec_T_27)
node _hitsVec_T_29 = and(vm_enabled[0], _hitsVec_T_28)
node hitsVec_idx_6 = bits(vpn[0], 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[6].tag, vpn[0])
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = and(sectored_entries[6].valid[hitsVec_idx_6], _hitsVec_T_32)
node _hitsVec_T_34 = and(vm_enabled[0], _hitsVec_T_33)
node hitsVec_idx_7 = bits(vpn[0], 1, 0)
node _hitsVec_T_35 = xor(sectored_entries[7].tag, vpn[0])
node _hitsVec_T_36 = shr(_hitsVec_T_35, 2)
node _hitsVec_T_37 = eq(_hitsVec_T_36, UInt<1>(0h0))
node _hitsVec_T_38 = and(sectored_entries[7].valid[hitsVec_idx_7], _hitsVec_T_37)
node _hitsVec_T_39 = and(vm_enabled[0], _hitsVec_T_38)
node _hitsVec_T_40 = xor(superpage_entries[0].tag, vpn[0])
node _hitsVec_T_41 = shr(_hitsVec_T_40, 0)
node _hitsVec_T_42 = eq(_hitsVec_T_41, UInt<1>(0h0))
node _hitsVec_T_43 = and(superpage_entries[0].valid[0], _hitsVec_T_42)
node _hitsVec_T_44 = and(vm_enabled[0], _hitsVec_T_43)
node _hitsVec_T_45 = xor(superpage_entries[1].tag, vpn[0])
node _hitsVec_T_46 = shr(_hitsVec_T_45, 0)
node _hitsVec_T_47 = eq(_hitsVec_T_46, UInt<1>(0h0))
node _hitsVec_T_48 = and(superpage_entries[1].valid[0], _hitsVec_T_47)
node _hitsVec_T_49 = and(vm_enabled[0], _hitsVec_T_48)
node _hitsVec_T_50 = xor(superpage_entries[2].tag, vpn[0])
node _hitsVec_T_51 = shr(_hitsVec_T_50, 0)
node _hitsVec_T_52 = eq(_hitsVec_T_51, UInt<1>(0h0))
node _hitsVec_T_53 = and(superpage_entries[2].valid[0], _hitsVec_T_52)
node _hitsVec_T_54 = and(vm_enabled[0], _hitsVec_T_53)
node _hitsVec_T_55 = xor(superpage_entries[3].tag, vpn[0])
node _hitsVec_T_56 = shr(_hitsVec_T_55, 0)
node _hitsVec_T_57 = eq(_hitsVec_T_56, UInt<1>(0h0))
node _hitsVec_T_58 = and(superpage_entries[3].valid[0], _hitsVec_T_57)
node _hitsVec_T_59 = and(vm_enabled[0], _hitsVec_T_58)
node _hitsVec_T_60 = xor(special_entry.tag, vpn[0])
node _hitsVec_T_61 = shr(_hitsVec_T_60, 0)
node _hitsVec_T_62 = eq(_hitsVec_T_61, UInt<1>(0h0))
node _hitsVec_T_63 = and(special_entry.valid[0], _hitsVec_T_62)
node _hitsVec_T_64 = and(vm_enabled[0], _hitsVec_T_63)
wire _hitsVec_WIRE : UInt<1>[13]
connect _hitsVec_WIRE[0], _hitsVec_T_4
connect _hitsVec_WIRE[1], _hitsVec_T_9
connect _hitsVec_WIRE[2], _hitsVec_T_14
connect _hitsVec_WIRE[3], _hitsVec_T_19
connect _hitsVec_WIRE[4], _hitsVec_T_24
connect _hitsVec_WIRE[5], _hitsVec_T_29
connect _hitsVec_WIRE[6], _hitsVec_T_34
connect _hitsVec_WIRE[7], _hitsVec_T_39
connect _hitsVec_WIRE[8], _hitsVec_T_44
connect _hitsVec_WIRE[9], _hitsVec_T_49
connect _hitsVec_WIRE[10], _hitsVec_T_54
connect _hitsVec_WIRE[11], _hitsVec_T_59
connect _hitsVec_WIRE[12], _hitsVec_T_64
wire hitsVec : UInt<1>[13][1]
connect hitsVec[0], _hitsVec_WIRE
node real_hits_lo_lo_hi = cat(hitsVec[0][2], hitsVec[0][1])
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec[0][0])
node real_hits_lo_hi_hi = cat(hitsVec[0][5], hitsVec[0][4])
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec[0][3])
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec[0][8], hitsVec[0][7])
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec[0][6])
node real_hits_hi_hi_lo = cat(hitsVec[0][10], hitsVec[0][9])
node real_hits_hi_hi_hi = cat(hitsVec[0][12], hitsVec[0][11])
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node _real_hits_T = cat(real_hits_hi, real_hits_lo)
wire real_hits : UInt<13>[1]
connect real_hits[0], _real_hits_T
node _hits_T = eq(vm_enabled[0], UInt<1>(0h0))
node _hits_T_1 = cat(_hits_T, real_hits[0])
wire hits : UInt<14>[1]
connect hits[0], _hits_T_1
node _ppn_T = eq(vm_enabled[0], UInt<1>(0h0))
node _ppn_data_T = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_1 : UInt<34>
connect _ppn_data_WIRE_1, sectored_entries[0].data[_ppn_data_T]
node _ppn_data_T_1 = bits(_ppn_data_WIRE_1, 0, 0)
connect _ppn_data_WIRE.fragmented_superpage, _ppn_data_T_1
node _ppn_data_T_2 = bits(_ppn_data_WIRE_1, 1, 1)
connect _ppn_data_WIRE.c, _ppn_data_T_2
node _ppn_data_T_3 = bits(_ppn_data_WIRE_1, 2, 2)
connect _ppn_data_WIRE.eff, _ppn_data_T_3
node _ppn_data_T_4 = bits(_ppn_data_WIRE_1, 3, 3)
connect _ppn_data_WIRE.paa, _ppn_data_T_4
node _ppn_data_T_5 = bits(_ppn_data_WIRE_1, 4, 4)
connect _ppn_data_WIRE.pal, _ppn_data_T_5
node _ppn_data_T_6 = bits(_ppn_data_WIRE_1, 5, 5)
connect _ppn_data_WIRE.pr, _ppn_data_T_6
node _ppn_data_T_7 = bits(_ppn_data_WIRE_1, 6, 6)
connect _ppn_data_WIRE.px, _ppn_data_T_7
node _ppn_data_T_8 = bits(_ppn_data_WIRE_1, 7, 7)
connect _ppn_data_WIRE.pw, _ppn_data_T_8
node _ppn_data_T_9 = bits(_ppn_data_WIRE_1, 8, 8)
connect _ppn_data_WIRE.sr, _ppn_data_T_9
node _ppn_data_T_10 = bits(_ppn_data_WIRE_1, 9, 9)
connect _ppn_data_WIRE.sx, _ppn_data_T_10
node _ppn_data_T_11 = bits(_ppn_data_WIRE_1, 10, 10)
connect _ppn_data_WIRE.sw, _ppn_data_T_11
node _ppn_data_T_12 = bits(_ppn_data_WIRE_1, 11, 11)
connect _ppn_data_WIRE.ae, _ppn_data_T_12
node _ppn_data_T_13 = bits(_ppn_data_WIRE_1, 12, 12)
connect _ppn_data_WIRE.g, _ppn_data_T_13
node _ppn_data_T_14 = bits(_ppn_data_WIRE_1, 13, 13)
connect _ppn_data_WIRE.u, _ppn_data_T_14
node _ppn_data_T_15 = bits(_ppn_data_WIRE_1, 33, 14)
connect _ppn_data_WIRE.ppn, _ppn_data_T_15
inst ppn_data_barrier of OptimizationBarrier_EntryData_40
connect ppn_data_barrier.clock, clock
connect ppn_data_barrier.reset, reset
connect ppn_data_barrier.io.x.fragmented_superpage, _ppn_data_WIRE.fragmented_superpage
connect ppn_data_barrier.io.x.c, _ppn_data_WIRE.c
connect ppn_data_barrier.io.x.eff, _ppn_data_WIRE.eff
connect ppn_data_barrier.io.x.paa, _ppn_data_WIRE.paa
connect ppn_data_barrier.io.x.pal, _ppn_data_WIRE.pal
connect ppn_data_barrier.io.x.pr, _ppn_data_WIRE.pr
connect ppn_data_barrier.io.x.px, _ppn_data_WIRE.px
connect ppn_data_barrier.io.x.pw, _ppn_data_WIRE.pw
connect ppn_data_barrier.io.x.sr, _ppn_data_WIRE.sr
connect ppn_data_barrier.io.x.sx, _ppn_data_WIRE.sx
connect ppn_data_barrier.io.x.sw, _ppn_data_WIRE.sw
connect ppn_data_barrier.io.x.ae, _ppn_data_WIRE.ae
connect ppn_data_barrier.io.x.g, _ppn_data_WIRE.g
connect ppn_data_barrier.io.x.u, _ppn_data_WIRE.u
connect ppn_data_barrier.io.x.ppn, _ppn_data_WIRE.ppn
node _ppn_data_T_16 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_3 : UInt<34>
connect _ppn_data_WIRE_3, sectored_entries[1].data[_ppn_data_T_16]
node _ppn_data_T_17 = bits(_ppn_data_WIRE_3, 0, 0)
connect _ppn_data_WIRE_2.fragmented_superpage, _ppn_data_T_17
node _ppn_data_T_18 = bits(_ppn_data_WIRE_3, 1, 1)
connect _ppn_data_WIRE_2.c, _ppn_data_T_18
node _ppn_data_T_19 = bits(_ppn_data_WIRE_3, 2, 2)
connect _ppn_data_WIRE_2.eff, _ppn_data_T_19
node _ppn_data_T_20 = bits(_ppn_data_WIRE_3, 3, 3)
connect _ppn_data_WIRE_2.paa, _ppn_data_T_20
node _ppn_data_T_21 = bits(_ppn_data_WIRE_3, 4, 4)
connect _ppn_data_WIRE_2.pal, _ppn_data_T_21
node _ppn_data_T_22 = bits(_ppn_data_WIRE_3, 5, 5)
connect _ppn_data_WIRE_2.pr, _ppn_data_T_22
node _ppn_data_T_23 = bits(_ppn_data_WIRE_3, 6, 6)
connect _ppn_data_WIRE_2.px, _ppn_data_T_23
node _ppn_data_T_24 = bits(_ppn_data_WIRE_3, 7, 7)
connect _ppn_data_WIRE_2.pw, _ppn_data_T_24
node _ppn_data_T_25 = bits(_ppn_data_WIRE_3, 8, 8)
connect _ppn_data_WIRE_2.sr, _ppn_data_T_25
node _ppn_data_T_26 = bits(_ppn_data_WIRE_3, 9, 9)
connect _ppn_data_WIRE_2.sx, _ppn_data_T_26
node _ppn_data_T_27 = bits(_ppn_data_WIRE_3, 10, 10)
connect _ppn_data_WIRE_2.sw, _ppn_data_T_27
node _ppn_data_T_28 = bits(_ppn_data_WIRE_3, 11, 11)
connect _ppn_data_WIRE_2.ae, _ppn_data_T_28
node _ppn_data_T_29 = bits(_ppn_data_WIRE_3, 12, 12)
connect _ppn_data_WIRE_2.g, _ppn_data_T_29
node _ppn_data_T_30 = bits(_ppn_data_WIRE_3, 13, 13)
connect _ppn_data_WIRE_2.u, _ppn_data_T_30
node _ppn_data_T_31 = bits(_ppn_data_WIRE_3, 33, 14)
connect _ppn_data_WIRE_2.ppn, _ppn_data_T_31
inst ppn_data_barrier_1 of OptimizationBarrier_EntryData_41
connect ppn_data_barrier_1.clock, clock
connect ppn_data_barrier_1.reset, reset
connect ppn_data_barrier_1.io.x.fragmented_superpage, _ppn_data_WIRE_2.fragmented_superpage
connect ppn_data_barrier_1.io.x.c, _ppn_data_WIRE_2.c
connect ppn_data_barrier_1.io.x.eff, _ppn_data_WIRE_2.eff
connect ppn_data_barrier_1.io.x.paa, _ppn_data_WIRE_2.paa
connect ppn_data_barrier_1.io.x.pal, _ppn_data_WIRE_2.pal
connect ppn_data_barrier_1.io.x.pr, _ppn_data_WIRE_2.pr
connect ppn_data_barrier_1.io.x.px, _ppn_data_WIRE_2.px
connect ppn_data_barrier_1.io.x.pw, _ppn_data_WIRE_2.pw
connect ppn_data_barrier_1.io.x.sr, _ppn_data_WIRE_2.sr
connect ppn_data_barrier_1.io.x.sx, _ppn_data_WIRE_2.sx
connect ppn_data_barrier_1.io.x.sw, _ppn_data_WIRE_2.sw
connect ppn_data_barrier_1.io.x.ae, _ppn_data_WIRE_2.ae
connect ppn_data_barrier_1.io.x.g, _ppn_data_WIRE_2.g
connect ppn_data_barrier_1.io.x.u, _ppn_data_WIRE_2.u
connect ppn_data_barrier_1.io.x.ppn, _ppn_data_WIRE_2.ppn
node _ppn_data_T_32 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_5 : UInt<34>
connect _ppn_data_WIRE_5, sectored_entries[2].data[_ppn_data_T_32]
node _ppn_data_T_33 = bits(_ppn_data_WIRE_5, 0, 0)
connect _ppn_data_WIRE_4.fragmented_superpage, _ppn_data_T_33
node _ppn_data_T_34 = bits(_ppn_data_WIRE_5, 1, 1)
connect _ppn_data_WIRE_4.c, _ppn_data_T_34
node _ppn_data_T_35 = bits(_ppn_data_WIRE_5, 2, 2)
connect _ppn_data_WIRE_4.eff, _ppn_data_T_35
node _ppn_data_T_36 = bits(_ppn_data_WIRE_5, 3, 3)
connect _ppn_data_WIRE_4.paa, _ppn_data_T_36
node _ppn_data_T_37 = bits(_ppn_data_WIRE_5, 4, 4)
connect _ppn_data_WIRE_4.pal, _ppn_data_T_37
node _ppn_data_T_38 = bits(_ppn_data_WIRE_5, 5, 5)
connect _ppn_data_WIRE_4.pr, _ppn_data_T_38
node _ppn_data_T_39 = bits(_ppn_data_WIRE_5, 6, 6)
connect _ppn_data_WIRE_4.px, _ppn_data_T_39
node _ppn_data_T_40 = bits(_ppn_data_WIRE_5, 7, 7)
connect _ppn_data_WIRE_4.pw, _ppn_data_T_40
node _ppn_data_T_41 = bits(_ppn_data_WIRE_5, 8, 8)
connect _ppn_data_WIRE_4.sr, _ppn_data_T_41
node _ppn_data_T_42 = bits(_ppn_data_WIRE_5, 9, 9)
connect _ppn_data_WIRE_4.sx, _ppn_data_T_42
node _ppn_data_T_43 = bits(_ppn_data_WIRE_5, 10, 10)
connect _ppn_data_WIRE_4.sw, _ppn_data_T_43
node _ppn_data_T_44 = bits(_ppn_data_WIRE_5, 11, 11)
connect _ppn_data_WIRE_4.ae, _ppn_data_T_44
node _ppn_data_T_45 = bits(_ppn_data_WIRE_5, 12, 12)
connect _ppn_data_WIRE_4.g, _ppn_data_T_45
node _ppn_data_T_46 = bits(_ppn_data_WIRE_5, 13, 13)
connect _ppn_data_WIRE_4.u, _ppn_data_T_46
node _ppn_data_T_47 = bits(_ppn_data_WIRE_5, 33, 14)
connect _ppn_data_WIRE_4.ppn, _ppn_data_T_47
inst ppn_data_barrier_2 of OptimizationBarrier_EntryData_42
connect ppn_data_barrier_2.clock, clock
connect ppn_data_barrier_2.reset, reset
connect ppn_data_barrier_2.io.x.fragmented_superpage, _ppn_data_WIRE_4.fragmented_superpage
connect ppn_data_barrier_2.io.x.c, _ppn_data_WIRE_4.c
connect ppn_data_barrier_2.io.x.eff, _ppn_data_WIRE_4.eff
connect ppn_data_barrier_2.io.x.paa, _ppn_data_WIRE_4.paa
connect ppn_data_barrier_2.io.x.pal, _ppn_data_WIRE_4.pal
connect ppn_data_barrier_2.io.x.pr, _ppn_data_WIRE_4.pr
connect ppn_data_barrier_2.io.x.px, _ppn_data_WIRE_4.px
connect ppn_data_barrier_2.io.x.pw, _ppn_data_WIRE_4.pw
connect ppn_data_barrier_2.io.x.sr, _ppn_data_WIRE_4.sr
connect ppn_data_barrier_2.io.x.sx, _ppn_data_WIRE_4.sx
connect ppn_data_barrier_2.io.x.sw, _ppn_data_WIRE_4.sw
connect ppn_data_barrier_2.io.x.ae, _ppn_data_WIRE_4.ae
connect ppn_data_barrier_2.io.x.g, _ppn_data_WIRE_4.g
connect ppn_data_barrier_2.io.x.u, _ppn_data_WIRE_4.u
connect ppn_data_barrier_2.io.x.ppn, _ppn_data_WIRE_4.ppn
node _ppn_data_T_48 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_7 : UInt<34>
connect _ppn_data_WIRE_7, sectored_entries[3].data[_ppn_data_T_48]
node _ppn_data_T_49 = bits(_ppn_data_WIRE_7, 0, 0)
connect _ppn_data_WIRE_6.fragmented_superpage, _ppn_data_T_49
node _ppn_data_T_50 = bits(_ppn_data_WIRE_7, 1, 1)
connect _ppn_data_WIRE_6.c, _ppn_data_T_50
node _ppn_data_T_51 = bits(_ppn_data_WIRE_7, 2, 2)
connect _ppn_data_WIRE_6.eff, _ppn_data_T_51
node _ppn_data_T_52 = bits(_ppn_data_WIRE_7, 3, 3)
connect _ppn_data_WIRE_6.paa, _ppn_data_T_52
node _ppn_data_T_53 = bits(_ppn_data_WIRE_7, 4, 4)
connect _ppn_data_WIRE_6.pal, _ppn_data_T_53
node _ppn_data_T_54 = bits(_ppn_data_WIRE_7, 5, 5)
connect _ppn_data_WIRE_6.pr, _ppn_data_T_54
node _ppn_data_T_55 = bits(_ppn_data_WIRE_7, 6, 6)
connect _ppn_data_WIRE_6.px, _ppn_data_T_55
node _ppn_data_T_56 = bits(_ppn_data_WIRE_7, 7, 7)
connect _ppn_data_WIRE_6.pw, _ppn_data_T_56
node _ppn_data_T_57 = bits(_ppn_data_WIRE_7, 8, 8)
connect _ppn_data_WIRE_6.sr, _ppn_data_T_57
node _ppn_data_T_58 = bits(_ppn_data_WIRE_7, 9, 9)
connect _ppn_data_WIRE_6.sx, _ppn_data_T_58
node _ppn_data_T_59 = bits(_ppn_data_WIRE_7, 10, 10)
connect _ppn_data_WIRE_6.sw, _ppn_data_T_59
node _ppn_data_T_60 = bits(_ppn_data_WIRE_7, 11, 11)
connect _ppn_data_WIRE_6.ae, _ppn_data_T_60
node _ppn_data_T_61 = bits(_ppn_data_WIRE_7, 12, 12)
connect _ppn_data_WIRE_6.g, _ppn_data_T_61
node _ppn_data_T_62 = bits(_ppn_data_WIRE_7, 13, 13)
connect _ppn_data_WIRE_6.u, _ppn_data_T_62
node _ppn_data_T_63 = bits(_ppn_data_WIRE_7, 33, 14)
connect _ppn_data_WIRE_6.ppn, _ppn_data_T_63
inst ppn_data_barrier_3 of OptimizationBarrier_EntryData_43
connect ppn_data_barrier_3.clock, clock
connect ppn_data_barrier_3.reset, reset
connect ppn_data_barrier_3.io.x.fragmented_superpage, _ppn_data_WIRE_6.fragmented_superpage
connect ppn_data_barrier_3.io.x.c, _ppn_data_WIRE_6.c
connect ppn_data_barrier_3.io.x.eff, _ppn_data_WIRE_6.eff
connect ppn_data_barrier_3.io.x.paa, _ppn_data_WIRE_6.paa
connect ppn_data_barrier_3.io.x.pal, _ppn_data_WIRE_6.pal
connect ppn_data_barrier_3.io.x.pr, _ppn_data_WIRE_6.pr
connect ppn_data_barrier_3.io.x.px, _ppn_data_WIRE_6.px
connect ppn_data_barrier_3.io.x.pw, _ppn_data_WIRE_6.pw
connect ppn_data_barrier_3.io.x.sr, _ppn_data_WIRE_6.sr
connect ppn_data_barrier_3.io.x.sx, _ppn_data_WIRE_6.sx
connect ppn_data_barrier_3.io.x.sw, _ppn_data_WIRE_6.sw
connect ppn_data_barrier_3.io.x.ae, _ppn_data_WIRE_6.ae
connect ppn_data_barrier_3.io.x.g, _ppn_data_WIRE_6.g
connect ppn_data_barrier_3.io.x.u, _ppn_data_WIRE_6.u
connect ppn_data_barrier_3.io.x.ppn, _ppn_data_WIRE_6.ppn
node _ppn_data_T_64 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_9 : UInt<34>
connect _ppn_data_WIRE_9, sectored_entries[4].data[_ppn_data_T_64]
node _ppn_data_T_65 = bits(_ppn_data_WIRE_9, 0, 0)
connect _ppn_data_WIRE_8.fragmented_superpage, _ppn_data_T_65
node _ppn_data_T_66 = bits(_ppn_data_WIRE_9, 1, 1)
connect _ppn_data_WIRE_8.c, _ppn_data_T_66
node _ppn_data_T_67 = bits(_ppn_data_WIRE_9, 2, 2)
connect _ppn_data_WIRE_8.eff, _ppn_data_T_67
node _ppn_data_T_68 = bits(_ppn_data_WIRE_9, 3, 3)
connect _ppn_data_WIRE_8.paa, _ppn_data_T_68
node _ppn_data_T_69 = bits(_ppn_data_WIRE_9, 4, 4)
connect _ppn_data_WIRE_8.pal, _ppn_data_T_69
node _ppn_data_T_70 = bits(_ppn_data_WIRE_9, 5, 5)
connect _ppn_data_WIRE_8.pr, _ppn_data_T_70
node _ppn_data_T_71 = bits(_ppn_data_WIRE_9, 6, 6)
connect _ppn_data_WIRE_8.px, _ppn_data_T_71
node _ppn_data_T_72 = bits(_ppn_data_WIRE_9, 7, 7)
connect _ppn_data_WIRE_8.pw, _ppn_data_T_72
node _ppn_data_T_73 = bits(_ppn_data_WIRE_9, 8, 8)
connect _ppn_data_WIRE_8.sr, _ppn_data_T_73
node _ppn_data_T_74 = bits(_ppn_data_WIRE_9, 9, 9)
connect _ppn_data_WIRE_8.sx, _ppn_data_T_74
node _ppn_data_T_75 = bits(_ppn_data_WIRE_9, 10, 10)
connect _ppn_data_WIRE_8.sw, _ppn_data_T_75
node _ppn_data_T_76 = bits(_ppn_data_WIRE_9, 11, 11)
connect _ppn_data_WIRE_8.ae, _ppn_data_T_76
node _ppn_data_T_77 = bits(_ppn_data_WIRE_9, 12, 12)
connect _ppn_data_WIRE_8.g, _ppn_data_T_77
node _ppn_data_T_78 = bits(_ppn_data_WIRE_9, 13, 13)
connect _ppn_data_WIRE_8.u, _ppn_data_T_78
node _ppn_data_T_79 = bits(_ppn_data_WIRE_9, 33, 14)
connect _ppn_data_WIRE_8.ppn, _ppn_data_T_79
inst ppn_data_barrier_4 of OptimizationBarrier_EntryData_44
connect ppn_data_barrier_4.clock, clock
connect ppn_data_barrier_4.reset, reset
connect ppn_data_barrier_4.io.x.fragmented_superpage, _ppn_data_WIRE_8.fragmented_superpage
connect ppn_data_barrier_4.io.x.c, _ppn_data_WIRE_8.c
connect ppn_data_barrier_4.io.x.eff, _ppn_data_WIRE_8.eff
connect ppn_data_barrier_4.io.x.paa, _ppn_data_WIRE_8.paa
connect ppn_data_barrier_4.io.x.pal, _ppn_data_WIRE_8.pal
connect ppn_data_barrier_4.io.x.pr, _ppn_data_WIRE_8.pr
connect ppn_data_barrier_4.io.x.px, _ppn_data_WIRE_8.px
connect ppn_data_barrier_4.io.x.pw, _ppn_data_WIRE_8.pw
connect ppn_data_barrier_4.io.x.sr, _ppn_data_WIRE_8.sr
connect ppn_data_barrier_4.io.x.sx, _ppn_data_WIRE_8.sx
connect ppn_data_barrier_4.io.x.sw, _ppn_data_WIRE_8.sw
connect ppn_data_barrier_4.io.x.ae, _ppn_data_WIRE_8.ae
connect ppn_data_barrier_4.io.x.g, _ppn_data_WIRE_8.g
connect ppn_data_barrier_4.io.x.u, _ppn_data_WIRE_8.u
connect ppn_data_barrier_4.io.x.ppn, _ppn_data_WIRE_8.ppn
node _ppn_data_T_80 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_11 : UInt<34>
connect _ppn_data_WIRE_11, sectored_entries[5].data[_ppn_data_T_80]
node _ppn_data_T_81 = bits(_ppn_data_WIRE_11, 0, 0)
connect _ppn_data_WIRE_10.fragmented_superpage, _ppn_data_T_81
node _ppn_data_T_82 = bits(_ppn_data_WIRE_11, 1, 1)
connect _ppn_data_WIRE_10.c, _ppn_data_T_82
node _ppn_data_T_83 = bits(_ppn_data_WIRE_11, 2, 2)
connect _ppn_data_WIRE_10.eff, _ppn_data_T_83
node _ppn_data_T_84 = bits(_ppn_data_WIRE_11, 3, 3)
connect _ppn_data_WIRE_10.paa, _ppn_data_T_84
node _ppn_data_T_85 = bits(_ppn_data_WIRE_11, 4, 4)
connect _ppn_data_WIRE_10.pal, _ppn_data_T_85
node _ppn_data_T_86 = bits(_ppn_data_WIRE_11, 5, 5)
connect _ppn_data_WIRE_10.pr, _ppn_data_T_86
node _ppn_data_T_87 = bits(_ppn_data_WIRE_11, 6, 6)
connect _ppn_data_WIRE_10.px, _ppn_data_T_87
node _ppn_data_T_88 = bits(_ppn_data_WIRE_11, 7, 7)
connect _ppn_data_WIRE_10.pw, _ppn_data_T_88
node _ppn_data_T_89 = bits(_ppn_data_WIRE_11, 8, 8)
connect _ppn_data_WIRE_10.sr, _ppn_data_T_89
node _ppn_data_T_90 = bits(_ppn_data_WIRE_11, 9, 9)
connect _ppn_data_WIRE_10.sx, _ppn_data_T_90
node _ppn_data_T_91 = bits(_ppn_data_WIRE_11, 10, 10)
connect _ppn_data_WIRE_10.sw, _ppn_data_T_91
node _ppn_data_T_92 = bits(_ppn_data_WIRE_11, 11, 11)
connect _ppn_data_WIRE_10.ae, _ppn_data_T_92
node _ppn_data_T_93 = bits(_ppn_data_WIRE_11, 12, 12)
connect _ppn_data_WIRE_10.g, _ppn_data_T_93
node _ppn_data_T_94 = bits(_ppn_data_WIRE_11, 13, 13)
connect _ppn_data_WIRE_10.u, _ppn_data_T_94
node _ppn_data_T_95 = bits(_ppn_data_WIRE_11, 33, 14)
connect _ppn_data_WIRE_10.ppn, _ppn_data_T_95
inst ppn_data_barrier_5 of OptimizationBarrier_EntryData_45
connect ppn_data_barrier_5.clock, clock
connect ppn_data_barrier_5.reset, reset
connect ppn_data_barrier_5.io.x.fragmented_superpage, _ppn_data_WIRE_10.fragmented_superpage
connect ppn_data_barrier_5.io.x.c, _ppn_data_WIRE_10.c
connect ppn_data_barrier_5.io.x.eff, _ppn_data_WIRE_10.eff
connect ppn_data_barrier_5.io.x.paa, _ppn_data_WIRE_10.paa
connect ppn_data_barrier_5.io.x.pal, _ppn_data_WIRE_10.pal
connect ppn_data_barrier_5.io.x.pr, _ppn_data_WIRE_10.pr
connect ppn_data_barrier_5.io.x.px, _ppn_data_WIRE_10.px
connect ppn_data_barrier_5.io.x.pw, _ppn_data_WIRE_10.pw
connect ppn_data_barrier_5.io.x.sr, _ppn_data_WIRE_10.sr
connect ppn_data_barrier_5.io.x.sx, _ppn_data_WIRE_10.sx
connect ppn_data_barrier_5.io.x.sw, _ppn_data_WIRE_10.sw
connect ppn_data_barrier_5.io.x.ae, _ppn_data_WIRE_10.ae
connect ppn_data_barrier_5.io.x.g, _ppn_data_WIRE_10.g
connect ppn_data_barrier_5.io.x.u, _ppn_data_WIRE_10.u
connect ppn_data_barrier_5.io.x.ppn, _ppn_data_WIRE_10.ppn
node _ppn_data_T_96 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_13 : UInt<34>
connect _ppn_data_WIRE_13, sectored_entries[6].data[_ppn_data_T_96]
node _ppn_data_T_97 = bits(_ppn_data_WIRE_13, 0, 0)
connect _ppn_data_WIRE_12.fragmented_superpage, _ppn_data_T_97
node _ppn_data_T_98 = bits(_ppn_data_WIRE_13, 1, 1)
connect _ppn_data_WIRE_12.c, _ppn_data_T_98
node _ppn_data_T_99 = bits(_ppn_data_WIRE_13, 2, 2)
connect _ppn_data_WIRE_12.eff, _ppn_data_T_99
node _ppn_data_T_100 = bits(_ppn_data_WIRE_13, 3, 3)
connect _ppn_data_WIRE_12.paa, _ppn_data_T_100
node _ppn_data_T_101 = bits(_ppn_data_WIRE_13, 4, 4)
connect _ppn_data_WIRE_12.pal, _ppn_data_T_101
node _ppn_data_T_102 = bits(_ppn_data_WIRE_13, 5, 5)
connect _ppn_data_WIRE_12.pr, _ppn_data_T_102
node _ppn_data_T_103 = bits(_ppn_data_WIRE_13, 6, 6)
connect _ppn_data_WIRE_12.px, _ppn_data_T_103
node _ppn_data_T_104 = bits(_ppn_data_WIRE_13, 7, 7)
connect _ppn_data_WIRE_12.pw, _ppn_data_T_104
node _ppn_data_T_105 = bits(_ppn_data_WIRE_13, 8, 8)
connect _ppn_data_WIRE_12.sr, _ppn_data_T_105
node _ppn_data_T_106 = bits(_ppn_data_WIRE_13, 9, 9)
connect _ppn_data_WIRE_12.sx, _ppn_data_T_106
node _ppn_data_T_107 = bits(_ppn_data_WIRE_13, 10, 10)
connect _ppn_data_WIRE_12.sw, _ppn_data_T_107
node _ppn_data_T_108 = bits(_ppn_data_WIRE_13, 11, 11)
connect _ppn_data_WIRE_12.ae, _ppn_data_T_108
node _ppn_data_T_109 = bits(_ppn_data_WIRE_13, 12, 12)
connect _ppn_data_WIRE_12.g, _ppn_data_T_109
node _ppn_data_T_110 = bits(_ppn_data_WIRE_13, 13, 13)
connect _ppn_data_WIRE_12.u, _ppn_data_T_110
node _ppn_data_T_111 = bits(_ppn_data_WIRE_13, 33, 14)
connect _ppn_data_WIRE_12.ppn, _ppn_data_T_111
inst ppn_data_barrier_6 of OptimizationBarrier_EntryData_46
connect ppn_data_barrier_6.clock, clock
connect ppn_data_barrier_6.reset, reset
connect ppn_data_barrier_6.io.x.fragmented_superpage, _ppn_data_WIRE_12.fragmented_superpage
connect ppn_data_barrier_6.io.x.c, _ppn_data_WIRE_12.c
connect ppn_data_barrier_6.io.x.eff, _ppn_data_WIRE_12.eff
connect ppn_data_barrier_6.io.x.paa, _ppn_data_WIRE_12.paa
connect ppn_data_barrier_6.io.x.pal, _ppn_data_WIRE_12.pal
connect ppn_data_barrier_6.io.x.pr, _ppn_data_WIRE_12.pr
connect ppn_data_barrier_6.io.x.px, _ppn_data_WIRE_12.px
connect ppn_data_barrier_6.io.x.pw, _ppn_data_WIRE_12.pw
connect ppn_data_barrier_6.io.x.sr, _ppn_data_WIRE_12.sr
connect ppn_data_barrier_6.io.x.sx, _ppn_data_WIRE_12.sx
connect ppn_data_barrier_6.io.x.sw, _ppn_data_WIRE_12.sw
connect ppn_data_barrier_6.io.x.ae, _ppn_data_WIRE_12.ae
connect ppn_data_barrier_6.io.x.g, _ppn_data_WIRE_12.g
connect ppn_data_barrier_6.io.x.u, _ppn_data_WIRE_12.u
connect ppn_data_barrier_6.io.x.ppn, _ppn_data_WIRE_12.ppn
node _ppn_data_T_112 = bits(vpn[0], 1, 0)
wire _ppn_data_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_15 : UInt<34>
connect _ppn_data_WIRE_15, sectored_entries[7].data[_ppn_data_T_112]
node _ppn_data_T_113 = bits(_ppn_data_WIRE_15, 0, 0)
connect _ppn_data_WIRE_14.fragmented_superpage, _ppn_data_T_113
node _ppn_data_T_114 = bits(_ppn_data_WIRE_15, 1, 1)
connect _ppn_data_WIRE_14.c, _ppn_data_T_114
node _ppn_data_T_115 = bits(_ppn_data_WIRE_15, 2, 2)
connect _ppn_data_WIRE_14.eff, _ppn_data_T_115
node _ppn_data_T_116 = bits(_ppn_data_WIRE_15, 3, 3)
connect _ppn_data_WIRE_14.paa, _ppn_data_T_116
node _ppn_data_T_117 = bits(_ppn_data_WIRE_15, 4, 4)
connect _ppn_data_WIRE_14.pal, _ppn_data_T_117
node _ppn_data_T_118 = bits(_ppn_data_WIRE_15, 5, 5)
connect _ppn_data_WIRE_14.pr, _ppn_data_T_118
node _ppn_data_T_119 = bits(_ppn_data_WIRE_15, 6, 6)
connect _ppn_data_WIRE_14.px, _ppn_data_T_119
node _ppn_data_T_120 = bits(_ppn_data_WIRE_15, 7, 7)
connect _ppn_data_WIRE_14.pw, _ppn_data_T_120
node _ppn_data_T_121 = bits(_ppn_data_WIRE_15, 8, 8)
connect _ppn_data_WIRE_14.sr, _ppn_data_T_121
node _ppn_data_T_122 = bits(_ppn_data_WIRE_15, 9, 9)
connect _ppn_data_WIRE_14.sx, _ppn_data_T_122
node _ppn_data_T_123 = bits(_ppn_data_WIRE_15, 10, 10)
connect _ppn_data_WIRE_14.sw, _ppn_data_T_123
node _ppn_data_T_124 = bits(_ppn_data_WIRE_15, 11, 11)
connect _ppn_data_WIRE_14.ae, _ppn_data_T_124
node _ppn_data_T_125 = bits(_ppn_data_WIRE_15, 12, 12)
connect _ppn_data_WIRE_14.g, _ppn_data_T_125
node _ppn_data_T_126 = bits(_ppn_data_WIRE_15, 13, 13)
connect _ppn_data_WIRE_14.u, _ppn_data_T_126
node _ppn_data_T_127 = bits(_ppn_data_WIRE_15, 33, 14)
connect _ppn_data_WIRE_14.ppn, _ppn_data_T_127
inst ppn_data_barrier_7 of OptimizationBarrier_EntryData_47
connect ppn_data_barrier_7.clock, clock
connect ppn_data_barrier_7.reset, reset
connect ppn_data_barrier_7.io.x.fragmented_superpage, _ppn_data_WIRE_14.fragmented_superpage
connect ppn_data_barrier_7.io.x.c, _ppn_data_WIRE_14.c
connect ppn_data_barrier_7.io.x.eff, _ppn_data_WIRE_14.eff
connect ppn_data_barrier_7.io.x.paa, _ppn_data_WIRE_14.paa
connect ppn_data_barrier_7.io.x.pal, _ppn_data_WIRE_14.pal
connect ppn_data_barrier_7.io.x.pr, _ppn_data_WIRE_14.pr
connect ppn_data_barrier_7.io.x.px, _ppn_data_WIRE_14.px
connect ppn_data_barrier_7.io.x.pw, _ppn_data_WIRE_14.pw
connect ppn_data_barrier_7.io.x.sr, _ppn_data_WIRE_14.sr
connect ppn_data_barrier_7.io.x.sx, _ppn_data_WIRE_14.sx
connect ppn_data_barrier_7.io.x.sw, _ppn_data_WIRE_14.sw
connect ppn_data_barrier_7.io.x.ae, _ppn_data_WIRE_14.ae
connect ppn_data_barrier_7.io.x.g, _ppn_data_WIRE_14.g
connect ppn_data_barrier_7.io.x.u, _ppn_data_WIRE_14.u
connect ppn_data_barrier_7.io.x.ppn, _ppn_data_WIRE_14.ppn
wire _ppn_data_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_17 : UInt<34>
connect _ppn_data_WIRE_17, superpage_entries[0].data[0]
node _ppn_data_T_128 = bits(_ppn_data_WIRE_17, 0, 0)
connect _ppn_data_WIRE_16.fragmented_superpage, _ppn_data_T_128
node _ppn_data_T_129 = bits(_ppn_data_WIRE_17, 1, 1)
connect _ppn_data_WIRE_16.c, _ppn_data_T_129
node _ppn_data_T_130 = bits(_ppn_data_WIRE_17, 2, 2)
connect _ppn_data_WIRE_16.eff, _ppn_data_T_130
node _ppn_data_T_131 = bits(_ppn_data_WIRE_17, 3, 3)
connect _ppn_data_WIRE_16.paa, _ppn_data_T_131
node _ppn_data_T_132 = bits(_ppn_data_WIRE_17, 4, 4)
connect _ppn_data_WIRE_16.pal, _ppn_data_T_132
node _ppn_data_T_133 = bits(_ppn_data_WIRE_17, 5, 5)
connect _ppn_data_WIRE_16.pr, _ppn_data_T_133
node _ppn_data_T_134 = bits(_ppn_data_WIRE_17, 6, 6)
connect _ppn_data_WIRE_16.px, _ppn_data_T_134
node _ppn_data_T_135 = bits(_ppn_data_WIRE_17, 7, 7)
connect _ppn_data_WIRE_16.pw, _ppn_data_T_135
node _ppn_data_T_136 = bits(_ppn_data_WIRE_17, 8, 8)
connect _ppn_data_WIRE_16.sr, _ppn_data_T_136
node _ppn_data_T_137 = bits(_ppn_data_WIRE_17, 9, 9)
connect _ppn_data_WIRE_16.sx, _ppn_data_T_137
node _ppn_data_T_138 = bits(_ppn_data_WIRE_17, 10, 10)
connect _ppn_data_WIRE_16.sw, _ppn_data_T_138
node _ppn_data_T_139 = bits(_ppn_data_WIRE_17, 11, 11)
connect _ppn_data_WIRE_16.ae, _ppn_data_T_139
node _ppn_data_T_140 = bits(_ppn_data_WIRE_17, 12, 12)
connect _ppn_data_WIRE_16.g, _ppn_data_T_140
node _ppn_data_T_141 = bits(_ppn_data_WIRE_17, 13, 13)
connect _ppn_data_WIRE_16.u, _ppn_data_T_141
node _ppn_data_T_142 = bits(_ppn_data_WIRE_17, 33, 14)
connect _ppn_data_WIRE_16.ppn, _ppn_data_T_142
inst ppn_data_barrier_8 of OptimizationBarrier_EntryData_48
connect ppn_data_barrier_8.clock, clock
connect ppn_data_barrier_8.reset, reset
connect ppn_data_barrier_8.io.x.fragmented_superpage, _ppn_data_WIRE_16.fragmented_superpage
connect ppn_data_barrier_8.io.x.c, _ppn_data_WIRE_16.c
connect ppn_data_barrier_8.io.x.eff, _ppn_data_WIRE_16.eff
connect ppn_data_barrier_8.io.x.paa, _ppn_data_WIRE_16.paa
connect ppn_data_barrier_8.io.x.pal, _ppn_data_WIRE_16.pal
connect ppn_data_barrier_8.io.x.pr, _ppn_data_WIRE_16.pr
connect ppn_data_barrier_8.io.x.px, _ppn_data_WIRE_16.px
connect ppn_data_barrier_8.io.x.pw, _ppn_data_WIRE_16.pw
connect ppn_data_barrier_8.io.x.sr, _ppn_data_WIRE_16.sr
connect ppn_data_barrier_8.io.x.sx, _ppn_data_WIRE_16.sx
connect ppn_data_barrier_8.io.x.sw, _ppn_data_WIRE_16.sw
connect ppn_data_barrier_8.io.x.ae, _ppn_data_WIRE_16.ae
connect ppn_data_barrier_8.io.x.g, _ppn_data_WIRE_16.g
connect ppn_data_barrier_8.io.x.u, _ppn_data_WIRE_16.u
connect ppn_data_barrier_8.io.x.ppn, _ppn_data_WIRE_16.ppn
wire _ppn_data_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_19 : UInt<34>
connect _ppn_data_WIRE_19, superpage_entries[1].data[0]
node _ppn_data_T_143 = bits(_ppn_data_WIRE_19, 0, 0)
connect _ppn_data_WIRE_18.fragmented_superpage, _ppn_data_T_143
node _ppn_data_T_144 = bits(_ppn_data_WIRE_19, 1, 1)
connect _ppn_data_WIRE_18.c, _ppn_data_T_144
node _ppn_data_T_145 = bits(_ppn_data_WIRE_19, 2, 2)
connect _ppn_data_WIRE_18.eff, _ppn_data_T_145
node _ppn_data_T_146 = bits(_ppn_data_WIRE_19, 3, 3)
connect _ppn_data_WIRE_18.paa, _ppn_data_T_146
node _ppn_data_T_147 = bits(_ppn_data_WIRE_19, 4, 4)
connect _ppn_data_WIRE_18.pal, _ppn_data_T_147
node _ppn_data_T_148 = bits(_ppn_data_WIRE_19, 5, 5)
connect _ppn_data_WIRE_18.pr, _ppn_data_T_148
node _ppn_data_T_149 = bits(_ppn_data_WIRE_19, 6, 6)
connect _ppn_data_WIRE_18.px, _ppn_data_T_149
node _ppn_data_T_150 = bits(_ppn_data_WIRE_19, 7, 7)
connect _ppn_data_WIRE_18.pw, _ppn_data_T_150
node _ppn_data_T_151 = bits(_ppn_data_WIRE_19, 8, 8)
connect _ppn_data_WIRE_18.sr, _ppn_data_T_151
node _ppn_data_T_152 = bits(_ppn_data_WIRE_19, 9, 9)
connect _ppn_data_WIRE_18.sx, _ppn_data_T_152
node _ppn_data_T_153 = bits(_ppn_data_WIRE_19, 10, 10)
connect _ppn_data_WIRE_18.sw, _ppn_data_T_153
node _ppn_data_T_154 = bits(_ppn_data_WIRE_19, 11, 11)
connect _ppn_data_WIRE_18.ae, _ppn_data_T_154
node _ppn_data_T_155 = bits(_ppn_data_WIRE_19, 12, 12)
connect _ppn_data_WIRE_18.g, _ppn_data_T_155
node _ppn_data_T_156 = bits(_ppn_data_WIRE_19, 13, 13)
connect _ppn_data_WIRE_18.u, _ppn_data_T_156
node _ppn_data_T_157 = bits(_ppn_data_WIRE_19, 33, 14)
connect _ppn_data_WIRE_18.ppn, _ppn_data_T_157
inst ppn_data_barrier_9 of OptimizationBarrier_EntryData_49
connect ppn_data_barrier_9.clock, clock
connect ppn_data_barrier_9.reset, reset
connect ppn_data_barrier_9.io.x.fragmented_superpage, _ppn_data_WIRE_18.fragmented_superpage
connect ppn_data_barrier_9.io.x.c, _ppn_data_WIRE_18.c
connect ppn_data_barrier_9.io.x.eff, _ppn_data_WIRE_18.eff
connect ppn_data_barrier_9.io.x.paa, _ppn_data_WIRE_18.paa
connect ppn_data_barrier_9.io.x.pal, _ppn_data_WIRE_18.pal
connect ppn_data_barrier_9.io.x.pr, _ppn_data_WIRE_18.pr
connect ppn_data_barrier_9.io.x.px, _ppn_data_WIRE_18.px
connect ppn_data_barrier_9.io.x.pw, _ppn_data_WIRE_18.pw
connect ppn_data_barrier_9.io.x.sr, _ppn_data_WIRE_18.sr
connect ppn_data_barrier_9.io.x.sx, _ppn_data_WIRE_18.sx
connect ppn_data_barrier_9.io.x.sw, _ppn_data_WIRE_18.sw
connect ppn_data_barrier_9.io.x.ae, _ppn_data_WIRE_18.ae
connect ppn_data_barrier_9.io.x.g, _ppn_data_WIRE_18.g
connect ppn_data_barrier_9.io.x.u, _ppn_data_WIRE_18.u
connect ppn_data_barrier_9.io.x.ppn, _ppn_data_WIRE_18.ppn
wire _ppn_data_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_21 : UInt<34>
connect _ppn_data_WIRE_21, superpage_entries[2].data[0]
node _ppn_data_T_158 = bits(_ppn_data_WIRE_21, 0, 0)
connect _ppn_data_WIRE_20.fragmented_superpage, _ppn_data_T_158
node _ppn_data_T_159 = bits(_ppn_data_WIRE_21, 1, 1)
connect _ppn_data_WIRE_20.c, _ppn_data_T_159
node _ppn_data_T_160 = bits(_ppn_data_WIRE_21, 2, 2)
connect _ppn_data_WIRE_20.eff, _ppn_data_T_160
node _ppn_data_T_161 = bits(_ppn_data_WIRE_21, 3, 3)
connect _ppn_data_WIRE_20.paa, _ppn_data_T_161
node _ppn_data_T_162 = bits(_ppn_data_WIRE_21, 4, 4)
connect _ppn_data_WIRE_20.pal, _ppn_data_T_162
node _ppn_data_T_163 = bits(_ppn_data_WIRE_21, 5, 5)
connect _ppn_data_WIRE_20.pr, _ppn_data_T_163
node _ppn_data_T_164 = bits(_ppn_data_WIRE_21, 6, 6)
connect _ppn_data_WIRE_20.px, _ppn_data_T_164
node _ppn_data_T_165 = bits(_ppn_data_WIRE_21, 7, 7)
connect _ppn_data_WIRE_20.pw, _ppn_data_T_165
node _ppn_data_T_166 = bits(_ppn_data_WIRE_21, 8, 8)
connect _ppn_data_WIRE_20.sr, _ppn_data_T_166
node _ppn_data_T_167 = bits(_ppn_data_WIRE_21, 9, 9)
connect _ppn_data_WIRE_20.sx, _ppn_data_T_167
node _ppn_data_T_168 = bits(_ppn_data_WIRE_21, 10, 10)
connect _ppn_data_WIRE_20.sw, _ppn_data_T_168
node _ppn_data_T_169 = bits(_ppn_data_WIRE_21, 11, 11)
connect _ppn_data_WIRE_20.ae, _ppn_data_T_169
node _ppn_data_T_170 = bits(_ppn_data_WIRE_21, 12, 12)
connect _ppn_data_WIRE_20.g, _ppn_data_T_170
node _ppn_data_T_171 = bits(_ppn_data_WIRE_21, 13, 13)
connect _ppn_data_WIRE_20.u, _ppn_data_T_171
node _ppn_data_T_172 = bits(_ppn_data_WIRE_21, 33, 14)
connect _ppn_data_WIRE_20.ppn, _ppn_data_T_172
inst ppn_data_barrier_10 of OptimizationBarrier_EntryData_50
connect ppn_data_barrier_10.clock, clock
connect ppn_data_barrier_10.reset, reset
connect ppn_data_barrier_10.io.x.fragmented_superpage, _ppn_data_WIRE_20.fragmented_superpage
connect ppn_data_barrier_10.io.x.c, _ppn_data_WIRE_20.c
connect ppn_data_barrier_10.io.x.eff, _ppn_data_WIRE_20.eff
connect ppn_data_barrier_10.io.x.paa, _ppn_data_WIRE_20.paa
connect ppn_data_barrier_10.io.x.pal, _ppn_data_WIRE_20.pal
connect ppn_data_barrier_10.io.x.pr, _ppn_data_WIRE_20.pr
connect ppn_data_barrier_10.io.x.px, _ppn_data_WIRE_20.px
connect ppn_data_barrier_10.io.x.pw, _ppn_data_WIRE_20.pw
connect ppn_data_barrier_10.io.x.sr, _ppn_data_WIRE_20.sr
connect ppn_data_barrier_10.io.x.sx, _ppn_data_WIRE_20.sx
connect ppn_data_barrier_10.io.x.sw, _ppn_data_WIRE_20.sw
connect ppn_data_barrier_10.io.x.ae, _ppn_data_WIRE_20.ae
connect ppn_data_barrier_10.io.x.g, _ppn_data_WIRE_20.g
connect ppn_data_barrier_10.io.x.u, _ppn_data_WIRE_20.u
connect ppn_data_barrier_10.io.x.ppn, _ppn_data_WIRE_20.ppn
wire _ppn_data_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_23 : UInt<34>
connect _ppn_data_WIRE_23, superpage_entries[3].data[0]
node _ppn_data_T_173 = bits(_ppn_data_WIRE_23, 0, 0)
connect _ppn_data_WIRE_22.fragmented_superpage, _ppn_data_T_173
node _ppn_data_T_174 = bits(_ppn_data_WIRE_23, 1, 1)
connect _ppn_data_WIRE_22.c, _ppn_data_T_174
node _ppn_data_T_175 = bits(_ppn_data_WIRE_23, 2, 2)
connect _ppn_data_WIRE_22.eff, _ppn_data_T_175
node _ppn_data_T_176 = bits(_ppn_data_WIRE_23, 3, 3)
connect _ppn_data_WIRE_22.paa, _ppn_data_T_176
node _ppn_data_T_177 = bits(_ppn_data_WIRE_23, 4, 4)
connect _ppn_data_WIRE_22.pal, _ppn_data_T_177
node _ppn_data_T_178 = bits(_ppn_data_WIRE_23, 5, 5)
connect _ppn_data_WIRE_22.pr, _ppn_data_T_178
node _ppn_data_T_179 = bits(_ppn_data_WIRE_23, 6, 6)
connect _ppn_data_WIRE_22.px, _ppn_data_T_179
node _ppn_data_T_180 = bits(_ppn_data_WIRE_23, 7, 7)
connect _ppn_data_WIRE_22.pw, _ppn_data_T_180
node _ppn_data_T_181 = bits(_ppn_data_WIRE_23, 8, 8)
connect _ppn_data_WIRE_22.sr, _ppn_data_T_181
node _ppn_data_T_182 = bits(_ppn_data_WIRE_23, 9, 9)
connect _ppn_data_WIRE_22.sx, _ppn_data_T_182
node _ppn_data_T_183 = bits(_ppn_data_WIRE_23, 10, 10)
connect _ppn_data_WIRE_22.sw, _ppn_data_T_183
node _ppn_data_T_184 = bits(_ppn_data_WIRE_23, 11, 11)
connect _ppn_data_WIRE_22.ae, _ppn_data_T_184
node _ppn_data_T_185 = bits(_ppn_data_WIRE_23, 12, 12)
connect _ppn_data_WIRE_22.g, _ppn_data_T_185
node _ppn_data_T_186 = bits(_ppn_data_WIRE_23, 13, 13)
connect _ppn_data_WIRE_22.u, _ppn_data_T_186
node _ppn_data_T_187 = bits(_ppn_data_WIRE_23, 33, 14)
connect _ppn_data_WIRE_22.ppn, _ppn_data_T_187
inst ppn_data_barrier_11 of OptimizationBarrier_EntryData_51
connect ppn_data_barrier_11.clock, clock
connect ppn_data_barrier_11.reset, reset
connect ppn_data_barrier_11.io.x.fragmented_superpage, _ppn_data_WIRE_22.fragmented_superpage
connect ppn_data_barrier_11.io.x.c, _ppn_data_WIRE_22.c
connect ppn_data_barrier_11.io.x.eff, _ppn_data_WIRE_22.eff
connect ppn_data_barrier_11.io.x.paa, _ppn_data_WIRE_22.paa
connect ppn_data_barrier_11.io.x.pal, _ppn_data_WIRE_22.pal
connect ppn_data_barrier_11.io.x.pr, _ppn_data_WIRE_22.pr
connect ppn_data_barrier_11.io.x.px, _ppn_data_WIRE_22.px
connect ppn_data_barrier_11.io.x.pw, _ppn_data_WIRE_22.pw
connect ppn_data_barrier_11.io.x.sr, _ppn_data_WIRE_22.sr
connect ppn_data_barrier_11.io.x.sx, _ppn_data_WIRE_22.sx
connect ppn_data_barrier_11.io.x.sw, _ppn_data_WIRE_22.sw
connect ppn_data_barrier_11.io.x.ae, _ppn_data_WIRE_22.ae
connect ppn_data_barrier_11.io.x.g, _ppn_data_WIRE_22.g
connect ppn_data_barrier_11.io.x.u, _ppn_data_WIRE_22.u
connect ppn_data_barrier_11.io.x.ppn, _ppn_data_WIRE_22.ppn
wire _ppn_data_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _ppn_data_WIRE_25 : UInt<34>
connect _ppn_data_WIRE_25, special_entry.data[0]
node _ppn_data_T_188 = bits(_ppn_data_WIRE_25, 0, 0)
connect _ppn_data_WIRE_24.fragmented_superpage, _ppn_data_T_188
node _ppn_data_T_189 = bits(_ppn_data_WIRE_25, 1, 1)
connect _ppn_data_WIRE_24.c, _ppn_data_T_189
node _ppn_data_T_190 = bits(_ppn_data_WIRE_25, 2, 2)
connect _ppn_data_WIRE_24.eff, _ppn_data_T_190
node _ppn_data_T_191 = bits(_ppn_data_WIRE_25, 3, 3)
connect _ppn_data_WIRE_24.paa, _ppn_data_T_191
node _ppn_data_T_192 = bits(_ppn_data_WIRE_25, 4, 4)
connect _ppn_data_WIRE_24.pal, _ppn_data_T_192
node _ppn_data_T_193 = bits(_ppn_data_WIRE_25, 5, 5)
connect _ppn_data_WIRE_24.pr, _ppn_data_T_193
node _ppn_data_T_194 = bits(_ppn_data_WIRE_25, 6, 6)
connect _ppn_data_WIRE_24.px, _ppn_data_T_194
node _ppn_data_T_195 = bits(_ppn_data_WIRE_25, 7, 7)
connect _ppn_data_WIRE_24.pw, _ppn_data_T_195
node _ppn_data_T_196 = bits(_ppn_data_WIRE_25, 8, 8)
connect _ppn_data_WIRE_24.sr, _ppn_data_T_196
node _ppn_data_T_197 = bits(_ppn_data_WIRE_25, 9, 9)
connect _ppn_data_WIRE_24.sx, _ppn_data_T_197
node _ppn_data_T_198 = bits(_ppn_data_WIRE_25, 10, 10)
connect _ppn_data_WIRE_24.sw, _ppn_data_T_198
node _ppn_data_T_199 = bits(_ppn_data_WIRE_25, 11, 11)
connect _ppn_data_WIRE_24.ae, _ppn_data_T_199
node _ppn_data_T_200 = bits(_ppn_data_WIRE_25, 12, 12)
connect _ppn_data_WIRE_24.g, _ppn_data_T_200
node _ppn_data_T_201 = bits(_ppn_data_WIRE_25, 13, 13)
connect _ppn_data_WIRE_24.u, _ppn_data_T_201
node _ppn_data_T_202 = bits(_ppn_data_WIRE_25, 33, 14)
connect _ppn_data_WIRE_24.ppn, _ppn_data_T_202
inst ppn_data_barrier_12 of OptimizationBarrier_EntryData_52
connect ppn_data_barrier_12.clock, clock
connect ppn_data_barrier_12.reset, reset
connect ppn_data_barrier_12.io.x.fragmented_superpage, _ppn_data_WIRE_24.fragmented_superpage
connect ppn_data_barrier_12.io.x.c, _ppn_data_WIRE_24.c
connect ppn_data_barrier_12.io.x.eff, _ppn_data_WIRE_24.eff
connect ppn_data_barrier_12.io.x.paa, _ppn_data_WIRE_24.paa
connect ppn_data_barrier_12.io.x.pal, _ppn_data_WIRE_24.pal
connect ppn_data_barrier_12.io.x.pr, _ppn_data_WIRE_24.pr
connect ppn_data_barrier_12.io.x.px, _ppn_data_WIRE_24.px
connect ppn_data_barrier_12.io.x.pw, _ppn_data_WIRE_24.pw
connect ppn_data_barrier_12.io.x.sr, _ppn_data_WIRE_24.sr
connect ppn_data_barrier_12.io.x.sx, _ppn_data_WIRE_24.sx
connect ppn_data_barrier_12.io.x.sw, _ppn_data_WIRE_24.sw
connect ppn_data_barrier_12.io.x.ae, _ppn_data_WIRE_24.ae
connect ppn_data_barrier_12.io.x.g, _ppn_data_WIRE_24.g
connect ppn_data_barrier_12.io.x.u, _ppn_data_WIRE_24.u
connect ppn_data_barrier_12.io.x.ppn, _ppn_data_WIRE_24.ppn
node _ppn_T_1 = bits(vpn[0], 19, 0)
node _ppn_T_2 = mux(hitsVec[0][0], ppn_data_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_3 = mux(hitsVec[0][1], ppn_data_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_4 = mux(hitsVec[0][2], ppn_data_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_5 = mux(hitsVec[0][3], ppn_data_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_6 = mux(hitsVec[0][4], ppn_data_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_7 = mux(hitsVec[0][5], ppn_data_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_8 = mux(hitsVec[0][6], ppn_data_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_9 = mux(hitsVec[0][7], ppn_data_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_10 = mux(hitsVec[0][8], ppn_data_barrier_8.io.y.ppn, UInt<1>(0h0))
node _ppn_T_11 = mux(hitsVec[0][9], ppn_data_barrier_9.io.y.ppn, UInt<1>(0h0))
node _ppn_T_12 = mux(hitsVec[0][10], ppn_data_barrier_10.io.y.ppn, UInt<1>(0h0))
node _ppn_T_13 = mux(hitsVec[0][11], ppn_data_barrier_11.io.y.ppn, UInt<1>(0h0))
node _ppn_T_14 = mux(hitsVec[0][12], ppn_data_barrier_12.io.y.ppn, UInt<1>(0h0))
node _ppn_T_15 = mux(_ppn_T, _ppn_T_1, UInt<1>(0h0))
node _ppn_T_16 = or(_ppn_T_2, _ppn_T_3)
node _ppn_T_17 = or(_ppn_T_16, _ppn_T_4)
node _ppn_T_18 = or(_ppn_T_17, _ppn_T_5)
node _ppn_T_19 = or(_ppn_T_18, _ppn_T_6)
node _ppn_T_20 = or(_ppn_T_19, _ppn_T_7)
node _ppn_T_21 = or(_ppn_T_20, _ppn_T_8)
node _ppn_T_22 = or(_ppn_T_21, _ppn_T_9)
node _ppn_T_23 = or(_ppn_T_22, _ppn_T_10)
node _ppn_T_24 = or(_ppn_T_23, _ppn_T_11)
node _ppn_T_25 = or(_ppn_T_24, _ppn_T_12)
node _ppn_T_26 = or(_ppn_T_25, _ppn_T_13)
node _ppn_T_27 = or(_ppn_T_26, _ppn_T_14)
node _ppn_T_28 = or(_ppn_T_27, _ppn_T_15)
wire _ppn_WIRE : UInt<20>
connect _ppn_WIRE, _ppn_T_28
wire ppn : UInt<20>[1]
connect ppn[0], _ppn_WIRE
when do_refill :
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable[0]
connect newEntry.u, io.ptw.resp.bits.pte.u
connect newEntry.g, io.ptw.resp.bits.pte.g
connect newEntry.ae, io.ptw.resp.bits.ae_final
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r[0]
connect newEntry.pw, prot_w[0]
connect newEntry.px, prot_x[0]
connect newEntry.pal, prot_al[0]
connect newEntry.paa, prot_aa[0]
connect newEntry.eff, prot_eff[0]
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag, r_refill_tag
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, newEntry.fragmented_superpage)
node special_entry_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node special_entry_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node special_entry_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag, r_refill_tag
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node superpage_entries_0_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node superpage_entries_0_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag, r_refill_tag
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node superpage_entries_1_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node superpage_entries_1_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag, r_refill_tag
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node superpage_entries_2_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node superpage_entries_2_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag, r_refill_tag
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node superpage_entries_3_data_0_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node superpage_entries_3_data_0_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
else :
node waddr = mux(r_sectored_hit, r_sectored_hit_addr, r_sectored_repl_addr)
node _T_7 = eq(waddr, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0].valid[0], UInt<1>(0h0)
connect sectored_entries[0].valid[1], UInt<1>(0h0)
connect sectored_entries[0].valid[2], UInt<1>(0h0)
connect sectored_entries[0].valid[3], UInt<1>(0h0)
connect sectored_entries[0].tag, r_refill_tag
connect sectored_entries[0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_0_data_lo_lo = cat(sectored_entries_0_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_0_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_data_lo_hi = cat(sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo)
node sectored_entries_0_data_lo = cat(sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo)
node sectored_entries_0_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_0_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_0_data_hi_lo = cat(sectored_entries_0_data_hi_lo_hi, sectored_entries_0_data_hi_lo_lo)
node sectored_entries_0_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_0_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_data_hi_hi = cat(sectored_entries_0_data_hi_hi_hi, sectored_entries_0_data_hi_hi_lo)
node sectored_entries_0_data_hi = cat(sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo)
node _sectored_entries_0_data_T = cat(sectored_entries_0_data_hi, sectored_entries_0_data_lo)
connect sectored_entries[0].data[idx], _sectored_entries_0_data_T
node _T_9 = eq(waddr, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[1].valid[0], UInt<1>(0h0)
connect sectored_entries[1].valid[1], UInt<1>(0h0)
connect sectored_entries[1].valid[2], UInt<1>(0h0)
connect sectored_entries[1].valid[3], UInt<1>(0h0)
connect sectored_entries[1].tag, r_refill_tag
connect sectored_entries[1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_1_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_1_data_lo_lo = cat(sectored_entries_1_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_1_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_1_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_1_data_lo_hi = cat(sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo)
node sectored_entries_1_data_lo = cat(sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo)
node sectored_entries_1_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_1_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_1_data_hi_lo = cat(sectored_entries_1_data_hi_lo_hi, sectored_entries_1_data_hi_lo_lo)
node sectored_entries_1_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_1_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_1_data_hi_hi = cat(sectored_entries_1_data_hi_hi_hi, sectored_entries_1_data_hi_hi_lo)
node sectored_entries_1_data_hi = cat(sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo)
node _sectored_entries_1_data_T = cat(sectored_entries_1_data_hi, sectored_entries_1_data_lo)
connect sectored_entries[1].data[idx_1], _sectored_entries_1_data_T
node _T_11 = eq(waddr, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[2].valid[0], UInt<1>(0h0)
connect sectored_entries[2].valid[1], UInt<1>(0h0)
connect sectored_entries[2].valid[2], UInt<1>(0h0)
connect sectored_entries[2].valid[3], UInt<1>(0h0)
connect sectored_entries[2].tag, r_refill_tag
connect sectored_entries[2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_2_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_2_data_lo_lo = cat(sectored_entries_2_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_2_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_2_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_2_data_lo_hi = cat(sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo)
node sectored_entries_2_data_lo = cat(sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo)
node sectored_entries_2_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_2_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_2_data_hi_lo = cat(sectored_entries_2_data_hi_lo_hi, sectored_entries_2_data_hi_lo_lo)
node sectored_entries_2_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_2_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_2_data_hi_hi = cat(sectored_entries_2_data_hi_hi_hi, sectored_entries_2_data_hi_hi_lo)
node sectored_entries_2_data_hi = cat(sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo)
node _sectored_entries_2_data_T = cat(sectored_entries_2_data_hi, sectored_entries_2_data_lo)
connect sectored_entries[2].data[idx_2], _sectored_entries_2_data_T
node _T_13 = eq(waddr, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[3].valid[0], UInt<1>(0h0)
connect sectored_entries[3].valid[1], UInt<1>(0h0)
connect sectored_entries[3].valid[2], UInt<1>(0h0)
connect sectored_entries[3].valid[3], UInt<1>(0h0)
connect sectored_entries[3].tag, r_refill_tag
connect sectored_entries[3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_3_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_3_data_lo_lo = cat(sectored_entries_3_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_3_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_3_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_3_data_lo_hi = cat(sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo)
node sectored_entries_3_data_lo = cat(sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo)
node sectored_entries_3_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_3_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_3_data_hi_lo = cat(sectored_entries_3_data_hi_lo_hi, sectored_entries_3_data_hi_lo_lo)
node sectored_entries_3_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_3_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_3_data_hi_hi = cat(sectored_entries_3_data_hi_hi_hi, sectored_entries_3_data_hi_hi_lo)
node sectored_entries_3_data_hi = cat(sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo)
node _sectored_entries_3_data_T = cat(sectored_entries_3_data_hi, sectored_entries_3_data_lo)
connect sectored_entries[3].data[idx_3], _sectored_entries_3_data_T
node _T_15 = eq(waddr, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[4].valid[0], UInt<1>(0h0)
connect sectored_entries[4].valid[1], UInt<1>(0h0)
connect sectored_entries[4].valid[2], UInt<1>(0h0)
connect sectored_entries[4].valid[3], UInt<1>(0h0)
connect sectored_entries[4].tag, r_refill_tag
connect sectored_entries[4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_4_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_4_data_lo_lo = cat(sectored_entries_4_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_4_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_4_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_4_data_lo_hi = cat(sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo)
node sectored_entries_4_data_lo = cat(sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo)
node sectored_entries_4_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_4_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_4_data_hi_lo = cat(sectored_entries_4_data_hi_lo_hi, sectored_entries_4_data_hi_lo_lo)
node sectored_entries_4_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_4_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_4_data_hi_hi = cat(sectored_entries_4_data_hi_hi_hi, sectored_entries_4_data_hi_hi_lo)
node sectored_entries_4_data_hi = cat(sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo)
node _sectored_entries_4_data_T = cat(sectored_entries_4_data_hi, sectored_entries_4_data_lo)
connect sectored_entries[4].data[idx_4], _sectored_entries_4_data_T
node _T_17 = eq(waddr, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[5].valid[0], UInt<1>(0h0)
connect sectored_entries[5].valid[1], UInt<1>(0h0)
connect sectored_entries[5].valid[2], UInt<1>(0h0)
connect sectored_entries[5].valid[3], UInt<1>(0h0)
connect sectored_entries[5].tag, r_refill_tag
connect sectored_entries[5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_5_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_5_data_lo_lo = cat(sectored_entries_5_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_5_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_5_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_5_data_lo_hi = cat(sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo)
node sectored_entries_5_data_lo = cat(sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo)
node sectored_entries_5_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_5_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_5_data_hi_lo = cat(sectored_entries_5_data_hi_lo_hi, sectored_entries_5_data_hi_lo_lo)
node sectored_entries_5_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_5_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_5_data_hi_hi = cat(sectored_entries_5_data_hi_hi_hi, sectored_entries_5_data_hi_hi_lo)
node sectored_entries_5_data_hi = cat(sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo)
node _sectored_entries_5_data_T = cat(sectored_entries_5_data_hi, sectored_entries_5_data_lo)
connect sectored_entries[5].data[idx_5], _sectored_entries_5_data_T
node _T_19 = eq(waddr, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[6].valid[0], UInt<1>(0h0)
connect sectored_entries[6].valid[1], UInt<1>(0h0)
connect sectored_entries[6].valid[2], UInt<1>(0h0)
connect sectored_entries[6].valid[3], UInt<1>(0h0)
connect sectored_entries[6].tag, r_refill_tag
connect sectored_entries[6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_6_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_6_data_lo_lo = cat(sectored_entries_6_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_6_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_6_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_6_data_lo_hi = cat(sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo)
node sectored_entries_6_data_lo = cat(sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo)
node sectored_entries_6_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_6_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_6_data_hi_lo = cat(sectored_entries_6_data_hi_lo_hi, sectored_entries_6_data_hi_lo_lo)
node sectored_entries_6_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_6_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_6_data_hi_hi = cat(sectored_entries_6_data_hi_hi_hi, sectored_entries_6_data_hi_hi_lo)
node sectored_entries_6_data_hi = cat(sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo)
node _sectored_entries_6_data_T = cat(sectored_entries_6_data_hi, sectored_entries_6_data_lo)
connect sectored_entries[6].data[idx_6], _sectored_entries_6_data_T
node _T_21 = eq(waddr, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[7].valid[0], UInt<1>(0h0)
connect sectored_entries[7].valid[1], UInt<1>(0h0)
connect sectored_entries[7].valid[2], UInt<1>(0h0)
connect sectored_entries[7].valid[3], UInt<1>(0h0)
connect sectored_entries[7].tag, r_refill_tag
connect sectored_entries[7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_7_data_lo_lo_hi = cat(newEntry.eff, newEntry.c)
node sectored_entries_7_data_lo_lo = cat(sectored_entries_7_data_lo_lo_hi, newEntry.fragmented_superpage)
node sectored_entries_7_data_lo_hi_lo = cat(newEntry.pal, newEntry.paa)
node sectored_entries_7_data_lo_hi_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_7_data_lo_hi = cat(sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo)
node sectored_entries_7_data_lo = cat(sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo)
node sectored_entries_7_data_hi_lo_lo = cat(newEntry.sr, newEntry.pw)
node sectored_entries_7_data_hi_lo_hi = cat(newEntry.sw, newEntry.sx)
node sectored_entries_7_data_hi_lo = cat(sectored_entries_7_data_hi_lo_hi, sectored_entries_7_data_hi_lo_lo)
node sectored_entries_7_data_hi_hi_lo = cat(newEntry.g, newEntry.ae)
node sectored_entries_7_data_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_7_data_hi_hi = cat(sectored_entries_7_data_hi_hi_hi, sectored_entries_7_data_hi_hi_lo)
node sectored_entries_7_data_hi = cat(sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo)
node _sectored_entries_7_data_T = cat(sectored_entries_7_data_hi, sectored_entries_7_data_lo)
connect sectored_entries[7].data[idx_7], _sectored_entries_7_data_T
node _entries_T = bits(vpn[0], 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<34>
connect _entries_WIRE_1, sectored_entries[0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.pr, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.px, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.pw, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.sr, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.sx, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.sw, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.ae, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.g, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.u, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 33, 14)
connect _entries_WIRE.ppn, _entries_T_15
inst entries_barrier of OptimizationBarrier_EntryData_53
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.ae, _entries_WIRE.ae
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_16 = bits(vpn[0], 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<34>
connect _entries_WIRE_3, sectored_entries[1].data[_entries_T_16]
node _entries_T_17 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.pr, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.px, _entries_T_23
node _entries_T_24 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.pw, _entries_T_24
node _entries_T_25 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.sr, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.sx, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.sw, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.ae, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.g, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.u, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 33, 14)
connect _entries_WIRE_2.ppn, _entries_T_31
inst entries_barrier_1 of OptimizationBarrier_EntryData_54
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.ae, _entries_WIRE_2.ae
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_32 = bits(vpn[0], 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<34>
connect _entries_WIRE_5, sectored_entries[2].data[_entries_T_32]
node _entries_T_33 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.pr, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.px, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.pw, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.sr, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.sx, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.sw, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.ae, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_5, 33, 14)
connect _entries_WIRE_4.ppn, _entries_T_47
inst entries_barrier_2 of OptimizationBarrier_EntryData_55
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.ae, _entries_WIRE_4.ae
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_48 = bits(vpn[0], 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<34>
connect _entries_WIRE_7, sectored_entries[3].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.pr, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.px, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.pw, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.sr, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.sx, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.sw, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.ae, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.g, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.u, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_7, 33, 14)
connect _entries_WIRE_6.ppn, _entries_T_63
inst entries_barrier_3 of OptimizationBarrier_EntryData_56
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.ae, _entries_WIRE_6.ae
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_64 = bits(vpn[0], 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<34>
connect _entries_WIRE_9, sectored_entries[4].data[_entries_T_64]
node _entries_T_65 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.pr, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.px, _entries_T_71
node _entries_T_72 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.pw, _entries_T_72
node _entries_T_73 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.sr, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.sx, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.sw, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.ae, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.g, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.u, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_9, 33, 14)
connect _entries_WIRE_8.ppn, _entries_T_79
inst entries_barrier_4 of OptimizationBarrier_EntryData_57
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.ae, _entries_WIRE_8.ae
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_80 = bits(vpn[0], 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<34>
connect _entries_WIRE_11, sectored_entries[5].data[_entries_T_80]
node _entries_T_81 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.pr, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.px, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.pw, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.sr, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.sx, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.sw, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.ae, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_11, 33, 14)
connect _entries_WIRE_10.ppn, _entries_T_95
inst entries_barrier_5 of OptimizationBarrier_EntryData_58
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.ae, _entries_WIRE_10.ae
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_96 = bits(vpn[0], 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<34>
connect _entries_WIRE_13, sectored_entries[6].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.pr, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.px, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.pw, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.sr, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.sx, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.sw, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.ae, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.g, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.u, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_13, 33, 14)
connect _entries_WIRE_12.ppn, _entries_T_111
inst entries_barrier_6 of OptimizationBarrier_EntryData_59
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.ae, _entries_WIRE_12.ae
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_112 = bits(vpn[0], 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<34>
connect _entries_WIRE_15, sectored_entries[7].data[_entries_T_112]
node _entries_T_113 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.pr, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.px, _entries_T_119
node _entries_T_120 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.pw, _entries_T_120
node _entries_T_121 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.sr, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.sx, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.sw, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.ae, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.g, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.u, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_15, 33, 14)
connect _entries_WIRE_14.ppn, _entries_T_127
inst entries_barrier_7 of OptimizationBarrier_EntryData_60
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.ae, _entries_WIRE_14.ae
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<34>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_128 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.pr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.px, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.pw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.sr, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.sx, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.sw, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.ae, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.g, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.u, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_17, 33, 14)
connect _entries_WIRE_16.ppn, _entries_T_142
inst entries_barrier_8 of OptimizationBarrier_EntryData_61
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.ae, _entries_WIRE_16.ae
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<34>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_143 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_143
node _entries_T_144 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_144
node _entries_T_145 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.pr, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.px, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.pw, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.sr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.sx, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.sw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.ae, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.g, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.u, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_19, 33, 14)
connect _entries_WIRE_18.ppn, _entries_T_157
inst entries_barrier_9 of OptimizationBarrier_EntryData_62
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.ae, _entries_WIRE_18.ae
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<34>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_158 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.pr, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.px, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.pw, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.sr, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.sx, _entries_T_167
node _entries_T_168 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.sw, _entries_T_168
node _entries_T_169 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.ae, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.g, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.u, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_21, 33, 14)
connect _entries_WIRE_20.ppn, _entries_T_172
inst entries_barrier_10 of OptimizationBarrier_EntryData_63
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.ae, _entries_WIRE_20.ae
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<34>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_173 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.pr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.px, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.pw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.ae, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.g, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.u, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_23, 33, 14)
connect _entries_WIRE_22.ppn, _entries_T_187
inst entries_barrier_11 of OptimizationBarrier_EntryData_64
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.ae, _entries_WIRE_22.ae
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<34>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_188 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_191
node _entries_T_192 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.pr, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.px, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.pw, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.sr, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.sx, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.sw, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.ae, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.g, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.u, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_25, 33, 14)
connect _entries_WIRE_24.ppn, _entries_T_202
inst entries_barrier_12 of OptimizationBarrier_EntryData_65
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.ae, _entries_WIRE_24.ae
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
wire _entries_WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13]
connect _entries_WIRE_26[0], entries_barrier.io.y
connect _entries_WIRE_26[1], entries_barrier_1.io.y
connect _entries_WIRE_26[2], entries_barrier_2.io.y
connect _entries_WIRE_26[3], entries_barrier_3.io.y
connect _entries_WIRE_26[4], entries_barrier_4.io.y
connect _entries_WIRE_26[5], entries_barrier_5.io.y
connect _entries_WIRE_26[6], entries_barrier_6.io.y
connect _entries_WIRE_26[7], entries_barrier_7.io.y
connect _entries_WIRE_26[8], entries_barrier_8.io.y
connect _entries_WIRE_26[9], entries_barrier_9.io.y
connect _entries_WIRE_26[10], entries_barrier_10.io.y
connect _entries_WIRE_26[11], entries_barrier_11.io.y
connect _entries_WIRE_26[12], entries_barrier_12.io.y
wire entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[13][1]
connect entries[0], _entries_WIRE_26
node _normal_entries_T = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_1 : UInt<34>
connect _normal_entries_WIRE_1, sectored_entries[0].data[_normal_entries_T]
node _normal_entries_T_1 = bits(_normal_entries_WIRE_1, 0, 0)
connect _normal_entries_WIRE.fragmented_superpage, _normal_entries_T_1
node _normal_entries_T_2 = bits(_normal_entries_WIRE_1, 1, 1)
connect _normal_entries_WIRE.c, _normal_entries_T_2
node _normal_entries_T_3 = bits(_normal_entries_WIRE_1, 2, 2)
connect _normal_entries_WIRE.eff, _normal_entries_T_3
node _normal_entries_T_4 = bits(_normal_entries_WIRE_1, 3, 3)
connect _normal_entries_WIRE.paa, _normal_entries_T_4
node _normal_entries_T_5 = bits(_normal_entries_WIRE_1, 4, 4)
connect _normal_entries_WIRE.pal, _normal_entries_T_5
node _normal_entries_T_6 = bits(_normal_entries_WIRE_1, 5, 5)
connect _normal_entries_WIRE.pr, _normal_entries_T_6
node _normal_entries_T_7 = bits(_normal_entries_WIRE_1, 6, 6)
connect _normal_entries_WIRE.px, _normal_entries_T_7
node _normal_entries_T_8 = bits(_normal_entries_WIRE_1, 7, 7)
connect _normal_entries_WIRE.pw, _normal_entries_T_8
node _normal_entries_T_9 = bits(_normal_entries_WIRE_1, 8, 8)
connect _normal_entries_WIRE.sr, _normal_entries_T_9
node _normal_entries_T_10 = bits(_normal_entries_WIRE_1, 9, 9)
connect _normal_entries_WIRE.sx, _normal_entries_T_10
node _normal_entries_T_11 = bits(_normal_entries_WIRE_1, 10, 10)
connect _normal_entries_WIRE.sw, _normal_entries_T_11
node _normal_entries_T_12 = bits(_normal_entries_WIRE_1, 11, 11)
connect _normal_entries_WIRE.ae, _normal_entries_T_12
node _normal_entries_T_13 = bits(_normal_entries_WIRE_1, 12, 12)
connect _normal_entries_WIRE.g, _normal_entries_T_13
node _normal_entries_T_14 = bits(_normal_entries_WIRE_1, 13, 13)
connect _normal_entries_WIRE.u, _normal_entries_T_14
node _normal_entries_T_15 = bits(_normal_entries_WIRE_1, 33, 14)
connect _normal_entries_WIRE.ppn, _normal_entries_T_15
inst normal_entries_barrier of OptimizationBarrier_EntryData_66
connect normal_entries_barrier.clock, clock
connect normal_entries_barrier.reset, reset
connect normal_entries_barrier.io.x.fragmented_superpage, _normal_entries_WIRE.fragmented_superpage
connect normal_entries_barrier.io.x.c, _normal_entries_WIRE.c
connect normal_entries_barrier.io.x.eff, _normal_entries_WIRE.eff
connect normal_entries_barrier.io.x.paa, _normal_entries_WIRE.paa
connect normal_entries_barrier.io.x.pal, _normal_entries_WIRE.pal
connect normal_entries_barrier.io.x.pr, _normal_entries_WIRE.pr
connect normal_entries_barrier.io.x.px, _normal_entries_WIRE.px
connect normal_entries_barrier.io.x.pw, _normal_entries_WIRE.pw
connect normal_entries_barrier.io.x.sr, _normal_entries_WIRE.sr
connect normal_entries_barrier.io.x.sx, _normal_entries_WIRE.sx
connect normal_entries_barrier.io.x.sw, _normal_entries_WIRE.sw
connect normal_entries_barrier.io.x.ae, _normal_entries_WIRE.ae
connect normal_entries_barrier.io.x.g, _normal_entries_WIRE.g
connect normal_entries_barrier.io.x.u, _normal_entries_WIRE.u
connect normal_entries_barrier.io.x.ppn, _normal_entries_WIRE.ppn
node _normal_entries_T_16 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_3 : UInt<34>
connect _normal_entries_WIRE_3, sectored_entries[1].data[_normal_entries_T_16]
node _normal_entries_T_17 = bits(_normal_entries_WIRE_3, 0, 0)
connect _normal_entries_WIRE_2.fragmented_superpage, _normal_entries_T_17
node _normal_entries_T_18 = bits(_normal_entries_WIRE_3, 1, 1)
connect _normal_entries_WIRE_2.c, _normal_entries_T_18
node _normal_entries_T_19 = bits(_normal_entries_WIRE_3, 2, 2)
connect _normal_entries_WIRE_2.eff, _normal_entries_T_19
node _normal_entries_T_20 = bits(_normal_entries_WIRE_3, 3, 3)
connect _normal_entries_WIRE_2.paa, _normal_entries_T_20
node _normal_entries_T_21 = bits(_normal_entries_WIRE_3, 4, 4)
connect _normal_entries_WIRE_2.pal, _normal_entries_T_21
node _normal_entries_T_22 = bits(_normal_entries_WIRE_3, 5, 5)
connect _normal_entries_WIRE_2.pr, _normal_entries_T_22
node _normal_entries_T_23 = bits(_normal_entries_WIRE_3, 6, 6)
connect _normal_entries_WIRE_2.px, _normal_entries_T_23
node _normal_entries_T_24 = bits(_normal_entries_WIRE_3, 7, 7)
connect _normal_entries_WIRE_2.pw, _normal_entries_T_24
node _normal_entries_T_25 = bits(_normal_entries_WIRE_3, 8, 8)
connect _normal_entries_WIRE_2.sr, _normal_entries_T_25
node _normal_entries_T_26 = bits(_normal_entries_WIRE_3, 9, 9)
connect _normal_entries_WIRE_2.sx, _normal_entries_T_26
node _normal_entries_T_27 = bits(_normal_entries_WIRE_3, 10, 10)
connect _normal_entries_WIRE_2.sw, _normal_entries_T_27
node _normal_entries_T_28 = bits(_normal_entries_WIRE_3, 11, 11)
connect _normal_entries_WIRE_2.ae, _normal_entries_T_28
node _normal_entries_T_29 = bits(_normal_entries_WIRE_3, 12, 12)
connect _normal_entries_WIRE_2.g, _normal_entries_T_29
node _normal_entries_T_30 = bits(_normal_entries_WIRE_3, 13, 13)
connect _normal_entries_WIRE_2.u, _normal_entries_T_30
node _normal_entries_T_31 = bits(_normal_entries_WIRE_3, 33, 14)
connect _normal_entries_WIRE_2.ppn, _normal_entries_T_31
inst normal_entries_barrier_1 of OptimizationBarrier_EntryData_67
connect normal_entries_barrier_1.clock, clock
connect normal_entries_barrier_1.reset, reset
connect normal_entries_barrier_1.io.x.fragmented_superpage, _normal_entries_WIRE_2.fragmented_superpage
connect normal_entries_barrier_1.io.x.c, _normal_entries_WIRE_2.c
connect normal_entries_barrier_1.io.x.eff, _normal_entries_WIRE_2.eff
connect normal_entries_barrier_1.io.x.paa, _normal_entries_WIRE_2.paa
connect normal_entries_barrier_1.io.x.pal, _normal_entries_WIRE_2.pal
connect normal_entries_barrier_1.io.x.pr, _normal_entries_WIRE_2.pr
connect normal_entries_barrier_1.io.x.px, _normal_entries_WIRE_2.px
connect normal_entries_barrier_1.io.x.pw, _normal_entries_WIRE_2.pw
connect normal_entries_barrier_1.io.x.sr, _normal_entries_WIRE_2.sr
connect normal_entries_barrier_1.io.x.sx, _normal_entries_WIRE_2.sx
connect normal_entries_barrier_1.io.x.sw, _normal_entries_WIRE_2.sw
connect normal_entries_barrier_1.io.x.ae, _normal_entries_WIRE_2.ae
connect normal_entries_barrier_1.io.x.g, _normal_entries_WIRE_2.g
connect normal_entries_barrier_1.io.x.u, _normal_entries_WIRE_2.u
connect normal_entries_barrier_1.io.x.ppn, _normal_entries_WIRE_2.ppn
node _normal_entries_T_32 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_5 : UInt<34>
connect _normal_entries_WIRE_5, sectored_entries[2].data[_normal_entries_T_32]
node _normal_entries_T_33 = bits(_normal_entries_WIRE_5, 0, 0)
connect _normal_entries_WIRE_4.fragmented_superpage, _normal_entries_T_33
node _normal_entries_T_34 = bits(_normal_entries_WIRE_5, 1, 1)
connect _normal_entries_WIRE_4.c, _normal_entries_T_34
node _normal_entries_T_35 = bits(_normal_entries_WIRE_5, 2, 2)
connect _normal_entries_WIRE_4.eff, _normal_entries_T_35
node _normal_entries_T_36 = bits(_normal_entries_WIRE_5, 3, 3)
connect _normal_entries_WIRE_4.paa, _normal_entries_T_36
node _normal_entries_T_37 = bits(_normal_entries_WIRE_5, 4, 4)
connect _normal_entries_WIRE_4.pal, _normal_entries_T_37
node _normal_entries_T_38 = bits(_normal_entries_WIRE_5, 5, 5)
connect _normal_entries_WIRE_4.pr, _normal_entries_T_38
node _normal_entries_T_39 = bits(_normal_entries_WIRE_5, 6, 6)
connect _normal_entries_WIRE_4.px, _normal_entries_T_39
node _normal_entries_T_40 = bits(_normal_entries_WIRE_5, 7, 7)
connect _normal_entries_WIRE_4.pw, _normal_entries_T_40
node _normal_entries_T_41 = bits(_normal_entries_WIRE_5, 8, 8)
connect _normal_entries_WIRE_4.sr, _normal_entries_T_41
node _normal_entries_T_42 = bits(_normal_entries_WIRE_5, 9, 9)
connect _normal_entries_WIRE_4.sx, _normal_entries_T_42
node _normal_entries_T_43 = bits(_normal_entries_WIRE_5, 10, 10)
connect _normal_entries_WIRE_4.sw, _normal_entries_T_43
node _normal_entries_T_44 = bits(_normal_entries_WIRE_5, 11, 11)
connect _normal_entries_WIRE_4.ae, _normal_entries_T_44
node _normal_entries_T_45 = bits(_normal_entries_WIRE_5, 12, 12)
connect _normal_entries_WIRE_4.g, _normal_entries_T_45
node _normal_entries_T_46 = bits(_normal_entries_WIRE_5, 13, 13)
connect _normal_entries_WIRE_4.u, _normal_entries_T_46
node _normal_entries_T_47 = bits(_normal_entries_WIRE_5, 33, 14)
connect _normal_entries_WIRE_4.ppn, _normal_entries_T_47
inst normal_entries_barrier_2 of OptimizationBarrier_EntryData_68
connect normal_entries_barrier_2.clock, clock
connect normal_entries_barrier_2.reset, reset
connect normal_entries_barrier_2.io.x.fragmented_superpage, _normal_entries_WIRE_4.fragmented_superpage
connect normal_entries_barrier_2.io.x.c, _normal_entries_WIRE_4.c
connect normal_entries_barrier_2.io.x.eff, _normal_entries_WIRE_4.eff
connect normal_entries_barrier_2.io.x.paa, _normal_entries_WIRE_4.paa
connect normal_entries_barrier_2.io.x.pal, _normal_entries_WIRE_4.pal
connect normal_entries_barrier_2.io.x.pr, _normal_entries_WIRE_4.pr
connect normal_entries_barrier_2.io.x.px, _normal_entries_WIRE_4.px
connect normal_entries_barrier_2.io.x.pw, _normal_entries_WIRE_4.pw
connect normal_entries_barrier_2.io.x.sr, _normal_entries_WIRE_4.sr
connect normal_entries_barrier_2.io.x.sx, _normal_entries_WIRE_4.sx
connect normal_entries_barrier_2.io.x.sw, _normal_entries_WIRE_4.sw
connect normal_entries_barrier_2.io.x.ae, _normal_entries_WIRE_4.ae
connect normal_entries_barrier_2.io.x.g, _normal_entries_WIRE_4.g
connect normal_entries_barrier_2.io.x.u, _normal_entries_WIRE_4.u
connect normal_entries_barrier_2.io.x.ppn, _normal_entries_WIRE_4.ppn
node _normal_entries_T_48 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_7 : UInt<34>
connect _normal_entries_WIRE_7, sectored_entries[3].data[_normal_entries_T_48]
node _normal_entries_T_49 = bits(_normal_entries_WIRE_7, 0, 0)
connect _normal_entries_WIRE_6.fragmented_superpage, _normal_entries_T_49
node _normal_entries_T_50 = bits(_normal_entries_WIRE_7, 1, 1)
connect _normal_entries_WIRE_6.c, _normal_entries_T_50
node _normal_entries_T_51 = bits(_normal_entries_WIRE_7, 2, 2)
connect _normal_entries_WIRE_6.eff, _normal_entries_T_51
node _normal_entries_T_52 = bits(_normal_entries_WIRE_7, 3, 3)
connect _normal_entries_WIRE_6.paa, _normal_entries_T_52
node _normal_entries_T_53 = bits(_normal_entries_WIRE_7, 4, 4)
connect _normal_entries_WIRE_6.pal, _normal_entries_T_53
node _normal_entries_T_54 = bits(_normal_entries_WIRE_7, 5, 5)
connect _normal_entries_WIRE_6.pr, _normal_entries_T_54
node _normal_entries_T_55 = bits(_normal_entries_WIRE_7, 6, 6)
connect _normal_entries_WIRE_6.px, _normal_entries_T_55
node _normal_entries_T_56 = bits(_normal_entries_WIRE_7, 7, 7)
connect _normal_entries_WIRE_6.pw, _normal_entries_T_56
node _normal_entries_T_57 = bits(_normal_entries_WIRE_7, 8, 8)
connect _normal_entries_WIRE_6.sr, _normal_entries_T_57
node _normal_entries_T_58 = bits(_normal_entries_WIRE_7, 9, 9)
connect _normal_entries_WIRE_6.sx, _normal_entries_T_58
node _normal_entries_T_59 = bits(_normal_entries_WIRE_7, 10, 10)
connect _normal_entries_WIRE_6.sw, _normal_entries_T_59
node _normal_entries_T_60 = bits(_normal_entries_WIRE_7, 11, 11)
connect _normal_entries_WIRE_6.ae, _normal_entries_T_60
node _normal_entries_T_61 = bits(_normal_entries_WIRE_7, 12, 12)
connect _normal_entries_WIRE_6.g, _normal_entries_T_61
node _normal_entries_T_62 = bits(_normal_entries_WIRE_7, 13, 13)
connect _normal_entries_WIRE_6.u, _normal_entries_T_62
node _normal_entries_T_63 = bits(_normal_entries_WIRE_7, 33, 14)
connect _normal_entries_WIRE_6.ppn, _normal_entries_T_63
inst normal_entries_barrier_3 of OptimizationBarrier_EntryData_69
connect normal_entries_barrier_3.clock, clock
connect normal_entries_barrier_3.reset, reset
connect normal_entries_barrier_3.io.x.fragmented_superpage, _normal_entries_WIRE_6.fragmented_superpage
connect normal_entries_barrier_3.io.x.c, _normal_entries_WIRE_6.c
connect normal_entries_barrier_3.io.x.eff, _normal_entries_WIRE_6.eff
connect normal_entries_barrier_3.io.x.paa, _normal_entries_WIRE_6.paa
connect normal_entries_barrier_3.io.x.pal, _normal_entries_WIRE_6.pal
connect normal_entries_barrier_3.io.x.pr, _normal_entries_WIRE_6.pr
connect normal_entries_barrier_3.io.x.px, _normal_entries_WIRE_6.px
connect normal_entries_barrier_3.io.x.pw, _normal_entries_WIRE_6.pw
connect normal_entries_barrier_3.io.x.sr, _normal_entries_WIRE_6.sr
connect normal_entries_barrier_3.io.x.sx, _normal_entries_WIRE_6.sx
connect normal_entries_barrier_3.io.x.sw, _normal_entries_WIRE_6.sw
connect normal_entries_barrier_3.io.x.ae, _normal_entries_WIRE_6.ae
connect normal_entries_barrier_3.io.x.g, _normal_entries_WIRE_6.g
connect normal_entries_barrier_3.io.x.u, _normal_entries_WIRE_6.u
connect normal_entries_barrier_3.io.x.ppn, _normal_entries_WIRE_6.ppn
node _normal_entries_T_64 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_9 : UInt<34>
connect _normal_entries_WIRE_9, sectored_entries[4].data[_normal_entries_T_64]
node _normal_entries_T_65 = bits(_normal_entries_WIRE_9, 0, 0)
connect _normal_entries_WIRE_8.fragmented_superpage, _normal_entries_T_65
node _normal_entries_T_66 = bits(_normal_entries_WIRE_9, 1, 1)
connect _normal_entries_WIRE_8.c, _normal_entries_T_66
node _normal_entries_T_67 = bits(_normal_entries_WIRE_9, 2, 2)
connect _normal_entries_WIRE_8.eff, _normal_entries_T_67
node _normal_entries_T_68 = bits(_normal_entries_WIRE_9, 3, 3)
connect _normal_entries_WIRE_8.paa, _normal_entries_T_68
node _normal_entries_T_69 = bits(_normal_entries_WIRE_9, 4, 4)
connect _normal_entries_WIRE_8.pal, _normal_entries_T_69
node _normal_entries_T_70 = bits(_normal_entries_WIRE_9, 5, 5)
connect _normal_entries_WIRE_8.pr, _normal_entries_T_70
node _normal_entries_T_71 = bits(_normal_entries_WIRE_9, 6, 6)
connect _normal_entries_WIRE_8.px, _normal_entries_T_71
node _normal_entries_T_72 = bits(_normal_entries_WIRE_9, 7, 7)
connect _normal_entries_WIRE_8.pw, _normal_entries_T_72
node _normal_entries_T_73 = bits(_normal_entries_WIRE_9, 8, 8)
connect _normal_entries_WIRE_8.sr, _normal_entries_T_73
node _normal_entries_T_74 = bits(_normal_entries_WIRE_9, 9, 9)
connect _normal_entries_WIRE_8.sx, _normal_entries_T_74
node _normal_entries_T_75 = bits(_normal_entries_WIRE_9, 10, 10)
connect _normal_entries_WIRE_8.sw, _normal_entries_T_75
node _normal_entries_T_76 = bits(_normal_entries_WIRE_9, 11, 11)
connect _normal_entries_WIRE_8.ae, _normal_entries_T_76
node _normal_entries_T_77 = bits(_normal_entries_WIRE_9, 12, 12)
connect _normal_entries_WIRE_8.g, _normal_entries_T_77
node _normal_entries_T_78 = bits(_normal_entries_WIRE_9, 13, 13)
connect _normal_entries_WIRE_8.u, _normal_entries_T_78
node _normal_entries_T_79 = bits(_normal_entries_WIRE_9, 33, 14)
connect _normal_entries_WIRE_8.ppn, _normal_entries_T_79
inst normal_entries_barrier_4 of OptimizationBarrier_EntryData_70
connect normal_entries_barrier_4.clock, clock
connect normal_entries_barrier_4.reset, reset
connect normal_entries_barrier_4.io.x.fragmented_superpage, _normal_entries_WIRE_8.fragmented_superpage
connect normal_entries_barrier_4.io.x.c, _normal_entries_WIRE_8.c
connect normal_entries_barrier_4.io.x.eff, _normal_entries_WIRE_8.eff
connect normal_entries_barrier_4.io.x.paa, _normal_entries_WIRE_8.paa
connect normal_entries_barrier_4.io.x.pal, _normal_entries_WIRE_8.pal
connect normal_entries_barrier_4.io.x.pr, _normal_entries_WIRE_8.pr
connect normal_entries_barrier_4.io.x.px, _normal_entries_WIRE_8.px
connect normal_entries_barrier_4.io.x.pw, _normal_entries_WIRE_8.pw
connect normal_entries_barrier_4.io.x.sr, _normal_entries_WIRE_8.sr
connect normal_entries_barrier_4.io.x.sx, _normal_entries_WIRE_8.sx
connect normal_entries_barrier_4.io.x.sw, _normal_entries_WIRE_8.sw
connect normal_entries_barrier_4.io.x.ae, _normal_entries_WIRE_8.ae
connect normal_entries_barrier_4.io.x.g, _normal_entries_WIRE_8.g
connect normal_entries_barrier_4.io.x.u, _normal_entries_WIRE_8.u
connect normal_entries_barrier_4.io.x.ppn, _normal_entries_WIRE_8.ppn
node _normal_entries_T_80 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_11 : UInt<34>
connect _normal_entries_WIRE_11, sectored_entries[5].data[_normal_entries_T_80]
node _normal_entries_T_81 = bits(_normal_entries_WIRE_11, 0, 0)
connect _normal_entries_WIRE_10.fragmented_superpage, _normal_entries_T_81
node _normal_entries_T_82 = bits(_normal_entries_WIRE_11, 1, 1)
connect _normal_entries_WIRE_10.c, _normal_entries_T_82
node _normal_entries_T_83 = bits(_normal_entries_WIRE_11, 2, 2)
connect _normal_entries_WIRE_10.eff, _normal_entries_T_83
node _normal_entries_T_84 = bits(_normal_entries_WIRE_11, 3, 3)
connect _normal_entries_WIRE_10.paa, _normal_entries_T_84
node _normal_entries_T_85 = bits(_normal_entries_WIRE_11, 4, 4)
connect _normal_entries_WIRE_10.pal, _normal_entries_T_85
node _normal_entries_T_86 = bits(_normal_entries_WIRE_11, 5, 5)
connect _normal_entries_WIRE_10.pr, _normal_entries_T_86
node _normal_entries_T_87 = bits(_normal_entries_WIRE_11, 6, 6)
connect _normal_entries_WIRE_10.px, _normal_entries_T_87
node _normal_entries_T_88 = bits(_normal_entries_WIRE_11, 7, 7)
connect _normal_entries_WIRE_10.pw, _normal_entries_T_88
node _normal_entries_T_89 = bits(_normal_entries_WIRE_11, 8, 8)
connect _normal_entries_WIRE_10.sr, _normal_entries_T_89
node _normal_entries_T_90 = bits(_normal_entries_WIRE_11, 9, 9)
connect _normal_entries_WIRE_10.sx, _normal_entries_T_90
node _normal_entries_T_91 = bits(_normal_entries_WIRE_11, 10, 10)
connect _normal_entries_WIRE_10.sw, _normal_entries_T_91
node _normal_entries_T_92 = bits(_normal_entries_WIRE_11, 11, 11)
connect _normal_entries_WIRE_10.ae, _normal_entries_T_92
node _normal_entries_T_93 = bits(_normal_entries_WIRE_11, 12, 12)
connect _normal_entries_WIRE_10.g, _normal_entries_T_93
node _normal_entries_T_94 = bits(_normal_entries_WIRE_11, 13, 13)
connect _normal_entries_WIRE_10.u, _normal_entries_T_94
node _normal_entries_T_95 = bits(_normal_entries_WIRE_11, 33, 14)
connect _normal_entries_WIRE_10.ppn, _normal_entries_T_95
inst normal_entries_barrier_5 of OptimizationBarrier_EntryData_71
connect normal_entries_barrier_5.clock, clock
connect normal_entries_barrier_5.reset, reset
connect normal_entries_barrier_5.io.x.fragmented_superpage, _normal_entries_WIRE_10.fragmented_superpage
connect normal_entries_barrier_5.io.x.c, _normal_entries_WIRE_10.c
connect normal_entries_barrier_5.io.x.eff, _normal_entries_WIRE_10.eff
connect normal_entries_barrier_5.io.x.paa, _normal_entries_WIRE_10.paa
connect normal_entries_barrier_5.io.x.pal, _normal_entries_WIRE_10.pal
connect normal_entries_barrier_5.io.x.pr, _normal_entries_WIRE_10.pr
connect normal_entries_barrier_5.io.x.px, _normal_entries_WIRE_10.px
connect normal_entries_barrier_5.io.x.pw, _normal_entries_WIRE_10.pw
connect normal_entries_barrier_5.io.x.sr, _normal_entries_WIRE_10.sr
connect normal_entries_barrier_5.io.x.sx, _normal_entries_WIRE_10.sx
connect normal_entries_barrier_5.io.x.sw, _normal_entries_WIRE_10.sw
connect normal_entries_barrier_5.io.x.ae, _normal_entries_WIRE_10.ae
connect normal_entries_barrier_5.io.x.g, _normal_entries_WIRE_10.g
connect normal_entries_barrier_5.io.x.u, _normal_entries_WIRE_10.u
connect normal_entries_barrier_5.io.x.ppn, _normal_entries_WIRE_10.ppn
node _normal_entries_T_96 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_13 : UInt<34>
connect _normal_entries_WIRE_13, sectored_entries[6].data[_normal_entries_T_96]
node _normal_entries_T_97 = bits(_normal_entries_WIRE_13, 0, 0)
connect _normal_entries_WIRE_12.fragmented_superpage, _normal_entries_T_97
node _normal_entries_T_98 = bits(_normal_entries_WIRE_13, 1, 1)
connect _normal_entries_WIRE_12.c, _normal_entries_T_98
node _normal_entries_T_99 = bits(_normal_entries_WIRE_13, 2, 2)
connect _normal_entries_WIRE_12.eff, _normal_entries_T_99
node _normal_entries_T_100 = bits(_normal_entries_WIRE_13, 3, 3)
connect _normal_entries_WIRE_12.paa, _normal_entries_T_100
node _normal_entries_T_101 = bits(_normal_entries_WIRE_13, 4, 4)
connect _normal_entries_WIRE_12.pal, _normal_entries_T_101
node _normal_entries_T_102 = bits(_normal_entries_WIRE_13, 5, 5)
connect _normal_entries_WIRE_12.pr, _normal_entries_T_102
node _normal_entries_T_103 = bits(_normal_entries_WIRE_13, 6, 6)
connect _normal_entries_WIRE_12.px, _normal_entries_T_103
node _normal_entries_T_104 = bits(_normal_entries_WIRE_13, 7, 7)
connect _normal_entries_WIRE_12.pw, _normal_entries_T_104
node _normal_entries_T_105 = bits(_normal_entries_WIRE_13, 8, 8)
connect _normal_entries_WIRE_12.sr, _normal_entries_T_105
node _normal_entries_T_106 = bits(_normal_entries_WIRE_13, 9, 9)
connect _normal_entries_WIRE_12.sx, _normal_entries_T_106
node _normal_entries_T_107 = bits(_normal_entries_WIRE_13, 10, 10)
connect _normal_entries_WIRE_12.sw, _normal_entries_T_107
node _normal_entries_T_108 = bits(_normal_entries_WIRE_13, 11, 11)
connect _normal_entries_WIRE_12.ae, _normal_entries_T_108
node _normal_entries_T_109 = bits(_normal_entries_WIRE_13, 12, 12)
connect _normal_entries_WIRE_12.g, _normal_entries_T_109
node _normal_entries_T_110 = bits(_normal_entries_WIRE_13, 13, 13)
connect _normal_entries_WIRE_12.u, _normal_entries_T_110
node _normal_entries_T_111 = bits(_normal_entries_WIRE_13, 33, 14)
connect _normal_entries_WIRE_12.ppn, _normal_entries_T_111
inst normal_entries_barrier_6 of OptimizationBarrier_EntryData_72
connect normal_entries_barrier_6.clock, clock
connect normal_entries_barrier_6.reset, reset
connect normal_entries_barrier_6.io.x.fragmented_superpage, _normal_entries_WIRE_12.fragmented_superpage
connect normal_entries_barrier_6.io.x.c, _normal_entries_WIRE_12.c
connect normal_entries_barrier_6.io.x.eff, _normal_entries_WIRE_12.eff
connect normal_entries_barrier_6.io.x.paa, _normal_entries_WIRE_12.paa
connect normal_entries_barrier_6.io.x.pal, _normal_entries_WIRE_12.pal
connect normal_entries_barrier_6.io.x.pr, _normal_entries_WIRE_12.pr
connect normal_entries_barrier_6.io.x.px, _normal_entries_WIRE_12.px
connect normal_entries_barrier_6.io.x.pw, _normal_entries_WIRE_12.pw
connect normal_entries_barrier_6.io.x.sr, _normal_entries_WIRE_12.sr
connect normal_entries_barrier_6.io.x.sx, _normal_entries_WIRE_12.sx
connect normal_entries_barrier_6.io.x.sw, _normal_entries_WIRE_12.sw
connect normal_entries_barrier_6.io.x.ae, _normal_entries_WIRE_12.ae
connect normal_entries_barrier_6.io.x.g, _normal_entries_WIRE_12.g
connect normal_entries_barrier_6.io.x.u, _normal_entries_WIRE_12.u
connect normal_entries_barrier_6.io.x.ppn, _normal_entries_WIRE_12.ppn
node _normal_entries_T_112 = bits(vpn[0], 1, 0)
wire _normal_entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_15 : UInt<34>
connect _normal_entries_WIRE_15, sectored_entries[7].data[_normal_entries_T_112]
node _normal_entries_T_113 = bits(_normal_entries_WIRE_15, 0, 0)
connect _normal_entries_WIRE_14.fragmented_superpage, _normal_entries_T_113
node _normal_entries_T_114 = bits(_normal_entries_WIRE_15, 1, 1)
connect _normal_entries_WIRE_14.c, _normal_entries_T_114
node _normal_entries_T_115 = bits(_normal_entries_WIRE_15, 2, 2)
connect _normal_entries_WIRE_14.eff, _normal_entries_T_115
node _normal_entries_T_116 = bits(_normal_entries_WIRE_15, 3, 3)
connect _normal_entries_WIRE_14.paa, _normal_entries_T_116
node _normal_entries_T_117 = bits(_normal_entries_WIRE_15, 4, 4)
connect _normal_entries_WIRE_14.pal, _normal_entries_T_117
node _normal_entries_T_118 = bits(_normal_entries_WIRE_15, 5, 5)
connect _normal_entries_WIRE_14.pr, _normal_entries_T_118
node _normal_entries_T_119 = bits(_normal_entries_WIRE_15, 6, 6)
connect _normal_entries_WIRE_14.px, _normal_entries_T_119
node _normal_entries_T_120 = bits(_normal_entries_WIRE_15, 7, 7)
connect _normal_entries_WIRE_14.pw, _normal_entries_T_120
node _normal_entries_T_121 = bits(_normal_entries_WIRE_15, 8, 8)
connect _normal_entries_WIRE_14.sr, _normal_entries_T_121
node _normal_entries_T_122 = bits(_normal_entries_WIRE_15, 9, 9)
connect _normal_entries_WIRE_14.sx, _normal_entries_T_122
node _normal_entries_T_123 = bits(_normal_entries_WIRE_15, 10, 10)
connect _normal_entries_WIRE_14.sw, _normal_entries_T_123
node _normal_entries_T_124 = bits(_normal_entries_WIRE_15, 11, 11)
connect _normal_entries_WIRE_14.ae, _normal_entries_T_124
node _normal_entries_T_125 = bits(_normal_entries_WIRE_15, 12, 12)
connect _normal_entries_WIRE_14.g, _normal_entries_T_125
node _normal_entries_T_126 = bits(_normal_entries_WIRE_15, 13, 13)
connect _normal_entries_WIRE_14.u, _normal_entries_T_126
node _normal_entries_T_127 = bits(_normal_entries_WIRE_15, 33, 14)
connect _normal_entries_WIRE_14.ppn, _normal_entries_T_127
inst normal_entries_barrier_7 of OptimizationBarrier_EntryData_73
connect normal_entries_barrier_7.clock, clock
connect normal_entries_barrier_7.reset, reset
connect normal_entries_barrier_7.io.x.fragmented_superpage, _normal_entries_WIRE_14.fragmented_superpage
connect normal_entries_barrier_7.io.x.c, _normal_entries_WIRE_14.c
connect normal_entries_barrier_7.io.x.eff, _normal_entries_WIRE_14.eff
connect normal_entries_barrier_7.io.x.paa, _normal_entries_WIRE_14.paa
connect normal_entries_barrier_7.io.x.pal, _normal_entries_WIRE_14.pal
connect normal_entries_barrier_7.io.x.pr, _normal_entries_WIRE_14.pr
connect normal_entries_barrier_7.io.x.px, _normal_entries_WIRE_14.px
connect normal_entries_barrier_7.io.x.pw, _normal_entries_WIRE_14.pw
connect normal_entries_barrier_7.io.x.sr, _normal_entries_WIRE_14.sr
connect normal_entries_barrier_7.io.x.sx, _normal_entries_WIRE_14.sx
connect normal_entries_barrier_7.io.x.sw, _normal_entries_WIRE_14.sw
connect normal_entries_barrier_7.io.x.ae, _normal_entries_WIRE_14.ae
connect normal_entries_barrier_7.io.x.g, _normal_entries_WIRE_14.g
connect normal_entries_barrier_7.io.x.u, _normal_entries_WIRE_14.u
connect normal_entries_barrier_7.io.x.ppn, _normal_entries_WIRE_14.ppn
wire _normal_entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_17 : UInt<34>
connect _normal_entries_WIRE_17, superpage_entries[0].data[0]
node _normal_entries_T_128 = bits(_normal_entries_WIRE_17, 0, 0)
connect _normal_entries_WIRE_16.fragmented_superpage, _normal_entries_T_128
node _normal_entries_T_129 = bits(_normal_entries_WIRE_17, 1, 1)
connect _normal_entries_WIRE_16.c, _normal_entries_T_129
node _normal_entries_T_130 = bits(_normal_entries_WIRE_17, 2, 2)
connect _normal_entries_WIRE_16.eff, _normal_entries_T_130
node _normal_entries_T_131 = bits(_normal_entries_WIRE_17, 3, 3)
connect _normal_entries_WIRE_16.paa, _normal_entries_T_131
node _normal_entries_T_132 = bits(_normal_entries_WIRE_17, 4, 4)
connect _normal_entries_WIRE_16.pal, _normal_entries_T_132
node _normal_entries_T_133 = bits(_normal_entries_WIRE_17, 5, 5)
connect _normal_entries_WIRE_16.pr, _normal_entries_T_133
node _normal_entries_T_134 = bits(_normal_entries_WIRE_17, 6, 6)
connect _normal_entries_WIRE_16.px, _normal_entries_T_134
node _normal_entries_T_135 = bits(_normal_entries_WIRE_17, 7, 7)
connect _normal_entries_WIRE_16.pw, _normal_entries_T_135
node _normal_entries_T_136 = bits(_normal_entries_WIRE_17, 8, 8)
connect _normal_entries_WIRE_16.sr, _normal_entries_T_136
node _normal_entries_T_137 = bits(_normal_entries_WIRE_17, 9, 9)
connect _normal_entries_WIRE_16.sx, _normal_entries_T_137
node _normal_entries_T_138 = bits(_normal_entries_WIRE_17, 10, 10)
connect _normal_entries_WIRE_16.sw, _normal_entries_T_138
node _normal_entries_T_139 = bits(_normal_entries_WIRE_17, 11, 11)
connect _normal_entries_WIRE_16.ae, _normal_entries_T_139
node _normal_entries_T_140 = bits(_normal_entries_WIRE_17, 12, 12)
connect _normal_entries_WIRE_16.g, _normal_entries_T_140
node _normal_entries_T_141 = bits(_normal_entries_WIRE_17, 13, 13)
connect _normal_entries_WIRE_16.u, _normal_entries_T_141
node _normal_entries_T_142 = bits(_normal_entries_WIRE_17, 33, 14)
connect _normal_entries_WIRE_16.ppn, _normal_entries_T_142
inst normal_entries_barrier_8 of OptimizationBarrier_EntryData_74
connect normal_entries_barrier_8.clock, clock
connect normal_entries_barrier_8.reset, reset
connect normal_entries_barrier_8.io.x.fragmented_superpage, _normal_entries_WIRE_16.fragmented_superpage
connect normal_entries_barrier_8.io.x.c, _normal_entries_WIRE_16.c
connect normal_entries_barrier_8.io.x.eff, _normal_entries_WIRE_16.eff
connect normal_entries_barrier_8.io.x.paa, _normal_entries_WIRE_16.paa
connect normal_entries_barrier_8.io.x.pal, _normal_entries_WIRE_16.pal
connect normal_entries_barrier_8.io.x.pr, _normal_entries_WIRE_16.pr
connect normal_entries_barrier_8.io.x.px, _normal_entries_WIRE_16.px
connect normal_entries_barrier_8.io.x.pw, _normal_entries_WIRE_16.pw
connect normal_entries_barrier_8.io.x.sr, _normal_entries_WIRE_16.sr
connect normal_entries_barrier_8.io.x.sx, _normal_entries_WIRE_16.sx
connect normal_entries_barrier_8.io.x.sw, _normal_entries_WIRE_16.sw
connect normal_entries_barrier_8.io.x.ae, _normal_entries_WIRE_16.ae
connect normal_entries_barrier_8.io.x.g, _normal_entries_WIRE_16.g
connect normal_entries_barrier_8.io.x.u, _normal_entries_WIRE_16.u
connect normal_entries_barrier_8.io.x.ppn, _normal_entries_WIRE_16.ppn
wire _normal_entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_19 : UInt<34>
connect _normal_entries_WIRE_19, superpage_entries[1].data[0]
node _normal_entries_T_143 = bits(_normal_entries_WIRE_19, 0, 0)
connect _normal_entries_WIRE_18.fragmented_superpage, _normal_entries_T_143
node _normal_entries_T_144 = bits(_normal_entries_WIRE_19, 1, 1)
connect _normal_entries_WIRE_18.c, _normal_entries_T_144
node _normal_entries_T_145 = bits(_normal_entries_WIRE_19, 2, 2)
connect _normal_entries_WIRE_18.eff, _normal_entries_T_145
node _normal_entries_T_146 = bits(_normal_entries_WIRE_19, 3, 3)
connect _normal_entries_WIRE_18.paa, _normal_entries_T_146
node _normal_entries_T_147 = bits(_normal_entries_WIRE_19, 4, 4)
connect _normal_entries_WIRE_18.pal, _normal_entries_T_147
node _normal_entries_T_148 = bits(_normal_entries_WIRE_19, 5, 5)
connect _normal_entries_WIRE_18.pr, _normal_entries_T_148
node _normal_entries_T_149 = bits(_normal_entries_WIRE_19, 6, 6)
connect _normal_entries_WIRE_18.px, _normal_entries_T_149
node _normal_entries_T_150 = bits(_normal_entries_WIRE_19, 7, 7)
connect _normal_entries_WIRE_18.pw, _normal_entries_T_150
node _normal_entries_T_151 = bits(_normal_entries_WIRE_19, 8, 8)
connect _normal_entries_WIRE_18.sr, _normal_entries_T_151
node _normal_entries_T_152 = bits(_normal_entries_WIRE_19, 9, 9)
connect _normal_entries_WIRE_18.sx, _normal_entries_T_152
node _normal_entries_T_153 = bits(_normal_entries_WIRE_19, 10, 10)
connect _normal_entries_WIRE_18.sw, _normal_entries_T_153
node _normal_entries_T_154 = bits(_normal_entries_WIRE_19, 11, 11)
connect _normal_entries_WIRE_18.ae, _normal_entries_T_154
node _normal_entries_T_155 = bits(_normal_entries_WIRE_19, 12, 12)
connect _normal_entries_WIRE_18.g, _normal_entries_T_155
node _normal_entries_T_156 = bits(_normal_entries_WIRE_19, 13, 13)
connect _normal_entries_WIRE_18.u, _normal_entries_T_156
node _normal_entries_T_157 = bits(_normal_entries_WIRE_19, 33, 14)
connect _normal_entries_WIRE_18.ppn, _normal_entries_T_157
inst normal_entries_barrier_9 of OptimizationBarrier_EntryData_75
connect normal_entries_barrier_9.clock, clock
connect normal_entries_barrier_9.reset, reset
connect normal_entries_barrier_9.io.x.fragmented_superpage, _normal_entries_WIRE_18.fragmented_superpage
connect normal_entries_barrier_9.io.x.c, _normal_entries_WIRE_18.c
connect normal_entries_barrier_9.io.x.eff, _normal_entries_WIRE_18.eff
connect normal_entries_barrier_9.io.x.paa, _normal_entries_WIRE_18.paa
connect normal_entries_barrier_9.io.x.pal, _normal_entries_WIRE_18.pal
connect normal_entries_barrier_9.io.x.pr, _normal_entries_WIRE_18.pr
connect normal_entries_barrier_9.io.x.px, _normal_entries_WIRE_18.px
connect normal_entries_barrier_9.io.x.pw, _normal_entries_WIRE_18.pw
connect normal_entries_barrier_9.io.x.sr, _normal_entries_WIRE_18.sr
connect normal_entries_barrier_9.io.x.sx, _normal_entries_WIRE_18.sx
connect normal_entries_barrier_9.io.x.sw, _normal_entries_WIRE_18.sw
connect normal_entries_barrier_9.io.x.ae, _normal_entries_WIRE_18.ae
connect normal_entries_barrier_9.io.x.g, _normal_entries_WIRE_18.g
connect normal_entries_barrier_9.io.x.u, _normal_entries_WIRE_18.u
connect normal_entries_barrier_9.io.x.ppn, _normal_entries_WIRE_18.ppn
wire _normal_entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_21 : UInt<34>
connect _normal_entries_WIRE_21, superpage_entries[2].data[0]
node _normal_entries_T_158 = bits(_normal_entries_WIRE_21, 0, 0)
connect _normal_entries_WIRE_20.fragmented_superpage, _normal_entries_T_158
node _normal_entries_T_159 = bits(_normal_entries_WIRE_21, 1, 1)
connect _normal_entries_WIRE_20.c, _normal_entries_T_159
node _normal_entries_T_160 = bits(_normal_entries_WIRE_21, 2, 2)
connect _normal_entries_WIRE_20.eff, _normal_entries_T_160
node _normal_entries_T_161 = bits(_normal_entries_WIRE_21, 3, 3)
connect _normal_entries_WIRE_20.paa, _normal_entries_T_161
node _normal_entries_T_162 = bits(_normal_entries_WIRE_21, 4, 4)
connect _normal_entries_WIRE_20.pal, _normal_entries_T_162
node _normal_entries_T_163 = bits(_normal_entries_WIRE_21, 5, 5)
connect _normal_entries_WIRE_20.pr, _normal_entries_T_163
node _normal_entries_T_164 = bits(_normal_entries_WIRE_21, 6, 6)
connect _normal_entries_WIRE_20.px, _normal_entries_T_164
node _normal_entries_T_165 = bits(_normal_entries_WIRE_21, 7, 7)
connect _normal_entries_WIRE_20.pw, _normal_entries_T_165
node _normal_entries_T_166 = bits(_normal_entries_WIRE_21, 8, 8)
connect _normal_entries_WIRE_20.sr, _normal_entries_T_166
node _normal_entries_T_167 = bits(_normal_entries_WIRE_21, 9, 9)
connect _normal_entries_WIRE_20.sx, _normal_entries_T_167
node _normal_entries_T_168 = bits(_normal_entries_WIRE_21, 10, 10)
connect _normal_entries_WIRE_20.sw, _normal_entries_T_168
node _normal_entries_T_169 = bits(_normal_entries_WIRE_21, 11, 11)
connect _normal_entries_WIRE_20.ae, _normal_entries_T_169
node _normal_entries_T_170 = bits(_normal_entries_WIRE_21, 12, 12)
connect _normal_entries_WIRE_20.g, _normal_entries_T_170
node _normal_entries_T_171 = bits(_normal_entries_WIRE_21, 13, 13)
connect _normal_entries_WIRE_20.u, _normal_entries_T_171
node _normal_entries_T_172 = bits(_normal_entries_WIRE_21, 33, 14)
connect _normal_entries_WIRE_20.ppn, _normal_entries_T_172
inst normal_entries_barrier_10 of OptimizationBarrier_EntryData_76
connect normal_entries_barrier_10.clock, clock
connect normal_entries_barrier_10.reset, reset
connect normal_entries_barrier_10.io.x.fragmented_superpage, _normal_entries_WIRE_20.fragmented_superpage
connect normal_entries_barrier_10.io.x.c, _normal_entries_WIRE_20.c
connect normal_entries_barrier_10.io.x.eff, _normal_entries_WIRE_20.eff
connect normal_entries_barrier_10.io.x.paa, _normal_entries_WIRE_20.paa
connect normal_entries_barrier_10.io.x.pal, _normal_entries_WIRE_20.pal
connect normal_entries_barrier_10.io.x.pr, _normal_entries_WIRE_20.pr
connect normal_entries_barrier_10.io.x.px, _normal_entries_WIRE_20.px
connect normal_entries_barrier_10.io.x.pw, _normal_entries_WIRE_20.pw
connect normal_entries_barrier_10.io.x.sr, _normal_entries_WIRE_20.sr
connect normal_entries_barrier_10.io.x.sx, _normal_entries_WIRE_20.sx
connect normal_entries_barrier_10.io.x.sw, _normal_entries_WIRE_20.sw
connect normal_entries_barrier_10.io.x.ae, _normal_entries_WIRE_20.ae
connect normal_entries_barrier_10.io.x.g, _normal_entries_WIRE_20.g
connect normal_entries_barrier_10.io.x.u, _normal_entries_WIRE_20.u
connect normal_entries_barrier_10.io.x.ppn, _normal_entries_WIRE_20.ppn
wire _normal_entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _normal_entries_WIRE_23 : UInt<34>
connect _normal_entries_WIRE_23, superpage_entries[3].data[0]
node _normal_entries_T_173 = bits(_normal_entries_WIRE_23, 0, 0)
connect _normal_entries_WIRE_22.fragmented_superpage, _normal_entries_T_173
node _normal_entries_T_174 = bits(_normal_entries_WIRE_23, 1, 1)
connect _normal_entries_WIRE_22.c, _normal_entries_T_174
node _normal_entries_T_175 = bits(_normal_entries_WIRE_23, 2, 2)
connect _normal_entries_WIRE_22.eff, _normal_entries_T_175
node _normal_entries_T_176 = bits(_normal_entries_WIRE_23, 3, 3)
connect _normal_entries_WIRE_22.paa, _normal_entries_T_176
node _normal_entries_T_177 = bits(_normal_entries_WIRE_23, 4, 4)
connect _normal_entries_WIRE_22.pal, _normal_entries_T_177
node _normal_entries_T_178 = bits(_normal_entries_WIRE_23, 5, 5)
connect _normal_entries_WIRE_22.pr, _normal_entries_T_178
node _normal_entries_T_179 = bits(_normal_entries_WIRE_23, 6, 6)
connect _normal_entries_WIRE_22.px, _normal_entries_T_179
node _normal_entries_T_180 = bits(_normal_entries_WIRE_23, 7, 7)
connect _normal_entries_WIRE_22.pw, _normal_entries_T_180
node _normal_entries_T_181 = bits(_normal_entries_WIRE_23, 8, 8)
connect _normal_entries_WIRE_22.sr, _normal_entries_T_181
node _normal_entries_T_182 = bits(_normal_entries_WIRE_23, 9, 9)
connect _normal_entries_WIRE_22.sx, _normal_entries_T_182
node _normal_entries_T_183 = bits(_normal_entries_WIRE_23, 10, 10)
connect _normal_entries_WIRE_22.sw, _normal_entries_T_183
node _normal_entries_T_184 = bits(_normal_entries_WIRE_23, 11, 11)
connect _normal_entries_WIRE_22.ae, _normal_entries_T_184
node _normal_entries_T_185 = bits(_normal_entries_WIRE_23, 12, 12)
connect _normal_entries_WIRE_22.g, _normal_entries_T_185
node _normal_entries_T_186 = bits(_normal_entries_WIRE_23, 13, 13)
connect _normal_entries_WIRE_22.u, _normal_entries_T_186
node _normal_entries_T_187 = bits(_normal_entries_WIRE_23, 33, 14)
connect _normal_entries_WIRE_22.ppn, _normal_entries_T_187
inst normal_entries_barrier_11 of OptimizationBarrier_EntryData_77
connect normal_entries_barrier_11.clock, clock
connect normal_entries_barrier_11.reset, reset
connect normal_entries_barrier_11.io.x.fragmented_superpage, _normal_entries_WIRE_22.fragmented_superpage
connect normal_entries_barrier_11.io.x.c, _normal_entries_WIRE_22.c
connect normal_entries_barrier_11.io.x.eff, _normal_entries_WIRE_22.eff
connect normal_entries_barrier_11.io.x.paa, _normal_entries_WIRE_22.paa
connect normal_entries_barrier_11.io.x.pal, _normal_entries_WIRE_22.pal
connect normal_entries_barrier_11.io.x.pr, _normal_entries_WIRE_22.pr
connect normal_entries_barrier_11.io.x.px, _normal_entries_WIRE_22.px
connect normal_entries_barrier_11.io.x.pw, _normal_entries_WIRE_22.pw
connect normal_entries_barrier_11.io.x.sr, _normal_entries_WIRE_22.sr
connect normal_entries_barrier_11.io.x.sx, _normal_entries_WIRE_22.sx
connect normal_entries_barrier_11.io.x.sw, _normal_entries_WIRE_22.sw
connect normal_entries_barrier_11.io.x.ae, _normal_entries_WIRE_22.ae
connect normal_entries_barrier_11.io.x.g, _normal_entries_WIRE_22.g
connect normal_entries_barrier_11.io.x.u, _normal_entries_WIRE_22.u
connect normal_entries_barrier_11.io.x.ppn, _normal_entries_WIRE_22.ppn
wire _normal_entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12]
connect _normal_entries_WIRE_24[0], normal_entries_barrier.io.y
connect _normal_entries_WIRE_24[1], normal_entries_barrier_1.io.y
connect _normal_entries_WIRE_24[2], normal_entries_barrier_2.io.y
connect _normal_entries_WIRE_24[3], normal_entries_barrier_3.io.y
connect _normal_entries_WIRE_24[4], normal_entries_barrier_4.io.y
connect _normal_entries_WIRE_24[5], normal_entries_barrier_5.io.y
connect _normal_entries_WIRE_24[6], normal_entries_barrier_6.io.y
connect _normal_entries_WIRE_24[7], normal_entries_barrier_7.io.y
connect _normal_entries_WIRE_24[8], normal_entries_barrier_8.io.y
connect _normal_entries_WIRE_24[9], normal_entries_barrier_9.io.y
connect _normal_entries_WIRE_24[10], normal_entries_barrier_10.io.y
connect _normal_entries_WIRE_24[11], normal_entries_barrier_11.io.y
wire normal_entries : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}[12][1]
connect normal_entries[0], _normal_entries_WIRE_24
node ptw_ae_array_lo_lo_hi = cat(entries[0][2].ae, entries[0][1].ae)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries[0][0].ae)
node ptw_ae_array_lo_hi_hi = cat(entries[0][5].ae, entries[0][4].ae)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries[0][3].ae)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries[0][8].ae, entries[0][7].ae)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries[0][6].ae)
node ptw_ae_array_hi_hi_lo = cat(entries[0][10].ae, entries[0][9].ae)
node ptw_ae_array_hi_hi_hi = cat(entries[0][12].ae, entries[0][11].ae)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node _ptw_ae_array_T_1 = cat(UInt<1>(0h0), _ptw_ae_array_T)
wire ptw_ae_array : UInt<14>[1]
connect ptw_ae_array[0], _ptw_ae_array_T_1
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, io.ptw.status.sum)
node priv_rw_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries[0][0].u)
node priv_rw_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries[0][3].u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries[0][6].u)
node priv_rw_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u)
node priv_rw_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries[0][0].u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries[0][3].u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries[0][6].u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node _priv_rw_ok_T_7 = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
wire priv_rw_ok : UInt<13>[1]
connect priv_rw_ok[0], _priv_rw_ok_T_7
node priv_x_ok_lo_lo_hi = cat(entries[0][2].u, entries[0][1].u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries[0][0].u)
node priv_x_ok_lo_hi_hi = cat(entries[0][5].u, entries[0][4].u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries[0][3].u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries[0][8].u, entries[0][7].u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries[0][6].u)
node priv_x_ok_hi_hi_lo = cat(entries[0][10].u, entries[0][9].u)
node priv_x_ok_hi_hi_hi = cat(entries[0][12].u, entries[0][11].u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries[0][2].u, entries[0][1].u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries[0][0].u)
node priv_x_ok_lo_hi_hi_1 = cat(entries[0][5].u, entries[0][4].u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries[0][3].u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries[0][8].u, entries[0][7].u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries[0][6].u)
node priv_x_ok_hi_hi_lo_1 = cat(entries[0][10].u, entries[0][9].u)
node priv_x_ok_hi_hi_hi_1 = cat(entries[0][12].u, entries[0][11].u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node _priv_x_ok_T_3 = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
wire priv_x_ok : UInt<13>[1]
connect priv_x_ok[0], _priv_x_ok_T_3
node r_array_lo_lo_hi = cat(entries[0][2].sr, entries[0][1].sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries[0][0].sr)
node r_array_lo_hi_hi = cat(entries[0][5].sr, entries[0][4].sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries[0][3].sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries[0][8].sr, entries[0][7].sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries[0][6].sr)
node r_array_hi_hi_lo = cat(entries[0][10].sr, entries[0][9].sr)
node r_array_hi_hi_hi = cat(entries[0][12].sr, entries[0][11].sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries[0][2].sx, entries[0][1].sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries[0][0].sx)
node r_array_lo_hi_hi_1 = cat(entries[0][5].sx, entries[0][4].sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries[0][3].sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries[0][8].sx, entries[0][7].sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries[0][6].sx)
node r_array_hi_hi_lo_1 = cat(entries[0][10].sx, entries[0][9].sx)
node r_array_hi_hi_hi_1 = cat(entries[0][12].sx, entries[0][11].sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(io.ptw.status.mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok[0], _r_array_T_3)
node _r_array_T_5 = cat(UInt<1>(0h1), _r_array_T_4)
wire r_array : UInt<14>[1]
connect r_array[0], _r_array_T_5
node w_array_lo_lo_hi = cat(entries[0][2].sw, entries[0][1].sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries[0][0].sw)
node w_array_lo_hi_hi = cat(entries[0][5].sw, entries[0][4].sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries[0][3].sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries[0][8].sw, entries[0][7].sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries[0][6].sw)
node w_array_hi_hi_lo = cat(entries[0][10].sw, entries[0][9].sw)
node w_array_hi_hi_hi = cat(entries[0][12].sw, entries[0][11].sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok[0], _w_array_T)
node _w_array_T_2 = cat(UInt<1>(0h1), _w_array_T_1)
wire w_array : UInt<14>[1]
connect w_array[0], _w_array_T_2
node x_array_lo_lo_hi = cat(entries[0][2].sx, entries[0][1].sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries[0][0].sx)
node x_array_lo_hi_hi = cat(entries[0][5].sx, entries[0][4].sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries[0][3].sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries[0][8].sx, entries[0][7].sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries[0][6].sx)
node x_array_hi_hi_lo = cat(entries[0][10].sx, entries[0][9].sx)
node x_array_hi_hi_hi = cat(entries[0][12].sx, entries[0][11].sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok[0], _x_array_T)
node _x_array_T_2 = cat(UInt<1>(0h1), _x_array_T_1)
wire x_array : UInt<14>[1]
connect x_array[0], _x_array_T_2
node _pr_array_T = mux(prot_r[0], UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(normal_entries[0][2].pr, normal_entries[0][1].pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, normal_entries[0][0].pr)
node pr_array_lo_hi_hi = cat(normal_entries[0][5].pr, normal_entries[0][4].pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, normal_entries[0][3].pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(normal_entries[0][8].pr, normal_entries[0][7].pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, normal_entries[0][6].pr)
node pr_array_hi_hi_hi = cat(normal_entries[0][11].pr, normal_entries[0][10].pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, normal_entries[0][9].pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = not(ptw_ae_array[0])
node _pr_array_T_4 = and(_pr_array_T_2, _pr_array_T_3)
wire pr_array : UInt<14>[1]
connect pr_array[0], _pr_array_T_4
node _pw_array_T = mux(prot_w[0], UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(normal_entries[0][2].pw, normal_entries[0][1].pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, normal_entries[0][0].pw)
node pw_array_lo_hi_hi = cat(normal_entries[0][5].pw, normal_entries[0][4].pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, normal_entries[0][3].pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(normal_entries[0][8].pw, normal_entries[0][7].pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, normal_entries[0][6].pw)
node pw_array_hi_hi_hi = cat(normal_entries[0][11].pw, normal_entries[0][10].pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, normal_entries[0][9].pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = not(ptw_ae_array[0])
node _pw_array_T_4 = and(_pw_array_T_2, _pw_array_T_3)
wire pw_array : UInt<14>[1]
connect pw_array[0], _pw_array_T_4
node _px_array_T = mux(prot_x[0], UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(normal_entries[0][2].px, normal_entries[0][1].px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, normal_entries[0][0].px)
node px_array_lo_hi_hi = cat(normal_entries[0][5].px, normal_entries[0][4].px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, normal_entries[0][3].px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(normal_entries[0][8].px, normal_entries[0][7].px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, normal_entries[0][6].px)
node px_array_hi_hi_hi = cat(normal_entries[0][11].px, normal_entries[0][10].px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, normal_entries[0][9].px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = not(ptw_ae_array[0])
node _px_array_T_4 = and(_px_array_T_2, _px_array_T_3)
wire px_array : UInt<14>[1]
connect px_array[0], _px_array_T_4
node _eff_array_T = mux(prot_eff[0], UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(normal_entries[0][2].eff, normal_entries[0][1].eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, normal_entries[0][0].eff)
node eff_array_lo_hi_hi = cat(normal_entries[0][5].eff, normal_entries[0][4].eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, normal_entries[0][3].eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(normal_entries[0][8].eff, normal_entries[0][7].eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, normal_entries[0][6].eff)
node eff_array_hi_hi_hi = cat(normal_entries[0][11].eff, normal_entries[0][10].eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, normal_entries[0][9].eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node _eff_array_T_2 = cat(_eff_array_T, _eff_array_T_1)
wire eff_array : UInt<14>[1]
connect eff_array[0], _eff_array_T_2
node _c_array_T = mux(cacheable[0], UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, normal_entries[0][0].c)
node c_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, normal_entries[0][3].c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, normal_entries[0][6].c)
node c_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, normal_entries[0][9].c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node _c_array_T_2 = cat(_c_array_T, _c_array_T_1)
wire c_array : UInt<14>[1]
connect c_array[0], _c_array_T_2
node _paa_array_T = mux(prot_aa[0], UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(normal_entries[0][2].paa, normal_entries[0][1].paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, normal_entries[0][0].paa)
node paa_array_lo_hi_hi = cat(normal_entries[0][5].paa, normal_entries[0][4].paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, normal_entries[0][3].paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(normal_entries[0][8].paa, normal_entries[0][7].paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, normal_entries[0][6].paa)
node paa_array_hi_hi_hi = cat(normal_entries[0][11].paa, normal_entries[0][10].paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, normal_entries[0][9].paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node _paa_array_T_2 = cat(_paa_array_T, _paa_array_T_1)
wire paa_array : UInt<14>[1]
connect paa_array[0], _paa_array_T_2
node _pal_array_T = mux(prot_al[0], UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(normal_entries[0][2].pal, normal_entries[0][1].pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, normal_entries[0][0].pal)
node pal_array_lo_hi_hi = cat(normal_entries[0][5].pal, normal_entries[0][4].pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, normal_entries[0][3].pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(normal_entries[0][8].pal, normal_entries[0][7].pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, normal_entries[0][6].pal)
node pal_array_hi_hi_hi = cat(normal_entries[0][11].pal, normal_entries[0][10].pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, normal_entries[0][9].pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node _pal_array_T_2 = cat(_pal_array_T, _pal_array_T_1)
wire pal_array : UInt<14>[1]
connect pal_array[0], _pal_array_T_2
node _paa_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0))
node _paa_array_if_cached_T_1 = or(paa_array[0], _paa_array_if_cached_T)
wire paa_array_if_cached : UInt<14>[1]
connect paa_array_if_cached[0], _paa_array_if_cached_T_1
node _pal_array_if_cached_T = mux(UInt<1>(0h1), c_array[0], UInt<1>(0h0))
node _pal_array_if_cached_T_1 = or(pal_array[0], _pal_array_if_cached_T)
wire pal_array_if_cached : UInt<14>[1]
connect pal_array_if_cached[0], _pal_array_if_cached_T_1
node _prefetchable_array_T = and(cacheable[0], homogeneous[0])
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(normal_entries[0][2].c, normal_entries[0][1].c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, normal_entries[0][0].c)
node prefetchable_array_lo_hi_hi = cat(normal_entries[0][5].c, normal_entries[0][4].c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, normal_entries[0][3].c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(normal_entries[0][8].c, normal_entries[0][7].c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, normal_entries[0][6].c)
node prefetchable_array_hi_hi_hi = cat(normal_entries[0][11].c, normal_entries[0][10].c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, normal_entries[0][9].c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node _prefetchable_array_T_3 = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
wire prefetchable_array : UInt<14>[1]
connect prefetchable_array[0], _prefetchable_array_T_3
node _misaligned_T = dshl(UInt<1>(0h1), io.req[0].bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req[0].bits.vaddr, _misaligned_T_2)
node _misaligned_T_4 = orr(_misaligned_T_3)
wire misaligned : UInt<1>[1]
connect misaligned[0], _misaligned_T_4
wire bad_va : UInt<1>[1]
connect bad_va[0], UInt<1>(0h0)
node _cmd_lrsc_T = eq(io.req[0].bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req[0].bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node _cmd_lrsc_T_3 = and(UInt<1>(0h1), _cmd_lrsc_T_2)
wire cmd_lrsc : UInt<1>[1]
connect cmd_lrsc[0], _cmd_lrsc_T_3
node _cmd_amo_logical_T = eq(io.req[0].bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node _cmd_amo_logical_T_7 = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
wire cmd_amo_logical : UInt<1>[1]
connect cmd_amo_logical[0], _cmd_amo_logical_T_7
node _cmd_amo_arithmetic_T = eq(io.req[0].bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req[0].bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req[0].bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req[0].bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req[0].bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node _cmd_amo_arithmetic_T_9 = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
wire cmd_amo_arithmetic : UInt<1>[1]
connect cmd_amo_arithmetic[0], _cmd_amo_arithmetic_T_9
node _cmd_read_T = eq(io.req[0].bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req[0].bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req[0].bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req[0].bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req[0].bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req[0].bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req[0].bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node _cmd_read_T_24 = or(_cmd_read_T_6, _cmd_read_T_23)
wire cmd_read : UInt<1>[1]
connect cmd_read[0], _cmd_read_T_24
node _cmd_write_T = eq(io.req[0].bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req[0].bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req[0].bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req[0].bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req[0].bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req[0].bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req[0].bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req[0].bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req[0].bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req[0].bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req[0].bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req[0].bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node _cmd_write_T_22 = or(_cmd_write_T_4, _cmd_write_T_21)
wire cmd_write : UInt<1>[1]
connect cmd_write[0], _cmd_write_T_22
node _cmd_write_perms_T = eq(io.req[0].bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = and(UInt<1>(0h0), _cmd_write_perms_T)
node _cmd_write_perms_T_2 = or(cmd_write[0], _cmd_write_perms_T_1)
wire cmd_write_perms : UInt<1>[1]
connect cmd_write_perms[0], _cmd_write_perms_T_2
node _lrscAllowed_T = mux(UInt<1>(0h0), UInt<1>(0h0), c_array[0])
wire lrscAllowed : UInt<14>[1]
connect lrscAllowed[0], _lrscAllowed_T
node _ae_array_T = mux(misaligned[0], eff_array[0], UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed[0])
node _ae_array_T_2 = mux(cmd_lrsc[0], _ae_array_T_1, UInt<1>(0h0))
node _ae_array_T_3 = or(_ae_array_T, _ae_array_T_2)
wire ae_array : UInt<14>[1]
connect ae_array[0], _ae_array_T_3
node _ae_valid_array_T = eq(do_refill, UInt<1>(0h0))
node _ae_valid_array_T_1 = cat(UInt<1>(0h1), _ae_valid_array_T)
node _ae_valid_array_T_2 = mux(UInt<1>(0h1), UInt<12>(0hfff), UInt<12>(0h0))
node _ae_valid_array_T_3 = cat(_ae_valid_array_T_1, _ae_valid_array_T_2)
wire ae_valid_array : UInt<14>[1]
connect ae_valid_array[0], _ae_valid_array_T_3
node _ae_ld_array_T = not(pr_array[0])
node _ae_ld_array_T_1 = or(ae_array[0], _ae_ld_array_T)
node _ae_ld_array_T_2 = mux(cmd_read[0], _ae_ld_array_T_1, UInt<1>(0h0))
wire ae_ld_array : UInt<14>[1]
connect ae_ld_array[0], _ae_ld_array_T_2
node _ae_st_array_T = not(pw_array[0])
node _ae_st_array_T_1 = or(ae_array[0], _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms[0], _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(pal_array_if_cached[0])
node _ae_st_array_T_4 = mux(cmd_amo_logical[0], _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(paa_array_if_cached[0])
node _ae_st_array_T_7 = mux(cmd_amo_arithmetic[0], _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
wire ae_st_array : UInt<14>[1]
connect ae_st_array[0], _ae_st_array_T_8
node _must_alloc_array_T = not(paa_array[0])
node _must_alloc_array_T_1 = mux(cmd_amo_logical[0], _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array[0])
node _must_alloc_array_T_3 = mux(cmd_amo_arithmetic[0], _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(UInt<14>(0h0))
node _must_alloc_array_T_6 = mux(cmd_lrsc[0], _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
wire must_alloc_array : UInt<14>[1]
connect must_alloc_array[0], _must_alloc_array_T_7
node _ma_ld_array_T = and(misaligned[0], cmd_read[0])
node _ma_ld_array_T_1 = not(eff_array[0])
node _ma_ld_array_T_2 = mux(_ma_ld_array_T, _ma_ld_array_T_1, UInt<1>(0h0))
wire ma_ld_array : UInt<14>[1]
connect ma_ld_array[0], _ma_ld_array_T_2
node _ma_st_array_T = and(misaligned[0], cmd_write[0])
node _ma_st_array_T_1 = not(eff_array[0])
node _ma_st_array_T_2 = mux(_ma_st_array_T, _ma_st_array_T_1, UInt<1>(0h0))
wire ma_st_array : UInt<14>[1]
connect ma_st_array[0], _ma_st_array_T_2
node _pf_ld_array_T = or(r_array[0], ptw_ae_array[0])
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = mux(cmd_read[0], _pf_ld_array_T_1, UInt<1>(0h0))
wire pf_ld_array : UInt<14>[1]
connect pf_ld_array[0], _pf_ld_array_T_2
node _pf_st_array_T = or(w_array[0], ptw_ae_array[0])
node _pf_st_array_T_1 = not(_pf_st_array_T)
node _pf_st_array_T_2 = mux(cmd_write_perms[0], _pf_st_array_T_1, UInt<1>(0h0))
wire pf_st_array : UInt<14>[1]
connect pf_st_array[0], _pf_st_array_T_2
node _pf_inst_array_T = or(x_array[0], ptw_ae_array[0])
node _pf_inst_array_T_1 = not(_pf_inst_array_T)
wire pf_inst_array : UInt<14>[1]
connect pf_inst_array[0], _pf_inst_array_T_1
node _tlb_hit_T = orr(real_hits[0])
wire tlb_hit : UInt<1>[1]
connect tlb_hit[0], _tlb_hit_T
node _tlb_miss_T = eq(bad_va[0], UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled[0], _tlb_miss_T)
node _tlb_miss_T_2 = eq(tlb_hit[0], UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
wire tlb_miss : UInt<1>[1]
connect tlb_miss[0], _tlb_miss_T_3
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req[0].valid, vm_enabled[0])
when _T_23 :
node _T_24 = or(sector_hits[0][0], sector_hits[0][1])
node _T_25 = or(_T_24, sector_hits[0][2])
node _T_26 = or(_T_25, sector_hits[0][3])
node _T_27 = or(_T_26, sector_hits[0][4])
node _T_28 = or(_T_27, sector_hits[0][5])
node _T_29 = or(_T_28, sector_hits[0][6])
node _T_30 = or(_T_29, sector_hits[0][7])
when _T_30 :
node lo_lo = cat(sector_hits[0][1], sector_hits[0][0])
node lo_hi = cat(sector_hits[0][3], sector_hits[0][2])
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits[0][5], sector_hits[0][4])
node hi_hi = cat(sector_hits[0][7], sector_hits[0][6])
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_reg_touch_way_sized = bits(_T_38, 2, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg, 5, 3)
node state_reg_right_subtree_state = bits(state_reg, 2, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1)
node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0))
node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1)
node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0)
node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0))
node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3)
node _state_reg_T_5 = bits(_state_reg_T, 0, 0)
node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0)
node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0))
node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1)
node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4)
node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8)
node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9)
node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0)
node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1)
node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0))
node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1)
node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0)
node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0)
node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0))
node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14)
node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0)
node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0)
node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0))
node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2)
node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15)
node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19)
node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state)
node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10)
node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21)
connect state_reg, _state_reg_T_22
node _T_39 = or(superpage_hits[0][0], superpage_hits[0][1])
node _T_40 = or(_T_39, superpage_hits[0][2])
node _T_41 = or(_T_40, superpage_hits[0][3])
when _T_41 :
node lo_3 = cat(superpage_hits[0][1], superpage_hits[0][0])
node hi_3 = cat(superpage_hits[0][3], superpage_hits[0][2])
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized_1 = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 1, 1)
node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0))
node state_reg_left_subtree_state_3 = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state_3 = bits(state_reg_1, 0, 0)
node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 0, 0)
node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0)
node _state_reg_T_25 = eq(_state_reg_T_24, UInt<1>(0h0))
node _state_reg_T_26 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_25)
node _state_reg_T_27 = bits(state_reg_touch_way_sized_1, 0, 0)
node _state_reg_T_28 = bits(_state_reg_T_27, 0, 0)
node _state_reg_T_29 = eq(_state_reg_T_28, UInt<1>(0h0))
node _state_reg_T_30 = mux(state_reg_set_left_older_3, _state_reg_T_29, state_reg_right_subtree_state_3)
node state_reg_hi_3 = cat(state_reg_set_left_older_3, _state_reg_T_26)
node _state_reg_T_31 = cat(state_reg_hi_3, _state_reg_T_30)
connect state_reg_1, _state_reg_T_31
node _multipleHits_T = bits(real_hits[0], 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits[0], 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_49 = or(_multipleHits_T_47, _multipleHits_T_48)
wire multipleHits : UInt<1>[1]
connect multipleHits[0], _multipleHits_T_49
node _io_miss_rdy_T = eq(state, UInt<2>(0h0))
connect io.miss_rdy, _io_miss_rdy_T
connect io.req[0].ready, UInt<1>(0h1)
node _io_resp_0_pf_ld_T = and(bad_va[0], cmd_read[0])
node _io_resp_0_pf_ld_T_1 = and(pf_ld_array[0], hits[0])
node _io_resp_0_pf_ld_T_2 = orr(_io_resp_0_pf_ld_T_1)
node _io_resp_0_pf_ld_T_3 = or(_io_resp_0_pf_ld_T, _io_resp_0_pf_ld_T_2)
connect io.resp[0].pf.ld, _io_resp_0_pf_ld_T_3
node _io_resp_0_pf_st_T = and(bad_va[0], cmd_write_perms[0])
node _io_resp_0_pf_st_T_1 = and(pf_st_array[0], hits[0])
node _io_resp_0_pf_st_T_2 = orr(_io_resp_0_pf_st_T_1)
node _io_resp_0_pf_st_T_3 = or(_io_resp_0_pf_st_T, _io_resp_0_pf_st_T_2)
connect io.resp[0].pf.st, _io_resp_0_pf_st_T_3
node _io_resp_0_pf_inst_T = and(pf_inst_array[0], hits[0])
node _io_resp_0_pf_inst_T_1 = orr(_io_resp_0_pf_inst_T)
node _io_resp_0_pf_inst_T_2 = or(bad_va[0], _io_resp_0_pf_inst_T_1)
connect io.resp[0].pf.inst, _io_resp_0_pf_inst_T_2
node _io_resp_0_ae_ld_T = and(ae_valid_array[0], ae_ld_array[0])
node _io_resp_0_ae_ld_T_1 = and(_io_resp_0_ae_ld_T, hits[0])
node _io_resp_0_ae_ld_T_2 = orr(_io_resp_0_ae_ld_T_1)
connect io.resp[0].ae.ld, _io_resp_0_ae_ld_T_2
node _io_resp_0_ae_st_T = and(ae_valid_array[0], ae_st_array[0])
node _io_resp_0_ae_st_T_1 = and(_io_resp_0_ae_st_T, hits[0])
node _io_resp_0_ae_st_T_2 = orr(_io_resp_0_ae_st_T_1)
connect io.resp[0].ae.st, _io_resp_0_ae_st_T_2
node _io_resp_0_ae_inst_T = not(px_array[0])
node _io_resp_0_ae_inst_T_1 = and(ae_valid_array[0], _io_resp_0_ae_inst_T)
node _io_resp_0_ae_inst_T_2 = and(_io_resp_0_ae_inst_T_1, hits[0])
node _io_resp_0_ae_inst_T_3 = orr(_io_resp_0_ae_inst_T_2)
connect io.resp[0].ae.inst, _io_resp_0_ae_inst_T_3
node _io_resp_0_ma_ld_T = and(ma_ld_array[0], hits[0])
node _io_resp_0_ma_ld_T_1 = orr(_io_resp_0_ma_ld_T)
connect io.resp[0].ma.ld, _io_resp_0_ma_ld_T_1
node _io_resp_0_ma_st_T = and(ma_st_array[0], hits[0])
node _io_resp_0_ma_st_T_1 = orr(_io_resp_0_ma_st_T)
connect io.resp[0].ma.st, _io_resp_0_ma_st_T_1
connect io.resp[0].ma.inst, UInt<1>(0h0)
node _io_resp_0_cacheable_T = and(c_array[0], hits[0])
node _io_resp_0_cacheable_T_1 = orr(_io_resp_0_cacheable_T)
connect io.resp[0].cacheable, _io_resp_0_cacheable_T_1
node _io_resp_0_must_alloc_T = and(must_alloc_array[0], hits[0])
node _io_resp_0_must_alloc_T_1 = orr(_io_resp_0_must_alloc_T)
connect io.resp[0].must_alloc, _io_resp_0_must_alloc_T_1
node _io_resp_0_prefetchable_T = and(prefetchable_array[0], hits[0])
node _io_resp_0_prefetchable_T_1 = orr(_io_resp_0_prefetchable_T)
node _io_resp_0_prefetchable_T_2 = and(_io_resp_0_prefetchable_T_1, UInt<1>(0h1))
connect io.resp[0].prefetchable, _io_resp_0_prefetchable_T_2
node _io_resp_0_miss_T = or(do_refill, tlb_miss[0])
node _io_resp_0_miss_T_1 = or(_io_resp_0_miss_T, multipleHits[0])
connect io.resp[0].miss, _io_resp_0_miss_T_1
node _io_resp_0_paddr_T = bits(io.req[0].bits.vaddr, 11, 0)
node _io_resp_0_paddr_T_1 = cat(ppn[0], _io_resp_0_paddr_T)
connect io.resp[0].paddr, _io_resp_0_paddr_T_1
connect io.resp[0].size, io.req[0].bits.size
connect io.resp[0].cmd, io.req[0].bits.cmd
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag | module NBDTLB_1( // @[tlb.scala:17:7]
input clock, // @[tlb.scala:17:7]
input reset, // @[tlb.scala:17:7]
input io_req_0_valid, // @[tlb.scala:19:14]
input [33:0] io_req_0_bits_vaddr, // @[tlb.scala:19:14]
input [1:0] io_req_0_bits_size, // @[tlb.scala:19:14]
input [4:0] io_req_0_bits_cmd, // @[tlb.scala:19:14]
output [31:0] io_resp_0_paddr, // @[tlb.scala:19:14]
output io_resp_0_pf_ld, // @[tlb.scala:19:14]
output io_resp_0_pf_st, // @[tlb.scala:19:14]
output io_resp_0_ae_ld, // @[tlb.scala:19:14]
output io_resp_0_ae_st, // @[tlb.scala:19:14]
output io_resp_0_ma_ld, // @[tlb.scala:19:14]
output io_resp_0_ma_st, // @[tlb.scala:19:14]
output io_resp_0_cacheable, // @[tlb.scala:19:14]
output [20:0] io_ptw_req_bits_bits_addr, // @[tlb.scala:19:14]
input io_ptw_resp_valid, // @[tlb.scala:19:14]
input [43:0] io_ptw_resp_bits_pte_ppn // @[tlb.scala:19:14]
);
wire _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_11_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_10_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_9_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_8_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_7_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_6_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_5_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_4_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_3_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_2_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_1_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_c; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_eff; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_paa; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_pal; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_pr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_px; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_pw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_sr; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_sx; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_sw; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_ae; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_g; // @[tlb.scala:214:45]
wire _normal_entries_WIRE_24_0_u; // @[tlb.scala:214:45]
wire [19:0] _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:214:45]
wire _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_12_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_12_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_11_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_11_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_10_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_10_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_9_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_9_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_8_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_8_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_7_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_7_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_6_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_6_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_5_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_5_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_4_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_4_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_3_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_3_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_2_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_2_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_1_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_1_ppn; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_c; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_eff; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_paa; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_pal; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_pr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_px; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_pw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_sr; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_sx; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_sw; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_ae; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_g; // @[tlb.scala:213:38]
wire _entries_WIRE_26_0_u; // @[tlb.scala:213:38]
wire [19:0] _entries_WIRE_26_0_ppn; // @[tlb.scala:213:38]
wire io_req_0_valid_0 = io_req_0_valid; // @[tlb.scala:17:7]
wire [33:0] io_req_0_bits_vaddr_0 = io_req_0_bits_vaddr; // @[tlb.scala:17:7]
wire [1:0] io_req_0_bits_size_0 = io_req_0_bits_size; // @[tlb.scala:17:7]
wire [4:0] io_req_0_bits_cmd_0 = io_req_0_bits_cmd; // @[tlb.scala:17:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[tlb.scala:17:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[tlb.scala:17:7]
wire [20:0] io_ptw_req_bits_bits_addr_0 = 21'h0; // @[tlb.scala:17:7, :124:29]
wire [11:0] _ae_valid_array_T_2 = 12'hFFF; // @[tlb.scala:257:46]
wire [34:0] _prot_r_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_r_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_w_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_w_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_al_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_al_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_aa_T_2 = 35'h0; // @[Parameters.scala:137:46]
wire [34:0] _prot_aa_T_3 = 35'h0; // @[Parameters.scala:137:46]
wire [13:0] _hits_T_1 = 14'h2000; // @[tlb.scala:121:49, :175:31]
wire [13:0] hits_0 = 14'h2000; // @[tlb.scala:121:49, :175:31]
wire [19:0] _ppn_T_2 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_3 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_4 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_5 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_6 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_7 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_8 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_9 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_10 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_11 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_12 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_13 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_14 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_16 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_17 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_18 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_19 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_20 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_21 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_22 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_23 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_24 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_25 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_26 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_27 = 20'h0; // @[Mux.scala:30:73]
wire [12:0] _real_hits_T = 13'h0; // @[tlb.scala:174:44]
wire [12:0] real_hits_0 = 13'h0; // @[tlb.scala:121:49]
wire [12:0] _priv_rw_ok_T_6 = 13'h0; // @[tlb.scala:217:108]
wire [12:0] _r_array_T_2 = 13'h0; // @[tlb.scala:219:98]
wire [1:0] _ae_valid_array_T_1 = 2'h3; // @[tlb.scala:256:84]
wire [13:0] _ae_valid_array_T_3 = 14'h3FFF; // @[tlb.scala:256:41]
wire [13:0] ae_valid_array_0 = 14'h3FFF; // @[tlb.scala:121:49]
wire [13:0] _must_alloc_array_T_5 = 14'h3FFF; // @[tlb.scala:266:32]
wire [6:0] real_hits_hi = 7'h0; // @[tlb.scala:174:44]
wire [6:0] _multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[tlb.scala:17:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[tlb.scala:17:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[tlb.scala:17:7, :19:14]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Misc.scala:181:37]
wire [5:0] real_hits_lo = 6'h0; // @[Misc.scala:181:37]
wire [5:0] _multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[tlb.scala:17:7, :19:14]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[tlb.scala:17:7, :19:14]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[tlb.scala:17:7, :19:14]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[tlb.scala:17:7, :19:14]
wire [31:0] io_ptw_status_isa = 32'h0; // @[tlb.scala:17:7, :19:14]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[tlb.scala:17:7, :19:14]
wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[tlb.scala:17:7, :19:14]
wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[Misc.scala:182:39]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Misc.scala:182:39]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Misc.scala:182:39]
wire [3:0] real_hits_hi_hi = 4'h0; // @[Misc.scala:182:39]
wire [3:0] _multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[tlb.scala:17:7, :19:14]
wire [32:0] io_sfence_bits_addr = 33'h0; // @[tlb.scala:17:7, :19:14]
wire [32:0] io_ptw_resp_bits_gpa_bits = 33'h0; // @[tlb.scala:17:7, :19:14]
wire [33:0] io_resp_0_gpa = 34'h0; // @[tlb.scala:17:7]
wire [33:0] _mpu_ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_1 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_3 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_5 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_7 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_9 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_11 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_13 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_15 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_17 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_19 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_21 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_23 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _ppn_data_WIRE_25 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_1 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_3 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_5 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_7 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_9 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_11 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_13 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_15 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_17 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_19 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_21 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_23 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _entries_WIRE_25 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_1 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_3 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_5 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_7 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_9 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_11 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_13 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_15 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_17 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_19 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_21 = 34'h0; // @[tlb.scala:60:79]
wire [33:0] _normal_entries_WIRE_23 = 34'h0; // @[tlb.scala:60:79]
wire [1:0] io_req_0_bits_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_dprv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_sxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_uxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_fs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_mpp = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[tlb.scala:17:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[tlb.scala:17:7]
wire [1:0] _pmp_0_io_prv_T_2 = 2'h0; // @[tlb.scala:157:25]
wire [1:0] real_hits_lo_lo_hi = 2'h0; // @[tlb.scala:174:44]
wire [1:0] real_hits_lo_hi_hi = 2'h0; // @[tlb.scala:174:44]
wire [1:0] real_hits_hi_lo_hi = 2'h0; // @[tlb.scala:174:44]
wire [1:0] real_hits_hi_hi_lo = 2'h0; // @[tlb.scala:174:44]
wire [1:0] real_hits_hi_hi_hi = 2'h0; // @[tlb.scala:174:44]
wire [1:0] special_entry_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_0_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_1_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_2_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_3_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_4_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_5_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_6_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] sectored_entries_7_data_hi_hi_lo = 2'h0; // @[tlb.scala:97:26]
wire [1:0] _multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] _multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] io_ptw_resp_bits_level = 2'h2; // @[tlb.scala:17:7]
wire [1:0] _special_entry_level_T = 2'h2; // @[package.scala:163:13]
wire [1:0] special_entry_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_0_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_1_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_2_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_3_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_4_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_5_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_6_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_7_data_hi_lo_hi = 2'h2; // @[tlb.scala:97:26]
wire [2:0] real_hits_lo_lo = 3'h0; // @[tlb.scala:174:44]
wire [2:0] real_hits_lo_hi = 3'h0; // @[tlb.scala:174:44]
wire [2:0] real_hits_hi_lo = 3'h0; // @[tlb.scala:174:44]
wire [2:0] waddr = 3'h0; // @[tlb.scala:205:22]
wire [2:0] state_reg_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] state_reg_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] _multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] _multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] _multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire io_req_0_ready = 1'h1; // @[tlb.scala:17:7]
wire io_miss_rdy = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_req_ready = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_req_bits_valid = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_d = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_a = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_u = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_w = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_r = 1'h1; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_v = 1'h1; // @[tlb.scala:17:7]
wire priv_uses_vm = 1'h1; // @[tlb.scala:140:27]
wire _vm_enabled_T_3 = 1'h1; // @[tlb.scala:141:112]
wire _homogeneous_T_24 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_25 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_39 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _homogeneous_T_40 = 1'h1; // @[TLBPermissions.scala:87:22]
wire _prot_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_w_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_al_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _prot_aa_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _hits_T = 1'h1; // @[tlb.scala:175:32]
wire _ppn_T = 1'h1; // @[tlb.scala:176:47]
wire newEntry_u = 1'h1; // @[tlb.scala:181:24]
wire newEntry_sw = 1'h1; // @[tlb.scala:181:24]
wire newEntry_sr = 1'h1; // @[tlb.scala:181:24]
wire _newEntry_sr_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sr_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sr_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _newEntry_sr_T_5 = 1'h1; // @[PTW.scala:149:35]
wire _newEntry_sw_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sw_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sw_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _newEntry_sw_T_5 = 1'h1; // @[PTW.scala:151:35]
wire _newEntry_sw_T_6 = 1'h1; // @[PTW.scala:151:40]
wire _newEntry_sx_T_2 = 1'h1; // @[PTW.scala:141:38]
wire _newEntry_sx_T_3 = 1'h1; // @[PTW.scala:141:32]
wire _newEntry_sx_T_4 = 1'h1; // @[PTW.scala:141:52]
wire _priv_rw_ok_T = 1'h1; // @[tlb.scala:217:40]
wire _priv_rw_ok_T_1 = 1'h1; // @[tlb.scala:217:48]
wire _ae_valid_array_T = 1'h1; // @[tlb.scala:256:118]
wire _tlb_miss_T = 1'h1; // @[tlb.scala:274:49]
wire _tlb_miss_T_2 = 1'h1; // @[tlb.scala:274:63]
wire _io_miss_rdy_T = 1'h1; // @[tlb.scala:292:24]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[tlb.scala:314:28]
wire io_req_0_bits_passthrough = 1'h0; // @[tlb.scala:17:7]
wire io_req_0_bits_v = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_miss = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gpa_is_pte = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_ld = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_st = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_gf_inst = 1'h0; // @[tlb.scala:17:7]
wire io_resp_0_ma_inst = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_valid = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_rs1 = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_rs2 = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_asid = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_hv = 1'h0; // @[tlb.scala:17:7]
wire io_sfence_bits_hg = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_valid = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_need_gpa = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_ae_ptw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_ae_final = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pf = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gf = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_hx = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_g = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_pte_x = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_homogeneous = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gpa_valid = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_debug = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_cease = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_wfi = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_dv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_v = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sd = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mpv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_tvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mxr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sum = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mprv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_spp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mpie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_ube = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_spie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_upie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_mie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_hie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_sie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_status_uie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_hu = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_spv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_debug = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_cease = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_dv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_v = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sd = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_gva = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tw = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sum = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_spp = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_ube = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_spie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_upie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_mie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_hie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_sie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_gstatus_uie = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[tlb.scala:17:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[tlb.scala:17:7]
wire io_kill = 1'h0; // @[tlb.scala:17:7]
wire priv_s = 1'h0; // @[tlb.scala:139:20]
wire _vm_enabled_T = 1'h0; // @[tlb.scala:141:63]
wire _vm_enabled_T_1 = 1'h0; // @[tlb.scala:141:44]
wire _vm_enabled_T_2 = 1'h0; // @[tlb.scala:141:93]
wire _vm_enabled_T_4 = 1'h0; // @[tlb.scala:141:109]
wire vm_enabled_0 = 1'h0; // @[tlb.scala:121:49]
wire do_refill = 1'h0; // @[tlb.scala:146:29]
wire _invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire invalidate_refill = 1'h0; // @[tlb.scala:147:88]
wire _mpu_ppn_T = 1'h0; // @[tlb.scala:150:35]
wire _pmp_0_io_prv_T = 1'h0; // @[tlb.scala:157:50]
wire _pmp_0_io_prv_T_1 = 1'h0; // @[tlb.scala:157:36]
wire _cacheable_T_10 = 1'h0; // @[Mux.scala:30:73]
wire _prot_x_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _prot_eff_T_22 = 1'h0; // @[Mux.scala:30:73]
wire _sector_hits_T = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_7 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_14 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_21 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_28 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_35 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_42 = 1'h0; // @[package.scala:81:59]
wire _sector_hits_T_49 = 1'h0; // @[package.scala:81:59]
wire _superpage_hits_T_3 = 1'h0; // @[tlb.scala:74:20]
wire _superpage_hits_T_7 = 1'h0; // @[tlb.scala:74:20]
wire _superpage_hits_T_11 = 1'h0; // @[tlb.scala:74:20]
wire _superpage_hits_T_15 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_3 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_4 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_8 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_9 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_13 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_14 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_18 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_19 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_23 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_24 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_28 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_29 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_33 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_34 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_38 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_39 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_43 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_44 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_48 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_49 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_53 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_54 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_58 = 1'h0; // @[tlb.scala:74:20]
wire _hitsVec_T_59 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_T_64 = 1'h0; // @[tlb.scala:173:69]
wire _hitsVec_WIRE_0 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_1 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_2 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_3 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_4 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_5 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_6 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_7 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_8 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_9 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_10 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_11 = 1'h0; // @[tlb.scala:173:38]
wire _hitsVec_WIRE_12 = 1'h0; // @[tlb.scala:173:38]
wire hitsVec_0_0 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_1 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_2 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_3 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_4 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_5 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_6 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_7 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_8 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_9 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_10 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_11 = 1'h0; // @[tlb.scala:121:49]
wire hitsVec_0_12 = 1'h0; // @[tlb.scala:121:49]
wire newEntry_g = 1'h0; // @[tlb.scala:181:24]
wire newEntry_ae = 1'h0; // @[tlb.scala:181:24]
wire newEntry_sx = 1'h0; // @[tlb.scala:181:24]
wire newEntry_fragmented_superpage = 1'h0; // @[tlb.scala:181:24]
wire _newEntry_sr_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sw_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sx_T = 1'h0; // @[PTW.scala:141:47]
wire _newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44]
wire _newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35]
wire _superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13]
wire bad_va_0 = 1'h0; // @[tlb.scala:121:49]
wire _cmd_write_perms_T_1 = 1'h0; // @[tlb.scala:250:29]
wire _tlb_hit_T = 1'h0; // @[tlb.scala:273:44]
wire tlb_hit_0 = 1'h0; // @[tlb.scala:121:49]
wire _tlb_miss_T_1 = 1'h0; // @[tlb.scala:274:46]
wire _tlb_miss_T_3 = 1'h0; // @[tlb.scala:274:60]
wire tlb_miss_0 = 1'h0; // @[tlb.scala:121:49]
wire state_reg_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire state_reg_left_subtree_state_3 = 1'h0; // @[package.scala:163:13]
wire state_reg_right_subtree_state_3 = 1'h0; // @[Replacement.scala:198:38]
wire _multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire _multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire _multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire _multipleHits_T_49 = 1'h0; // @[Misc.scala:183:49]
wire multipleHits_0 = 1'h0; // @[tlb.scala:121:49]
wire _io_resp_0_pf_ld_T = 1'h0; // @[tlb.scala:295:38]
wire _io_resp_0_pf_st_T = 1'h0; // @[tlb.scala:296:38]
wire _io_resp_0_miss_T = 1'h0; // @[tlb.scala:307:35]
wire _io_resp_0_miss_T_1 = 1'h0; // @[tlb.scala:307:50]
wire _io_ptw_req_valid_T = 1'h0; // @[tlb.scala:313:29]
wire [1:0] io_resp_0_size = io_req_0_bits_size_0; // @[tlb.scala:17:7]
wire [4:0] io_resp_0_cmd = io_req_0_bits_cmd_0; // @[tlb.scala:17:7]
wire [31:0] _io_resp_0_paddr_T_1; // @[tlb.scala:308:28]
wire _io_resp_0_pf_ld_T_3; // @[tlb.scala:295:54]
wire _io_resp_0_pf_st_T_3; // @[tlb.scala:296:61]
wire _io_resp_0_pf_inst_T_2; // @[tlb.scala:297:37]
wire _io_resp_0_ae_ld_T_2; // @[tlb.scala:298:74]
wire _io_resp_0_ae_st_T_2; // @[tlb.scala:299:74]
wire _io_resp_0_ae_inst_T_3; // @[tlb.scala:300:74]
wire _io_resp_0_ma_ld_T_1; // @[tlb.scala:301:54]
wire _io_resp_0_ma_st_T_1; // @[tlb.scala:302:54]
wire _io_resp_0_cacheable_T_1; // @[tlb.scala:304:55]
wire _io_resp_0_must_alloc_T_1; // @[tlb.scala:305:64]
wire _io_resp_0_prefetchable_T_2; // @[tlb.scala:306:70]
wire io_resp_0_pf_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_pf_st_0; // @[tlb.scala:17:7]
wire io_resp_0_pf_inst; // @[tlb.scala:17:7]
wire io_resp_0_ae_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_ae_st_0; // @[tlb.scala:17:7]
wire io_resp_0_ae_inst; // @[tlb.scala:17:7]
wire io_resp_0_ma_ld_0; // @[tlb.scala:17:7]
wire io_resp_0_ma_st_0; // @[tlb.scala:17:7]
wire [31:0] io_resp_0_paddr_0; // @[tlb.scala:17:7]
wire io_resp_0_cacheable_0; // @[tlb.scala:17:7]
wire io_resp_0_must_alloc; // @[tlb.scala:17:7]
wire io_resp_0_prefetchable; // @[tlb.scala:17:7]
wire [20:0] _vpn_T = io_req_0_bits_vaddr_0[32:12]; // @[tlb.scala:17:7, :144:47]
wire [20:0] vpn_0 = _vpn_T; // @[tlb.scala:121:49, :144:47]
wire [20:0] _sector_hits_T_3 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_10 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_17 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_24 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_31 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_38 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_45 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _sector_hits_T_52 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _superpage_hits_T = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _superpage_hits_T_4 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _superpage_hits_T_8 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _superpage_hits_T_12 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_5 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_10 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_15 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_20 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_25 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_30 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_35 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_40 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_45 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_50 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_55 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [20:0] _hitsVec_T_60 = vpn_0; // @[tlb.scala:62:43, :121:49]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :145:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[tlb.scala:17:7, :145:44, :181:24]
wire [19:0] _mpu_ppn_data_T_14; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_13; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_12; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_11; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_10; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_9; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_8; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_7; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_6; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_5; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_4; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_3; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_2; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T_1; // @[tlb.scala:60:79]
wire _mpu_ppn_data_T; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T = _mpu_ppn_data_WIRE_1[0]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_fragmented_superpage = _mpu_ppn_data_T; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_1 = _mpu_ppn_data_WIRE_1[1]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_c = _mpu_ppn_data_T_1; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_2 = _mpu_ppn_data_WIRE_1[2]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_eff = _mpu_ppn_data_T_2; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_3 = _mpu_ppn_data_WIRE_1[3]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_paa = _mpu_ppn_data_T_3; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_4 = _mpu_ppn_data_WIRE_1[4]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_pal = _mpu_ppn_data_T_4; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_5 = _mpu_ppn_data_WIRE_1[5]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_pr = _mpu_ppn_data_T_5; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_6 = _mpu_ppn_data_WIRE_1[6]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_px = _mpu_ppn_data_T_6; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_7 = _mpu_ppn_data_WIRE_1[7]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_pw = _mpu_ppn_data_T_7; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_8 = _mpu_ppn_data_WIRE_1[8]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_sr = _mpu_ppn_data_T_8; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_9 = _mpu_ppn_data_WIRE_1[9]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_sx = _mpu_ppn_data_T_9; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_10 = _mpu_ppn_data_WIRE_1[10]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_sw = _mpu_ppn_data_T_10; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_11 = _mpu_ppn_data_WIRE_1[11]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_ae = _mpu_ppn_data_T_11; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_12 = _mpu_ppn_data_WIRE_1[12]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_g = _mpu_ppn_data_T_12; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_13 = _mpu_ppn_data_WIRE_1[13]; // @[tlb.scala:60:79]
wire _mpu_ppn_data_WIRE_u = _mpu_ppn_data_T_13; // @[tlb.scala:60:79]
assign _mpu_ppn_data_T_14 = _mpu_ppn_data_WIRE_1[33:14]; // @[tlb.scala:60:79]
wire [19:0] _mpu_ppn_data_WIRE_ppn = _mpu_ppn_data_T_14; // @[tlb.scala:60:79]
wire [21:0] _mpu_ppn_T_1 = io_req_0_bits_vaddr_0[33:12]; // @[tlb.scala:17:7, :150:134]
wire [21:0] _mpu_ppn_T_2 = _mpu_ppn_T_1; // @[tlb.scala:150:{20,134}]
wire [21:0] _mpu_ppn_T_3 = _mpu_ppn_T_2; // @[tlb.scala:149:20, :150:20]
wire [21:0] mpu_ppn_0 = _mpu_ppn_T_3; // @[tlb.scala:121:49, :149:20]
wire [11:0] _mpu_physaddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :151:72]
wire [11:0] _io_resp_0_paddr_T = io_req_0_bits_vaddr_0[11:0]; // @[tlb.scala:17:7, :151:72, :308:57]
wire [33:0] _mpu_physaddr_T_1 = {mpu_ppn_0, _mpu_physaddr_T}; // @[tlb.scala:121:49, :151:{39,72}]
wire [33:0] mpu_physaddr_0 = _mpu_physaddr_T_1; // @[tlb.scala:121:49, :151:39]
wire [33:0] _cacheable_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_26 = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_r_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_w_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_al_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_aa_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T = mpu_physaddr_0; // @[Parameters.scala:137:31]
wire [33:0] _GEN = {mpu_physaddr_0[33:14], mpu_physaddr_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T; // @[Parameters.scala:137:31]
assign _legal_address_T = _GEN; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T; // @[Parameters.scala:137:31]
assign _homogeneous_T = _GEN; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_2 = _legal_address_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [33:0] _GEN_0 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_16; // @[Parameters.scala:137:31]
assign _prot_x_T_16 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_16; // @[Parameters.scala:137:31]
assign _prot_eff_T_16 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_7 = _legal_address_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [33:0] _legal_address_T_10 = {mpu_physaddr_0[33:21], mpu_physaddr_0[20:0] ^ 21'h110000}; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_12 = _legal_address_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [33:0] _GEN_1 = {mpu_physaddr_0[33:26], mpu_physaddr_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_17 = _legal_address_T_16 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [33:0] _GEN_2 = {mpu_physaddr_0[33:32], mpu_physaddr_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [33:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _cacheable_T_5; // @[Parameters.scala:137:31]
assign _cacheable_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_15; // @[Parameters.scala:137:31]
assign _homogeneous_T_15 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _homogeneous_T_33; // @[Parameters.scala:137:31]
assign _homogeneous_T_33 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_5; // @[Parameters.scala:137:31]
assign _prot_x_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_5; // @[Parameters.scala:137:31]
assign _prot_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [34:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _legal_address_T_22 = _legal_address_T_21 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire _legal_address_T_25 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_26 = _legal_address_T_25 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_27 = _legal_address_T_26 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_28 = _legal_address_T_27 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire legal_address_0 = _legal_address_T_28; // @[tlb.scala:121:49, :159:84]
wire _prot_r_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22]
wire _prot_w_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22]
wire _prot_al_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22]
wire _prot_aa_T_5 = legal_address_0; // @[tlb.scala:121:49, :161:22]
wire [34:0] _cacheable_T_1 = {1'h0, _cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _cacheable_T_2 = _cacheable_T_1 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _cacheable_T_3 = _cacheable_T_2; // @[Parameters.scala:137:46]
wire _cacheable_T_4 = _cacheable_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _cacheable_T_6 = {1'h0, _cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _cacheable_T_7 = _cacheable_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _cacheable_T_8 = _cacheable_T_7; // @[Parameters.scala:137:46]
wire _cacheable_T_9 = _cacheable_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _cacheable_T_11 = _cacheable_T_9; // @[Mux.scala:30:73]
wire _cacheable_T_12 = _cacheable_T_11; // @[Mux.scala:30:73]
wire _cacheable_WIRE = _cacheable_T_12; // @[Mux.scala:30:73]
wire _cacheable_T_13 = legal_address_0 & _cacheable_WIRE; // @[Mux.scala:30:73]
wire _cacheable_T_14 = _cacheable_T_13; // @[tlb.scala:161:22, :162:66]
wire cacheable_0 = _cacheable_T_14; // @[tlb.scala:121:49, :162:66]
wire newEntry_c = cacheable_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_2 = _homogeneous_T_1 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_20 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_7 = _homogeneous_T_6 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_12 = _homogeneous_T_11 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_17 = _homogeneous_T_16 & 35'h7F0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_21 = _homogeneous_T_20 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_22 = _homogeneous_T_21 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_23 = _homogeneous_T_22 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire homogeneous_0 = _homogeneous_T_23; // @[TLBPermissions.scala:101:65]
wire [34:0] _homogeneous_T_27 = {1'h0, _homogeneous_T_26}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_28 = _homogeneous_T_27 & 35'h80002000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_29 = _homogeneous_T_28; // @[Parameters.scala:137:46]
wire _homogeneous_T_30 = _homogeneous_T_29 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_31 = _homogeneous_T_30; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_32 = ~_homogeneous_T_31; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] _homogeneous_T_34 = {1'h0, _homogeneous_T_33}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _homogeneous_T_35 = _homogeneous_T_34 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _homogeneous_T_36 = _homogeneous_T_35; // @[Parameters.scala:137:46]
wire _homogeneous_T_37 = _homogeneous_T_36 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_38 = _homogeneous_T_37; // @[TLBPermissions.scala:85:66]
wire [34:0] _prot_r_T_1 = {1'h0, _prot_r_T}; // @[Parameters.scala:137:{31,41}]
wire _prot_r_T_6 = _prot_r_T_5; // @[tlb.scala:161:22, :164:60]
wire prot_r_0 = _prot_r_T_6; // @[tlb.scala:121:49, :164:60]
wire newEntry_pr = prot_r_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _prot_w_T_1 = {1'h0, _prot_w_T}; // @[Parameters.scala:137:{31,41}]
wire _prot_w_T_6 = _prot_w_T_5; // @[tlb.scala:161:22, :165:64]
wire prot_w_0 = _prot_w_T_6; // @[tlb.scala:121:49, :165:64]
wire newEntry_pw = prot_w_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _prot_al_T_1 = {1'h0, _prot_al_T}; // @[Parameters.scala:137:{31,41}]
wire prot_al_0 = _prot_al_T_5; // @[tlb.scala:121:49, :161:22]
wire newEntry_pal = prot_al_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _prot_aa_T_1 = {1'h0, _prot_aa_T}; // @[Parameters.scala:137:{31,41}]
wire prot_aa_0 = _prot_aa_T_5; // @[tlb.scala:121:49, :161:22]
wire newEntry_paa = prot_aa_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _prot_x_T_1 = {1'h0, _prot_x_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_2 = _prot_x_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_3 = _prot_x_T_2; // @[Parameters.scala:137:46]
wire _prot_x_T_4 = _prot_x_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_x_T_6 = {1'h0, _prot_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_7 = _prot_x_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_8 = _prot_x_T_7; // @[Parameters.scala:137:46]
wire _prot_x_T_9 = _prot_x_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_x_T_10 = _prot_x_T_4 | _prot_x_T_9; // @[Parameters.scala:629:89]
wire _prot_x_T_22 = _prot_x_T_10; // @[Mux.scala:30:73]
wire [33:0] _GEN_3 = {mpu_physaddr_0[33:17], mpu_physaddr_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [33:0] _prot_x_T_11; // @[Parameters.scala:137:31]
assign _prot_x_T_11 = _GEN_3; // @[Parameters.scala:137:31]
wire [33:0] _prot_eff_T_11; // @[Parameters.scala:137:31]
assign _prot_eff_T_11 = _GEN_3; // @[Parameters.scala:137:31]
wire [34:0] _prot_x_T_12 = {1'h0, _prot_x_T_11}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_13 = _prot_x_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_14 = _prot_x_T_13; // @[Parameters.scala:137:46]
wire _prot_x_T_15 = _prot_x_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_x_T_17 = {1'h0, _prot_x_T_16}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_x_T_18 = _prot_x_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_x_T_19 = _prot_x_T_18; // @[Parameters.scala:137:46]
wire _prot_x_T_20 = _prot_x_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_x_T_21 = _prot_x_T_15 | _prot_x_T_20; // @[Parameters.scala:629:89]
wire _prot_x_T_24 = _prot_x_T_22; // @[Mux.scala:30:73]
wire _prot_x_WIRE = _prot_x_T_24; // @[Mux.scala:30:73]
wire _prot_x_T_25 = legal_address_0 & _prot_x_WIRE; // @[Mux.scala:30:73]
wire _prot_x_T_26 = _prot_x_T_25; // @[tlb.scala:161:22, :168:59]
wire prot_x_0 = _prot_x_T_26; // @[tlb.scala:121:49, :168:59]
wire newEntry_px = prot_x_0; // @[tlb.scala:121:49, :181:24]
wire [34:0] _prot_eff_T_1 = {1'h0, _prot_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_2 = _prot_eff_T_1 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_3 = _prot_eff_T_2; // @[Parameters.scala:137:46]
wire _prot_eff_T_4 = _prot_eff_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_eff_T_6 = {1'h0, _prot_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_7 = _prot_eff_T_6 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_8 = _prot_eff_T_7; // @[Parameters.scala:137:46]
wire _prot_eff_T_9 = _prot_eff_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_eff_T_10 = _prot_eff_T_4 | _prot_eff_T_9; // @[Parameters.scala:629:89]
wire [34:0] _prot_eff_T_12 = {1'h0, _prot_eff_T_11}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_13 = _prot_eff_T_12 & 35'h80110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_14 = _prot_eff_T_13; // @[Parameters.scala:137:46]
wire _prot_eff_T_15 = _prot_eff_T_14 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _prot_eff_T_17 = {1'h0, _prot_eff_T_16}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _prot_eff_T_18 = _prot_eff_T_17 & 35'h80100000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _prot_eff_T_19 = _prot_eff_T_18; // @[Parameters.scala:137:46]
wire _prot_eff_T_20 = _prot_eff_T_19 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _prot_eff_T_21 = _prot_eff_T_15 | _prot_eff_T_20; // @[Parameters.scala:629:89]
wire _prot_eff_T_23 = _prot_eff_T_21; // @[Mux.scala:30:73]
wire _prot_eff_T_24 = _prot_eff_T_23; // @[Mux.scala:30:73]
wire _prot_eff_WIRE = _prot_eff_T_24; // @[Mux.scala:30:73]
wire _prot_eff_T_25 = legal_address_0 & _prot_eff_WIRE; // @[Mux.scala:30:73]
wire prot_eff_0 = _prot_eff_T_25; // @[tlb.scala:121:49, :161:22]
wire newEntry_eff = prot_eff_0; // @[tlb.scala:121:49, :181:24]
wire _sector_hits_T_1 = _sector_hits_T; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_4 = _sector_hits_T_3[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_6 = _sector_hits_T_2 & _sector_hits_T_5; // @[package.scala:81:59]
wire _sector_hits_WIRE_0 = _sector_hits_T_6; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_8 = _sector_hits_T_7; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_11 = _sector_hits_T_10[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_12 = _sector_hits_T_11 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_13 = _sector_hits_T_9 & _sector_hits_T_12; // @[package.scala:81:59]
wire _sector_hits_WIRE_1 = _sector_hits_T_13; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_15 = _sector_hits_T_14; // @[package.scala:81:59]
wire _sector_hits_T_16 = _sector_hits_T_15; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_18 = _sector_hits_T_17[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_19 = _sector_hits_T_18 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_20 = _sector_hits_T_16 & _sector_hits_T_19; // @[package.scala:81:59]
wire _sector_hits_WIRE_2 = _sector_hits_T_20; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_22 = _sector_hits_T_21; // @[package.scala:81:59]
wire _sector_hits_T_23 = _sector_hits_T_22; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_25 = _sector_hits_T_24[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_26 = _sector_hits_T_25 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_27 = _sector_hits_T_23 & _sector_hits_T_26; // @[package.scala:81:59]
wire _sector_hits_WIRE_3 = _sector_hits_T_27; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_29 = _sector_hits_T_28; // @[package.scala:81:59]
wire _sector_hits_T_30 = _sector_hits_T_29; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_32 = _sector_hits_T_31[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_33 = _sector_hits_T_32 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_34 = _sector_hits_T_30 & _sector_hits_T_33; // @[package.scala:81:59]
wire _sector_hits_WIRE_4 = _sector_hits_T_34; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_36 = _sector_hits_T_35; // @[package.scala:81:59]
wire _sector_hits_T_37 = _sector_hits_T_36; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_39 = _sector_hits_T_38[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_40 = _sector_hits_T_39 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_41 = _sector_hits_T_37 & _sector_hits_T_40; // @[package.scala:81:59]
wire _sector_hits_WIRE_5 = _sector_hits_T_41; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_43 = _sector_hits_T_42; // @[package.scala:81:59]
wire _sector_hits_T_44 = _sector_hits_T_43; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_46 = _sector_hits_T_45[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_47 = _sector_hits_T_46 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_48 = _sector_hits_T_44 & _sector_hits_T_47; // @[package.scala:81:59]
wire _sector_hits_WIRE_6 = _sector_hits_T_48; // @[tlb.scala:61:42, :171:42]
wire _sector_hits_T_50 = _sector_hits_T_49; // @[package.scala:81:59]
wire _sector_hits_T_51 = _sector_hits_T_50; // @[package.scala:81:59]
wire [18:0] _sector_hits_T_53 = _sector_hits_T_52[20:2]; // @[tlb.scala:62:{43,50}]
wire _sector_hits_T_54 = _sector_hits_T_53 == 19'h0; // @[tlb.scala:62:{50,73}]
wire _sector_hits_T_55 = _sector_hits_T_51 & _sector_hits_T_54; // @[package.scala:81:59]
wire _sector_hits_WIRE_7 = _sector_hits_T_55; // @[tlb.scala:61:42, :171:42]
wire sector_hits_0_0 = _sector_hits_WIRE_0; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_1 = _sector_hits_WIRE_1; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_2 = _sector_hits_WIRE_2; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_3 = _sector_hits_WIRE_3; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_4 = _sector_hits_WIRE_4; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_5 = _sector_hits_WIRE_5; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_6 = _sector_hits_WIRE_6; // @[tlb.scala:121:49, :171:42]
wire sector_hits_0_7 = _sector_hits_WIRE_7; // @[tlb.scala:121:49, :171:42]
wire [20:0] _superpage_hits_T_1 = _superpage_hits_T; // @[tlb.scala:62:{43,50}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire _superpage_hits_WIRE_0 = _superpage_hits_T_3; // @[tlb.scala:74:20, :172:45]
wire [20:0] _superpage_hits_T_5 = _superpage_hits_T_4; // @[tlb.scala:62:{43,50}]
wire _superpage_hits_T_6 = _superpage_hits_T_5 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire _superpage_hits_WIRE_1 = _superpage_hits_T_7; // @[tlb.scala:74:20, :172:45]
wire [20:0] _superpage_hits_T_9 = _superpage_hits_T_8; // @[tlb.scala:62:{43,50}]
wire _superpage_hits_T_10 = _superpage_hits_T_9 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire _superpage_hits_WIRE_2 = _superpage_hits_T_11; // @[tlb.scala:74:20, :172:45]
wire [20:0] _superpage_hits_T_13 = _superpage_hits_T_12; // @[tlb.scala:62:{43,50}]
wire _superpage_hits_T_14 = _superpage_hits_T_13 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire _superpage_hits_WIRE_3 = _superpage_hits_T_15; // @[tlb.scala:74:20, :172:45]
wire superpage_hits_0_0 = _superpage_hits_WIRE_0; // @[tlb.scala:121:49, :172:45]
wire superpage_hits_0_1 = _superpage_hits_WIRE_1; // @[tlb.scala:121:49, :172:45]
wire superpage_hits_0_2 = _superpage_hits_WIRE_2; // @[tlb.scala:121:49, :172:45]
wire superpage_hits_0_3 = _superpage_hits_WIRE_3; // @[tlb.scala:121:49, :172:45]
wire [1:0] hitsVec_idx = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _ppn_data_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_16 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_32 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_48 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_64 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_80 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_96 = vpn_0[1:0]; // @[package.scala:163:13]
wire [1:0] _normal_entries_T_112 = vpn_0[1:0]; // @[package.scala:163:13]
wire [18:0] _hitsVec_T_1 = _hitsVec_T[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_6 = _hitsVec_T_5[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_7 = _hitsVec_T_6 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_11 = _hitsVec_T_10[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_12 = _hitsVec_T_11 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_16 = _hitsVec_T_15[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_17 = _hitsVec_T_16 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_21 = _hitsVec_T_20[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_22 = _hitsVec_T_21 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_26 = _hitsVec_T_25[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_27 = _hitsVec_T_26 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_31 = _hitsVec_T_30[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [18:0] _hitsVec_T_36 = _hitsVec_T_35[20:2]; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_37 = _hitsVec_T_36 == 19'h0; // @[tlb.scala:62:{50,73}]
wire [20:0] _hitsVec_T_41 = _hitsVec_T_40; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_42 = _hitsVec_T_41 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire [20:0] _hitsVec_T_46 = _hitsVec_T_45; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_47 = _hitsVec_T_46 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire [20:0] _hitsVec_T_51 = _hitsVec_T_50; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_52 = _hitsVec_T_51 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire [20:0] _hitsVec_T_56 = _hitsVec_T_55; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_57 = _hitsVec_T_56 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire [20:0] _hitsVec_T_61 = _hitsVec_T_60; // @[tlb.scala:62:{43,50}]
wire _hitsVec_T_62 = _hitsVec_T_61 == 21'h0; // @[tlb.scala:62:{50,73}, :124:29]
wire _hitsVec_T_63 = _hitsVec_T_62; // @[tlb.scala:62:73, :74:20]
wire [19:0] _ppn_data_T_15; // @[tlb.scala:60:79]
wire _ppn_data_T_14; // @[tlb.scala:60:79]
wire _ppn_data_T_13; // @[tlb.scala:60:79]
wire _ppn_data_T_12; // @[tlb.scala:60:79]
wire _ppn_data_T_11; // @[tlb.scala:60:79]
wire _ppn_data_T_10; // @[tlb.scala:60:79]
wire _ppn_data_T_9; // @[tlb.scala:60:79]
wire _ppn_data_T_8; // @[tlb.scala:60:79]
wire _ppn_data_T_7; // @[tlb.scala:60:79]
wire _ppn_data_T_6; // @[tlb.scala:60:79]
wire _ppn_data_T_5; // @[tlb.scala:60:79]
wire _ppn_data_T_4; // @[tlb.scala:60:79]
wire _ppn_data_T_3; // @[tlb.scala:60:79]
wire _ppn_data_T_2; // @[tlb.scala:60:79]
wire _ppn_data_T_1; // @[tlb.scala:60:79]
assign _ppn_data_T_1 = _ppn_data_WIRE_1[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_fragmented_superpage = _ppn_data_T_1; // @[tlb.scala:60:79]
assign _ppn_data_T_2 = _ppn_data_WIRE_1[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_c = _ppn_data_T_2; // @[tlb.scala:60:79]
assign _ppn_data_T_3 = _ppn_data_WIRE_1[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_eff = _ppn_data_T_3; // @[tlb.scala:60:79]
assign _ppn_data_T_4 = _ppn_data_WIRE_1[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_paa = _ppn_data_T_4; // @[tlb.scala:60:79]
assign _ppn_data_T_5 = _ppn_data_WIRE_1[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_pal = _ppn_data_T_5; // @[tlb.scala:60:79]
assign _ppn_data_T_6 = _ppn_data_WIRE_1[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_pr = _ppn_data_T_6; // @[tlb.scala:60:79]
assign _ppn_data_T_7 = _ppn_data_WIRE_1[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_px = _ppn_data_T_7; // @[tlb.scala:60:79]
assign _ppn_data_T_8 = _ppn_data_WIRE_1[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_pw = _ppn_data_T_8; // @[tlb.scala:60:79]
assign _ppn_data_T_9 = _ppn_data_WIRE_1[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_sr = _ppn_data_T_9; // @[tlb.scala:60:79]
assign _ppn_data_T_10 = _ppn_data_WIRE_1[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_sx = _ppn_data_T_10; // @[tlb.scala:60:79]
assign _ppn_data_T_11 = _ppn_data_WIRE_1[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_sw = _ppn_data_T_11; // @[tlb.scala:60:79]
assign _ppn_data_T_12 = _ppn_data_WIRE_1[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_ae = _ppn_data_T_12; // @[tlb.scala:60:79]
assign _ppn_data_T_13 = _ppn_data_WIRE_1[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_g = _ppn_data_T_13; // @[tlb.scala:60:79]
assign _ppn_data_T_14 = _ppn_data_WIRE_1[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_u = _ppn_data_T_14; // @[tlb.scala:60:79]
assign _ppn_data_T_15 = _ppn_data_WIRE_1[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_ppn = _ppn_data_T_15; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_31; // @[tlb.scala:60:79]
wire _ppn_data_T_30; // @[tlb.scala:60:79]
wire _ppn_data_T_29; // @[tlb.scala:60:79]
wire _ppn_data_T_28; // @[tlb.scala:60:79]
wire _ppn_data_T_27; // @[tlb.scala:60:79]
wire _ppn_data_T_26; // @[tlb.scala:60:79]
wire _ppn_data_T_25; // @[tlb.scala:60:79]
wire _ppn_data_T_24; // @[tlb.scala:60:79]
wire _ppn_data_T_23; // @[tlb.scala:60:79]
wire _ppn_data_T_22; // @[tlb.scala:60:79]
wire _ppn_data_T_21; // @[tlb.scala:60:79]
wire _ppn_data_T_20; // @[tlb.scala:60:79]
wire _ppn_data_T_19; // @[tlb.scala:60:79]
wire _ppn_data_T_18; // @[tlb.scala:60:79]
wire _ppn_data_T_17; // @[tlb.scala:60:79]
assign _ppn_data_T_17 = _ppn_data_WIRE_3[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_fragmented_superpage = _ppn_data_T_17; // @[tlb.scala:60:79]
assign _ppn_data_T_18 = _ppn_data_WIRE_3[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_c = _ppn_data_T_18; // @[tlb.scala:60:79]
assign _ppn_data_T_19 = _ppn_data_WIRE_3[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_eff = _ppn_data_T_19; // @[tlb.scala:60:79]
assign _ppn_data_T_20 = _ppn_data_WIRE_3[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_paa = _ppn_data_T_20; // @[tlb.scala:60:79]
assign _ppn_data_T_21 = _ppn_data_WIRE_3[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_pal = _ppn_data_T_21; // @[tlb.scala:60:79]
assign _ppn_data_T_22 = _ppn_data_WIRE_3[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_pr = _ppn_data_T_22; // @[tlb.scala:60:79]
assign _ppn_data_T_23 = _ppn_data_WIRE_3[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_px = _ppn_data_T_23; // @[tlb.scala:60:79]
assign _ppn_data_T_24 = _ppn_data_WIRE_3[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_pw = _ppn_data_T_24; // @[tlb.scala:60:79]
assign _ppn_data_T_25 = _ppn_data_WIRE_3[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_sr = _ppn_data_T_25; // @[tlb.scala:60:79]
assign _ppn_data_T_26 = _ppn_data_WIRE_3[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_sx = _ppn_data_T_26; // @[tlb.scala:60:79]
assign _ppn_data_T_27 = _ppn_data_WIRE_3[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_sw = _ppn_data_T_27; // @[tlb.scala:60:79]
assign _ppn_data_T_28 = _ppn_data_WIRE_3[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_ae = _ppn_data_T_28; // @[tlb.scala:60:79]
assign _ppn_data_T_29 = _ppn_data_WIRE_3[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_g = _ppn_data_T_29; // @[tlb.scala:60:79]
assign _ppn_data_T_30 = _ppn_data_WIRE_3[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_2_u = _ppn_data_T_30; // @[tlb.scala:60:79]
assign _ppn_data_T_31 = _ppn_data_WIRE_3[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_2_ppn = _ppn_data_T_31; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_47; // @[tlb.scala:60:79]
wire _ppn_data_T_46; // @[tlb.scala:60:79]
wire _ppn_data_T_45; // @[tlb.scala:60:79]
wire _ppn_data_T_44; // @[tlb.scala:60:79]
wire _ppn_data_T_43; // @[tlb.scala:60:79]
wire _ppn_data_T_42; // @[tlb.scala:60:79]
wire _ppn_data_T_41; // @[tlb.scala:60:79]
wire _ppn_data_T_40; // @[tlb.scala:60:79]
wire _ppn_data_T_39; // @[tlb.scala:60:79]
wire _ppn_data_T_38; // @[tlb.scala:60:79]
wire _ppn_data_T_37; // @[tlb.scala:60:79]
wire _ppn_data_T_36; // @[tlb.scala:60:79]
wire _ppn_data_T_35; // @[tlb.scala:60:79]
wire _ppn_data_T_34; // @[tlb.scala:60:79]
wire _ppn_data_T_33; // @[tlb.scala:60:79]
assign _ppn_data_T_33 = _ppn_data_WIRE_5[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_fragmented_superpage = _ppn_data_T_33; // @[tlb.scala:60:79]
assign _ppn_data_T_34 = _ppn_data_WIRE_5[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_c = _ppn_data_T_34; // @[tlb.scala:60:79]
assign _ppn_data_T_35 = _ppn_data_WIRE_5[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_eff = _ppn_data_T_35; // @[tlb.scala:60:79]
assign _ppn_data_T_36 = _ppn_data_WIRE_5[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_paa = _ppn_data_T_36; // @[tlb.scala:60:79]
assign _ppn_data_T_37 = _ppn_data_WIRE_5[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_pal = _ppn_data_T_37; // @[tlb.scala:60:79]
assign _ppn_data_T_38 = _ppn_data_WIRE_5[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_pr = _ppn_data_T_38; // @[tlb.scala:60:79]
assign _ppn_data_T_39 = _ppn_data_WIRE_5[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_px = _ppn_data_T_39; // @[tlb.scala:60:79]
assign _ppn_data_T_40 = _ppn_data_WIRE_5[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_pw = _ppn_data_T_40; // @[tlb.scala:60:79]
assign _ppn_data_T_41 = _ppn_data_WIRE_5[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_sr = _ppn_data_T_41; // @[tlb.scala:60:79]
assign _ppn_data_T_42 = _ppn_data_WIRE_5[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_sx = _ppn_data_T_42; // @[tlb.scala:60:79]
assign _ppn_data_T_43 = _ppn_data_WIRE_5[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_sw = _ppn_data_T_43; // @[tlb.scala:60:79]
assign _ppn_data_T_44 = _ppn_data_WIRE_5[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_ae = _ppn_data_T_44; // @[tlb.scala:60:79]
assign _ppn_data_T_45 = _ppn_data_WIRE_5[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_g = _ppn_data_T_45; // @[tlb.scala:60:79]
assign _ppn_data_T_46 = _ppn_data_WIRE_5[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_4_u = _ppn_data_T_46; // @[tlb.scala:60:79]
assign _ppn_data_T_47 = _ppn_data_WIRE_5[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_4_ppn = _ppn_data_T_47; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_63; // @[tlb.scala:60:79]
wire _ppn_data_T_62; // @[tlb.scala:60:79]
wire _ppn_data_T_61; // @[tlb.scala:60:79]
wire _ppn_data_T_60; // @[tlb.scala:60:79]
wire _ppn_data_T_59; // @[tlb.scala:60:79]
wire _ppn_data_T_58; // @[tlb.scala:60:79]
wire _ppn_data_T_57; // @[tlb.scala:60:79]
wire _ppn_data_T_56; // @[tlb.scala:60:79]
wire _ppn_data_T_55; // @[tlb.scala:60:79]
wire _ppn_data_T_54; // @[tlb.scala:60:79]
wire _ppn_data_T_53; // @[tlb.scala:60:79]
wire _ppn_data_T_52; // @[tlb.scala:60:79]
wire _ppn_data_T_51; // @[tlb.scala:60:79]
wire _ppn_data_T_50; // @[tlb.scala:60:79]
wire _ppn_data_T_49; // @[tlb.scala:60:79]
assign _ppn_data_T_49 = _ppn_data_WIRE_7[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_fragmented_superpage = _ppn_data_T_49; // @[tlb.scala:60:79]
assign _ppn_data_T_50 = _ppn_data_WIRE_7[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_c = _ppn_data_T_50; // @[tlb.scala:60:79]
assign _ppn_data_T_51 = _ppn_data_WIRE_7[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_eff = _ppn_data_T_51; // @[tlb.scala:60:79]
assign _ppn_data_T_52 = _ppn_data_WIRE_7[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_paa = _ppn_data_T_52; // @[tlb.scala:60:79]
assign _ppn_data_T_53 = _ppn_data_WIRE_7[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_pal = _ppn_data_T_53; // @[tlb.scala:60:79]
assign _ppn_data_T_54 = _ppn_data_WIRE_7[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_pr = _ppn_data_T_54; // @[tlb.scala:60:79]
assign _ppn_data_T_55 = _ppn_data_WIRE_7[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_px = _ppn_data_T_55; // @[tlb.scala:60:79]
assign _ppn_data_T_56 = _ppn_data_WIRE_7[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_pw = _ppn_data_T_56; // @[tlb.scala:60:79]
assign _ppn_data_T_57 = _ppn_data_WIRE_7[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_sr = _ppn_data_T_57; // @[tlb.scala:60:79]
assign _ppn_data_T_58 = _ppn_data_WIRE_7[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_sx = _ppn_data_T_58; // @[tlb.scala:60:79]
assign _ppn_data_T_59 = _ppn_data_WIRE_7[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_sw = _ppn_data_T_59; // @[tlb.scala:60:79]
assign _ppn_data_T_60 = _ppn_data_WIRE_7[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_ae = _ppn_data_T_60; // @[tlb.scala:60:79]
assign _ppn_data_T_61 = _ppn_data_WIRE_7[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_g = _ppn_data_T_61; // @[tlb.scala:60:79]
assign _ppn_data_T_62 = _ppn_data_WIRE_7[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_6_u = _ppn_data_T_62; // @[tlb.scala:60:79]
assign _ppn_data_T_63 = _ppn_data_WIRE_7[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_6_ppn = _ppn_data_T_63; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_79; // @[tlb.scala:60:79]
wire _ppn_data_T_78; // @[tlb.scala:60:79]
wire _ppn_data_T_77; // @[tlb.scala:60:79]
wire _ppn_data_T_76; // @[tlb.scala:60:79]
wire _ppn_data_T_75; // @[tlb.scala:60:79]
wire _ppn_data_T_74; // @[tlb.scala:60:79]
wire _ppn_data_T_73; // @[tlb.scala:60:79]
wire _ppn_data_T_72; // @[tlb.scala:60:79]
wire _ppn_data_T_71; // @[tlb.scala:60:79]
wire _ppn_data_T_70; // @[tlb.scala:60:79]
wire _ppn_data_T_69; // @[tlb.scala:60:79]
wire _ppn_data_T_68; // @[tlb.scala:60:79]
wire _ppn_data_T_67; // @[tlb.scala:60:79]
wire _ppn_data_T_66; // @[tlb.scala:60:79]
wire _ppn_data_T_65; // @[tlb.scala:60:79]
assign _ppn_data_T_65 = _ppn_data_WIRE_9[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_fragmented_superpage = _ppn_data_T_65; // @[tlb.scala:60:79]
assign _ppn_data_T_66 = _ppn_data_WIRE_9[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_c = _ppn_data_T_66; // @[tlb.scala:60:79]
assign _ppn_data_T_67 = _ppn_data_WIRE_9[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_eff = _ppn_data_T_67; // @[tlb.scala:60:79]
assign _ppn_data_T_68 = _ppn_data_WIRE_9[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_paa = _ppn_data_T_68; // @[tlb.scala:60:79]
assign _ppn_data_T_69 = _ppn_data_WIRE_9[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_pal = _ppn_data_T_69; // @[tlb.scala:60:79]
assign _ppn_data_T_70 = _ppn_data_WIRE_9[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_pr = _ppn_data_T_70; // @[tlb.scala:60:79]
assign _ppn_data_T_71 = _ppn_data_WIRE_9[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_px = _ppn_data_T_71; // @[tlb.scala:60:79]
assign _ppn_data_T_72 = _ppn_data_WIRE_9[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_pw = _ppn_data_T_72; // @[tlb.scala:60:79]
assign _ppn_data_T_73 = _ppn_data_WIRE_9[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_sr = _ppn_data_T_73; // @[tlb.scala:60:79]
assign _ppn_data_T_74 = _ppn_data_WIRE_9[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_sx = _ppn_data_T_74; // @[tlb.scala:60:79]
assign _ppn_data_T_75 = _ppn_data_WIRE_9[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_sw = _ppn_data_T_75; // @[tlb.scala:60:79]
assign _ppn_data_T_76 = _ppn_data_WIRE_9[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_ae = _ppn_data_T_76; // @[tlb.scala:60:79]
assign _ppn_data_T_77 = _ppn_data_WIRE_9[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_g = _ppn_data_T_77; // @[tlb.scala:60:79]
assign _ppn_data_T_78 = _ppn_data_WIRE_9[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_8_u = _ppn_data_T_78; // @[tlb.scala:60:79]
assign _ppn_data_T_79 = _ppn_data_WIRE_9[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_8_ppn = _ppn_data_T_79; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_95; // @[tlb.scala:60:79]
wire _ppn_data_T_94; // @[tlb.scala:60:79]
wire _ppn_data_T_93; // @[tlb.scala:60:79]
wire _ppn_data_T_92; // @[tlb.scala:60:79]
wire _ppn_data_T_91; // @[tlb.scala:60:79]
wire _ppn_data_T_90; // @[tlb.scala:60:79]
wire _ppn_data_T_89; // @[tlb.scala:60:79]
wire _ppn_data_T_88; // @[tlb.scala:60:79]
wire _ppn_data_T_87; // @[tlb.scala:60:79]
wire _ppn_data_T_86; // @[tlb.scala:60:79]
wire _ppn_data_T_85; // @[tlb.scala:60:79]
wire _ppn_data_T_84; // @[tlb.scala:60:79]
wire _ppn_data_T_83; // @[tlb.scala:60:79]
wire _ppn_data_T_82; // @[tlb.scala:60:79]
wire _ppn_data_T_81; // @[tlb.scala:60:79]
assign _ppn_data_T_81 = _ppn_data_WIRE_11[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_fragmented_superpage = _ppn_data_T_81; // @[tlb.scala:60:79]
assign _ppn_data_T_82 = _ppn_data_WIRE_11[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_c = _ppn_data_T_82; // @[tlb.scala:60:79]
assign _ppn_data_T_83 = _ppn_data_WIRE_11[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_eff = _ppn_data_T_83; // @[tlb.scala:60:79]
assign _ppn_data_T_84 = _ppn_data_WIRE_11[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_paa = _ppn_data_T_84; // @[tlb.scala:60:79]
assign _ppn_data_T_85 = _ppn_data_WIRE_11[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_pal = _ppn_data_T_85; // @[tlb.scala:60:79]
assign _ppn_data_T_86 = _ppn_data_WIRE_11[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_pr = _ppn_data_T_86; // @[tlb.scala:60:79]
assign _ppn_data_T_87 = _ppn_data_WIRE_11[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_px = _ppn_data_T_87; // @[tlb.scala:60:79]
assign _ppn_data_T_88 = _ppn_data_WIRE_11[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_pw = _ppn_data_T_88; // @[tlb.scala:60:79]
assign _ppn_data_T_89 = _ppn_data_WIRE_11[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_sr = _ppn_data_T_89; // @[tlb.scala:60:79]
assign _ppn_data_T_90 = _ppn_data_WIRE_11[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_sx = _ppn_data_T_90; // @[tlb.scala:60:79]
assign _ppn_data_T_91 = _ppn_data_WIRE_11[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_sw = _ppn_data_T_91; // @[tlb.scala:60:79]
assign _ppn_data_T_92 = _ppn_data_WIRE_11[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_ae = _ppn_data_T_92; // @[tlb.scala:60:79]
assign _ppn_data_T_93 = _ppn_data_WIRE_11[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_g = _ppn_data_T_93; // @[tlb.scala:60:79]
assign _ppn_data_T_94 = _ppn_data_WIRE_11[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_10_u = _ppn_data_T_94; // @[tlb.scala:60:79]
assign _ppn_data_T_95 = _ppn_data_WIRE_11[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_10_ppn = _ppn_data_T_95; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_111; // @[tlb.scala:60:79]
wire _ppn_data_T_110; // @[tlb.scala:60:79]
wire _ppn_data_T_109; // @[tlb.scala:60:79]
wire _ppn_data_T_108; // @[tlb.scala:60:79]
wire _ppn_data_T_107; // @[tlb.scala:60:79]
wire _ppn_data_T_106; // @[tlb.scala:60:79]
wire _ppn_data_T_105; // @[tlb.scala:60:79]
wire _ppn_data_T_104; // @[tlb.scala:60:79]
wire _ppn_data_T_103; // @[tlb.scala:60:79]
wire _ppn_data_T_102; // @[tlb.scala:60:79]
wire _ppn_data_T_101; // @[tlb.scala:60:79]
wire _ppn_data_T_100; // @[tlb.scala:60:79]
wire _ppn_data_T_99; // @[tlb.scala:60:79]
wire _ppn_data_T_98; // @[tlb.scala:60:79]
wire _ppn_data_T_97; // @[tlb.scala:60:79]
assign _ppn_data_T_97 = _ppn_data_WIRE_13[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_fragmented_superpage = _ppn_data_T_97; // @[tlb.scala:60:79]
assign _ppn_data_T_98 = _ppn_data_WIRE_13[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_c = _ppn_data_T_98; // @[tlb.scala:60:79]
assign _ppn_data_T_99 = _ppn_data_WIRE_13[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_eff = _ppn_data_T_99; // @[tlb.scala:60:79]
assign _ppn_data_T_100 = _ppn_data_WIRE_13[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_paa = _ppn_data_T_100; // @[tlb.scala:60:79]
assign _ppn_data_T_101 = _ppn_data_WIRE_13[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_pal = _ppn_data_T_101; // @[tlb.scala:60:79]
assign _ppn_data_T_102 = _ppn_data_WIRE_13[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_pr = _ppn_data_T_102; // @[tlb.scala:60:79]
assign _ppn_data_T_103 = _ppn_data_WIRE_13[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_px = _ppn_data_T_103; // @[tlb.scala:60:79]
assign _ppn_data_T_104 = _ppn_data_WIRE_13[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_pw = _ppn_data_T_104; // @[tlb.scala:60:79]
assign _ppn_data_T_105 = _ppn_data_WIRE_13[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_sr = _ppn_data_T_105; // @[tlb.scala:60:79]
assign _ppn_data_T_106 = _ppn_data_WIRE_13[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_sx = _ppn_data_T_106; // @[tlb.scala:60:79]
assign _ppn_data_T_107 = _ppn_data_WIRE_13[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_sw = _ppn_data_T_107; // @[tlb.scala:60:79]
assign _ppn_data_T_108 = _ppn_data_WIRE_13[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_ae = _ppn_data_T_108; // @[tlb.scala:60:79]
assign _ppn_data_T_109 = _ppn_data_WIRE_13[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_g = _ppn_data_T_109; // @[tlb.scala:60:79]
assign _ppn_data_T_110 = _ppn_data_WIRE_13[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_12_u = _ppn_data_T_110; // @[tlb.scala:60:79]
assign _ppn_data_T_111 = _ppn_data_WIRE_13[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_12_ppn = _ppn_data_T_111; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_127; // @[tlb.scala:60:79]
wire _ppn_data_T_126; // @[tlb.scala:60:79]
wire _ppn_data_T_125; // @[tlb.scala:60:79]
wire _ppn_data_T_124; // @[tlb.scala:60:79]
wire _ppn_data_T_123; // @[tlb.scala:60:79]
wire _ppn_data_T_122; // @[tlb.scala:60:79]
wire _ppn_data_T_121; // @[tlb.scala:60:79]
wire _ppn_data_T_120; // @[tlb.scala:60:79]
wire _ppn_data_T_119; // @[tlb.scala:60:79]
wire _ppn_data_T_118; // @[tlb.scala:60:79]
wire _ppn_data_T_117; // @[tlb.scala:60:79]
wire _ppn_data_T_116; // @[tlb.scala:60:79]
wire _ppn_data_T_115; // @[tlb.scala:60:79]
wire _ppn_data_T_114; // @[tlb.scala:60:79]
wire _ppn_data_T_113; // @[tlb.scala:60:79]
assign _ppn_data_T_113 = _ppn_data_WIRE_15[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_fragmented_superpage = _ppn_data_T_113; // @[tlb.scala:60:79]
assign _ppn_data_T_114 = _ppn_data_WIRE_15[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_c = _ppn_data_T_114; // @[tlb.scala:60:79]
assign _ppn_data_T_115 = _ppn_data_WIRE_15[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_eff = _ppn_data_T_115; // @[tlb.scala:60:79]
assign _ppn_data_T_116 = _ppn_data_WIRE_15[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_paa = _ppn_data_T_116; // @[tlb.scala:60:79]
assign _ppn_data_T_117 = _ppn_data_WIRE_15[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_pal = _ppn_data_T_117; // @[tlb.scala:60:79]
assign _ppn_data_T_118 = _ppn_data_WIRE_15[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_pr = _ppn_data_T_118; // @[tlb.scala:60:79]
assign _ppn_data_T_119 = _ppn_data_WIRE_15[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_px = _ppn_data_T_119; // @[tlb.scala:60:79]
assign _ppn_data_T_120 = _ppn_data_WIRE_15[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_pw = _ppn_data_T_120; // @[tlb.scala:60:79]
assign _ppn_data_T_121 = _ppn_data_WIRE_15[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_sr = _ppn_data_T_121; // @[tlb.scala:60:79]
assign _ppn_data_T_122 = _ppn_data_WIRE_15[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_sx = _ppn_data_T_122; // @[tlb.scala:60:79]
assign _ppn_data_T_123 = _ppn_data_WIRE_15[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_sw = _ppn_data_T_123; // @[tlb.scala:60:79]
assign _ppn_data_T_124 = _ppn_data_WIRE_15[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_ae = _ppn_data_T_124; // @[tlb.scala:60:79]
assign _ppn_data_T_125 = _ppn_data_WIRE_15[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_g = _ppn_data_T_125; // @[tlb.scala:60:79]
assign _ppn_data_T_126 = _ppn_data_WIRE_15[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_14_u = _ppn_data_T_126; // @[tlb.scala:60:79]
assign _ppn_data_T_127 = _ppn_data_WIRE_15[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_14_ppn = _ppn_data_T_127; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_142; // @[tlb.scala:60:79]
wire _ppn_data_T_141; // @[tlb.scala:60:79]
wire _ppn_data_T_140; // @[tlb.scala:60:79]
wire _ppn_data_T_139; // @[tlb.scala:60:79]
wire _ppn_data_T_138; // @[tlb.scala:60:79]
wire _ppn_data_T_137; // @[tlb.scala:60:79]
wire _ppn_data_T_136; // @[tlb.scala:60:79]
wire _ppn_data_T_135; // @[tlb.scala:60:79]
wire _ppn_data_T_134; // @[tlb.scala:60:79]
wire _ppn_data_T_133; // @[tlb.scala:60:79]
wire _ppn_data_T_132; // @[tlb.scala:60:79]
wire _ppn_data_T_131; // @[tlb.scala:60:79]
wire _ppn_data_T_130; // @[tlb.scala:60:79]
wire _ppn_data_T_129; // @[tlb.scala:60:79]
wire _ppn_data_T_128; // @[tlb.scala:60:79]
assign _ppn_data_T_128 = _ppn_data_WIRE_17[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_fragmented_superpage = _ppn_data_T_128; // @[tlb.scala:60:79]
assign _ppn_data_T_129 = _ppn_data_WIRE_17[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_c = _ppn_data_T_129; // @[tlb.scala:60:79]
assign _ppn_data_T_130 = _ppn_data_WIRE_17[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_eff = _ppn_data_T_130; // @[tlb.scala:60:79]
assign _ppn_data_T_131 = _ppn_data_WIRE_17[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_paa = _ppn_data_T_131; // @[tlb.scala:60:79]
assign _ppn_data_T_132 = _ppn_data_WIRE_17[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_pal = _ppn_data_T_132; // @[tlb.scala:60:79]
assign _ppn_data_T_133 = _ppn_data_WIRE_17[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_pr = _ppn_data_T_133; // @[tlb.scala:60:79]
assign _ppn_data_T_134 = _ppn_data_WIRE_17[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_px = _ppn_data_T_134; // @[tlb.scala:60:79]
assign _ppn_data_T_135 = _ppn_data_WIRE_17[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_pw = _ppn_data_T_135; // @[tlb.scala:60:79]
assign _ppn_data_T_136 = _ppn_data_WIRE_17[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_sr = _ppn_data_T_136; // @[tlb.scala:60:79]
assign _ppn_data_T_137 = _ppn_data_WIRE_17[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_sx = _ppn_data_T_137; // @[tlb.scala:60:79]
assign _ppn_data_T_138 = _ppn_data_WIRE_17[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_sw = _ppn_data_T_138; // @[tlb.scala:60:79]
assign _ppn_data_T_139 = _ppn_data_WIRE_17[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_ae = _ppn_data_T_139; // @[tlb.scala:60:79]
assign _ppn_data_T_140 = _ppn_data_WIRE_17[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_g = _ppn_data_T_140; // @[tlb.scala:60:79]
assign _ppn_data_T_141 = _ppn_data_WIRE_17[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_16_u = _ppn_data_T_141; // @[tlb.scala:60:79]
assign _ppn_data_T_142 = _ppn_data_WIRE_17[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_16_ppn = _ppn_data_T_142; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_157; // @[tlb.scala:60:79]
wire _ppn_data_T_156; // @[tlb.scala:60:79]
wire _ppn_data_T_155; // @[tlb.scala:60:79]
wire _ppn_data_T_154; // @[tlb.scala:60:79]
wire _ppn_data_T_153; // @[tlb.scala:60:79]
wire _ppn_data_T_152; // @[tlb.scala:60:79]
wire _ppn_data_T_151; // @[tlb.scala:60:79]
wire _ppn_data_T_150; // @[tlb.scala:60:79]
wire _ppn_data_T_149; // @[tlb.scala:60:79]
wire _ppn_data_T_148; // @[tlb.scala:60:79]
wire _ppn_data_T_147; // @[tlb.scala:60:79]
wire _ppn_data_T_146; // @[tlb.scala:60:79]
wire _ppn_data_T_145; // @[tlb.scala:60:79]
wire _ppn_data_T_144; // @[tlb.scala:60:79]
wire _ppn_data_T_143; // @[tlb.scala:60:79]
assign _ppn_data_T_143 = _ppn_data_WIRE_19[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_fragmented_superpage = _ppn_data_T_143; // @[tlb.scala:60:79]
assign _ppn_data_T_144 = _ppn_data_WIRE_19[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_c = _ppn_data_T_144; // @[tlb.scala:60:79]
assign _ppn_data_T_145 = _ppn_data_WIRE_19[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_eff = _ppn_data_T_145; // @[tlb.scala:60:79]
assign _ppn_data_T_146 = _ppn_data_WIRE_19[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_paa = _ppn_data_T_146; // @[tlb.scala:60:79]
assign _ppn_data_T_147 = _ppn_data_WIRE_19[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_pal = _ppn_data_T_147; // @[tlb.scala:60:79]
assign _ppn_data_T_148 = _ppn_data_WIRE_19[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_pr = _ppn_data_T_148; // @[tlb.scala:60:79]
assign _ppn_data_T_149 = _ppn_data_WIRE_19[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_px = _ppn_data_T_149; // @[tlb.scala:60:79]
assign _ppn_data_T_150 = _ppn_data_WIRE_19[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_pw = _ppn_data_T_150; // @[tlb.scala:60:79]
assign _ppn_data_T_151 = _ppn_data_WIRE_19[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_sr = _ppn_data_T_151; // @[tlb.scala:60:79]
assign _ppn_data_T_152 = _ppn_data_WIRE_19[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_sx = _ppn_data_T_152; // @[tlb.scala:60:79]
assign _ppn_data_T_153 = _ppn_data_WIRE_19[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_sw = _ppn_data_T_153; // @[tlb.scala:60:79]
assign _ppn_data_T_154 = _ppn_data_WIRE_19[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_ae = _ppn_data_T_154; // @[tlb.scala:60:79]
assign _ppn_data_T_155 = _ppn_data_WIRE_19[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_g = _ppn_data_T_155; // @[tlb.scala:60:79]
assign _ppn_data_T_156 = _ppn_data_WIRE_19[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_18_u = _ppn_data_T_156; // @[tlb.scala:60:79]
assign _ppn_data_T_157 = _ppn_data_WIRE_19[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_18_ppn = _ppn_data_T_157; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_172; // @[tlb.scala:60:79]
wire _ppn_data_T_171; // @[tlb.scala:60:79]
wire _ppn_data_T_170; // @[tlb.scala:60:79]
wire _ppn_data_T_169; // @[tlb.scala:60:79]
wire _ppn_data_T_168; // @[tlb.scala:60:79]
wire _ppn_data_T_167; // @[tlb.scala:60:79]
wire _ppn_data_T_166; // @[tlb.scala:60:79]
wire _ppn_data_T_165; // @[tlb.scala:60:79]
wire _ppn_data_T_164; // @[tlb.scala:60:79]
wire _ppn_data_T_163; // @[tlb.scala:60:79]
wire _ppn_data_T_162; // @[tlb.scala:60:79]
wire _ppn_data_T_161; // @[tlb.scala:60:79]
wire _ppn_data_T_160; // @[tlb.scala:60:79]
wire _ppn_data_T_159; // @[tlb.scala:60:79]
wire _ppn_data_T_158; // @[tlb.scala:60:79]
assign _ppn_data_T_158 = _ppn_data_WIRE_21[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_fragmented_superpage = _ppn_data_T_158; // @[tlb.scala:60:79]
assign _ppn_data_T_159 = _ppn_data_WIRE_21[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_c = _ppn_data_T_159; // @[tlb.scala:60:79]
assign _ppn_data_T_160 = _ppn_data_WIRE_21[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_eff = _ppn_data_T_160; // @[tlb.scala:60:79]
assign _ppn_data_T_161 = _ppn_data_WIRE_21[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_paa = _ppn_data_T_161; // @[tlb.scala:60:79]
assign _ppn_data_T_162 = _ppn_data_WIRE_21[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_pal = _ppn_data_T_162; // @[tlb.scala:60:79]
assign _ppn_data_T_163 = _ppn_data_WIRE_21[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_pr = _ppn_data_T_163; // @[tlb.scala:60:79]
assign _ppn_data_T_164 = _ppn_data_WIRE_21[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_px = _ppn_data_T_164; // @[tlb.scala:60:79]
assign _ppn_data_T_165 = _ppn_data_WIRE_21[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_pw = _ppn_data_T_165; // @[tlb.scala:60:79]
assign _ppn_data_T_166 = _ppn_data_WIRE_21[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_sr = _ppn_data_T_166; // @[tlb.scala:60:79]
assign _ppn_data_T_167 = _ppn_data_WIRE_21[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_sx = _ppn_data_T_167; // @[tlb.scala:60:79]
assign _ppn_data_T_168 = _ppn_data_WIRE_21[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_sw = _ppn_data_T_168; // @[tlb.scala:60:79]
assign _ppn_data_T_169 = _ppn_data_WIRE_21[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_ae = _ppn_data_T_169; // @[tlb.scala:60:79]
assign _ppn_data_T_170 = _ppn_data_WIRE_21[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_g = _ppn_data_T_170; // @[tlb.scala:60:79]
assign _ppn_data_T_171 = _ppn_data_WIRE_21[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_20_u = _ppn_data_T_171; // @[tlb.scala:60:79]
assign _ppn_data_T_172 = _ppn_data_WIRE_21[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_20_ppn = _ppn_data_T_172; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_187; // @[tlb.scala:60:79]
wire _ppn_data_T_186; // @[tlb.scala:60:79]
wire _ppn_data_T_185; // @[tlb.scala:60:79]
wire _ppn_data_T_184; // @[tlb.scala:60:79]
wire _ppn_data_T_183; // @[tlb.scala:60:79]
wire _ppn_data_T_182; // @[tlb.scala:60:79]
wire _ppn_data_T_181; // @[tlb.scala:60:79]
wire _ppn_data_T_180; // @[tlb.scala:60:79]
wire _ppn_data_T_179; // @[tlb.scala:60:79]
wire _ppn_data_T_178; // @[tlb.scala:60:79]
wire _ppn_data_T_177; // @[tlb.scala:60:79]
wire _ppn_data_T_176; // @[tlb.scala:60:79]
wire _ppn_data_T_175; // @[tlb.scala:60:79]
wire _ppn_data_T_174; // @[tlb.scala:60:79]
wire _ppn_data_T_173; // @[tlb.scala:60:79]
assign _ppn_data_T_173 = _ppn_data_WIRE_23[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_fragmented_superpage = _ppn_data_T_173; // @[tlb.scala:60:79]
assign _ppn_data_T_174 = _ppn_data_WIRE_23[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_c = _ppn_data_T_174; // @[tlb.scala:60:79]
assign _ppn_data_T_175 = _ppn_data_WIRE_23[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_eff = _ppn_data_T_175; // @[tlb.scala:60:79]
assign _ppn_data_T_176 = _ppn_data_WIRE_23[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_paa = _ppn_data_T_176; // @[tlb.scala:60:79]
assign _ppn_data_T_177 = _ppn_data_WIRE_23[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_pal = _ppn_data_T_177; // @[tlb.scala:60:79]
assign _ppn_data_T_178 = _ppn_data_WIRE_23[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_pr = _ppn_data_T_178; // @[tlb.scala:60:79]
assign _ppn_data_T_179 = _ppn_data_WIRE_23[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_px = _ppn_data_T_179; // @[tlb.scala:60:79]
assign _ppn_data_T_180 = _ppn_data_WIRE_23[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_pw = _ppn_data_T_180; // @[tlb.scala:60:79]
assign _ppn_data_T_181 = _ppn_data_WIRE_23[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_sr = _ppn_data_T_181; // @[tlb.scala:60:79]
assign _ppn_data_T_182 = _ppn_data_WIRE_23[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_sx = _ppn_data_T_182; // @[tlb.scala:60:79]
assign _ppn_data_T_183 = _ppn_data_WIRE_23[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_sw = _ppn_data_T_183; // @[tlb.scala:60:79]
assign _ppn_data_T_184 = _ppn_data_WIRE_23[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_ae = _ppn_data_T_184; // @[tlb.scala:60:79]
assign _ppn_data_T_185 = _ppn_data_WIRE_23[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_g = _ppn_data_T_185; // @[tlb.scala:60:79]
assign _ppn_data_T_186 = _ppn_data_WIRE_23[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_22_u = _ppn_data_T_186; // @[tlb.scala:60:79]
assign _ppn_data_T_187 = _ppn_data_WIRE_23[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_22_ppn = _ppn_data_T_187; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_T_202; // @[tlb.scala:60:79]
wire _ppn_data_T_201; // @[tlb.scala:60:79]
wire _ppn_data_T_200; // @[tlb.scala:60:79]
wire _ppn_data_T_199; // @[tlb.scala:60:79]
wire _ppn_data_T_198; // @[tlb.scala:60:79]
wire _ppn_data_T_197; // @[tlb.scala:60:79]
wire _ppn_data_T_196; // @[tlb.scala:60:79]
wire _ppn_data_T_195; // @[tlb.scala:60:79]
wire _ppn_data_T_194; // @[tlb.scala:60:79]
wire _ppn_data_T_193; // @[tlb.scala:60:79]
wire _ppn_data_T_192; // @[tlb.scala:60:79]
wire _ppn_data_T_191; // @[tlb.scala:60:79]
wire _ppn_data_T_190; // @[tlb.scala:60:79]
wire _ppn_data_T_189; // @[tlb.scala:60:79]
wire _ppn_data_T_188; // @[tlb.scala:60:79]
assign _ppn_data_T_188 = _ppn_data_WIRE_25[0]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_fragmented_superpage = _ppn_data_T_188; // @[tlb.scala:60:79]
assign _ppn_data_T_189 = _ppn_data_WIRE_25[1]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_c = _ppn_data_T_189; // @[tlb.scala:60:79]
assign _ppn_data_T_190 = _ppn_data_WIRE_25[2]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_eff = _ppn_data_T_190; // @[tlb.scala:60:79]
assign _ppn_data_T_191 = _ppn_data_WIRE_25[3]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_paa = _ppn_data_T_191; // @[tlb.scala:60:79]
assign _ppn_data_T_192 = _ppn_data_WIRE_25[4]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_pal = _ppn_data_T_192; // @[tlb.scala:60:79]
assign _ppn_data_T_193 = _ppn_data_WIRE_25[5]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_pr = _ppn_data_T_193; // @[tlb.scala:60:79]
assign _ppn_data_T_194 = _ppn_data_WIRE_25[6]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_px = _ppn_data_T_194; // @[tlb.scala:60:79]
assign _ppn_data_T_195 = _ppn_data_WIRE_25[7]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_pw = _ppn_data_T_195; // @[tlb.scala:60:79]
assign _ppn_data_T_196 = _ppn_data_WIRE_25[8]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_sr = _ppn_data_T_196; // @[tlb.scala:60:79]
assign _ppn_data_T_197 = _ppn_data_WIRE_25[9]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_sx = _ppn_data_T_197; // @[tlb.scala:60:79]
assign _ppn_data_T_198 = _ppn_data_WIRE_25[10]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_sw = _ppn_data_T_198; // @[tlb.scala:60:79]
assign _ppn_data_T_199 = _ppn_data_WIRE_25[11]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_ae = _ppn_data_T_199; // @[tlb.scala:60:79]
assign _ppn_data_T_200 = _ppn_data_WIRE_25[12]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_g = _ppn_data_T_200; // @[tlb.scala:60:79]
assign _ppn_data_T_201 = _ppn_data_WIRE_25[13]; // @[tlb.scala:60:79]
wire _ppn_data_WIRE_24_u = _ppn_data_T_201; // @[tlb.scala:60:79]
assign _ppn_data_T_202 = _ppn_data_WIRE_25[33:14]; // @[tlb.scala:60:79]
wire [19:0] _ppn_data_WIRE_24_ppn = _ppn_data_T_202; // @[tlb.scala:60:79]
wire [19:0] _ppn_T_1 = vpn_0[19:0]; // @[tlb.scala:121:49, :176:103]
wire [19:0] _ppn_T_15 = _ppn_T_1; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_28 = _ppn_T_15; // @[Mux.scala:30:73]
wire [19:0] _ppn_WIRE = _ppn_T_28; // @[Mux.scala:30:73]
wire [19:0] ppn_0 = _ppn_WIRE; // @[Mux.scala:30:73]
wire [1:0] _GEN_4 = {newEntry_eff, newEntry_c}; // @[tlb.scala:97:26, :181:24]
wire [1:0] special_entry_data_0_lo_lo_hi; // @[tlb.scala:97:26]
assign special_entry_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi; // @[tlb.scala:97:26]
assign superpage_entries_0_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi; // @[tlb.scala:97:26]
assign superpage_entries_1_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi; // @[tlb.scala:97:26]
assign superpage_entries_2_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi; // @[tlb.scala:97:26]
assign superpage_entries_3_data_0_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_0_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_0_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_1_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_1_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_2_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_2_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_3_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_3_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_4_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_4_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_5_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_5_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_6_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_6_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_7_data_lo_lo_hi; // @[tlb.scala:97:26]
assign sectored_entries_7_data_lo_lo_hi = _GEN_4; // @[tlb.scala:97:26]
wire [2:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [1:0] _GEN_5 = {newEntry_pal, newEntry_paa}; // @[tlb.scala:97:26, :181:24]
wire [1:0] special_entry_data_0_lo_hi_lo; // @[tlb.scala:97:26]
assign special_entry_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo; // @[tlb.scala:97:26]
assign superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo; // @[tlb.scala:97:26]
assign superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo; // @[tlb.scala:97:26]
assign superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo; // @[tlb.scala:97:26]
assign superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_0_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_0_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_1_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_1_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_2_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_2_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_3_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_3_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_4_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_4_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_5_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_5_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_6_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_6_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_7_data_lo_hi_lo; // @[tlb.scala:97:26]
assign sectored_entries_7_data_lo_hi_lo = _GEN_5; // @[tlb.scala:97:26]
wire [1:0] _GEN_6 = {newEntry_px, newEntry_pr}; // @[tlb.scala:97:26, :181:24]
wire [1:0] special_entry_data_0_lo_hi_hi; // @[tlb.scala:97:26]
assign special_entry_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_0_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_1_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_2_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_3_data_0_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_0_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_0_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_1_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_1_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_2_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_2_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_3_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_3_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_4_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_4_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_5_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_5_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_6_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_6_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_7_data_lo_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_7_data_lo_hi_hi = _GEN_6; // @[tlb.scala:97:26]
wire [3:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[tlb.scala:97:26]
wire [1:0] _GEN_7 = {1'h1, newEntry_pw}; // @[tlb.scala:97:26, :181:24]
wire [1:0] special_entry_data_0_hi_lo_lo; // @[tlb.scala:97:26]
assign special_entry_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo; // @[tlb.scala:97:26]
assign superpage_entries_0_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo; // @[tlb.scala:97:26]
assign superpage_entries_1_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo; // @[tlb.scala:97:26]
assign superpage_entries_2_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo; // @[tlb.scala:97:26]
assign superpage_entries_3_data_0_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_0_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_0_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_1_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_1_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_2_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_2_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_3_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_3_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_4_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_4_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_5_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_5_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_6_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_6_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [1:0] sectored_entries_7_data_hi_lo_lo; // @[tlb.scala:97:26]
assign sectored_entries_7_data_hi_lo_lo = _GEN_7; // @[tlb.scala:97:26]
wire [3:0] special_entry_data_0_hi_lo = {2'h2, special_entry_data_0_hi_lo_lo}; // @[tlb.scala:97:26]
wire [20:0] _GEN_8 = {newEntry_ppn, 1'h1}; // @[tlb.scala:97:26, :181:24]
wire [20:0] special_entry_data_0_hi_hi_hi; // @[tlb.scala:97:26]
assign special_entry_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_0_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_1_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_2_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi; // @[tlb.scala:97:26]
assign superpage_entries_3_data_0_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_0_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_0_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_1_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_1_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_2_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_2_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_3_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_3_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_4_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_4_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_5_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_5_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_6_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_6_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [20:0] sectored_entries_7_data_hi_hi_hi; // @[tlb.scala:97:26]
assign sectored_entries_7_data_hi_hi_hi = _GEN_8; // @[tlb.scala:97:26]
wire [22:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[tlb.scala:97:26]
wire [2:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_0_data_0_hi_lo = {2'h2, superpage_entries_0_data_0_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[tlb.scala:97:26]
wire [2:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_1_data_0_hi_lo = {2'h2, superpage_entries_1_data_0_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[tlb.scala:97:26]
wire [2:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_2_data_0_hi_lo = {2'h2, superpage_entries_2_data_0_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[tlb.scala:97:26]
wire [2:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] superpage_entries_3_data_0_hi_lo = {2'h2, superpage_entries_3_data_0_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_0_data_lo_lo = {sectored_entries_0_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_0_data_lo_hi = {sectored_entries_0_data_lo_hi_hi, sectored_entries_0_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_0_data_lo = {sectored_entries_0_data_lo_hi, sectored_entries_0_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_0_data_hi_lo = {2'h2, sectored_entries_0_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_0_data_hi_hi = {sectored_entries_0_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_0_data_hi = {sectored_entries_0_data_hi_hi, sectored_entries_0_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_0_data_T = {sectored_entries_0_data_hi, sectored_entries_0_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_1_data_lo_lo = {sectored_entries_1_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_1_data_lo_hi = {sectored_entries_1_data_lo_hi_hi, sectored_entries_1_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_1_data_lo = {sectored_entries_1_data_lo_hi, sectored_entries_1_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_1_data_hi_lo = {2'h2, sectored_entries_1_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_1_data_hi_hi = {sectored_entries_1_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_1_data_hi = {sectored_entries_1_data_hi_hi, sectored_entries_1_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_1_data_T = {sectored_entries_1_data_hi, sectored_entries_1_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_2_data_lo_lo = {sectored_entries_2_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_2_data_lo_hi = {sectored_entries_2_data_lo_hi_hi, sectored_entries_2_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_2_data_lo = {sectored_entries_2_data_lo_hi, sectored_entries_2_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_2_data_hi_lo = {2'h2, sectored_entries_2_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_2_data_hi_hi = {sectored_entries_2_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_2_data_hi = {sectored_entries_2_data_hi_hi, sectored_entries_2_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_2_data_T = {sectored_entries_2_data_hi, sectored_entries_2_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_3_data_lo_lo = {sectored_entries_3_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_3_data_lo_hi = {sectored_entries_3_data_lo_hi_hi, sectored_entries_3_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_3_data_lo = {sectored_entries_3_data_lo_hi, sectored_entries_3_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_3_data_hi_lo = {2'h2, sectored_entries_3_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_3_data_hi_hi = {sectored_entries_3_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_3_data_hi = {sectored_entries_3_data_hi_hi, sectored_entries_3_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_3_data_T = {sectored_entries_3_data_hi, sectored_entries_3_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_4_data_lo_lo = {sectored_entries_4_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_4_data_lo_hi = {sectored_entries_4_data_lo_hi_hi, sectored_entries_4_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_4_data_lo = {sectored_entries_4_data_lo_hi, sectored_entries_4_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_4_data_hi_lo = {2'h2, sectored_entries_4_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_4_data_hi_hi = {sectored_entries_4_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_4_data_hi = {sectored_entries_4_data_hi_hi, sectored_entries_4_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_4_data_T = {sectored_entries_4_data_hi, sectored_entries_4_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_5_data_lo_lo = {sectored_entries_5_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_5_data_lo_hi = {sectored_entries_5_data_lo_hi_hi, sectored_entries_5_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_5_data_lo = {sectored_entries_5_data_lo_hi, sectored_entries_5_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_5_data_hi_lo = {2'h2, sectored_entries_5_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_5_data_hi_hi = {sectored_entries_5_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_5_data_hi = {sectored_entries_5_data_hi_hi, sectored_entries_5_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_5_data_T = {sectored_entries_5_data_hi, sectored_entries_5_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_6_data_lo_lo = {sectored_entries_6_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_6_data_lo_hi = {sectored_entries_6_data_lo_hi_hi, sectored_entries_6_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_6_data_lo = {sectored_entries_6_data_lo_hi, sectored_entries_6_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_6_data_hi_lo = {2'h2, sectored_entries_6_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_6_data_hi_hi = {sectored_entries_6_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_6_data_hi = {sectored_entries_6_data_hi_hi, sectored_entries_6_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_6_data_T = {sectored_entries_6_data_hi, sectored_entries_6_data_lo}; // @[tlb.scala:97:26]
wire [2:0] sectored_entries_7_data_lo_lo = {sectored_entries_7_data_lo_lo_hi, 1'h0}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_7_data_lo_hi = {sectored_entries_7_data_lo_hi_hi, sectored_entries_7_data_lo_hi_lo}; // @[tlb.scala:97:26]
wire [6:0] sectored_entries_7_data_lo = {sectored_entries_7_data_lo_hi, sectored_entries_7_data_lo_lo}; // @[tlb.scala:97:26]
wire [3:0] sectored_entries_7_data_hi_lo = {2'h2, sectored_entries_7_data_hi_lo_lo}; // @[tlb.scala:97:26]
wire [22:0] sectored_entries_7_data_hi_hi = {sectored_entries_7_data_hi_hi_hi, 2'h0}; // @[tlb.scala:97:26]
wire [26:0] sectored_entries_7_data_hi = {sectored_entries_7_data_hi_hi, sectored_entries_7_data_hi_lo}; // @[tlb.scala:97:26]
wire [33:0] _sectored_entries_7_data_T = {sectored_entries_7_data_hi, sectored_entries_7_data_lo}; // @[tlb.scala:97:26]
wire [19:0] _entries_T_15; // @[tlb.scala:60:79]
wire _entries_T_14; // @[tlb.scala:60:79]
wire _entries_T_13; // @[tlb.scala:60:79]
wire _entries_T_12; // @[tlb.scala:60:79]
wire _entries_T_11; // @[tlb.scala:60:79]
wire _entries_T_10; // @[tlb.scala:60:79]
wire _entries_T_9; // @[tlb.scala:60:79]
wire _entries_T_8; // @[tlb.scala:60:79]
wire _entries_T_7; // @[tlb.scala:60:79]
wire _entries_T_6; // @[tlb.scala:60:79]
wire _entries_T_5; // @[tlb.scala:60:79]
wire _entries_T_4; // @[tlb.scala:60:79]
wire _entries_T_3; // @[tlb.scala:60:79]
wire _entries_T_2; // @[tlb.scala:60:79]
wire _entries_T_1; // @[tlb.scala:60:79]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[tlb.scala:60:79]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_c = _entries_T_2; // @[tlb.scala:60:79]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_eff = _entries_T_3; // @[tlb.scala:60:79]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_paa = _entries_T_4; // @[tlb.scala:60:79]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_pal = _entries_T_5; // @[tlb.scala:60:79]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_pr = _entries_T_6; // @[tlb.scala:60:79]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_px = _entries_T_7; // @[tlb.scala:60:79]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_pw = _entries_T_8; // @[tlb.scala:60:79]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_sr = _entries_T_9; // @[tlb.scala:60:79]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_sx = _entries_T_10; // @[tlb.scala:60:79]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_sw = _entries_T_11; // @[tlb.scala:60:79]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_ae = _entries_T_12; // @[tlb.scala:60:79]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_g = _entries_T_13; // @[tlb.scala:60:79]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_u = _entries_T_14; // @[tlb.scala:60:79]
assign _entries_T_15 = _entries_WIRE_1[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_ppn = _entries_T_15; // @[tlb.scala:60:79]
wire [19:0] _entries_T_31; // @[tlb.scala:60:79]
wire _entries_T_30; // @[tlb.scala:60:79]
wire _entries_T_29; // @[tlb.scala:60:79]
wire _entries_T_28; // @[tlb.scala:60:79]
wire _entries_T_27; // @[tlb.scala:60:79]
wire _entries_T_26; // @[tlb.scala:60:79]
wire _entries_T_25; // @[tlb.scala:60:79]
wire _entries_T_24; // @[tlb.scala:60:79]
wire _entries_T_23; // @[tlb.scala:60:79]
wire _entries_T_22; // @[tlb.scala:60:79]
wire _entries_T_21; // @[tlb.scala:60:79]
wire _entries_T_20; // @[tlb.scala:60:79]
wire _entries_T_19; // @[tlb.scala:60:79]
wire _entries_T_18; // @[tlb.scala:60:79]
wire _entries_T_17; // @[tlb.scala:60:79]
assign _entries_T_17 = _entries_WIRE_3[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_17; // @[tlb.scala:60:79]
assign _entries_T_18 = _entries_WIRE_3[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_c = _entries_T_18; // @[tlb.scala:60:79]
assign _entries_T_19 = _entries_WIRE_3[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_eff = _entries_T_19; // @[tlb.scala:60:79]
assign _entries_T_20 = _entries_WIRE_3[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_paa = _entries_T_20; // @[tlb.scala:60:79]
assign _entries_T_21 = _entries_WIRE_3[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_pal = _entries_T_21; // @[tlb.scala:60:79]
assign _entries_T_22 = _entries_WIRE_3[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_pr = _entries_T_22; // @[tlb.scala:60:79]
assign _entries_T_23 = _entries_WIRE_3[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_px = _entries_T_23; // @[tlb.scala:60:79]
assign _entries_T_24 = _entries_WIRE_3[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_pw = _entries_T_24; // @[tlb.scala:60:79]
assign _entries_T_25 = _entries_WIRE_3[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_sr = _entries_T_25; // @[tlb.scala:60:79]
assign _entries_T_26 = _entries_WIRE_3[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_sx = _entries_T_26; // @[tlb.scala:60:79]
assign _entries_T_27 = _entries_WIRE_3[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_sw = _entries_T_27; // @[tlb.scala:60:79]
assign _entries_T_28 = _entries_WIRE_3[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_ae = _entries_T_28; // @[tlb.scala:60:79]
assign _entries_T_29 = _entries_WIRE_3[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_g = _entries_T_29; // @[tlb.scala:60:79]
assign _entries_T_30 = _entries_WIRE_3[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_2_u = _entries_T_30; // @[tlb.scala:60:79]
assign _entries_T_31 = _entries_WIRE_3[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_31; // @[tlb.scala:60:79]
wire [19:0] _entries_T_47; // @[tlb.scala:60:79]
wire _entries_T_46; // @[tlb.scala:60:79]
wire _entries_T_45; // @[tlb.scala:60:79]
wire _entries_T_44; // @[tlb.scala:60:79]
wire _entries_T_43; // @[tlb.scala:60:79]
wire _entries_T_42; // @[tlb.scala:60:79]
wire _entries_T_41; // @[tlb.scala:60:79]
wire _entries_T_40; // @[tlb.scala:60:79]
wire _entries_T_39; // @[tlb.scala:60:79]
wire _entries_T_38; // @[tlb.scala:60:79]
wire _entries_T_37; // @[tlb.scala:60:79]
wire _entries_T_36; // @[tlb.scala:60:79]
wire _entries_T_35; // @[tlb.scala:60:79]
wire _entries_T_34; // @[tlb.scala:60:79]
wire _entries_T_33; // @[tlb.scala:60:79]
assign _entries_T_33 = _entries_WIRE_5[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_33; // @[tlb.scala:60:79]
assign _entries_T_34 = _entries_WIRE_5[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_c = _entries_T_34; // @[tlb.scala:60:79]
assign _entries_T_35 = _entries_WIRE_5[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_eff = _entries_T_35; // @[tlb.scala:60:79]
assign _entries_T_36 = _entries_WIRE_5[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_paa = _entries_T_36; // @[tlb.scala:60:79]
assign _entries_T_37 = _entries_WIRE_5[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_pal = _entries_T_37; // @[tlb.scala:60:79]
assign _entries_T_38 = _entries_WIRE_5[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_pr = _entries_T_38; // @[tlb.scala:60:79]
assign _entries_T_39 = _entries_WIRE_5[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_px = _entries_T_39; // @[tlb.scala:60:79]
assign _entries_T_40 = _entries_WIRE_5[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_pw = _entries_T_40; // @[tlb.scala:60:79]
assign _entries_T_41 = _entries_WIRE_5[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_sr = _entries_T_41; // @[tlb.scala:60:79]
assign _entries_T_42 = _entries_WIRE_5[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_sx = _entries_T_42; // @[tlb.scala:60:79]
assign _entries_T_43 = _entries_WIRE_5[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_sw = _entries_T_43; // @[tlb.scala:60:79]
assign _entries_T_44 = _entries_WIRE_5[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_ae = _entries_T_44; // @[tlb.scala:60:79]
assign _entries_T_45 = _entries_WIRE_5[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_g = _entries_T_45; // @[tlb.scala:60:79]
assign _entries_T_46 = _entries_WIRE_5[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_4_u = _entries_T_46; // @[tlb.scala:60:79]
assign _entries_T_47 = _entries_WIRE_5[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_47; // @[tlb.scala:60:79]
wire [19:0] _entries_T_63; // @[tlb.scala:60:79]
wire _entries_T_62; // @[tlb.scala:60:79]
wire _entries_T_61; // @[tlb.scala:60:79]
wire _entries_T_60; // @[tlb.scala:60:79]
wire _entries_T_59; // @[tlb.scala:60:79]
wire _entries_T_58; // @[tlb.scala:60:79]
wire _entries_T_57; // @[tlb.scala:60:79]
wire _entries_T_56; // @[tlb.scala:60:79]
wire _entries_T_55; // @[tlb.scala:60:79]
wire _entries_T_54; // @[tlb.scala:60:79]
wire _entries_T_53; // @[tlb.scala:60:79]
wire _entries_T_52; // @[tlb.scala:60:79]
wire _entries_T_51; // @[tlb.scala:60:79]
wire _entries_T_50; // @[tlb.scala:60:79]
wire _entries_T_49; // @[tlb.scala:60:79]
assign _entries_T_49 = _entries_WIRE_7[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_49; // @[tlb.scala:60:79]
assign _entries_T_50 = _entries_WIRE_7[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_c = _entries_T_50; // @[tlb.scala:60:79]
assign _entries_T_51 = _entries_WIRE_7[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_eff = _entries_T_51; // @[tlb.scala:60:79]
assign _entries_T_52 = _entries_WIRE_7[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_paa = _entries_T_52; // @[tlb.scala:60:79]
assign _entries_T_53 = _entries_WIRE_7[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_pal = _entries_T_53; // @[tlb.scala:60:79]
assign _entries_T_54 = _entries_WIRE_7[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_pr = _entries_T_54; // @[tlb.scala:60:79]
assign _entries_T_55 = _entries_WIRE_7[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_px = _entries_T_55; // @[tlb.scala:60:79]
assign _entries_T_56 = _entries_WIRE_7[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_pw = _entries_T_56; // @[tlb.scala:60:79]
assign _entries_T_57 = _entries_WIRE_7[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_sr = _entries_T_57; // @[tlb.scala:60:79]
assign _entries_T_58 = _entries_WIRE_7[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_sx = _entries_T_58; // @[tlb.scala:60:79]
assign _entries_T_59 = _entries_WIRE_7[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_sw = _entries_T_59; // @[tlb.scala:60:79]
assign _entries_T_60 = _entries_WIRE_7[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_ae = _entries_T_60; // @[tlb.scala:60:79]
assign _entries_T_61 = _entries_WIRE_7[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_g = _entries_T_61; // @[tlb.scala:60:79]
assign _entries_T_62 = _entries_WIRE_7[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_6_u = _entries_T_62; // @[tlb.scala:60:79]
assign _entries_T_63 = _entries_WIRE_7[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_63; // @[tlb.scala:60:79]
wire [19:0] _entries_T_79; // @[tlb.scala:60:79]
wire _entries_T_78; // @[tlb.scala:60:79]
wire _entries_T_77; // @[tlb.scala:60:79]
wire _entries_T_76; // @[tlb.scala:60:79]
wire _entries_T_75; // @[tlb.scala:60:79]
wire _entries_T_74; // @[tlb.scala:60:79]
wire _entries_T_73; // @[tlb.scala:60:79]
wire _entries_T_72; // @[tlb.scala:60:79]
wire _entries_T_71; // @[tlb.scala:60:79]
wire _entries_T_70; // @[tlb.scala:60:79]
wire _entries_T_69; // @[tlb.scala:60:79]
wire _entries_T_68; // @[tlb.scala:60:79]
wire _entries_T_67; // @[tlb.scala:60:79]
wire _entries_T_66; // @[tlb.scala:60:79]
wire _entries_T_65; // @[tlb.scala:60:79]
assign _entries_T_65 = _entries_WIRE_9[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_65; // @[tlb.scala:60:79]
assign _entries_T_66 = _entries_WIRE_9[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_c = _entries_T_66; // @[tlb.scala:60:79]
assign _entries_T_67 = _entries_WIRE_9[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_eff = _entries_T_67; // @[tlb.scala:60:79]
assign _entries_T_68 = _entries_WIRE_9[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_paa = _entries_T_68; // @[tlb.scala:60:79]
assign _entries_T_69 = _entries_WIRE_9[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_pal = _entries_T_69; // @[tlb.scala:60:79]
assign _entries_T_70 = _entries_WIRE_9[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_pr = _entries_T_70; // @[tlb.scala:60:79]
assign _entries_T_71 = _entries_WIRE_9[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_px = _entries_T_71; // @[tlb.scala:60:79]
assign _entries_T_72 = _entries_WIRE_9[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_pw = _entries_T_72; // @[tlb.scala:60:79]
assign _entries_T_73 = _entries_WIRE_9[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_sr = _entries_T_73; // @[tlb.scala:60:79]
assign _entries_T_74 = _entries_WIRE_9[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_sx = _entries_T_74; // @[tlb.scala:60:79]
assign _entries_T_75 = _entries_WIRE_9[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_sw = _entries_T_75; // @[tlb.scala:60:79]
assign _entries_T_76 = _entries_WIRE_9[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_ae = _entries_T_76; // @[tlb.scala:60:79]
assign _entries_T_77 = _entries_WIRE_9[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_g = _entries_T_77; // @[tlb.scala:60:79]
assign _entries_T_78 = _entries_WIRE_9[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_8_u = _entries_T_78; // @[tlb.scala:60:79]
assign _entries_T_79 = _entries_WIRE_9[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_79; // @[tlb.scala:60:79]
wire [19:0] _entries_T_95; // @[tlb.scala:60:79]
wire _entries_T_94; // @[tlb.scala:60:79]
wire _entries_T_93; // @[tlb.scala:60:79]
wire _entries_T_92; // @[tlb.scala:60:79]
wire _entries_T_91; // @[tlb.scala:60:79]
wire _entries_T_90; // @[tlb.scala:60:79]
wire _entries_T_89; // @[tlb.scala:60:79]
wire _entries_T_88; // @[tlb.scala:60:79]
wire _entries_T_87; // @[tlb.scala:60:79]
wire _entries_T_86; // @[tlb.scala:60:79]
wire _entries_T_85; // @[tlb.scala:60:79]
wire _entries_T_84; // @[tlb.scala:60:79]
wire _entries_T_83; // @[tlb.scala:60:79]
wire _entries_T_82; // @[tlb.scala:60:79]
wire _entries_T_81; // @[tlb.scala:60:79]
assign _entries_T_81 = _entries_WIRE_11[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_81; // @[tlb.scala:60:79]
assign _entries_T_82 = _entries_WIRE_11[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_c = _entries_T_82; // @[tlb.scala:60:79]
assign _entries_T_83 = _entries_WIRE_11[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_eff = _entries_T_83; // @[tlb.scala:60:79]
assign _entries_T_84 = _entries_WIRE_11[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_paa = _entries_T_84; // @[tlb.scala:60:79]
assign _entries_T_85 = _entries_WIRE_11[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_pal = _entries_T_85; // @[tlb.scala:60:79]
assign _entries_T_86 = _entries_WIRE_11[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_pr = _entries_T_86; // @[tlb.scala:60:79]
assign _entries_T_87 = _entries_WIRE_11[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_px = _entries_T_87; // @[tlb.scala:60:79]
assign _entries_T_88 = _entries_WIRE_11[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_pw = _entries_T_88; // @[tlb.scala:60:79]
assign _entries_T_89 = _entries_WIRE_11[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_sr = _entries_T_89; // @[tlb.scala:60:79]
assign _entries_T_90 = _entries_WIRE_11[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_sx = _entries_T_90; // @[tlb.scala:60:79]
assign _entries_T_91 = _entries_WIRE_11[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_sw = _entries_T_91; // @[tlb.scala:60:79]
assign _entries_T_92 = _entries_WIRE_11[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_ae = _entries_T_92; // @[tlb.scala:60:79]
assign _entries_T_93 = _entries_WIRE_11[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_g = _entries_T_93; // @[tlb.scala:60:79]
assign _entries_T_94 = _entries_WIRE_11[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_10_u = _entries_T_94; // @[tlb.scala:60:79]
assign _entries_T_95 = _entries_WIRE_11[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_95; // @[tlb.scala:60:79]
wire [19:0] _entries_T_111; // @[tlb.scala:60:79]
wire _entries_T_110; // @[tlb.scala:60:79]
wire _entries_T_109; // @[tlb.scala:60:79]
wire _entries_T_108; // @[tlb.scala:60:79]
wire _entries_T_107; // @[tlb.scala:60:79]
wire _entries_T_106; // @[tlb.scala:60:79]
wire _entries_T_105; // @[tlb.scala:60:79]
wire _entries_T_104; // @[tlb.scala:60:79]
wire _entries_T_103; // @[tlb.scala:60:79]
wire _entries_T_102; // @[tlb.scala:60:79]
wire _entries_T_101; // @[tlb.scala:60:79]
wire _entries_T_100; // @[tlb.scala:60:79]
wire _entries_T_99; // @[tlb.scala:60:79]
wire _entries_T_98; // @[tlb.scala:60:79]
wire _entries_T_97; // @[tlb.scala:60:79]
assign _entries_T_97 = _entries_WIRE_13[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_97; // @[tlb.scala:60:79]
assign _entries_T_98 = _entries_WIRE_13[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_c = _entries_T_98; // @[tlb.scala:60:79]
assign _entries_T_99 = _entries_WIRE_13[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_eff = _entries_T_99; // @[tlb.scala:60:79]
assign _entries_T_100 = _entries_WIRE_13[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_paa = _entries_T_100; // @[tlb.scala:60:79]
assign _entries_T_101 = _entries_WIRE_13[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_pal = _entries_T_101; // @[tlb.scala:60:79]
assign _entries_T_102 = _entries_WIRE_13[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_pr = _entries_T_102; // @[tlb.scala:60:79]
assign _entries_T_103 = _entries_WIRE_13[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_px = _entries_T_103; // @[tlb.scala:60:79]
assign _entries_T_104 = _entries_WIRE_13[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_pw = _entries_T_104; // @[tlb.scala:60:79]
assign _entries_T_105 = _entries_WIRE_13[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_sr = _entries_T_105; // @[tlb.scala:60:79]
assign _entries_T_106 = _entries_WIRE_13[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_sx = _entries_T_106; // @[tlb.scala:60:79]
assign _entries_T_107 = _entries_WIRE_13[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_sw = _entries_T_107; // @[tlb.scala:60:79]
assign _entries_T_108 = _entries_WIRE_13[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_ae = _entries_T_108; // @[tlb.scala:60:79]
assign _entries_T_109 = _entries_WIRE_13[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_g = _entries_T_109; // @[tlb.scala:60:79]
assign _entries_T_110 = _entries_WIRE_13[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_12_u = _entries_T_110; // @[tlb.scala:60:79]
assign _entries_T_111 = _entries_WIRE_13[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_111; // @[tlb.scala:60:79]
wire [19:0] _entries_T_127; // @[tlb.scala:60:79]
wire _entries_T_126; // @[tlb.scala:60:79]
wire _entries_T_125; // @[tlb.scala:60:79]
wire _entries_T_124; // @[tlb.scala:60:79]
wire _entries_T_123; // @[tlb.scala:60:79]
wire _entries_T_122; // @[tlb.scala:60:79]
wire _entries_T_121; // @[tlb.scala:60:79]
wire _entries_T_120; // @[tlb.scala:60:79]
wire _entries_T_119; // @[tlb.scala:60:79]
wire _entries_T_118; // @[tlb.scala:60:79]
wire _entries_T_117; // @[tlb.scala:60:79]
wire _entries_T_116; // @[tlb.scala:60:79]
wire _entries_T_115; // @[tlb.scala:60:79]
wire _entries_T_114; // @[tlb.scala:60:79]
wire _entries_T_113; // @[tlb.scala:60:79]
assign _entries_T_113 = _entries_WIRE_15[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_113; // @[tlb.scala:60:79]
assign _entries_T_114 = _entries_WIRE_15[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_c = _entries_T_114; // @[tlb.scala:60:79]
assign _entries_T_115 = _entries_WIRE_15[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_eff = _entries_T_115; // @[tlb.scala:60:79]
assign _entries_T_116 = _entries_WIRE_15[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_paa = _entries_T_116; // @[tlb.scala:60:79]
assign _entries_T_117 = _entries_WIRE_15[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_pal = _entries_T_117; // @[tlb.scala:60:79]
assign _entries_T_118 = _entries_WIRE_15[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_pr = _entries_T_118; // @[tlb.scala:60:79]
assign _entries_T_119 = _entries_WIRE_15[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_px = _entries_T_119; // @[tlb.scala:60:79]
assign _entries_T_120 = _entries_WIRE_15[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_pw = _entries_T_120; // @[tlb.scala:60:79]
assign _entries_T_121 = _entries_WIRE_15[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_sr = _entries_T_121; // @[tlb.scala:60:79]
assign _entries_T_122 = _entries_WIRE_15[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_sx = _entries_T_122; // @[tlb.scala:60:79]
assign _entries_T_123 = _entries_WIRE_15[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_sw = _entries_T_123; // @[tlb.scala:60:79]
assign _entries_T_124 = _entries_WIRE_15[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_ae = _entries_T_124; // @[tlb.scala:60:79]
assign _entries_T_125 = _entries_WIRE_15[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_g = _entries_T_125; // @[tlb.scala:60:79]
assign _entries_T_126 = _entries_WIRE_15[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_14_u = _entries_T_126; // @[tlb.scala:60:79]
assign _entries_T_127 = _entries_WIRE_15[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_127; // @[tlb.scala:60:79]
wire [19:0] _entries_T_142; // @[tlb.scala:60:79]
wire _entries_T_141; // @[tlb.scala:60:79]
wire _entries_T_140; // @[tlb.scala:60:79]
wire _entries_T_139; // @[tlb.scala:60:79]
wire _entries_T_138; // @[tlb.scala:60:79]
wire _entries_T_137; // @[tlb.scala:60:79]
wire _entries_T_136; // @[tlb.scala:60:79]
wire _entries_T_135; // @[tlb.scala:60:79]
wire _entries_T_134; // @[tlb.scala:60:79]
wire _entries_T_133; // @[tlb.scala:60:79]
wire _entries_T_132; // @[tlb.scala:60:79]
wire _entries_T_131; // @[tlb.scala:60:79]
wire _entries_T_130; // @[tlb.scala:60:79]
wire _entries_T_129; // @[tlb.scala:60:79]
wire _entries_T_128; // @[tlb.scala:60:79]
assign _entries_T_128 = _entries_WIRE_17[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_128; // @[tlb.scala:60:79]
assign _entries_T_129 = _entries_WIRE_17[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_c = _entries_T_129; // @[tlb.scala:60:79]
assign _entries_T_130 = _entries_WIRE_17[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_eff = _entries_T_130; // @[tlb.scala:60:79]
assign _entries_T_131 = _entries_WIRE_17[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_paa = _entries_T_131; // @[tlb.scala:60:79]
assign _entries_T_132 = _entries_WIRE_17[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_pal = _entries_T_132; // @[tlb.scala:60:79]
assign _entries_T_133 = _entries_WIRE_17[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_pr = _entries_T_133; // @[tlb.scala:60:79]
assign _entries_T_134 = _entries_WIRE_17[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_px = _entries_T_134; // @[tlb.scala:60:79]
assign _entries_T_135 = _entries_WIRE_17[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_pw = _entries_T_135; // @[tlb.scala:60:79]
assign _entries_T_136 = _entries_WIRE_17[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_sr = _entries_T_136; // @[tlb.scala:60:79]
assign _entries_T_137 = _entries_WIRE_17[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_sx = _entries_T_137; // @[tlb.scala:60:79]
assign _entries_T_138 = _entries_WIRE_17[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_sw = _entries_T_138; // @[tlb.scala:60:79]
assign _entries_T_139 = _entries_WIRE_17[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_ae = _entries_T_139; // @[tlb.scala:60:79]
assign _entries_T_140 = _entries_WIRE_17[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_g = _entries_T_140; // @[tlb.scala:60:79]
assign _entries_T_141 = _entries_WIRE_17[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_16_u = _entries_T_141; // @[tlb.scala:60:79]
assign _entries_T_142 = _entries_WIRE_17[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_142; // @[tlb.scala:60:79]
wire [19:0] _entries_T_157; // @[tlb.scala:60:79]
wire _entries_T_156; // @[tlb.scala:60:79]
wire _entries_T_155; // @[tlb.scala:60:79]
wire _entries_T_154; // @[tlb.scala:60:79]
wire _entries_T_153; // @[tlb.scala:60:79]
wire _entries_T_152; // @[tlb.scala:60:79]
wire _entries_T_151; // @[tlb.scala:60:79]
wire _entries_T_150; // @[tlb.scala:60:79]
wire _entries_T_149; // @[tlb.scala:60:79]
wire _entries_T_148; // @[tlb.scala:60:79]
wire _entries_T_147; // @[tlb.scala:60:79]
wire _entries_T_146; // @[tlb.scala:60:79]
wire _entries_T_145; // @[tlb.scala:60:79]
wire _entries_T_144; // @[tlb.scala:60:79]
wire _entries_T_143; // @[tlb.scala:60:79]
assign _entries_T_143 = _entries_WIRE_19[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_143; // @[tlb.scala:60:79]
assign _entries_T_144 = _entries_WIRE_19[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_c = _entries_T_144; // @[tlb.scala:60:79]
assign _entries_T_145 = _entries_WIRE_19[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_eff = _entries_T_145; // @[tlb.scala:60:79]
assign _entries_T_146 = _entries_WIRE_19[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_paa = _entries_T_146; // @[tlb.scala:60:79]
assign _entries_T_147 = _entries_WIRE_19[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_pal = _entries_T_147; // @[tlb.scala:60:79]
assign _entries_T_148 = _entries_WIRE_19[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_pr = _entries_T_148; // @[tlb.scala:60:79]
assign _entries_T_149 = _entries_WIRE_19[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_px = _entries_T_149; // @[tlb.scala:60:79]
assign _entries_T_150 = _entries_WIRE_19[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_pw = _entries_T_150; // @[tlb.scala:60:79]
assign _entries_T_151 = _entries_WIRE_19[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_sr = _entries_T_151; // @[tlb.scala:60:79]
assign _entries_T_152 = _entries_WIRE_19[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_sx = _entries_T_152; // @[tlb.scala:60:79]
assign _entries_T_153 = _entries_WIRE_19[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_sw = _entries_T_153; // @[tlb.scala:60:79]
assign _entries_T_154 = _entries_WIRE_19[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_ae = _entries_T_154; // @[tlb.scala:60:79]
assign _entries_T_155 = _entries_WIRE_19[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_g = _entries_T_155; // @[tlb.scala:60:79]
assign _entries_T_156 = _entries_WIRE_19[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_18_u = _entries_T_156; // @[tlb.scala:60:79]
assign _entries_T_157 = _entries_WIRE_19[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_157; // @[tlb.scala:60:79]
wire [19:0] _entries_T_172; // @[tlb.scala:60:79]
wire _entries_T_171; // @[tlb.scala:60:79]
wire _entries_T_170; // @[tlb.scala:60:79]
wire _entries_T_169; // @[tlb.scala:60:79]
wire _entries_T_168; // @[tlb.scala:60:79]
wire _entries_T_167; // @[tlb.scala:60:79]
wire _entries_T_166; // @[tlb.scala:60:79]
wire _entries_T_165; // @[tlb.scala:60:79]
wire _entries_T_164; // @[tlb.scala:60:79]
wire _entries_T_163; // @[tlb.scala:60:79]
wire _entries_T_162; // @[tlb.scala:60:79]
wire _entries_T_161; // @[tlb.scala:60:79]
wire _entries_T_160; // @[tlb.scala:60:79]
wire _entries_T_159; // @[tlb.scala:60:79]
wire _entries_T_158; // @[tlb.scala:60:79]
assign _entries_T_158 = _entries_WIRE_21[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_158; // @[tlb.scala:60:79]
assign _entries_T_159 = _entries_WIRE_21[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_c = _entries_T_159; // @[tlb.scala:60:79]
assign _entries_T_160 = _entries_WIRE_21[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_eff = _entries_T_160; // @[tlb.scala:60:79]
assign _entries_T_161 = _entries_WIRE_21[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_paa = _entries_T_161; // @[tlb.scala:60:79]
assign _entries_T_162 = _entries_WIRE_21[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_pal = _entries_T_162; // @[tlb.scala:60:79]
assign _entries_T_163 = _entries_WIRE_21[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_pr = _entries_T_163; // @[tlb.scala:60:79]
assign _entries_T_164 = _entries_WIRE_21[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_px = _entries_T_164; // @[tlb.scala:60:79]
assign _entries_T_165 = _entries_WIRE_21[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_pw = _entries_T_165; // @[tlb.scala:60:79]
assign _entries_T_166 = _entries_WIRE_21[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_sr = _entries_T_166; // @[tlb.scala:60:79]
assign _entries_T_167 = _entries_WIRE_21[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_sx = _entries_T_167; // @[tlb.scala:60:79]
assign _entries_T_168 = _entries_WIRE_21[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_sw = _entries_T_168; // @[tlb.scala:60:79]
assign _entries_T_169 = _entries_WIRE_21[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_ae = _entries_T_169; // @[tlb.scala:60:79]
assign _entries_T_170 = _entries_WIRE_21[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_g = _entries_T_170; // @[tlb.scala:60:79]
assign _entries_T_171 = _entries_WIRE_21[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_20_u = _entries_T_171; // @[tlb.scala:60:79]
assign _entries_T_172 = _entries_WIRE_21[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_172; // @[tlb.scala:60:79]
wire [19:0] _entries_T_187; // @[tlb.scala:60:79]
wire _entries_T_186; // @[tlb.scala:60:79]
wire _entries_T_185; // @[tlb.scala:60:79]
wire _entries_T_184; // @[tlb.scala:60:79]
wire _entries_T_183; // @[tlb.scala:60:79]
wire _entries_T_182; // @[tlb.scala:60:79]
wire _entries_T_181; // @[tlb.scala:60:79]
wire _entries_T_180; // @[tlb.scala:60:79]
wire _entries_T_179; // @[tlb.scala:60:79]
wire _entries_T_178; // @[tlb.scala:60:79]
wire _entries_T_177; // @[tlb.scala:60:79]
wire _entries_T_176; // @[tlb.scala:60:79]
wire _entries_T_175; // @[tlb.scala:60:79]
wire _entries_T_174; // @[tlb.scala:60:79]
wire _entries_T_173; // @[tlb.scala:60:79]
assign _entries_T_173 = _entries_WIRE_23[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_173; // @[tlb.scala:60:79]
assign _entries_T_174 = _entries_WIRE_23[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_c = _entries_T_174; // @[tlb.scala:60:79]
assign _entries_T_175 = _entries_WIRE_23[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_eff = _entries_T_175; // @[tlb.scala:60:79]
assign _entries_T_176 = _entries_WIRE_23[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_paa = _entries_T_176; // @[tlb.scala:60:79]
assign _entries_T_177 = _entries_WIRE_23[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_pal = _entries_T_177; // @[tlb.scala:60:79]
assign _entries_T_178 = _entries_WIRE_23[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_pr = _entries_T_178; // @[tlb.scala:60:79]
assign _entries_T_179 = _entries_WIRE_23[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_px = _entries_T_179; // @[tlb.scala:60:79]
assign _entries_T_180 = _entries_WIRE_23[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_pw = _entries_T_180; // @[tlb.scala:60:79]
assign _entries_T_181 = _entries_WIRE_23[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_sr = _entries_T_181; // @[tlb.scala:60:79]
assign _entries_T_182 = _entries_WIRE_23[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_sx = _entries_T_182; // @[tlb.scala:60:79]
assign _entries_T_183 = _entries_WIRE_23[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_sw = _entries_T_183; // @[tlb.scala:60:79]
assign _entries_T_184 = _entries_WIRE_23[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_ae = _entries_T_184; // @[tlb.scala:60:79]
assign _entries_T_185 = _entries_WIRE_23[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_g = _entries_T_185; // @[tlb.scala:60:79]
assign _entries_T_186 = _entries_WIRE_23[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_22_u = _entries_T_186; // @[tlb.scala:60:79]
assign _entries_T_187 = _entries_WIRE_23[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_187; // @[tlb.scala:60:79]
wire [19:0] _entries_T_202; // @[tlb.scala:60:79]
wire _entries_T_201; // @[tlb.scala:60:79]
wire _entries_T_200; // @[tlb.scala:60:79]
wire _entries_T_199; // @[tlb.scala:60:79]
wire _entries_T_198; // @[tlb.scala:60:79]
wire _entries_T_197; // @[tlb.scala:60:79]
wire _entries_T_196; // @[tlb.scala:60:79]
wire _entries_T_195; // @[tlb.scala:60:79]
wire _entries_T_194; // @[tlb.scala:60:79]
wire _entries_T_193; // @[tlb.scala:60:79]
wire _entries_T_192; // @[tlb.scala:60:79]
wire _entries_T_191; // @[tlb.scala:60:79]
wire _entries_T_190; // @[tlb.scala:60:79]
wire _entries_T_189; // @[tlb.scala:60:79]
wire _entries_T_188; // @[tlb.scala:60:79]
assign _entries_T_188 = _entries_WIRE_25[0]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_188; // @[tlb.scala:60:79]
assign _entries_T_189 = _entries_WIRE_25[1]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_c = _entries_T_189; // @[tlb.scala:60:79]
assign _entries_T_190 = _entries_WIRE_25[2]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_eff = _entries_T_190; // @[tlb.scala:60:79]
assign _entries_T_191 = _entries_WIRE_25[3]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_paa = _entries_T_191; // @[tlb.scala:60:79]
assign _entries_T_192 = _entries_WIRE_25[4]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_pal = _entries_T_192; // @[tlb.scala:60:79]
assign _entries_T_193 = _entries_WIRE_25[5]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_pr = _entries_T_193; // @[tlb.scala:60:79]
assign _entries_T_194 = _entries_WIRE_25[6]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_px = _entries_T_194; // @[tlb.scala:60:79]
assign _entries_T_195 = _entries_WIRE_25[7]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_pw = _entries_T_195; // @[tlb.scala:60:79]
assign _entries_T_196 = _entries_WIRE_25[8]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_sr = _entries_T_196; // @[tlb.scala:60:79]
assign _entries_T_197 = _entries_WIRE_25[9]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_sx = _entries_T_197; // @[tlb.scala:60:79]
assign _entries_T_198 = _entries_WIRE_25[10]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_sw = _entries_T_198; // @[tlb.scala:60:79]
assign _entries_T_199 = _entries_WIRE_25[11]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_ae = _entries_T_199; // @[tlb.scala:60:79]
assign _entries_T_200 = _entries_WIRE_25[12]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_g = _entries_T_200; // @[tlb.scala:60:79]
assign _entries_T_201 = _entries_WIRE_25[13]; // @[tlb.scala:60:79]
wire _entries_WIRE_24_u = _entries_T_201; // @[tlb.scala:60:79]
assign _entries_T_202 = _entries_WIRE_25[33:14]; // @[tlb.scala:60:79]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_202; // @[tlb.scala:60:79]
wire [19:0] entries_0_0_ppn = _entries_WIRE_26_0_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_u = _entries_WIRE_26_0_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_g = _entries_WIRE_26_0_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_ae = _entries_WIRE_26_0_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_sw = _entries_WIRE_26_0_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_sx = _entries_WIRE_26_0_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_sr = _entries_WIRE_26_0_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_pw = _entries_WIRE_26_0_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_px = _entries_WIRE_26_0_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_pr = _entries_WIRE_26_0_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_pal = _entries_WIRE_26_0_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_paa = _entries_WIRE_26_0_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_eff = _entries_WIRE_26_0_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_c = _entries_WIRE_26_0_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_0_fragmented_superpage = _entries_WIRE_26_0_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_1_ppn = _entries_WIRE_26_1_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_u = _entries_WIRE_26_1_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_g = _entries_WIRE_26_1_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_ae = _entries_WIRE_26_1_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_sw = _entries_WIRE_26_1_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_sx = _entries_WIRE_26_1_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_sr = _entries_WIRE_26_1_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_pw = _entries_WIRE_26_1_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_px = _entries_WIRE_26_1_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_pr = _entries_WIRE_26_1_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_pal = _entries_WIRE_26_1_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_paa = _entries_WIRE_26_1_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_eff = _entries_WIRE_26_1_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_c = _entries_WIRE_26_1_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_1_fragmented_superpage = _entries_WIRE_26_1_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_2_ppn = _entries_WIRE_26_2_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_u = _entries_WIRE_26_2_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_g = _entries_WIRE_26_2_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_ae = _entries_WIRE_26_2_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_sw = _entries_WIRE_26_2_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_sx = _entries_WIRE_26_2_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_sr = _entries_WIRE_26_2_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_pw = _entries_WIRE_26_2_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_px = _entries_WIRE_26_2_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_pr = _entries_WIRE_26_2_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_pal = _entries_WIRE_26_2_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_paa = _entries_WIRE_26_2_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_eff = _entries_WIRE_26_2_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_c = _entries_WIRE_26_2_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_2_fragmented_superpage = _entries_WIRE_26_2_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_3_ppn = _entries_WIRE_26_3_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_u = _entries_WIRE_26_3_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_g = _entries_WIRE_26_3_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_ae = _entries_WIRE_26_3_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_sw = _entries_WIRE_26_3_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_sx = _entries_WIRE_26_3_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_sr = _entries_WIRE_26_3_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_pw = _entries_WIRE_26_3_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_px = _entries_WIRE_26_3_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_pr = _entries_WIRE_26_3_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_pal = _entries_WIRE_26_3_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_paa = _entries_WIRE_26_3_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_eff = _entries_WIRE_26_3_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_c = _entries_WIRE_26_3_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_3_fragmented_superpage = _entries_WIRE_26_3_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_4_ppn = _entries_WIRE_26_4_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_u = _entries_WIRE_26_4_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_g = _entries_WIRE_26_4_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_ae = _entries_WIRE_26_4_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_sw = _entries_WIRE_26_4_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_sx = _entries_WIRE_26_4_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_sr = _entries_WIRE_26_4_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_pw = _entries_WIRE_26_4_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_px = _entries_WIRE_26_4_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_pr = _entries_WIRE_26_4_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_pal = _entries_WIRE_26_4_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_paa = _entries_WIRE_26_4_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_eff = _entries_WIRE_26_4_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_c = _entries_WIRE_26_4_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_4_fragmented_superpage = _entries_WIRE_26_4_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_5_ppn = _entries_WIRE_26_5_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_u = _entries_WIRE_26_5_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_g = _entries_WIRE_26_5_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_ae = _entries_WIRE_26_5_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_sw = _entries_WIRE_26_5_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_sx = _entries_WIRE_26_5_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_sr = _entries_WIRE_26_5_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_pw = _entries_WIRE_26_5_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_px = _entries_WIRE_26_5_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_pr = _entries_WIRE_26_5_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_pal = _entries_WIRE_26_5_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_paa = _entries_WIRE_26_5_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_eff = _entries_WIRE_26_5_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_c = _entries_WIRE_26_5_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_5_fragmented_superpage = _entries_WIRE_26_5_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_6_ppn = _entries_WIRE_26_6_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_u = _entries_WIRE_26_6_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_g = _entries_WIRE_26_6_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_ae = _entries_WIRE_26_6_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_sw = _entries_WIRE_26_6_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_sx = _entries_WIRE_26_6_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_sr = _entries_WIRE_26_6_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_pw = _entries_WIRE_26_6_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_px = _entries_WIRE_26_6_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_pr = _entries_WIRE_26_6_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_pal = _entries_WIRE_26_6_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_paa = _entries_WIRE_26_6_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_eff = _entries_WIRE_26_6_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_c = _entries_WIRE_26_6_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_6_fragmented_superpage = _entries_WIRE_26_6_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_7_ppn = _entries_WIRE_26_7_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_u = _entries_WIRE_26_7_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_g = _entries_WIRE_26_7_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_ae = _entries_WIRE_26_7_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_sw = _entries_WIRE_26_7_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_sx = _entries_WIRE_26_7_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_sr = _entries_WIRE_26_7_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_pw = _entries_WIRE_26_7_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_px = _entries_WIRE_26_7_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_pr = _entries_WIRE_26_7_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_pal = _entries_WIRE_26_7_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_paa = _entries_WIRE_26_7_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_eff = _entries_WIRE_26_7_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_c = _entries_WIRE_26_7_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_7_fragmented_superpage = _entries_WIRE_26_7_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_8_ppn = _entries_WIRE_26_8_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_u = _entries_WIRE_26_8_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_g = _entries_WIRE_26_8_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_ae = _entries_WIRE_26_8_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_sw = _entries_WIRE_26_8_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_sx = _entries_WIRE_26_8_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_sr = _entries_WIRE_26_8_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_pw = _entries_WIRE_26_8_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_px = _entries_WIRE_26_8_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_pr = _entries_WIRE_26_8_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_pal = _entries_WIRE_26_8_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_paa = _entries_WIRE_26_8_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_eff = _entries_WIRE_26_8_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_c = _entries_WIRE_26_8_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_8_fragmented_superpage = _entries_WIRE_26_8_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_9_ppn = _entries_WIRE_26_9_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_u = _entries_WIRE_26_9_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_g = _entries_WIRE_26_9_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_ae = _entries_WIRE_26_9_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_sw = _entries_WIRE_26_9_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_sx = _entries_WIRE_26_9_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_sr = _entries_WIRE_26_9_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_pw = _entries_WIRE_26_9_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_px = _entries_WIRE_26_9_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_pr = _entries_WIRE_26_9_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_pal = _entries_WIRE_26_9_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_paa = _entries_WIRE_26_9_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_eff = _entries_WIRE_26_9_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_c = _entries_WIRE_26_9_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_9_fragmented_superpage = _entries_WIRE_26_9_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_10_ppn = _entries_WIRE_26_10_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_u = _entries_WIRE_26_10_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_g = _entries_WIRE_26_10_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_ae = _entries_WIRE_26_10_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_sw = _entries_WIRE_26_10_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_sx = _entries_WIRE_26_10_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_sr = _entries_WIRE_26_10_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_pw = _entries_WIRE_26_10_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_px = _entries_WIRE_26_10_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_pr = _entries_WIRE_26_10_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_pal = _entries_WIRE_26_10_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_paa = _entries_WIRE_26_10_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_eff = _entries_WIRE_26_10_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_c = _entries_WIRE_26_10_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_10_fragmented_superpage = _entries_WIRE_26_10_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_11_ppn = _entries_WIRE_26_11_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_u = _entries_WIRE_26_11_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_g = _entries_WIRE_26_11_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_ae = _entries_WIRE_26_11_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_sw = _entries_WIRE_26_11_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_sx = _entries_WIRE_26_11_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_sr = _entries_WIRE_26_11_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_pw = _entries_WIRE_26_11_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_px = _entries_WIRE_26_11_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_pr = _entries_WIRE_26_11_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_pal = _entries_WIRE_26_11_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_paa = _entries_WIRE_26_11_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_eff = _entries_WIRE_26_11_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_c = _entries_WIRE_26_11_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_11_fragmented_superpage = _entries_WIRE_26_11_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] entries_0_12_ppn = _entries_WIRE_26_12_ppn; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_u = _entries_WIRE_26_12_u; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_g = _entries_WIRE_26_12_g; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_ae = _entries_WIRE_26_12_ae; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_sw = _entries_WIRE_26_12_sw; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_sx = _entries_WIRE_26_12_sx; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_sr = _entries_WIRE_26_12_sr; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_pw = _entries_WIRE_26_12_pw; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_px = _entries_WIRE_26_12_px; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_pr = _entries_WIRE_26_12_pr; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_pal = _entries_WIRE_26_12_pal; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_paa = _entries_WIRE_26_12_paa; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_eff = _entries_WIRE_26_12_eff; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_c = _entries_WIRE_26_12_c; // @[tlb.scala:121:49, :213:38]
wire entries_0_12_fragmented_superpage = _entries_WIRE_26_12_fragmented_superpage; // @[tlb.scala:121:49, :213:38]
wire [19:0] _normal_entries_T_15; // @[tlb.scala:60:79]
wire _normal_entries_T_14; // @[tlb.scala:60:79]
wire _normal_entries_T_13; // @[tlb.scala:60:79]
wire _normal_entries_T_12; // @[tlb.scala:60:79]
wire _normal_entries_T_11; // @[tlb.scala:60:79]
wire _normal_entries_T_10; // @[tlb.scala:60:79]
wire _normal_entries_T_9; // @[tlb.scala:60:79]
wire _normal_entries_T_8; // @[tlb.scala:60:79]
wire _normal_entries_T_7; // @[tlb.scala:60:79]
wire _normal_entries_T_6; // @[tlb.scala:60:79]
wire _normal_entries_T_5; // @[tlb.scala:60:79]
wire _normal_entries_T_4; // @[tlb.scala:60:79]
wire _normal_entries_T_3; // @[tlb.scala:60:79]
wire _normal_entries_T_2; // @[tlb.scala:60:79]
wire _normal_entries_T_1; // @[tlb.scala:60:79]
assign _normal_entries_T_1 = _normal_entries_WIRE_1[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_fragmented_superpage = _normal_entries_T_1; // @[tlb.scala:60:79]
assign _normal_entries_T_2 = _normal_entries_WIRE_1[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_c = _normal_entries_T_2; // @[tlb.scala:60:79]
assign _normal_entries_T_3 = _normal_entries_WIRE_1[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_eff = _normal_entries_T_3; // @[tlb.scala:60:79]
assign _normal_entries_T_4 = _normal_entries_WIRE_1[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_paa = _normal_entries_T_4; // @[tlb.scala:60:79]
assign _normal_entries_T_5 = _normal_entries_WIRE_1[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_pal = _normal_entries_T_5; // @[tlb.scala:60:79]
assign _normal_entries_T_6 = _normal_entries_WIRE_1[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_pr = _normal_entries_T_6; // @[tlb.scala:60:79]
assign _normal_entries_T_7 = _normal_entries_WIRE_1[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_px = _normal_entries_T_7; // @[tlb.scala:60:79]
assign _normal_entries_T_8 = _normal_entries_WIRE_1[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_pw = _normal_entries_T_8; // @[tlb.scala:60:79]
assign _normal_entries_T_9 = _normal_entries_WIRE_1[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_sr = _normal_entries_T_9; // @[tlb.scala:60:79]
assign _normal_entries_T_10 = _normal_entries_WIRE_1[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_sx = _normal_entries_T_10; // @[tlb.scala:60:79]
assign _normal_entries_T_11 = _normal_entries_WIRE_1[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_sw = _normal_entries_T_11; // @[tlb.scala:60:79]
assign _normal_entries_T_12 = _normal_entries_WIRE_1[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_ae = _normal_entries_T_12; // @[tlb.scala:60:79]
assign _normal_entries_T_13 = _normal_entries_WIRE_1[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_g = _normal_entries_T_13; // @[tlb.scala:60:79]
assign _normal_entries_T_14 = _normal_entries_WIRE_1[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_u = _normal_entries_T_14; // @[tlb.scala:60:79]
assign _normal_entries_T_15 = _normal_entries_WIRE_1[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_ppn = _normal_entries_T_15; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_31; // @[tlb.scala:60:79]
wire _normal_entries_T_30; // @[tlb.scala:60:79]
wire _normal_entries_T_29; // @[tlb.scala:60:79]
wire _normal_entries_T_28; // @[tlb.scala:60:79]
wire _normal_entries_T_27; // @[tlb.scala:60:79]
wire _normal_entries_T_26; // @[tlb.scala:60:79]
wire _normal_entries_T_25; // @[tlb.scala:60:79]
wire _normal_entries_T_24; // @[tlb.scala:60:79]
wire _normal_entries_T_23; // @[tlb.scala:60:79]
wire _normal_entries_T_22; // @[tlb.scala:60:79]
wire _normal_entries_T_21; // @[tlb.scala:60:79]
wire _normal_entries_T_20; // @[tlb.scala:60:79]
wire _normal_entries_T_19; // @[tlb.scala:60:79]
wire _normal_entries_T_18; // @[tlb.scala:60:79]
wire _normal_entries_T_17; // @[tlb.scala:60:79]
assign _normal_entries_T_17 = _normal_entries_WIRE_3[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_fragmented_superpage = _normal_entries_T_17; // @[tlb.scala:60:79]
assign _normal_entries_T_18 = _normal_entries_WIRE_3[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_c = _normal_entries_T_18; // @[tlb.scala:60:79]
assign _normal_entries_T_19 = _normal_entries_WIRE_3[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_eff = _normal_entries_T_19; // @[tlb.scala:60:79]
assign _normal_entries_T_20 = _normal_entries_WIRE_3[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_paa = _normal_entries_T_20; // @[tlb.scala:60:79]
assign _normal_entries_T_21 = _normal_entries_WIRE_3[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_pal = _normal_entries_T_21; // @[tlb.scala:60:79]
assign _normal_entries_T_22 = _normal_entries_WIRE_3[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_pr = _normal_entries_T_22; // @[tlb.scala:60:79]
assign _normal_entries_T_23 = _normal_entries_WIRE_3[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_px = _normal_entries_T_23; // @[tlb.scala:60:79]
assign _normal_entries_T_24 = _normal_entries_WIRE_3[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_pw = _normal_entries_T_24; // @[tlb.scala:60:79]
assign _normal_entries_T_25 = _normal_entries_WIRE_3[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_sr = _normal_entries_T_25; // @[tlb.scala:60:79]
assign _normal_entries_T_26 = _normal_entries_WIRE_3[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_sx = _normal_entries_T_26; // @[tlb.scala:60:79]
assign _normal_entries_T_27 = _normal_entries_WIRE_3[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_sw = _normal_entries_T_27; // @[tlb.scala:60:79]
assign _normal_entries_T_28 = _normal_entries_WIRE_3[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_ae = _normal_entries_T_28; // @[tlb.scala:60:79]
assign _normal_entries_T_29 = _normal_entries_WIRE_3[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_g = _normal_entries_T_29; // @[tlb.scala:60:79]
assign _normal_entries_T_30 = _normal_entries_WIRE_3[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_2_u = _normal_entries_T_30; // @[tlb.scala:60:79]
assign _normal_entries_T_31 = _normal_entries_WIRE_3[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_2_ppn = _normal_entries_T_31; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_47; // @[tlb.scala:60:79]
wire _normal_entries_T_46; // @[tlb.scala:60:79]
wire _normal_entries_T_45; // @[tlb.scala:60:79]
wire _normal_entries_T_44; // @[tlb.scala:60:79]
wire _normal_entries_T_43; // @[tlb.scala:60:79]
wire _normal_entries_T_42; // @[tlb.scala:60:79]
wire _normal_entries_T_41; // @[tlb.scala:60:79]
wire _normal_entries_T_40; // @[tlb.scala:60:79]
wire _normal_entries_T_39; // @[tlb.scala:60:79]
wire _normal_entries_T_38; // @[tlb.scala:60:79]
wire _normal_entries_T_37; // @[tlb.scala:60:79]
wire _normal_entries_T_36; // @[tlb.scala:60:79]
wire _normal_entries_T_35; // @[tlb.scala:60:79]
wire _normal_entries_T_34; // @[tlb.scala:60:79]
wire _normal_entries_T_33; // @[tlb.scala:60:79]
assign _normal_entries_T_33 = _normal_entries_WIRE_5[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_fragmented_superpage = _normal_entries_T_33; // @[tlb.scala:60:79]
assign _normal_entries_T_34 = _normal_entries_WIRE_5[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_c = _normal_entries_T_34; // @[tlb.scala:60:79]
assign _normal_entries_T_35 = _normal_entries_WIRE_5[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_eff = _normal_entries_T_35; // @[tlb.scala:60:79]
assign _normal_entries_T_36 = _normal_entries_WIRE_5[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_paa = _normal_entries_T_36; // @[tlb.scala:60:79]
assign _normal_entries_T_37 = _normal_entries_WIRE_5[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_pal = _normal_entries_T_37; // @[tlb.scala:60:79]
assign _normal_entries_T_38 = _normal_entries_WIRE_5[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_pr = _normal_entries_T_38; // @[tlb.scala:60:79]
assign _normal_entries_T_39 = _normal_entries_WIRE_5[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_px = _normal_entries_T_39; // @[tlb.scala:60:79]
assign _normal_entries_T_40 = _normal_entries_WIRE_5[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_pw = _normal_entries_T_40; // @[tlb.scala:60:79]
assign _normal_entries_T_41 = _normal_entries_WIRE_5[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_sr = _normal_entries_T_41; // @[tlb.scala:60:79]
assign _normal_entries_T_42 = _normal_entries_WIRE_5[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_sx = _normal_entries_T_42; // @[tlb.scala:60:79]
assign _normal_entries_T_43 = _normal_entries_WIRE_5[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_sw = _normal_entries_T_43; // @[tlb.scala:60:79]
assign _normal_entries_T_44 = _normal_entries_WIRE_5[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_ae = _normal_entries_T_44; // @[tlb.scala:60:79]
assign _normal_entries_T_45 = _normal_entries_WIRE_5[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_g = _normal_entries_T_45; // @[tlb.scala:60:79]
assign _normal_entries_T_46 = _normal_entries_WIRE_5[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_4_u = _normal_entries_T_46; // @[tlb.scala:60:79]
assign _normal_entries_T_47 = _normal_entries_WIRE_5[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_4_ppn = _normal_entries_T_47; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_63; // @[tlb.scala:60:79]
wire _normal_entries_T_62; // @[tlb.scala:60:79]
wire _normal_entries_T_61; // @[tlb.scala:60:79]
wire _normal_entries_T_60; // @[tlb.scala:60:79]
wire _normal_entries_T_59; // @[tlb.scala:60:79]
wire _normal_entries_T_58; // @[tlb.scala:60:79]
wire _normal_entries_T_57; // @[tlb.scala:60:79]
wire _normal_entries_T_56; // @[tlb.scala:60:79]
wire _normal_entries_T_55; // @[tlb.scala:60:79]
wire _normal_entries_T_54; // @[tlb.scala:60:79]
wire _normal_entries_T_53; // @[tlb.scala:60:79]
wire _normal_entries_T_52; // @[tlb.scala:60:79]
wire _normal_entries_T_51; // @[tlb.scala:60:79]
wire _normal_entries_T_50; // @[tlb.scala:60:79]
wire _normal_entries_T_49; // @[tlb.scala:60:79]
assign _normal_entries_T_49 = _normal_entries_WIRE_7[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_fragmented_superpage = _normal_entries_T_49; // @[tlb.scala:60:79]
assign _normal_entries_T_50 = _normal_entries_WIRE_7[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_c = _normal_entries_T_50; // @[tlb.scala:60:79]
assign _normal_entries_T_51 = _normal_entries_WIRE_7[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_eff = _normal_entries_T_51; // @[tlb.scala:60:79]
assign _normal_entries_T_52 = _normal_entries_WIRE_7[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_paa = _normal_entries_T_52; // @[tlb.scala:60:79]
assign _normal_entries_T_53 = _normal_entries_WIRE_7[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_pal = _normal_entries_T_53; // @[tlb.scala:60:79]
assign _normal_entries_T_54 = _normal_entries_WIRE_7[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_pr = _normal_entries_T_54; // @[tlb.scala:60:79]
assign _normal_entries_T_55 = _normal_entries_WIRE_7[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_px = _normal_entries_T_55; // @[tlb.scala:60:79]
assign _normal_entries_T_56 = _normal_entries_WIRE_7[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_pw = _normal_entries_T_56; // @[tlb.scala:60:79]
assign _normal_entries_T_57 = _normal_entries_WIRE_7[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_sr = _normal_entries_T_57; // @[tlb.scala:60:79]
assign _normal_entries_T_58 = _normal_entries_WIRE_7[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_sx = _normal_entries_T_58; // @[tlb.scala:60:79]
assign _normal_entries_T_59 = _normal_entries_WIRE_7[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_sw = _normal_entries_T_59; // @[tlb.scala:60:79]
assign _normal_entries_T_60 = _normal_entries_WIRE_7[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_ae = _normal_entries_T_60; // @[tlb.scala:60:79]
assign _normal_entries_T_61 = _normal_entries_WIRE_7[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_g = _normal_entries_T_61; // @[tlb.scala:60:79]
assign _normal_entries_T_62 = _normal_entries_WIRE_7[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_6_u = _normal_entries_T_62; // @[tlb.scala:60:79]
assign _normal_entries_T_63 = _normal_entries_WIRE_7[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_6_ppn = _normal_entries_T_63; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_79; // @[tlb.scala:60:79]
wire _normal_entries_T_78; // @[tlb.scala:60:79]
wire _normal_entries_T_77; // @[tlb.scala:60:79]
wire _normal_entries_T_76; // @[tlb.scala:60:79]
wire _normal_entries_T_75; // @[tlb.scala:60:79]
wire _normal_entries_T_74; // @[tlb.scala:60:79]
wire _normal_entries_T_73; // @[tlb.scala:60:79]
wire _normal_entries_T_72; // @[tlb.scala:60:79]
wire _normal_entries_T_71; // @[tlb.scala:60:79]
wire _normal_entries_T_70; // @[tlb.scala:60:79]
wire _normal_entries_T_69; // @[tlb.scala:60:79]
wire _normal_entries_T_68; // @[tlb.scala:60:79]
wire _normal_entries_T_67; // @[tlb.scala:60:79]
wire _normal_entries_T_66; // @[tlb.scala:60:79]
wire _normal_entries_T_65; // @[tlb.scala:60:79]
assign _normal_entries_T_65 = _normal_entries_WIRE_9[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_fragmented_superpage = _normal_entries_T_65; // @[tlb.scala:60:79]
assign _normal_entries_T_66 = _normal_entries_WIRE_9[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_c = _normal_entries_T_66; // @[tlb.scala:60:79]
assign _normal_entries_T_67 = _normal_entries_WIRE_9[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_eff = _normal_entries_T_67; // @[tlb.scala:60:79]
assign _normal_entries_T_68 = _normal_entries_WIRE_9[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_paa = _normal_entries_T_68; // @[tlb.scala:60:79]
assign _normal_entries_T_69 = _normal_entries_WIRE_9[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_pal = _normal_entries_T_69; // @[tlb.scala:60:79]
assign _normal_entries_T_70 = _normal_entries_WIRE_9[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_pr = _normal_entries_T_70; // @[tlb.scala:60:79]
assign _normal_entries_T_71 = _normal_entries_WIRE_9[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_px = _normal_entries_T_71; // @[tlb.scala:60:79]
assign _normal_entries_T_72 = _normal_entries_WIRE_9[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_pw = _normal_entries_T_72; // @[tlb.scala:60:79]
assign _normal_entries_T_73 = _normal_entries_WIRE_9[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_sr = _normal_entries_T_73; // @[tlb.scala:60:79]
assign _normal_entries_T_74 = _normal_entries_WIRE_9[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_sx = _normal_entries_T_74; // @[tlb.scala:60:79]
assign _normal_entries_T_75 = _normal_entries_WIRE_9[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_sw = _normal_entries_T_75; // @[tlb.scala:60:79]
assign _normal_entries_T_76 = _normal_entries_WIRE_9[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_ae = _normal_entries_T_76; // @[tlb.scala:60:79]
assign _normal_entries_T_77 = _normal_entries_WIRE_9[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_g = _normal_entries_T_77; // @[tlb.scala:60:79]
assign _normal_entries_T_78 = _normal_entries_WIRE_9[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_8_u = _normal_entries_T_78; // @[tlb.scala:60:79]
assign _normal_entries_T_79 = _normal_entries_WIRE_9[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_8_ppn = _normal_entries_T_79; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_95; // @[tlb.scala:60:79]
wire _normal_entries_T_94; // @[tlb.scala:60:79]
wire _normal_entries_T_93; // @[tlb.scala:60:79]
wire _normal_entries_T_92; // @[tlb.scala:60:79]
wire _normal_entries_T_91; // @[tlb.scala:60:79]
wire _normal_entries_T_90; // @[tlb.scala:60:79]
wire _normal_entries_T_89; // @[tlb.scala:60:79]
wire _normal_entries_T_88; // @[tlb.scala:60:79]
wire _normal_entries_T_87; // @[tlb.scala:60:79]
wire _normal_entries_T_86; // @[tlb.scala:60:79]
wire _normal_entries_T_85; // @[tlb.scala:60:79]
wire _normal_entries_T_84; // @[tlb.scala:60:79]
wire _normal_entries_T_83; // @[tlb.scala:60:79]
wire _normal_entries_T_82; // @[tlb.scala:60:79]
wire _normal_entries_T_81; // @[tlb.scala:60:79]
assign _normal_entries_T_81 = _normal_entries_WIRE_11[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_fragmented_superpage = _normal_entries_T_81; // @[tlb.scala:60:79]
assign _normal_entries_T_82 = _normal_entries_WIRE_11[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_c = _normal_entries_T_82; // @[tlb.scala:60:79]
assign _normal_entries_T_83 = _normal_entries_WIRE_11[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_eff = _normal_entries_T_83; // @[tlb.scala:60:79]
assign _normal_entries_T_84 = _normal_entries_WIRE_11[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_paa = _normal_entries_T_84; // @[tlb.scala:60:79]
assign _normal_entries_T_85 = _normal_entries_WIRE_11[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_pal = _normal_entries_T_85; // @[tlb.scala:60:79]
assign _normal_entries_T_86 = _normal_entries_WIRE_11[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_pr = _normal_entries_T_86; // @[tlb.scala:60:79]
assign _normal_entries_T_87 = _normal_entries_WIRE_11[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_px = _normal_entries_T_87; // @[tlb.scala:60:79]
assign _normal_entries_T_88 = _normal_entries_WIRE_11[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_pw = _normal_entries_T_88; // @[tlb.scala:60:79]
assign _normal_entries_T_89 = _normal_entries_WIRE_11[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_sr = _normal_entries_T_89; // @[tlb.scala:60:79]
assign _normal_entries_T_90 = _normal_entries_WIRE_11[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_sx = _normal_entries_T_90; // @[tlb.scala:60:79]
assign _normal_entries_T_91 = _normal_entries_WIRE_11[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_sw = _normal_entries_T_91; // @[tlb.scala:60:79]
assign _normal_entries_T_92 = _normal_entries_WIRE_11[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_ae = _normal_entries_T_92; // @[tlb.scala:60:79]
assign _normal_entries_T_93 = _normal_entries_WIRE_11[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_g = _normal_entries_T_93; // @[tlb.scala:60:79]
assign _normal_entries_T_94 = _normal_entries_WIRE_11[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_10_u = _normal_entries_T_94; // @[tlb.scala:60:79]
assign _normal_entries_T_95 = _normal_entries_WIRE_11[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_10_ppn = _normal_entries_T_95; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_111; // @[tlb.scala:60:79]
wire _normal_entries_T_110; // @[tlb.scala:60:79]
wire _normal_entries_T_109; // @[tlb.scala:60:79]
wire _normal_entries_T_108; // @[tlb.scala:60:79]
wire _normal_entries_T_107; // @[tlb.scala:60:79]
wire _normal_entries_T_106; // @[tlb.scala:60:79]
wire _normal_entries_T_105; // @[tlb.scala:60:79]
wire _normal_entries_T_104; // @[tlb.scala:60:79]
wire _normal_entries_T_103; // @[tlb.scala:60:79]
wire _normal_entries_T_102; // @[tlb.scala:60:79]
wire _normal_entries_T_101; // @[tlb.scala:60:79]
wire _normal_entries_T_100; // @[tlb.scala:60:79]
wire _normal_entries_T_99; // @[tlb.scala:60:79]
wire _normal_entries_T_98; // @[tlb.scala:60:79]
wire _normal_entries_T_97; // @[tlb.scala:60:79]
assign _normal_entries_T_97 = _normal_entries_WIRE_13[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_fragmented_superpage = _normal_entries_T_97; // @[tlb.scala:60:79]
assign _normal_entries_T_98 = _normal_entries_WIRE_13[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_c = _normal_entries_T_98; // @[tlb.scala:60:79]
assign _normal_entries_T_99 = _normal_entries_WIRE_13[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_eff = _normal_entries_T_99; // @[tlb.scala:60:79]
assign _normal_entries_T_100 = _normal_entries_WIRE_13[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_paa = _normal_entries_T_100; // @[tlb.scala:60:79]
assign _normal_entries_T_101 = _normal_entries_WIRE_13[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_pal = _normal_entries_T_101; // @[tlb.scala:60:79]
assign _normal_entries_T_102 = _normal_entries_WIRE_13[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_pr = _normal_entries_T_102; // @[tlb.scala:60:79]
assign _normal_entries_T_103 = _normal_entries_WIRE_13[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_px = _normal_entries_T_103; // @[tlb.scala:60:79]
assign _normal_entries_T_104 = _normal_entries_WIRE_13[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_pw = _normal_entries_T_104; // @[tlb.scala:60:79]
assign _normal_entries_T_105 = _normal_entries_WIRE_13[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_sr = _normal_entries_T_105; // @[tlb.scala:60:79]
assign _normal_entries_T_106 = _normal_entries_WIRE_13[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_sx = _normal_entries_T_106; // @[tlb.scala:60:79]
assign _normal_entries_T_107 = _normal_entries_WIRE_13[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_sw = _normal_entries_T_107; // @[tlb.scala:60:79]
assign _normal_entries_T_108 = _normal_entries_WIRE_13[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_ae = _normal_entries_T_108; // @[tlb.scala:60:79]
assign _normal_entries_T_109 = _normal_entries_WIRE_13[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_g = _normal_entries_T_109; // @[tlb.scala:60:79]
assign _normal_entries_T_110 = _normal_entries_WIRE_13[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_12_u = _normal_entries_T_110; // @[tlb.scala:60:79]
assign _normal_entries_T_111 = _normal_entries_WIRE_13[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_12_ppn = _normal_entries_T_111; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_127; // @[tlb.scala:60:79]
wire _normal_entries_T_126; // @[tlb.scala:60:79]
wire _normal_entries_T_125; // @[tlb.scala:60:79]
wire _normal_entries_T_124; // @[tlb.scala:60:79]
wire _normal_entries_T_123; // @[tlb.scala:60:79]
wire _normal_entries_T_122; // @[tlb.scala:60:79]
wire _normal_entries_T_121; // @[tlb.scala:60:79]
wire _normal_entries_T_120; // @[tlb.scala:60:79]
wire _normal_entries_T_119; // @[tlb.scala:60:79]
wire _normal_entries_T_118; // @[tlb.scala:60:79]
wire _normal_entries_T_117; // @[tlb.scala:60:79]
wire _normal_entries_T_116; // @[tlb.scala:60:79]
wire _normal_entries_T_115; // @[tlb.scala:60:79]
wire _normal_entries_T_114; // @[tlb.scala:60:79]
wire _normal_entries_T_113; // @[tlb.scala:60:79]
assign _normal_entries_T_113 = _normal_entries_WIRE_15[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_fragmented_superpage = _normal_entries_T_113; // @[tlb.scala:60:79]
assign _normal_entries_T_114 = _normal_entries_WIRE_15[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_c = _normal_entries_T_114; // @[tlb.scala:60:79]
assign _normal_entries_T_115 = _normal_entries_WIRE_15[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_eff = _normal_entries_T_115; // @[tlb.scala:60:79]
assign _normal_entries_T_116 = _normal_entries_WIRE_15[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_paa = _normal_entries_T_116; // @[tlb.scala:60:79]
assign _normal_entries_T_117 = _normal_entries_WIRE_15[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_pal = _normal_entries_T_117; // @[tlb.scala:60:79]
assign _normal_entries_T_118 = _normal_entries_WIRE_15[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_pr = _normal_entries_T_118; // @[tlb.scala:60:79]
assign _normal_entries_T_119 = _normal_entries_WIRE_15[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_px = _normal_entries_T_119; // @[tlb.scala:60:79]
assign _normal_entries_T_120 = _normal_entries_WIRE_15[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_pw = _normal_entries_T_120; // @[tlb.scala:60:79]
assign _normal_entries_T_121 = _normal_entries_WIRE_15[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_sr = _normal_entries_T_121; // @[tlb.scala:60:79]
assign _normal_entries_T_122 = _normal_entries_WIRE_15[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_sx = _normal_entries_T_122; // @[tlb.scala:60:79]
assign _normal_entries_T_123 = _normal_entries_WIRE_15[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_sw = _normal_entries_T_123; // @[tlb.scala:60:79]
assign _normal_entries_T_124 = _normal_entries_WIRE_15[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_ae = _normal_entries_T_124; // @[tlb.scala:60:79]
assign _normal_entries_T_125 = _normal_entries_WIRE_15[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_g = _normal_entries_T_125; // @[tlb.scala:60:79]
assign _normal_entries_T_126 = _normal_entries_WIRE_15[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_14_u = _normal_entries_T_126; // @[tlb.scala:60:79]
assign _normal_entries_T_127 = _normal_entries_WIRE_15[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_14_ppn = _normal_entries_T_127; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_142; // @[tlb.scala:60:79]
wire _normal_entries_T_141; // @[tlb.scala:60:79]
wire _normal_entries_T_140; // @[tlb.scala:60:79]
wire _normal_entries_T_139; // @[tlb.scala:60:79]
wire _normal_entries_T_138; // @[tlb.scala:60:79]
wire _normal_entries_T_137; // @[tlb.scala:60:79]
wire _normal_entries_T_136; // @[tlb.scala:60:79]
wire _normal_entries_T_135; // @[tlb.scala:60:79]
wire _normal_entries_T_134; // @[tlb.scala:60:79]
wire _normal_entries_T_133; // @[tlb.scala:60:79]
wire _normal_entries_T_132; // @[tlb.scala:60:79]
wire _normal_entries_T_131; // @[tlb.scala:60:79]
wire _normal_entries_T_130; // @[tlb.scala:60:79]
wire _normal_entries_T_129; // @[tlb.scala:60:79]
wire _normal_entries_T_128; // @[tlb.scala:60:79]
assign _normal_entries_T_128 = _normal_entries_WIRE_17[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_fragmented_superpage = _normal_entries_T_128; // @[tlb.scala:60:79]
assign _normal_entries_T_129 = _normal_entries_WIRE_17[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_c = _normal_entries_T_129; // @[tlb.scala:60:79]
assign _normal_entries_T_130 = _normal_entries_WIRE_17[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_eff = _normal_entries_T_130; // @[tlb.scala:60:79]
assign _normal_entries_T_131 = _normal_entries_WIRE_17[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_paa = _normal_entries_T_131; // @[tlb.scala:60:79]
assign _normal_entries_T_132 = _normal_entries_WIRE_17[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_pal = _normal_entries_T_132; // @[tlb.scala:60:79]
assign _normal_entries_T_133 = _normal_entries_WIRE_17[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_pr = _normal_entries_T_133; // @[tlb.scala:60:79]
assign _normal_entries_T_134 = _normal_entries_WIRE_17[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_px = _normal_entries_T_134; // @[tlb.scala:60:79]
assign _normal_entries_T_135 = _normal_entries_WIRE_17[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_pw = _normal_entries_T_135; // @[tlb.scala:60:79]
assign _normal_entries_T_136 = _normal_entries_WIRE_17[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_sr = _normal_entries_T_136; // @[tlb.scala:60:79]
assign _normal_entries_T_137 = _normal_entries_WIRE_17[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_sx = _normal_entries_T_137; // @[tlb.scala:60:79]
assign _normal_entries_T_138 = _normal_entries_WIRE_17[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_sw = _normal_entries_T_138; // @[tlb.scala:60:79]
assign _normal_entries_T_139 = _normal_entries_WIRE_17[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_ae = _normal_entries_T_139; // @[tlb.scala:60:79]
assign _normal_entries_T_140 = _normal_entries_WIRE_17[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_g = _normal_entries_T_140; // @[tlb.scala:60:79]
assign _normal_entries_T_141 = _normal_entries_WIRE_17[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_16_u = _normal_entries_T_141; // @[tlb.scala:60:79]
assign _normal_entries_T_142 = _normal_entries_WIRE_17[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_16_ppn = _normal_entries_T_142; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_157; // @[tlb.scala:60:79]
wire _normal_entries_T_156; // @[tlb.scala:60:79]
wire _normal_entries_T_155; // @[tlb.scala:60:79]
wire _normal_entries_T_154; // @[tlb.scala:60:79]
wire _normal_entries_T_153; // @[tlb.scala:60:79]
wire _normal_entries_T_152; // @[tlb.scala:60:79]
wire _normal_entries_T_151; // @[tlb.scala:60:79]
wire _normal_entries_T_150; // @[tlb.scala:60:79]
wire _normal_entries_T_149; // @[tlb.scala:60:79]
wire _normal_entries_T_148; // @[tlb.scala:60:79]
wire _normal_entries_T_147; // @[tlb.scala:60:79]
wire _normal_entries_T_146; // @[tlb.scala:60:79]
wire _normal_entries_T_145; // @[tlb.scala:60:79]
wire _normal_entries_T_144; // @[tlb.scala:60:79]
wire _normal_entries_T_143; // @[tlb.scala:60:79]
assign _normal_entries_T_143 = _normal_entries_WIRE_19[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_fragmented_superpage = _normal_entries_T_143; // @[tlb.scala:60:79]
assign _normal_entries_T_144 = _normal_entries_WIRE_19[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_c = _normal_entries_T_144; // @[tlb.scala:60:79]
assign _normal_entries_T_145 = _normal_entries_WIRE_19[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_eff = _normal_entries_T_145; // @[tlb.scala:60:79]
assign _normal_entries_T_146 = _normal_entries_WIRE_19[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_paa = _normal_entries_T_146; // @[tlb.scala:60:79]
assign _normal_entries_T_147 = _normal_entries_WIRE_19[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_pal = _normal_entries_T_147; // @[tlb.scala:60:79]
assign _normal_entries_T_148 = _normal_entries_WIRE_19[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_pr = _normal_entries_T_148; // @[tlb.scala:60:79]
assign _normal_entries_T_149 = _normal_entries_WIRE_19[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_px = _normal_entries_T_149; // @[tlb.scala:60:79]
assign _normal_entries_T_150 = _normal_entries_WIRE_19[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_pw = _normal_entries_T_150; // @[tlb.scala:60:79]
assign _normal_entries_T_151 = _normal_entries_WIRE_19[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_sr = _normal_entries_T_151; // @[tlb.scala:60:79]
assign _normal_entries_T_152 = _normal_entries_WIRE_19[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_sx = _normal_entries_T_152; // @[tlb.scala:60:79]
assign _normal_entries_T_153 = _normal_entries_WIRE_19[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_sw = _normal_entries_T_153; // @[tlb.scala:60:79]
assign _normal_entries_T_154 = _normal_entries_WIRE_19[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_ae = _normal_entries_T_154; // @[tlb.scala:60:79]
assign _normal_entries_T_155 = _normal_entries_WIRE_19[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_g = _normal_entries_T_155; // @[tlb.scala:60:79]
assign _normal_entries_T_156 = _normal_entries_WIRE_19[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_18_u = _normal_entries_T_156; // @[tlb.scala:60:79]
assign _normal_entries_T_157 = _normal_entries_WIRE_19[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_18_ppn = _normal_entries_T_157; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_172; // @[tlb.scala:60:79]
wire _normal_entries_T_171; // @[tlb.scala:60:79]
wire _normal_entries_T_170; // @[tlb.scala:60:79]
wire _normal_entries_T_169; // @[tlb.scala:60:79]
wire _normal_entries_T_168; // @[tlb.scala:60:79]
wire _normal_entries_T_167; // @[tlb.scala:60:79]
wire _normal_entries_T_166; // @[tlb.scala:60:79]
wire _normal_entries_T_165; // @[tlb.scala:60:79]
wire _normal_entries_T_164; // @[tlb.scala:60:79]
wire _normal_entries_T_163; // @[tlb.scala:60:79]
wire _normal_entries_T_162; // @[tlb.scala:60:79]
wire _normal_entries_T_161; // @[tlb.scala:60:79]
wire _normal_entries_T_160; // @[tlb.scala:60:79]
wire _normal_entries_T_159; // @[tlb.scala:60:79]
wire _normal_entries_T_158; // @[tlb.scala:60:79]
assign _normal_entries_T_158 = _normal_entries_WIRE_21[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_fragmented_superpage = _normal_entries_T_158; // @[tlb.scala:60:79]
assign _normal_entries_T_159 = _normal_entries_WIRE_21[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_c = _normal_entries_T_159; // @[tlb.scala:60:79]
assign _normal_entries_T_160 = _normal_entries_WIRE_21[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_eff = _normal_entries_T_160; // @[tlb.scala:60:79]
assign _normal_entries_T_161 = _normal_entries_WIRE_21[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_paa = _normal_entries_T_161; // @[tlb.scala:60:79]
assign _normal_entries_T_162 = _normal_entries_WIRE_21[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_pal = _normal_entries_T_162; // @[tlb.scala:60:79]
assign _normal_entries_T_163 = _normal_entries_WIRE_21[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_pr = _normal_entries_T_163; // @[tlb.scala:60:79]
assign _normal_entries_T_164 = _normal_entries_WIRE_21[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_px = _normal_entries_T_164; // @[tlb.scala:60:79]
assign _normal_entries_T_165 = _normal_entries_WIRE_21[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_pw = _normal_entries_T_165; // @[tlb.scala:60:79]
assign _normal_entries_T_166 = _normal_entries_WIRE_21[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_sr = _normal_entries_T_166; // @[tlb.scala:60:79]
assign _normal_entries_T_167 = _normal_entries_WIRE_21[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_sx = _normal_entries_T_167; // @[tlb.scala:60:79]
assign _normal_entries_T_168 = _normal_entries_WIRE_21[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_sw = _normal_entries_T_168; // @[tlb.scala:60:79]
assign _normal_entries_T_169 = _normal_entries_WIRE_21[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_ae = _normal_entries_T_169; // @[tlb.scala:60:79]
assign _normal_entries_T_170 = _normal_entries_WIRE_21[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_g = _normal_entries_T_170; // @[tlb.scala:60:79]
assign _normal_entries_T_171 = _normal_entries_WIRE_21[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_20_u = _normal_entries_T_171; // @[tlb.scala:60:79]
assign _normal_entries_T_172 = _normal_entries_WIRE_21[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_20_ppn = _normal_entries_T_172; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_T_187; // @[tlb.scala:60:79]
wire _normal_entries_T_186; // @[tlb.scala:60:79]
wire _normal_entries_T_185; // @[tlb.scala:60:79]
wire _normal_entries_T_184; // @[tlb.scala:60:79]
wire _normal_entries_T_183; // @[tlb.scala:60:79]
wire _normal_entries_T_182; // @[tlb.scala:60:79]
wire _normal_entries_T_181; // @[tlb.scala:60:79]
wire _normal_entries_T_180; // @[tlb.scala:60:79]
wire _normal_entries_T_179; // @[tlb.scala:60:79]
wire _normal_entries_T_178; // @[tlb.scala:60:79]
wire _normal_entries_T_177; // @[tlb.scala:60:79]
wire _normal_entries_T_176; // @[tlb.scala:60:79]
wire _normal_entries_T_175; // @[tlb.scala:60:79]
wire _normal_entries_T_174; // @[tlb.scala:60:79]
wire _normal_entries_T_173; // @[tlb.scala:60:79]
assign _normal_entries_T_173 = _normal_entries_WIRE_23[0]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_fragmented_superpage = _normal_entries_T_173; // @[tlb.scala:60:79]
assign _normal_entries_T_174 = _normal_entries_WIRE_23[1]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_c = _normal_entries_T_174; // @[tlb.scala:60:79]
assign _normal_entries_T_175 = _normal_entries_WIRE_23[2]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_eff = _normal_entries_T_175; // @[tlb.scala:60:79]
assign _normal_entries_T_176 = _normal_entries_WIRE_23[3]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_paa = _normal_entries_T_176; // @[tlb.scala:60:79]
assign _normal_entries_T_177 = _normal_entries_WIRE_23[4]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_pal = _normal_entries_T_177; // @[tlb.scala:60:79]
assign _normal_entries_T_178 = _normal_entries_WIRE_23[5]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_pr = _normal_entries_T_178; // @[tlb.scala:60:79]
assign _normal_entries_T_179 = _normal_entries_WIRE_23[6]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_px = _normal_entries_T_179; // @[tlb.scala:60:79]
assign _normal_entries_T_180 = _normal_entries_WIRE_23[7]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_pw = _normal_entries_T_180; // @[tlb.scala:60:79]
assign _normal_entries_T_181 = _normal_entries_WIRE_23[8]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_sr = _normal_entries_T_181; // @[tlb.scala:60:79]
assign _normal_entries_T_182 = _normal_entries_WIRE_23[9]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_sx = _normal_entries_T_182; // @[tlb.scala:60:79]
assign _normal_entries_T_183 = _normal_entries_WIRE_23[10]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_sw = _normal_entries_T_183; // @[tlb.scala:60:79]
assign _normal_entries_T_184 = _normal_entries_WIRE_23[11]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_ae = _normal_entries_T_184; // @[tlb.scala:60:79]
assign _normal_entries_T_185 = _normal_entries_WIRE_23[12]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_g = _normal_entries_T_185; // @[tlb.scala:60:79]
assign _normal_entries_T_186 = _normal_entries_WIRE_23[13]; // @[tlb.scala:60:79]
wire _normal_entries_WIRE_22_u = _normal_entries_T_186; // @[tlb.scala:60:79]
assign _normal_entries_T_187 = _normal_entries_WIRE_23[33:14]; // @[tlb.scala:60:79]
wire [19:0] _normal_entries_WIRE_22_ppn = _normal_entries_T_187; // @[tlb.scala:60:79]
wire [19:0] normal_entries_0_0_ppn = _normal_entries_WIRE_24_0_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_u = _normal_entries_WIRE_24_0_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_g = _normal_entries_WIRE_24_0_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_ae = _normal_entries_WIRE_24_0_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_sw = _normal_entries_WIRE_24_0_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_sx = _normal_entries_WIRE_24_0_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_sr = _normal_entries_WIRE_24_0_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_pw = _normal_entries_WIRE_24_0_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_px = _normal_entries_WIRE_24_0_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_pr = _normal_entries_WIRE_24_0_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_pal = _normal_entries_WIRE_24_0_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_paa = _normal_entries_WIRE_24_0_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_eff = _normal_entries_WIRE_24_0_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_c = _normal_entries_WIRE_24_0_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_0_fragmented_superpage = _normal_entries_WIRE_24_0_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_1_ppn = _normal_entries_WIRE_24_1_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_u = _normal_entries_WIRE_24_1_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_g = _normal_entries_WIRE_24_1_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_ae = _normal_entries_WIRE_24_1_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_sw = _normal_entries_WIRE_24_1_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_sx = _normal_entries_WIRE_24_1_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_sr = _normal_entries_WIRE_24_1_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_pw = _normal_entries_WIRE_24_1_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_px = _normal_entries_WIRE_24_1_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_pr = _normal_entries_WIRE_24_1_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_pal = _normal_entries_WIRE_24_1_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_paa = _normal_entries_WIRE_24_1_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_eff = _normal_entries_WIRE_24_1_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_c = _normal_entries_WIRE_24_1_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_1_fragmented_superpage = _normal_entries_WIRE_24_1_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_2_ppn = _normal_entries_WIRE_24_2_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_u = _normal_entries_WIRE_24_2_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_g = _normal_entries_WIRE_24_2_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_ae = _normal_entries_WIRE_24_2_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_sw = _normal_entries_WIRE_24_2_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_sx = _normal_entries_WIRE_24_2_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_sr = _normal_entries_WIRE_24_2_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_pw = _normal_entries_WIRE_24_2_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_px = _normal_entries_WIRE_24_2_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_pr = _normal_entries_WIRE_24_2_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_pal = _normal_entries_WIRE_24_2_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_paa = _normal_entries_WIRE_24_2_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_eff = _normal_entries_WIRE_24_2_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_c = _normal_entries_WIRE_24_2_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_2_fragmented_superpage = _normal_entries_WIRE_24_2_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_3_ppn = _normal_entries_WIRE_24_3_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_u = _normal_entries_WIRE_24_3_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_g = _normal_entries_WIRE_24_3_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_ae = _normal_entries_WIRE_24_3_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_sw = _normal_entries_WIRE_24_3_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_sx = _normal_entries_WIRE_24_3_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_sr = _normal_entries_WIRE_24_3_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_pw = _normal_entries_WIRE_24_3_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_px = _normal_entries_WIRE_24_3_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_pr = _normal_entries_WIRE_24_3_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_pal = _normal_entries_WIRE_24_3_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_paa = _normal_entries_WIRE_24_3_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_eff = _normal_entries_WIRE_24_3_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_c = _normal_entries_WIRE_24_3_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_3_fragmented_superpage = _normal_entries_WIRE_24_3_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_4_ppn = _normal_entries_WIRE_24_4_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_u = _normal_entries_WIRE_24_4_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_g = _normal_entries_WIRE_24_4_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_ae = _normal_entries_WIRE_24_4_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_sw = _normal_entries_WIRE_24_4_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_sx = _normal_entries_WIRE_24_4_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_sr = _normal_entries_WIRE_24_4_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_pw = _normal_entries_WIRE_24_4_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_px = _normal_entries_WIRE_24_4_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_pr = _normal_entries_WIRE_24_4_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_pal = _normal_entries_WIRE_24_4_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_paa = _normal_entries_WIRE_24_4_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_eff = _normal_entries_WIRE_24_4_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_c = _normal_entries_WIRE_24_4_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_4_fragmented_superpage = _normal_entries_WIRE_24_4_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_5_ppn = _normal_entries_WIRE_24_5_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_u = _normal_entries_WIRE_24_5_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_g = _normal_entries_WIRE_24_5_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_ae = _normal_entries_WIRE_24_5_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_sw = _normal_entries_WIRE_24_5_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_sx = _normal_entries_WIRE_24_5_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_sr = _normal_entries_WIRE_24_5_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_pw = _normal_entries_WIRE_24_5_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_px = _normal_entries_WIRE_24_5_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_pr = _normal_entries_WIRE_24_5_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_pal = _normal_entries_WIRE_24_5_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_paa = _normal_entries_WIRE_24_5_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_eff = _normal_entries_WIRE_24_5_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_c = _normal_entries_WIRE_24_5_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_5_fragmented_superpage = _normal_entries_WIRE_24_5_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_6_ppn = _normal_entries_WIRE_24_6_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_u = _normal_entries_WIRE_24_6_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_g = _normal_entries_WIRE_24_6_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_ae = _normal_entries_WIRE_24_6_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_sw = _normal_entries_WIRE_24_6_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_sx = _normal_entries_WIRE_24_6_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_sr = _normal_entries_WIRE_24_6_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_pw = _normal_entries_WIRE_24_6_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_px = _normal_entries_WIRE_24_6_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_pr = _normal_entries_WIRE_24_6_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_pal = _normal_entries_WIRE_24_6_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_paa = _normal_entries_WIRE_24_6_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_eff = _normal_entries_WIRE_24_6_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_c = _normal_entries_WIRE_24_6_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_6_fragmented_superpage = _normal_entries_WIRE_24_6_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_7_ppn = _normal_entries_WIRE_24_7_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_u = _normal_entries_WIRE_24_7_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_g = _normal_entries_WIRE_24_7_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_ae = _normal_entries_WIRE_24_7_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_sw = _normal_entries_WIRE_24_7_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_sx = _normal_entries_WIRE_24_7_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_sr = _normal_entries_WIRE_24_7_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_pw = _normal_entries_WIRE_24_7_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_px = _normal_entries_WIRE_24_7_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_pr = _normal_entries_WIRE_24_7_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_pal = _normal_entries_WIRE_24_7_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_paa = _normal_entries_WIRE_24_7_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_eff = _normal_entries_WIRE_24_7_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_c = _normal_entries_WIRE_24_7_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_7_fragmented_superpage = _normal_entries_WIRE_24_7_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_8_ppn = _normal_entries_WIRE_24_8_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_u = _normal_entries_WIRE_24_8_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_g = _normal_entries_WIRE_24_8_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_ae = _normal_entries_WIRE_24_8_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_sw = _normal_entries_WIRE_24_8_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_sx = _normal_entries_WIRE_24_8_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_sr = _normal_entries_WIRE_24_8_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_pw = _normal_entries_WIRE_24_8_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_px = _normal_entries_WIRE_24_8_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_pr = _normal_entries_WIRE_24_8_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_pal = _normal_entries_WIRE_24_8_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_paa = _normal_entries_WIRE_24_8_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_eff = _normal_entries_WIRE_24_8_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_c = _normal_entries_WIRE_24_8_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_8_fragmented_superpage = _normal_entries_WIRE_24_8_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_9_ppn = _normal_entries_WIRE_24_9_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_u = _normal_entries_WIRE_24_9_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_g = _normal_entries_WIRE_24_9_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_ae = _normal_entries_WIRE_24_9_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_sw = _normal_entries_WIRE_24_9_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_sx = _normal_entries_WIRE_24_9_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_sr = _normal_entries_WIRE_24_9_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_pw = _normal_entries_WIRE_24_9_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_px = _normal_entries_WIRE_24_9_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_pr = _normal_entries_WIRE_24_9_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_pal = _normal_entries_WIRE_24_9_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_paa = _normal_entries_WIRE_24_9_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_eff = _normal_entries_WIRE_24_9_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_c = _normal_entries_WIRE_24_9_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_9_fragmented_superpage = _normal_entries_WIRE_24_9_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_10_ppn = _normal_entries_WIRE_24_10_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_u = _normal_entries_WIRE_24_10_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_g = _normal_entries_WIRE_24_10_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_ae = _normal_entries_WIRE_24_10_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_sw = _normal_entries_WIRE_24_10_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_sx = _normal_entries_WIRE_24_10_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_sr = _normal_entries_WIRE_24_10_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_pw = _normal_entries_WIRE_24_10_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_px = _normal_entries_WIRE_24_10_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_pr = _normal_entries_WIRE_24_10_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_pal = _normal_entries_WIRE_24_10_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_paa = _normal_entries_WIRE_24_10_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_eff = _normal_entries_WIRE_24_10_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_c = _normal_entries_WIRE_24_10_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_10_fragmented_superpage = _normal_entries_WIRE_24_10_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [19:0] normal_entries_0_11_ppn = _normal_entries_WIRE_24_11_ppn; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_u = _normal_entries_WIRE_24_11_u; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_g = _normal_entries_WIRE_24_11_g; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_ae = _normal_entries_WIRE_24_11_ae; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_sw = _normal_entries_WIRE_24_11_sw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_sx = _normal_entries_WIRE_24_11_sx; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_sr = _normal_entries_WIRE_24_11_sr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_pw = _normal_entries_WIRE_24_11_pw; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_px = _normal_entries_WIRE_24_11_px; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_pr = _normal_entries_WIRE_24_11_pr; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_pal = _normal_entries_WIRE_24_11_pal; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_paa = _normal_entries_WIRE_24_11_paa; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_eff = _normal_entries_WIRE_24_11_eff; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_c = _normal_entries_WIRE_24_11_c; // @[tlb.scala:121:49, :214:45]
wire normal_entries_0_11_fragmented_superpage = _normal_entries_WIRE_24_11_fragmented_superpage; // @[tlb.scala:121:49, :214:45]
wire [1:0] ptw_ae_array_lo_lo_hi = {entries_0_2_ae, entries_0_1_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, entries_0_0_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_lo_hi_hi = {entries_0_5_ae, entries_0_4_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, entries_0_3_ae}; // @[package.scala:45:27]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {entries_0_8_ae, entries_0_7_ae}; // @[package.scala:45:27]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, entries_0_6_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_hi_lo = {entries_0_10_ae, entries_0_9_ae}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_hi_hi = {entries_0_12_ae, entries_0_11_ae}; // @[package.scala:45:27]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] _ptw_ae_array_T_1 = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array_0 = _ptw_ae_array_T_1; // @[tlb.scala:121:49, :216:39]
wire [1:0] _GEN_9 = {entries_0_2_u, entries_0_1_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27]
wire [1:0] _GEN_10 = {entries_0_5_u, entries_0_4_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_11 = {entries_0_8_u, entries_0_7_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {entries_0_10_u, entries_0_9_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_12; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] _GEN_13 = {entries_0_12_u, entries_0_11_u}; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_13; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_2; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_7 = _priv_rw_ok_T_3; // @[tlb.scala:217:{39,103}]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] priv_rw_ok_0 = _priv_rw_ok_T_7; // @[tlb.scala:121:49, :217:103]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, entries_0_0_u}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, entries_0_3_u}; // @[package.scala:45:27]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, entries_0_6_u}; // @[package.scala:45:27]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_3 = _priv_x_ok_T_2; // @[package.scala:45:27]
wire [12:0] priv_x_ok_0 = _priv_x_ok_T_3; // @[tlb.scala:121:49, :218:39]
wire [1:0] r_array_lo_lo_hi = {entries_0_2_sr, entries_0_1_sr}; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, entries_0_0_sr}; // @[package.scala:45:27]
wire [1:0] r_array_lo_hi_hi = {entries_0_5_sr, entries_0_4_sr}; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, entries_0_3_sr}; // @[package.scala:45:27]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {entries_0_8_sr, entries_0_7_sr}; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, entries_0_6_sr}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_lo = {entries_0_10_sr, entries_0_9_sr}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_hi = {entries_0_12_sr, entries_0_11_sr}; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_14 = {entries_0_2_sx, entries_0_1_sx}; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_14; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, entries_0_0_sx}; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {entries_0_5_sx, entries_0_4_sx}; // @[package.scala:45:27]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_15; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, entries_0_3_sx}; // @[package.scala:45:27]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_16 = {entries_0_8_sx, entries_0_7_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_16; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, entries_0_6_sx}; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {entries_0_10_sx, entries_0_9_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_17; // @[package.scala:45:27]
wire [1:0] _GEN_18 = {entries_0_12_sx, entries_0_11_sx}; // @[package.scala:45:27]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_18; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok_0 & _r_array_T_3; // @[tlb.scala:121:49, :219:{62,93}]
wire [13:0] _r_array_T_5 = {1'h1, _r_array_T_4}; // @[tlb.scala:219:{39,62}]
wire [13:0] r_array_0 = _r_array_T_5; // @[tlb.scala:121:49, :219:39]
wire [1:0] w_array_lo_lo_hi = {entries_0_2_sw, entries_0_1_sw}; // @[package.scala:45:27]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, entries_0_0_sw}; // @[package.scala:45:27]
wire [1:0] w_array_lo_hi_hi = {entries_0_5_sw, entries_0_4_sw}; // @[package.scala:45:27]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, entries_0_3_sw}; // @[package.scala:45:27]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {entries_0_8_sw, entries_0_7_sw}; // @[package.scala:45:27]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, entries_0_6_sw}; // @[package.scala:45:27]
wire [1:0] w_array_hi_hi_lo = {entries_0_10_sw, entries_0_9_sw}; // @[package.scala:45:27]
wire [1:0] w_array_hi_hi_hi = {entries_0_12_sw, entries_0_11_sw}; // @[package.scala:45:27]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok_0 & _w_array_T; // @[package.scala:45:27]
wire [13:0] _w_array_T_2 = {1'h1, _w_array_T_1}; // @[tlb.scala:220:{39,62}]
wire [13:0] w_array_0 = _w_array_T_2; // @[tlb.scala:121:49, :220:39]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, entries_0_0_sx}; // @[package.scala:45:27]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, entries_0_3_sx}; // @[package.scala:45:27]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, entries_0_6_sx}; // @[package.scala:45:27]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok_0 & _x_array_T; // @[package.scala:45:27]
wire [13:0] _x_array_T_2 = {1'h1, _x_array_T_1}; // @[tlb.scala:221:{39,62}]
wire [13:0] x_array_0 = _x_array_T_2; // @[tlb.scala:121:49, :221:39]
wire [1:0] _pr_array_T = {2{prot_r_0}}; // @[tlb.scala:121:49, :222:44]
wire [1:0] pr_array_lo_lo_hi = {normal_entries_0_2_pr, normal_entries_0_1_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, normal_entries_0_0_pr}; // @[package.scala:45:27]
wire [1:0] pr_array_lo_hi_hi = {normal_entries_0_5_pr, normal_entries_0_4_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, normal_entries_0_3_pr}; // @[package.scala:45:27]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {normal_entries_0_8_pr, normal_entries_0_7_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, normal_entries_0_6_pr}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_hi_hi = {normal_entries_0_11_pr, normal_entries_0_10_pr}; // @[package.scala:45:27]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, normal_entries_0_9_pr}; // @[package.scala:45:27]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116]
wire [13:0] _pr_array_T_4 = _pr_array_T_2 & _pr_array_T_3; // @[tlb.scala:222:{39,114,116}]
wire [13:0] pr_array_0 = _pr_array_T_4; // @[tlb.scala:121:49, :222:114]
wire [1:0] _pw_array_T = {2{prot_w_0}}; // @[tlb.scala:121:49, :223:44]
wire [1:0] pw_array_lo_lo_hi = {normal_entries_0_2_pw, normal_entries_0_1_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, normal_entries_0_0_pw}; // @[package.scala:45:27]
wire [1:0] pw_array_lo_hi_hi = {normal_entries_0_5_pw, normal_entries_0_4_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, normal_entries_0_3_pw}; // @[package.scala:45:27]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {normal_entries_0_8_pw, normal_entries_0_7_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, normal_entries_0_6_pw}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_hi_hi = {normal_entries_0_11_pw, normal_entries_0_10_pw}; // @[package.scala:45:27]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, normal_entries_0_9_pw}; // @[package.scala:45:27]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116, :223:116]
wire [13:0] _pw_array_T_4 = _pw_array_T_2 & _pw_array_T_3; // @[tlb.scala:223:{39,114,116}]
wire [13:0] pw_array_0 = _pw_array_T_4; // @[tlb.scala:121:49, :223:114]
wire [1:0] _px_array_T = {2{prot_x_0}}; // @[tlb.scala:121:49, :224:44]
wire [1:0] px_array_lo_lo_hi = {normal_entries_0_2_px, normal_entries_0_1_px}; // @[package.scala:45:27]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, normal_entries_0_0_px}; // @[package.scala:45:27]
wire [1:0] px_array_lo_hi_hi = {normal_entries_0_5_px, normal_entries_0_4_px}; // @[package.scala:45:27]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, normal_entries_0_3_px}; // @[package.scala:45:27]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {normal_entries_0_8_px, normal_entries_0_7_px}; // @[package.scala:45:27]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, normal_entries_0_6_px}; // @[package.scala:45:27]
wire [1:0] px_array_hi_hi_hi = {normal_entries_0_11_px, normal_entries_0_10_px}; // @[package.scala:45:27]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, normal_entries_0_9_px}; // @[package.scala:45:27]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_3 = ~ptw_ae_array_0; // @[tlb.scala:121:49, :222:116, :224:116]
wire [13:0] _px_array_T_4 = _px_array_T_2 & _px_array_T_3; // @[tlb.scala:224:{39,114,116}]
wire [13:0] px_array_0 = _px_array_T_4; // @[tlb.scala:121:49, :224:114]
wire [1:0] _eff_array_T = {2{prot_eff_0}}; // @[tlb.scala:121:49, :225:44]
wire [1:0] eff_array_lo_lo_hi = {normal_entries_0_2_eff, normal_entries_0_1_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, normal_entries_0_0_eff}; // @[package.scala:45:27]
wire [1:0] eff_array_lo_hi_hi = {normal_entries_0_5_eff, normal_entries_0_4_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, normal_entries_0_3_eff}; // @[package.scala:45:27]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {normal_entries_0_8_eff, normal_entries_0_7_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, normal_entries_0_6_eff}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_hi_hi = {normal_entries_0_11_eff, normal_entries_0_10_eff}; // @[package.scala:45:27]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, normal_entries_0_9_eff}; // @[package.scala:45:27]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] _eff_array_T_2 = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [13:0] eff_array_0 = _eff_array_T_2; // @[tlb.scala:121:49, :225:39]
wire [1:0] _c_array_T = {2{cacheable_0}}; // @[tlb.scala:121:49, :226:44]
wire [1:0] _GEN_19 = {normal_entries_0_2_c, normal_entries_0_1_c}; // @[package.scala:45:27]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_19; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {normal_entries_0_5_c, normal_entries_0_4_c}; // @[package.scala:45:27]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_20; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_21 = {normal_entries_0_8_c, normal_entries_0_7_c}; // @[package.scala:45:27]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_21; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {normal_entries_0_11_c, normal_entries_0_10_c}; // @[package.scala:45:27]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_22; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] _c_array_T_2 = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] c_array_0 = _c_array_T_2; // @[tlb.scala:121:49, :226:39]
wire [13:0] _paa_array_if_cached_T = c_array_0; // @[tlb.scala:121:49, :229:61]
wire [13:0] _pal_array_if_cached_T = c_array_0; // @[tlb.scala:121:49, :230:61]
wire [13:0] _lrscAllowed_T = c_array_0; // @[tlb.scala:121:49, :252:38]
wire [1:0] _paa_array_T = {2{prot_aa_0}}; // @[tlb.scala:121:49, :227:44]
wire [1:0] paa_array_lo_lo_hi = {normal_entries_0_2_paa, normal_entries_0_1_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, normal_entries_0_0_paa}; // @[package.scala:45:27]
wire [1:0] paa_array_lo_hi_hi = {normal_entries_0_5_paa, normal_entries_0_4_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, normal_entries_0_3_paa}; // @[package.scala:45:27]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {normal_entries_0_8_paa, normal_entries_0_7_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, normal_entries_0_6_paa}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_hi_hi = {normal_entries_0_11_paa, normal_entries_0_10_paa}; // @[package.scala:45:27]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, normal_entries_0_9_paa}; // @[package.scala:45:27]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] _paa_array_T_2 = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [13:0] paa_array_0 = _paa_array_T_2; // @[tlb.scala:121:49, :227:39]
wire [1:0] _pal_array_T = {2{prot_al_0}}; // @[tlb.scala:121:49, :228:44]
wire [1:0] pal_array_lo_lo_hi = {normal_entries_0_2_pal, normal_entries_0_1_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, normal_entries_0_0_pal}; // @[package.scala:45:27]
wire [1:0] pal_array_lo_hi_hi = {normal_entries_0_5_pal, normal_entries_0_4_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, normal_entries_0_3_pal}; // @[package.scala:45:27]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {normal_entries_0_8_pal, normal_entries_0_7_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, normal_entries_0_6_pal}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_hi_hi = {normal_entries_0_11_pal, normal_entries_0_10_pal}; // @[package.scala:45:27]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, normal_entries_0_9_pal}; // @[package.scala:45:27]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] _pal_array_T_2 = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pal_array_0 = _pal_array_T_2; // @[tlb.scala:121:49, :228:39]
wire [13:0] _paa_array_if_cached_T_1 = paa_array_0 | _paa_array_if_cached_T; // @[tlb.scala:121:49, :229:{56,61}]
wire [13:0] paa_array_if_cached_0 = _paa_array_if_cached_T_1; // @[tlb.scala:121:49, :229:56]
wire [13:0] _pal_array_if_cached_T_1 = pal_array_0 | _pal_array_if_cached_T; // @[tlb.scala:121:49, :230:{56,61}]
wire [13:0] pal_array_if_cached_0 = _pal_array_if_cached_T_1; // @[tlb.scala:121:49, :230:56]
wire _prefetchable_array_T = cacheable_0 & homogeneous_0; // @[tlb.scala:121:49, :231:61]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[tlb.scala:231:{61,80}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, normal_entries_0_0_c}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, normal_entries_0_3_c}; // @[package.scala:45:27]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, normal_entries_0_6_c}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, normal_entries_0_9_c}; // @[package.scala:45:27]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] _prefetchable_array_T_3 = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [13:0] prefetchable_array_0 = _prefetchable_array_T_3; // @[tlb.scala:121:49, :231:46]
wire [3:0] _misaligned_T = 4'h1 << io_req_0_bits_size_0; // @[OneHot.scala:58:35]
wire [4:0] _misaligned_T_1 = {1'h0, _misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] _misaligned_T_2 = _misaligned_T_1[3:0]; // @[tlb.scala:233:89]
wire [33:0] _misaligned_T_3 = {30'h0, io_req_0_bits_vaddr_0[3:0] & _misaligned_T_2}; // @[tlb.scala:17:7, :19:14, :233:{56,89}]
wire _misaligned_T_4 = |_misaligned_T_3; // @[tlb.scala:233:{56,97}]
wire misaligned_0 = _misaligned_T_4; // @[tlb.scala:121:49, :233:97]
wire _GEN_23 = io_req_0_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _cmd_lrsc_T; // @[package.scala:16:47]
assign _cmd_lrsc_T = _GEN_23; // @[package.scala:16:47]
wire _cmd_read_T_2; // @[package.scala:16:47]
assign _cmd_read_T_2 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_0_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _cmd_lrsc_T_1; // @[package.scala:16:47]
assign _cmd_lrsc_T_1 = _GEN_24; // @[package.scala:16:47]
wire _cmd_read_T_3; // @[package.scala:16:47]
assign _cmd_read_T_3 = _GEN_24; // @[package.scala:16:47]
wire _cmd_write_T_3; // @[Consts.scala:90:66]
assign _cmd_write_T_3 = _GEN_24; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_lrsc_T_3 = _cmd_lrsc_T_2; // @[package.scala:81:59]
wire cmd_lrsc_0 = _cmd_lrsc_T_3; // @[tlb.scala:121:49, :244:57]
wire _GEN_25 = io_req_0_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _cmd_amo_logical_T; // @[package.scala:16:47]
assign _cmd_amo_logical_T = _GEN_25; // @[package.scala:16:47]
wire _cmd_read_T_7; // @[package.scala:16:47]
assign _cmd_read_T_7 = _GEN_25; // @[package.scala:16:47]
wire _cmd_write_T_5; // @[package.scala:16:47]
assign _cmd_write_T_5 = _GEN_25; // @[package.scala:16:47]
wire _GEN_26 = io_req_0_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1; // @[package.scala:16:47]
assign _cmd_amo_logical_T_1 = _GEN_26; // @[package.scala:16:47]
wire _cmd_read_T_8; // @[package.scala:16:47]
assign _cmd_read_T_8 = _GEN_26; // @[package.scala:16:47]
wire _cmd_write_T_6; // @[package.scala:16:47]
assign _cmd_write_T_6 = _GEN_26; // @[package.scala:16:47]
wire _GEN_27 = io_req_0_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2; // @[package.scala:16:47]
assign _cmd_amo_logical_T_2 = _GEN_27; // @[package.scala:16:47]
wire _cmd_read_T_9; // @[package.scala:16:47]
assign _cmd_read_T_9 = _GEN_27; // @[package.scala:16:47]
wire _cmd_write_T_7; // @[package.scala:16:47]
assign _cmd_write_T_7 = _GEN_27; // @[package.scala:16:47]
wire _GEN_28 = io_req_0_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3; // @[package.scala:16:47]
assign _cmd_amo_logical_T_3 = _GEN_28; // @[package.scala:16:47]
wire _cmd_read_T_10; // @[package.scala:16:47]
assign _cmd_read_T_10 = _GEN_28; // @[package.scala:16:47]
wire _cmd_write_T_8; // @[package.scala:16:47]
assign _cmd_write_T_8 = _GEN_28; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = _cmd_amo_logical_T | _cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_5 = _cmd_amo_logical_T_4 | _cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_6 = _cmd_amo_logical_T_5 | _cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_logical_T_7 = _cmd_amo_logical_T_6; // @[package.scala:81:59]
wire cmd_amo_logical_0 = _cmd_amo_logical_T_7; // @[tlb.scala:121:49, :245:57]
wire _GEN_29 = io_req_0_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T = _GEN_29; // @[package.scala:16:47]
wire _cmd_read_T_14; // @[package.scala:16:47]
assign _cmd_read_T_14 = _GEN_29; // @[package.scala:16:47]
wire _cmd_write_T_12; // @[package.scala:16:47]
assign _cmd_write_T_12 = _GEN_29; // @[package.scala:16:47]
wire _GEN_30 = io_req_0_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_1 = _GEN_30; // @[package.scala:16:47]
wire _cmd_read_T_15; // @[package.scala:16:47]
assign _cmd_read_T_15 = _GEN_30; // @[package.scala:16:47]
wire _cmd_write_T_13; // @[package.scala:16:47]
assign _cmd_write_T_13 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = io_req_0_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_2 = _GEN_31; // @[package.scala:16:47]
wire _cmd_read_T_16; // @[package.scala:16:47]
assign _cmd_read_T_16 = _GEN_31; // @[package.scala:16:47]
wire _cmd_write_T_14; // @[package.scala:16:47]
assign _cmd_write_T_14 = _GEN_31; // @[package.scala:16:47]
wire _GEN_32 = io_req_0_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_3 = _GEN_32; // @[package.scala:16:47]
wire _cmd_read_T_17; // @[package.scala:16:47]
assign _cmd_read_T_17 = _GEN_32; // @[package.scala:16:47]
wire _cmd_write_T_15; // @[package.scala:16:47]
assign _cmd_write_T_15 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = io_req_0_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign _cmd_amo_arithmetic_T_4 = _GEN_33; // @[package.scala:16:47]
wire _cmd_read_T_18; // @[package.scala:16:47]
assign _cmd_read_T_18 = _GEN_33; // @[package.scala:16:47]
wire _cmd_write_T_16; // @[package.scala:16:47]
assign _cmd_write_T_16 = _GEN_33; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_6 = _cmd_amo_arithmetic_T_5 | _cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_7 = _cmd_amo_arithmetic_T_6 | _cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_8 = _cmd_amo_arithmetic_T_7 | _cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire _cmd_amo_arithmetic_T_9 = _cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire cmd_amo_arithmetic_0 = _cmd_amo_arithmetic_T_9; // @[tlb.scala:121:49, :246:57]
wire _cmd_read_T = io_req_0_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _cmd_read_T_1 = io_req_0_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _cmd_read_T_4 = _cmd_read_T | _cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_5 = _cmd_read_T_4 | _cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_6 = _cmd_read_T_5 | _cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_11 = _cmd_read_T_7 | _cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_12 = _cmd_read_T_11 | _cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_13 = _cmd_read_T_12 | _cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_19 = _cmd_read_T_14 | _cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_20 = _cmd_read_T_19 | _cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_21 = _cmd_read_T_20 | _cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_22 = _cmd_read_T_21 | _cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire _cmd_read_T_23 = _cmd_read_T_13 | _cmd_read_T_22; // @[package.scala:81:59]
wire _cmd_read_T_24 = _cmd_read_T_6 | _cmd_read_T_23; // @[package.scala:81:59]
wire cmd_read_0 = _cmd_read_T_24; // @[Consts.scala:89:68]
wire _cmd_write_T = io_req_0_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = io_req_0_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = _cmd_write_T | _cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _cmd_write_T_4 = _cmd_write_T_2 | _cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _cmd_write_T_9 = _cmd_write_T_5 | _cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_10 = _cmd_write_T_9 | _cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_11 = _cmd_write_T_10 | _cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_17 = _cmd_write_T_12 | _cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_18 = _cmd_write_T_17 | _cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_19 = _cmd_write_T_18 | _cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_20 = _cmd_write_T_19 | _cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire _cmd_write_T_21 = _cmd_write_T_11 | _cmd_write_T_20; // @[package.scala:81:59]
wire _cmd_write_T_22 = _cmd_write_T_4 | _cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire cmd_write_0 = _cmd_write_T_22; // @[Consts.scala:90:76]
wire _cmd_write_perms_T_2 = cmd_write_0; // @[tlb.scala:121:49, :249:55]
wire _cmd_write_perms_T = io_req_0_bits_cmd_0 == 5'h5; // @[tlb.scala:17:7, :250:51]
wire cmd_write_perms_0 = _cmd_write_perms_T_2; // @[tlb.scala:121:49, :249:55]
wire [13:0] lrscAllowed_0 = _lrscAllowed_T; // @[tlb.scala:121:49, :252:38]
wire [13:0] _ae_array_T = misaligned_0 ? eff_array_0 : 14'h0; // @[tlb.scala:121:49, :254:8]
wire [13:0] _ae_array_T_1 = ~lrscAllowed_0; // @[tlb.scala:121:49, :255:24]
wire [13:0] _ae_array_T_2 = cmd_lrsc_0 ? _ae_array_T_1 : 14'h0; // @[tlb.scala:121:49, :255:{8,24}]
wire [13:0] _ae_array_T_3 = _ae_array_T | _ae_array_T_2; // @[tlb.scala:254:{8,43}, :255:8]
wire [13:0] ae_array_0 = _ae_array_T_3; // @[tlb.scala:121:49, :254:43]
wire [13:0] _ae_ld_array_T = ~pr_array_0; // @[tlb.scala:121:49, :258:66]
wire [13:0] _ae_ld_array_T_1 = ae_array_0 | _ae_ld_array_T; // @[tlb.scala:121:49, :258:{64,66}]
wire [13:0] _ae_ld_array_T_2 = cmd_read_0 ? _ae_ld_array_T_1 : 14'h0; // @[tlb.scala:121:49, :258:{38,64}]
wire [13:0] ae_ld_array_0 = _ae_ld_array_T_2; // @[tlb.scala:121:49, :258:38]
wire [13:0] _io_resp_0_ae_ld_T = ae_ld_array_0; // @[tlb.scala:121:49, :298:46]
wire [13:0] _ae_st_array_T = ~pw_array_0; // @[tlb.scala:121:49, :260:46]
wire [13:0] _ae_st_array_T_1 = ae_array_0 | _ae_st_array_T; // @[tlb.scala:121:49, :260:{44,46}]
wire [13:0] _ae_st_array_T_2 = cmd_write_perms_0 ? _ae_st_array_T_1 : 14'h0; // @[tlb.scala:121:49, :260:{8,44}]
wire [13:0] _ae_st_array_T_3 = ~pal_array_if_cached_0; // @[tlb.scala:121:49, :261:32]
wire [13:0] _ae_st_array_T_4 = cmd_amo_logical_0 ? _ae_st_array_T_3 : 14'h0; // @[tlb.scala:121:49, :261:{8,32}]
wire [13:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[tlb.scala:260:{8,65}, :261:8]
wire [13:0] _ae_st_array_T_6 = ~paa_array_if_cached_0; // @[tlb.scala:121:49, :262:32]
wire [13:0] _ae_st_array_T_7 = cmd_amo_arithmetic_0 ? _ae_st_array_T_6 : 14'h0; // @[tlb.scala:121:49, :262:{8,32}]
wire [13:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[tlb.scala:260:65, :261:62, :262:8]
wire [13:0] ae_st_array_0 = _ae_st_array_T_8; // @[tlb.scala:121:49, :261:62]
wire [13:0] _io_resp_0_ae_st_T = ae_st_array_0; // @[tlb.scala:121:49, :299:46]
wire [13:0] _must_alloc_array_T = ~paa_array_0; // @[tlb.scala:121:49, :264:32]
wire [13:0] _must_alloc_array_T_1 = cmd_amo_logical_0 ? _must_alloc_array_T : 14'h0; // @[tlb.scala:121:49, :264:{8,32}]
wire [13:0] _must_alloc_array_T_2 = ~pal_array_0; // @[tlb.scala:121:49, :265:32]
wire [13:0] _must_alloc_array_T_3 = cmd_amo_arithmetic_0 ? _must_alloc_array_T_2 : 14'h0; // @[tlb.scala:121:49, :265:{8,32}]
wire [13:0] _must_alloc_array_T_4 = _must_alloc_array_T_1 | _must_alloc_array_T_3; // @[tlb.scala:264:{8,52}, :265:8]
wire [13:0] _must_alloc_array_T_6 = {14{cmd_lrsc_0}}; // @[tlb.scala:121:49, :266:8]
wire [13:0] _must_alloc_array_T_7 = _must_alloc_array_T_4 | _must_alloc_array_T_6; // @[tlb.scala:264:52, :265:52, :266:8]
wire [13:0] must_alloc_array_0 = _must_alloc_array_T_7; // @[tlb.scala:121:49, :265:52]
wire _ma_ld_array_T = misaligned_0 & cmd_read_0; // @[tlb.scala:121:49, :267:53]
wire [13:0] _ma_ld_array_T_1 = ~eff_array_0; // @[tlb.scala:121:49, :267:70]
wire [13:0] _ma_ld_array_T_2 = _ma_ld_array_T ? _ma_ld_array_T_1 : 14'h0; // @[tlb.scala:267:{38,53,70}]
wire [13:0] ma_ld_array_0 = _ma_ld_array_T_2; // @[tlb.scala:121:49, :267:38]
wire _ma_st_array_T = misaligned_0 & cmd_write_0; // @[tlb.scala:121:49, :268:53]
wire [13:0] _ma_st_array_T_1 = ~eff_array_0; // @[tlb.scala:121:49, :267:70, :268:70]
wire [13:0] _ma_st_array_T_2 = _ma_st_array_T ? _ma_st_array_T_1 : 14'h0; // @[tlb.scala:268:{38,53,70}]
wire [13:0] ma_st_array_0 = _ma_st_array_T_2; // @[tlb.scala:121:49, :268:38]
wire [13:0] _pf_ld_array_T = r_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :269:72]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[tlb.scala:269:{59,72}]
wire [13:0] _pf_ld_array_T_2 = cmd_read_0 ? _pf_ld_array_T_1 : 14'h0; // @[tlb.scala:121:49, :269:{38,59}]
wire [13:0] pf_ld_array_0 = _pf_ld_array_T_2; // @[tlb.scala:121:49, :269:38]
wire [13:0] _pf_st_array_T = w_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :270:72]
wire [13:0] _pf_st_array_T_1 = ~_pf_st_array_T; // @[tlb.scala:270:{59,72}]
wire [13:0] _pf_st_array_T_2 = cmd_write_perms_0 ? _pf_st_array_T_1 : 14'h0; // @[tlb.scala:121:49, :270:{38,59}]
wire [13:0] pf_st_array_0 = _pf_st_array_T_2; // @[tlb.scala:121:49, :270:38]
wire [13:0] _pf_inst_array_T = x_array_0 | ptw_ae_array_0; // @[tlb.scala:121:49, :271:50]
wire [13:0] _pf_inst_array_T_1 = ~_pf_inst_array_T; // @[tlb.scala:271:{37,50}]
wire [13:0] pf_inst_array_0 = _pf_inst_array_T_1; // @[tlb.scala:121:49, :271:37]
wire [1:0] lo_lo = {sector_hits_0_1, sector_hits_0_0}; // @[OneHot.scala:22:45]
wire [1:0] lo_hi = {sector_hits_0_3, sector_hits_0_2}; // @[OneHot.scala:22:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:22:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:22:45, :31:18]
wire [1:0] hi_lo = {sector_hits_0_5, sector_hits_0_4}; // @[OneHot.scala:22:45]
wire [1:0] hi_hi = {sector_hits_0_7, sector_hits_0_6}; // @[OneHot.scala:22:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:22:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:22:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_reg_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13]
wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13]
wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_4 = ~state_reg_set_left_older_1 & _state_reg_T_3; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_8 = state_reg_set_left_older_1 & _state_reg_T_7; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? 3'h0 : _state_reg_T_9; // @[Replacement.scala:196:33, :202:12, :203:16]
wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13]
wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13]
wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_15 = ~state_reg_set_left_older_2 & _state_reg_T_14; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_19 = state_reg_set_left_older_2 & _state_reg_T_18; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16]
wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] lo_3 = {superpage_hits_0_1, superpage_hits_0_0}; // @[OneHot.scala:22:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:22:45, :31:18]
wire [1:0] hi_3 = {superpage_hits_0_3, superpage_hits_0_2}; // @[OneHot.scala:22:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:22:45, :30:18]
wire [1:0] state_reg_touch_way_sized_1 = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[1]; // @[package.scala:163:13]
wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}]
wire _state_reg_T_23 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13]
wire _state_reg_T_27 = state_reg_touch_way_sized_1[0]; // @[package.scala:163:13]
wire _state_reg_T_24 = _state_reg_T_23; // @[package.scala:163:13]
wire _state_reg_T_25 = ~_state_reg_T_24; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_26 = ~state_reg_set_left_older_3 & _state_reg_T_25; // @[Replacement.scala:196:33, :203:16, :218:7]
wire _state_reg_T_28 = _state_reg_T_27; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_29 = ~_state_reg_T_28; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_30 = state_reg_set_left_older_3 & _state_reg_T_29; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_3, _state_reg_T_26}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_31 = {state_reg_hi_3, _state_reg_T_30}; // @[Replacement.scala:202:12, :206:16]
wire [13:0] _io_resp_0_pf_ld_T_1 = pf_ld_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :295:73]
wire _io_resp_0_pf_ld_T_2 = |_io_resp_0_pf_ld_T_1; // @[tlb.scala:295:{73,84}]
assign _io_resp_0_pf_ld_T_3 = _io_resp_0_pf_ld_T_2; // @[tlb.scala:295:{54,84}]
assign io_resp_0_pf_ld_0 = _io_resp_0_pf_ld_T_3; // @[tlb.scala:17:7, :295:54]
wire [13:0] _io_resp_0_pf_st_T_1 = pf_st_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :296:80]
wire _io_resp_0_pf_st_T_2 = |_io_resp_0_pf_st_T_1; // @[tlb.scala:296:{80,91}]
assign _io_resp_0_pf_st_T_3 = _io_resp_0_pf_st_T_2; // @[tlb.scala:296:{61,91}]
assign io_resp_0_pf_st_0 = _io_resp_0_pf_st_T_3; // @[tlb.scala:17:7, :296:61]
wire [13:0] _io_resp_0_pf_inst_T = pf_inst_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :297:58]
wire _io_resp_0_pf_inst_T_1 = |_io_resp_0_pf_inst_T; // @[tlb.scala:297:{58,69}]
assign _io_resp_0_pf_inst_T_2 = _io_resp_0_pf_inst_T_1; // @[tlb.scala:297:{37,69}]
assign io_resp_0_pf_inst = _io_resp_0_pf_inst_T_2; // @[tlb.scala:17:7, :297:37]
wire [13:0] _io_resp_0_ae_ld_T_1 = _io_resp_0_ae_ld_T & 14'h2000; // @[tlb.scala:121:49, :175:31, :298:{46,63}]
assign _io_resp_0_ae_ld_T_2 = |_io_resp_0_ae_ld_T_1; // @[tlb.scala:298:{63,74}]
assign io_resp_0_ae_ld_0 = _io_resp_0_ae_ld_T_2; // @[tlb.scala:17:7, :298:74]
wire [13:0] _io_resp_0_ae_st_T_1 = _io_resp_0_ae_st_T & 14'h2000; // @[tlb.scala:121:49, :175:31, :299:{46,63}]
assign _io_resp_0_ae_st_T_2 = |_io_resp_0_ae_st_T_1; // @[tlb.scala:299:{63,74}]
assign io_resp_0_ae_st_0 = _io_resp_0_ae_st_T_2; // @[tlb.scala:17:7, :299:74]
wire [13:0] _io_resp_0_ae_inst_T = ~px_array_0; // @[tlb.scala:121:49, :300:48]
wire [13:0] _io_resp_0_ae_inst_T_1 = _io_resp_0_ae_inst_T; // @[tlb.scala:300:{46,48}]
wire [13:0] _io_resp_0_ae_inst_T_2 = _io_resp_0_ae_inst_T_1 & 14'h2000; // @[tlb.scala:121:49, :175:31, :300:{46,63}]
assign _io_resp_0_ae_inst_T_3 = |_io_resp_0_ae_inst_T_2; // @[tlb.scala:300:{63,74}]
assign io_resp_0_ae_inst = _io_resp_0_ae_inst_T_3; // @[tlb.scala:17:7, :300:74]
wire [13:0] _io_resp_0_ma_ld_T = ma_ld_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :301:43]
assign _io_resp_0_ma_ld_T_1 = |_io_resp_0_ma_ld_T; // @[tlb.scala:301:{43,54}]
assign io_resp_0_ma_ld_0 = _io_resp_0_ma_ld_T_1; // @[tlb.scala:17:7, :301:54]
wire [13:0] _io_resp_0_ma_st_T = ma_st_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :302:43]
assign _io_resp_0_ma_st_T_1 = |_io_resp_0_ma_st_T; // @[tlb.scala:302:{43,54}]
assign io_resp_0_ma_st_0 = _io_resp_0_ma_st_T_1; // @[tlb.scala:17:7, :302:54]
wire [13:0] _io_resp_0_cacheable_T = c_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :304:44]
assign _io_resp_0_cacheable_T_1 = |_io_resp_0_cacheable_T; // @[tlb.scala:304:{44,55}]
assign io_resp_0_cacheable_0 = _io_resp_0_cacheable_T_1; // @[tlb.scala:17:7, :304:55]
wire [13:0] _io_resp_0_must_alloc_T = must_alloc_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :305:53]
assign _io_resp_0_must_alloc_T_1 = |_io_resp_0_must_alloc_T; // @[tlb.scala:305:{53,64}]
assign io_resp_0_must_alloc = _io_resp_0_must_alloc_T_1; // @[tlb.scala:17:7, :305:64]
wire [13:0] _io_resp_0_prefetchable_T = prefetchable_array_0 & 14'h2000; // @[tlb.scala:121:49, :175:31, :306:55]
wire _io_resp_0_prefetchable_T_1 = |_io_resp_0_prefetchable_T; // @[tlb.scala:306:{55,66}]
assign _io_resp_0_prefetchable_T_2 = _io_resp_0_prefetchable_T_1; // @[tlb.scala:306:{66,70}]
assign io_resp_0_prefetchable = _io_resp_0_prefetchable_T_2; // @[tlb.scala:17:7, :306:70]
assign _io_resp_0_paddr_T_1 = {ppn_0, _io_resp_0_paddr_T}; // @[tlb.scala:121:49, :308:{28,57}]
assign io_resp_0_paddr_0 = _io_resp_0_paddr_T_1; // @[tlb.scala:17:7, :308:28]
OptimizationBarrier_EntryData_39 mpu_ppn_data_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_mpu_ppn_data_WIRE_ppn), // @[tlb.scala:60:79]
.io_x_u (_mpu_ppn_data_WIRE_u), // @[tlb.scala:60:79]
.io_x_g (_mpu_ppn_data_WIRE_g), // @[tlb.scala:60:79]
.io_x_ae (_mpu_ppn_data_WIRE_ae), // @[tlb.scala:60:79]
.io_x_sw (_mpu_ppn_data_WIRE_sw), // @[tlb.scala:60:79]
.io_x_sx (_mpu_ppn_data_WIRE_sx), // @[tlb.scala:60:79]
.io_x_sr (_mpu_ppn_data_WIRE_sr), // @[tlb.scala:60:79]
.io_x_pw (_mpu_ppn_data_WIRE_pw), // @[tlb.scala:60:79]
.io_x_px (_mpu_ppn_data_WIRE_px), // @[tlb.scala:60:79]
.io_x_pr (_mpu_ppn_data_WIRE_pr), // @[tlb.scala:60:79]
.io_x_pal (_mpu_ppn_data_WIRE_pal), // @[tlb.scala:60:79]
.io_x_paa (_mpu_ppn_data_WIRE_paa), // @[tlb.scala:60:79]
.io_x_eff (_mpu_ppn_data_WIRE_eff), // @[tlb.scala:60:79]
.io_x_c (_mpu_ppn_data_WIRE_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_mpu_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
PMPChecker_s3_1 pmp_0 ( // @[tlb.scala:152:40]
.clock (clock),
.reset (reset),
.io_addr (mpu_physaddr_0[31:0]), // @[tlb.scala:121:49, :154:20]
.io_size (io_req_0_bits_size_0) // @[tlb.scala:17:7]
); // @[tlb.scala:152:40]
OptimizationBarrier_EntryData_40 ppn_data_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_41 ppn_data_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_2_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_2_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_2_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_2_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_2_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_2_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_2_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_2_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_2_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_2_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_2_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_2_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_2_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_2_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_2_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_42 ppn_data_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_4_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_4_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_4_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_4_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_4_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_4_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_4_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_4_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_4_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_4_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_4_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_4_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_4_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_4_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_4_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_43 ppn_data_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_6_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_6_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_6_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_6_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_6_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_6_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_6_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_6_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_6_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_6_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_6_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_6_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_6_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_6_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_6_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_44 ppn_data_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_8_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_8_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_8_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_8_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_8_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_8_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_8_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_8_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_8_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_8_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_8_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_8_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_8_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_8_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_8_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_45 ppn_data_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_10_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_10_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_10_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_10_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_10_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_10_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_10_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_10_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_10_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_10_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_10_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_10_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_10_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_10_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_10_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_46 ppn_data_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_12_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_12_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_12_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_12_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_12_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_12_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_12_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_12_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_12_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_12_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_12_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_12_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_12_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_12_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_12_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_47 ppn_data_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_14_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_14_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_14_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_14_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_14_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_14_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_14_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_14_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_14_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_14_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_14_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_14_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_14_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_14_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_14_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_48 ppn_data_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_16_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_16_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_16_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_16_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_16_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_16_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_16_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_16_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_16_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_16_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_16_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_16_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_16_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_16_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_16_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_49 ppn_data_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_18_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_18_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_18_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_18_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_18_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_18_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_18_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_18_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_18_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_18_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_18_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_18_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_18_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_18_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_18_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_50 ppn_data_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_20_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_20_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_20_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_20_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_20_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_20_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_20_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_20_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_20_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_20_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_20_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_20_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_20_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_20_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_20_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_51 ppn_data_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_22_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_22_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_22_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_22_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_22_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_22_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_22_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_22_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_22_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_22_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_22_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_22_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_22_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_22_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_22_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_52 ppn_data_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_ppn_data_WIRE_24_ppn), // @[tlb.scala:60:79]
.io_x_u (_ppn_data_WIRE_24_u), // @[tlb.scala:60:79]
.io_x_g (_ppn_data_WIRE_24_g), // @[tlb.scala:60:79]
.io_x_ae (_ppn_data_WIRE_24_ae), // @[tlb.scala:60:79]
.io_x_sw (_ppn_data_WIRE_24_sw), // @[tlb.scala:60:79]
.io_x_sx (_ppn_data_WIRE_24_sx), // @[tlb.scala:60:79]
.io_x_sr (_ppn_data_WIRE_24_sr), // @[tlb.scala:60:79]
.io_x_pw (_ppn_data_WIRE_24_pw), // @[tlb.scala:60:79]
.io_x_px (_ppn_data_WIRE_24_px), // @[tlb.scala:60:79]
.io_x_pr (_ppn_data_WIRE_24_pr), // @[tlb.scala:60:79]
.io_x_pal (_ppn_data_WIRE_24_pal), // @[tlb.scala:60:79]
.io_x_paa (_ppn_data_WIRE_24_paa), // @[tlb.scala:60:79]
.io_x_eff (_ppn_data_WIRE_24_eff), // @[tlb.scala:60:79]
.io_x_c (_ppn_data_WIRE_24_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_ppn_data_WIRE_24_fragmented_superpage) // @[tlb.scala:60:79]
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_53 entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_0_ppn),
.io_y_u (_entries_WIRE_26_0_u),
.io_y_g (_entries_WIRE_26_0_g),
.io_y_ae (_entries_WIRE_26_0_ae),
.io_y_sw (_entries_WIRE_26_0_sw),
.io_y_sx (_entries_WIRE_26_0_sx),
.io_y_sr (_entries_WIRE_26_0_sr),
.io_y_pw (_entries_WIRE_26_0_pw),
.io_y_px (_entries_WIRE_26_0_px),
.io_y_pr (_entries_WIRE_26_0_pr),
.io_y_pal (_entries_WIRE_26_0_pal),
.io_y_paa (_entries_WIRE_26_0_paa),
.io_y_eff (_entries_WIRE_26_0_eff),
.io_y_c (_entries_WIRE_26_0_c),
.io_y_fragmented_superpage (_entries_WIRE_26_0_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_54 entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_2_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_2_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_2_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_2_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_2_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_2_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_2_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_2_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_2_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_2_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_2_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_2_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_2_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_2_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_1_ppn),
.io_y_u (_entries_WIRE_26_1_u),
.io_y_g (_entries_WIRE_26_1_g),
.io_y_ae (_entries_WIRE_26_1_ae),
.io_y_sw (_entries_WIRE_26_1_sw),
.io_y_sx (_entries_WIRE_26_1_sx),
.io_y_sr (_entries_WIRE_26_1_sr),
.io_y_pw (_entries_WIRE_26_1_pw),
.io_y_px (_entries_WIRE_26_1_px),
.io_y_pr (_entries_WIRE_26_1_pr),
.io_y_pal (_entries_WIRE_26_1_pal),
.io_y_paa (_entries_WIRE_26_1_paa),
.io_y_eff (_entries_WIRE_26_1_eff),
.io_y_c (_entries_WIRE_26_1_c),
.io_y_fragmented_superpage (_entries_WIRE_26_1_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_55 entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_4_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_4_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_4_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_4_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_4_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_4_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_4_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_4_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_4_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_4_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_4_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_4_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_4_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_4_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_2_ppn),
.io_y_u (_entries_WIRE_26_2_u),
.io_y_g (_entries_WIRE_26_2_g),
.io_y_ae (_entries_WIRE_26_2_ae),
.io_y_sw (_entries_WIRE_26_2_sw),
.io_y_sx (_entries_WIRE_26_2_sx),
.io_y_sr (_entries_WIRE_26_2_sr),
.io_y_pw (_entries_WIRE_26_2_pw),
.io_y_px (_entries_WIRE_26_2_px),
.io_y_pr (_entries_WIRE_26_2_pr),
.io_y_pal (_entries_WIRE_26_2_pal),
.io_y_paa (_entries_WIRE_26_2_paa),
.io_y_eff (_entries_WIRE_26_2_eff),
.io_y_c (_entries_WIRE_26_2_c),
.io_y_fragmented_superpage (_entries_WIRE_26_2_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_56 entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_6_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_6_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_6_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_6_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_6_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_6_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_6_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_6_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_6_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_6_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_6_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_6_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_6_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_6_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_3_ppn),
.io_y_u (_entries_WIRE_26_3_u),
.io_y_g (_entries_WIRE_26_3_g),
.io_y_ae (_entries_WIRE_26_3_ae),
.io_y_sw (_entries_WIRE_26_3_sw),
.io_y_sx (_entries_WIRE_26_3_sx),
.io_y_sr (_entries_WIRE_26_3_sr),
.io_y_pw (_entries_WIRE_26_3_pw),
.io_y_px (_entries_WIRE_26_3_px),
.io_y_pr (_entries_WIRE_26_3_pr),
.io_y_pal (_entries_WIRE_26_3_pal),
.io_y_paa (_entries_WIRE_26_3_paa),
.io_y_eff (_entries_WIRE_26_3_eff),
.io_y_c (_entries_WIRE_26_3_c),
.io_y_fragmented_superpage (_entries_WIRE_26_3_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_57 entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_8_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_8_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_8_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_8_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_8_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_8_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_8_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_8_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_8_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_8_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_8_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_8_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_8_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_8_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_4_ppn),
.io_y_u (_entries_WIRE_26_4_u),
.io_y_g (_entries_WIRE_26_4_g),
.io_y_ae (_entries_WIRE_26_4_ae),
.io_y_sw (_entries_WIRE_26_4_sw),
.io_y_sx (_entries_WIRE_26_4_sx),
.io_y_sr (_entries_WIRE_26_4_sr),
.io_y_pw (_entries_WIRE_26_4_pw),
.io_y_px (_entries_WIRE_26_4_px),
.io_y_pr (_entries_WIRE_26_4_pr),
.io_y_pal (_entries_WIRE_26_4_pal),
.io_y_paa (_entries_WIRE_26_4_paa),
.io_y_eff (_entries_WIRE_26_4_eff),
.io_y_c (_entries_WIRE_26_4_c),
.io_y_fragmented_superpage (_entries_WIRE_26_4_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_58 entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_10_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_10_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_10_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_10_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_10_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_10_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_10_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_10_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_10_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_10_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_10_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_10_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_10_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_10_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_5_ppn),
.io_y_u (_entries_WIRE_26_5_u),
.io_y_g (_entries_WIRE_26_5_g),
.io_y_ae (_entries_WIRE_26_5_ae),
.io_y_sw (_entries_WIRE_26_5_sw),
.io_y_sx (_entries_WIRE_26_5_sx),
.io_y_sr (_entries_WIRE_26_5_sr),
.io_y_pw (_entries_WIRE_26_5_pw),
.io_y_px (_entries_WIRE_26_5_px),
.io_y_pr (_entries_WIRE_26_5_pr),
.io_y_pal (_entries_WIRE_26_5_pal),
.io_y_paa (_entries_WIRE_26_5_paa),
.io_y_eff (_entries_WIRE_26_5_eff),
.io_y_c (_entries_WIRE_26_5_c),
.io_y_fragmented_superpage (_entries_WIRE_26_5_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_59 entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_12_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_12_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_12_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_12_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_12_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_12_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_12_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_12_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_12_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_12_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_12_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_12_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_12_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_12_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_6_ppn),
.io_y_u (_entries_WIRE_26_6_u),
.io_y_g (_entries_WIRE_26_6_g),
.io_y_ae (_entries_WIRE_26_6_ae),
.io_y_sw (_entries_WIRE_26_6_sw),
.io_y_sx (_entries_WIRE_26_6_sx),
.io_y_sr (_entries_WIRE_26_6_sr),
.io_y_pw (_entries_WIRE_26_6_pw),
.io_y_px (_entries_WIRE_26_6_px),
.io_y_pr (_entries_WIRE_26_6_pr),
.io_y_pal (_entries_WIRE_26_6_pal),
.io_y_paa (_entries_WIRE_26_6_paa),
.io_y_eff (_entries_WIRE_26_6_eff),
.io_y_c (_entries_WIRE_26_6_c),
.io_y_fragmented_superpage (_entries_WIRE_26_6_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_60 entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_14_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_14_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_14_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_14_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_14_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_14_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_14_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_14_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_14_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_14_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_14_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_14_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_14_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_14_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_7_ppn),
.io_y_u (_entries_WIRE_26_7_u),
.io_y_g (_entries_WIRE_26_7_g),
.io_y_ae (_entries_WIRE_26_7_ae),
.io_y_sw (_entries_WIRE_26_7_sw),
.io_y_sx (_entries_WIRE_26_7_sx),
.io_y_sr (_entries_WIRE_26_7_sr),
.io_y_pw (_entries_WIRE_26_7_pw),
.io_y_px (_entries_WIRE_26_7_px),
.io_y_pr (_entries_WIRE_26_7_pr),
.io_y_pal (_entries_WIRE_26_7_pal),
.io_y_paa (_entries_WIRE_26_7_paa),
.io_y_eff (_entries_WIRE_26_7_eff),
.io_y_c (_entries_WIRE_26_7_c),
.io_y_fragmented_superpage (_entries_WIRE_26_7_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_61 entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_16_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_16_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_16_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_16_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_16_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_16_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_16_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_16_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_16_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_16_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_16_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_16_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_16_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_16_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_8_ppn),
.io_y_u (_entries_WIRE_26_8_u),
.io_y_g (_entries_WIRE_26_8_g),
.io_y_ae (_entries_WIRE_26_8_ae),
.io_y_sw (_entries_WIRE_26_8_sw),
.io_y_sx (_entries_WIRE_26_8_sx),
.io_y_sr (_entries_WIRE_26_8_sr),
.io_y_pw (_entries_WIRE_26_8_pw),
.io_y_px (_entries_WIRE_26_8_px),
.io_y_pr (_entries_WIRE_26_8_pr),
.io_y_pal (_entries_WIRE_26_8_pal),
.io_y_paa (_entries_WIRE_26_8_paa),
.io_y_eff (_entries_WIRE_26_8_eff),
.io_y_c (_entries_WIRE_26_8_c),
.io_y_fragmented_superpage (_entries_WIRE_26_8_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_62 entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_18_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_18_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_18_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_18_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_18_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_18_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_18_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_18_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_18_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_18_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_18_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_18_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_18_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_18_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_9_ppn),
.io_y_u (_entries_WIRE_26_9_u),
.io_y_g (_entries_WIRE_26_9_g),
.io_y_ae (_entries_WIRE_26_9_ae),
.io_y_sw (_entries_WIRE_26_9_sw),
.io_y_sx (_entries_WIRE_26_9_sx),
.io_y_sr (_entries_WIRE_26_9_sr),
.io_y_pw (_entries_WIRE_26_9_pw),
.io_y_px (_entries_WIRE_26_9_px),
.io_y_pr (_entries_WIRE_26_9_pr),
.io_y_pal (_entries_WIRE_26_9_pal),
.io_y_paa (_entries_WIRE_26_9_paa),
.io_y_eff (_entries_WIRE_26_9_eff),
.io_y_c (_entries_WIRE_26_9_c),
.io_y_fragmented_superpage (_entries_WIRE_26_9_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_63 entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_20_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_20_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_20_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_20_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_20_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_20_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_20_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_20_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_20_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_20_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_20_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_20_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_20_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_20_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_10_ppn),
.io_y_u (_entries_WIRE_26_10_u),
.io_y_g (_entries_WIRE_26_10_g),
.io_y_ae (_entries_WIRE_26_10_ae),
.io_y_sw (_entries_WIRE_26_10_sw),
.io_y_sx (_entries_WIRE_26_10_sx),
.io_y_sr (_entries_WIRE_26_10_sr),
.io_y_pw (_entries_WIRE_26_10_pw),
.io_y_px (_entries_WIRE_26_10_px),
.io_y_pr (_entries_WIRE_26_10_pr),
.io_y_pal (_entries_WIRE_26_10_pal),
.io_y_paa (_entries_WIRE_26_10_paa),
.io_y_eff (_entries_WIRE_26_10_eff),
.io_y_c (_entries_WIRE_26_10_c),
.io_y_fragmented_superpage (_entries_WIRE_26_10_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_64 entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_22_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_22_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_22_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_22_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_22_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_22_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_22_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_22_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_22_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_22_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_22_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_22_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_22_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_22_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_11_ppn),
.io_y_u (_entries_WIRE_26_11_u),
.io_y_g (_entries_WIRE_26_11_g),
.io_y_ae (_entries_WIRE_26_11_ae),
.io_y_sw (_entries_WIRE_26_11_sw),
.io_y_sx (_entries_WIRE_26_11_sx),
.io_y_sr (_entries_WIRE_26_11_sr),
.io_y_pw (_entries_WIRE_26_11_pw),
.io_y_px (_entries_WIRE_26_11_px),
.io_y_pr (_entries_WIRE_26_11_pr),
.io_y_pal (_entries_WIRE_26_11_pal),
.io_y_paa (_entries_WIRE_26_11_paa),
.io_y_eff (_entries_WIRE_26_11_eff),
.io_y_c (_entries_WIRE_26_11_c),
.io_y_fragmented_superpage (_entries_WIRE_26_11_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_65 entries_barrier_12 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_entries_WIRE_24_ppn), // @[tlb.scala:60:79]
.io_x_u (_entries_WIRE_24_u), // @[tlb.scala:60:79]
.io_x_g (_entries_WIRE_24_g), // @[tlb.scala:60:79]
.io_x_ae (_entries_WIRE_24_ae), // @[tlb.scala:60:79]
.io_x_sw (_entries_WIRE_24_sw), // @[tlb.scala:60:79]
.io_x_sx (_entries_WIRE_24_sx), // @[tlb.scala:60:79]
.io_x_sr (_entries_WIRE_24_sr), // @[tlb.scala:60:79]
.io_x_pw (_entries_WIRE_24_pw), // @[tlb.scala:60:79]
.io_x_px (_entries_WIRE_24_px), // @[tlb.scala:60:79]
.io_x_pr (_entries_WIRE_24_pr), // @[tlb.scala:60:79]
.io_x_pal (_entries_WIRE_24_pal), // @[tlb.scala:60:79]
.io_x_paa (_entries_WIRE_24_paa), // @[tlb.scala:60:79]
.io_x_eff (_entries_WIRE_24_eff), // @[tlb.scala:60:79]
.io_x_c (_entries_WIRE_24_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_entries_WIRE_24_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_entries_WIRE_26_12_ppn),
.io_y_u (_entries_WIRE_26_12_u),
.io_y_g (_entries_WIRE_26_12_g),
.io_y_ae (_entries_WIRE_26_12_ae),
.io_y_sw (_entries_WIRE_26_12_sw),
.io_y_sx (_entries_WIRE_26_12_sx),
.io_y_sr (_entries_WIRE_26_12_sr),
.io_y_pw (_entries_WIRE_26_12_pw),
.io_y_px (_entries_WIRE_26_12_px),
.io_y_pr (_entries_WIRE_26_12_pr),
.io_y_pal (_entries_WIRE_26_12_pal),
.io_y_paa (_entries_WIRE_26_12_paa),
.io_y_eff (_entries_WIRE_26_12_eff),
.io_y_c (_entries_WIRE_26_12_c),
.io_y_fragmented_superpage (_entries_WIRE_26_12_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_66 normal_entries_barrier ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_0_ppn),
.io_y_u (_normal_entries_WIRE_24_0_u),
.io_y_g (_normal_entries_WIRE_24_0_g),
.io_y_ae (_normal_entries_WIRE_24_0_ae),
.io_y_sw (_normal_entries_WIRE_24_0_sw),
.io_y_sx (_normal_entries_WIRE_24_0_sx),
.io_y_sr (_normal_entries_WIRE_24_0_sr),
.io_y_pw (_normal_entries_WIRE_24_0_pw),
.io_y_px (_normal_entries_WIRE_24_0_px),
.io_y_pr (_normal_entries_WIRE_24_0_pr),
.io_y_pal (_normal_entries_WIRE_24_0_pal),
.io_y_paa (_normal_entries_WIRE_24_0_paa),
.io_y_eff (_normal_entries_WIRE_24_0_eff),
.io_y_c (_normal_entries_WIRE_24_0_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_0_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_67 normal_entries_barrier_1 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_2_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_2_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_2_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_2_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_2_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_2_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_2_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_2_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_2_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_2_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_2_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_2_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_2_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_2_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_2_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_1_ppn),
.io_y_u (_normal_entries_WIRE_24_1_u),
.io_y_g (_normal_entries_WIRE_24_1_g),
.io_y_ae (_normal_entries_WIRE_24_1_ae),
.io_y_sw (_normal_entries_WIRE_24_1_sw),
.io_y_sx (_normal_entries_WIRE_24_1_sx),
.io_y_sr (_normal_entries_WIRE_24_1_sr),
.io_y_pw (_normal_entries_WIRE_24_1_pw),
.io_y_px (_normal_entries_WIRE_24_1_px),
.io_y_pr (_normal_entries_WIRE_24_1_pr),
.io_y_pal (_normal_entries_WIRE_24_1_pal),
.io_y_paa (_normal_entries_WIRE_24_1_paa),
.io_y_eff (_normal_entries_WIRE_24_1_eff),
.io_y_c (_normal_entries_WIRE_24_1_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_1_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_68 normal_entries_barrier_2 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_4_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_4_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_4_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_4_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_4_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_4_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_4_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_4_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_4_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_4_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_4_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_4_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_4_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_4_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_4_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_2_ppn),
.io_y_u (_normal_entries_WIRE_24_2_u),
.io_y_g (_normal_entries_WIRE_24_2_g),
.io_y_ae (_normal_entries_WIRE_24_2_ae),
.io_y_sw (_normal_entries_WIRE_24_2_sw),
.io_y_sx (_normal_entries_WIRE_24_2_sx),
.io_y_sr (_normal_entries_WIRE_24_2_sr),
.io_y_pw (_normal_entries_WIRE_24_2_pw),
.io_y_px (_normal_entries_WIRE_24_2_px),
.io_y_pr (_normal_entries_WIRE_24_2_pr),
.io_y_pal (_normal_entries_WIRE_24_2_pal),
.io_y_paa (_normal_entries_WIRE_24_2_paa),
.io_y_eff (_normal_entries_WIRE_24_2_eff),
.io_y_c (_normal_entries_WIRE_24_2_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_2_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_69 normal_entries_barrier_3 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_6_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_6_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_6_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_6_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_6_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_6_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_6_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_6_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_6_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_6_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_6_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_6_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_6_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_6_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_6_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_3_ppn),
.io_y_u (_normal_entries_WIRE_24_3_u),
.io_y_g (_normal_entries_WIRE_24_3_g),
.io_y_ae (_normal_entries_WIRE_24_3_ae),
.io_y_sw (_normal_entries_WIRE_24_3_sw),
.io_y_sx (_normal_entries_WIRE_24_3_sx),
.io_y_sr (_normal_entries_WIRE_24_3_sr),
.io_y_pw (_normal_entries_WIRE_24_3_pw),
.io_y_px (_normal_entries_WIRE_24_3_px),
.io_y_pr (_normal_entries_WIRE_24_3_pr),
.io_y_pal (_normal_entries_WIRE_24_3_pal),
.io_y_paa (_normal_entries_WIRE_24_3_paa),
.io_y_eff (_normal_entries_WIRE_24_3_eff),
.io_y_c (_normal_entries_WIRE_24_3_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_3_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_70 normal_entries_barrier_4 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_8_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_8_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_8_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_8_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_8_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_8_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_8_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_8_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_8_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_8_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_8_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_8_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_8_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_8_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_8_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_4_ppn),
.io_y_u (_normal_entries_WIRE_24_4_u),
.io_y_g (_normal_entries_WIRE_24_4_g),
.io_y_ae (_normal_entries_WIRE_24_4_ae),
.io_y_sw (_normal_entries_WIRE_24_4_sw),
.io_y_sx (_normal_entries_WIRE_24_4_sx),
.io_y_sr (_normal_entries_WIRE_24_4_sr),
.io_y_pw (_normal_entries_WIRE_24_4_pw),
.io_y_px (_normal_entries_WIRE_24_4_px),
.io_y_pr (_normal_entries_WIRE_24_4_pr),
.io_y_pal (_normal_entries_WIRE_24_4_pal),
.io_y_paa (_normal_entries_WIRE_24_4_paa),
.io_y_eff (_normal_entries_WIRE_24_4_eff),
.io_y_c (_normal_entries_WIRE_24_4_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_4_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_71 normal_entries_barrier_5 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_10_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_10_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_10_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_10_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_10_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_10_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_10_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_10_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_10_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_10_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_10_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_10_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_10_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_10_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_10_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_5_ppn),
.io_y_u (_normal_entries_WIRE_24_5_u),
.io_y_g (_normal_entries_WIRE_24_5_g),
.io_y_ae (_normal_entries_WIRE_24_5_ae),
.io_y_sw (_normal_entries_WIRE_24_5_sw),
.io_y_sx (_normal_entries_WIRE_24_5_sx),
.io_y_sr (_normal_entries_WIRE_24_5_sr),
.io_y_pw (_normal_entries_WIRE_24_5_pw),
.io_y_px (_normal_entries_WIRE_24_5_px),
.io_y_pr (_normal_entries_WIRE_24_5_pr),
.io_y_pal (_normal_entries_WIRE_24_5_pal),
.io_y_paa (_normal_entries_WIRE_24_5_paa),
.io_y_eff (_normal_entries_WIRE_24_5_eff),
.io_y_c (_normal_entries_WIRE_24_5_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_5_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_72 normal_entries_barrier_6 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_12_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_12_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_12_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_12_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_12_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_12_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_12_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_12_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_12_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_12_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_12_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_12_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_12_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_12_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_12_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_6_ppn),
.io_y_u (_normal_entries_WIRE_24_6_u),
.io_y_g (_normal_entries_WIRE_24_6_g),
.io_y_ae (_normal_entries_WIRE_24_6_ae),
.io_y_sw (_normal_entries_WIRE_24_6_sw),
.io_y_sx (_normal_entries_WIRE_24_6_sx),
.io_y_sr (_normal_entries_WIRE_24_6_sr),
.io_y_pw (_normal_entries_WIRE_24_6_pw),
.io_y_px (_normal_entries_WIRE_24_6_px),
.io_y_pr (_normal_entries_WIRE_24_6_pr),
.io_y_pal (_normal_entries_WIRE_24_6_pal),
.io_y_paa (_normal_entries_WIRE_24_6_paa),
.io_y_eff (_normal_entries_WIRE_24_6_eff),
.io_y_c (_normal_entries_WIRE_24_6_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_6_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_73 normal_entries_barrier_7 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_14_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_14_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_14_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_14_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_14_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_14_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_14_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_14_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_14_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_14_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_14_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_14_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_14_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_14_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_14_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_7_ppn),
.io_y_u (_normal_entries_WIRE_24_7_u),
.io_y_g (_normal_entries_WIRE_24_7_g),
.io_y_ae (_normal_entries_WIRE_24_7_ae),
.io_y_sw (_normal_entries_WIRE_24_7_sw),
.io_y_sx (_normal_entries_WIRE_24_7_sx),
.io_y_sr (_normal_entries_WIRE_24_7_sr),
.io_y_pw (_normal_entries_WIRE_24_7_pw),
.io_y_px (_normal_entries_WIRE_24_7_px),
.io_y_pr (_normal_entries_WIRE_24_7_pr),
.io_y_pal (_normal_entries_WIRE_24_7_pal),
.io_y_paa (_normal_entries_WIRE_24_7_paa),
.io_y_eff (_normal_entries_WIRE_24_7_eff),
.io_y_c (_normal_entries_WIRE_24_7_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_7_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_74 normal_entries_barrier_8 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_16_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_16_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_16_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_16_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_16_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_16_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_16_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_16_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_16_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_16_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_16_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_16_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_16_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_16_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_16_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_8_ppn),
.io_y_u (_normal_entries_WIRE_24_8_u),
.io_y_g (_normal_entries_WIRE_24_8_g),
.io_y_ae (_normal_entries_WIRE_24_8_ae),
.io_y_sw (_normal_entries_WIRE_24_8_sw),
.io_y_sx (_normal_entries_WIRE_24_8_sx),
.io_y_sr (_normal_entries_WIRE_24_8_sr),
.io_y_pw (_normal_entries_WIRE_24_8_pw),
.io_y_px (_normal_entries_WIRE_24_8_px),
.io_y_pr (_normal_entries_WIRE_24_8_pr),
.io_y_pal (_normal_entries_WIRE_24_8_pal),
.io_y_paa (_normal_entries_WIRE_24_8_paa),
.io_y_eff (_normal_entries_WIRE_24_8_eff),
.io_y_c (_normal_entries_WIRE_24_8_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_8_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_75 normal_entries_barrier_9 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_18_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_18_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_18_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_18_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_18_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_18_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_18_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_18_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_18_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_18_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_18_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_18_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_18_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_18_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_18_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_9_ppn),
.io_y_u (_normal_entries_WIRE_24_9_u),
.io_y_g (_normal_entries_WIRE_24_9_g),
.io_y_ae (_normal_entries_WIRE_24_9_ae),
.io_y_sw (_normal_entries_WIRE_24_9_sw),
.io_y_sx (_normal_entries_WIRE_24_9_sx),
.io_y_sr (_normal_entries_WIRE_24_9_sr),
.io_y_pw (_normal_entries_WIRE_24_9_pw),
.io_y_px (_normal_entries_WIRE_24_9_px),
.io_y_pr (_normal_entries_WIRE_24_9_pr),
.io_y_pal (_normal_entries_WIRE_24_9_pal),
.io_y_paa (_normal_entries_WIRE_24_9_paa),
.io_y_eff (_normal_entries_WIRE_24_9_eff),
.io_y_c (_normal_entries_WIRE_24_9_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_9_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_76 normal_entries_barrier_10 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_20_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_20_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_20_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_20_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_20_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_20_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_20_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_20_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_20_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_20_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_20_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_20_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_20_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_20_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_20_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_10_ppn),
.io_y_u (_normal_entries_WIRE_24_10_u),
.io_y_g (_normal_entries_WIRE_24_10_g),
.io_y_ae (_normal_entries_WIRE_24_10_ae),
.io_y_sw (_normal_entries_WIRE_24_10_sw),
.io_y_sx (_normal_entries_WIRE_24_10_sx),
.io_y_sr (_normal_entries_WIRE_24_10_sr),
.io_y_pw (_normal_entries_WIRE_24_10_pw),
.io_y_px (_normal_entries_WIRE_24_10_px),
.io_y_pr (_normal_entries_WIRE_24_10_pr),
.io_y_pal (_normal_entries_WIRE_24_10_pal),
.io_y_paa (_normal_entries_WIRE_24_10_paa),
.io_y_eff (_normal_entries_WIRE_24_10_eff),
.io_y_c (_normal_entries_WIRE_24_10_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_10_fragmented_superpage)
); // @[package.scala:267:25]
OptimizationBarrier_EntryData_77 normal_entries_barrier_11 ( // @[package.scala:267:25]
.clock (clock),
.reset (reset),
.io_x_ppn (_normal_entries_WIRE_22_ppn), // @[tlb.scala:60:79]
.io_x_u (_normal_entries_WIRE_22_u), // @[tlb.scala:60:79]
.io_x_g (_normal_entries_WIRE_22_g), // @[tlb.scala:60:79]
.io_x_ae (_normal_entries_WIRE_22_ae), // @[tlb.scala:60:79]
.io_x_sw (_normal_entries_WIRE_22_sw), // @[tlb.scala:60:79]
.io_x_sx (_normal_entries_WIRE_22_sx), // @[tlb.scala:60:79]
.io_x_sr (_normal_entries_WIRE_22_sr), // @[tlb.scala:60:79]
.io_x_pw (_normal_entries_WIRE_22_pw), // @[tlb.scala:60:79]
.io_x_px (_normal_entries_WIRE_22_px), // @[tlb.scala:60:79]
.io_x_pr (_normal_entries_WIRE_22_pr), // @[tlb.scala:60:79]
.io_x_pal (_normal_entries_WIRE_22_pal), // @[tlb.scala:60:79]
.io_x_paa (_normal_entries_WIRE_22_paa), // @[tlb.scala:60:79]
.io_x_eff (_normal_entries_WIRE_22_eff), // @[tlb.scala:60:79]
.io_x_c (_normal_entries_WIRE_22_c), // @[tlb.scala:60:79]
.io_x_fragmented_superpage (_normal_entries_WIRE_22_fragmented_superpage), // @[tlb.scala:60:79]
.io_y_ppn (_normal_entries_WIRE_24_11_ppn),
.io_y_u (_normal_entries_WIRE_24_11_u),
.io_y_g (_normal_entries_WIRE_24_11_g),
.io_y_ae (_normal_entries_WIRE_24_11_ae),
.io_y_sw (_normal_entries_WIRE_24_11_sw),
.io_y_sx (_normal_entries_WIRE_24_11_sx),
.io_y_sr (_normal_entries_WIRE_24_11_sr),
.io_y_pw (_normal_entries_WIRE_24_11_pw),
.io_y_px (_normal_entries_WIRE_24_11_px),
.io_y_pr (_normal_entries_WIRE_24_11_pr),
.io_y_pal (_normal_entries_WIRE_24_11_pal),
.io_y_paa (_normal_entries_WIRE_24_11_paa),
.io_y_eff (_normal_entries_WIRE_24_11_eff),
.io_y_c (_normal_entries_WIRE_24_11_c),
.io_y_fragmented_superpage (_normal_entries_WIRE_24_11_fragmented_superpage)
); // @[package.scala:267:25]
assign io_resp_0_paddr = io_resp_0_paddr_0; // @[tlb.scala:17:7]
assign io_resp_0_pf_ld = io_resp_0_pf_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_pf_st = io_resp_0_pf_st_0; // @[tlb.scala:17:7]
assign io_resp_0_ae_ld = io_resp_0_ae_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_ae_st = io_resp_0_ae_st_0; // @[tlb.scala:17:7]
assign io_resp_0_ma_ld = io_resp_0_ma_ld_0; // @[tlb.scala:17:7]
assign io_resp_0_ma_st = io_resp_0_ma_st_0; // @[tlb.scala:17:7]
assign io_resp_0_cacheable = io_resp_0_cacheable_0; // @[tlb.scala:17:7]
assign io_ptw_req_bits_bits_addr = io_ptw_req_bits_bits_addr_0; // @[tlb.scala:17:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_36 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_26 = shr(io.in.a.bits.source, 4)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h1))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_32 = shr(io.in.a.bits.source, 4)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h0))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
node _source_ok_T_39 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[2])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[3])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[4])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[5])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[6])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_45, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<5>(0h10))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<5>(0h11))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<5>(0h12))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<5>(0h13))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_72 = shr(io.in.a.bits.source, 4)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_77 = and(_T_75, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_85 = shr(io.in.a.bits.source, 4)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_88 = and(_T_86, _T_87)
node _T_89 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = and(_T_11, _T_24)
node _T_107 = and(_T_106, _T_37)
node _T_108 = and(_T_107, _T_50)
node _T_109 = and(_T_108, _T_63)
node _T_110 = and(_T_109, _T_71)
node _T_111 = and(_T_110, _T_84)
node _T_112 = and(_T_111, _T_97)
node _T_113 = and(_T_112, _T_105)
node _T_114 = asUInt(reset)
node _T_115 = eq(_T_114, UInt<1>(0h0))
when _T_115 :
node _T_116 = eq(_T_113, UInt<1>(0h0))
when _T_116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_113, UInt<1>(0h1), "") : assert_1
node _T_117 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_117 :
node _T_118 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_119 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_122 = shr(io.in.a.bits.source, 2)
node _T_123 = eq(_T_122, UInt<5>(0h10))
node _T_124 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_125 = and(_T_123, _T_124)
node _T_126 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_127 = and(_T_125, _T_126)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_128 = shr(io.in.a.bits.source, 2)
node _T_129 = eq(_T_128, UInt<5>(0h11))
node _T_130 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_131 = and(_T_129, _T_130)
node _T_132 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_133 = and(_T_131, _T_132)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_134 = shr(io.in.a.bits.source, 2)
node _T_135 = eq(_T_134, UInt<5>(0h12))
node _T_136 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_137 = and(_T_135, _T_136)
node _T_138 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_139 = and(_T_137, _T_138)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<5>(0h13))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_147 = shr(io.in.a.bits.source, 4)
node _T_148 = eq(_T_147, UInt<1>(0h1))
node _T_149 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_150 = and(_T_148, _T_149)
node _T_151 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_152 = and(_T_150, _T_151)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_153 = shr(io.in.a.bits.source, 4)
node _T_154 = eq(_T_153, UInt<1>(0h0))
node _T_155 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_156 = and(_T_154, _T_155)
node _T_157 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_160 = or(_T_121, _T_127)
node _T_161 = or(_T_160, _T_133)
node _T_162 = or(_T_161, _T_139)
node _T_163 = or(_T_162, _T_145)
node _T_164 = or(_T_163, _T_146)
node _T_165 = or(_T_164, _T_152)
node _T_166 = or(_T_165, _T_158)
node _T_167 = or(_T_166, _T_159)
node _T_168 = and(_T_120, _T_167)
node _T_169 = or(UInt<1>(0h0), _T_168)
node _T_170 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<17>(0h10000)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_178 = cvt(_T_177)
node _T_179 = and(_T_178, asSInt(UInt<29>(0h10000000)))
node _T_180 = asSInt(_T_179)
node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0)))
node _T_182 = or(_T_176, _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = or(UInt<1>(0h0), _T_183)
node _T_185 = and(_T_169, _T_184)
node _T_186 = asUInt(reset)
node _T_187 = eq(_T_186, UInt<1>(0h0))
when _T_187 :
node _T_188 = eq(_T_185, UInt<1>(0h0))
when _T_188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_185, UInt<1>(0h1), "") : assert_2
node _T_189 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_190 = shr(io.in.a.bits.source, 2)
node _T_191 = eq(_T_190, UInt<5>(0h10))
node _T_192 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_193 = and(_T_191, _T_192)
node _T_194 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_195 = and(_T_193, _T_194)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_196 = shr(io.in.a.bits.source, 2)
node _T_197 = eq(_T_196, UInt<5>(0h11))
node _T_198 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_199 = and(_T_197, _T_198)
node _T_200 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_201 = and(_T_199, _T_200)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_202 = shr(io.in.a.bits.source, 2)
node _T_203 = eq(_T_202, UInt<5>(0h12))
node _T_204 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_205 = and(_T_203, _T_204)
node _T_206 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_207 = and(_T_205, _T_206)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_208 = shr(io.in.a.bits.source, 2)
node _T_209 = eq(_T_208, UInt<5>(0h13))
node _T_210 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_211 = and(_T_209, _T_210)
node _T_212 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_215 = shr(io.in.a.bits.source, 4)
node _T_216 = eq(_T_215, UInt<1>(0h1))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_221 = shr(io.in.a.bits.source, 4)
node _T_222 = eq(_T_221, UInt<1>(0h0))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_189
connect _WIRE[1], _T_195
connect _WIRE[2], _T_201
connect _WIRE[3], _T_207
connect _WIRE[4], _T_213
connect _WIRE[5], _T_214
connect _WIRE[6], _T_220
connect _WIRE[7], _T_226
connect _WIRE[8], _T_227
node _T_228 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_229 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_230 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_231 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_232 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_233 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = mux(_WIRE[5], _T_228, UInt<1>(0h0))
node _T_235 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_236 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_237 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_238 = or(_T_229, _T_230)
node _T_239 = or(_T_238, _T_231)
node _T_240 = or(_T_239, _T_232)
node _T_241 = or(_T_240, _T_233)
node _T_242 = or(_T_241, _T_234)
node _T_243 = or(_T_242, _T_235)
node _T_244 = or(_T_243, _T_236)
node _T_245 = or(_T_244, _T_237)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_245
node _T_246 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_247 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_248 = and(_T_246, _T_247)
node _T_249 = or(UInt<1>(0h0), _T_248)
node _T_250 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<17>(0h10000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<29>(0h10000000)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = or(_T_254, _T_259)
node _T_261 = and(_T_249, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = and(_WIRE_1, _T_262)
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_263, UInt<1>(0h1), "") : assert_3
node _T_267 = asUInt(reset)
node _T_268 = eq(_T_267, UInt<1>(0h0))
when _T_268 :
node _T_269 = eq(source_ok, UInt<1>(0h0))
when _T_269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_270 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_271 = asUInt(reset)
node _T_272 = eq(_T_271, UInt<1>(0h0))
when _T_272 :
node _T_273 = eq(_T_270, UInt<1>(0h0))
when _T_273 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_270, UInt<1>(0h1), "") : assert_5
node _T_274 = asUInt(reset)
node _T_275 = eq(_T_274, UInt<1>(0h0))
when _T_275 :
node _T_276 = eq(is_aligned, UInt<1>(0h0))
when _T_276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_277 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_277, UInt<1>(0h1), "") : assert_7
node _T_281 = not(io.in.a.bits.mask)
node _T_282 = eq(_T_281, UInt<1>(0h0))
node _T_283 = asUInt(reset)
node _T_284 = eq(_T_283, UInt<1>(0h0))
when _T_284 :
node _T_285 = eq(_T_282, UInt<1>(0h0))
when _T_285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_282, UInt<1>(0h1), "") : assert_8
node _T_286 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_287 = asUInt(reset)
node _T_288 = eq(_T_287, UInt<1>(0h0))
when _T_288 :
node _T_289 = eq(_T_286, UInt<1>(0h0))
when _T_289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_286, UInt<1>(0h1), "") : assert_9
node _T_290 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_290 :
node _T_291 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_292 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_295 = shr(io.in.a.bits.source, 2)
node _T_296 = eq(_T_295, UInt<5>(0h10))
node _T_297 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_298 = and(_T_296, _T_297)
node _T_299 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_300 = and(_T_298, _T_299)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_301 = shr(io.in.a.bits.source, 2)
node _T_302 = eq(_T_301, UInt<5>(0h11))
node _T_303 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_304 = and(_T_302, _T_303)
node _T_305 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_306 = and(_T_304, _T_305)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_307 = shr(io.in.a.bits.source, 2)
node _T_308 = eq(_T_307, UInt<5>(0h12))
node _T_309 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_310 = and(_T_308, _T_309)
node _T_311 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_312 = and(_T_310, _T_311)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_313 = shr(io.in.a.bits.source, 2)
node _T_314 = eq(_T_313, UInt<5>(0h13))
node _T_315 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_316 = and(_T_314, _T_315)
node _T_317 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_320 = shr(io.in.a.bits.source, 4)
node _T_321 = eq(_T_320, UInt<1>(0h1))
node _T_322 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_323 = and(_T_321, _T_322)
node _T_324 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_325 = and(_T_323, _T_324)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_326 = shr(io.in.a.bits.source, 4)
node _T_327 = eq(_T_326, UInt<1>(0h0))
node _T_328 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_329 = and(_T_327, _T_328)
node _T_330 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_333 = or(_T_294, _T_300)
node _T_334 = or(_T_333, _T_306)
node _T_335 = or(_T_334, _T_312)
node _T_336 = or(_T_335, _T_318)
node _T_337 = or(_T_336, _T_319)
node _T_338 = or(_T_337, _T_325)
node _T_339 = or(_T_338, _T_331)
node _T_340 = or(_T_339, _T_332)
node _T_341 = and(_T_293, _T_340)
node _T_342 = or(UInt<1>(0h0), _T_341)
node _T_343 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_344 = or(UInt<1>(0h0), _T_343)
node _T_345 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<17>(0h10000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_351 = cvt(_T_350)
node _T_352 = and(_T_351, asSInt(UInt<29>(0h10000000)))
node _T_353 = asSInt(_T_352)
node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0)))
node _T_355 = or(_T_349, _T_354)
node _T_356 = and(_T_344, _T_355)
node _T_357 = or(UInt<1>(0h0), _T_356)
node _T_358 = and(_T_342, _T_357)
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_T_358, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_358, UInt<1>(0h1), "") : assert_10
node _T_362 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<5>(0h10))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<5>(0h11))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<5>(0h12))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<5>(0h13))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_388 = shr(io.in.a.bits.source, 4)
node _T_389 = eq(_T_388, UInt<1>(0h1))
node _T_390 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_391 = and(_T_389, _T_390)
node _T_392 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_393 = and(_T_391, _T_392)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_394 = shr(io.in.a.bits.source, 4)
node _T_395 = eq(_T_394, UInt<1>(0h0))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_399 = and(_T_397, _T_398)
node _T_400 = eq(io.in.a.bits.source, UInt<6>(0h22))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_362
connect _WIRE_2[1], _T_368
connect _WIRE_2[2], _T_374
connect _WIRE_2[3], _T_380
connect _WIRE_2[4], _T_386
connect _WIRE_2[5], _T_387
connect _WIRE_2[6], _T_393
connect _WIRE_2[7], _T_399
connect _WIRE_2[8], _T_400
node _T_401 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_402 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_403 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_404 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_405 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_406 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_407 = mux(_WIRE_2[5], _T_401, UInt<1>(0h0))
node _T_408 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_410 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = or(_T_402, _T_403)
node _T_412 = or(_T_411, _T_404)
node _T_413 = or(_T_412, _T_405)
node _T_414 = or(_T_413, _T_406)
node _T_415 = or(_T_414, _T_407)
node _T_416 = or(_T_415, _T_408)
node _T_417 = or(_T_416, _T_409)
node _T_418 = or(_T_417, _T_410)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_418
node _T_419 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_420 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_421 = and(_T_419, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<17>(0h10000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<29>(0h10000000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = or(_T_427, _T_432)
node _T_434 = and(_T_422, _T_433)
node _T_435 = or(UInt<1>(0h0), _T_434)
node _T_436 = and(_WIRE_3, _T_435)
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_436, UInt<1>(0h1), "") : assert_11
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(source_ok, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_443 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_443, UInt<1>(0h1), "") : assert_13
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(is_aligned, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_450, UInt<1>(0h1), "") : assert_15
node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_454, UInt<1>(0h1), "") : assert_16
node _T_458 = not(io.in.a.bits.mask)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_459, UInt<1>(0h1), "") : assert_17
node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_463, UInt<1>(0h1), "") : assert_18
node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_467 :
node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_472 = shr(io.in.a.bits.source, 2)
node _T_473 = eq(_T_472, UInt<5>(0h10))
node _T_474 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_475 = and(_T_473, _T_474)
node _T_476 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_477 = and(_T_475, _T_476)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_478 = shr(io.in.a.bits.source, 2)
node _T_479 = eq(_T_478, UInt<5>(0h11))
node _T_480 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_481 = and(_T_479, _T_480)
node _T_482 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_483 = and(_T_481, _T_482)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<5>(0h12))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<5>(0h13))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_497 = shr(io.in.a.bits.source, 4)
node _T_498 = eq(_T_497, UInt<1>(0h1))
node _T_499 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_500 = and(_T_498, _T_499)
node _T_501 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_502 = and(_T_500, _T_501)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_503 = shr(io.in.a.bits.source, 4)
node _T_504 = eq(_T_503, UInt<1>(0h0))
node _T_505 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_506 = and(_T_504, _T_505)
node _T_507 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_510 = or(_T_471, _T_477)
node _T_511 = or(_T_510, _T_483)
node _T_512 = or(_T_511, _T_489)
node _T_513 = or(_T_512, _T_495)
node _T_514 = or(_T_513, _T_496)
node _T_515 = or(_T_514, _T_502)
node _T_516 = or(_T_515, _T_508)
node _T_517 = or(_T_516, _T_509)
node _T_518 = and(_T_470, _T_517)
node _T_519 = or(UInt<1>(0h0), _T_518)
node _T_520 = asUInt(reset)
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(_T_519, UInt<1>(0h0))
when _T_522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_519, UInt<1>(0h1), "") : assert_19
node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_524 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_525 = and(_T_523, _T_524)
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<17>(0h10000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_533 = cvt(_T_532)
node _T_534 = and(_T_533, asSInt(UInt<29>(0h10000000)))
node _T_535 = asSInt(_T_534)
node _T_536 = eq(_T_535, asSInt(UInt<1>(0h0)))
node _T_537 = or(_T_531, _T_536)
node _T_538 = and(_T_526, _T_537)
node _T_539 = or(UInt<1>(0h0), _T_538)
node _T_540 = asUInt(reset)
node _T_541 = eq(_T_540, UInt<1>(0h0))
when _T_541 :
node _T_542 = eq(_T_539, UInt<1>(0h0))
when _T_542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_539, UInt<1>(0h1), "") : assert_20
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(source_ok, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(is_aligned, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_549 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_549, UInt<1>(0h1), "") : assert_23
node _T_553 = eq(io.in.a.bits.mask, mask)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_553, UInt<1>(0h1), "") : assert_24
node _T_557 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_558 = asUInt(reset)
node _T_559 = eq(_T_558, UInt<1>(0h0))
when _T_559 :
node _T_560 = eq(_T_557, UInt<1>(0h0))
when _T_560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_557, UInt<1>(0h1), "") : assert_25
node _T_561 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_561 :
node _T_562 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_563 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_566 = shr(io.in.a.bits.source, 2)
node _T_567 = eq(_T_566, UInt<5>(0h10))
node _T_568 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_569 = and(_T_567, _T_568)
node _T_570 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_571 = and(_T_569, _T_570)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_572 = shr(io.in.a.bits.source, 2)
node _T_573 = eq(_T_572, UInt<5>(0h11))
node _T_574 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_575 = and(_T_573, _T_574)
node _T_576 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_577 = and(_T_575, _T_576)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_578 = shr(io.in.a.bits.source, 2)
node _T_579 = eq(_T_578, UInt<5>(0h12))
node _T_580 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_581 = and(_T_579, _T_580)
node _T_582 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_583 = and(_T_581, _T_582)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_584 = shr(io.in.a.bits.source, 2)
node _T_585 = eq(_T_584, UInt<5>(0h13))
node _T_586 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_587 = and(_T_585, _T_586)
node _T_588 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_589 = and(_T_587, _T_588)
node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_591 = shr(io.in.a.bits.source, 4)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_597 = shr(io.in.a.bits.source, 4)
node _T_598 = eq(_T_597, UInt<1>(0h0))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_602 = and(_T_600, _T_601)
node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_604 = or(_T_565, _T_571)
node _T_605 = or(_T_604, _T_577)
node _T_606 = or(_T_605, _T_583)
node _T_607 = or(_T_606, _T_589)
node _T_608 = or(_T_607, _T_590)
node _T_609 = or(_T_608, _T_596)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_603)
node _T_612 = and(_T_564, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<17>(0h10000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<29>(0h10000000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = or(_T_622, _T_627)
node _T_629 = and(_T_617, _T_628)
node _T_630 = or(UInt<1>(0h0), _T_629)
node _T_631 = and(_T_613, _T_630)
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(_T_631, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_631, UInt<1>(0h1), "") : assert_26
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(source_ok, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(is_aligned, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_641 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(_T_641, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_641, UInt<1>(0h1), "") : assert_29
node _T_645 = eq(io.in.a.bits.mask, mask)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_645, UInt<1>(0h1), "") : assert_30
node _T_649 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_649 :
node _T_650 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_651 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_652 = and(_T_650, _T_651)
node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_654 = shr(io.in.a.bits.source, 2)
node _T_655 = eq(_T_654, UInt<5>(0h10))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<5>(0h11))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<5>(0h12))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<5>(0h13))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_679 = shr(io.in.a.bits.source, 4)
node _T_680 = eq(_T_679, UInt<1>(0h1))
node _T_681 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_682 = and(_T_680, _T_681)
node _T_683 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_684 = and(_T_682, _T_683)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_685 = shr(io.in.a.bits.source, 4)
node _T_686 = eq(_T_685, UInt<1>(0h0))
node _T_687 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_688 = and(_T_686, _T_687)
node _T_689 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_690 = and(_T_688, _T_689)
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_692 = or(_T_653, _T_659)
node _T_693 = or(_T_692, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_678)
node _T_697 = or(_T_696, _T_684)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = and(_T_652, _T_699)
node _T_701 = or(UInt<1>(0h0), _T_700)
node _T_702 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_703 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_704 = and(_T_702, _T_703)
node _T_705 = or(UInt<1>(0h0), _T_704)
node _T_706 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<29>(0h10000000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = or(_T_710, _T_715)
node _T_717 = and(_T_705, _T_716)
node _T_718 = or(UInt<1>(0h0), _T_717)
node _T_719 = and(_T_701, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_719, UInt<1>(0h1), "") : assert_31
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(source_ok, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(is_aligned, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_729 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_730 = asUInt(reset)
node _T_731 = eq(_T_730, UInt<1>(0h0))
when _T_731 :
node _T_732 = eq(_T_729, UInt<1>(0h0))
when _T_732 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_729, UInt<1>(0h1), "") : assert_34
node _T_733 = not(mask)
node _T_734 = and(io.in.a.bits.mask, _T_733)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_735, UInt<1>(0h1), "") : assert_35
node _T_739 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_739 :
node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_741 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_744 = shr(io.in.a.bits.source, 2)
node _T_745 = eq(_T_744, UInt<5>(0h10))
node _T_746 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_747 = and(_T_745, _T_746)
node _T_748 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_749 = and(_T_747, _T_748)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<5>(0h11))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<5>(0h12))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<5>(0h13))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_769 = shr(io.in.a.bits.source, 4)
node _T_770 = eq(_T_769, UInt<1>(0h1))
node _T_771 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_772 = and(_T_770, _T_771)
node _T_773 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_774 = and(_T_772, _T_773)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_775 = shr(io.in.a.bits.source, 4)
node _T_776 = eq(_T_775, UInt<1>(0h0))
node _T_777 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_778 = and(_T_776, _T_777)
node _T_779 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_782 = or(_T_743, _T_749)
node _T_783 = or(_T_782, _T_755)
node _T_784 = or(_T_783, _T_761)
node _T_785 = or(_T_784, _T_767)
node _T_786 = or(_T_785, _T_768)
node _T_787 = or(_T_786, _T_774)
node _T_788 = or(_T_787, _T_780)
node _T_789 = or(_T_788, _T_781)
node _T_790 = and(_T_742, _T_789)
node _T_791 = or(UInt<1>(0h0), _T_790)
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_794 = and(_T_792, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_797 = cvt(_T_796)
node _T_798 = and(_T_797, asSInt(UInt<17>(0h10000)))
node _T_799 = asSInt(_T_798)
node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0)))
node _T_801 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_802 = cvt(_T_801)
node _T_803 = and(_T_802, asSInt(UInt<29>(0h10000000)))
node _T_804 = asSInt(_T_803)
node _T_805 = eq(_T_804, asSInt(UInt<1>(0h0)))
node _T_806 = or(_T_800, _T_805)
node _T_807 = and(_T_795, _T_806)
node _T_808 = or(UInt<1>(0h0), _T_807)
node _T_809 = and(_T_791, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_809, UInt<1>(0h1), "") : assert_36
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_819 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_819, UInt<1>(0h1), "") : assert_39
node _T_823 = eq(io.in.a.bits.mask, mask)
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_823, UInt<1>(0h1), "") : assert_40
node _T_827 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_827 :
node _T_828 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_829 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<5>(0h10))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_838 = shr(io.in.a.bits.source, 2)
node _T_839 = eq(_T_838, UInt<5>(0h11))
node _T_840 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_841 = and(_T_839, _T_840)
node _T_842 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_843 = and(_T_841, _T_842)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_844 = shr(io.in.a.bits.source, 2)
node _T_845 = eq(_T_844, UInt<5>(0h12))
node _T_846 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_847 = and(_T_845, _T_846)
node _T_848 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_849 = and(_T_847, _T_848)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_850 = shr(io.in.a.bits.source, 2)
node _T_851 = eq(_T_850, UInt<5>(0h13))
node _T_852 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_853 = and(_T_851, _T_852)
node _T_854 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_855 = and(_T_853, _T_854)
node _T_856 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_857 = shr(io.in.a.bits.source, 4)
node _T_858 = eq(_T_857, UInt<1>(0h1))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_863 = shr(io.in.a.bits.source, 4)
node _T_864 = eq(_T_863, UInt<1>(0h0))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_868 = and(_T_866, _T_867)
node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_870 = or(_T_831, _T_837)
node _T_871 = or(_T_870, _T_843)
node _T_872 = or(_T_871, _T_849)
node _T_873 = or(_T_872, _T_855)
node _T_874 = or(_T_873, _T_856)
node _T_875 = or(_T_874, _T_862)
node _T_876 = or(_T_875, _T_868)
node _T_877 = or(_T_876, _T_869)
node _T_878 = and(_T_830, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_882 = and(_T_880, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_882)
node _T_884 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<29>(0h10000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = or(_T_888, _T_893)
node _T_895 = and(_T_883, _T_894)
node _T_896 = or(UInt<1>(0h0), _T_895)
node _T_897 = and(_T_879, _T_896)
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_897, UInt<1>(0h1), "") : assert_41
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(source_ok, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(is_aligned, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_907 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_907, UInt<1>(0h1), "") : assert_44
node _T_911 = eq(io.in.a.bits.mask, mask)
node _T_912 = asUInt(reset)
node _T_913 = eq(_T_912, UInt<1>(0h0))
when _T_913 :
node _T_914 = eq(_T_911, UInt<1>(0h0))
when _T_914 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_911, UInt<1>(0h1), "") : assert_45
node _T_915 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_915 :
node _T_916 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_917 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_918 = and(_T_916, _T_917)
node _T_919 = eq(io.in.a.bits.source, UInt<7>(0h50))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_920 = shr(io.in.a.bits.source, 2)
node _T_921 = eq(_T_920, UInt<5>(0h10))
node _T_922 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_923 = and(_T_921, _T_922)
node _T_924 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_925 = and(_T_923, _T_924)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<5>(0h11))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<5>(0h12))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<5>(0h13))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _T_944 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_945 = shr(io.in.a.bits.source, 4)
node _T_946 = eq(_T_945, UInt<1>(0h1))
node _T_947 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_948 = and(_T_946, _T_947)
node _T_949 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_951 = shr(io.in.a.bits.source, 4)
node _T_952 = eq(_T_951, UInt<1>(0h0))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_958 = or(_T_919, _T_925)
node _T_959 = or(_T_958, _T_931)
node _T_960 = or(_T_959, _T_937)
node _T_961 = or(_T_960, _T_943)
node _T_962 = or(_T_961, _T_944)
node _T_963 = or(_T_962, _T_950)
node _T_964 = or(_T_963, _T_956)
node _T_965 = or(_T_964, _T_957)
node _T_966 = and(_T_918, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<17>(0h10000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<29>(0h10000000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = or(_T_976, _T_981)
node _T_983 = and(_T_971, _T_982)
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = and(_T_967, _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_985, UInt<1>(0h1), "") : assert_46
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(source_ok, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(is_aligned, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_995 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_995, UInt<1>(0h1), "") : assert_49
node _T_999 = eq(io.in.a.bits.mask, mask)
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_999, UInt<1>(0h1), "") : assert_50
node _T_1003 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1007 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_52
node _source_ok_T_46 = eq(io.in.d.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<5>(0h10))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_53 = shr(io.in.d.bits.source, 2)
node _source_ok_T_54 = eq(_source_ok_T_53, UInt<5>(0h11))
node _source_ok_T_55 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<5>(0h12))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<5>(0h13))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_72 = shr(io.in.d.bits.source, 4)
node _source_ok_T_73 = eq(_source_ok_T_72, UInt<1>(0h1))
node _source_ok_T_74 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_77 = and(_source_ok_T_75, _source_ok_T_76)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_78 = shr(io.in.d.bits.source, 4)
node _source_ok_T_79 = eq(_source_ok_T_78, UInt<1>(0h0))
node _source_ok_T_80 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_T_82 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_83 = and(_source_ok_T_81, _source_ok_T_82)
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_46
connect _source_ok_WIRE_1[1], _source_ok_T_52
connect _source_ok_WIRE_1[2], _source_ok_T_58
connect _source_ok_WIRE_1[3], _source_ok_T_64
connect _source_ok_WIRE_1[4], _source_ok_T_70
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_77
connect _source_ok_WIRE_1[7], _source_ok_T_83
connect _source_ok_WIRE_1[8], _source_ok_T_84
node _source_ok_T_85 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE_1[2])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE_1[3])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE_1[4])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE_1[5])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE_1[6])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_91, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0hc))
node _T_1011 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1011 :
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(source_ok_1, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1015 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_54
node _T_1019 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_55
node _T_1023 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1024 = asUInt(reset)
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(_T_1023, UInt<1>(0h0))
when _T_1026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1023, UInt<1>(0h1), "") : assert_56
node _T_1027 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1028 = asUInt(reset)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
when _T_1029 :
node _T_1030 = eq(_T_1027, UInt<1>(0h0))
when _T_1030 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1027, UInt<1>(0h1), "") : assert_57
node _T_1031 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1031 :
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(source_ok_1, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(sink_ok, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1038 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_60
node _T_1042 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1043 = asUInt(reset)
node _T_1044 = eq(_T_1043, UInt<1>(0h0))
when _T_1044 :
node _T_1045 = eq(_T_1042, UInt<1>(0h0))
when _T_1045 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1042, UInt<1>(0h1), "") : assert_61
node _T_1046 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_62
node _T_1050 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_63
node _T_1054 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1055 = or(UInt<1>(0h1), _T_1054)
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(_T_1055, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1055, UInt<1>(0h1), "") : assert_64
node _T_1059 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1059 :
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(source_ok_1, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(sink_ok, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1066 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(_T_1066, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1066, UInt<1>(0h1), "") : assert_67
node _T_1070 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_68
node _T_1074 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_69
node _T_1078 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1079 = or(_T_1078, io.in.d.bits.corrupt)
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(_T_1079, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1079, UInt<1>(0h1), "") : assert_70
node _T_1083 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1084 = or(UInt<1>(0h1), _T_1083)
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_71
node _T_1088 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(source_ok_1, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1092 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_73
node _T_1096 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_74
node _T_1100 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1101 = or(UInt<1>(0h1), _T_1100)
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_75
node _T_1105 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1105 :
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok_1, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1109 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_77
node _T_1113 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1114 = or(_T_1113, io.in.d.bits.corrupt)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_78
node _T_1118 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1119 = or(UInt<1>(0h1), _T_1118)
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_79
node _T_1123 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1123 :
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(source_ok_1, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1127 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_81
node _T_1131 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_82
node _T_1135 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1136 = or(UInt<1>(0h1), _T_1135)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1140 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(_T_1140, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1140, UInt<1>(0h1), "") : assert_84
node _T_1144 = eq(io.in.b.bits.source, UInt<7>(0h50))
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
node _T_1146 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1147 = cvt(_T_1146)
node _T_1148 = and(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = asSInt(_T_1148)
node _T_1150 = eq(_T_1149, asSInt(UInt<1>(0h0)))
node _T_1151 = or(_T_1145, _T_1150)
node _uncommonBits_T_66 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_1152 = shr(io.in.b.bits.source, 2)
node _T_1153 = eq(_T_1152, UInt<5>(0h10))
node _T_1154 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
node _T_1159 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1160 = cvt(_T_1159)
node _T_1161 = and(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = asSInt(_T_1161)
node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0)))
node _T_1164 = or(_T_1158, _T_1163)
node _uncommonBits_T_67 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 1, 0)
node _T_1165 = shr(io.in.b.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<5>(0h11))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_67, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
node _T_1172 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1173 = cvt(_T_1172)
node _T_1174 = and(_T_1173, asSInt(UInt<1>(0h0)))
node _T_1175 = asSInt(_T_1174)
node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0)))
node _T_1177 = or(_T_1171, _T_1176)
node _uncommonBits_T_68 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 1, 0)
node _T_1178 = shr(io.in.b.bits.source, 2)
node _T_1179 = eq(_T_1178, UInt<5>(0h12))
node _T_1180 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_1181 = and(_T_1179, _T_1180)
node _T_1182 = leq(uncommonBits_68, UInt<2>(0h3))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
node _T_1185 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<1>(0h0)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = or(_T_1184, _T_1189)
node _uncommonBits_T_69 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 1, 0)
node _T_1191 = shr(io.in.b.bits.source, 2)
node _T_1192 = eq(_T_1191, UInt<5>(0h13))
node _T_1193 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_1194 = and(_T_1192, _T_1193)
node _T_1195 = leq(uncommonBits_69, UInt<2>(0h3))
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
node _T_1198 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1199 = cvt(_T_1198)
node _T_1200 = and(_T_1199, asSInt(UInt<1>(0h0)))
node _T_1201 = asSInt(_T_1200)
node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0)))
node _T_1203 = or(_T_1197, _T_1202)
node _T_1204 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
node _T_1206 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1207 = cvt(_T_1206)
node _T_1208 = and(_T_1207, asSInt(UInt<1>(0h0)))
node _T_1209 = asSInt(_T_1208)
node _T_1210 = eq(_T_1209, asSInt(UInt<1>(0h0)))
node _T_1211 = or(_T_1205, _T_1210)
node _uncommonBits_T_70 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 3, 0)
node _T_1212 = shr(io.in.b.bits.source, 4)
node _T_1213 = eq(_T_1212, UInt<1>(0h1))
node _T_1214 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_1215 = and(_T_1213, _T_1214)
node _T_1216 = leq(uncommonBits_70, UInt<4>(0hf))
node _T_1217 = and(_T_1215, _T_1216)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
node _T_1219 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1220 = cvt(_T_1219)
node _T_1221 = and(_T_1220, asSInt(UInt<1>(0h0)))
node _T_1222 = asSInt(_T_1221)
node _T_1223 = eq(_T_1222, asSInt(UInt<1>(0h0)))
node _T_1224 = or(_T_1218, _T_1223)
node _uncommonBits_T_71 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 3, 0)
node _T_1225 = shr(io.in.b.bits.source, 4)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
node _T_1227 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = leq(uncommonBits_71, UInt<4>(0hf))
node _T_1230 = and(_T_1228, _T_1229)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
node _T_1232 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1233 = cvt(_T_1232)
node _T_1234 = and(_T_1233, asSInt(UInt<1>(0h0)))
node _T_1235 = asSInt(_T_1234)
node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0)))
node _T_1237 = or(_T_1231, _T_1236)
node _T_1238 = eq(io.in.b.bits.source, UInt<6>(0h22))
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
node _T_1240 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = or(_T_1239, _T_1244)
node _T_1246 = and(_T_1151, _T_1164)
node _T_1247 = and(_T_1246, _T_1177)
node _T_1248 = and(_T_1247, _T_1190)
node _T_1249 = and(_T_1248, _T_1203)
node _T_1250 = and(_T_1249, _T_1211)
node _T_1251 = and(_T_1250, _T_1224)
node _T_1252 = and(_T_1251, _T_1237)
node _T_1253 = and(_T_1252, _T_1245)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[2]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3)
node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3)
node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1)
node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1)
node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2)
node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1)
node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1)
node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3)
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4)
node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5)
node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1)
node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6)
node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1)
node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11)
node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1)
node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12)
node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1)
node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13)
node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1)
node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14)
node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1)
node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_16 = and(mask_size_1, mask_eq_16)
node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16)
node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_17 = and(mask_size_1, mask_eq_17)
node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17)
node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_18 = and(mask_size_1, mask_eq_18)
node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18)
node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_19 = and(mask_size_1, mask_eq_19)
node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19)
node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_20 = and(mask_size_1, mask_eq_20)
node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20)
node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_21 = and(mask_size_1, mask_eq_21)
node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21)
node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_22 = and(mask_size_1, mask_eq_22)
node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22)
node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_23 = and(mask_size_1, mask_eq_23)
node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23)
node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1)
node _mask_acc_T_24 = and(mask_size_1, mask_eq_24)
node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24)
node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1)
node _mask_acc_T_25 = and(mask_size_1, mask_eq_25)
node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25)
node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1)
node _mask_acc_T_26 = and(mask_size_1, mask_eq_26)
node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26)
node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1)
node _mask_acc_T_27 = and(mask_size_1, mask_eq_27)
node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27)
node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1)
node _mask_acc_T_28 = and(mask_size_1, mask_eq_28)
node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28)
node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1)
node _mask_acc_T_29 = and(mask_size_1, mask_eq_29)
node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29)
node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1)
node _mask_acc_T_30 = and(mask_size_1, mask_eq_30)
node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30)
node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1)
node _mask_acc_T_31 = and(mask_size_1, mask_eq_31)
node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31)
node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16)
node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18)
node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1)
node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20)
node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22)
node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24)
node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26)
node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1)
node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28)
node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30)
node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<7>(0h50))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<5>(0h10))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_uncommonBits_T_1 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_1 = bits(_legal_source_uncommonBits_T_1, 1, 0)
node _legal_source_T_7 = shr(io.in.b.bits.source, 2)
node _legal_source_T_8 = eq(_legal_source_T_7, UInt<5>(0h11))
node _legal_source_T_9 = leq(UInt<1>(0h0), legal_source_uncommonBits_1)
node _legal_source_T_10 = and(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_11 = leq(legal_source_uncommonBits_1, UInt<2>(0h3))
node _legal_source_T_12 = and(_legal_source_T_10, _legal_source_T_11)
node _legal_source_uncommonBits_T_2 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_2 = bits(_legal_source_uncommonBits_T_2, 1, 0)
node _legal_source_T_13 = shr(io.in.b.bits.source, 2)
node _legal_source_T_14 = eq(_legal_source_T_13, UInt<5>(0h12))
node _legal_source_T_15 = leq(UInt<1>(0h0), legal_source_uncommonBits_2)
node _legal_source_T_16 = and(_legal_source_T_14, _legal_source_T_15)
node _legal_source_T_17 = leq(legal_source_uncommonBits_2, UInt<2>(0h3))
node _legal_source_T_18 = and(_legal_source_T_16, _legal_source_T_17)
node _legal_source_uncommonBits_T_3 = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits_3 = bits(_legal_source_uncommonBits_T_3, 1, 0)
node _legal_source_T_19 = shr(io.in.b.bits.source, 2)
node _legal_source_T_20 = eq(_legal_source_T_19, UInt<5>(0h13))
node _legal_source_T_21 = leq(UInt<1>(0h0), legal_source_uncommonBits_3)
node _legal_source_T_22 = and(_legal_source_T_20, _legal_source_T_21)
node _legal_source_T_23 = leq(legal_source_uncommonBits_3, UInt<2>(0h3))
node _legal_source_T_24 = and(_legal_source_T_22, _legal_source_T_23)
node _legal_source_T_25 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _legal_source_uncommonBits_T_4 = or(io.in.b.bits.source, UInt<4>(0h0))
node legal_source_uncommonBits_4 = bits(_legal_source_uncommonBits_T_4, 3, 0)
node _legal_source_T_26 = shr(io.in.b.bits.source, 4)
node _legal_source_T_27 = eq(_legal_source_T_26, UInt<1>(0h1))
node _legal_source_T_28 = leq(UInt<1>(0h0), legal_source_uncommonBits_4)
node _legal_source_T_29 = and(_legal_source_T_27, _legal_source_T_28)
node _legal_source_T_30 = leq(legal_source_uncommonBits_4, UInt<4>(0hf))
node _legal_source_T_31 = and(_legal_source_T_29, _legal_source_T_30)
node _legal_source_uncommonBits_T_5 = or(io.in.b.bits.source, UInt<4>(0h0))
node legal_source_uncommonBits_5 = bits(_legal_source_uncommonBits_T_5, 3, 0)
node _legal_source_T_32 = shr(io.in.b.bits.source, 4)
node _legal_source_T_33 = eq(_legal_source_T_32, UInt<1>(0h0))
node _legal_source_T_34 = leq(UInt<1>(0h0), legal_source_uncommonBits_5)
node _legal_source_T_35 = and(_legal_source_T_33, _legal_source_T_34)
node _legal_source_T_36 = leq(legal_source_uncommonBits_5, UInt<4>(0hf))
node _legal_source_T_37 = and(_legal_source_T_35, _legal_source_T_36)
node _legal_source_T_38 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _legal_source_WIRE : UInt<1>[9]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_12
connect _legal_source_WIRE[3], _legal_source_T_18
connect _legal_source_WIRE[4], _legal_source_T_24
connect _legal_source_WIRE[5], _legal_source_T_25
connect _legal_source_WIRE[6], _legal_source_T_31
connect _legal_source_WIRE[7], _legal_source_T_37
connect _legal_source_WIRE[8], _legal_source_T_38
node _legal_source_T_39 = mux(_legal_source_WIRE[0], UInt<7>(0h50), UInt<1>(0h0))
node _legal_source_T_40 = mux(_legal_source_WIRE[1], UInt<7>(0h40), UInt<1>(0h0))
node _legal_source_T_41 = mux(_legal_source_WIRE[2], UInt<7>(0h44), UInt<1>(0h0))
node _legal_source_T_42 = mux(_legal_source_WIRE[3], UInt<7>(0h48), UInt<1>(0h0))
node _legal_source_T_43 = mux(_legal_source_WIRE[4], UInt<7>(0h4c), UInt<1>(0h0))
node _legal_source_T_44 = mux(_legal_source_WIRE[5], UInt<6>(0h20), UInt<1>(0h0))
node _legal_source_T_45 = mux(_legal_source_WIRE[6], UInt<5>(0h10), UInt<1>(0h0))
node _legal_source_T_46 = mux(_legal_source_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_47 = mux(_legal_source_WIRE[8], UInt<6>(0h22), UInt<1>(0h0))
node _legal_source_T_48 = or(_legal_source_T_39, _legal_source_T_40)
node _legal_source_T_49 = or(_legal_source_T_48, _legal_source_T_41)
node _legal_source_T_50 = or(_legal_source_T_49, _legal_source_T_42)
node _legal_source_T_51 = or(_legal_source_T_50, _legal_source_T_43)
node _legal_source_T_52 = or(_legal_source_T_51, _legal_source_T_44)
node _legal_source_T_53 = or(_legal_source_T_52, _legal_source_T_45)
node _legal_source_T_54 = or(_legal_source_T_53, _legal_source_T_46)
node _legal_source_T_55 = or(_legal_source_T_54, _legal_source_T_47)
wire _legal_source_WIRE_1 : UInt<7>
connect _legal_source_WIRE_1, _legal_source_T_55
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1257 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1257 :
node _T_1258 = eq(io.in.b.bits.source, UInt<7>(0h50))
node _uncommonBits_T_72 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_1259 = shr(io.in.b.bits.source, 2)
node _T_1260 = eq(_T_1259, UInt<5>(0h10))
node _T_1261 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_1262 = and(_T_1260, _T_1261)
node _T_1263 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_1264 = and(_T_1262, _T_1263)
node _uncommonBits_T_73 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_1265 = shr(io.in.b.bits.source, 2)
node _T_1266 = eq(_T_1265, UInt<5>(0h11))
node _T_1267 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_1270 = and(_T_1268, _T_1269)
node _uncommonBits_T_74 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_1271 = shr(io.in.b.bits.source, 2)
node _T_1272 = eq(_T_1271, UInt<5>(0h12))
node _T_1273 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_1276 = and(_T_1274, _T_1275)
node _uncommonBits_T_75 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_1277 = shr(io.in.b.bits.source, 2)
node _T_1278 = eq(_T_1277, UInt<5>(0h13))
node _T_1279 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1280 = and(_T_1278, _T_1279)
node _T_1281 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_1282 = and(_T_1280, _T_1281)
node _T_1283 = eq(io.in.b.bits.source, UInt<6>(0h20))
node _uncommonBits_T_76 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 3, 0)
node _T_1284 = shr(io.in.b.bits.source, 4)
node _T_1285 = eq(_T_1284, UInt<1>(0h1))
node _T_1286 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1287 = and(_T_1285, _T_1286)
node _T_1288 = leq(uncommonBits_76, UInt<4>(0hf))
node _T_1289 = and(_T_1287, _T_1288)
node _uncommonBits_T_77 = or(io.in.b.bits.source, UInt<4>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 3, 0)
node _T_1290 = shr(io.in.b.bits.source, 4)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
node _T_1292 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_1293 = and(_T_1291, _T_1292)
node _T_1294 = leq(uncommonBits_77, UInt<4>(0hf))
node _T_1295 = and(_T_1293, _T_1294)
node _T_1296 = eq(io.in.b.bits.source, UInt<6>(0h22))
wire _WIRE_4 : UInt<1>[9]
connect _WIRE_4[0], _T_1258
connect _WIRE_4[1], _T_1264
connect _WIRE_4[2], _T_1270
connect _WIRE_4[3], _T_1276
connect _WIRE_4[4], _T_1282
connect _WIRE_4[5], _T_1283
connect _WIRE_4[6], _T_1289
connect _WIRE_4[7], _T_1295
connect _WIRE_4[8], _T_1296
node _T_1297 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1298 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1299 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1300 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1301 = mux(_WIRE_4[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1302 = mux(_WIRE_4[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1303 = mux(_WIRE_4[5], _T_1297, UInt<1>(0h0))
node _T_1304 = mux(_WIRE_4[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1305 = mux(_WIRE_4[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1306 = mux(_WIRE_4[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1307 = or(_T_1298, _T_1299)
node _T_1308 = or(_T_1307, _T_1300)
node _T_1309 = or(_T_1308, _T_1301)
node _T_1310 = or(_T_1309, _T_1302)
node _T_1311 = or(_T_1310, _T_1303)
node _T_1312 = or(_T_1311, _T_1304)
node _T_1313 = or(_T_1312, _T_1305)
node _T_1314 = or(_T_1313, _T_1306)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1314
node _T_1315 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1316 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1317 = and(_T_1315, _T_1316)
node _T_1318 = or(UInt<1>(0h0), _T_1317)
node _T_1319 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1320 = cvt(_T_1319)
node _T_1321 = and(_T_1320, asSInt(UInt<17>(0h10000)))
node _T_1322 = asSInt(_T_1321)
node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0)))
node _T_1324 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<29>(0h10000000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = or(_T_1323, _T_1328)
node _T_1330 = and(_T_1318, _T_1329)
node _T_1331 = or(UInt<1>(0h0), _T_1330)
node _T_1332 = and(_WIRE_5, _T_1331)
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_86
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(address_ok, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1339 = asUInt(reset)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
when _T_1340 :
node _T_1341 = eq(legal_source, UInt<1>(0h0))
when _T_1341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1345 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1346 = asUInt(reset)
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
when _T_1347 :
node _T_1348 = eq(_T_1345, UInt<1>(0h0))
when _T_1348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1345, UInt<1>(0h1), "") : assert_90
node _T_1349 = eq(io.in.b.bits.mask, mask_1)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_91
node _T_1353 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_92
node _T_1357 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1357 :
node _T_1358 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1359 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1360 = and(_T_1358, _T_1359)
node _T_1361 = or(UInt<1>(0h0), _T_1360)
node _T_1362 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1363 = cvt(_T_1362)
node _T_1364 = and(_T_1363, asSInt(UInt<17>(0h10000)))
node _T_1365 = asSInt(_T_1364)
node _T_1366 = eq(_T_1365, asSInt(UInt<1>(0h0)))
node _T_1367 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1368 = cvt(_T_1367)
node _T_1369 = and(_T_1368, asSInt(UInt<29>(0h10000000)))
node _T_1370 = asSInt(_T_1369)
node _T_1371 = eq(_T_1370, asSInt(UInt<1>(0h0)))
node _T_1372 = or(_T_1366, _T_1371)
node _T_1373 = and(_T_1361, _T_1372)
node _T_1374 = or(UInt<1>(0h0), _T_1373)
node _T_1375 = and(UInt<1>(0h0), _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_93
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(address_ok, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(legal_source, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1388 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(_T_1388, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1388, UInt<1>(0h1), "") : assert_97
node _T_1392 = eq(io.in.b.bits.mask, mask_1)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_98
node _T_1396 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_99
node _T_1400 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1402 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1403 = and(_T_1401, _T_1402)
node _T_1404 = or(UInt<1>(0h0), _T_1403)
node _T_1405 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1406 = cvt(_T_1405)
node _T_1407 = and(_T_1406, asSInt(UInt<17>(0h10000)))
node _T_1408 = asSInt(_T_1407)
node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0)))
node _T_1410 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1411 = cvt(_T_1410)
node _T_1412 = and(_T_1411, asSInt(UInt<29>(0h10000000)))
node _T_1413 = asSInt(_T_1412)
node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0)))
node _T_1415 = or(_T_1409, _T_1414)
node _T_1416 = and(_T_1404, _T_1415)
node _T_1417 = or(UInt<1>(0h0), _T_1416)
node _T_1418 = and(UInt<1>(0h0), _T_1417)
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_100
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(address_ok, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1425 = asUInt(reset)
node _T_1426 = eq(_T_1425, UInt<1>(0h0))
when _T_1426 :
node _T_1427 = eq(legal_source, UInt<1>(0h0))
when _T_1427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1431 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_104
node _T_1435 = eq(io.in.b.bits.mask, mask_1)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_105
node _T_1439 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1439 :
node _T_1440 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1441 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1442 = and(_T_1440, _T_1441)
node _T_1443 = or(UInt<1>(0h0), _T_1442)
node _T_1444 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1445 = cvt(_T_1444)
node _T_1446 = and(_T_1445, asSInt(UInt<17>(0h10000)))
node _T_1447 = asSInt(_T_1446)
node _T_1448 = eq(_T_1447, asSInt(UInt<1>(0h0)))
node _T_1449 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1450 = cvt(_T_1449)
node _T_1451 = and(_T_1450, asSInt(UInt<29>(0h10000000)))
node _T_1452 = asSInt(_T_1451)
node _T_1453 = eq(_T_1452, asSInt(UInt<1>(0h0)))
node _T_1454 = or(_T_1448, _T_1453)
node _T_1455 = and(_T_1443, _T_1454)
node _T_1456 = or(UInt<1>(0h0), _T_1455)
node _T_1457 = and(UInt<1>(0h0), _T_1456)
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_106
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(address_ok, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(legal_source, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1467 = asUInt(reset)
node _T_1468 = eq(_T_1467, UInt<1>(0h0))
when _T_1468 :
node _T_1469 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1470 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1471 = asUInt(reset)
node _T_1472 = eq(_T_1471, UInt<1>(0h0))
when _T_1472 :
node _T_1473 = eq(_T_1470, UInt<1>(0h0))
when _T_1473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1470, UInt<1>(0h1), "") : assert_110
node _T_1474 = not(mask_1)
node _T_1475 = and(io.in.b.bits.mask, _T_1474)
node _T_1476 = eq(_T_1475, UInt<1>(0h0))
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_111
node _T_1480 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1480 :
node _T_1481 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1482 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1483 = and(_T_1481, _T_1482)
node _T_1484 = or(UInt<1>(0h0), _T_1483)
node _T_1485 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1486 = cvt(_T_1485)
node _T_1487 = and(_T_1486, asSInt(UInt<17>(0h10000)))
node _T_1488 = asSInt(_T_1487)
node _T_1489 = eq(_T_1488, asSInt(UInt<1>(0h0)))
node _T_1490 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1491 = cvt(_T_1490)
node _T_1492 = and(_T_1491, asSInt(UInt<29>(0h10000000)))
node _T_1493 = asSInt(_T_1492)
node _T_1494 = eq(_T_1493, asSInt(UInt<1>(0h0)))
node _T_1495 = or(_T_1489, _T_1494)
node _T_1496 = and(_T_1484, _T_1495)
node _T_1497 = or(UInt<1>(0h0), _T_1496)
node _T_1498 = and(UInt<1>(0h0), _T_1497)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_112
node _T_1502 = asUInt(reset)
node _T_1503 = eq(_T_1502, UInt<1>(0h0))
when _T_1503 :
node _T_1504 = eq(address_ok, UInt<1>(0h0))
when _T_1504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(legal_source, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1511 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_116
node _T_1515 = eq(io.in.b.bits.mask, mask_1)
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_117
node _T_1519 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1519 :
node _T_1520 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1521 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1522 = and(_T_1520, _T_1521)
node _T_1523 = or(UInt<1>(0h0), _T_1522)
node _T_1524 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1525 = cvt(_T_1524)
node _T_1526 = and(_T_1525, asSInt(UInt<17>(0h10000)))
node _T_1527 = asSInt(_T_1526)
node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0)))
node _T_1529 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1530 = cvt(_T_1529)
node _T_1531 = and(_T_1530, asSInt(UInt<29>(0h10000000)))
node _T_1532 = asSInt(_T_1531)
node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0)))
node _T_1534 = or(_T_1528, _T_1533)
node _T_1535 = and(_T_1523, _T_1534)
node _T_1536 = or(UInt<1>(0h0), _T_1535)
node _T_1537 = and(UInt<1>(0h0), _T_1536)
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_118
node _T_1541 = asUInt(reset)
node _T_1542 = eq(_T_1541, UInt<1>(0h0))
when _T_1542 :
node _T_1543 = eq(address_ok, UInt<1>(0h0))
when _T_1543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1544 = asUInt(reset)
node _T_1545 = eq(_T_1544, UInt<1>(0h0))
when _T_1545 :
node _T_1546 = eq(legal_source, UInt<1>(0h0))
when _T_1546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1550 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_122
node _T_1554 = eq(io.in.b.bits.mask, mask_1)
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_123
node _T_1558 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1558 :
node _T_1559 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1560 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1561 = and(_T_1559, _T_1560)
node _T_1562 = or(UInt<1>(0h0), _T_1561)
node _T_1563 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1564 = cvt(_T_1563)
node _T_1565 = and(_T_1564, asSInt(UInt<17>(0h10000)))
node _T_1566 = asSInt(_T_1565)
node _T_1567 = eq(_T_1566, asSInt(UInt<1>(0h0)))
node _T_1568 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1569 = cvt(_T_1568)
node _T_1570 = and(_T_1569, asSInt(UInt<29>(0h10000000)))
node _T_1571 = asSInt(_T_1570)
node _T_1572 = eq(_T_1571, asSInt(UInt<1>(0h0)))
node _T_1573 = or(_T_1567, _T_1572)
node _T_1574 = and(_T_1562, _T_1573)
node _T_1575 = or(UInt<1>(0h0), _T_1574)
node _T_1576 = and(UInt<1>(0h0), _T_1575)
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_124
node _T_1580 = asUInt(reset)
node _T_1581 = eq(_T_1580, UInt<1>(0h0))
when _T_1581 :
node _T_1582 = eq(address_ok, UInt<1>(0h0))
when _T_1582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1583 = asUInt(reset)
node _T_1584 = eq(_T_1583, UInt<1>(0h0))
when _T_1584 :
node _T_1585 = eq(legal_source, UInt<1>(0h0))
when _T_1585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1589 = eq(io.in.b.bits.mask, mask_1)
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_128
node _T_1593 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1597 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(_T_1597, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1597, UInt<1>(0h1), "") : assert_130
node _source_ok_T_92 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _source_ok_uncommonBits_T_12 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.c.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<5>(0h10))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.c.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<5>(0h11))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.c.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<5>(0h12))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.c.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<5>(0h13))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_T_117 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _source_ok_uncommonBits_T_16 = or(io.in.c.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 3, 0)
node _source_ok_T_118 = shr(io.in.c.bits.source, 4)
node _source_ok_T_119 = eq(_source_ok_T_118, UInt<1>(0h1))
node _source_ok_T_120 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_121 = and(_source_ok_T_119, _source_ok_T_120)
node _source_ok_T_122 = leq(source_ok_uncommonBits_16, UInt<4>(0hf))
node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122)
node _source_ok_uncommonBits_T_17 = or(io.in.c.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 3, 0)
node _source_ok_T_124 = shr(io.in.c.bits.source, 4)
node _source_ok_T_125 = eq(_source_ok_T_124, UInt<1>(0h0))
node _source_ok_T_126 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_127 = and(_source_ok_T_125, _source_ok_T_126)
node _source_ok_T_128 = leq(source_ok_uncommonBits_17, UInt<4>(0hf))
node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128)
node _source_ok_T_130 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _source_ok_WIRE_2 : UInt<1>[9]
connect _source_ok_WIRE_2[0], _source_ok_T_92
connect _source_ok_WIRE_2[1], _source_ok_T_98
connect _source_ok_WIRE_2[2], _source_ok_T_104
connect _source_ok_WIRE_2[3], _source_ok_T_110
connect _source_ok_WIRE_2[4], _source_ok_T_116
connect _source_ok_WIRE_2[5], _source_ok_T_117
connect _source_ok_WIRE_2[6], _source_ok_T_123
connect _source_ok_WIRE_2[7], _source_ok_T_129
connect _source_ok_WIRE_2[8], _source_ok_T_130
node _source_ok_T_131 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_2[2])
node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_2[3])
node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_2[4])
node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_2[5])
node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_2[6])
node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_2[7])
node source_ok_2 = or(_source_ok_T_137, _source_ok_WIRE_2[8])
node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[2]
connect _address_ok_WIRE_1[0], _address_ok_T_14
connect _address_ok_WIRE_1[1], _address_ok_T_19
node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _T_1601 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _T_1602 = eq(_T_1601, UInt<1>(0h0))
node _T_1603 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1604 = cvt(_T_1603)
node _T_1605 = and(_T_1604, asSInt(UInt<1>(0h0)))
node _T_1606 = asSInt(_T_1605)
node _T_1607 = eq(_T_1606, asSInt(UInt<1>(0h0)))
node _T_1608 = or(_T_1602, _T_1607)
node _uncommonBits_T_78 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 1, 0)
node _T_1609 = shr(io.in.c.bits.source, 2)
node _T_1610 = eq(_T_1609, UInt<5>(0h10))
node _T_1611 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_1612 = and(_T_1610, _T_1611)
node _T_1613 = leq(uncommonBits_78, UInt<2>(0h3))
node _T_1614 = and(_T_1612, _T_1613)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
node _T_1616 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1617 = cvt(_T_1616)
node _T_1618 = and(_T_1617, asSInt(UInt<1>(0h0)))
node _T_1619 = asSInt(_T_1618)
node _T_1620 = eq(_T_1619, asSInt(UInt<1>(0h0)))
node _T_1621 = or(_T_1615, _T_1620)
node _uncommonBits_T_79 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 1, 0)
node _T_1622 = shr(io.in.c.bits.source, 2)
node _T_1623 = eq(_T_1622, UInt<5>(0h11))
node _T_1624 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_1625 = and(_T_1623, _T_1624)
node _T_1626 = leq(uncommonBits_79, UInt<2>(0h3))
node _T_1627 = and(_T_1625, _T_1626)
node _T_1628 = eq(_T_1627, UInt<1>(0h0))
node _T_1629 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1630 = cvt(_T_1629)
node _T_1631 = and(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = asSInt(_T_1631)
node _T_1633 = eq(_T_1632, asSInt(UInt<1>(0h0)))
node _T_1634 = or(_T_1628, _T_1633)
node _uncommonBits_T_80 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 1, 0)
node _T_1635 = shr(io.in.c.bits.source, 2)
node _T_1636 = eq(_T_1635, UInt<5>(0h12))
node _T_1637 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_1638 = and(_T_1636, _T_1637)
node _T_1639 = leq(uncommonBits_80, UInt<2>(0h3))
node _T_1640 = and(_T_1638, _T_1639)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
node _T_1642 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1643 = cvt(_T_1642)
node _T_1644 = and(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = asSInt(_T_1644)
node _T_1646 = eq(_T_1645, asSInt(UInt<1>(0h0)))
node _T_1647 = or(_T_1641, _T_1646)
node _uncommonBits_T_81 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 1, 0)
node _T_1648 = shr(io.in.c.bits.source, 2)
node _T_1649 = eq(_T_1648, UInt<5>(0h13))
node _T_1650 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_1651 = and(_T_1649, _T_1650)
node _T_1652 = leq(uncommonBits_81, UInt<2>(0h3))
node _T_1653 = and(_T_1651, _T_1652)
node _T_1654 = eq(_T_1653, UInt<1>(0h0))
node _T_1655 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<1>(0h0)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = or(_T_1654, _T_1659)
node _T_1661 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _T_1662 = eq(_T_1661, UInt<1>(0h0))
node _T_1663 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1664 = cvt(_T_1663)
node _T_1665 = and(_T_1664, asSInt(UInt<1>(0h0)))
node _T_1666 = asSInt(_T_1665)
node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0)))
node _T_1668 = or(_T_1662, _T_1667)
node _uncommonBits_T_82 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 3, 0)
node _T_1669 = shr(io.in.c.bits.source, 4)
node _T_1670 = eq(_T_1669, UInt<1>(0h1))
node _T_1671 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_1672 = and(_T_1670, _T_1671)
node _T_1673 = leq(uncommonBits_82, UInt<4>(0hf))
node _T_1674 = and(_T_1672, _T_1673)
node _T_1675 = eq(_T_1674, UInt<1>(0h0))
node _T_1676 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1677 = cvt(_T_1676)
node _T_1678 = and(_T_1677, asSInt(UInt<1>(0h0)))
node _T_1679 = asSInt(_T_1678)
node _T_1680 = eq(_T_1679, asSInt(UInt<1>(0h0)))
node _T_1681 = or(_T_1675, _T_1680)
node _uncommonBits_T_83 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 3, 0)
node _T_1682 = shr(io.in.c.bits.source, 4)
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
node _T_1684 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_1685 = and(_T_1683, _T_1684)
node _T_1686 = leq(uncommonBits_83, UInt<4>(0hf))
node _T_1687 = and(_T_1685, _T_1686)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
node _T_1689 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1690 = cvt(_T_1689)
node _T_1691 = and(_T_1690, asSInt(UInt<1>(0h0)))
node _T_1692 = asSInt(_T_1691)
node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = or(_T_1688, _T_1693)
node _T_1695 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_1696 = eq(_T_1695, UInt<1>(0h0))
node _T_1697 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1698 = cvt(_T_1697)
node _T_1699 = and(_T_1698, asSInt(UInt<1>(0h0)))
node _T_1700 = asSInt(_T_1699)
node _T_1701 = eq(_T_1700, asSInt(UInt<1>(0h0)))
node _T_1702 = or(_T_1696, _T_1701)
node _T_1703 = and(_T_1608, _T_1621)
node _T_1704 = and(_T_1703, _T_1634)
node _T_1705 = and(_T_1704, _T_1647)
node _T_1706 = and(_T_1705, _T_1660)
node _T_1707 = and(_T_1706, _T_1668)
node _T_1708 = and(_T_1707, _T_1681)
node _T_1709 = and(_T_1708, _T_1694)
node _T_1710 = and(_T_1709, _T_1702)
node _T_1711 = asUInt(reset)
node _T_1712 = eq(_T_1711, UInt<1>(0h0))
when _T_1712 :
node _T_1713 = eq(_T_1710, UInt<1>(0h0))
when _T_1713 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1710, UInt<1>(0h1), "") : assert_131
node _T_1714 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1714 :
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(address_ok_1, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1718 = asUInt(reset)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
when _T_1719 :
node _T_1720 = eq(source_ok_2, UInt<1>(0h0))
when _T_1720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1721 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1722 = asUInt(reset)
node _T_1723 = eq(_T_1722, UInt<1>(0h0))
when _T_1723 :
node _T_1724 = eq(_T_1721, UInt<1>(0h0))
when _T_1724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1721, UInt<1>(0h1), "") : assert_134
node _T_1725 = asUInt(reset)
node _T_1726 = eq(_T_1725, UInt<1>(0h0))
when _T_1726 :
node _T_1727 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1728 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1729 = asUInt(reset)
node _T_1730 = eq(_T_1729, UInt<1>(0h0))
when _T_1730 :
node _T_1731 = eq(_T_1728, UInt<1>(0h0))
when _T_1731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1728, UInt<1>(0h1), "") : assert_136
node _T_1732 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1733 = asUInt(reset)
node _T_1734 = eq(_T_1733, UInt<1>(0h0))
when _T_1734 :
node _T_1735 = eq(_T_1732, UInt<1>(0h0))
when _T_1735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1732, UInt<1>(0h1), "") : assert_137
node _T_1736 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1736 :
node _T_1737 = asUInt(reset)
node _T_1738 = eq(_T_1737, UInt<1>(0h0))
when _T_1738 :
node _T_1739 = eq(address_ok_1, UInt<1>(0h0))
when _T_1739 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1740 = asUInt(reset)
node _T_1741 = eq(_T_1740, UInt<1>(0h0))
when _T_1741 :
node _T_1742 = eq(source_ok_2, UInt<1>(0h0))
when _T_1742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1743 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1744 = asUInt(reset)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
when _T_1745 :
node _T_1746 = eq(_T_1743, UInt<1>(0h0))
when _T_1746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1743, UInt<1>(0h1), "") : assert_140
node _T_1747 = asUInt(reset)
node _T_1748 = eq(_T_1747, UInt<1>(0h0))
when _T_1748 :
node _T_1749 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1750 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1751 = asUInt(reset)
node _T_1752 = eq(_T_1751, UInt<1>(0h0))
when _T_1752 :
node _T_1753 = eq(_T_1750, UInt<1>(0h0))
when _T_1753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1750, UInt<1>(0h1), "") : assert_142
node _T_1754 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1754 :
node _T_1755 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1756 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1757 = and(_T_1755, _T_1756)
node _T_1758 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _uncommonBits_T_84 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1759 = shr(io.in.c.bits.source, 2)
node _T_1760 = eq(_T_1759, UInt<5>(0h10))
node _T_1761 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1762 = and(_T_1760, _T_1761)
node _T_1763 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1764 = and(_T_1762, _T_1763)
node _uncommonBits_T_85 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1765 = shr(io.in.c.bits.source, 2)
node _T_1766 = eq(_T_1765, UInt<5>(0h11))
node _T_1767 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1768 = and(_T_1766, _T_1767)
node _T_1769 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1770 = and(_T_1768, _T_1769)
node _uncommonBits_T_86 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1771 = shr(io.in.c.bits.source, 2)
node _T_1772 = eq(_T_1771, UInt<5>(0h12))
node _T_1773 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1774 = and(_T_1772, _T_1773)
node _T_1775 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1776 = and(_T_1774, _T_1775)
node _uncommonBits_T_87 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1777 = shr(io.in.c.bits.source, 2)
node _T_1778 = eq(_T_1777, UInt<5>(0h13))
node _T_1779 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1782 = and(_T_1780, _T_1781)
node _T_1783 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_88 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 3, 0)
node _T_1784 = shr(io.in.c.bits.source, 4)
node _T_1785 = eq(_T_1784, UInt<1>(0h1))
node _T_1786 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1787 = and(_T_1785, _T_1786)
node _T_1788 = leq(uncommonBits_88, UInt<4>(0hf))
node _T_1789 = and(_T_1787, _T_1788)
node _uncommonBits_T_89 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 3, 0)
node _T_1790 = shr(io.in.c.bits.source, 4)
node _T_1791 = eq(_T_1790, UInt<1>(0h0))
node _T_1792 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1793 = and(_T_1791, _T_1792)
node _T_1794 = leq(uncommonBits_89, UInt<4>(0hf))
node _T_1795 = and(_T_1793, _T_1794)
node _T_1796 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_1797 = or(_T_1758, _T_1764)
node _T_1798 = or(_T_1797, _T_1770)
node _T_1799 = or(_T_1798, _T_1776)
node _T_1800 = or(_T_1799, _T_1782)
node _T_1801 = or(_T_1800, _T_1783)
node _T_1802 = or(_T_1801, _T_1789)
node _T_1803 = or(_T_1802, _T_1795)
node _T_1804 = or(_T_1803, _T_1796)
node _T_1805 = and(_T_1757, _T_1804)
node _T_1806 = or(UInt<1>(0h0), _T_1805)
node _T_1807 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1808 = or(UInt<1>(0h0), _T_1807)
node _T_1809 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1810 = cvt(_T_1809)
node _T_1811 = and(_T_1810, asSInt(UInt<17>(0h10000)))
node _T_1812 = asSInt(_T_1811)
node _T_1813 = eq(_T_1812, asSInt(UInt<1>(0h0)))
node _T_1814 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1815 = cvt(_T_1814)
node _T_1816 = and(_T_1815, asSInt(UInt<29>(0h10000000)))
node _T_1817 = asSInt(_T_1816)
node _T_1818 = eq(_T_1817, asSInt(UInt<1>(0h0)))
node _T_1819 = or(_T_1813, _T_1818)
node _T_1820 = and(_T_1808, _T_1819)
node _T_1821 = or(UInt<1>(0h0), _T_1820)
node _T_1822 = and(_T_1806, _T_1821)
node _T_1823 = asUInt(reset)
node _T_1824 = eq(_T_1823, UInt<1>(0h0))
when _T_1824 :
node _T_1825 = eq(_T_1822, UInt<1>(0h0))
when _T_1825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1822, UInt<1>(0h1), "") : assert_143
node _T_1826 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _uncommonBits_T_90 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 1, 0)
node _T_1827 = shr(io.in.c.bits.source, 2)
node _T_1828 = eq(_T_1827, UInt<5>(0h10))
node _T_1829 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1830 = and(_T_1828, _T_1829)
node _T_1831 = leq(uncommonBits_90, UInt<2>(0h3))
node _T_1832 = and(_T_1830, _T_1831)
node _uncommonBits_T_91 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 1, 0)
node _T_1833 = shr(io.in.c.bits.source, 2)
node _T_1834 = eq(_T_1833, UInt<5>(0h11))
node _T_1835 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1836 = and(_T_1834, _T_1835)
node _T_1837 = leq(uncommonBits_91, UInt<2>(0h3))
node _T_1838 = and(_T_1836, _T_1837)
node _uncommonBits_T_92 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 1, 0)
node _T_1839 = shr(io.in.c.bits.source, 2)
node _T_1840 = eq(_T_1839, UInt<5>(0h12))
node _T_1841 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1842 = and(_T_1840, _T_1841)
node _T_1843 = leq(uncommonBits_92, UInt<2>(0h3))
node _T_1844 = and(_T_1842, _T_1843)
node _uncommonBits_T_93 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 1, 0)
node _T_1845 = shr(io.in.c.bits.source, 2)
node _T_1846 = eq(_T_1845, UInt<5>(0h13))
node _T_1847 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1848 = and(_T_1846, _T_1847)
node _T_1849 = leq(uncommonBits_93, UInt<2>(0h3))
node _T_1850 = and(_T_1848, _T_1849)
node _T_1851 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_94 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 3, 0)
node _T_1852 = shr(io.in.c.bits.source, 4)
node _T_1853 = eq(_T_1852, UInt<1>(0h1))
node _T_1854 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1855 = and(_T_1853, _T_1854)
node _T_1856 = leq(uncommonBits_94, UInt<4>(0hf))
node _T_1857 = and(_T_1855, _T_1856)
node _uncommonBits_T_95 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 3, 0)
node _T_1858 = shr(io.in.c.bits.source, 4)
node _T_1859 = eq(_T_1858, UInt<1>(0h0))
node _T_1860 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1861 = and(_T_1859, _T_1860)
node _T_1862 = leq(uncommonBits_95, UInt<4>(0hf))
node _T_1863 = and(_T_1861, _T_1862)
node _T_1864 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_6 : UInt<1>[9]
connect _WIRE_6[0], _T_1826
connect _WIRE_6[1], _T_1832
connect _WIRE_6[2], _T_1838
connect _WIRE_6[3], _T_1844
connect _WIRE_6[4], _T_1850
connect _WIRE_6[5], _T_1851
connect _WIRE_6[6], _T_1857
connect _WIRE_6[7], _T_1863
connect _WIRE_6[8], _T_1864
node _T_1865 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1866 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1867 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1868 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1869 = mux(_WIRE_6[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_1870 = mux(_WIRE_6[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_1871 = mux(_WIRE_6[5], _T_1865, UInt<1>(0h0))
node _T_1872 = mux(_WIRE_6[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_1873 = mux(_WIRE_6[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_1874 = mux(_WIRE_6[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_1875 = or(_T_1866, _T_1867)
node _T_1876 = or(_T_1875, _T_1868)
node _T_1877 = or(_T_1876, _T_1869)
node _T_1878 = or(_T_1877, _T_1870)
node _T_1879 = or(_T_1878, _T_1871)
node _T_1880 = or(_T_1879, _T_1872)
node _T_1881 = or(_T_1880, _T_1873)
node _T_1882 = or(_T_1881, _T_1874)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1882
node _T_1883 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1884 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1885 = and(_T_1883, _T_1884)
node _T_1886 = or(UInt<1>(0h0), _T_1885)
node _T_1887 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1888 = cvt(_T_1887)
node _T_1889 = and(_T_1888, asSInt(UInt<17>(0h10000)))
node _T_1890 = asSInt(_T_1889)
node _T_1891 = eq(_T_1890, asSInt(UInt<1>(0h0)))
node _T_1892 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1893 = cvt(_T_1892)
node _T_1894 = and(_T_1893, asSInt(UInt<29>(0h10000000)))
node _T_1895 = asSInt(_T_1894)
node _T_1896 = eq(_T_1895, asSInt(UInt<1>(0h0)))
node _T_1897 = or(_T_1891, _T_1896)
node _T_1898 = and(_T_1886, _T_1897)
node _T_1899 = or(UInt<1>(0h0), _T_1898)
node _T_1900 = and(_WIRE_7, _T_1899)
node _T_1901 = asUInt(reset)
node _T_1902 = eq(_T_1901, UInt<1>(0h0))
when _T_1902 :
node _T_1903 = eq(_T_1900, UInt<1>(0h0))
when _T_1903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1900, UInt<1>(0h1), "") : assert_144
node _T_1904 = asUInt(reset)
node _T_1905 = eq(_T_1904, UInt<1>(0h0))
when _T_1905 :
node _T_1906 = eq(source_ok_2, UInt<1>(0h0))
when _T_1906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1907 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_1908 = asUInt(reset)
node _T_1909 = eq(_T_1908, UInt<1>(0h0))
when _T_1909 :
node _T_1910 = eq(_T_1907, UInt<1>(0h0))
when _T_1910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1907, UInt<1>(0h1), "") : assert_146
node _T_1911 = asUInt(reset)
node _T_1912 = eq(_T_1911, UInt<1>(0h0))
when _T_1912 :
node _T_1913 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1913 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1914 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1915 = asUInt(reset)
node _T_1916 = eq(_T_1915, UInt<1>(0h0))
when _T_1916 :
node _T_1917 = eq(_T_1914, UInt<1>(0h0))
when _T_1917 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1914, UInt<1>(0h1), "") : assert_148
node _T_1918 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1919 = asUInt(reset)
node _T_1920 = eq(_T_1919, UInt<1>(0h0))
when _T_1920 :
node _T_1921 = eq(_T_1918, UInt<1>(0h0))
when _T_1921 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1918, UInt<1>(0h1), "") : assert_149
node _T_1922 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1922 :
node _T_1923 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1924 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1925 = and(_T_1923, _T_1924)
node _T_1926 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _uncommonBits_T_96 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1927 = shr(io.in.c.bits.source, 2)
node _T_1928 = eq(_T_1927, UInt<5>(0h10))
node _T_1929 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1930 = and(_T_1928, _T_1929)
node _T_1931 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1932 = and(_T_1930, _T_1931)
node _uncommonBits_T_97 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1933 = shr(io.in.c.bits.source, 2)
node _T_1934 = eq(_T_1933, UInt<5>(0h11))
node _T_1935 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1936 = and(_T_1934, _T_1935)
node _T_1937 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1938 = and(_T_1936, _T_1937)
node _uncommonBits_T_98 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1939 = shr(io.in.c.bits.source, 2)
node _T_1940 = eq(_T_1939, UInt<5>(0h12))
node _T_1941 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1942 = and(_T_1940, _T_1941)
node _T_1943 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1944 = and(_T_1942, _T_1943)
node _uncommonBits_T_99 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1945 = shr(io.in.c.bits.source, 2)
node _T_1946 = eq(_T_1945, UInt<5>(0h13))
node _T_1947 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1948 = and(_T_1946, _T_1947)
node _T_1949 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1950 = and(_T_1948, _T_1949)
node _T_1951 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_100 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 3, 0)
node _T_1952 = shr(io.in.c.bits.source, 4)
node _T_1953 = eq(_T_1952, UInt<1>(0h1))
node _T_1954 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1955 = and(_T_1953, _T_1954)
node _T_1956 = leq(uncommonBits_100, UInt<4>(0hf))
node _T_1957 = and(_T_1955, _T_1956)
node _uncommonBits_T_101 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 3, 0)
node _T_1958 = shr(io.in.c.bits.source, 4)
node _T_1959 = eq(_T_1958, UInt<1>(0h0))
node _T_1960 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1961 = and(_T_1959, _T_1960)
node _T_1962 = leq(uncommonBits_101, UInt<4>(0hf))
node _T_1963 = and(_T_1961, _T_1962)
node _T_1964 = eq(io.in.c.bits.source, UInt<6>(0h22))
node _T_1965 = or(_T_1926, _T_1932)
node _T_1966 = or(_T_1965, _T_1938)
node _T_1967 = or(_T_1966, _T_1944)
node _T_1968 = or(_T_1967, _T_1950)
node _T_1969 = or(_T_1968, _T_1951)
node _T_1970 = or(_T_1969, _T_1957)
node _T_1971 = or(_T_1970, _T_1963)
node _T_1972 = or(_T_1971, _T_1964)
node _T_1973 = and(_T_1925, _T_1972)
node _T_1974 = or(UInt<1>(0h0), _T_1973)
node _T_1975 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1976 = or(UInt<1>(0h0), _T_1975)
node _T_1977 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1978 = cvt(_T_1977)
node _T_1979 = and(_T_1978, asSInt(UInt<17>(0h10000)))
node _T_1980 = asSInt(_T_1979)
node _T_1981 = eq(_T_1980, asSInt(UInt<1>(0h0)))
node _T_1982 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1983 = cvt(_T_1982)
node _T_1984 = and(_T_1983, asSInt(UInt<29>(0h10000000)))
node _T_1985 = asSInt(_T_1984)
node _T_1986 = eq(_T_1985, asSInt(UInt<1>(0h0)))
node _T_1987 = or(_T_1981, _T_1986)
node _T_1988 = and(_T_1976, _T_1987)
node _T_1989 = or(UInt<1>(0h0), _T_1988)
node _T_1990 = and(_T_1974, _T_1989)
node _T_1991 = asUInt(reset)
node _T_1992 = eq(_T_1991, UInt<1>(0h0))
when _T_1992 :
node _T_1993 = eq(_T_1990, UInt<1>(0h0))
when _T_1993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_1990, UInt<1>(0h1), "") : assert_150
node _T_1994 = eq(io.in.c.bits.source, UInt<7>(0h50))
node _uncommonBits_T_102 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 1, 0)
node _T_1995 = shr(io.in.c.bits.source, 2)
node _T_1996 = eq(_T_1995, UInt<5>(0h10))
node _T_1997 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1998 = and(_T_1996, _T_1997)
node _T_1999 = leq(uncommonBits_102, UInt<2>(0h3))
node _T_2000 = and(_T_1998, _T_1999)
node _uncommonBits_T_103 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 1, 0)
node _T_2001 = shr(io.in.c.bits.source, 2)
node _T_2002 = eq(_T_2001, UInt<5>(0h11))
node _T_2003 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_2004 = and(_T_2002, _T_2003)
node _T_2005 = leq(uncommonBits_103, UInt<2>(0h3))
node _T_2006 = and(_T_2004, _T_2005)
node _uncommonBits_T_104 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 1, 0)
node _T_2007 = shr(io.in.c.bits.source, 2)
node _T_2008 = eq(_T_2007, UInt<5>(0h12))
node _T_2009 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_2010 = and(_T_2008, _T_2009)
node _T_2011 = leq(uncommonBits_104, UInt<2>(0h3))
node _T_2012 = and(_T_2010, _T_2011)
node _uncommonBits_T_105 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 1, 0)
node _T_2013 = shr(io.in.c.bits.source, 2)
node _T_2014 = eq(_T_2013, UInt<5>(0h13))
node _T_2015 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_2016 = and(_T_2014, _T_2015)
node _T_2017 = leq(uncommonBits_105, UInt<2>(0h3))
node _T_2018 = and(_T_2016, _T_2017)
node _T_2019 = eq(io.in.c.bits.source, UInt<6>(0h20))
node _uncommonBits_T_106 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 3, 0)
node _T_2020 = shr(io.in.c.bits.source, 4)
node _T_2021 = eq(_T_2020, UInt<1>(0h1))
node _T_2022 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_2023 = and(_T_2021, _T_2022)
node _T_2024 = leq(uncommonBits_106, UInt<4>(0hf))
node _T_2025 = and(_T_2023, _T_2024)
node _uncommonBits_T_107 = or(io.in.c.bits.source, UInt<4>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 3, 0)
node _T_2026 = shr(io.in.c.bits.source, 4)
node _T_2027 = eq(_T_2026, UInt<1>(0h0))
node _T_2028 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_2029 = and(_T_2027, _T_2028)
node _T_2030 = leq(uncommonBits_107, UInt<4>(0hf))
node _T_2031 = and(_T_2029, _T_2030)
node _T_2032 = eq(io.in.c.bits.source, UInt<6>(0h22))
wire _WIRE_8 : UInt<1>[9]
connect _WIRE_8[0], _T_1994
connect _WIRE_8[1], _T_2000
connect _WIRE_8[2], _T_2006
connect _WIRE_8[3], _T_2012
connect _WIRE_8[4], _T_2018
connect _WIRE_8[5], _T_2019
connect _WIRE_8[6], _T_2025
connect _WIRE_8[7], _T_2031
connect _WIRE_8[8], _T_2032
node _T_2033 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2034 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2035 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2036 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2037 = mux(_WIRE_8[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_2038 = mux(_WIRE_8[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_2039 = mux(_WIRE_8[5], _T_2033, UInt<1>(0h0))
node _T_2040 = mux(_WIRE_8[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_2041 = mux(_WIRE_8[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_2042 = mux(_WIRE_8[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_2043 = or(_T_2034, _T_2035)
node _T_2044 = or(_T_2043, _T_2036)
node _T_2045 = or(_T_2044, _T_2037)
node _T_2046 = or(_T_2045, _T_2038)
node _T_2047 = or(_T_2046, _T_2039)
node _T_2048 = or(_T_2047, _T_2040)
node _T_2049 = or(_T_2048, _T_2041)
node _T_2050 = or(_T_2049, _T_2042)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2050
node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2053 = and(_T_2051, _T_2052)
node _T_2054 = or(UInt<1>(0h0), _T_2053)
node _T_2055 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2056 = cvt(_T_2055)
node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000)))
node _T_2058 = asSInt(_T_2057)
node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0)))
node _T_2060 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<29>(0h10000000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = or(_T_2059, _T_2064)
node _T_2066 = and(_T_2054, _T_2065)
node _T_2067 = or(UInt<1>(0h0), _T_2066)
node _T_2068 = and(_WIRE_9, _T_2067)
node _T_2069 = asUInt(reset)
node _T_2070 = eq(_T_2069, UInt<1>(0h0))
when _T_2070 :
node _T_2071 = eq(_T_2068, UInt<1>(0h0))
when _T_2071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2068, UInt<1>(0h1), "") : assert_151
node _T_2072 = asUInt(reset)
node _T_2073 = eq(_T_2072, UInt<1>(0h0))
when _T_2073 :
node _T_2074 = eq(source_ok_2, UInt<1>(0h0))
when _T_2074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2075 = geq(io.in.c.bits.size, UInt<3>(0h4))
node _T_2076 = asUInt(reset)
node _T_2077 = eq(_T_2076, UInt<1>(0h0))
when _T_2077 :
node _T_2078 = eq(_T_2075, UInt<1>(0h0))
when _T_2078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2075, UInt<1>(0h1), "") : assert_153
node _T_2079 = asUInt(reset)
node _T_2080 = eq(_T_2079, UInt<1>(0h0))
when _T_2080 :
node _T_2081 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2082 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2083 = asUInt(reset)
node _T_2084 = eq(_T_2083, UInt<1>(0h0))
when _T_2084 :
node _T_2085 = eq(_T_2082, UInt<1>(0h0))
when _T_2085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2082, UInt<1>(0h1), "") : assert_155
node _T_2086 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2086 :
node _T_2087 = asUInt(reset)
node _T_2088 = eq(_T_2087, UInt<1>(0h0))
when _T_2088 :
node _T_2089 = eq(address_ok_1, UInt<1>(0h0))
when _T_2089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2090 = asUInt(reset)
node _T_2091 = eq(_T_2090, UInt<1>(0h0))
when _T_2091 :
node _T_2092 = eq(source_ok_2, UInt<1>(0h0))
when _T_2092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2093 = asUInt(reset)
node _T_2094 = eq(_T_2093, UInt<1>(0h0))
when _T_2094 :
node _T_2095 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2096 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2097 = asUInt(reset)
node _T_2098 = eq(_T_2097, UInt<1>(0h0))
when _T_2098 :
node _T_2099 = eq(_T_2096, UInt<1>(0h0))
when _T_2099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2096, UInt<1>(0h1), "") : assert_159
node _T_2100 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2101 = asUInt(reset)
node _T_2102 = eq(_T_2101, UInt<1>(0h0))
when _T_2102 :
node _T_2103 = eq(_T_2100, UInt<1>(0h0))
when _T_2103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2100, UInt<1>(0h1), "") : assert_160
node _T_2104 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2104 :
node _T_2105 = asUInt(reset)
node _T_2106 = eq(_T_2105, UInt<1>(0h0))
when _T_2106 :
node _T_2107 = eq(address_ok_1, UInt<1>(0h0))
when _T_2107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2108 = asUInt(reset)
node _T_2109 = eq(_T_2108, UInt<1>(0h0))
when _T_2109 :
node _T_2110 = eq(source_ok_2, UInt<1>(0h0))
when _T_2110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2111 = asUInt(reset)
node _T_2112 = eq(_T_2111, UInt<1>(0h0))
when _T_2112 :
node _T_2113 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2114 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2115 = asUInt(reset)
node _T_2116 = eq(_T_2115, UInt<1>(0h0))
when _T_2116 :
node _T_2117 = eq(_T_2114, UInt<1>(0h0))
when _T_2117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2114, UInt<1>(0h1), "") : assert_164
node _T_2118 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2118 :
node _T_2119 = asUInt(reset)
node _T_2120 = eq(_T_2119, UInt<1>(0h0))
when _T_2120 :
node _T_2121 = eq(address_ok_1, UInt<1>(0h0))
when _T_2121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2122 = asUInt(reset)
node _T_2123 = eq(_T_2122, UInt<1>(0h0))
when _T_2123 :
node _T_2124 = eq(source_ok_2, UInt<1>(0h0))
when _T_2124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2128 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2129 = asUInt(reset)
node _T_2130 = eq(_T_2129, UInt<1>(0h0))
when _T_2130 :
node _T_2131 = eq(_T_2128, UInt<1>(0h0))
when _T_2131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2128, UInt<1>(0h1), "") : assert_168
node _T_2132 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2133 = asUInt(reset)
node _T_2134 = eq(_T_2133, UInt<1>(0h0))
when _T_2134 :
node _T_2135 = eq(_T_2132, UInt<1>(0h0))
when _T_2135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2132, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0hc))
node _T_2136 = asUInt(reset)
node _T_2137 = eq(_T_2136, UInt<1>(0h0))
when _T_2137 :
node _T_2138 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2139 = eq(a_first, UInt<1>(0h0))
node _T_2140 = and(io.in.a.valid, _T_2139)
when _T_2140 :
node _T_2141 = eq(io.in.a.bits.opcode, opcode)
node _T_2142 = asUInt(reset)
node _T_2143 = eq(_T_2142, UInt<1>(0h0))
when _T_2143 :
node _T_2144 = eq(_T_2141, UInt<1>(0h0))
when _T_2144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2141, UInt<1>(0h1), "") : assert_171
node _T_2145 = eq(io.in.a.bits.param, param)
node _T_2146 = asUInt(reset)
node _T_2147 = eq(_T_2146, UInt<1>(0h0))
when _T_2147 :
node _T_2148 = eq(_T_2145, UInt<1>(0h0))
when _T_2148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2145, UInt<1>(0h1), "") : assert_172
node _T_2149 = eq(io.in.a.bits.size, size)
node _T_2150 = asUInt(reset)
node _T_2151 = eq(_T_2150, UInt<1>(0h0))
when _T_2151 :
node _T_2152 = eq(_T_2149, UInt<1>(0h0))
when _T_2152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2149, UInt<1>(0h1), "") : assert_173
node _T_2153 = eq(io.in.a.bits.source, source)
node _T_2154 = asUInt(reset)
node _T_2155 = eq(_T_2154, UInt<1>(0h0))
when _T_2155 :
node _T_2156 = eq(_T_2153, UInt<1>(0h0))
when _T_2156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2153, UInt<1>(0h1), "") : assert_174
node _T_2157 = eq(io.in.a.bits.address, address)
node _T_2158 = asUInt(reset)
node _T_2159 = eq(_T_2158, UInt<1>(0h0))
when _T_2159 :
node _T_2160 = eq(_T_2157, UInt<1>(0h0))
when _T_2160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2157, UInt<1>(0h1), "") : assert_175
node _T_2161 = and(io.in.a.ready, io.in.a.valid)
node _T_2162 = and(_T_2161, a_first)
when _T_2162 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2163 = eq(d_first, UInt<1>(0h0))
node _T_2164 = and(io.in.d.valid, _T_2163)
when _T_2164 :
node _T_2165 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2166 = asUInt(reset)
node _T_2167 = eq(_T_2166, UInt<1>(0h0))
when _T_2167 :
node _T_2168 = eq(_T_2165, UInt<1>(0h0))
when _T_2168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2165, UInt<1>(0h1), "") : assert_176
node _T_2169 = eq(io.in.d.bits.param, param_1)
node _T_2170 = asUInt(reset)
node _T_2171 = eq(_T_2170, UInt<1>(0h0))
when _T_2171 :
node _T_2172 = eq(_T_2169, UInt<1>(0h0))
when _T_2172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2169, UInt<1>(0h1), "") : assert_177
node _T_2173 = eq(io.in.d.bits.size, size_1)
node _T_2174 = asUInt(reset)
node _T_2175 = eq(_T_2174, UInt<1>(0h0))
when _T_2175 :
node _T_2176 = eq(_T_2173, UInt<1>(0h0))
when _T_2176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2173, UInt<1>(0h1), "") : assert_178
node _T_2177 = eq(io.in.d.bits.source, source_1)
node _T_2178 = asUInt(reset)
node _T_2179 = eq(_T_2178, UInt<1>(0h0))
when _T_2179 :
node _T_2180 = eq(_T_2177, UInt<1>(0h0))
when _T_2180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2177, UInt<1>(0h1), "") : assert_179
node _T_2181 = eq(io.in.d.bits.sink, sink)
node _T_2182 = asUInt(reset)
node _T_2183 = eq(_T_2182, UInt<1>(0h0))
when _T_2183 :
node _T_2184 = eq(_T_2181, UInt<1>(0h0))
when _T_2184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2181, UInt<1>(0h1), "") : assert_180
node _T_2185 = eq(io.in.d.bits.denied, denied)
node _T_2186 = asUInt(reset)
node _T_2187 = eq(_T_2186, UInt<1>(0h0))
when _T_2187 :
node _T_2188 = eq(_T_2185, UInt<1>(0h0))
when _T_2188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2185, UInt<1>(0h1), "") : assert_181
node _T_2189 = and(io.in.d.ready, io.in.d.valid)
node _T_2190 = and(_T_2189, d_first)
when _T_2190 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2191 = eq(b_first, UInt<1>(0h0))
node _T_2192 = and(io.in.b.valid, _T_2191)
when _T_2192 :
node _T_2193 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2194 = asUInt(reset)
node _T_2195 = eq(_T_2194, UInt<1>(0h0))
when _T_2195 :
node _T_2196 = eq(_T_2193, UInt<1>(0h0))
when _T_2196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2193, UInt<1>(0h1), "") : assert_182
node _T_2197 = eq(io.in.b.bits.param, param_2)
node _T_2198 = asUInt(reset)
node _T_2199 = eq(_T_2198, UInt<1>(0h0))
when _T_2199 :
node _T_2200 = eq(_T_2197, UInt<1>(0h0))
when _T_2200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2197, UInt<1>(0h1), "") : assert_183
node _T_2201 = eq(io.in.b.bits.size, size_2)
node _T_2202 = asUInt(reset)
node _T_2203 = eq(_T_2202, UInt<1>(0h0))
when _T_2203 :
node _T_2204 = eq(_T_2201, UInt<1>(0h0))
when _T_2204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2201, UInt<1>(0h1), "") : assert_184
node _T_2205 = eq(io.in.b.bits.source, source_2)
node _T_2206 = asUInt(reset)
node _T_2207 = eq(_T_2206, UInt<1>(0h0))
when _T_2207 :
node _T_2208 = eq(_T_2205, UInt<1>(0h0))
when _T_2208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2205, UInt<1>(0h1), "") : assert_185
node _T_2209 = eq(io.in.b.bits.address, address_1)
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_186
node _T_2213 = and(io.in.b.ready, io.in.b.valid)
node _T_2214 = and(_T_2213, b_first)
when _T_2214 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2215 = eq(c_first, UInt<1>(0h0))
node _T_2216 = and(io.in.c.valid, _T_2215)
when _T_2216 :
node _T_2217 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
node _T_2220 = eq(_T_2217, UInt<1>(0h0))
when _T_2220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2217, UInt<1>(0h1), "") : assert_187
node _T_2221 = eq(io.in.c.bits.param, param_3)
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
node _T_2224 = eq(_T_2221, UInt<1>(0h0))
when _T_2224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2221, UInt<1>(0h1), "") : assert_188
node _T_2225 = eq(io.in.c.bits.size, size_3)
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(_T_2225, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2225, UInt<1>(0h1), "") : assert_189
node _T_2229 = eq(io.in.c.bits.source, source_3)
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(_T_2229, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2229, UInt<1>(0h1), "") : assert_190
node _T_2233 = eq(io.in.c.bits.address, address_2)
node _T_2234 = asUInt(reset)
node _T_2235 = eq(_T_2234, UInt<1>(0h0))
when _T_2235 :
node _T_2236 = eq(_T_2233, UInt<1>(0h0))
when _T_2236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2233, UInt<1>(0h1), "") : assert_191
node _T_2237 = and(io.in.c.ready, io.in.c.valid)
node _T_2238 = and(_T_2237, c_first)
when _T_2238 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<81>, clock, reset, UInt<81>(0h0)
regreset inflight_opcodes : UInt<324>, clock, reset, UInt<324>(0h0)
regreset inflight_sizes : UInt<324>, clock, reset, UInt<324>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<81>
connect a_set, UInt<81>(0h0)
wire a_set_wo_ready : UInt<81>
connect a_set_wo_ready, UInt<81>(0h0)
wire a_opcodes_set : UInt<324>
connect a_opcodes_set, UInt<324>(0h0)
wire a_sizes_set : UInt<324>
connect a_sizes_set, UInt<324>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_2239 = and(io.in.a.valid, a_first_1)
node _T_2240 = and(_T_2239, UInt<1>(0h1))
when _T_2240 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2241 = and(io.in.a.ready, io.in.a.valid)
node _T_2242 = and(_T_2241, a_first_1)
node _T_2243 = and(_T_2242, UInt<1>(0h1))
when _T_2243 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2244 = dshr(inflight, io.in.a.bits.source)
node _T_2245 = bits(_T_2244, 0, 0)
node _T_2246 = eq(_T_2245, UInt<1>(0h0))
node _T_2247 = asUInt(reset)
node _T_2248 = eq(_T_2247, UInt<1>(0h0))
when _T_2248 :
node _T_2249 = eq(_T_2246, UInt<1>(0h0))
when _T_2249 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2246, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<81>
connect d_clr, UInt<81>(0h0)
wire d_clr_wo_ready : UInt<81>
connect d_clr_wo_ready, UInt<81>(0h0)
wire d_opcodes_clr : UInt<324>
connect d_opcodes_clr, UInt<324>(0h0)
wire d_sizes_clr : UInt<324>
connect d_sizes_clr, UInt<324>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2250 = and(io.in.d.valid, d_first_1)
node _T_2251 = and(_T_2250, UInt<1>(0h1))
node _T_2252 = eq(d_release_ack, UInt<1>(0h0))
node _T_2253 = and(_T_2251, _T_2252)
when _T_2253 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2254 = and(io.in.d.ready, io.in.d.valid)
node _T_2255 = and(_T_2254, d_first_1)
node _T_2256 = and(_T_2255, UInt<1>(0h1))
node _T_2257 = eq(d_release_ack, UInt<1>(0h0))
node _T_2258 = and(_T_2256, _T_2257)
when _T_2258 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2259 = and(io.in.d.valid, d_first_1)
node _T_2260 = and(_T_2259, UInt<1>(0h1))
node _T_2261 = eq(d_release_ack, UInt<1>(0h0))
node _T_2262 = and(_T_2260, _T_2261)
when _T_2262 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2263 = dshr(inflight, io.in.d.bits.source)
node _T_2264 = bits(_T_2263, 0, 0)
node _T_2265 = or(_T_2264, same_cycle_resp)
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
node _T_2268 = eq(_T_2265, UInt<1>(0h0))
when _T_2268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2265, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2269 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2270 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2271 = or(_T_2269, _T_2270)
node _T_2272 = asUInt(reset)
node _T_2273 = eq(_T_2272, UInt<1>(0h0))
when _T_2273 :
node _T_2274 = eq(_T_2271, UInt<1>(0h0))
when _T_2274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2271, UInt<1>(0h1), "") : assert_194
node _T_2275 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2276 = asUInt(reset)
node _T_2277 = eq(_T_2276, UInt<1>(0h0))
when _T_2277 :
node _T_2278 = eq(_T_2275, UInt<1>(0h0))
when _T_2278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2275, UInt<1>(0h1), "") : assert_195
else :
node _T_2279 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2280 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2281 = or(_T_2279, _T_2280)
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
node _T_2284 = eq(_T_2281, UInt<1>(0h0))
when _T_2284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2281, UInt<1>(0h1), "") : assert_196
node _T_2285 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2286 = asUInt(reset)
node _T_2287 = eq(_T_2286, UInt<1>(0h0))
when _T_2287 :
node _T_2288 = eq(_T_2285, UInt<1>(0h0))
when _T_2288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2285, UInt<1>(0h1), "") : assert_197
node _T_2289 = and(io.in.d.valid, d_first_1)
node _T_2290 = and(_T_2289, a_first_1)
node _T_2291 = and(_T_2290, io.in.a.valid)
node _T_2292 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2293 = and(_T_2291, _T_2292)
node _T_2294 = eq(d_release_ack, UInt<1>(0h0))
node _T_2295 = and(_T_2293, _T_2294)
when _T_2295 :
node _T_2296 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2297 = or(_T_2296, io.in.a.ready)
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
node _T_2300 = eq(_T_2297, UInt<1>(0h0))
when _T_2300 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2297, UInt<1>(0h1), "") : assert_198
node _T_2301 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2302 = orr(a_set_wo_ready)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
node _T_2304 = or(_T_2301, _T_2303)
node _T_2305 = asUInt(reset)
node _T_2306 = eq(_T_2305, UInt<1>(0h0))
when _T_2306 :
node _T_2307 = eq(_T_2304, UInt<1>(0h0))
when _T_2307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2304, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_72
node _T_2308 = orr(inflight)
node _T_2309 = eq(_T_2308, UInt<1>(0h0))
node _T_2310 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2311 = or(_T_2309, _T_2310)
node _T_2312 = lt(watchdog, plusarg_reader.out)
node _T_2313 = or(_T_2311, _T_2312)
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(_T_2313, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2313, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2317 = and(io.in.a.ready, io.in.a.valid)
node _T_2318 = and(io.in.d.ready, io.in.d.valid)
node _T_2319 = or(_T_2317, _T_2318)
when _T_2319 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<81>, clock, reset, UInt<81>(0h0)
regreset inflight_opcodes_1 : UInt<324>, clock, reset, UInt<324>(0h0)
regreset inflight_sizes_1 : UInt<324>, clock, reset, UInt<324>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<2>, clock, reset, UInt<2>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<81>
connect c_set, UInt<81>(0h0)
wire c_set_wo_ready : UInt<81>
connect c_set_wo_ready, UInt<81>(0h0)
wire c_opcodes_set : UInt<324>
connect c_opcodes_set, UInt<324>(0h0)
wire c_sizes_set : UInt<324>
connect c_sizes_set, UInt<324>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
node _T_2320 = and(io.in.c.valid, c_first_1)
node _T_2321 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2322 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2323 = and(_T_2321, _T_2322)
node _T_2324 = and(_T_2320, _T_2323)
when _T_2324 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2325 = and(io.in.c.ready, io.in.c.valid)
node _T_2326 = and(_T_2325, c_first_1)
node _T_2327 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2328 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2329 = and(_T_2327, _T_2328)
node _T_2330 = and(_T_2326, _T_2329)
when _T_2330 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2331 = dshr(inflight_1, io.in.c.bits.source)
node _T_2332 = bits(_T_2331, 0, 0)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
node _T_2334 = asUInt(reset)
node _T_2335 = eq(_T_2334, UInt<1>(0h0))
when _T_2335 :
node _T_2336 = eq(_T_2333, UInt<1>(0h0))
when _T_2336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2333, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<81>
connect d_clr_1, UInt<81>(0h0)
wire d_clr_wo_ready_1 : UInt<81>
connect d_clr_wo_ready_1, UInt<81>(0h0)
wire d_opcodes_clr_1 : UInt<324>
connect d_opcodes_clr_1, UInt<324>(0h0)
wire d_sizes_clr_1 : UInt<324>
connect d_sizes_clr_1, UInt<324>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2337 = and(io.in.d.valid, d_first_2)
node _T_2338 = and(_T_2337, UInt<1>(0h1))
node _T_2339 = and(_T_2338, d_release_ack_1)
when _T_2339 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2340 = and(io.in.d.ready, io.in.d.valid)
node _T_2341 = and(_T_2340, d_first_2)
node _T_2342 = and(_T_2341, UInt<1>(0h1))
node _T_2343 = and(_T_2342, d_release_ack_1)
when _T_2343 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2344 = and(io.in.d.valid, d_first_2)
node _T_2345 = and(_T_2344, UInt<1>(0h1))
node _T_2346 = and(_T_2345, d_release_ack_1)
when _T_2346 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2347 = dshr(inflight_1, io.in.d.bits.source)
node _T_2348 = bits(_T_2347, 0, 0)
node _T_2349 = or(_T_2348, same_cycle_resp_1)
node _T_2350 = asUInt(reset)
node _T_2351 = eq(_T_2350, UInt<1>(0h0))
when _T_2351 :
node _T_2352 = eq(_T_2349, UInt<1>(0h0))
when _T_2352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2349, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2353 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2354 = asUInt(reset)
node _T_2355 = eq(_T_2354, UInt<1>(0h0))
when _T_2355 :
node _T_2356 = eq(_T_2353, UInt<1>(0h0))
when _T_2356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2353, UInt<1>(0h1), "") : assert_203
else :
node _T_2357 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2358 = asUInt(reset)
node _T_2359 = eq(_T_2358, UInt<1>(0h0))
when _T_2359 :
node _T_2360 = eq(_T_2357, UInt<1>(0h0))
when _T_2360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2357, UInt<1>(0h1), "") : assert_204
node _T_2361 = and(io.in.d.valid, d_first_2)
node _T_2362 = and(_T_2361, c_first_1)
node _T_2363 = and(_T_2362, io.in.c.valid)
node _T_2364 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2365 = and(_T_2363, _T_2364)
node _T_2366 = and(_T_2365, d_release_ack_1)
node _T_2367 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2368 = and(_T_2366, _T_2367)
when _T_2368 :
node _T_2369 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2370 = or(_T_2369, io.in.c.ready)
node _T_2371 = asUInt(reset)
node _T_2372 = eq(_T_2371, UInt<1>(0h0))
when _T_2372 :
node _T_2373 = eq(_T_2370, UInt<1>(0h0))
when _T_2373 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2370, UInt<1>(0h1), "") : assert_205
node _T_2374 = orr(c_set_wo_ready)
when _T_2374 :
node _T_2375 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2376 = asUInt(reset)
node _T_2377 = eq(_T_2376, UInt<1>(0h0))
when _T_2377 :
node _T_2378 = eq(_T_2375, UInt<1>(0h0))
when _T_2378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2375, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_73
node _T_2379 = orr(inflight_1)
node _T_2380 = eq(_T_2379, UInt<1>(0h0))
node _T_2381 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2382 = or(_T_2380, _T_2381)
node _T_2383 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2384 = or(_T_2382, _T_2383)
node _T_2385 = asUInt(reset)
node _T_2386 = eq(_T_2385, UInt<1>(0h0))
when _T_2386 :
node _T_2387 = eq(_T_2384, UInt<1>(0h0))
when _T_2387 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2384, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2388 = and(io.in.c.ready, io.in.c.valid)
node _T_2389 = and(io.in.d.ready, io.in.d.valid)
node _T_2390 = or(_T_2388, _T_2389)
when _T_2390 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<12>, clock, reset, UInt<12>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<2>, clock, reset, UInt<2>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<12>
connect d_set, UInt<12>(0h0)
node _T_2391 = and(io.in.d.ready, io.in.d.valid)
node _T_2392 = and(_T_2391, d_first_3)
node _T_2393 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2394 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2395 = eq(_T_2394, UInt<1>(0h0))
node _T_2396 = and(_T_2393, _T_2395)
node _T_2397 = and(_T_2392, _T_2396)
when _T_2397 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2398 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2399 = bits(_T_2398, 0, 0)
node _T_2400 = eq(_T_2399, UInt<1>(0h0))
node _T_2401 = asUInt(reset)
node _T_2402 = eq(_T_2401, UInt<1>(0h0))
when _T_2402 :
node _T_2403 = eq(_T_2400, UInt<1>(0h0))
when _T_2403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2400, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<12>
connect e_clr, UInt<12>(0h0)
node _T_2404 = and(io.in.e.ready, io.in.e.valid)
node _T_2405 = and(_T_2404, UInt<1>(0h1))
node _T_2406 = and(_T_2405, UInt<1>(0h1))
when _T_2406 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2407 = or(d_set, inflight_2)
node _T_2408 = dshr(_T_2407, io.in.e.bits.sink)
node _T_2409 = bits(_T_2408, 0, 0)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:127:13)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_36( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_76 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_82 = 1'h1; // @[Parameters.scala:57:20]
wire mask_sub_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire mask_acc_16 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_17 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_18 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_19 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_20 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_21 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_22 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_23 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_24 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_25 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_26 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_27 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_28 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_29 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_30 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_31 = 1'h1; // @[Misc.scala:215:29]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_25 = 1'h1; // @[Parameters.scala:46:9]
wire _legal_source_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _legal_source_WIRE_5 = 1'h1; // @[Parameters.scala:1138:31]
wire legal_source = 1'h1; // @[Monitor.scala:168:113]
wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_103 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_107 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_109 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_113 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_115 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_120 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_122 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_126 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_128 = 1'h1; // @[Parameters.scala:57:20]
wire _b_first_beats1_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [6:0] io_in_b_bits_source = 7'h20; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_67 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_68 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_69 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_70 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_71 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_1 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_2 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_3 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_4 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_uncommonBits_T_5 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _legal_source_T_52 = 7'h20; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_53 = 7'h20; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_54 = 7'h20; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_55 = 7'h20; // @[Mux.scala:30:73]
wire [6:0] _legal_source_WIRE_1 = 7'h20; // @[Mux.scala:30:73]
wire [6:0] _uncommonBits_T_72 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_73 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_74 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_75 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_76 = 7'h20; // @[Parameters.scala:52:29]
wire [6:0] _uncommonBits_T_77 = 7'h20; // @[Parameters.scala:52:29]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Monitor.scala:36:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask_1 = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T_8 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire _legal_source_T = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_T_2 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_4 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_6 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_8 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_10 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_12 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_14 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_16 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_18 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_20 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_22 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_24 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_27 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_29 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_31 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_33 = 1'h0; // @[Parameters.scala:54:32]
wire _legal_source_T_35 = 1'h0; // @[Parameters.scala:54:67]
wire _legal_source_T_37 = 1'h0; // @[Parameters.scala:56:48]
wire _legal_source_T_38 = 1'h0; // @[Parameters.scala:46:9]
wire _legal_source_WIRE_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1_0 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_3 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_4 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_6 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_7 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_8 = 1'h0; // @[Parameters.scala:1138:31]
wire _legal_source_T_46 = 1'h0; // @[Mux.scala:30:73]
wire b_first_beats1_opdata = 1'h0; // @[Edges.scala:97:28]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_5 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _legal_source_T_26 = 3'h2; // @[Parameters.scala:54:10]
wire [2:0] _legal_source_T_32 = 3'h2; // @[Parameters.scala:54:10]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [1:0] uncommonBits_66 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_67 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_68 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_69 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_1 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_2 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] legal_source_uncommonBits_3 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_72 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_73 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_74 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] uncommonBits_75 = 2'h0; // @[Parameters.scala:52:56]
wire [1:0] b_first_beats1 = 2'h0; // @[Edges.scala:221:14]
wire [1:0] b_first_count = 2'h0; // @[Edges.scala:234:25]
wire [1:0] mask_lo_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] b_first_beats1_decode = 2'h3; // @[Edges.scala:220:59]
wire [5:0] is_aligned_mask_1 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _b_first_beats1_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] _is_aligned_mask_T_3 = 6'h0; // @[package.scala:243:76]
wire [5:0] _legal_source_T_47 = 6'h0; // @[Mux.scala:30:73]
wire [5:0] _b_first_beats1_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] _is_aligned_mask_T_2 = 13'hFC0; // @[package.scala:243:71]
wire [12:0] _b_first_beats1_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [3:0] uncommonBits_70 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_71 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] legal_source_uncommonBits_4 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] legal_source_uncommonBits_5 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_76 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] uncommonBits_77 = 4'h0; // @[Parameters.scala:52:56]
wire [6:0] _legal_source_T_39 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_40 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_41 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_42 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_43 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_48 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_49 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_50 = 7'h0; // @[Mux.scala:30:73]
wire [6:0] _legal_source_T_51 = 7'h0; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_45 = 5'h0; // @[Mux.scala:30:73]
wire [5:0] _legal_source_T_44 = 6'h20; // @[Mux.scala:30:73]
wire [4:0] _legal_source_T_1 = 5'h8; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_7 = 5'h8; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_13 = 5'h8; // @[Parameters.scala:54:10]
wire [4:0] _legal_source_T_19 = 5'h8; // @[Parameters.scala:54:10]
wire [7:0] mask_lo_1 = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi_1 = 8'hFF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi_1 = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH_1 = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_3 = 4'h6; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_78 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_79 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_80 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_81 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_82 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_83 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_84 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_85 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_86 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_87 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_88 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_89 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_90 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_91 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_92 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_93 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_94 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_95 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_96 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_97 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_98 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_99 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_100 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_101 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_102 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_103 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_104 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_105 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_106 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_107 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_26 = io_in_a_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_32 = io_in_a_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_45 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [3:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = io_in_a_bits_size_0[2]; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = io_in_d_bits_source_0 == 7'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_47 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_53 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_48 = _source_ok_T_47 == 5'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_52; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_54 = _source_ok_T_53 == 5'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_72 = io_in_d_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_78 = io_in_d_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_73 = _source_ok_T_72 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_77 = _source_ok_T_75; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_77; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_79 = _source_ok_T_78 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_83 = _source_ok_T_81; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_86 = _source_ok_T_85 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_87 = _source_ok_T_86 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_88 = _source_ok_T_87 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_91 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :309:31]
wire [27:0] _GEN_0 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = {io_in_b_bits_address_0[31:28], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire address_ok = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire [31:0] _is_aligned_T_1 = {26'h0, io_in_b_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_4 = mask_sub_sub_0_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_5 = mask_sub_sub_1_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_6 = mask_sub_sub_2_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_7 = mask_sub_sub_3_2_1; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_16 = mask_eq_16; // @[Misc.scala:214:27, :215:38]
wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_17 = mask_eq_17; // @[Misc.scala:214:27, :215:38]
wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_18 = mask_eq_18; // @[Misc.scala:214:27, :215:38]
wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_19 = mask_eq_19; // @[Misc.scala:214:27, :215:38]
wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_20 = mask_eq_20; // @[Misc.scala:214:27, :215:38]
wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_21 = mask_eq_21; // @[Misc.scala:214:27, :215:38]
wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_22 = mask_eq_22; // @[Misc.scala:214:27, :215:38]
wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_23 = mask_eq_23; // @[Misc.scala:214:27, :215:38]
wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_24 = mask_eq_24; // @[Misc.scala:214:27, :215:38]
wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_25 = mask_eq_25; // @[Misc.scala:214:27, :215:38]
wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_26 = mask_eq_26; // @[Misc.scala:214:27, :215:38]
wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_27 = mask_eq_27; // @[Misc.scala:214:27, :215:38]
wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_28 = mask_eq_28; // @[Misc.scala:214:27, :215:38]
wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_29 = mask_eq_29; // @[Misc.scala:214:27, :215:38]
wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_30 = mask_eq_30; // @[Misc.scala:214:27, :215:38]
wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_31 = mask_eq_31; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_92 = io_in_c_bits_source_0 == 7'h50; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_93 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_99 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_105 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_111 = io_in_c_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_94 = _source_ok_T_93 == 5'h10; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_98; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_100 = _source_ok_T_99 == 5'h11; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_104 = _source_ok_T_102; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_2 = _source_ok_T_104; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_14 = _source_ok_uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_106 = _source_ok_T_105 == 5'h12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_108 = _source_ok_T_106; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_110 = _source_ok_T_108; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_3 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_15 = _source_ok_uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_112 = _source_ok_T_111 == 5'h13; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_114 = _source_ok_T_112; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_116 = _source_ok_T_114; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_4 = _source_ok_T_116; // @[Parameters.scala:1138:31]
wire _source_ok_T_117 = io_in_c_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_5 = _source_ok_T_117; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_16 = _source_ok_uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] _source_ok_T_118 = io_in_c_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire [2:0] _source_ok_T_124 = io_in_c_bits_source_0[6:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_119 = _source_ok_T_118 == 3'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_121 = _source_ok_T_119; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_123 = _source_ok_T_121; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_6 = _source_ok_T_123; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_17 = _source_ok_uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_125 = _source_ok_T_124 == 3'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_127 = _source_ok_T_125; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_129 = _source_ok_T_127; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_7 = _source_ok_T_129; // @[Parameters.scala:1138:31]
wire _source_ok_T_130 = io_in_c_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_8 = _source_ok_T_130; // @[Parameters.scala:1138:31]
wire _source_ok_T_131 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_2_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_2_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_2_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_2_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_2_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_137 | _source_ok_WIRE_2_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN_1 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_1; // @[package.scala:243:71]
wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_1; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [27:0] _GEN_2 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_78 = _uncommonBits_T_78[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_79 = _uncommonBits_T_79[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_80 = _uncommonBits_T_80[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_81 = _uncommonBits_T_81[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_82 = _uncommonBits_T_82[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_83 = _uncommonBits_T_83[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_84 = _uncommonBits_T_84[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_85 = _uncommonBits_T_85[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_86 = _uncommonBits_T_86[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_87 = _uncommonBits_T_87[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_88 = _uncommonBits_T_88[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_89 = _uncommonBits_T_89[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_90 = _uncommonBits_T_90[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_91 = _uncommonBits_T_91[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_92 = _uncommonBits_T_92[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_93 = _uncommonBits_T_93[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_94 = _uncommonBits_T_94[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_95 = _uncommonBits_T_95[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_96 = _uncommonBits_T_96[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_97 = _uncommonBits_T_97[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_98 = _uncommonBits_T_98[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_99 = _uncommonBits_T_99[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_100 = _uncommonBits_T_100[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_101 = _uncommonBits_T_101[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_102 = _uncommonBits_T_102[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_103 = _uncommonBits_T_103[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_104 = _uncommonBits_T_104[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_105 = _uncommonBits_T_105[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_106 = _uncommonBits_T_106[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_107 = _uncommonBits_T_107[3:0]; // @[Parameters.scala:52:{29,56}]
wire sink_ok_1 = io_in_e_bits_sink_0[3:2] != 2'h3; // @[Monitor.scala:36:7, :367:31]
wire _T_2317 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2317; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2317; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T = {1'h0, a_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1 = _a_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2391 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2391; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2391; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_3 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_3; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_3; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T = {1'h0, d_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1 = _d_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
reg [1:0] b_first_counter; // @[Edges.scala:229:27]
wire [2:0] _b_first_counter1_T = {1'h0, b_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] b_first_counter1 = _b_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] _b_first_counter_T = b_first ? 2'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2388 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2388; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2388; // @[Decoupled.scala:51:35]
wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:4]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [1:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T = {1'h0, c_first_counter} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1 = _c_first_counter1_T[1:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [2:0] size_3; // @[Monitor.scala:517:22]
reg [6:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [80:0] inflight; // @[Monitor.scala:614:27]
reg [323:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [323:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [1:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 2'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [1:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] a_first_counter1_1 = _a_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_1 = _d_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [80:0] a_set; // @[Monitor.scala:626:34]
wire [80:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [323:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [323:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_4 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_4; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_4; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_4; // @[Monitor.scala:637:69, :791:99]
wire [323:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [323:0] _a_opcode_lookup_T_6 = {320'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [323:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[323:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [323:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [323:0] _a_size_lookup_T_6 = {320'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [323:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[323:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_5 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_5; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire _T_2243 = _T_2317 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2243 ? _a_set_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2243 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2243 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_6 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_6; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_6; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2243 ? _a_opcodes_set_T_1[323:0] : 324'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2243 ? _a_sizes_set_T_1[323:0] : 324'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [80:0] d_clr; // @[Monitor.scala:664:34]
wire [80:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [323:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [323:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_7 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_7; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_7; // @[Monitor.scala:673:46, :783:46]
wire _T_2289 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_8 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_8; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_8; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2289 & ~d_release_ack ? _d_clr_wo_ready_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire _T_2258 = _T_2391 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2258 ? _d_clr_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2258 ? _d_opcodes_clr_T_5[323:0] : 324'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2258 ? _d_sizes_clr_T_5[323:0] : 324'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [80:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [80:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [80:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [323:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [323:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [323:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [323:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [323:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [323:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [80:0] inflight_1; // @[Monitor.scala:726:35]
reg [323:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [323:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [1:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:4]; // @[package.scala:243:46]
wire [1:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 2'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [1:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [2:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] c_first_counter1_1 = _c_first_counter1_T_1[1:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [1:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_2 = _d_first_counter1_T_2[1:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [80:0] c_set; // @[Monitor.scala:738:34]
wire [80:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [323:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [323:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [323:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [323:0] _c_opcode_lookup_T_6 = {320'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [323:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[323:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [323:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [323:0] _c_size_lookup_T_6 = {320'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [323:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[323:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [127:0] _GEN_9 = 128'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_9; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_9; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire _T_2330 = _T_2388 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2330 ? _c_set_T[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2330 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2330 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [9:0] _GEN_10 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [9:0] _c_opcodes_set_T; // @[Monitor.scala:767:79]
assign _c_opcodes_set_T = _GEN_10; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T; // @[Monitor.scala:768:77]
assign _c_sizes_set_T = _GEN_10; // @[Monitor.scala:767:79, :768:77]
wire [1026:0] _c_opcodes_set_T_1 = {1023'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2330 ? _c_opcodes_set_T_1[323:0] : 324'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [1026:0] _c_sizes_set_T_1 = {1023'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2330 ? _c_sizes_set_T_1[323:0] : 324'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [80:0] d_clr_1; // @[Monitor.scala:774:34]
wire [80:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [323:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [323:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2361 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2361 & d_release_ack_1 ? _d_clr_wo_ready_T_1[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire _T_2343 = _T_2391 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2343 ? _d_clr_T_1[80:0] : 81'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2343 ? _d_opcodes_clr_T_11[323:0] : 324'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2343 ? _d_sizes_clr_T_11[323:0] : 324'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [80:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [80:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [80:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [323:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [323:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [323:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [323:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [323:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [323:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [11:0] inflight_2; // @[Monitor.scala:828:27]
wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [1:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:4]; // @[package.scala:243:46]
wire [1:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 2'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [1:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [2:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 3'h1; // @[Edges.scala:229:27, :230:28]
wire [1:0] d_first_counter1_3 = _d_first_counter1_T_3[1:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 2'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 2'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 2'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [1:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [1:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_set; // @[Monitor.scala:833:25]
wire _T_2397 = _T_2391 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [15:0] _d_set_T = 16'h1 << io_in_d_bits_sink_0; // @[OneHot.scala:58:35]
assign d_set = _T_2397 ? _d_set_T[11:0] : 12'h0; // @[OneHot.scala:58:35]
wire [11:0] e_clr; // @[Monitor.scala:839:25]
wire [15:0] _e_clr_T = 16'h1 << io_in_e_bits_sink_0; // @[OneHot.scala:58:35]
assign e_clr = io_in_e_valid_0 ? _e_clr_T[11:0] : 12'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR_2 :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 9, 6)
node req_tag = shr(req.addr, 10)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue_2
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5)
node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7)
node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9)
node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR_2( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
input io_lb_write_ready, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h2; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h2; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_source = 4'h2; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h2; // @[mshrs.scala:36:7]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] io_mem_acquire_bits_a_source = 4'h2; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata | io_lb_write_ready_0); // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_223 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_223( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_8 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_61, _T_68)
node _T_91 = or(_T_90, _T_75)
node _T_92 = or(_T_91, _T_82)
node _T_93 = or(_T_92, _T_89)
node _T_94 = or(_T_54, _T_93)
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_94, UInt<1>(0h1), "") : assert_3
node _T_98 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_135 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_136 = and(_T_134, _T_135)
node _T_137 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_142 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_143 = and(_T_141, _T_142)
node _T_144 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_149 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_150 = and(_T_148, _T_149)
node _T_151 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_156 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_157 = and(_T_155, _T_156)
node _T_158 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_161 = and(_T_159, _T_160)
node _T_162 = or(_T_105, _T_112)
node _T_163 = or(_T_162, _T_119)
node _T_164 = or(_T_163, _T_126)
node _T_165 = or(_T_164, _T_133)
node _T_166 = or(_T_165, _T_140)
node _T_167 = or(_T_166, _T_147)
node _T_168 = or(_T_167, _T_154)
node _T_169 = or(_T_168, _T_161)
node _T_170 = or(_T_98, _T_169)
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_170, UInt<1>(0h1), "") : assert_4
node _T_174 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_175 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_176 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_183 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_190 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_197 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_204 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_211 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_218 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_225 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_232 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_237 = and(_T_235, _T_236)
node _T_238 = or(_T_181, _T_188)
node _T_239 = or(_T_238, _T_195)
node _T_240 = or(_T_239, _T_202)
node _T_241 = or(_T_240, _T_209)
node _T_242 = or(_T_241, _T_216)
node _T_243 = or(_T_242, _T_223)
node _T_244 = or(_T_243, _T_230)
node _T_245 = or(_T_244, _T_237)
node _T_246 = or(_T_174, _T_245)
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_246, UInt<1>(0h1), "") : assert_5
node _T_250 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_251 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_257 = and(_T_255, _T_256)
node _T_258 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_259 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_264 = and(_T_262, _T_263)
node _T_265 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_266 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_271 = and(_T_269, _T_270)
node _T_272 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_273 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_280 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_313 = and(_T_311, _T_312)
node _T_314 = or(_T_257, _T_264)
node _T_315 = or(_T_314, _T_271)
node _T_316 = or(_T_315, _T_278)
node _T_317 = or(_T_316, _T_285)
node _T_318 = or(_T_317, _T_292)
node _T_319 = or(_T_318, _T_299)
node _T_320 = or(_T_319, _T_306)
node _T_321 = or(_T_320, _T_313)
node _T_322 = or(_T_250, _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_322, UInt<1>(0h1), "") : assert_6
node _T_326 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_335 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_342 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_349 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_356 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_363 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_370 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_377 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_384 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_385 = and(_T_383, _T_384)
node _T_386 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_389 = and(_T_387, _T_388)
node _T_390 = or(_T_333, _T_340)
node _T_391 = or(_T_390, _T_347)
node _T_392 = or(_T_391, _T_354)
node _T_393 = or(_T_392, _T_361)
node _T_394 = or(_T_393, _T_368)
node _T_395 = or(_T_394, _T_375)
node _T_396 = or(_T_395, _T_382)
node _T_397 = or(_T_396, _T_389)
node _T_398 = or(_T_326, _T_397)
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_398, UInt<1>(0h1), "") : assert_7
node _T_402 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_403 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_416 = and(_T_414, _T_415)
node _T_417 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_423 = and(_T_421, _T_422)
node _T_424 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_430 = and(_T_428, _T_429)
node _T_431 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_437 = and(_T_435, _T_436)
node _T_438 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_456 = and(_T_454, _T_455)
node _T_457 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_460 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(_T_409, _T_416)
node _T_467 = or(_T_466, _T_423)
node _T_468 = or(_T_467, _T_430)
node _T_469 = or(_T_468, _T_437)
node _T_470 = or(_T_469, _T_444)
node _T_471 = or(_T_470, _T_451)
node _T_472 = or(_T_471, _T_458)
node _T_473 = or(_T_472, _T_465)
node _T_474 = or(_T_402, _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_474, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_8( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module DecodeUnit :
input clock : Clock
input reset : Reset
output io : { enq : { flip uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, deq : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip csr_decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}, flip interrupt : UInt<1>, flip interrupt_cause : UInt<64>}
wire uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
connect uop, io.enq.uop
wire cs : { legal : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, uopc : UInt<7>, iq_type : UInt<3>, fu_code : UInt<10>, dst_type : UInt<2>, rs1_type : UInt<2>, rs2_type : UInt<2>, frs3_en : UInt<1>, imm_sel : UInt<3>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_amo : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, mem_cmd : UInt<5>, wakeup_delay : UInt<2>, bypassable : UInt<1>, is_br : UInt<1>, is_sys_pc2epc : UInt<1>, inst_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, rocc : UInt<1>}
wire cs_decoder_decoded_plaInput : UInt<32>
node cs_decoder_decoded_invInputs = not(cs_decoder_decoded_plaInput)
wire cs_decoder_decoded : UInt<53>
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5)
node cs_decoder_decoded_andMatrixOutputs_lo = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6)
node cs_decoder_decoded_andMatrixOutputs_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3)
node cs_decoder_decoded_andMatrixOutputs_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1)
node cs_decoder_decoded_andMatrixOutputs_hi = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo)
node _cs_decoder_decoded_andMatrixOutputs_T = cat(cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo)
node cs_decoder_decoded_andMatrixOutputs_77_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1)
node cs_decoder_decoded_andMatrixOutputs_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1)
node cs_decoder_decoded_andMatrixOutputs_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1)
node _cs_decoder_decoded_andMatrixOutputs_T_1 = cat(cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1)
node cs_decoder_decoded_andMatrixOutputs_84_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2)
node cs_decoder_decoded_andMatrixOutputs_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2)
node cs_decoder_decoded_andMatrixOutputs_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2)
node _cs_decoder_decoded_andMatrixOutputs_T_2 = cat(cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2)
node cs_decoder_decoded_andMatrixOutputs_8_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3)
node cs_decoder_decoded_andMatrixOutputs_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3)
node cs_decoder_decoded_andMatrixOutputs_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3)
node _cs_decoder_decoded_andMatrixOutputs_T_3 = cat(cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3)
node cs_decoder_decoded_andMatrixOutputs_29_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4)
node cs_decoder_decoded_andMatrixOutputs_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4)
node cs_decoder_decoded_andMatrixOutputs_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4)
node _cs_decoder_decoded_andMatrixOutputs_T_4 = cat(cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4)
node cs_decoder_decoded_andMatrixOutputs_124_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5)
node cs_decoder_decoded_andMatrixOutputs_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5)
node cs_decoder_decoded_andMatrixOutputs_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5)
node _cs_decoder_decoded_andMatrixOutputs_T_5 = cat(cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5)
node cs_decoder_decoded_andMatrixOutputs_102_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4)
node cs_decoder_decoded_andMatrixOutputs_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6)
node cs_decoder_decoded_andMatrixOutputs_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6)
node _cs_decoder_decoded_andMatrixOutputs_T_6 = cat(cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6)
node cs_decoder_decoded_andMatrixOutputs_85_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7)
node cs_decoder_decoded_andMatrixOutputs_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7)
node cs_decoder_decoded_andMatrixOutputs_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7)
node _cs_decoder_decoded_andMatrixOutputs_T_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7)
node cs_decoder_decoded_andMatrixOutputs_56_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8)
node cs_decoder_decoded_andMatrixOutputs_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_6)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8)
node cs_decoder_decoded_andMatrixOutputs_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_8)
node _cs_decoder_decoded_andMatrixOutputs_T_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8)
node cs_decoder_decoded_andMatrixOutputs_71_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7)
node cs_decoder_decoded_andMatrixOutputs_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_7)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9)
node cs_decoder_decoded_andMatrixOutputs_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_9)
node _cs_decoder_decoded_andMatrixOutputs_T_9 = cat(cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9)
node cs_decoder_decoded_andMatrixOutputs_130_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10)
node cs_decoder_decoded_andMatrixOutputs_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10)
node cs_decoder_decoded_andMatrixOutputs_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10)
node _cs_decoder_decoded_andMatrixOutputs_T_10 = cat(cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10)
node cs_decoder_decoded_andMatrixOutputs_34_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11)
node cs_decoder_decoded_andMatrixOutputs_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11)
node cs_decoder_decoded_andMatrixOutputs_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10)
node _cs_decoder_decoded_andMatrixOutputs_T_11 = cat(cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11)
node cs_decoder_decoded_andMatrixOutputs_163_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8)
node cs_decoder_decoded_andMatrixOutputs_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_8)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12)
node cs_decoder_decoded_andMatrixOutputs_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11)
node _cs_decoder_decoded_andMatrixOutputs_T_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12)
node cs_decoder_decoded_andMatrixOutputs_48_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13)
node cs_decoder_decoded_andMatrixOutputs_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_9)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13)
node cs_decoder_decoded_andMatrixOutputs_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12)
node _cs_decoder_decoded_andMatrixOutputs_T_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13)
node cs_decoder_decoded_andMatrixOutputs_110_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_10)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13)
node _cs_decoder_decoded_andMatrixOutputs_T_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14)
node cs_decoder_decoded_andMatrixOutputs_170_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4)
node cs_decoder_decoded_andMatrixOutputs_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_11)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14)
node _cs_decoder_decoded_andMatrixOutputs_T_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15)
node cs_decoder_decoded_andMatrixOutputs_5_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_12)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15)
node _cs_decoder_decoded_andMatrixOutputs_T_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16)
node cs_decoder_decoded_andMatrixOutputs_75_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_13)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_16)
node _cs_decoder_decoded_andMatrixOutputs_T_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17)
node cs_decoder_decoded_andMatrixOutputs_12_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_lo_14)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_17)
node _cs_decoder_decoded_andMatrixOutputs_T_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18)
node cs_decoder_decoded_andMatrixOutputs_35_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_15)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_18)
node _cs_decoder_decoded_andMatrixOutputs_T_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19)
node cs_decoder_decoded_andMatrixOutputs_30_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_16)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_19)
node _cs_decoder_decoded_andMatrixOutputs_T_20 = cat(cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20)
node cs_decoder_decoded_andMatrixOutputs_24_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21)
node cs_decoder_decoded_andMatrixOutputs_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21)
node cs_decoder_decoded_andMatrixOutputs_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_20)
node _cs_decoder_decoded_andMatrixOutputs_T_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21)
node cs_decoder_decoded_andMatrixOutputs_144_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_17)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_21)
node _cs_decoder_decoded_andMatrixOutputs_T_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22)
node cs_decoder_decoded_andMatrixOutputs_28_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_18)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8)
node cs_decoder_decoded_andMatrixOutputs_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_22)
node _cs_decoder_decoded_andMatrixOutputs_T_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23)
node cs_decoder_decoded_andMatrixOutputs_126_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24)
node cs_decoder_decoded_andMatrixOutputs_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24)
node _cs_decoder_decoded_andMatrixOutputs_T_24 = cat(cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24)
node cs_decoder_decoded_andMatrixOutputs_162_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25)
node cs_decoder_decoded_andMatrixOutputs_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25)
node cs_decoder_decoded_andMatrixOutputs_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25)
node _cs_decoder_decoded_andMatrixOutputs_T_25 = cat(cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25)
node cs_decoder_decoded_andMatrixOutputs_1_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25)
node cs_decoder_decoded_andMatrixOutputs_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26)
node cs_decoder_decoded_andMatrixOutputs_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23)
node _cs_decoder_decoded_andMatrixOutputs_T_26 = cat(cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26)
node cs_decoder_decoded_andMatrixOutputs_17_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26)
node cs_decoder_decoded_andMatrixOutputs_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27)
node cs_decoder_decoded_andMatrixOutputs_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24)
node _cs_decoder_decoded_andMatrixOutputs_T_27 = cat(cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27)
node cs_decoder_decoded_andMatrixOutputs_98_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27)
node cs_decoder_decoded_andMatrixOutputs_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_lo_20)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28)
node cs_decoder_decoded_andMatrixOutputs_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25)
node _cs_decoder_decoded_andMatrixOutputs_T_28 = cat(cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28)
node cs_decoder_decoded_andMatrixOutputs_27_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28)
node cs_decoder_decoded_andMatrixOutputs_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29)
node cs_decoder_decoded_andMatrixOutputs_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26)
node _cs_decoder_decoded_andMatrixOutputs_T_29 = cat(cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29)
node cs_decoder_decoded_andMatrixOutputs_105_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29)
node cs_decoder_decoded_andMatrixOutputs_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_21)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30)
node cs_decoder_decoded_andMatrixOutputs_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27)
node _cs_decoder_decoded_andMatrixOutputs_T_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30)
node cs_decoder_decoded_andMatrixOutputs_122_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30)
node cs_decoder_decoded_andMatrixOutputs_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_22)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31)
node cs_decoder_decoded_andMatrixOutputs_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28)
node _cs_decoder_decoded_andMatrixOutputs_T_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31)
node cs_decoder_decoded_andMatrixOutputs_38_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_31)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31)
node cs_decoder_decoded_andMatrixOutputs_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_23)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32)
node cs_decoder_decoded_andMatrixOutputs_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29)
node _cs_decoder_decoded_andMatrixOutputs_T_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32)
node cs_decoder_decoded_andMatrixOutputs_165_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_32)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14)
node cs_decoder_decoded_andMatrixOutputs_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_24)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33)
node cs_decoder_decoded_andMatrixOutputs_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30)
node _cs_decoder_decoded_andMatrixOutputs_T_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33)
node cs_decoder_decoded_andMatrixOutputs_19_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_33)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15)
node cs_decoder_decoded_andMatrixOutputs_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_25)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34)
node cs_decoder_decoded_andMatrixOutputs_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31)
node _cs_decoder_decoded_andMatrixOutputs_T_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34)
node cs_decoder_decoded_andMatrixOutputs_118_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_34)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16)
node cs_decoder_decoded_andMatrixOutputs_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_26)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35)
node cs_decoder_decoded_andMatrixOutputs_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32)
node _cs_decoder_decoded_andMatrixOutputs_T_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35)
node cs_decoder_decoded_andMatrixOutputs_153_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_35)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15)
node cs_decoder_decoded_andMatrixOutputs_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_27)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9)
node cs_decoder_decoded_andMatrixOutputs_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33)
node _cs_decoder_decoded_andMatrixOutputs_T_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36)
node cs_decoder_decoded_andMatrixOutputs_141_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_36)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18)
node cs_decoder_decoded_andMatrixOutputs_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_28)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37)
node cs_decoder_decoded_andMatrixOutputs_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34)
node _cs_decoder_decoded_andMatrixOutputs_T_37 = cat(cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37)
node cs_decoder_decoded_andMatrixOutputs_168_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_37)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17)
node cs_decoder_decoded_andMatrixOutputs_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10)
node cs_decoder_decoded_andMatrixOutputs_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35)
node _cs_decoder_decoded_andMatrixOutputs_T_38 = cat(cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38)
node cs_decoder_decoded_andMatrixOutputs_73_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_38)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8)
node cs_decoder_decoded_andMatrixOutputs_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11)
node cs_decoder_decoded_andMatrixOutputs_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36)
node _cs_decoder_decoded_andMatrixOutputs_T_39 = cat(cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39)
node cs_decoder_decoded_andMatrixOutputs_25_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_39)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39)
node cs_decoder_decoded_andMatrixOutputs_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40)
node cs_decoder_decoded_andMatrixOutputs_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37)
node _cs_decoder_decoded_andMatrixOutputs_T_40 = cat(cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40)
node cs_decoder_decoded_andMatrixOutputs_79_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_40)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38)
node cs_decoder_decoded_andMatrixOutputs_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41)
node cs_decoder_decoded_andMatrixOutputs_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38)
node _cs_decoder_decoded_andMatrixOutputs_T_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41)
node cs_decoder_decoded_andMatrixOutputs_114_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_41)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33)
node cs_decoder_decoded_andMatrixOutputs_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42)
node cs_decoder_decoded_andMatrixOutputs_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39)
node _cs_decoder_decoded_andMatrixOutputs_T_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42)
node cs_decoder_decoded_andMatrixOutputs_174_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_42)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42)
node cs_decoder_decoded_andMatrixOutputs_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43)
node cs_decoder_decoded_andMatrixOutputs_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40)
node _cs_decoder_decoded_andMatrixOutputs_T_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43)
node cs_decoder_decoded_andMatrixOutputs_139_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_43)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9)
node cs_decoder_decoded_andMatrixOutputs_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_34)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12)
node cs_decoder_decoded_andMatrixOutputs_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41)
node _cs_decoder_decoded_andMatrixOutputs_T_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44)
node cs_decoder_decoded_andMatrixOutputs_43_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_44)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10)
node cs_decoder_decoded_andMatrixOutputs_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_35)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13)
node cs_decoder_decoded_andMatrixOutputs_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42)
node _cs_decoder_decoded_andMatrixOutputs_T_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45)
node cs_decoder_decoded_andMatrixOutputs_67_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_45)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36)
node cs_decoder_decoded_andMatrixOutputs_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_36)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46)
node cs_decoder_decoded_andMatrixOutputs_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43)
node _cs_decoder_decoded_andMatrixOutputs_T_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46)
node cs_decoder_decoded_andMatrixOutputs_18_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_46)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11)
node cs_decoder_decoded_andMatrixOutputs_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_37)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14)
node cs_decoder_decoded_andMatrixOutputs_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44)
node _cs_decoder_decoded_andMatrixOutputs_T_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47)
node cs_decoder_decoded_andMatrixOutputs_108_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_47)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12)
node cs_decoder_decoded_andMatrixOutputs_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_38)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15)
node cs_decoder_decoded_andMatrixOutputs_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45)
node _cs_decoder_decoded_andMatrixOutputs_T_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48)
node cs_decoder_decoded_andMatrixOutputs_46_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_48)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13)
node cs_decoder_decoded_andMatrixOutputs_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_39)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16)
node cs_decoder_decoded_andMatrixOutputs_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46)
node _cs_decoder_decoded_andMatrixOutputs_T_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49)
node cs_decoder_decoded_andMatrixOutputs_10_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_49)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14)
node cs_decoder_decoded_andMatrixOutputs_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_40)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17)
node cs_decoder_decoded_andMatrixOutputs_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47)
node _cs_decoder_decoded_andMatrixOutputs_T_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50)
node cs_decoder_decoded_andMatrixOutputs_82_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_50)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15)
node cs_decoder_decoded_andMatrixOutputs_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_41)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18)
node cs_decoder_decoded_andMatrixOutputs_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48)
node _cs_decoder_decoded_andMatrixOutputs_T_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51)
node cs_decoder_decoded_andMatrixOutputs_26_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_51)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16)
node cs_decoder_decoded_andMatrixOutputs_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_42)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19)
node cs_decoder_decoded_andMatrixOutputs_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49)
node _cs_decoder_decoded_andMatrixOutputs_T_52 = cat(cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52)
node cs_decoder_decoded_andMatrixOutputs_42_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_52)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17)
node cs_decoder_decoded_andMatrixOutputs_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_43)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20)
node cs_decoder_decoded_andMatrixOutputs_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50)
node _cs_decoder_decoded_andMatrixOutputs_T_53 = cat(cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53)
node cs_decoder_decoded_andMatrixOutputs_41_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_53)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18)
node cs_decoder_decoded_andMatrixOutputs_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_44)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21)
node cs_decoder_decoded_andMatrixOutputs_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51)
node _cs_decoder_decoded_andMatrixOutputs_T_54 = cat(cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54)
node cs_decoder_decoded_andMatrixOutputs_93_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_54)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54)
node cs_decoder_decoded_andMatrixOutputs_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_45)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55)
node cs_decoder_decoded_andMatrixOutputs_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52)
node _cs_decoder_decoded_andMatrixOutputs_T_55 = cat(cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55)
node cs_decoder_decoded_andMatrixOutputs_70_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_55)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53)
node cs_decoder_decoded_andMatrixOutputs_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_46)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56)
node cs_decoder_decoded_andMatrixOutputs_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53)
node _cs_decoder_decoded_andMatrixOutputs_T_56 = cat(cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56)
node cs_decoder_decoded_andMatrixOutputs_11_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_56)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47)
node cs_decoder_decoded_andMatrixOutputs_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_47)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57)
node cs_decoder_decoded_andMatrixOutputs_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54)
node _cs_decoder_decoded_andMatrixOutputs_T_57 = cat(cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57)
node cs_decoder_decoded_andMatrixOutputs_76_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_57)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57)
node cs_decoder_decoded_andMatrixOutputs_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_48)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58)
node cs_decoder_decoded_andMatrixOutputs_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55)
node _cs_decoder_decoded_andMatrixOutputs_T_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58)
node cs_decoder_decoded_andMatrixOutputs_167_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_58)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49)
node cs_decoder_decoded_andMatrixOutputs_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_49)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59)
node cs_decoder_decoded_andMatrixOutputs_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56)
node _cs_decoder_decoded_andMatrixOutputs_T_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59)
node cs_decoder_decoded_andMatrixOutputs_152_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_59)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59)
node cs_decoder_decoded_andMatrixOutputs_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_50)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60)
node cs_decoder_decoded_andMatrixOutputs_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57)
node _cs_decoder_decoded_andMatrixOutputs_T_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60)
node cs_decoder_decoded_andMatrixOutputs_96_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_60)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60)
node cs_decoder_decoded_andMatrixOutputs_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61)
node cs_decoder_decoded_andMatrixOutputs_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58)
node _cs_decoder_decoded_andMatrixOutputs_T_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61)
node cs_decoder_decoded_andMatrixOutputs_125_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_61)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61)
node cs_decoder_decoded_andMatrixOutputs_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_51)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62)
node cs_decoder_decoded_andMatrixOutputs_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59)
node _cs_decoder_decoded_andMatrixOutputs_T_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62)
node cs_decoder_decoded_andMatrixOutputs_40_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_62)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62)
node cs_decoder_decoded_andMatrixOutputs_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_52)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63)
node cs_decoder_decoded_andMatrixOutputs_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60)
node _cs_decoder_decoded_andMatrixOutputs_T_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63)
node cs_decoder_decoded_andMatrixOutputs_169_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_63)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61)
node cs_decoder_decoded_andMatrixOutputs_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_53)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64)
node cs_decoder_decoded_andMatrixOutputs_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61)
node _cs_decoder_decoded_andMatrixOutputs_T_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64)
node cs_decoder_decoded_andMatrixOutputs_69_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_64)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62)
node cs_decoder_decoded_andMatrixOutputs_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_54)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65)
node cs_decoder_decoded_andMatrixOutputs_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62)
node _cs_decoder_decoded_andMatrixOutputs_T_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65)
node cs_decoder_decoded_andMatrixOutputs_3_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_65)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65)
node cs_decoder_decoded_andMatrixOutputs_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_55)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66)
node cs_decoder_decoded_andMatrixOutputs_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63)
node _cs_decoder_decoded_andMatrixOutputs_T_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66)
node cs_decoder_decoded_andMatrixOutputs_16_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_66)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64)
node cs_decoder_decoded_andMatrixOutputs_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_56)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67)
node cs_decoder_decoded_andMatrixOutputs_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64)
node _cs_decoder_decoded_andMatrixOutputs_T_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67)
node cs_decoder_decoded_andMatrixOutputs_112_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_67)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67)
node cs_decoder_decoded_andMatrixOutputs_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_57)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68)
node cs_decoder_decoded_andMatrixOutputs_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65)
node _cs_decoder_decoded_andMatrixOutputs_T_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68)
node cs_decoder_decoded_andMatrixOutputs_160_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_68)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66)
node cs_decoder_decoded_andMatrixOutputs_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_58)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69)
node cs_decoder_decoded_andMatrixOutputs_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66)
node _cs_decoder_decoded_andMatrixOutputs_T_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69)
node cs_decoder_decoded_andMatrixOutputs_101_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_69)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41)
node cs_decoder_decoded_andMatrixOutputs_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_59)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70)
node cs_decoder_decoded_andMatrixOutputs_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67)
node _cs_decoder_decoded_andMatrixOutputs_T_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70)
node cs_decoder_decoded_andMatrixOutputs_15_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_70)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19)
node cs_decoder_decoded_andMatrixOutputs_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_60)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22)
node cs_decoder_decoded_andMatrixOutputs_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68)
node _cs_decoder_decoded_andMatrixOutputs_T_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71)
node cs_decoder_decoded_andMatrixOutputs_23_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_71)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20)
node cs_decoder_decoded_andMatrixOutputs_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_61)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23)
node cs_decoder_decoded_andMatrixOutputs_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69)
node _cs_decoder_decoded_andMatrixOutputs_T_72 = cat(cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72)
node cs_decoder_decoded_andMatrixOutputs_173_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_72)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72)
node cs_decoder_decoded_andMatrixOutputs_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_62)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73)
node cs_decoder_decoded_andMatrixOutputs_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70)
node _cs_decoder_decoded_andMatrixOutputs_T_73 = cat(cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73)
node cs_decoder_decoded_andMatrixOutputs_137_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_73)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71)
node cs_decoder_decoded_andMatrixOutputs_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_63)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74)
node cs_decoder_decoded_andMatrixOutputs_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71)
node _cs_decoder_decoded_andMatrixOutputs_T_74 = cat(cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74)
node cs_decoder_decoded_andMatrixOutputs_20_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_74)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64)
node cs_decoder_decoded_andMatrixOutputs_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_64)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75)
node cs_decoder_decoded_andMatrixOutputs_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72)
node _cs_decoder_decoded_andMatrixOutputs_T_75 = cat(cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75)
node cs_decoder_decoded_andMatrixOutputs_54_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_75)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73)
node cs_decoder_decoded_andMatrixOutputs_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_65)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76)
node cs_decoder_decoded_andMatrixOutputs_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73)
node _cs_decoder_decoded_andMatrixOutputs_T_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76)
node cs_decoder_decoded_andMatrixOutputs_97_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_76)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74)
node cs_decoder_decoded_andMatrixOutputs_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_66)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77)
node cs_decoder_decoded_andMatrixOutputs_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74)
node _cs_decoder_decoded_andMatrixOutputs_T_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77)
node cs_decoder_decoded_andMatrixOutputs_157_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_77)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67)
node cs_decoder_decoded_andMatrixOutputs_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_67)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78)
node cs_decoder_decoded_andMatrixOutputs_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75)
node _cs_decoder_decoded_andMatrixOutputs_T_78 = cat(cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78)
node cs_decoder_decoded_andMatrixOutputs_145_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_78)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21)
node cs_decoder_decoded_andMatrixOutputs_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_68)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24)
node cs_decoder_decoded_andMatrixOutputs_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76)
node _cs_decoder_decoded_andMatrixOutputs_T_79 = cat(cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79)
node cs_decoder_decoded_andMatrixOutputs_134_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_79)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22)
node cs_decoder_decoded_andMatrixOutputs_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_69)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25)
node cs_decoder_decoded_andMatrixOutputs_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77)
node _cs_decoder_decoded_andMatrixOutputs_T_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80)
node cs_decoder_decoded_andMatrixOutputs_128_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_80)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80)
node cs_decoder_decoded_andMatrixOutputs_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_70)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81)
node cs_decoder_decoded_andMatrixOutputs_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78)
node _cs_decoder_decoded_andMatrixOutputs_T_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81)
node cs_decoder_decoded_andMatrixOutputs_142_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_81)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79)
node cs_decoder_decoded_andMatrixOutputs_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_71)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82)
node cs_decoder_decoded_andMatrixOutputs_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79)
node _cs_decoder_decoded_andMatrixOutputs_T_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82)
node cs_decoder_decoded_andMatrixOutputs_117_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_82)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23)
node cs_decoder_decoded_andMatrixOutputs_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_72)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26)
node cs_decoder_decoded_andMatrixOutputs_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80)
node _cs_decoder_decoded_andMatrixOutputs_T_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83)
node cs_decoder_decoded_andMatrixOutputs_53_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_83)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24)
node cs_decoder_decoded_andMatrixOutputs_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_73)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27)
node cs_decoder_decoded_andMatrixOutputs_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81)
node _cs_decoder_decoded_andMatrixOutputs_T_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84)
node cs_decoder_decoded_andMatrixOutputs_166_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_84)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25)
node cs_decoder_decoded_andMatrixOutputs_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_74)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28)
node cs_decoder_decoded_andMatrixOutputs_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82)
node _cs_decoder_decoded_andMatrixOutputs_T_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85)
node cs_decoder_decoded_andMatrixOutputs_21_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_85)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26)
node cs_decoder_decoded_andMatrixOutputs_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_75)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29)
node cs_decoder_decoded_andMatrixOutputs_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83)
node _cs_decoder_decoded_andMatrixOutputs_T_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86)
node cs_decoder_decoded_andMatrixOutputs_65_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_86)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27)
node cs_decoder_decoded_andMatrixOutputs_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_76)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30)
node cs_decoder_decoded_andMatrixOutputs_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84)
node _cs_decoder_decoded_andMatrixOutputs_T_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87)
node cs_decoder_decoded_andMatrixOutputs_52_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_87)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28)
node cs_decoder_decoded_andMatrixOutputs_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_77)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31)
node cs_decoder_decoded_andMatrixOutputs_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85)
node _cs_decoder_decoded_andMatrixOutputs_T_88 = cat(cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88)
node cs_decoder_decoded_andMatrixOutputs_57_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_88)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29)
node cs_decoder_decoded_andMatrixOutputs_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_78)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32)
node cs_decoder_decoded_andMatrixOutputs_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86)
node _cs_decoder_decoded_andMatrixOutputs_T_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89)
node cs_decoder_decoded_andMatrixOutputs_74_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_89)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30)
node cs_decoder_decoded_andMatrixOutputs_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_79)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33)
node cs_decoder_decoded_andMatrixOutputs_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87)
node _cs_decoder_decoded_andMatrixOutputs_T_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90)
node cs_decoder_decoded_andMatrixOutputs_91_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_90)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88)
node cs_decoder_decoded_andMatrixOutputs_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_80)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91)
node cs_decoder_decoded_andMatrixOutputs_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88)
node _cs_decoder_decoded_andMatrixOutputs_T_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91)
node cs_decoder_decoded_andMatrixOutputs_104_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_91)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89)
node cs_decoder_decoded_andMatrixOutputs_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_81)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92)
node cs_decoder_decoded_andMatrixOutputs_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89)
node _cs_decoder_decoded_andMatrixOutputs_T_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92)
node cs_decoder_decoded_andMatrixOutputs_68_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_92)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90)
node cs_decoder_decoded_andMatrixOutputs_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_82)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93)
node cs_decoder_decoded_andMatrixOutputs_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90)
node _cs_decoder_decoded_andMatrixOutputs_T_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93)
node cs_decoder_decoded_andMatrixOutputs_94_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_93)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91)
node cs_decoder_decoded_andMatrixOutputs_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_83)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94)
node cs_decoder_decoded_andMatrixOutputs_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91)
node _cs_decoder_decoded_andMatrixOutputs_T_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94)
node cs_decoder_decoded_andMatrixOutputs_151_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_94)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92)
node cs_decoder_decoded_andMatrixOutputs_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_84)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95)
node cs_decoder_decoded_andMatrixOutputs_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92)
node _cs_decoder_decoded_andMatrixOutputs_T_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95)
node cs_decoder_decoded_andMatrixOutputs_2_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_95)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31)
node cs_decoder_decoded_andMatrixOutputs_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_85)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34)
node cs_decoder_decoded_andMatrixOutputs_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93)
node _cs_decoder_decoded_andMatrixOutputs_T_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96)
node cs_decoder_decoded_andMatrixOutputs_156_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_96)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32)
node cs_decoder_decoded_andMatrixOutputs_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_86)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35)
node cs_decoder_decoded_andMatrixOutputs_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94)
node _cs_decoder_decoded_andMatrixOutputs_T_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97)
node cs_decoder_decoded_andMatrixOutputs_154_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_97)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33)
node cs_decoder_decoded_andMatrixOutputs_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_87)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36)
node cs_decoder_decoded_andMatrixOutputs_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95)
node _cs_decoder_decoded_andMatrixOutputs_T_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98)
node cs_decoder_decoded_andMatrixOutputs_148_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_98)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34)
node cs_decoder_decoded_andMatrixOutputs_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_88)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37)
node cs_decoder_decoded_andMatrixOutputs_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96)
node _cs_decoder_decoded_andMatrixOutputs_T_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99)
node cs_decoder_decoded_andMatrixOutputs_89_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_99)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99)
node cs_decoder_decoded_andMatrixOutputs_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100)
node cs_decoder_decoded_andMatrixOutputs_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97)
node _cs_decoder_decoded_andMatrixOutputs_T_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100)
node cs_decoder_decoded_andMatrixOutputs_55_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_100)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98)
node cs_decoder_decoded_andMatrixOutputs_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_89)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101)
node cs_decoder_decoded_andMatrixOutputs_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98)
node _cs_decoder_decoded_andMatrixOutputs_T_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101)
node cs_decoder_decoded_andMatrixOutputs_116_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_101)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52)
node cs_decoder_decoded_andMatrixOutputs_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_90)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38)
node cs_decoder_decoded_andMatrixOutputs_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99)
node _cs_decoder_decoded_andMatrixOutputs_T_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102)
node cs_decoder_decoded_andMatrixOutputs_131_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_102)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35)
node cs_decoder_decoded_andMatrixOutputs_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_91)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39)
node cs_decoder_decoded_andMatrixOutputs_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100)
node _cs_decoder_decoded_andMatrixOutputs_T_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103)
node cs_decoder_decoded_andMatrixOutputs_172_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_103)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36)
node cs_decoder_decoded_andMatrixOutputs_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_92)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40)
node cs_decoder_decoded_andMatrixOutputs_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101)
node _cs_decoder_decoded_andMatrixOutputs_T_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104)
node cs_decoder_decoded_andMatrixOutputs_72_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_104)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37)
node cs_decoder_decoded_andMatrixOutputs_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_93)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41)
node cs_decoder_decoded_andMatrixOutputs_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102)
node _cs_decoder_decoded_andMatrixOutputs_T_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105)
node cs_decoder_decoded_andMatrixOutputs_81_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_105)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38)
node cs_decoder_decoded_andMatrixOutputs_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_94)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42)
node cs_decoder_decoded_andMatrixOutputs_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103)
node _cs_decoder_decoded_andMatrixOutputs_T_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106)
node cs_decoder_decoded_andMatrixOutputs_6_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_106)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39)
node cs_decoder_decoded_andMatrixOutputs_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_95)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43)
node cs_decoder_decoded_andMatrixOutputs_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104)
node _cs_decoder_decoded_andMatrixOutputs_T_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107)
node cs_decoder_decoded_andMatrixOutputs_143_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_107)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40)
node cs_decoder_decoded_andMatrixOutputs_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_96)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44)
node cs_decoder_decoded_andMatrixOutputs_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105)
node _cs_decoder_decoded_andMatrixOutputs_T_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108)
node cs_decoder_decoded_andMatrixOutputs_66_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_108)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41)
node cs_decoder_decoded_andMatrixOutputs_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_97)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45)
node cs_decoder_decoded_andMatrixOutputs_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106)
node _cs_decoder_decoded_andMatrixOutputs_T_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109)
node cs_decoder_decoded_andMatrixOutputs_63_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_109)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42)
node cs_decoder_decoded_andMatrixOutputs_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_98)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46)
node cs_decoder_decoded_andMatrixOutputs_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107)
node _cs_decoder_decoded_andMatrixOutputs_T_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110)
node cs_decoder_decoded_andMatrixOutputs_161_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_110)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43)
node cs_decoder_decoded_andMatrixOutputs_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_99)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47)
node cs_decoder_decoded_andMatrixOutputs_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108)
node _cs_decoder_decoded_andMatrixOutputs_T_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111)
node cs_decoder_decoded_andMatrixOutputs_132_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_111)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44)
node cs_decoder_decoded_andMatrixOutputs_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_100)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48)
node cs_decoder_decoded_andMatrixOutputs_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109)
node _cs_decoder_decoded_andMatrixOutputs_T_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112)
node cs_decoder_decoded_andMatrixOutputs_133_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_112)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(cs_decoder_decoded_plaInput, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45)
node cs_decoder_decoded_andMatrixOutputs_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_101)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49)
node cs_decoder_decoded_andMatrixOutputs_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110)
node _cs_decoder_decoded_andMatrixOutputs_T_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113)
node cs_decoder_decoded_andMatrixOutputs_147_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_113)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64)
node cs_decoder_decoded_andMatrixOutputs_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_102)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50)
node cs_decoder_decoded_andMatrixOutputs_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111)
node _cs_decoder_decoded_andMatrixOutputs_T_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114)
node cs_decoder_decoded_andMatrixOutputs_129_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_114)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65)
node cs_decoder_decoded_andMatrixOutputs_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_103)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51)
node cs_decoder_decoded_andMatrixOutputs_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112)
node _cs_decoder_decoded_andMatrixOutputs_T_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115)
node cs_decoder_decoded_andMatrixOutputs_100_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_115)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66)
node cs_decoder_decoded_andMatrixOutputs_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_104)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52)
node cs_decoder_decoded_andMatrixOutputs_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113)
node _cs_decoder_decoded_andMatrixOutputs_T_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116)
node cs_decoder_decoded_andMatrixOutputs_119_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_116)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46)
node cs_decoder_decoded_andMatrixOutputs_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_105)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53)
node cs_decoder_decoded_andMatrixOutputs_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114)
node _cs_decoder_decoded_andMatrixOutputs_T_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117)
node cs_decoder_decoded_andMatrixOutputs_150_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_117)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47)
node cs_decoder_decoded_andMatrixOutputs_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_106)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54)
node cs_decoder_decoded_andMatrixOutputs_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115)
node _cs_decoder_decoded_andMatrixOutputs_T_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118)
node cs_decoder_decoded_andMatrixOutputs_121_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_118)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69)
node cs_decoder_decoded_andMatrixOutputs_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_107)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55)
node cs_decoder_decoded_andMatrixOutputs_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116)
node _cs_decoder_decoded_andMatrixOutputs_T_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119)
node cs_decoder_decoded_andMatrixOutputs_158_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_119)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70)
node cs_decoder_decoded_andMatrixOutputs_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_108)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56)
node cs_decoder_decoded_andMatrixOutputs_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117)
node _cs_decoder_decoded_andMatrixOutputs_T_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120)
node cs_decoder_decoded_andMatrixOutputs_49_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_120)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48)
node cs_decoder_decoded_andMatrixOutputs_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_109)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57)
node cs_decoder_decoded_andMatrixOutputs_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118)
node _cs_decoder_decoded_andMatrixOutputs_T_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121)
node cs_decoder_decoded_andMatrixOutputs_50_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_121)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = bits(cs_decoder_decoded_plaInput, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49)
node cs_decoder_decoded_andMatrixOutputs_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_110)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58)
node cs_decoder_decoded_andMatrixOutputs_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119)
node _cs_decoder_decoded_andMatrixOutputs_T_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122)
node cs_decoder_decoded_andMatrixOutputs_45_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_122)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = bits(cs_decoder_decoded_plaInput, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50)
node cs_decoder_decoded_andMatrixOutputs_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_111)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59)
node cs_decoder_decoded_andMatrixOutputs_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120)
node _cs_decoder_decoded_andMatrixOutputs_T_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123)
node cs_decoder_decoded_andMatrixOutputs_135_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_123)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(cs_decoder_decoded_plaInput, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = bits(cs_decoder_decoded_plaInput, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51)
node cs_decoder_decoded_andMatrixOutputs_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_112)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60)
node cs_decoder_decoded_andMatrixOutputs_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121)
node _cs_decoder_decoded_andMatrixOutputs_T_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124)
node cs_decoder_decoded_andMatrixOutputs_140_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_124)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = bits(cs_decoder_decoded_plaInput, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = bits(cs_decoder_decoded_plaInput, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52)
node cs_decoder_decoded_andMatrixOutputs_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_113)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61)
node cs_decoder_decoded_andMatrixOutputs_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122)
node _cs_decoder_decoded_andMatrixOutputs_T_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125)
node cs_decoder_decoded_andMatrixOutputs_95_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_125)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76)
node cs_decoder_decoded_andMatrixOutputs_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_114)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62)
node cs_decoder_decoded_andMatrixOutputs_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123)
node _cs_decoder_decoded_andMatrixOutputs_T_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126)
node cs_decoder_decoded_andMatrixOutputs_115_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_126)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53)
node cs_decoder_decoded_andMatrixOutputs_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_115)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63)
node cs_decoder_decoded_andMatrixOutputs_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124)
node _cs_decoder_decoded_andMatrixOutputs_T_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127)
node cs_decoder_decoded_andMatrixOutputs_60_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_127)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54)
node cs_decoder_decoded_andMatrixOutputs_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_116)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64)
node cs_decoder_decoded_andMatrixOutputs_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125)
node _cs_decoder_decoded_andMatrixOutputs_T_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128)
node cs_decoder_decoded_andMatrixOutputs_7_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_128)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55)
node cs_decoder_decoded_andMatrixOutputs_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_117)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65)
node cs_decoder_decoded_andMatrixOutputs_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126)
node _cs_decoder_decoded_andMatrixOutputs_T_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129)
node cs_decoder_decoded_andMatrixOutputs_14_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_129)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56)
node cs_decoder_decoded_andMatrixOutputs_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_118)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66)
node cs_decoder_decoded_andMatrixOutputs_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127)
node _cs_decoder_decoded_andMatrixOutputs_T_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130)
node cs_decoder_decoded_andMatrixOutputs_92_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_130)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81)
node cs_decoder_decoded_andMatrixOutputs_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_119)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67)
node cs_decoder_decoded_andMatrixOutputs_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128)
node _cs_decoder_decoded_andMatrixOutputs_T_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131)
node cs_decoder_decoded_andMatrixOutputs_78_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_131)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57)
node cs_decoder_decoded_andMatrixOutputs_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_120)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68)
node cs_decoder_decoded_andMatrixOutputs_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129)
node _cs_decoder_decoded_andMatrixOutputs_T_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132)
node cs_decoder_decoded_andMatrixOutputs_47_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_132)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58)
node cs_decoder_decoded_andMatrixOutputs_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_121)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69)
node cs_decoder_decoded_andMatrixOutputs_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130)
node _cs_decoder_decoded_andMatrixOutputs_T_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133)
node cs_decoder_decoded_andMatrixOutputs_4_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_133)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59)
node cs_decoder_decoded_andMatrixOutputs_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_122)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70)
node cs_decoder_decoded_andMatrixOutputs_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131)
node _cs_decoder_decoded_andMatrixOutputs_T_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134)
node cs_decoder_decoded_andMatrixOutputs_123_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_134)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60)
node cs_decoder_decoded_andMatrixOutputs_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_123)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71)
node cs_decoder_decoded_andMatrixOutputs_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132)
node _cs_decoder_decoded_andMatrixOutputs_T_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135)
node cs_decoder_decoded_andMatrixOutputs_107_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_135)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61)
node cs_decoder_decoded_andMatrixOutputs_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_124)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72)
node cs_decoder_decoded_andMatrixOutputs_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133)
node _cs_decoder_decoded_andMatrixOutputs_T_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136)
node cs_decoder_decoded_andMatrixOutputs_33_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_136)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62)
node cs_decoder_decoded_andMatrixOutputs_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_125)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73)
node cs_decoder_decoded_andMatrixOutputs_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134)
node _cs_decoder_decoded_andMatrixOutputs_T_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137)
node cs_decoder_decoded_andMatrixOutputs_88_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_137)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63)
node cs_decoder_decoded_andMatrixOutputs_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_126)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74)
node cs_decoder_decoded_andMatrixOutputs_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135)
node _cs_decoder_decoded_andMatrixOutputs_T_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138)
node cs_decoder_decoded_andMatrixOutputs_87_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_138)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64)
node cs_decoder_decoded_andMatrixOutputs_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_127)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75)
node cs_decoder_decoded_andMatrixOutputs_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136)
node _cs_decoder_decoded_andMatrixOutputs_T_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139)
node cs_decoder_decoded_andMatrixOutputs_37_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_139)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65)
node cs_decoder_decoded_andMatrixOutputs_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_128)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76)
node cs_decoder_decoded_andMatrixOutputs_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137)
node _cs_decoder_decoded_andMatrixOutputs_T_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140)
node cs_decoder_decoded_andMatrixOutputs_22_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_140)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109)
node cs_decoder_decoded_andMatrixOutputs_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_129)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141)
node cs_decoder_decoded_andMatrixOutputs_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138)
node _cs_decoder_decoded_andMatrixOutputs_T_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141)
node cs_decoder_decoded_andMatrixOutputs_58_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_141)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66)
node cs_decoder_decoded_andMatrixOutputs_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_130)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77)
node cs_decoder_decoded_andMatrixOutputs_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139)
node _cs_decoder_decoded_andMatrixOutputs_T_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142)
node cs_decoder_decoded_andMatrixOutputs_62_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_142)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67)
node cs_decoder_decoded_andMatrixOutputs_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_131)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78)
node cs_decoder_decoded_andMatrixOutputs_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140)
node _cs_decoder_decoded_andMatrixOutputs_T_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143)
node cs_decoder_decoded_andMatrixOutputs_9_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_143)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68)
node cs_decoder_decoded_andMatrixOutputs_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_132)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79)
node cs_decoder_decoded_andMatrixOutputs_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141)
node _cs_decoder_decoded_andMatrixOutputs_T_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144)
node cs_decoder_decoded_andMatrixOutputs_64_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_144)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69)
node cs_decoder_decoded_andMatrixOutputs_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_133)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80)
node cs_decoder_decoded_andMatrixOutputs_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142)
node _cs_decoder_decoded_andMatrixOutputs_T_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145)
node cs_decoder_decoded_andMatrixOutputs_146_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_145)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70)
node cs_decoder_decoded_andMatrixOutputs_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_134)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81)
node cs_decoder_decoded_andMatrixOutputs_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143)
node _cs_decoder_decoded_andMatrixOutputs_T_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146)
node cs_decoder_decoded_andMatrixOutputs_113_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_146)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71)
node cs_decoder_decoded_andMatrixOutputs_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_135)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82)
node cs_decoder_decoded_andMatrixOutputs_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144)
node _cs_decoder_decoded_andMatrixOutputs_T_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147)
node cs_decoder_decoded_andMatrixOutputs_80_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_147)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116)
node cs_decoder_decoded_andMatrixOutputs_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_136)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148)
node cs_decoder_decoded_andMatrixOutputs_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145)
node _cs_decoder_decoded_andMatrixOutputs_T_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148)
node cs_decoder_decoded_andMatrixOutputs_44_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_148)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(cs_decoder_decoded_plaInput, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72)
node cs_decoder_decoded_andMatrixOutputs_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_137)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83)
node cs_decoder_decoded_andMatrixOutputs_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146)
node _cs_decoder_decoded_andMatrixOutputs_T_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149)
node cs_decoder_decoded_andMatrixOutputs_159_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_149)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(cs_decoder_decoded_plaInput, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73)
node cs_decoder_decoded_andMatrixOutputs_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_138)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84)
node cs_decoder_decoded_andMatrixOutputs_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147)
node _cs_decoder_decoded_andMatrixOutputs_T_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150)
node cs_decoder_decoded_andMatrixOutputs_0_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_150)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74)
node cs_decoder_decoded_andMatrixOutputs_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_139)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85)
node cs_decoder_decoded_andMatrixOutputs_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148)
node _cs_decoder_decoded_andMatrixOutputs_T_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151)
node cs_decoder_decoded_andMatrixOutputs_99_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_151)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75)
node cs_decoder_decoded_andMatrixOutputs_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_140)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86)
node cs_decoder_decoded_andMatrixOutputs_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149)
node _cs_decoder_decoded_andMatrixOutputs_T_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152)
node cs_decoder_decoded_andMatrixOutputs_13_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_152)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76)
node cs_decoder_decoded_andMatrixOutputs_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_141)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87)
node cs_decoder_decoded_andMatrixOutputs_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150)
node _cs_decoder_decoded_andMatrixOutputs_T_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153)
node cs_decoder_decoded_andMatrixOutputs_120_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_153)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77)
node cs_decoder_decoded_andMatrixOutputs_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_142)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88)
node cs_decoder_decoded_andMatrixOutputs_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151)
node _cs_decoder_decoded_andMatrixOutputs_T_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154)
node cs_decoder_decoded_andMatrixOutputs_171_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_154)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78)
node cs_decoder_decoded_andMatrixOutputs_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_143)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89)
node cs_decoder_decoded_andMatrixOutputs_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152)
node _cs_decoder_decoded_andMatrixOutputs_T_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155)
node cs_decoder_decoded_andMatrixOutputs_109_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_155)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(cs_decoder_decoded_plaInput, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = bits(cs_decoder_decoded_plaInput, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79)
node cs_decoder_decoded_andMatrixOutputs_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_144)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90)
node cs_decoder_decoded_andMatrixOutputs_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153)
node _cs_decoder_decoded_andMatrixOutputs_T_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156)
node cs_decoder_decoded_andMatrixOutputs_59_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_156)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(cs_decoder_decoded_invInputs, 7, 7)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(cs_decoder_decoded_invInputs, 8, 8)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(cs_decoder_decoded_invInputs, 9, 9)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(cs_decoder_decoded_invInputs, 10, 10)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(cs_decoder_decoded_invInputs, 11, 11)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = bits(cs_decoder_decoded_invInputs, 15, 15)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = bits(cs_decoder_decoded_invInputs, 16, 16)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(cs_decoder_decoded_invInputs, 17, 17)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = bits(cs_decoder_decoded_invInputs, 18, 18)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = bits(cs_decoder_decoded_invInputs, 19, 19)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = bits(cs_decoder_decoded_plaInput, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = bits(cs_decoder_decoded_plaInput, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = bits(cs_decoder_decoded_plaInput, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = bits(cs_decoder_decoded_invInputs, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80)
node cs_decoder_decoded_andMatrixOutputs_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_145)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91)
node cs_decoder_decoded_andMatrixOutputs_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154)
node _cs_decoder_decoded_andMatrixOutputs_T_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157)
node cs_decoder_decoded_andMatrixOutputs_106_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_157)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(cs_decoder_decoded_plaInput, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(cs_decoder_decoded_plaInput, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(cs_decoder_decoded_invInputs, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(cs_decoder_decoded_plaInput, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(cs_decoder_decoded_invInputs, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(cs_decoder_decoded_plaInput, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126)
node cs_decoder_decoded_andMatrixOutputs_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_146)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158)
node cs_decoder_decoded_andMatrixOutputs_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155)
node _cs_decoder_decoded_andMatrixOutputs_T_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158)
node cs_decoder_decoded_andMatrixOutputs_155_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_158)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81)
node cs_decoder_decoded_andMatrixOutputs_lo_159 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_147)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92)
node cs_decoder_decoded_andMatrixOutputs_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156)
node _cs_decoder_decoded_andMatrixOutputs_T_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159)
node cs_decoder_decoded_andMatrixOutputs_149_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_159)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = bits(cs_decoder_decoded_invInputs, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82)
node cs_decoder_decoded_andMatrixOutputs_lo_160 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_148)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93)
node cs_decoder_decoded_andMatrixOutputs_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157)
node _cs_decoder_decoded_andMatrixOutputs_T_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160)
node cs_decoder_decoded_andMatrixOutputs_136_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_160)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83)
node cs_decoder_decoded_andMatrixOutputs_lo_161 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_149)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94)
node cs_decoder_decoded_andMatrixOutputs_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158)
node _cs_decoder_decoded_andMatrixOutputs_T_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161)
node cs_decoder_decoded_andMatrixOutputs_31_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_161)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84)
node cs_decoder_decoded_andMatrixOutputs_lo_162 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_150)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95)
node cs_decoder_decoded_andMatrixOutputs_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159)
node _cs_decoder_decoded_andMatrixOutputs_T_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162)
node cs_decoder_decoded_andMatrixOutputs_90_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_162)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85)
node cs_decoder_decoded_andMatrixOutputs_lo_163 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_151)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96)
node cs_decoder_decoded_andMatrixOutputs_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160)
node _cs_decoder_decoded_andMatrixOutputs_T_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163)
node cs_decoder_decoded_andMatrixOutputs_39_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_163)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86)
node cs_decoder_decoded_andMatrixOutputs_lo_164 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_152)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97)
node cs_decoder_decoded_andMatrixOutputs_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161)
node _cs_decoder_decoded_andMatrixOutputs_T_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164)
node cs_decoder_decoded_andMatrixOutputs_83_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_164)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87)
node cs_decoder_decoded_andMatrixOutputs_lo_165 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_153)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98)
node cs_decoder_decoded_andMatrixOutputs_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162)
node _cs_decoder_decoded_andMatrixOutputs_T_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165)
node cs_decoder_decoded_andMatrixOutputs_103_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_165)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = bits(cs_decoder_decoded_invInputs, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88)
node cs_decoder_decoded_andMatrixOutputs_lo_166 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_154)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99)
node cs_decoder_decoded_andMatrixOutputs_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163)
node _cs_decoder_decoded_andMatrixOutputs_T_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166)
node cs_decoder_decoded_andMatrixOutputs_138_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_166)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89)
node cs_decoder_decoded_andMatrixOutputs_lo_167 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_155)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100)
node cs_decoder_decoded_andMatrixOutputs_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164)
node _cs_decoder_decoded_andMatrixOutputs_T_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167)
node cs_decoder_decoded_andMatrixOutputs_86_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_167)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90)
node cs_decoder_decoded_andMatrixOutputs_lo_168 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_156)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101)
node cs_decoder_decoded_andMatrixOutputs_hi_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165)
node _cs_decoder_decoded_andMatrixOutputs_T_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168)
node cs_decoder_decoded_andMatrixOutputs_111_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_168)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_168 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91)
node cs_decoder_decoded_andMatrixOutputs_lo_169 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_lo_157)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_166 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_169 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102)
node cs_decoder_decoded_andMatrixOutputs_hi_169 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_169, cs_decoder_decoded_andMatrixOutputs_hi_lo_166)
node _cs_decoder_decoded_andMatrixOutputs_T_169 = cat(cs_decoder_decoded_andMatrixOutputs_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_169)
node cs_decoder_decoded_andMatrixOutputs_32_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_169)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = bits(cs_decoder_decoded_invInputs, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_169 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92)
node cs_decoder_decoded_andMatrixOutputs_lo_170 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_lo_158)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_167 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_170 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103)
node cs_decoder_decoded_andMatrixOutputs_hi_170 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_170, cs_decoder_decoded_andMatrixOutputs_hi_lo_167)
node _cs_decoder_decoded_andMatrixOutputs_T_170 = cat(cs_decoder_decoded_andMatrixOutputs_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_170)
node cs_decoder_decoded_andMatrixOutputs_127_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_170)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(cs_decoder_decoded_plaInput, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_159 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_170 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93)
node cs_decoder_decoded_andMatrixOutputs_lo_171 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_lo_159)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_168 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_171 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104)
node cs_decoder_decoded_andMatrixOutputs_hi_171 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_171, cs_decoder_decoded_andMatrixOutputs_hi_lo_168)
node _cs_decoder_decoded_andMatrixOutputs_T_171 = cat(cs_decoder_decoded_andMatrixOutputs_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_171)
node cs_decoder_decoded_andMatrixOutputs_164_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_171)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_160 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_171 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94)
node cs_decoder_decoded_andMatrixOutputs_lo_172 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_lo_160)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_169 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_172 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105)
node cs_decoder_decoded_andMatrixOutputs_hi_172 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_172, cs_decoder_decoded_andMatrixOutputs_hi_lo_169)
node _cs_decoder_decoded_andMatrixOutputs_T_172 = cat(cs_decoder_decoded_andMatrixOutputs_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_172)
node cs_decoder_decoded_andMatrixOutputs_61_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_172)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = bits(cs_decoder_decoded_plaInput, 25, 25)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = bits(cs_decoder_decoded_invInputs, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_161 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_172 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95)
node cs_decoder_decoded_andMatrixOutputs_lo_173 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_lo_161)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_170 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_173 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106)
node cs_decoder_decoded_andMatrixOutputs_hi_173 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_173, cs_decoder_decoded_andMatrixOutputs_hi_lo_170)
node _cs_decoder_decoded_andMatrixOutputs_T_173 = cat(cs_decoder_decoded_andMatrixOutputs_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_173)
node cs_decoder_decoded_andMatrixOutputs_36_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_173)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(cs_decoder_decoded_plaInput, 0, 0)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(cs_decoder_decoded_plaInput, 1, 1)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(cs_decoder_decoded_invInputs, 2, 2)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(cs_decoder_decoded_invInputs, 3, 3)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(cs_decoder_decoded_plaInput, 4, 4)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(cs_decoder_decoded_invInputs, 5, 5)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(cs_decoder_decoded_plaInput, 6, 6)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(cs_decoder_decoded_invInputs, 12, 12)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(cs_decoder_decoded_invInputs, 13, 13)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(cs_decoder_decoded_invInputs, 14, 14)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(cs_decoder_decoded_invInputs, 20, 20)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(cs_decoder_decoded_invInputs, 21, 21)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = bits(cs_decoder_decoded_invInputs, 22, 22)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = bits(cs_decoder_decoded_invInputs, 23, 23)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = bits(cs_decoder_decoded_invInputs, 24, 24)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = bits(cs_decoder_decoded_invInputs, 26, 26)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = bits(cs_decoder_decoded_invInputs, 27, 27)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = bits(cs_decoder_decoded_plaInput, 28, 28)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = bits(cs_decoder_decoded_plaInput, 29, 29)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = bits(cs_decoder_decoded_plaInput, 30, 30)
node cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = bits(cs_decoder_decoded_plaInput, 31, 31)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23)
node cs_decoder_decoded_andMatrixOutputs_lo_lo_162 = cat(cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96)
node cs_decoder_decoded_andMatrixOutputs_lo_hi_173 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96)
node cs_decoder_decoded_andMatrixOutputs_lo_174 = cat(cs_decoder_decoded_andMatrixOutputs_lo_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_lo_162)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142)
node cs_decoder_decoded_andMatrixOutputs_hi_lo_171 = cat(cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = cat(cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174)
node cs_decoder_decoded_andMatrixOutputs_hi_hi_174 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107)
node cs_decoder_decoded_andMatrixOutputs_hi_174 = cat(cs_decoder_decoded_andMatrixOutputs_hi_hi_174, cs_decoder_decoded_andMatrixOutputs_hi_lo_171)
node _cs_decoder_decoded_andMatrixOutputs_T_174 = cat(cs_decoder_decoded_andMatrixOutputs_hi_174, cs_decoder_decoded_andMatrixOutputs_lo_174)
node cs_decoder_decoded_andMatrixOutputs_51_2 = andr(_cs_decoder_decoded_andMatrixOutputs_T_174)
node _cs_decoder_decoded_orMatrixOutputs_T = orr(cs_decoder_decoded_andMatrixOutputs_167_2)
node _cs_decoder_decoded_orMatrixOutputs_T_1 = orr(cs_decoder_decoded_andMatrixOutputs_137_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2)
node cs_decoder_decoded_orMatrixOutputs_hi = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_137_2)
node _cs_decoder_decoded_orMatrixOutputs_T_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo)
node _cs_decoder_decoded_orMatrixOutputs_T_3 = orr(_cs_decoder_decoded_orMatrixOutputs_T_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_43_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_167_2)
node cs_decoder_decoded_orMatrixOutputs_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo)
node _cs_decoder_decoded_orMatrixOutputs_T_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_1)
node _cs_decoder_decoded_orMatrixOutputs_T_5 = orr(_cs_decoder_decoded_orMatrixOutputs_T_4)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_106_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_135_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_95_2)
node cs_decoder_decoded_orMatrixOutputs_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_67_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_167_2)
node cs_decoder_decoded_orMatrixOutputs_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_1)
node _cs_decoder_decoded_orMatrixOutputs_T_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_2)
node _cs_decoder_decoded_orMatrixOutputs_T_7 = orr(_cs_decoder_decoded_orMatrixOutputs_T_6)
node _cs_decoder_decoded_orMatrixOutputs_T_8 = orr(cs_decoder_decoded_andMatrixOutputs_67_2)
node _cs_decoder_decoded_orMatrixOutputs_T_9 = cat(cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_142_2)
node _cs_decoder_decoded_orMatrixOutputs_T_10 = orr(_cs_decoder_decoded_orMatrixOutputs_T_9)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_53_2)
node cs_decoder_decoded_orMatrixOutputs_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_144_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_46_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_170_2)
node cs_decoder_decoded_orMatrixOutputs_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_2)
node _cs_decoder_decoded_orMatrixOutputs_T_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_3)
node _cs_decoder_decoded_orMatrixOutputs_T_12 = orr(_cs_decoder_decoded_orMatrixOutputs_T_11)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_65_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_46_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_174_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3)
node _cs_decoder_decoded_orMatrixOutputs_T_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_4)
node _cs_decoder_decoded_orMatrixOutputs_T_14 = orr(_cs_decoder_decoded_orMatrixOutputs_T_13)
node cs_decoder_decoded_orMatrixOutputs_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node _cs_decoder_decoded_orMatrixOutputs_T_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_124_2)
node _cs_decoder_decoded_orMatrixOutputs_T_16 = orr(_cs_decoder_decoded_orMatrixOutputs_T_15)
node cs_decoder_decoded_orMatrixOutputs_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_58_2)
node cs_decoder_decoded_orMatrixOutputs_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_160_2)
node _cs_decoder_decoded_orMatrixOutputs_T_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5)
node _cs_decoder_decoded_orMatrixOutputs_T_18 = orr(_cs_decoder_decoded_orMatrixOutputs_T_17)
node cs_decoder_decoded_orMatrixOutputs_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_47_2)
node _cs_decoder_decoded_orMatrixOutputs_T_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_44_2)
node _cs_decoder_decoded_orMatrixOutputs_T_20 = orr(_cs_decoder_decoded_orMatrixOutputs_T_19)
node cs_decoder_decoded_orMatrixOutputs_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_155_2)
node cs_decoder_decoded_orMatrixOutputs_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_121_2)
node _cs_decoder_decoded_orMatrixOutputs_T_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_6)
node _cs_decoder_decoded_orMatrixOutputs_T_22 = orr(_cs_decoder_decoded_orMatrixOutputs_T_21)
node _cs_decoder_decoded_orMatrixOutputs_T_23 = orr(cs_decoder_decoded_andMatrixOutputs_15_2)
node _cs_decoder_decoded_orMatrixOutputs_T_24 = orr(cs_decoder_decoded_andMatrixOutputs_60_2)
node _cs_decoder_decoded_orMatrixOutputs_T_25 = orr(cs_decoder_decoded_andMatrixOutputs_18_2)
node _cs_decoder_decoded_orMatrixOutputs_T_26 = orr(cs_decoder_decoded_andMatrixOutputs_85_2)
node _cs_decoder_decoded_orMatrixOutputs_T_27 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2)
node _cs_decoder_decoded_orMatrixOutputs_T_28 = orr(_cs_decoder_decoded_orMatrixOutputs_T_27)
node cs_decoder_decoded_orMatrixOutputs_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_110_2)
node cs_decoder_decoded_orMatrixOutputs_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_160_2)
node _cs_decoder_decoded_orMatrixOutputs_T_29 = cat(cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_7)
node _cs_decoder_decoded_orMatrixOutputs_T_30 = orr(_cs_decoder_decoded_orMatrixOutputs_T_29)
node cs_decoder_decoded_orMatrixOutputs_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_121_2)
node cs_decoder_decoded_orMatrixOutputs_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node _cs_decoder_decoded_orMatrixOutputs_T_31 = cat(cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_8)
node _cs_decoder_decoded_orMatrixOutputs_T_32 = orr(_cs_decoder_decoded_orMatrixOutputs_T_31)
node cs_decoder_decoded_orMatrixOutputs_hi_11 = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_110_2)
node _cs_decoder_decoded_orMatrixOutputs_T_33 = cat(cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2)
node _cs_decoder_decoded_orMatrixOutputs_T_34 = orr(_cs_decoder_decoded_orMatrixOutputs_T_33)
node cs_decoder_decoded_orMatrixOutputs_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_79_2)
node _cs_decoder_decoded_orMatrixOutputs_T_35 = cat(cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_142_2)
node _cs_decoder_decoded_orMatrixOutputs_T_36 = orr(_cs_decoder_decoded_orMatrixOutputs_T_35)
node _cs_decoder_decoded_orMatrixOutputs_T_37 = orr(cs_decoder_decoded_andMatrixOutputs_139_2)
node _cs_decoder_decoded_orMatrixOutputs_T_38 = orr(cs_decoder_decoded_andMatrixOutputs_162_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_101_2)
node _cs_decoder_decoded_orMatrixOutputs_T_39 = cat(cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_9)
node _cs_decoder_decoded_orMatrixOutputs_T_40 = orr(_cs_decoder_decoded_orMatrixOutputs_T_39)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_31_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_16_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_46_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_26_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_174_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_4)
node _cs_decoder_decoded_orMatrixOutputs_T_41 = cat(cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_10)
node _cs_decoder_decoded_orMatrixOutputs_T_42 = orr(_cs_decoder_decoded_orMatrixOutputs_T_41)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_83_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_4_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_68_2)
node cs_decoder_decoded_orMatrixOutputs_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_5)
node _cs_decoder_decoded_orMatrixOutputs_T_43 = cat(cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_11)
node _cs_decoder_decoded_orMatrixOutputs_T_44 = orr(_cs_decoder_decoded_orMatrixOutputs_T_43)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_45_2)
node cs_decoder_decoded_orMatrixOutputs_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_6)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = cat(cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_68_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_34_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_6)
node _cs_decoder_decoded_orMatrixOutputs_T_45 = cat(cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_12)
node _cs_decoder_decoded_orMatrixOutputs_T_46 = orr(_cs_decoder_decoded_orMatrixOutputs_T_45)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_13_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_13 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_7)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_37_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_69_2)
node cs_decoder_decoded_orMatrixOutputs_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_7)
node _cs_decoder_decoded_orMatrixOutputs_T_47 = cat(cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_13)
node _cs_decoder_decoded_orMatrixOutputs_T_48 = orr(_cs_decoder_decoded_orMatrixOutputs_T_47)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_4_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_8)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_16_2, cs_decoder_decoded_andMatrixOutputs_15_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_5_2, cs_decoder_decoded_andMatrixOutputs_75_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_8)
node _cs_decoder_decoded_orMatrixOutputs_T_49 = cat(cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_14)
node _cs_decoder_decoded_orMatrixOutputs_T_50 = orr(_cs_decoder_decoded_orMatrixOutputs_T_49)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_65_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_142_2)
node cs_decoder_decoded_orMatrixOutputs_lo_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_9)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_144_2, cs_decoder_decoded_andMatrixOutputs_79_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_46_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_12_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_9)
node _cs_decoder_decoded_orMatrixOutputs_T_51 = cat(cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_15)
node _cs_decoder_decoded_orMatrixOutputs_T_52 = orr(_cs_decoder_decoded_orMatrixOutputs_T_51)
node cs_decoder_decoded_orMatrixOutputs_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_174_2)
node _cs_decoder_decoded_orMatrixOutputs_T_53 = cat(cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_139_2)
node _cs_decoder_decoded_orMatrixOutputs_T_54 = orr(_cs_decoder_decoded_orMatrixOutputs_T_53)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_14_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_lo_16 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_10)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_125_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_29_2)
node cs_decoder_decoded_orMatrixOutputs_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_10)
node _cs_decoder_decoded_orMatrixOutputs_T_55 = cat(cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_16)
node _cs_decoder_decoded_orMatrixOutputs_T_56 = orr(_cs_decoder_decoded_orMatrixOutputs_T_55)
node _cs_decoder_decoded_orMatrixOutputs_T_57 = cat(cs_decoder_decoded_andMatrixOutputs_148_2, cs_decoder_decoded_andMatrixOutputs_89_2)
node _cs_decoder_decoded_orMatrixOutputs_T_58 = orr(_cs_decoder_decoded_orMatrixOutputs_T_57)
node _cs_decoder_decoded_orMatrixOutputs_T_59 = orr(cs_decoder_decoded_andMatrixOutputs_6_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2)
node cs_decoder_decoded_orMatrixOutputs_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_137_2)
node _cs_decoder_decoded_orMatrixOutputs_T_60 = cat(cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_17)
node _cs_decoder_decoded_orMatrixOutputs_T_61 = orr(_cs_decoder_decoded_orMatrixOutputs_T_60)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = cat(cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_0_2)
node cs_decoder_decoded_orMatrixOutputs_lo_18 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_13_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = cat(cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_153_2)
node cs_decoder_decoded_orMatrixOutputs_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_11)
node _cs_decoder_decoded_orMatrixOutputs_T_62 = cat(cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_18)
node _cs_decoder_decoded_orMatrixOutputs_T_63 = orr(_cs_decoder_decoded_orMatrixOutputs_T_62)
node _cs_decoder_decoded_orMatrixOutputs_T_64 = cat(cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2)
node _cs_decoder_decoded_orMatrixOutputs_T_65 = orr(_cs_decoder_decoded_orMatrixOutputs_T_64)
node _cs_decoder_decoded_orMatrixOutputs_T_66 = cat(cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2)
node _cs_decoder_decoded_orMatrixOutputs_T_67 = orr(_cs_decoder_decoded_orMatrixOutputs_T_66)
node cs_decoder_decoded_orMatrixOutputs_lo_19 = cat(cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_101_2, cs_decoder_decoded_andMatrixOutputs_149_2)
node cs_decoder_decoded_orMatrixOutputs_hi_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_136_2)
node _cs_decoder_decoded_orMatrixOutputs_T_68 = cat(cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_19)
node _cs_decoder_decoded_orMatrixOutputs_T_69 = orr(_cs_decoder_decoded_orMatrixOutputs_T_68)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_4_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_11)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_15_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_29_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_25 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_12)
node _cs_decoder_decoded_orMatrixOutputs_T_70 = cat(cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_20)
node _cs_decoder_decoded_orMatrixOutputs_T_71 = orr(_cs_decoder_decoded_orMatrixOutputs_T_70)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = cat(cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_92_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2)
node cs_decoder_decoded_orMatrixOutputs_lo_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_lo_12)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_125_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_26 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_lo_13)
node _cs_decoder_decoded_orMatrixOutputs_T_72 = cat(cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_21)
node _cs_decoder_decoded_orMatrixOutputs_T_73 = orr(_cs_decoder_decoded_orMatrixOutputs_T_72)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = cat(cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_13)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_101_2)
node cs_decoder_decoded_orMatrixOutputs_hi_27 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14)
node _cs_decoder_decoded_orMatrixOutputs_T_74 = cat(cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_22)
node _cs_decoder_decoded_orMatrixOutputs_T_75 = orr(_cs_decoder_decoded_orMatrixOutputs_T_74)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_61_2, cs_decoder_decoded_andMatrixOutputs_36_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_103_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_9_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_64_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_158_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_150_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_151_2, cs_decoder_decoded_andMatrixOutputs_172_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_66_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_23 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_14)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_68_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_74_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_173_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_96_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_40_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_93_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_141_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_17_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_163_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_28 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15)
node _cs_decoder_decoded_orMatrixOutputs_T_76 = cat(cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_23)
node _cs_decoder_decoded_orMatrixOutputs_T_77 = orr(_cs_decoder_decoded_orMatrixOutputs_T_76)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_7_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_119_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_72_2, cs_decoder_decoded_andMatrixOutputs_133_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_2_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_57_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_24 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_15)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_20_2, cs_decoder_decoded_andMatrixOutputs_97_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_15_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_41_2, cs_decoder_decoded_andMatrixOutputs_152_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_10_2, cs_decoder_decoded_andMatrixOutputs_82_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_43_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_73_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_24_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_48_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_hi_29 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16)
node _cs_decoder_decoded_orMatrixOutputs_T_78 = cat(cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_24)
node _cs_decoder_decoded_orMatrixOutputs_T_79 = orr(_cs_decoder_decoded_orMatrixOutputs_T_78)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_86_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_146_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_115_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_81_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_161_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_148_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_52_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_lo_25 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_16)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_128_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_117_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_42_2, cs_decoder_decoded_andMatrixOutputs_152_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_25_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_30_2, cs_decoder_decoded_andMatrixOutputs_28_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_34_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7)
node cs_decoder_decoded_orMatrixOutputs_hi_30 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17)
node _cs_decoder_decoded_orMatrixOutputs_T_80 = cat(cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_25)
node _cs_decoder_decoded_orMatrixOutputs_T_81 = orr(_cs_decoder_decoded_orMatrixOutputs_T_80)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_109_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_159_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_37_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_129_2, cs_decoder_decoded_andMatrixOutputs_49_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_66_2, cs_decoder_decoded_andMatrixOutputs_63_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_143_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7)
node cs_decoder_decoded_orMatrixOutputs_lo_26 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_17)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_145_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_112_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_42_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = cat(cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_43_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = cat(cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_126_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_48_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_30_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8)
node cs_decoder_decoded_orMatrixOutputs_hi_31 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18)
node _cs_decoder_decoded_orMatrixOutputs_T_82 = cat(cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_26)
node _cs_decoder_decoded_orMatrixOutputs_T_83 = orr(_cs_decoder_decoded_orMatrixOutputs_T_82)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = cat(cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_164_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_113_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_149_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_154_2, cs_decoder_decoded_andMatrixOutputs_66_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_57_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_156_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8)
node cs_decoder_decoded_orMatrixOutputs_lo_27 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_18)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = cat(cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_166_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_54_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_134_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_79_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_11_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_153_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9)
node cs_decoder_decoded_orMatrixOutputs_hi_32 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19)
node _cs_decoder_decoded_orMatrixOutputs_T_84 = cat(cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_27)
node _cs_decoder_decoded_orMatrixOutputs_T_85 = orr(_cs_decoder_decoded_orMatrixOutputs_T_84)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_14_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_66_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_63_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_156_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_154_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9)
node cs_decoder_decoded_orMatrixOutputs_lo_28 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_lo_19)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = cat(cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_166_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_68_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_43_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_82_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = cat(cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_38_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_174_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = cat(cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_48_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10)
node cs_decoder_decoded_orMatrixOutputs_hi_33 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20)
node _cs_decoder_decoded_orMatrixOutputs_T_86 = cat(cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_orMatrixOutputs_lo_28)
node _cs_decoder_decoded_orMatrixOutputs_T_87 = orr(_cs_decoder_decoded_orMatrixOutputs_T_86)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = cat(cs_decoder_decoded_andMatrixOutputs_31_2, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = cat(cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_59_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10)
node cs_decoder_decoded_orMatrixOutputs_lo_29 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_lo_20)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = cat(cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_45_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_147_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = cat(cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_43_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11)
node cs_decoder_decoded_orMatrixOutputs_hi_34 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21)
node _cs_decoder_decoded_orMatrixOutputs_T_88 = cat(cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_29)
node _cs_decoder_decoded_orMatrixOutputs_T_89 = orr(_cs_decoder_decoded_orMatrixOutputs_T_88)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = cat(cs_decoder_decoded_andMatrixOutputs_111_2, cs_decoder_decoded_andMatrixOutputs_127_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_171_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_39_2)
node cs_decoder_decoded_orMatrixOutputs_lo_30 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_lo_21)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = cat(cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_33_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_87_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = cat(cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_118_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_3_2)
node cs_decoder_decoded_orMatrixOutputs_hi_35 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22)
node _cs_decoder_decoded_orMatrixOutputs_T_90 = cat(cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_30)
node _cs_decoder_decoded_orMatrixOutputs_T_91 = orr(_cs_decoder_decoded_orMatrixOutputs_T_90)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = cat(cs_decoder_decoded_andMatrixOutputs_90_2, cs_decoder_decoded_andMatrixOutputs_86_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_120_2)
node cs_decoder_decoded_orMatrixOutputs_lo_31 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_22)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = cat(cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_169_2)
node cs_decoder_decoded_orMatrixOutputs_hi_36 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_orMatrixOutputs_hi_lo_23)
node _cs_decoder_decoded_orMatrixOutputs_T_92 = cat(cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_31)
node _cs_decoder_decoded_orMatrixOutputs_T_93 = orr(_cs_decoder_decoded_orMatrixOutputs_T_92)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_106_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_90_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_88_2)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_23 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_92_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_135_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_6_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = cat(cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_166_2)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11)
node cs_decoder_decoded_orMatrixOutputs_lo_32 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_23)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(cs_decoder_decoded_andMatrixOutputs_70_2, cs_decoder_decoded_andMatrixOutputs_125_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_16_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = cat(cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_114_2, cs_decoder_decoded_andMatrixOutputs_139_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_67_2)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = cat(cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = cat(cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_5_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_75_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_34_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = cat(cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_29_2)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12)
node cs_decoder_decoded_orMatrixOutputs_hi_37 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_24)
node _cs_decoder_decoded_orMatrixOutputs_T_94 = cat(cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_32)
node _cs_decoder_decoded_orMatrixOutputs_T_95 = orr(_cs_decoder_decoded_orMatrixOutputs_T_94)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_1)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_8, _cs_decoder_decoded_orMatrixOutputs_T_7)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_5)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_14, _cs_decoder_decoded_orMatrixOutputs_T_12)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_10)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(_cs_decoder_decoded_orMatrixOutputs_T_18, _cs_decoder_decoded_orMatrixOutputs_T_16)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_22, _cs_decoder_decoded_orMatrixOutputs_T_20)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_lo_lo_24 = cat(cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_25, _cs_decoder_decoded_orMatrixOutputs_T_24)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_23)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_30, _cs_decoder_decoded_orMatrixOutputs_T_28)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_26)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_32)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(_cs_decoder_decoded_orMatrixOutputs_T_38, _cs_decoder_decoded_orMatrixOutputs_T_37)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = cat(_cs_decoder_decoded_orMatrixOutputs_T_42, _cs_decoder_decoded_orMatrixOutputs_T_40)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12)
node cs_decoder_decoded_orMatrixOutputs_lo_33 = cat(cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_24)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_48, _cs_decoder_decoded_orMatrixOutputs_T_46)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_44)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_54, _cs_decoder_decoded_orMatrixOutputs_T_52)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_50)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_59, _cs_decoder_decoded_orMatrixOutputs_T_58)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_56)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(_cs_decoder_decoded_orMatrixOutputs_T_63, _cs_decoder_decoded_orMatrixOutputs_T_61)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_67, _cs_decoder_decoded_orMatrixOutputs_T_65)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6)
node cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = cat(cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(_cs_decoder_decoded_orMatrixOutputs_T_73, _cs_decoder_decoded_orMatrixOutputs_T_71)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_69)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(_cs_decoder_decoded_orMatrixOutputs_T_77, _cs_decoder_decoded_orMatrixOutputs_T_75)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = cat(_cs_decoder_decoded_orMatrixOutputs_T_81, _cs_decoder_decoded_orMatrixOutputs_T_79)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = cat(_cs_decoder_decoded_orMatrixOutputs_T_87, _cs_decoder_decoded_orMatrixOutputs_T_85)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_83)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(_cs_decoder_decoded_orMatrixOutputs_T_91, _cs_decoder_decoded_orMatrixOutputs_T_89)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = cat(_cs_decoder_decoded_orMatrixOutputs_T_95, _cs_decoder_decoded_orMatrixOutputs_T_93)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7)
node cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13)
node cs_decoder_decoded_orMatrixOutputs_hi_38 = cat(cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_25)
node cs_decoder_decoded_orMatrixOutputs = cat(cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_33)
node _cs_decoder_decoded_invMatrixOutputs_T = bits(cs_decoder_decoded_orMatrixOutputs, 0, 0)
node _cs_decoder_decoded_invMatrixOutputs_T_1 = bits(cs_decoder_decoded_orMatrixOutputs, 1, 1)
node _cs_decoder_decoded_invMatrixOutputs_T_2 = bits(cs_decoder_decoded_orMatrixOutputs, 2, 2)
node _cs_decoder_decoded_invMatrixOutputs_T_3 = bits(cs_decoder_decoded_orMatrixOutputs, 3, 3)
node _cs_decoder_decoded_invMatrixOutputs_T_4 = bits(cs_decoder_decoded_orMatrixOutputs, 4, 4)
node _cs_decoder_decoded_invMatrixOutputs_T_5 = bits(cs_decoder_decoded_orMatrixOutputs, 5, 5)
node _cs_decoder_decoded_invMatrixOutputs_T_6 = bits(cs_decoder_decoded_orMatrixOutputs, 6, 6)
node _cs_decoder_decoded_invMatrixOutputs_T_7 = bits(cs_decoder_decoded_orMatrixOutputs, 7, 7)
node _cs_decoder_decoded_invMatrixOutputs_T_8 = bits(cs_decoder_decoded_orMatrixOutputs, 8, 8)
node _cs_decoder_decoded_invMatrixOutputs_T_9 = bits(cs_decoder_decoded_orMatrixOutputs, 9, 9)
node _cs_decoder_decoded_invMatrixOutputs_T_10 = bits(cs_decoder_decoded_orMatrixOutputs, 10, 10)
node _cs_decoder_decoded_invMatrixOutputs_T_11 = bits(cs_decoder_decoded_orMatrixOutputs, 11, 11)
node _cs_decoder_decoded_invMatrixOutputs_T_12 = bits(cs_decoder_decoded_orMatrixOutputs, 12, 12)
node _cs_decoder_decoded_invMatrixOutputs_T_13 = bits(cs_decoder_decoded_orMatrixOutputs, 13, 13)
node _cs_decoder_decoded_invMatrixOutputs_T_14 = bits(cs_decoder_decoded_orMatrixOutputs, 14, 14)
node _cs_decoder_decoded_invMatrixOutputs_T_15 = bits(cs_decoder_decoded_orMatrixOutputs, 15, 15)
node _cs_decoder_decoded_invMatrixOutputs_T_16 = bits(cs_decoder_decoded_orMatrixOutputs, 16, 16)
node _cs_decoder_decoded_invMatrixOutputs_T_17 = bits(cs_decoder_decoded_orMatrixOutputs, 17, 17)
node _cs_decoder_decoded_invMatrixOutputs_T_18 = bits(cs_decoder_decoded_orMatrixOutputs, 18, 18)
node _cs_decoder_decoded_invMatrixOutputs_T_19 = bits(cs_decoder_decoded_orMatrixOutputs, 19, 19)
node _cs_decoder_decoded_invMatrixOutputs_T_20 = bits(cs_decoder_decoded_orMatrixOutputs, 20, 20)
node _cs_decoder_decoded_invMatrixOutputs_T_21 = bits(cs_decoder_decoded_orMatrixOutputs, 21, 21)
node _cs_decoder_decoded_invMatrixOutputs_T_22 = bits(cs_decoder_decoded_orMatrixOutputs, 22, 22)
node _cs_decoder_decoded_invMatrixOutputs_T_23 = bits(cs_decoder_decoded_orMatrixOutputs, 23, 23)
node _cs_decoder_decoded_invMatrixOutputs_T_24 = bits(cs_decoder_decoded_orMatrixOutputs, 24, 24)
node _cs_decoder_decoded_invMatrixOutputs_T_25 = bits(cs_decoder_decoded_orMatrixOutputs, 25, 25)
node _cs_decoder_decoded_invMatrixOutputs_T_26 = bits(cs_decoder_decoded_orMatrixOutputs, 26, 26)
node _cs_decoder_decoded_invMatrixOutputs_T_27 = bits(cs_decoder_decoded_orMatrixOutputs, 27, 27)
node _cs_decoder_decoded_invMatrixOutputs_T_28 = bits(cs_decoder_decoded_orMatrixOutputs, 28, 28)
node _cs_decoder_decoded_invMatrixOutputs_T_29 = bits(cs_decoder_decoded_orMatrixOutputs, 29, 29)
node _cs_decoder_decoded_invMatrixOutputs_T_30 = not(_cs_decoder_decoded_invMatrixOutputs_T_29)
node _cs_decoder_decoded_invMatrixOutputs_T_31 = bits(cs_decoder_decoded_orMatrixOutputs, 30, 30)
node _cs_decoder_decoded_invMatrixOutputs_T_32 = bits(cs_decoder_decoded_orMatrixOutputs, 31, 31)
node _cs_decoder_decoded_invMatrixOutputs_T_33 = bits(cs_decoder_decoded_orMatrixOutputs, 32, 32)
node _cs_decoder_decoded_invMatrixOutputs_T_34 = bits(cs_decoder_decoded_orMatrixOutputs, 33, 33)
node _cs_decoder_decoded_invMatrixOutputs_T_35 = bits(cs_decoder_decoded_orMatrixOutputs, 34, 34)
node _cs_decoder_decoded_invMatrixOutputs_T_36 = bits(cs_decoder_decoded_orMatrixOutputs, 35, 35)
node _cs_decoder_decoded_invMatrixOutputs_T_37 = bits(cs_decoder_decoded_orMatrixOutputs, 36, 36)
node _cs_decoder_decoded_invMatrixOutputs_T_38 = bits(cs_decoder_decoded_orMatrixOutputs, 37, 37)
node _cs_decoder_decoded_invMatrixOutputs_T_39 = bits(cs_decoder_decoded_orMatrixOutputs, 38, 38)
node _cs_decoder_decoded_invMatrixOutputs_T_40 = bits(cs_decoder_decoded_orMatrixOutputs, 39, 39)
node _cs_decoder_decoded_invMatrixOutputs_T_41 = bits(cs_decoder_decoded_orMatrixOutputs, 40, 40)
node _cs_decoder_decoded_invMatrixOutputs_T_42 = not(_cs_decoder_decoded_invMatrixOutputs_T_41)
node _cs_decoder_decoded_invMatrixOutputs_T_43 = bits(cs_decoder_decoded_orMatrixOutputs, 41, 41)
node _cs_decoder_decoded_invMatrixOutputs_T_44 = bits(cs_decoder_decoded_orMatrixOutputs, 42, 42)
node _cs_decoder_decoded_invMatrixOutputs_T_45 = bits(cs_decoder_decoded_orMatrixOutputs, 43, 43)
node _cs_decoder_decoded_invMatrixOutputs_T_46 = bits(cs_decoder_decoded_orMatrixOutputs, 44, 44)
node _cs_decoder_decoded_invMatrixOutputs_T_47 = bits(cs_decoder_decoded_orMatrixOutputs, 45, 45)
node _cs_decoder_decoded_invMatrixOutputs_T_48 = bits(cs_decoder_decoded_orMatrixOutputs, 46, 46)
node _cs_decoder_decoded_invMatrixOutputs_T_49 = bits(cs_decoder_decoded_orMatrixOutputs, 47, 47)
node _cs_decoder_decoded_invMatrixOutputs_T_50 = bits(cs_decoder_decoded_orMatrixOutputs, 48, 48)
node _cs_decoder_decoded_invMatrixOutputs_T_51 = bits(cs_decoder_decoded_orMatrixOutputs, 49, 49)
node _cs_decoder_decoded_invMatrixOutputs_T_52 = bits(cs_decoder_decoded_orMatrixOutputs, 50, 50)
node _cs_decoder_decoded_invMatrixOutputs_T_53 = bits(cs_decoder_decoded_orMatrixOutputs, 51, 51)
node _cs_decoder_decoded_invMatrixOutputs_T_54 = bits(cs_decoder_decoded_orMatrixOutputs, 52, 52)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_5, _cs_decoder_decoded_invMatrixOutputs_T_4)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_3)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_8, _cs_decoder_decoded_invMatrixOutputs_T_7)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_6)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_10, _cs_decoder_decoded_invMatrixOutputs_T_9)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_12, _cs_decoder_decoded_invMatrixOutputs_T_11)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_15, _cs_decoder_decoded_invMatrixOutputs_T_14)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_13)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_16)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_21, _cs_decoder_decoded_invMatrixOutputs_T_20)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_19)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_lo = cat(cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_28, _cs_decoder_decoded_invMatrixOutputs_T_27)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_26)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_30)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_35, _cs_decoder_decoded_invMatrixOutputs_T_34)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_33)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_37, _cs_decoder_decoded_invMatrixOutputs_T_36)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_38)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_40)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_45, _cs_decoder_decoded_invMatrixOutputs_T_44)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_46)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_50, _cs_decoder_decoded_invMatrixOutputs_T_49)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_48)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(_cs_decoder_decoded_invMatrixOutputs_T_52, _cs_decoder_decoded_invMatrixOutputs_T_51)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(_cs_decoder_decoded_invMatrixOutputs_T_54, _cs_decoder_decoded_invMatrixOutputs_T_53)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo)
node cs_decoder_decoded_invMatrixOutputs_hi = cat(cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo)
node cs_decoder_decoded_invMatrixOutputs = cat(cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo)
connect cs_decoder_decoded, cs_decoder_decoded_invMatrixOutputs
connect cs_decoder_decoded_plaInput, uop.inst
node cs_decoder_0 = bits(cs_decoder_decoded, 52, 52)
node cs_decoder_1 = bits(cs_decoder_decoded, 51, 51)
node cs_decoder_2 = bits(cs_decoder_decoded, 50, 50)
node cs_decoder_3 = bits(cs_decoder_decoded, 49, 43)
node cs_decoder_4 = bits(cs_decoder_decoded, 42, 40)
node cs_decoder_5 = bits(cs_decoder_decoded, 39, 30)
node cs_decoder_6 = bits(cs_decoder_decoded, 29, 28)
node cs_decoder_7 = bits(cs_decoder_decoded, 27, 26)
node cs_decoder_8 = bits(cs_decoder_decoded, 25, 24)
node cs_decoder_9 = bits(cs_decoder_decoded, 23, 23)
node cs_decoder_10 = bits(cs_decoder_decoded, 22, 20)
node cs_decoder_11 = bits(cs_decoder_decoded, 19, 19)
node cs_decoder_12 = bits(cs_decoder_decoded, 18, 18)
node cs_decoder_13 = bits(cs_decoder_decoded, 17, 17)
node cs_decoder_14 = bits(cs_decoder_decoded, 16, 16)
node cs_decoder_15 = bits(cs_decoder_decoded, 15, 15)
node cs_decoder_16 = bits(cs_decoder_decoded, 14, 10)
node cs_decoder_17 = bits(cs_decoder_decoded, 9, 8)
node cs_decoder_18 = bits(cs_decoder_decoded, 7, 7)
node cs_decoder_19 = bits(cs_decoder_decoded, 6, 6)
node cs_decoder_20 = bits(cs_decoder_decoded, 5, 5)
node cs_decoder_21 = bits(cs_decoder_decoded, 4, 4)
node cs_decoder_22 = bits(cs_decoder_decoded, 3, 3)
node cs_decoder_23 = bits(cs_decoder_decoded, 2, 0)
connect cs.legal, cs_decoder_0
connect cs.fp_val, cs_decoder_1
connect cs.fp_single, cs_decoder_2
connect cs.uopc, cs_decoder_3
connect cs.iq_type, cs_decoder_4
connect cs.fu_code, cs_decoder_5
connect cs.dst_type, cs_decoder_6
connect cs.rs1_type, cs_decoder_7
connect cs.rs2_type, cs_decoder_8
connect cs.frs3_en, cs_decoder_9
connect cs.imm_sel, cs_decoder_10
connect cs.uses_ldq, cs_decoder_11
connect cs.uses_stq, cs_decoder_12
connect cs.is_amo, cs_decoder_13
connect cs.is_fence, cs_decoder_14
connect cs.is_fencei, cs_decoder_15
connect cs.mem_cmd, cs_decoder_16
connect cs.wakeup_delay, cs_decoder_17
connect cs.bypassable, cs_decoder_18
connect cs.is_br, cs_decoder_19
connect cs.is_sys_pc2epc, cs_decoder_20
connect cs.inst_unique, cs_decoder_21
connect cs.flush_on_commit, cs_decoder_22
connect cs.csr_cmd, cs_decoder_23
connect cs.rocc, UInt<1>(0h0)
connect io.csr_decode.inst, uop.inst
node _csr_en_T = eq(cs.csr_cmd, UInt<3>(0h6))
node _csr_en_T_1 = eq(cs.csr_cmd, UInt<3>(0h7))
node _csr_en_T_2 = eq(cs.csr_cmd, UInt<3>(0h5))
node _csr_en_T_3 = or(_csr_en_T, _csr_en_T_1)
node csr_en = or(_csr_en_T_3, _csr_en_T_2)
node _csr_ren_T = eq(cs.csr_cmd, UInt<3>(0h6))
node _csr_ren_T_1 = eq(cs.csr_cmd, UInt<3>(0h7))
node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1)
node _csr_ren_T_3 = eq(uop.lrs1, UInt<1>(0h0))
node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3)
node system_insn = eq(cs.csr_cmd, UInt<3>(0h4))
node sfence = eq(cs.uopc, UInt<7>(0h6b))
node _id_illegal_insn_T = eq(cs.legal, UInt<1>(0h0))
node _id_illegal_insn_T_1 = and(cs.fp_val, io.csr_decode.fp_illegal)
node _id_illegal_insn_T_2 = or(_id_illegal_insn_T, _id_illegal_insn_T_1)
node _id_illegal_insn_T_3 = and(cs.rocc, io.csr_decode.rocc_illegal)
node _id_illegal_insn_T_4 = or(_id_illegal_insn_T_2, _id_illegal_insn_T_3)
node _id_illegal_insn_T_5 = bits(io.status.isa, 0, 0)
node _id_illegal_insn_T_6 = eq(_id_illegal_insn_T_5, UInt<1>(0h0))
node _id_illegal_insn_T_7 = and(cs.is_amo, _id_illegal_insn_T_6)
node _id_illegal_insn_T_8 = or(_id_illegal_insn_T_4, _id_illegal_insn_T_7)
node _id_illegal_insn_T_9 = eq(cs.fp_single, UInt<1>(0h0))
node _id_illegal_insn_T_10 = and(cs.fp_val, _id_illegal_insn_T_9)
node _id_illegal_insn_T_11 = bits(io.status.isa, 3, 3)
node _id_illegal_insn_T_12 = eq(_id_illegal_insn_T_11, UInt<1>(0h0))
node _id_illegal_insn_T_13 = and(_id_illegal_insn_T_10, _id_illegal_insn_T_12)
node _id_illegal_insn_T_14 = or(_id_illegal_insn_T_8, _id_illegal_insn_T_13)
node _id_illegal_insn_T_15 = eq(csr_ren, UInt<1>(0h0))
node _id_illegal_insn_T_16 = and(_id_illegal_insn_T_15, io.csr_decode.write_illegal)
node _id_illegal_insn_T_17 = or(io.csr_decode.read_illegal, _id_illegal_insn_T_16)
node _id_illegal_insn_T_18 = and(csr_en, _id_illegal_insn_T_17)
node _id_illegal_insn_T_19 = or(_id_illegal_insn_T_14, _id_illegal_insn_T_18)
node _id_illegal_insn_T_20 = or(sfence, system_insn)
node _id_illegal_insn_T_21 = and(_id_illegal_insn_T_20, io.csr_decode.system_illegal)
node id_illegal_insn = or(_id_illegal_insn_T_19, _id_illegal_insn_T_21)
node _T = eq(io.enq.uop.is_sfb, UInt<1>(0h0))
node _T_1 = and(io.interrupt, _T)
node _T_2 = or(_T_1, uop.bp_debug_if)
node _T_3 = or(_T_2, uop.bp_xcpt_if)
node _T_4 = or(_T_3, uop.xcpt_pf_if)
node _T_5 = or(_T_4, uop.xcpt_ae_if)
node xcpt_valid = or(_T_5, id_illegal_insn)
node _T_6 = mux(uop.xcpt_ae_if, UInt<1>(0h1), UInt<2>(0h2))
node _T_7 = mux(uop.xcpt_pf_if, UInt<4>(0hc), _T_6)
node _T_8 = mux(uop.bp_xcpt_if, UInt<2>(0h3), _T_7)
node _T_9 = mux(uop.bp_debug_if, UInt<4>(0he), _T_8)
node xcpt_cause = mux(_T_1, io.interrupt_cause, _T_9)
connect uop.exception, xcpt_valid
connect uop.exc_cause, xcpt_cause
connect uop.uopc, cs.uopc
connect uop.iq_type, cs.iq_type
connect uop.fu_code, cs.fu_code
node _uop_ldst_T = bits(uop.inst, 11, 7)
connect uop.ldst, _uop_ldst_T
node _uop_lrs1_T = bits(uop.inst, 19, 15)
connect uop.lrs1, _uop_lrs1_T
node _uop_lrs2_T = bits(uop.inst, 24, 20)
connect uop.lrs2, _uop_lrs2_T
node _uop_lrs3_T = bits(uop.inst, 31, 27)
connect uop.lrs3, _uop_lrs3_T
node _uop_ldst_val_T = neq(cs.dst_type, UInt<2>(0h2))
node _uop_ldst_val_T_1 = eq(uop.ldst, UInt<1>(0h0))
node _uop_ldst_val_T_2 = eq(uop.dst_rtype, UInt<2>(0h0))
node _uop_ldst_val_T_3 = and(_uop_ldst_val_T_1, _uop_ldst_val_T_2)
node _uop_ldst_val_T_4 = eq(_uop_ldst_val_T_3, UInt<1>(0h0))
node _uop_ldst_val_T_5 = and(_uop_ldst_val_T, _uop_ldst_val_T_4)
connect uop.ldst_val, _uop_ldst_val_T_5
connect uop.dst_rtype, cs.dst_type
connect uop.lrs1_rtype, cs.rs1_type
connect uop.lrs2_rtype, cs.rs2_type
connect uop.frs3_en, cs.frs3_en
node _uop_ldst_is_rs1_T = eq(uop.is_br, UInt<1>(0h0))
node _uop_ldst_is_rs1_T_1 = and(_uop_ldst_is_rs1_T, uop.is_sfb)
node _uop_ldst_is_rs1_T_2 = and(_uop_ldst_is_rs1_T_1, UInt<1>(0h0))
connect uop.ldst_is_rs1, _uop_ldst_is_rs1_T_2
node _T_10 = eq(uop.is_br, UInt<1>(0h0))
node _T_11 = and(_T_10, uop.is_sfb)
node _T_12 = and(_T_11, UInt<1>(0h0))
node _T_13 = eq(cs.rs2_type, UInt<2>(0h2))
node _T_14 = and(_T_12, _T_13)
when _T_14 :
connect uop.lrs2_rtype, UInt<2>(0h0)
node _uop_lrs2_T_1 = bits(uop.inst, 11, 7)
connect uop.lrs2, _uop_lrs2_T_1
connect uop.ldst_is_rs1, UInt<1>(0h0)
else :
node _T_15 = eq(uop.is_br, UInt<1>(0h0))
node _T_16 = and(_T_15, uop.is_sfb)
node _T_17 = and(_T_16, UInt<1>(0h0))
node _T_18 = eq(cs.uopc, UInt<7>(0hf))
node _T_19 = and(_T_17, _T_18)
node _T_20 = bits(uop.inst, 19, 15)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = and(_T_19, _T_21)
when _T_22 :
connect uop.uopc, UInt<7>(0h6d)
node _uop_lrs1_T_1 = bits(uop.inst, 11, 7)
connect uop.lrs1, _uop_lrs1_T_1
connect uop.ldst_is_rs1, UInt<1>(0h1)
node _T_23 = and(uop.is_br, uop.is_sfb)
node _T_24 = and(_T_23, UInt<1>(0h0))
when _T_24 :
connect uop.fu_code, UInt<10>(0h2)
connect uop.fp_val, cs.fp_val
connect uop.fp_single, cs.fp_single
connect uop.mem_cmd, cs.mem_cmd
node _uop_mem_size_T = eq(cs.mem_cmd, UInt<5>(0h14))
node _uop_mem_size_T_1 = eq(cs.mem_cmd, UInt<3>(0h5))
node _uop_mem_size_T_2 = or(_uop_mem_size_T, _uop_mem_size_T_1)
node _uop_mem_size_T_3 = neq(uop.lrs2, UInt<1>(0h0))
node _uop_mem_size_T_4 = neq(uop.lrs1, UInt<1>(0h0))
node _uop_mem_size_T_5 = cat(_uop_mem_size_T_3, _uop_mem_size_T_4)
node _uop_mem_size_T_6 = bits(uop.inst, 13, 12)
node _uop_mem_size_T_7 = mux(_uop_mem_size_T_2, _uop_mem_size_T_5, _uop_mem_size_T_6)
connect uop.mem_size, _uop_mem_size_T_7
node _uop_mem_signed_T = bits(uop.inst, 14, 14)
node _uop_mem_signed_T_1 = eq(_uop_mem_signed_T, UInt<1>(0h0))
connect uop.mem_signed, _uop_mem_signed_T_1
connect uop.uses_ldq, cs.uses_ldq
connect uop.uses_stq, cs.uses_stq
connect uop.is_amo, cs.is_amo
connect uop.is_fence, cs.is_fence
connect uop.is_fencei, cs.is_fencei
connect uop.is_sys_pc2epc, cs.is_sys_pc2epc
connect uop.is_unique, cs.inst_unique
node _uop_flush_on_commit_T = eq(csr_ren, UInt<1>(0h0))
node _uop_flush_on_commit_T_1 = and(csr_en, _uop_flush_on_commit_T)
node _uop_flush_on_commit_T_2 = and(_uop_flush_on_commit_T_1, io.csr_decode.write_flush)
node _uop_flush_on_commit_T_3 = or(cs.flush_on_commit, _uop_flush_on_commit_T_2)
connect uop.flush_on_commit, _uop_flush_on_commit_T_3
connect uop.bypassable, cs.bypassable
node _di24_20_T = eq(cs.imm_sel, UInt<3>(0h2))
node _di24_20_T_1 = eq(cs.imm_sel, UInt<3>(0h1))
node _di24_20_T_2 = or(_di24_20_T, _di24_20_T_1)
node _di24_20_T_3 = bits(uop.inst, 11, 7)
node _di24_20_T_4 = bits(uop.inst, 24, 20)
node di24_20 = mux(_di24_20_T_2, _di24_20_T_3, _di24_20_T_4)
node _uop_imm_packed_T = bits(uop.inst, 31, 25)
node _uop_imm_packed_T_1 = bits(uop.inst, 19, 12)
node uop_imm_packed_hi = cat(_uop_imm_packed_T, di24_20)
node _uop_imm_packed_T_2 = cat(uop_imm_packed_hi, _uop_imm_packed_T_1)
connect uop.imm_packed, _uop_imm_packed_T_2
connect uop.is_br, cs.is_br
node _uop_is_jal_T = eq(uop.uopc, UInt<7>(0h25))
connect uop.is_jal, _uop_is_jal_T
node _uop_is_jalr_T = eq(uop.uopc, UInt<7>(0h26))
connect uop.is_jalr, _uop_is_jalr_T
connect io.deq.uop, uop | module DecodeUnit( // @[decode.scala:474:7]
input clock, // @[decode.scala:474:7]
input reset, // @[decode.scala:474:7]
input [31:0] io_enq_uop_inst, // @[decode.scala:477:14]
input [31:0] io_enq_uop_debug_inst, // @[decode.scala:477:14]
input io_enq_uop_is_rvc, // @[decode.scala:477:14]
input [39:0] io_enq_uop_debug_pc, // @[decode.scala:477:14]
input io_enq_uop_is_sfb, // @[decode.scala:477:14]
input [4:0] io_enq_uop_ftq_idx, // @[decode.scala:477:14]
input io_enq_uop_edge_inst, // @[decode.scala:477:14]
input [5:0] io_enq_uop_pc_lob, // @[decode.scala:477:14]
input io_enq_uop_taken, // @[decode.scala:477:14]
input io_enq_uop_xcpt_pf_if, // @[decode.scala:477:14]
input io_enq_uop_xcpt_ae_if, // @[decode.scala:477:14]
input io_enq_uop_bp_debug_if, // @[decode.scala:477:14]
input io_enq_uop_bp_xcpt_if, // @[decode.scala:477:14]
input [1:0] io_enq_uop_debug_fsrc, // @[decode.scala:477:14]
output [6:0] io_deq_uop_uopc, // @[decode.scala:477:14]
output [31:0] io_deq_uop_inst, // @[decode.scala:477:14]
output [31:0] io_deq_uop_debug_inst, // @[decode.scala:477:14]
output io_deq_uop_is_rvc, // @[decode.scala:477:14]
output [39:0] io_deq_uop_debug_pc, // @[decode.scala:477:14]
output [2:0] io_deq_uop_iq_type, // @[decode.scala:477:14]
output [9:0] io_deq_uop_fu_code, // @[decode.scala:477:14]
output io_deq_uop_is_br, // @[decode.scala:477:14]
output io_deq_uop_is_jalr, // @[decode.scala:477:14]
output io_deq_uop_is_jal, // @[decode.scala:477:14]
output io_deq_uop_is_sfb, // @[decode.scala:477:14]
output [4:0] io_deq_uop_ftq_idx, // @[decode.scala:477:14]
output io_deq_uop_edge_inst, // @[decode.scala:477:14]
output [5:0] io_deq_uop_pc_lob, // @[decode.scala:477:14]
output io_deq_uop_taken, // @[decode.scala:477:14]
output [19:0] io_deq_uop_imm_packed, // @[decode.scala:477:14]
output io_deq_uop_exception, // @[decode.scala:477:14]
output [63:0] io_deq_uop_exc_cause, // @[decode.scala:477:14]
output io_deq_uop_bypassable, // @[decode.scala:477:14]
output [4:0] io_deq_uop_mem_cmd, // @[decode.scala:477:14]
output [1:0] io_deq_uop_mem_size, // @[decode.scala:477:14]
output io_deq_uop_mem_signed, // @[decode.scala:477:14]
output io_deq_uop_is_fence, // @[decode.scala:477:14]
output io_deq_uop_is_fencei, // @[decode.scala:477:14]
output io_deq_uop_is_amo, // @[decode.scala:477:14]
output io_deq_uop_uses_ldq, // @[decode.scala:477:14]
output io_deq_uop_uses_stq, // @[decode.scala:477:14]
output io_deq_uop_is_sys_pc2epc, // @[decode.scala:477:14]
output io_deq_uop_is_unique, // @[decode.scala:477:14]
output io_deq_uop_flush_on_commit, // @[decode.scala:477:14]
output [5:0] io_deq_uop_ldst, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs1, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs2, // @[decode.scala:477:14]
output [5:0] io_deq_uop_lrs3, // @[decode.scala:477:14]
output io_deq_uop_ldst_val, // @[decode.scala:477:14]
output [1:0] io_deq_uop_dst_rtype, // @[decode.scala:477:14]
output [1:0] io_deq_uop_lrs1_rtype, // @[decode.scala:477:14]
output [1:0] io_deq_uop_lrs2_rtype, // @[decode.scala:477:14]
output io_deq_uop_frs3_en, // @[decode.scala:477:14]
output io_deq_uop_fp_val, // @[decode.scala:477:14]
output io_deq_uop_fp_single, // @[decode.scala:477:14]
output io_deq_uop_xcpt_pf_if, // @[decode.scala:477:14]
output io_deq_uop_xcpt_ae_if, // @[decode.scala:477:14]
output io_deq_uop_bp_debug_if, // @[decode.scala:477:14]
output io_deq_uop_bp_xcpt_if, // @[decode.scala:477:14]
output [1:0] io_deq_uop_debug_fsrc, // @[decode.scala:477:14]
input io_status_debug, // @[decode.scala:477:14]
input io_status_cease, // @[decode.scala:477:14]
input io_status_wfi, // @[decode.scala:477:14]
input [1:0] io_status_dprv, // @[decode.scala:477:14]
input io_status_dv, // @[decode.scala:477:14]
input [1:0] io_status_prv, // @[decode.scala:477:14]
input io_status_v, // @[decode.scala:477:14]
input io_status_sd, // @[decode.scala:477:14]
input io_status_mpv, // @[decode.scala:477:14]
input io_status_gva, // @[decode.scala:477:14]
input io_status_tsr, // @[decode.scala:477:14]
input io_status_tw, // @[decode.scala:477:14]
input io_status_tvm, // @[decode.scala:477:14]
input io_status_mxr, // @[decode.scala:477:14]
input io_status_sum, // @[decode.scala:477:14]
input io_status_mprv, // @[decode.scala:477:14]
input [1:0] io_status_fs, // @[decode.scala:477:14]
input [1:0] io_status_mpp, // @[decode.scala:477:14]
input io_status_spp, // @[decode.scala:477:14]
input io_status_mpie, // @[decode.scala:477:14]
input io_status_spie, // @[decode.scala:477:14]
input io_status_mie, // @[decode.scala:477:14]
input io_status_sie, // @[decode.scala:477:14]
output [31:0] io_csr_decode_inst, // @[decode.scala:477:14]
input io_csr_decode_fp_illegal, // @[decode.scala:477:14]
input io_csr_decode_fp_csr, // @[decode.scala:477:14]
input io_csr_decode_read_illegal, // @[decode.scala:477:14]
input io_csr_decode_write_illegal, // @[decode.scala:477:14]
input io_csr_decode_write_flush, // @[decode.scala:477:14]
input io_csr_decode_system_illegal, // @[decode.scala:477:14]
input io_csr_decode_virtual_access_illegal, // @[decode.scala:477:14]
input io_csr_decode_virtual_system_illegal, // @[decode.scala:477:14]
input io_interrupt, // @[decode.scala:477:14]
input [63:0] io_interrupt_cause // @[decode.scala:477:14]
);
wire [31:0] io_enq_uop_inst_0 = io_enq_uop_inst; // @[decode.scala:474:7]
wire [31:0] io_enq_uop_debug_inst_0 = io_enq_uop_debug_inst; // @[decode.scala:474:7]
wire io_enq_uop_is_rvc_0 = io_enq_uop_is_rvc; // @[decode.scala:474:7]
wire [39:0] io_enq_uop_debug_pc_0 = io_enq_uop_debug_pc; // @[decode.scala:474:7]
wire io_enq_uop_is_sfb_0 = io_enq_uop_is_sfb; // @[decode.scala:474:7]
wire [4:0] io_enq_uop_ftq_idx_0 = io_enq_uop_ftq_idx; // @[decode.scala:474:7]
wire io_enq_uop_edge_inst_0 = io_enq_uop_edge_inst; // @[decode.scala:474:7]
wire [5:0] io_enq_uop_pc_lob_0 = io_enq_uop_pc_lob; // @[decode.scala:474:7]
wire io_enq_uop_taken_0 = io_enq_uop_taken; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_pf_if_0 = io_enq_uop_xcpt_pf_if; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_ae_if_0 = io_enq_uop_xcpt_ae_if; // @[decode.scala:474:7]
wire io_enq_uop_bp_debug_if_0 = io_enq_uop_bp_debug_if; // @[decode.scala:474:7]
wire io_enq_uop_bp_xcpt_if_0 = io_enq_uop_bp_xcpt_if; // @[decode.scala:474:7]
wire [1:0] io_enq_uop_debug_fsrc_0 = io_enq_uop_debug_fsrc; // @[decode.scala:474:7]
wire io_status_debug_0 = io_status_debug; // @[decode.scala:474:7]
wire io_status_cease_0 = io_status_cease; // @[decode.scala:474:7]
wire io_status_wfi_0 = io_status_wfi; // @[decode.scala:474:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[decode.scala:474:7]
wire io_status_dv_0 = io_status_dv; // @[decode.scala:474:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[decode.scala:474:7]
wire io_status_v_0 = io_status_v; // @[decode.scala:474:7]
wire io_status_sd_0 = io_status_sd; // @[decode.scala:474:7]
wire io_status_mpv_0 = io_status_mpv; // @[decode.scala:474:7]
wire io_status_gva_0 = io_status_gva; // @[decode.scala:474:7]
wire io_status_tsr_0 = io_status_tsr; // @[decode.scala:474:7]
wire io_status_tw_0 = io_status_tw; // @[decode.scala:474:7]
wire io_status_tvm_0 = io_status_tvm; // @[decode.scala:474:7]
wire io_status_mxr_0 = io_status_mxr; // @[decode.scala:474:7]
wire io_status_sum_0 = io_status_sum; // @[decode.scala:474:7]
wire io_status_mprv_0 = io_status_mprv; // @[decode.scala:474:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[decode.scala:474:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[decode.scala:474:7]
wire io_status_spp_0 = io_status_spp; // @[decode.scala:474:7]
wire io_status_mpie_0 = io_status_mpie; // @[decode.scala:474:7]
wire io_status_spie_0 = io_status_spie; // @[decode.scala:474:7]
wire io_status_mie_0 = io_status_mie; // @[decode.scala:474:7]
wire io_status_sie_0 = io_status_sie; // @[decode.scala:474:7]
wire io_csr_decode_fp_illegal_0 = io_csr_decode_fp_illegal; // @[decode.scala:474:7]
wire io_csr_decode_fp_csr_0 = io_csr_decode_fp_csr; // @[decode.scala:474:7]
wire io_csr_decode_read_illegal_0 = io_csr_decode_read_illegal; // @[decode.scala:474:7]
wire io_csr_decode_write_illegal_0 = io_csr_decode_write_illegal; // @[decode.scala:474:7]
wire io_csr_decode_write_flush_0 = io_csr_decode_write_flush; // @[decode.scala:474:7]
wire io_csr_decode_system_illegal_0 = io_csr_decode_system_illegal; // @[decode.scala:474:7]
wire io_csr_decode_virtual_access_illegal_0 = io_csr_decode_virtual_access_illegal; // @[decode.scala:474:7]
wire io_csr_decode_virtual_system_illegal_0 = io_csr_decode_virtual_system_illegal; // @[decode.scala:474:7]
wire io_interrupt_0 = io_interrupt; // @[decode.scala:474:7]
wire [63:0] io_interrupt_cause_0 = io_interrupt_cause; // @[decode.scala:474:7]
wire [1:0] io_status_sxl = 2'h2; // @[decode.scala:474:7]
wire [1:0] io_status_uxl = 2'h2; // @[decode.scala:474:7]
wire io_csr_decode_vector_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire io_csr_decode_rocc_illegal = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire _id_illegal_insn_T_5 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire _id_illegal_insn_T_11 = 1'h1; // @[decode.scala:474:7, :477:14, :505:32, :506:51]
wire [7:0] io_status_zero1 = 8'h0; // @[decode.scala:474:7, :477:14]
wire [22:0] io_status_zero2 = 23'h0; // @[decode.scala:474:7, :477:14]
wire [31:0] io_status_isa = 32'h14112D; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_ldst = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs1 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs2 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [5:0] io_enq_uop_lrs3 = 6'h0; // @[decode.scala:474:7, :477:14]
wire [63:0] io_enq_uop_exc_cause = 64'h0; // @[decode.scala:474:7, :477:14]
wire [11:0] io_enq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [11:0] io_deq_uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [11:0] uop_csr_addr = 12'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [19:0] io_enq_uop_imm_packed = 20'h0; // @[decode.scala:474:7, :477:14]
wire [15:0] io_enq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [15:0] io_deq_uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [15:0] uop_br_mask = 16'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire io_enq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_br = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_jalr = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_jal = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_exception = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_bypassable = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_mem_signed = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_fence = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_fencei = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_amo = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_uses_ldq = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_uses_stq = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_sys_pc2epc = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_is_unique = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_flush_on_commit = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_ldst_val = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_frs3_en = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_fp_val = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_fp_single = 1'h0; // @[decode.scala:474:7]
wire io_enq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_load = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_sta = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ctrl_is_std = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_iw_p1_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_iw_p2_poisoned = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs1_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs2_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_prs3_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ppred_busy = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_ldst_is_rs1 = 1'h0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_ma_if = 1'h0; // @[decode.scala:474:7]
wire io_status_mbe = 1'h0; // @[decode.scala:474:7]
wire io_status_sbe = 1'h0; // @[decode.scala:474:7]
wire io_status_sd_rv32 = 1'h0; // @[decode.scala:474:7]
wire io_status_ube = 1'h0; // @[decode.scala:474:7]
wire io_status_upie = 1'h0; // @[decode.scala:474:7]
wire io_status_hie = 1'h0; // @[decode.scala:474:7]
wire io_status_uie = 1'h0; // @[decode.scala:474:7]
wire io_csr_decode_vector_csr = 1'h0; // @[decode.scala:474:7]
wire uop_ctrl_fcn_dw = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_load = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_sta = 1'h0; // @[decode.scala:479:17]
wire uop_ctrl_is_std = 1'h0; // @[decode.scala:479:17]
wire uop_iw_p1_poisoned = 1'h0; // @[decode.scala:479:17]
wire uop_iw_p2_poisoned = 1'h0; // @[decode.scala:479:17]
wire uop_prs1_busy = 1'h0; // @[decode.scala:479:17]
wire uop_prs2_busy = 1'h0; // @[decode.scala:479:17]
wire uop_prs3_busy = 1'h0; // @[decode.scala:479:17]
wire uop_ppred_busy = 1'h0; // @[decode.scala:479:17]
wire uop_ldst_is_rs1 = 1'h0; // @[decode.scala:479:17]
wire uop_xcpt_ma_if = 1'h0; // @[decode.scala:479:17]
wire cs_rocc = 1'h0; // @[decode.scala:490:16]
wire _id_illegal_insn_T_3 = 1'h0; // @[decode.scala:504:13]
wire _id_illegal_insn_T_6 = 1'h0; // @[decode.scala:505:18]
wire _id_illegal_insn_T_7 = 1'h0; // @[decode.scala:505:15]
wire _id_illegal_insn_T_12 = 1'h0; // @[decode.scala:506:37]
wire _id_illegal_insn_T_13 = 1'h0; // @[decode.scala:506:34]
wire _uop_ldst_is_rs1_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire [4:0] io_enq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_enq_uop_mem_cmd = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] io_deq_uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ctrl_op_fcn = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ldq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_stq_idx = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [4:0] uop_ppred = 5'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_mem_size = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_dst_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_lrs1_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_lrs2_rtype = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_enq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_deq_uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_status_xs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] io_status_vs = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_ctrl_op1_sel = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_iw_state = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_rxq_idx = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [1:0] uop_debug_tsrc = 2'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_enq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_enq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_deq_uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] io_deq_uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] uop_ctrl_br_type = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [3:0] uop_br_tag = 4'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [9:0] io_enq_uop_fu_code = 10'h0; // @[decode.scala:474:7, :477:14]
wire [2:0] io_enq_uop_iq_type = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_enq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] io_deq_uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_op2_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_imm_sel = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [2:0] uop_ctrl_csr_cmd = 3'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_uopc = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_enq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] io_deq_uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_rob_idx = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs1 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs2 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_prs3 = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [6:0] uop_stale_pdst = 7'h0; // @[decode.scala:474:7, :477:14, :479:17]
wire [31:0] uop_inst = io_enq_uop_inst_0; // @[decode.scala:474:7, :479:17]
wire [31:0] uop_debug_inst = io_enq_uop_debug_inst_0; // @[decode.scala:474:7, :479:17]
wire uop_is_rvc = io_enq_uop_is_rvc_0; // @[decode.scala:474:7, :479:17]
wire [39:0] uop_debug_pc = io_enq_uop_debug_pc_0; // @[decode.scala:474:7, :479:17]
wire uop_is_sfb = io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :479:17]
wire [4:0] uop_ftq_idx = io_enq_uop_ftq_idx_0; // @[decode.scala:474:7, :479:17]
wire uop_edge_inst = io_enq_uop_edge_inst_0; // @[decode.scala:474:7, :479:17]
wire [5:0] uop_pc_lob = io_enq_uop_pc_lob_0; // @[decode.scala:474:7, :479:17]
wire uop_taken = io_enq_uop_taken_0; // @[decode.scala:474:7, :479:17]
wire uop_xcpt_pf_if = io_enq_uop_xcpt_pf_if_0; // @[decode.scala:474:7, :479:17]
wire uop_xcpt_ae_if = io_enq_uop_xcpt_ae_if_0; // @[decode.scala:474:7, :479:17]
wire uop_bp_debug_if = io_enq_uop_bp_debug_if_0; // @[decode.scala:474:7, :479:17]
wire uop_bp_xcpt_if = io_enq_uop_bp_xcpt_if_0; // @[decode.scala:474:7, :479:17]
wire [1:0] uop_debug_fsrc = io_enq_uop_debug_fsrc_0; // @[decode.scala:474:7, :479:17]
wire [6:0] uop_uopc; // @[decode.scala:479:17]
wire [2:0] uop_iq_type; // @[decode.scala:479:17]
wire [9:0] uop_fu_code; // @[decode.scala:479:17]
wire uop_is_br; // @[decode.scala:479:17]
wire uop_is_jalr; // @[decode.scala:479:17]
wire uop_is_jal; // @[decode.scala:479:17]
wire [19:0] uop_imm_packed; // @[decode.scala:479:17]
wire uop_exception; // @[decode.scala:479:17]
wire [63:0] uop_exc_cause; // @[decode.scala:479:17]
wire uop_bypassable; // @[decode.scala:479:17]
wire [4:0] uop_mem_cmd; // @[decode.scala:479:17]
wire [1:0] uop_mem_size; // @[decode.scala:479:17]
wire uop_mem_signed; // @[decode.scala:479:17]
wire uop_is_fence; // @[decode.scala:479:17]
wire uop_is_fencei; // @[decode.scala:479:17]
wire uop_is_amo; // @[decode.scala:479:17]
wire uop_uses_ldq; // @[decode.scala:479:17]
wire uop_uses_stq; // @[decode.scala:479:17]
wire uop_is_sys_pc2epc; // @[decode.scala:479:17]
wire uop_is_unique; // @[decode.scala:479:17]
wire uop_flush_on_commit; // @[decode.scala:479:17]
wire [5:0] uop_ldst; // @[decode.scala:479:17]
wire [5:0] uop_lrs1; // @[decode.scala:479:17]
wire [5:0] uop_lrs2; // @[decode.scala:479:17]
wire [5:0] uop_lrs3; // @[decode.scala:479:17]
wire uop_ldst_val; // @[decode.scala:479:17]
wire [1:0] uop_dst_rtype; // @[decode.scala:479:17]
wire [1:0] uop_lrs1_rtype; // @[decode.scala:479:17]
wire [1:0] uop_lrs2_rtype; // @[decode.scala:479:17]
wire uop_frs3_en; // @[decode.scala:479:17]
wire uop_fp_val; // @[decode.scala:479:17]
wire uop_fp_single; // @[decode.scala:479:17]
wire [6:0] io_deq_uop_uopc_0; // @[decode.scala:474:7]
wire [31:0] io_deq_uop_inst_0; // @[decode.scala:474:7]
wire [31:0] io_deq_uop_debug_inst_0; // @[decode.scala:474:7]
wire io_deq_uop_is_rvc_0; // @[decode.scala:474:7]
wire [39:0] io_deq_uop_debug_pc_0; // @[decode.scala:474:7]
wire [2:0] io_deq_uop_iq_type_0; // @[decode.scala:474:7]
wire [9:0] io_deq_uop_fu_code_0; // @[decode.scala:474:7]
wire io_deq_uop_is_br_0; // @[decode.scala:474:7]
wire io_deq_uop_is_jalr_0; // @[decode.scala:474:7]
wire io_deq_uop_is_jal_0; // @[decode.scala:474:7]
wire io_deq_uop_is_sfb_0; // @[decode.scala:474:7]
wire [4:0] io_deq_uop_ftq_idx_0; // @[decode.scala:474:7]
wire io_deq_uop_edge_inst_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_pc_lob_0; // @[decode.scala:474:7]
wire io_deq_uop_taken_0; // @[decode.scala:474:7]
wire [19:0] io_deq_uop_imm_packed_0; // @[decode.scala:474:7]
wire io_deq_uop_exception_0; // @[decode.scala:474:7]
wire [63:0] io_deq_uop_exc_cause_0; // @[decode.scala:474:7]
wire io_deq_uop_bypassable_0; // @[decode.scala:474:7]
wire [4:0] io_deq_uop_mem_cmd_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_mem_size_0; // @[decode.scala:474:7]
wire io_deq_uop_mem_signed_0; // @[decode.scala:474:7]
wire io_deq_uop_is_fence_0; // @[decode.scala:474:7]
wire io_deq_uop_is_fencei_0; // @[decode.scala:474:7]
wire io_deq_uop_is_amo_0; // @[decode.scala:474:7]
wire io_deq_uop_uses_ldq_0; // @[decode.scala:474:7]
wire io_deq_uop_uses_stq_0; // @[decode.scala:474:7]
wire io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7]
wire io_deq_uop_is_unique_0; // @[decode.scala:474:7]
wire io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_ldst_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs1_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs2_0; // @[decode.scala:474:7]
wire [5:0] io_deq_uop_lrs3_0; // @[decode.scala:474:7]
wire io_deq_uop_ldst_val_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_dst_rtype_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7]
wire io_deq_uop_frs3_en_0; // @[decode.scala:474:7]
wire io_deq_uop_fp_val_0; // @[decode.scala:474:7]
wire io_deq_uop_fp_single_0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7]
wire io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7]
wire io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7]
wire io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7]
wire [1:0] io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7]
wire [31:0] io_csr_decode_inst_0; // @[decode.scala:474:7]
wire [6:0] cs_uopc; // @[decode.scala:490:16]
assign io_deq_uop_uopc_0 = uop_uopc; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17]
assign io_csr_decode_inst_0 = uop_inst; // @[decode.scala:474:7, :479:17]
wire [31:0] cs_decoder_decoded_plaInput = uop_inst; // @[pla.scala:77:22]
assign io_deq_uop_debug_inst_0 = uop_debug_inst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_is_rvc_0 = uop_is_rvc; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_debug_pc_0 = uop_debug_pc; // @[decode.scala:474:7, :479:17]
wire [2:0] cs_iq_type; // @[decode.scala:490:16]
assign io_deq_uop_iq_type_0 = uop_iq_type; // @[decode.scala:474:7, :479:17]
wire [9:0] cs_fu_code; // @[decode.scala:490:16]
assign io_deq_uop_fu_code_0 = uop_fu_code; // @[decode.scala:474:7, :479:17]
wire cs_is_br; // @[decode.scala:490:16]
assign io_deq_uop_is_br_0 = uop_is_br; // @[decode.scala:474:7, :479:17]
wire _uop_is_jalr_T; // @[decode.scala:590:35]
assign io_deq_uop_is_jalr_0 = uop_is_jalr; // @[decode.scala:474:7, :479:17]
wire _uop_is_jal_T; // @[decode.scala:589:35]
assign io_deq_uop_is_jal_0 = uop_is_jal; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_is_sfb_0 = uop_is_sfb; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_ftq_idx_0 = uop_ftq_idx; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_edge_inst_0 = uop_edge_inst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_pc_lob_0 = uop_pc_lob; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_taken_0 = uop_taken; // @[decode.scala:474:7, :479:17]
wire [19:0] _uop_imm_packed_T_2; // @[decode.scala:584:24]
assign io_deq_uop_imm_packed_0 = uop_imm_packed; // @[decode.scala:474:7, :479:17]
wire xcpt_valid; // @[decode.scala:513:26]
assign io_deq_uop_exception_0 = uop_exception; // @[decode.scala:474:7, :479:17]
wire [63:0] xcpt_cause; // @[Mux.scala:50:70]
assign io_deq_uop_exc_cause_0 = uop_exc_cause; // @[decode.scala:474:7, :479:17]
wire cs_bypassable; // @[decode.scala:490:16]
assign io_deq_uop_bypassable_0 = uop_bypassable; // @[decode.scala:474:7, :479:17]
wire [4:0] cs_mem_cmd; // @[decode.scala:490:16]
assign io_deq_uop_mem_cmd_0 = uop_mem_cmd; // @[decode.scala:474:7, :479:17]
wire [1:0] _uop_mem_size_T_7; // @[decode.scala:566:24]
assign io_deq_uop_mem_size_0 = uop_mem_size; // @[decode.scala:474:7, :479:17]
wire _uop_mem_signed_T_1; // @[decode.scala:567:21]
assign io_deq_uop_mem_signed_0 = uop_mem_signed; // @[decode.scala:474:7, :479:17]
wire cs_is_fence; // @[decode.scala:490:16]
assign io_deq_uop_is_fence_0 = uop_is_fence; // @[decode.scala:474:7, :479:17]
wire cs_is_fencei; // @[decode.scala:490:16]
assign io_deq_uop_is_fencei_0 = uop_is_fencei; // @[decode.scala:474:7, :479:17]
wire cs_is_amo; // @[decode.scala:490:16]
assign io_deq_uop_is_amo_0 = uop_is_amo; // @[decode.scala:474:7, :479:17]
wire cs_uses_ldq; // @[decode.scala:490:16]
assign io_deq_uop_uses_ldq_0 = uop_uses_ldq; // @[decode.scala:474:7, :479:17]
wire cs_uses_stq; // @[decode.scala:490:16]
assign io_deq_uop_uses_stq_0 = uop_uses_stq; // @[decode.scala:474:7, :479:17]
wire cs_is_sys_pc2epc; // @[decode.scala:490:16]
assign io_deq_uop_is_sys_pc2epc_0 = uop_is_sys_pc2epc; // @[decode.scala:474:7, :479:17]
wire cs_inst_unique; // @[decode.scala:490:16]
assign io_deq_uop_is_unique_0 = uop_is_unique; // @[decode.scala:474:7, :479:17]
wire _uop_flush_on_commit_T_3; // @[decode.scala:575:45]
assign io_deq_uop_flush_on_commit_0 = uop_flush_on_commit; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_ldst_0 = uop_ldst; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs1_0 = uop_lrs1; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs2_0 = uop_lrs2; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_lrs3_0 = uop_lrs3; // @[decode.scala:474:7, :479:17]
wire _uop_ldst_val_T_5; // @[decode.scala:540:42]
assign io_deq_uop_ldst_val_0 = uop_ldst_val; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_dst_type; // @[decode.scala:490:16]
assign io_deq_uop_dst_rtype_0 = uop_dst_rtype; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_rs1_type; // @[decode.scala:490:16]
assign io_deq_uop_lrs1_rtype_0 = uop_lrs1_rtype; // @[decode.scala:474:7, :479:17]
wire [1:0] cs_rs2_type; // @[decode.scala:490:16]
assign io_deq_uop_lrs2_rtype_0 = uop_lrs2_rtype; // @[decode.scala:474:7, :479:17]
wire cs_frs3_en; // @[decode.scala:490:16]
assign io_deq_uop_frs3_en_0 = uop_frs3_en; // @[decode.scala:474:7, :479:17]
wire cs_fp_val; // @[decode.scala:490:16]
assign io_deq_uop_fp_val_0 = uop_fp_val; // @[decode.scala:474:7, :479:17]
wire cs_fp_single; // @[decode.scala:490:16]
assign io_deq_uop_fp_single_0 = uop_fp_single; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_xcpt_pf_if_0 = uop_xcpt_pf_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_xcpt_ae_if_0 = uop_xcpt_ae_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_bp_debug_if_0 = uop_bp_debug_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_bp_xcpt_if_0 = uop_bp_xcpt_if; // @[decode.scala:474:7, :479:17]
assign io_deq_uop_debug_fsrc_0 = uop_debug_fsrc; // @[decode.scala:474:7, :479:17]
wire cs_decoder_0; // @[Decode.scala:50:77]
wire cs_decoder_1; // @[Decode.scala:50:77]
assign uop_fp_val = cs_fp_val; // @[decode.scala:479:17, :490:16]
wire cs_decoder_2; // @[Decode.scala:50:77]
assign uop_fp_single = cs_fp_single; // @[decode.scala:479:17, :490:16]
wire [6:0] cs_decoder_3; // @[Decode.scala:50:77]
assign uop_uopc = cs_uopc; // @[decode.scala:479:17, :490:16]
wire [2:0] cs_decoder_4; // @[Decode.scala:50:77]
assign uop_iq_type = cs_iq_type; // @[decode.scala:479:17, :490:16]
wire [9:0] cs_decoder_5; // @[Decode.scala:50:77]
assign uop_fu_code = cs_fu_code; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_6; // @[Decode.scala:50:77]
assign uop_dst_rtype = cs_dst_type; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_7; // @[Decode.scala:50:77]
assign uop_lrs1_rtype = cs_rs1_type; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_8; // @[Decode.scala:50:77]
assign uop_lrs2_rtype = cs_rs2_type; // @[decode.scala:479:17, :490:16]
wire cs_decoder_9; // @[Decode.scala:50:77]
assign uop_frs3_en = cs_frs3_en; // @[decode.scala:479:17, :490:16]
wire [2:0] cs_decoder_10; // @[Decode.scala:50:77]
wire cs_decoder_11; // @[Decode.scala:50:77]
assign uop_uses_ldq = cs_uses_ldq; // @[decode.scala:479:17, :490:16]
wire cs_decoder_12; // @[Decode.scala:50:77]
assign uop_uses_stq = cs_uses_stq; // @[decode.scala:479:17, :490:16]
wire cs_decoder_13; // @[Decode.scala:50:77]
assign uop_is_amo = cs_is_amo; // @[decode.scala:479:17, :490:16]
wire cs_decoder_14; // @[Decode.scala:50:77]
assign uop_is_fence = cs_is_fence; // @[decode.scala:479:17, :490:16]
wire cs_decoder_15; // @[Decode.scala:50:77]
assign uop_is_fencei = cs_is_fencei; // @[decode.scala:479:17, :490:16]
wire [4:0] cs_decoder_16; // @[Decode.scala:50:77]
assign uop_mem_cmd = cs_mem_cmd; // @[decode.scala:479:17, :490:16]
wire [1:0] cs_decoder_17; // @[Decode.scala:50:77]
wire cs_decoder_18; // @[Decode.scala:50:77]
assign uop_bypassable = cs_bypassable; // @[decode.scala:479:17, :490:16]
wire cs_decoder_19; // @[Decode.scala:50:77]
assign uop_is_br = cs_is_br; // @[decode.scala:479:17, :490:16]
wire cs_decoder_20; // @[Decode.scala:50:77]
assign uop_is_sys_pc2epc = cs_is_sys_pc2epc; // @[decode.scala:479:17, :490:16]
wire cs_decoder_21; // @[Decode.scala:50:77]
assign uop_is_unique = cs_inst_unique; // @[decode.scala:479:17, :490:16]
wire cs_decoder_22; // @[Decode.scala:50:77]
wire [2:0] cs_decoder_23; // @[Decode.scala:50:77]
wire cs_legal; // @[decode.scala:490:16]
wire [2:0] cs_imm_sel; // @[decode.scala:490:16]
wire [1:0] cs_wakeup_delay; // @[decode.scala:490:16]
wire cs_flush_on_commit; // @[decode.scala:490:16]
wire [2:0] cs_csr_cmd; // @[decode.scala:490:16]
wire [31:0] cs_decoder_decoded_invInputs = ~cs_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [52:0] cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [52:0] cs_decoder_decoded; // @[pla.scala:81:23]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = cs_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = cs_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = cs_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = cs_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = cs_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = cs_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = cs_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo = {cs_decoder_decoded_andMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi = {cs_decoder_decoded_andMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T = {cs_decoder_decoded_andMatrixOutputs_hi, cs_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_77_2 = &_cs_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = cs_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_1 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_1 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_1 = {cs_decoder_decoded_andMatrixOutputs_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_84_2 = &_cs_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = cs_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_2 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_2 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_2 = {cs_decoder_decoded_andMatrixOutputs_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_8_2 = &_cs_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = cs_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_3 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_3 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_3 = {cs_decoder_decoded_andMatrixOutputs_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_29_2 = &_cs_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_4 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_4 = {cs_decoder_decoded_andMatrixOutputs_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_124_2 = &_cs_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = cs_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = cs_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_5 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_5 = {cs_decoder_decoded_andMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_102_2 = &_cs_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_6 = {cs_decoder_decoded_andMatrixOutputs_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_85_2 = &_cs_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_26 = cs_decoder_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = cs_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_7 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_7 = {cs_decoder_decoded_andMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_56_2 = &_cs_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_8 = {cs_decoder_decoded_andMatrixOutputs_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_71_2 = &_cs_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_9 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_130_2 = &_cs_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_10 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_10 = {cs_decoder_decoded_andMatrixOutputs_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_34_2 = &_cs_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_11 = {cs_decoder_decoded_andMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_163_2 = &_cs_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_12 = {cs_decoder_decoded_andMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_48_2 = &_cs_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = cs_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_13 = {cs_decoder_decoded_andMatrixOutputs_hi_13, cs_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_110_2 = &_cs_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = cs_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = cs_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = cs_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = cs_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = cs_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1 = cs_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_14 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_14 = {cs_decoder_decoded_andMatrixOutputs_hi_14, cs_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_170_2 = &_cs_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = cs_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_15 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_15 = {cs_decoder_decoded_andMatrixOutputs_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_5_2 = &_cs_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_16 = {cs_decoder_decoded_andMatrixOutputs_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_75_2 = &_cs_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_17 = {cs_decoder_decoded_andMatrixOutputs_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_12_2 = &_cs_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_18 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_18 = {cs_decoder_decoded_andMatrixOutputs_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_35_2 = &_cs_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_19 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_19 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_19 = {cs_decoder_decoded_andMatrixOutputs_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_30_2 = &_cs_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_20 = {cs_decoder_decoded_andMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_24_2 = &_cs_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_21 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_21 = {cs_decoder_decoded_andMatrixOutputs_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_144_2 = &_cs_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_22 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_22 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_22 = {cs_decoder_decoded_andMatrixOutputs_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_28_2 = &_cs_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_23 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_23 = {cs_decoder_decoded_andMatrixOutputs_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_126_2 = &_cs_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = cs_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53]
wire [4:0] _cs_decoder_decoded_andMatrixOutputs_T_24 = {cs_decoder_decoded_andMatrixOutputs_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_162_2 = &_cs_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_38 = cs_decoder_decoded_andMatrixOutputs_162_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_25 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:91:29, :98:53]
wire [5:0] _cs_decoder_decoded_andMatrixOutputs_T_25 = {cs_decoder_decoded_andMatrixOutputs_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_1_2 = &_cs_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_26 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_26 = {cs_decoder_decoded_andMatrixOutputs_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_17_2 = &_cs_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_27 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_27 = {cs_decoder_decoded_andMatrixOutputs_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_98_2 = &_cs_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_28 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_28 = {cs_decoder_decoded_andMatrixOutputs_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_27_2 = &_cs_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_29 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_29 = {cs_decoder_decoded_andMatrixOutputs_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_105_2 = &_cs_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_30 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_30 = {cs_decoder_decoded_andMatrixOutputs_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_122_2 = &_cs_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_31 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_31 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_31 = {cs_decoder_decoded_andMatrixOutputs_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_38_2 = &_cs_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_32 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_32 = {cs_decoder_decoded_andMatrixOutputs_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_165_2 = &_cs_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_33 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_33 = {cs_decoder_decoded_andMatrixOutputs_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_19_2 = &_cs_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_34 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_34 = {cs_decoder_decoded_andMatrixOutputs_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_118_2 = &_cs_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_35 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_35 = {cs_decoder_decoded_andMatrixOutputs_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_153_2 = &_cs_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_36 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_36 = {cs_decoder_decoded_andMatrixOutputs_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_141_2 = &_cs_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_37 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_37 = {cs_decoder_decoded_andMatrixOutputs_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_168_2 = &_cs_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_38 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_38 = {cs_decoder_decoded_andMatrixOutputs_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_73_2 = &_cs_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_39 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_39 = {cs_decoder_decoded_andMatrixOutputs_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_25_2 = &_cs_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_40 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_40 = {cs_decoder_decoded_andMatrixOutputs_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_79_2 = &_cs_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_41 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_41 = {cs_decoder_decoded_andMatrixOutputs_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_114_2 = &_cs_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_42 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_42 = {cs_decoder_decoded_andMatrixOutputs_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_174_2 = &_cs_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_43 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_43 = {cs_decoder_decoded_andMatrixOutputs_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_139_2 = &_cs_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_37 = cs_decoder_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = cs_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = cs_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = cs_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = cs_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = cs_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = cs_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = cs_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = cs_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = cs_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = cs_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = cs_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = cs_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = cs_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = cs_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_44 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_44 = {cs_decoder_decoded_andMatrixOutputs_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_43_2 = &_cs_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_45 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_45 = {cs_decoder_decoded_andMatrixOutputs_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_67_2 = &_cs_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_8 = cs_decoder_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = cs_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_46 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_46 = {cs_decoder_decoded_andMatrixOutputs_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_18_2 = &_cs_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_25 = cs_decoder_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_47 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_47 = {cs_decoder_decoded_andMatrixOutputs_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_108_2 = &_cs_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_48 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_48 = {cs_decoder_decoded_andMatrixOutputs_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_46_2 = &_cs_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_49 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_49 = {cs_decoder_decoded_andMatrixOutputs_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_10_2 = &_cs_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_50 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_50 = {cs_decoder_decoded_andMatrixOutputs_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_82_2 = &_cs_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_51 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_51 = {cs_decoder_decoded_andMatrixOutputs_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_26_2 = &_cs_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_52 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_52 = {cs_decoder_decoded_andMatrixOutputs_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_42_2 = &_cs_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_53 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_53 = {cs_decoder_decoded_andMatrixOutputs_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_41_2 = &_cs_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_54 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_54 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_54 = {cs_decoder_decoded_andMatrixOutputs_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_93_2 = &_cs_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_55 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_55 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_55 = {cs_decoder_decoded_andMatrixOutputs_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_70_2 = &_cs_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_56 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_56 = {cs_decoder_decoded_andMatrixOutputs_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_11_2 = &_cs_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_57 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_57 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_76_2 = &_cs_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_58 = {cs_decoder_decoded_andMatrixOutputs_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_167_2 = &_cs_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T = cs_decoder_decoded_andMatrixOutputs_167_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_59 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_59 = {cs_decoder_decoded_andMatrixOutputs_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_152_2 = &_cs_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = cs_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_60 = {cs_decoder_decoded_andMatrixOutputs_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_96_2 = &_cs_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_61 = {cs_decoder_decoded_andMatrixOutputs_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_125_2 = &_cs_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_62 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_62 = {cs_decoder_decoded_andMatrixOutputs_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_40_2 = &_cs_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_63 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_63 = {cs_decoder_decoded_andMatrixOutputs_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_169_2 = &_cs_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_64 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_64 = {cs_decoder_decoded_andMatrixOutputs_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_69_2 = &_cs_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_65 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_65 = {cs_decoder_decoded_andMatrixOutputs_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_3_2 = &_cs_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_66 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_66 = {cs_decoder_decoded_andMatrixOutputs_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_16_2 = &_cs_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_67 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_67 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_67 = {cs_decoder_decoded_andMatrixOutputs_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_112_2 = &_cs_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_68 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_68 = {cs_decoder_decoded_andMatrixOutputs_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_160_2 = &_cs_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_69 = {cs_decoder_decoded_andMatrixOutputs_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_101_2 = &_cs_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [10:0] _cs_decoder_decoded_andMatrixOutputs_T_70 = {cs_decoder_decoded_andMatrixOutputs_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_15_2 = &_cs_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_23 = cs_decoder_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_71 = {cs_decoder_decoded_andMatrixOutputs_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_23_2 = &_cs_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_72 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_72 = {cs_decoder_decoded_andMatrixOutputs_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_173_2 = &_cs_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_73 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_73 = {cs_decoder_decoded_andMatrixOutputs_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_137_2 = &_cs_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_1 = cs_decoder_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_74 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_74 = {cs_decoder_decoded_andMatrixOutputs_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_20_2 = &_cs_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_75 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_75 = {cs_decoder_decoded_andMatrixOutputs_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_54_2 = &_cs_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_76 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_76 = {cs_decoder_decoded_andMatrixOutputs_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_97_2 = &_cs_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_77 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_77 = {cs_decoder_decoded_andMatrixOutputs_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_157_2 = &_cs_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = cs_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_78 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [9:0] _cs_decoder_decoded_andMatrixOutputs_T_78 = {cs_decoder_decoded_andMatrixOutputs_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_145_2 = &_cs_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_79 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_79 = {cs_decoder_decoded_andMatrixOutputs_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_134_2 = &_cs_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_80 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_80 = {cs_decoder_decoded_andMatrixOutputs_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_128_2 = &_cs_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_81 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] _cs_decoder_decoded_andMatrixOutputs_T_81 = {cs_decoder_decoded_andMatrixOutputs_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_142_2 = &_cs_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_82 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_82 = {cs_decoder_decoded_andMatrixOutputs_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_117_2 = &_cs_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_83 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_83 = {cs_decoder_decoded_andMatrixOutputs_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_53_2 = &_cs_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_84 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_84 = {cs_decoder_decoded_andMatrixOutputs_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_166_2 = &_cs_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_85 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_85 = {cs_decoder_decoded_andMatrixOutputs_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_21_2 = &_cs_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_86 = {cs_decoder_decoded_andMatrixOutputs_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_65_2 = &_cs_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_87 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_87 = {cs_decoder_decoded_andMatrixOutputs_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_52_2 = &_cs_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_88 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_88 = {cs_decoder_decoded_andMatrixOutputs_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_57_2 = &_cs_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_89 = {cs_decoder_decoded_andMatrixOutputs_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_74_2 = &_cs_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_90 = {cs_decoder_decoded_andMatrixOutputs_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_91_2 = &_cs_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_91 = {cs_decoder_decoded_andMatrixOutputs_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_104_2 = &_cs_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_92 = {cs_decoder_decoded_andMatrixOutputs_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_68_2 = &_cs_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_93 = {cs_decoder_decoded_andMatrixOutputs_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_94_2 = &_cs_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_94 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_94 = {cs_decoder_decoded_andMatrixOutputs_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_151_2 = &_cs_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_95 = {cs_decoder_decoded_andMatrixOutputs_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_2_2 = &_cs_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = cs_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_85 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_96 = {cs_decoder_decoded_andMatrixOutputs_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_156_2 = &_cs_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_86 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_97 = {cs_decoder_decoded_andMatrixOutputs_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_154_2 = &_cs_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_87 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_98 = {cs_decoder_decoded_andMatrixOutputs_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_148_2 = &_cs_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_88 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_99 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_99 = {cs_decoder_decoded_andMatrixOutputs_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_89_2 = &_cs_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_100 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [6:0] _cs_decoder_decoded_andMatrixOutputs_T_100 = {cs_decoder_decoded_andMatrixOutputs_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_55_2 = &_cs_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [8:0] _cs_decoder_decoded_andMatrixOutputs_T_101 = {cs_decoder_decoded_andMatrixOutputs_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_116_2 = &_cs_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_90 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_102 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_102 = {cs_decoder_decoded_andMatrixOutputs_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_131_2 = &_cs_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_91 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_103 = {cs_decoder_decoded_andMatrixOutputs_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_172_2 = &_cs_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_92 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_104 = {cs_decoder_decoded_andMatrixOutputs_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_72_2 = &_cs_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_93 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_105 = {cs_decoder_decoded_andMatrixOutputs_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_81_2 = &_cs_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_94 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_106 = {cs_decoder_decoded_andMatrixOutputs_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_6_2 = &_cs_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_59 = cs_decoder_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_107 = {cs_decoder_decoded_andMatrixOutputs_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_143_2 = &_cs_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_108 = {cs_decoder_decoded_andMatrixOutputs_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_66_2 = &_cs_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_97 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_109 = {cs_decoder_decoded_andMatrixOutputs_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_63_2 = &_cs_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_98 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_110 = {cs_decoder_decoded_andMatrixOutputs_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_161_2 = &_cs_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_99 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_111 = {cs_decoder_decoded_andMatrixOutputs_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_132_2 = &_cs_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_100 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_112 = {cs_decoder_decoded_andMatrixOutputs_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_133_2 = &_cs_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_101 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_113 = {cs_decoder_decoded_andMatrixOutputs_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_147_2 = &_cs_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = cs_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_102 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_114 = {cs_decoder_decoded_andMatrixOutputs_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_129_2 = &_cs_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_103 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_115 = {cs_decoder_decoded_andMatrixOutputs_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_100_2 = &_cs_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_104 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_116 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_116 = {cs_decoder_decoded_andMatrixOutputs_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_119_2 = &_cs_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_105 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_116 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_117 = {cs_decoder_decoded_andMatrixOutputs_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_150_2 = &_cs_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = cs_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = cs_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_118 = {cs_decoder_decoded_andMatrixOutputs_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_121_2 = &_cs_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_116 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_119 = {cs_decoder_decoded_andMatrixOutputs_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_158_2 = &_cs_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_117 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_120 = {cs_decoder_decoded_andMatrixOutputs_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_49_2 = &_cs_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_118 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_121 = {cs_decoder_decoded_andMatrixOutputs_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_50_2 = &_cs_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = cs_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_119 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_122 = {cs_decoder_decoded_andMatrixOutputs_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_45_2 = &_cs_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [14:0] cs_decoder_decoded_andMatrixOutputs_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_120 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [30:0] _cs_decoder_decoded_andMatrixOutputs_T_123 = {cs_decoder_decoded_andMatrixOutputs_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_135_2 = &_cs_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = cs_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = cs_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_121 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_124 = {cs_decoder_decoded_andMatrixOutputs_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_140_2 = &_cs_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_122 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_125 = {cs_decoder_decoded_andMatrixOutputs_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_95_2 = &_cs_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_114 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_125 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_125, cs_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_123 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_126 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_126 = {cs_decoder_decoded_andMatrixOutputs_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_115_2 = &_cs_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_115 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_126 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_126, cs_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_124 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_127 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_127 = {cs_decoder_decoded_andMatrixOutputs_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_60_2 = &_cs_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire _cs_decoder_decoded_orMatrixOutputs_T_24 = cs_decoder_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_116 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_127 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_127, cs_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_125 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_128 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_128 = {cs_decoder_decoded_andMatrixOutputs_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_7_2 = &_cs_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_117 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_128 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_128, cs_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_126 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_129 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_129 = {cs_decoder_decoded_andMatrixOutputs_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_14_2 = &_cs_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_118 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_129 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_129, cs_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_127 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_130 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [21:0] _cs_decoder_decoded_andMatrixOutputs_T_130 = {cs_decoder_decoded_andMatrixOutputs_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_92_2 = &_cs_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_119 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_130 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_130, cs_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_128 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_131 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [12:0] _cs_decoder_decoded_andMatrixOutputs_T_131 = {cs_decoder_decoded_andMatrixOutputs_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_78_2 = &_cs_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_120 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_131 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_131, cs_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_129 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_132 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_132 = {cs_decoder_decoded_andMatrixOutputs_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_47_2 = &_cs_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = cs_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_121 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_132 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_132, cs_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_130 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_133 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_133 = {cs_decoder_decoded_andMatrixOutputs_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_4_2 = &_cs_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_122 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_133 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_133, cs_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_131 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_134 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_134 = {cs_decoder_decoded_andMatrixOutputs_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_123_2 = &_cs_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_123 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_134 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_134, cs_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_132 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_135 = {cs_decoder_decoded_andMatrixOutputs_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_107_2 = &_cs_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_124 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_135 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_135, cs_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_133 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_136 = {cs_decoder_decoded_andMatrixOutputs_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_33_2 = &_cs_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_125 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_136 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_136, cs_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_134 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [13:0] _cs_decoder_decoded_andMatrixOutputs_T_137 = {cs_decoder_decoded_andMatrixOutputs_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_88_2 = &_cs_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_126 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_137 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_137, cs_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_135 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_138 = {cs_decoder_decoded_andMatrixOutputs_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_87_2 = &_cs_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_127 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_138 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_138, cs_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_136 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_139 = {cs_decoder_decoded_andMatrixOutputs_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_37_2 = &_cs_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_128 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_139 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_139, cs_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_137 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_140 = {cs_decoder_decoded_andMatrixOutputs_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_22_2 = &_cs_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_129 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_140 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_140, cs_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_138 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_141 = {cs_decoder_decoded_andMatrixOutputs_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_58_2 = &_cs_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_130 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_141 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_141, cs_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_139 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_142 = {cs_decoder_decoded_andMatrixOutputs_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_62_2 = &_cs_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_131 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_142 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_142, cs_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_140 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_143 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_143, cs_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_143 = {cs_decoder_decoded_andMatrixOutputs_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_9_2 = &_cs_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_132 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_143 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_143, cs_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_141 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_144 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_144, cs_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_144 = {cs_decoder_decoded_andMatrixOutputs_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_64_2 = &_cs_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_133 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_144 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_144, cs_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_142 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_145 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_145, cs_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_145 = {cs_decoder_decoded_andMatrixOutputs_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_146_2 = &_cs_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = cs_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_134 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_145 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_145, cs_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_143 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_146 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_146, cs_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_146 = {cs_decoder_decoded_andMatrixOutputs_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_113_2 = &_cs_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_135 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_146 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_146, cs_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_144 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_147 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_147, cs_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [16:0] _cs_decoder_decoded_andMatrixOutputs_T_147 = {cs_decoder_decoded_andMatrixOutputs_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_80_2 = &_cs_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_136 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_147 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_147, cs_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_145 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_148 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_148, cs_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_148 = {cs_decoder_decoded_andMatrixOutputs_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_44_2 = &_cs_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_137 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_148 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_148, cs_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_146 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_149 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_149, cs_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_149 = {cs_decoder_decoded_andMatrixOutputs_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_159_2 = &_cs_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_138 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_149 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_149, cs_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_147 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_150 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_150, cs_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_150 = {cs_decoder_decoded_andMatrixOutputs_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_0_2 = &_cs_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_139 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_150 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_150, cs_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_148 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_151 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_151, cs_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_151 = {cs_decoder_decoded_andMatrixOutputs_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_99_2 = &_cs_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_140 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_151 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_151, cs_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_149 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_152 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_152, cs_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_152 = {cs_decoder_decoded_andMatrixOutputs_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_13_2 = &_cs_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_141 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_152 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_152, cs_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_150 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_hi_153 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_153, cs_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53]
wire [17:0] _cs_decoder_decoded_andMatrixOutputs_T_153 = {cs_decoder_decoded_andMatrixOutputs_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_120_2 = &_cs_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_142 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_153 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_153, cs_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_151 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_154 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_154, cs_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_154 = {cs_decoder_decoded_andMatrixOutputs_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_171_2 = &_cs_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_143 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_154 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53]
wire [8:0] cs_decoder_decoded_andMatrixOutputs_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_154, cs_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_152 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_155 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_155, cs_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53]
wire [18:0] _cs_decoder_decoded_andMatrixOutputs_T_155 = {cs_decoder_decoded_andMatrixOutputs_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_109_2 = &_cs_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = cs_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_144 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_155 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_155, cs_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_153 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53]
wire [13:0] cs_decoder_decoded_andMatrixOutputs_hi_156 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_156, cs_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53]
wire [27:0] _cs_decoder_decoded_andMatrixOutputs_T_156 = {cs_decoder_decoded_andMatrixOutputs_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_59_2 = &_cs_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_31_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_145 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_156 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_156, cs_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_154 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53]
wire [15:0] cs_decoder_decoded_andMatrixOutputs_hi_157 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_157, cs_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53]
wire [31:0] _cs_decoder_decoded_andMatrixOutputs_T_157 = {cs_decoder_decoded_andMatrixOutputs_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_106_2 = &_cs_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = cs_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_146 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_157 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_157, cs_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_155 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:90:45, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_158 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_158, cs_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53]
wire [11:0] _cs_decoder_decoded_andMatrixOutputs_T_158 = {cs_decoder_decoded_andMatrixOutputs_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_155_2 = &_cs_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_147 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_158 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_158, cs_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_156 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_159 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_159, cs_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_159 = {cs_decoder_decoded_andMatrixOutputs_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_149_2 = &_cs_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_148 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_159 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_159, cs_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_157 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_160 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_160, cs_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_160 = {cs_decoder_decoded_andMatrixOutputs_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_136_2 = &_cs_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_149 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_160 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_160, cs_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_158 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_161 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_161, cs_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_161 = {cs_decoder_decoded_andMatrixOutputs_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_31_2 = &_cs_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_150 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_161 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53]
wire [6:0] cs_decoder_decoded_andMatrixOutputs_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_161, cs_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_159 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_162 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_162, cs_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53]
wire [14:0] _cs_decoder_decoded_andMatrixOutputs_T_162 = {cs_decoder_decoded_andMatrixOutputs_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_90_2 = &_cs_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_151 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_162 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_162, cs_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_160 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_163 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_163, cs_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_163 = {cs_decoder_decoded_andMatrixOutputs_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_39_2 = &_cs_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_152 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_163 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_163, cs_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_161 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_164 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_164, cs_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_164 = {cs_decoder_decoded_andMatrixOutputs_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_83_2 = &_cs_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_153 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_164 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_164, cs_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_162 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_165 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_165, cs_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_165 = {cs_decoder_decoded_andMatrixOutputs_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_103_2 = &_cs_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_154 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_165 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_lo_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_165, cs_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_163 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53]
wire [3:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53]
wire [7:0] cs_decoder_decoded_andMatrixOutputs_hi_166 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_166, cs_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53]
wire [15:0] _cs_decoder_decoded_andMatrixOutputs_T_166 = {cs_decoder_decoded_andMatrixOutputs_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_138_2 = &_cs_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_155 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_166 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_166, cs_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_164 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_167 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_167, cs_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_167 = {cs_decoder_decoded_andMatrixOutputs_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_86_2 = &_cs_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_156 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_167 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_167, cs_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_165 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_168 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_168, cs_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_168 = {cs_decoder_decoded_andMatrixOutputs_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_111_2 = &_cs_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_157 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_168 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_168, cs_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_166 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_hi_169 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_169, cs_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53]
wire [19:0] _cs_decoder_decoded_andMatrixOutputs_T_169 = {cs_decoder_decoded_andMatrixOutputs_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_32_2 = &_cs_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_158 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_169 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_169, cs_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_167 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_170 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_170, cs_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_170 = {cs_decoder_decoded_andMatrixOutputs_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_127_2 = &_cs_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_159 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_170 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_170, cs_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_168 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_171 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_171, cs_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_171 = {cs_decoder_decoded_andMatrixOutputs_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_164_2 = &_cs_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_160 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_171 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_171, cs_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_169 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_172 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_172, cs_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_172 = {cs_decoder_decoded_andMatrixOutputs_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_61_2 = &_cs_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_161 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_172 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_172, cs_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_170 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_173 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_173, cs_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_173 = {cs_decoder_decoded_andMatrixOutputs_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_36_2 = &_cs_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_lo_162 = {cs_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, cs_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_lo_hi_173 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, cs_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53]
wire [9:0] cs_decoder_decoded_andMatrixOutputs_lo_174 = {cs_decoder_decoded_andMatrixOutputs_lo_hi_173, cs_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] cs_decoder_decoded_andMatrixOutputs_hi_lo_171 = {cs_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, cs_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:91:29, :98:53]
wire [1:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {cs_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53]
wire [2:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, cs_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:91:29, :98:53]
wire [5:0] cs_decoder_decoded_andMatrixOutputs_hi_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, cs_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53]
wire [10:0] cs_decoder_decoded_andMatrixOutputs_hi_174 = {cs_decoder_decoded_andMatrixOutputs_hi_hi_174, cs_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53]
wire [20:0] _cs_decoder_decoded_andMatrixOutputs_T_174 = {cs_decoder_decoded_andMatrixOutputs_hi_174, cs_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53]
wire cs_decoder_decoded_andMatrixOutputs_51_2 = &_cs_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}]
wire [1:0] _GEN = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_13; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_13 = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo = {cs_decoder_decoded_orMatrixOutputs_lo_hi, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_0 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi = _GEN_0; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_14; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_14 = _GEN_0; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi = {cs_decoder_decoded_orMatrixOutputs_hi_hi, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_2 = {cs_decoder_decoded_orMatrixOutputs_hi, cs_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_3 = |_cs_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_1 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi = _GEN_1; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = _GEN_1; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_2 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi = _GEN_2; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_2; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_4 = {cs_decoder_decoded_orMatrixOutputs_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_5 = |_cs_decoder_decoded_orMatrixOutputs_T_4; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_167_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_6 = {cs_decoder_decoded_orMatrixOutputs_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_7 = |_cs_decoder_decoded_orMatrixOutputs_T_6; // @[pla.scala:114:{19,36}]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_9 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_10 = |_cs_decoder_decoded_orMatrixOutputs_T_9; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_3 = {cs_decoder_decoded_andMatrixOutputs_166_2, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = _GEN_3; // @[pla.scala:114:19]
wire [1:0] _GEN_4 = {cs_decoder_decoded_andMatrixOutputs_82_2, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo = _GEN_4; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_5 = {cs_decoder_decoded_andMatrixOutputs_56_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = _GEN_5; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = _GEN_5; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_11 = {cs_decoder_decoded_orMatrixOutputs_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_12 = |_cs_decoder_decoded_orMatrixOutputs_T_11; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_6 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi = _GEN_6; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = _GEN_6; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_12_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_7 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = _GEN_7; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = _GEN_7; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_3 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_andMatrixOutputs_124_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_8 = {cs_decoder_decoded_andMatrixOutputs_77_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [14:0] _cs_decoder_decoded_orMatrixOutputs_T_13 = {cs_decoder_decoded_orMatrixOutputs_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_14 = |_cs_decoder_decoded_orMatrixOutputs_T_13; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_9 = {cs_decoder_decoded_andMatrixOutputs_84_2, cs_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_5 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_18; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_18 = _GEN_9; // @[pla.scala:114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_15 = {cs_decoder_decoded_orMatrixOutputs_hi_5, cs_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_16 = |_cs_decoder_decoded_orMatrixOutputs_T_15; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_5 = {cs_decoder_decoded_andMatrixOutputs_47_2, cs_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_6 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_17 = {cs_decoder_decoded_orMatrixOutputs_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_18 = |_cs_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_7 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_47_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_19 = {cs_decoder_decoded_orMatrixOutputs_hi_7, cs_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_20 = |_cs_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_6 = {cs_decoder_decoded_andMatrixOutputs_60_2, cs_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_8 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_21 = {cs_decoder_decoded_orMatrixOutputs_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_22 = |_cs_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_10 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_27 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_7 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_12; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_12 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_16; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_16 = _GEN_10; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_28 = |_cs_decoder_decoded_orMatrixOutputs_T_27; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_29 = {cs_decoder_decoded_orMatrixOutputs_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_30 = |_cs_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_8 = {cs_decoder_decoded_andMatrixOutputs_40_2, cs_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _cs_decoder_decoded_orMatrixOutputs_T_31 = {cs_decoder_decoded_orMatrixOutputs_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_32 = |_cs_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_11 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_33 = {cs_decoder_decoded_orMatrixOutputs_hi_11, cs_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_34 = |_cs_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_12 = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_35 = {cs_decoder_decoded_orMatrixOutputs_hi_12, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_36 = |_cs_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_11 = {cs_decoder_decoded_andMatrixOutputs_4_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_5 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = _GEN_11; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_12 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_6; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_6 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = _GEN_12; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_39 = {cs_decoder_decoded_orMatrixOutputs_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_40 = |_cs_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_31_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_13 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = _GEN_13; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_14 = {cs_decoder_decoded_andMatrixOutputs_137_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = _GEN_14; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = _GEN_14; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_21_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] _GEN_15 = {cs_decoder_decoded_andMatrixOutputs_167_2, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = _GEN_15; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = _GEN_15; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_andMatrixOutputs_34_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_16 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = _GEN_16; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_16; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [24:0] _cs_decoder_decoded_orMatrixOutputs_T_41 = {cs_decoder_decoded_orMatrixOutputs_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_42 = |_cs_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_17 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = _GEN_17; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_43 = {cs_decoder_decoded_orMatrixOutputs_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_44 = |_cs_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_6 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_6 = {cs_decoder_decoded_andMatrixOutputs_43_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_102_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_45 = {cs_decoder_decoded_orMatrixOutputs_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_46 = |_cs_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_18 = {cs_decoder_decoded_andMatrixOutputs_138_2, cs_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_7 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_66 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_0_2, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_7 = {cs_decoder_decoded_andMatrixOutputs_88_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_19 = {cs_decoder_decoded_andMatrixOutputs_1_2, cs_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_19; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [9:0] _cs_decoder_decoded_orMatrixOutputs_T_47 = {cs_decoder_decoded_orMatrixOutputs_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_48 = |_cs_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_20 = {cs_decoder_decoded_andMatrixOutputs_86_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_20; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_123_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_6_2, cs_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_andMatrixOutputs_16_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_21 = {cs_decoder_decoded_andMatrixOutputs_108_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = _GEN_21; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] _GEN_22 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = _GEN_22; // @[pla.scala:114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {cs_decoder_decoded_andMatrixOutputs_5_2, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_49 = {cs_decoder_decoded_orMatrixOutputs_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_50 = |_cs_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_144_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_12_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [12:0] _cs_decoder_decoded_orMatrixOutputs_T_51 = {cs_decoder_decoded_orMatrixOutputs_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_52 = |_cs_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_20 = {cs_decoder_decoded_andMatrixOutputs_163_2, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _cs_decoder_decoded_orMatrixOutputs_T_53 = {cs_decoder_decoded_orMatrixOutputs_hi_20, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_54 = |_cs_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_10 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_10 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19]
wire [8:0] _cs_decoder_decoded_orMatrixOutputs_T_55 = {cs_decoder_decoded_orMatrixOutputs_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_56 = |_cs_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_57 = {cs_decoder_decoded_andMatrixOutputs_148_2, cs_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_58 = |_cs_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_14, cs_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _cs_decoder_decoded_orMatrixOutputs_T_60 = {cs_decoder_decoded_orMatrixOutputs_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_61 = |_cs_decoder_decoded_orMatrixOutputs_T_60; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_14 = {cs_decoder_decoded_andMatrixOutputs_37_2, cs_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_14, cs_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_15 = {cs_decoder_decoded_andMatrixOutputs_162_2, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19]
wire [6:0] _cs_decoder_decoded_orMatrixOutputs_T_62 = {cs_decoder_decoded_orMatrixOutputs_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_63 = |_cs_decoder_decoded_orMatrixOutputs_T_62; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_23 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:19]
assign _cs_decoder_decoded_orMatrixOutputs_T_64 = _GEN_23; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = _GEN_23; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_65 = |_cs_decoder_decoded_orMatrixOutputs_T_64; // @[pla.scala:114:{19,36}]
wire _cs_decoder_decoded_orMatrixOutputs_T_67 = |_cs_decoder_decoded_orMatrixOutputs_T_66; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_24 = {cs_decoder_decoded_andMatrixOutputs_83_2, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_19; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_19 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_13; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_13 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_16 = {cs_decoder_decoded_andMatrixOutputs_101_2, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_16, cs_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _cs_decoder_decoded_orMatrixOutputs_T_68 = {cs_decoder_decoded_orMatrixOutputs_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_69 = |_cs_decoder_decoded_orMatrixOutputs_T_68; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = {cs_decoder_decoded_andMatrixOutputs_92_2, cs_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_123_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] _GEN_25 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_25; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {cs_decoder_decoded_andMatrixOutputs_125_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19]
wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_70 = {cs_decoder_decoded_orMatrixOutputs_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_71 = |_cs_decoder_decoded_orMatrixOutputs_T_70; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_12 = {cs_decoder_decoded_andMatrixOutputs_50_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_13 = {cs_decoder_decoded_andMatrixOutputs_29_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19]
wire [7:0] _cs_decoder_decoded_orMatrixOutputs_T_72 = {cs_decoder_decoded_orMatrixOutputs_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_73 = |_cs_decoder_decoded_orMatrixOutputs_T_72; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, cs_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_74 = {cs_decoder_decoded_orMatrixOutputs_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_75 = |_cs_decoder_decoded_orMatrixOutputs_T_74; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_61_2, cs_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_80_2, cs_decoder_decoded_andMatrixOutputs_99_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_62_2, cs_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_64_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] _GEN_26 = {cs_decoder_decoded_andMatrixOutputs_140_2, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_121_2, cs_decoder_decoded_andMatrixOutputs_158_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_150_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_151_2, cs_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_18 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [17:0] cs_decoder_decoded_orMatrixOutputs_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_18, cs_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_91_2, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {cs_decoder_decoded_andMatrixOutputs_76_2, cs_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_165_2, cs_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_35_2, cs_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_8_2, cs_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [18:0] cs_decoder_decoded_orMatrixOutputs_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19]
wire [36:0] _cs_decoder_decoded_orMatrixOutputs_T_76 = {cs_decoder_decoded_orMatrixOutputs_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_77 = |_cs_decoder_decoded_orMatrixOutputs_T_76; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_45_2, cs_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_72_2, cs_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_52_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_104_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_20_2, cs_decoder_decoded_andMatrixOutputs_97_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_160_2, cs_decoder_decoded_andMatrixOutputs_15_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {cs_decoder_decoded_andMatrixOutputs_41_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_10_2, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_16 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = {cs_decoder_decoded_andMatrixOutputs_174_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {cs_decoder_decoded_andMatrixOutputs_105_2, cs_decoder_decoded_andMatrixOutputs_73_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_110_2, cs_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_27 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = _GEN_27; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19]
wire [33:0] _cs_decoder_decoded_orMatrixOutputs_T_78 = {cs_decoder_decoded_orMatrixOutputs_hi_29, cs_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_79 = |_cs_decoder_decoded_orMatrixOutputs_T_78; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_171_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_78_2, cs_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {cs_decoder_decoded_andMatrixOutputs_132_2, cs_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_16 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_116_2, cs_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_94_2, cs_decoder_decoded_andMatrixOutputs_148_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_53_2, cs_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_lo_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_128_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_117_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = {cs_decoder_decoded_andMatrixOutputs_42_2, cs_decoder_decoded_andMatrixOutputs_152_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_17 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] _GEN_28 = {cs_decoder_decoded_andMatrixOutputs_27_2, cs_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_28; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, cs_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_30_2, cs_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_130_2, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19]
wire [27:0] _cs_decoder_decoded_orMatrixOutputs_T_80 = {cs_decoder_decoded_orMatrixOutputs_hi_30, cs_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_81 = |_cs_decoder_decoded_orMatrixOutputs_T_80; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_59_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_99_2, cs_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_22_2, cs_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_7_2, cs_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_17 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_129_2, cs_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_66_2, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_131_2, cs_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19]
wire [15:0] cs_decoder_decoded_orMatrixOutputs_lo_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19]
wire [1:0] _GEN_29 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {cs_decoder_decoded_andMatrixOutputs_54_2, cs_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {cs_decoder_decoded_andMatrixOutputs_11_2, cs_decoder_decoded_andMatrixOutputs_112_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {cs_decoder_decoded_andMatrixOutputs_46_2, cs_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_18 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = {cs_decoder_decoded_andMatrixOutputs_79_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = {cs_decoder_decoded_andMatrixOutputs_85_2, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, cs_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19]
wire [16:0] cs_decoder_decoded_orMatrixOutputs_hi_31 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19]
wire [32:0] _cs_decoder_decoded_orMatrixOutputs_T_82 = {cs_decoder_decoded_orMatrixOutputs_hi_31, cs_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_83 = |_cs_decoder_decoded_orMatrixOutputs_T_82; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {cs_decoder_decoded_andMatrixOutputs_136_2, cs_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_146_2, cs_decoder_decoded_andMatrixOutputs_113_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_18 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {cs_decoder_decoded_andMatrixOutputs_154_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_57_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_22 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_22, cs_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {cs_decoder_decoded_andMatrixOutputs_142_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {cs_decoder_decoded_andMatrixOutputs_23_2, cs_decoder_decoded_andMatrixOutputs_54_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, cs_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_168_2, cs_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_11_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_24 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19]
wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_32 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_24, cs_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19]
wire [20:0] _cs_decoder_decoded_orMatrixOutputs_T_84 = {cs_decoder_decoded_orMatrixOutputs_hi_32, cs_decoder_decoded_orMatrixOutputs_lo_27}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_85 = |_cs_decoder_decoded_orMatrixOutputs_T_84; // @[pla.scala:114:{19,36}]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_19 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_55_2, cs_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {cs_decoder_decoded_andMatrixOutputs_2_2, cs_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_154_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_23 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_lo_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_23, cs_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {cs_decoder_decoded_andMatrixOutputs_157_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, cs_decoder_decoded_andMatrixOutputs_68_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {cs_decoder_decoded_andMatrixOutputs_139_2, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, cs_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = {cs_decoder_decoded_andMatrixOutputs_28_2, cs_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, cs_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, cs_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_25 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19]
wire [11:0] cs_decoder_decoded_orMatrixOutputs_hi_33 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_25, cs_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19]
wire [23:0] _cs_decoder_decoded_orMatrixOutputs_T_86 = {cs_decoder_decoded_orMatrixOutputs_hi_33, cs_decoder_decoded_orMatrixOutputs_lo_28}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_87 = |_cs_decoder_decoded_orMatrixOutputs_T_86; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {cs_decoder_decoded_andMatrixOutputs_31_2, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_20 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_24 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_lo_29 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_24, cs_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {cs_decoder_decoded_andMatrixOutputs_100_2, cs_decoder_decoded_andMatrixOutputs_45_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_21 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {cs_decoder_decoded_andMatrixOutputs_15_2, cs_decoder_decoded_andMatrixOutputs_147_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, cs_decoder_decoded_andMatrixOutputs_43_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_26 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19]
wire [8:0] cs_decoder_decoded_orMatrixOutputs_hi_34 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_26, cs_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:114:19]
wire [17:0] _cs_decoder_decoded_orMatrixOutputs_T_88 = {cs_decoder_decoded_orMatrixOutputs_hi_34, cs_decoder_decoded_orMatrixOutputs_lo_29}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_89 = |_cs_decoder_decoded_orMatrixOutputs_T_88; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_21 = {cs_decoder_decoded_andMatrixOutputs_111_2, cs_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {cs_decoder_decoded_andMatrixOutputs_159_2, cs_decoder_decoded_andMatrixOutputs_171_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_25 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, cs_decoder_decoded_andMatrixOutputs_39_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_30 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_25, cs_decoder_decoded_orMatrixOutputs_lo_lo_21}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {cs_decoder_decoded_andMatrixOutputs_107_2, cs_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_22 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, cs_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {cs_decoder_decoded_andMatrixOutputs_98_2, cs_decoder_decoded_andMatrixOutputs_118_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_27 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, cs_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_35 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_27, cs_decoder_decoded_orMatrixOutputs_hi_lo_22}; // @[pla.scala:114:19]
wire [10:0] _cs_decoder_decoded_orMatrixOutputs_T_90 = {cs_decoder_decoded_orMatrixOutputs_hi_35, cs_decoder_decoded_orMatrixOutputs_lo_30}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_91 = |_cs_decoder_decoded_orMatrixOutputs_T_90; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {cs_decoder_decoded_andMatrixOutputs_90_2, cs_decoder_decoded_andMatrixOutputs_86_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_22 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, cs_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_26 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, cs_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_31 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_26, cs_decoder_decoded_orMatrixOutputs_lo_lo_22}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_23 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_28 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_21, cs_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_36 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_28, cs_decoder_decoded_orMatrixOutputs_hi_lo_23}; // @[pla.scala:114:19]
wire [11:0] _cs_decoder_decoded_orMatrixOutputs_T_92 = {cs_decoder_decoded_orMatrixOutputs_hi_36, cs_decoder_decoded_orMatrixOutputs_lo_31}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_93 = |_cs_decoder_decoded_orMatrixOutputs_T_92; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_120_2, cs_decoder_decoded_andMatrixOutputs_106_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_90_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_23 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = {cs_decoder_decoded_andMatrixOutputs_95_2, cs_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {cs_decoder_decoded_andMatrixOutputs_65_2, cs_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, cs_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_27 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_20, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19]
wire [19:0] cs_decoder_decoded_orMatrixOutputs_lo_32 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_27, cs_decoder_decoded_orMatrixOutputs_lo_lo_23}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {cs_decoder_decoded_andMatrixOutputs_70_2, cs_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, cs_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_114_2, cs_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [9:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_24 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_19, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = {cs_decoder_decoded_andMatrixOutputs_170_2, cs_decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, cs_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, cs_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, cs_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [10:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_29 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_22, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19]
wire [20:0] cs_decoder_decoded_orMatrixOutputs_hi_37 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_29, cs_decoder_decoded_orMatrixOutputs_hi_lo_24}; // @[pla.scala:114:19]
wire [40:0] _cs_decoder_decoded_orMatrixOutputs_T_94 = {cs_decoder_decoded_orMatrixOutputs_hi_37, cs_decoder_decoded_orMatrixOutputs_lo_32}; // @[pla.scala:114:19]
wire _cs_decoder_decoded_orMatrixOutputs_T_95 = |_cs_decoder_decoded_orMatrixOutputs_T_94; // @[pla.scala:114:{19,36}]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_3, _cs_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_8, _cs_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_14, _cs_decoder_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_18, _cs_decoder_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_22, _cs_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_lo_24 = {cs_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, cs_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_25, _cs_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_23}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_30, _cs_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_36, _cs_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_38, _cs_decoder_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {_cs_decoder_decoded_orMatrixOutputs_T_42, _cs_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_lo_hi_28 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_hi_21, cs_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:102:36]
wire [25:0] cs_decoder_decoded_orMatrixOutputs_lo_33 = {cs_decoder_decoded_orMatrixOutputs_lo_hi_28, cs_decoder_decoded_orMatrixOutputs_lo_lo_24}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_48, _cs_decoder_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_54, _cs_decoder_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36]
wire [5:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_8, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_59, _cs_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_63, _cs_decoder_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_67, _cs_decoder_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [12:0] cs_decoder_decoded_orMatrixOutputs_hi_lo_25 = {cs_decoder_decoded_orMatrixOutputs_hi_lo_hi_20, cs_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_orMatrixOutputs_T_73, _cs_decoder_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_orMatrixOutputs_T_69}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_77, _cs_decoder_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = {_cs_decoder_decoded_orMatrixOutputs_T_81, _cs_decoder_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:102:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = {_cs_decoder_decoded_orMatrixOutputs_T_87, _cs_decoder_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36]
wire [2:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, _cs_decoder_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_orMatrixOutputs_T_91, _cs_decoder_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36]
wire [1:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {_cs_decoder_decoded_orMatrixOutputs_T_95, _cs_decoder_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36]
wire [3:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [6:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36]
wire [13:0] cs_decoder_decoded_orMatrixOutputs_hi_hi_30 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_hi_23, cs_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:102:36]
wire [26:0] cs_decoder_decoded_orMatrixOutputs_hi_38 = {cs_decoder_decoded_orMatrixOutputs_hi_hi_30, cs_decoder_decoded_orMatrixOutputs_hi_lo_25}; // @[pla.scala:102:36]
wire [52:0] cs_decoder_decoded_orMatrixOutputs = {cs_decoder_decoded_orMatrixOutputs_hi_38, cs_decoder_decoded_orMatrixOutputs_lo_33}; // @[pla.scala:102:36]
wire _cs_decoder_decoded_invMatrixOutputs_T = cs_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_1 = cs_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_2 = cs_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_3 = cs_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_4 = cs_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_5 = cs_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_6 = cs_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_7 = cs_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_8 = cs_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_9 = cs_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_10 = cs_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_11 = cs_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_12 = cs_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_13 = cs_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_14 = cs_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_15 = cs_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_16 = cs_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_17 = cs_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_18 = cs_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_19 = cs_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_20 = cs_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_21 = cs_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_22 = cs_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_23 = cs_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_24 = cs_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_25 = cs_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_26 = cs_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_27 = cs_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_28 = cs_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_29 = cs_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :123:56]
wire _cs_decoder_decoded_invMatrixOutputs_T_30 = ~_cs_decoder_decoded_invMatrixOutputs_T_29; // @[pla.scala:123:{40,56}]
wire _cs_decoder_decoded_invMatrixOutputs_T_31 = cs_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_32 = cs_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_33 = cs_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_34 = cs_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_35 = cs_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_36 = cs_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_37 = cs_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_38 = cs_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_39 = cs_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_40 = cs_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_41 = cs_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :123:56]
wire _cs_decoder_decoded_invMatrixOutputs_T_42 = ~_cs_decoder_decoded_invMatrixOutputs_T_41; // @[pla.scala:123:{40,56}]
wire _cs_decoder_decoded_invMatrixOutputs_T_43 = cs_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_44 = cs_decoder_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_45 = cs_decoder_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_46 = cs_decoder_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_47 = cs_decoder_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_48 = cs_decoder_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_49 = cs_decoder_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_50 = cs_decoder_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_51 = cs_decoder_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_52 = cs_decoder_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_53 = cs_decoder_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31]
wire _cs_decoder_decoded_invMatrixOutputs_T_54 = cs_decoder_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_2, _cs_decoder_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_5, _cs_decoder_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_8, _cs_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_10, _cs_decoder_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_12, _cs_decoder_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_15, _cs_decoder_decoded_invMatrixOutputs_T_14}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_18, _cs_decoder_decoded_invMatrixOutputs_T_17}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_21, _cs_decoder_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_23, _cs_decoder_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_25, _cs_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_lo_hi = {cs_decoder_decoded_invMatrixOutputs_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [25:0] cs_decoder_decoded_invMatrixOutputs_lo = {cs_decoder_decoded_invMatrixOutputs_lo_hi, cs_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_28, _cs_decoder_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_32, _cs_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _cs_decoder_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :123:40]
wire [5:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_35, _cs_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_37, _cs_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_39, _cs_decoder_decoded_invMatrixOutputs_T_38}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [12:0] cs_decoder_decoded_invMatrixOutputs_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_43, _cs_decoder_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :123:40, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_45, _cs_decoder_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_47, _cs_decoder_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_cs_decoder_decoded_invMatrixOutputs_T_50, _cs_decoder_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31]
wire [2:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _cs_decoder_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {_cs_decoder_decoded_invMatrixOutputs_T_52, _cs_decoder_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31]
wire [1:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_cs_decoder_decoded_invMatrixOutputs_T_54, _cs_decoder_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31]
wire [3:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [6:0] cs_decoder_decoded_invMatrixOutputs_hi_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [13:0] cs_decoder_decoded_invMatrixOutputs_hi_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [26:0] cs_decoder_decoded_invMatrixOutputs_hi = {cs_decoder_decoded_invMatrixOutputs_hi_hi, cs_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign cs_decoder_decoded_invMatrixOutputs = {cs_decoder_decoded_invMatrixOutputs_hi, cs_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign cs_decoder_decoded = cs_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign cs_decoder_0 = cs_decoder_decoded[52]; // @[pla.scala:81:23]
assign cs_legal = cs_decoder_0; // @[Decode.scala:50:77]
assign cs_decoder_1 = cs_decoder_decoded[51]; // @[pla.scala:81:23]
assign cs_fp_val = cs_decoder_1; // @[Decode.scala:50:77]
assign cs_decoder_2 = cs_decoder_decoded[50]; // @[pla.scala:81:23]
assign cs_fp_single = cs_decoder_2; // @[Decode.scala:50:77]
assign cs_decoder_3 = cs_decoder_decoded[49:43]; // @[pla.scala:81:23]
assign cs_uopc = cs_decoder_3; // @[Decode.scala:50:77]
assign cs_decoder_4 = cs_decoder_decoded[42:40]; // @[pla.scala:81:23]
assign cs_iq_type = cs_decoder_4; // @[Decode.scala:50:77]
assign cs_decoder_5 = cs_decoder_decoded[39:30]; // @[pla.scala:81:23]
assign cs_fu_code = cs_decoder_5; // @[Decode.scala:50:77]
assign cs_decoder_6 = cs_decoder_decoded[29:28]; // @[pla.scala:81:23]
assign cs_dst_type = cs_decoder_6; // @[Decode.scala:50:77]
assign cs_decoder_7 = cs_decoder_decoded[27:26]; // @[pla.scala:81:23]
assign cs_rs1_type = cs_decoder_7; // @[Decode.scala:50:77]
assign cs_decoder_8 = cs_decoder_decoded[25:24]; // @[pla.scala:81:23]
assign cs_rs2_type = cs_decoder_8; // @[Decode.scala:50:77]
assign cs_decoder_9 = cs_decoder_decoded[23]; // @[pla.scala:81:23]
assign cs_frs3_en = cs_decoder_9; // @[Decode.scala:50:77]
assign cs_decoder_10 = cs_decoder_decoded[22:20]; // @[pla.scala:81:23]
assign cs_imm_sel = cs_decoder_10; // @[Decode.scala:50:77]
assign cs_decoder_11 = cs_decoder_decoded[19]; // @[pla.scala:81:23]
assign cs_uses_ldq = cs_decoder_11; // @[Decode.scala:50:77]
assign cs_decoder_12 = cs_decoder_decoded[18]; // @[pla.scala:81:23]
assign cs_uses_stq = cs_decoder_12; // @[Decode.scala:50:77]
assign cs_decoder_13 = cs_decoder_decoded[17]; // @[pla.scala:81:23]
assign cs_is_amo = cs_decoder_13; // @[Decode.scala:50:77]
assign cs_decoder_14 = cs_decoder_decoded[16]; // @[pla.scala:81:23]
assign cs_is_fence = cs_decoder_14; // @[Decode.scala:50:77]
assign cs_decoder_15 = cs_decoder_decoded[15]; // @[pla.scala:81:23]
assign cs_is_fencei = cs_decoder_15; // @[Decode.scala:50:77]
assign cs_decoder_16 = cs_decoder_decoded[14:10]; // @[pla.scala:81:23]
assign cs_mem_cmd = cs_decoder_16; // @[Decode.scala:50:77]
assign cs_decoder_17 = cs_decoder_decoded[9:8]; // @[pla.scala:81:23]
assign cs_wakeup_delay = cs_decoder_17; // @[Decode.scala:50:77]
assign cs_decoder_18 = cs_decoder_decoded[7]; // @[pla.scala:81:23]
assign cs_bypassable = cs_decoder_18; // @[Decode.scala:50:77]
assign cs_decoder_19 = cs_decoder_decoded[6]; // @[pla.scala:81:23]
assign cs_is_br = cs_decoder_19; // @[Decode.scala:50:77]
assign cs_decoder_20 = cs_decoder_decoded[5]; // @[pla.scala:81:23]
assign cs_is_sys_pc2epc = cs_decoder_20; // @[Decode.scala:50:77]
assign cs_decoder_21 = cs_decoder_decoded[4]; // @[pla.scala:81:23]
assign cs_inst_unique = cs_decoder_21; // @[Decode.scala:50:77]
assign cs_decoder_22 = cs_decoder_decoded[3]; // @[pla.scala:81:23]
assign cs_flush_on_commit = cs_decoder_22; // @[Decode.scala:50:77]
assign cs_decoder_23 = cs_decoder_decoded[2:0]; // @[pla.scala:81:23]
assign cs_csr_cmd = cs_decoder_23; // @[Decode.scala:50:77]
wire _GEN_30 = cs_csr_cmd == 3'h6; // @[package.scala:16:47]
wire _csr_en_T; // @[package.scala:16:47]
assign _csr_en_T = _GEN_30; // @[package.scala:16:47]
wire _csr_ren_T; // @[package.scala:16:47]
assign _csr_ren_T = _GEN_30; // @[package.scala:16:47]
wire _csr_en_T_1 = &cs_csr_cmd; // @[package.scala:16:47]
wire _csr_en_T_2 = cs_csr_cmd == 3'h5; // @[package.scala:16:47]
wire _csr_en_T_3 = _csr_en_T | _csr_en_T_1; // @[package.scala:16:47, :81:59]
wire csr_en = _csr_en_T_3 | _csr_en_T_2; // @[package.scala:16:47, :81:59]
wire _csr_ren_T_1 = &cs_csr_cmd; // @[package.scala:16:47]
wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[package.scala:16:47, :81:59]
wire _csr_ren_T_3 = ~(|uop_lrs1); // @[decode.scala:479:17, :495:62]
wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[package.scala:81:59]
wire system_insn = cs_csr_cmd == 3'h4; // @[decode.scala:490:16, :496:32]
wire sfence = cs_uopc == 7'h6B; // @[decode.scala:490:16, :497:24]
wire _id_illegal_insn_T = ~cs_legal; // @[decode.scala:490:16, :502:25]
wire _id_illegal_insn_T_1 = cs_fp_val & io_csr_decode_fp_illegal_0; // @[decode.scala:474:7, :490:16, :503:15]
wire _id_illegal_insn_T_2 = _id_illegal_insn_T | _id_illegal_insn_T_1; // @[decode.scala:502:{25,35}, :503:15]
wire _id_illegal_insn_T_4 = _id_illegal_insn_T_2; // @[decode.scala:502:35, :503:43]
wire _id_illegal_insn_T_8 = _id_illegal_insn_T_4; // @[decode.scala:503:43, :504:43]
wire _id_illegal_insn_T_14 = _id_illegal_insn_T_8; // @[decode.scala:504:43, :505:43]
wire _id_illegal_insn_T_9 = ~cs_fp_single; // @[decode.scala:490:16, :506:19]
wire _id_illegal_insn_T_10 = cs_fp_val & _id_illegal_insn_T_9; // @[decode.scala:490:16, :506:{16,19}]
wire _id_illegal_insn_T_15 = ~csr_ren; // @[decode.scala:495:50, :507:46]
wire _id_illegal_insn_T_16 = _id_illegal_insn_T_15 & io_csr_decode_write_illegal_0; // @[decode.scala:474:7, :507:{46,55}]
wire _id_illegal_insn_T_17 = io_csr_decode_read_illegal_0 | _id_illegal_insn_T_16; // @[decode.scala:474:7, :507:{43,55}]
wire _id_illegal_insn_T_18 = csr_en & _id_illegal_insn_T_17; // @[package.scala:81:59]
wire _id_illegal_insn_T_19 = _id_illegal_insn_T_14 | _id_illegal_insn_T_18; // @[decode.scala:505:43, :506:61, :507:12]
wire _id_illegal_insn_T_20 = sfence | system_insn; // @[decode.scala:496:32, :497:24, :508:14]
wire _id_illegal_insn_T_21 = _id_illegal_insn_T_20 & io_csr_decode_system_illegal_0; // @[decode.scala:474:7, :508:{14,30}]
wire id_illegal_insn = _id_illegal_insn_T_19 | _id_illegal_insn_T_21; // @[decode.scala:506:61, :507:87, :508:30]
wire _T_1 = io_interrupt_0 & ~io_enq_uop_is_sfb_0; // @[decode.scala:474:7, :516:{19,22}]
assign xcpt_valid = _T_1 | uop_bp_debug_if | uop_bp_xcpt_if | uop_xcpt_pf_if | uop_xcpt_ae_if | id_illegal_insn; // @[decode.scala:479:17, :507:87, :513:26, :516:19]
assign uop_exception = xcpt_valid; // @[decode.scala:479:17, :513:26]
assign xcpt_cause = _T_1 ? io_interrupt_cause_0 : {60'h0, uop_bp_debug_if ? 4'hE : uop_bp_xcpt_if ? 4'h3 : uop_xcpt_pf_if ? 4'hC : {2'h0, uop_xcpt_ae_if ? 2'h1 : 2'h2}}; // @[Mux.scala:50:70]
assign uop_exc_cause = xcpt_cause; // @[Mux.scala:50:70]
wire [4:0] _uop_ldst_T = uop_inst[11:7]; // @[decode.scala:479:17, :535:25]
wire [4:0] _uop_lrs2_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :550:28]
wire [4:0] _uop_lrs1_T_1 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :554:28]
wire [4:0] _di24_20_T_3 = uop_inst[11:7]; // @[decode.scala:479:17, :535:25, :583:69]
assign uop_ldst = {1'h0, _uop_ldst_T}; // @[decode.scala:479:17, :535:{18,25}]
wire [4:0] _uop_lrs1_T = uop_inst[19:15]; // @[decode.scala:479:17, :536:25]
assign uop_lrs1 = {1'h0, _uop_lrs1_T}; // @[decode.scala:479:17, :536:{18,25}]
wire [4:0] _uop_lrs2_T = uop_inst[24:20]; // @[decode.scala:479:17, :537:25]
wire [4:0] _di24_20_T_4 = uop_inst[24:20]; // @[decode.scala:479:17, :537:25, :583:81]
assign uop_lrs2 = {1'h0, _uop_lrs2_T}; // @[decode.scala:479:17, :537:{18,25}]
wire [4:0] _uop_lrs3_T = uop_inst[31:27]; // @[decode.scala:479:17, :538:25]
assign uop_lrs3 = {1'h0, _uop_lrs3_T}; // @[decode.scala:479:17, :538:{18,25}]
wire _uop_ldst_val_T = cs_dst_type != 2'h2; // @[decode.scala:490:16, :540:33]
wire _uop_ldst_val_T_1 = uop_ldst == 6'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:56]
wire _uop_ldst_val_T_2 = uop_dst_rtype == 2'h0; // @[decode.scala:474:7, :477:14, :479:17, :540:81]
wire _uop_ldst_val_T_3 = _uop_ldst_val_T_1 & _uop_ldst_val_T_2; // @[decode.scala:540:{56,64,81}]
wire _uop_ldst_val_T_4 = ~_uop_ldst_val_T_3; // @[decode.scala:540:{45,64}]
assign _uop_ldst_val_T_5 = _uop_ldst_val_T & _uop_ldst_val_T_4; // @[decode.scala:540:{33,42,45}]
assign uop_ldst_val = _uop_ldst_val_T_5; // @[decode.scala:479:17, :540:42]
wire _uop_ldst_is_rs1_T = ~uop_is_br; // @[decode.scala:479:17]
wire _uop_ldst_is_rs1_T_1 = _uop_ldst_is_rs1_T & uop_is_sfb; // @[decode.scala:479:17]
wire _uop_mem_size_T = cs_mem_cmd == 5'h14; // @[package.scala:16:47]
wire _uop_mem_size_T_1 = cs_mem_cmd == 5'h5; // @[package.scala:16:47]
wire _uop_mem_size_T_2 = _uop_mem_size_T | _uop_mem_size_T_1; // @[package.scala:16:47, :81:59]
wire _uop_mem_size_T_3 = |uop_lrs2; // @[decode.scala:479:17, :566:81]
wire _uop_mem_size_T_4 = |uop_lrs1; // @[decode.scala:479:17, :495:62, :566:99]
wire [1:0] _uop_mem_size_T_5 = {_uop_mem_size_T_3, _uop_mem_size_T_4}; // @[decode.scala:566:{71,81,99}]
wire [1:0] _uop_mem_size_T_6 = uop_inst[13:12]; // @[decode.scala:479:17, :566:113]
assign _uop_mem_size_T_7 = _uop_mem_size_T_2 ? _uop_mem_size_T_5 : _uop_mem_size_T_6; // @[package.scala:81:59]
assign uop_mem_size = _uop_mem_size_T_7; // @[decode.scala:479:17, :566:24]
wire _uop_mem_signed_T = uop_inst[14]; // @[decode.scala:479:17, :567:26]
assign _uop_mem_signed_T_1 = ~_uop_mem_signed_T; // @[decode.scala:567:{21,26}]
assign uop_mem_signed = _uop_mem_signed_T_1; // @[decode.scala:479:17, :567:21]
wire _uop_flush_on_commit_T = ~csr_ren; // @[decode.scala:495:50, :507:46, :575:59]
wire _uop_flush_on_commit_T_1 = csr_en & _uop_flush_on_commit_T; // @[package.scala:81:59]
wire _uop_flush_on_commit_T_2 = _uop_flush_on_commit_T_1 & io_csr_decode_write_flush_0; // @[decode.scala:474:7, :575:{56,68}]
assign _uop_flush_on_commit_T_3 = cs_flush_on_commit | _uop_flush_on_commit_T_2; // @[decode.scala:490:16, :575:{45,68}]
assign uop_flush_on_commit = _uop_flush_on_commit_T_3; // @[decode.scala:479:17, :575:45]
wire _di24_20_T = cs_imm_sel == 3'h2; // @[decode.scala:490:16, :583:32]
wire _di24_20_T_1 = cs_imm_sel == 3'h1; // @[decode.scala:490:16, :583:55]
wire _di24_20_T_2 = _di24_20_T | _di24_20_T_1; // @[decode.scala:583:{32,41,55}]
wire [4:0] di24_20 = _di24_20_T_2 ? _di24_20_T_3 : _di24_20_T_4; // @[decode.scala:583:{20,41,69,81}]
wire [6:0] _uop_imm_packed_T = uop_inst[31:25]; // @[decode.scala:479:17, :584:29]
wire [7:0] _uop_imm_packed_T_1 = uop_inst[19:12]; // @[decode.scala:479:17, :584:51]
wire [11:0] uop_imm_packed_hi = {_uop_imm_packed_T, di24_20}; // @[decode.scala:583:20, :584:{24,29}]
assign _uop_imm_packed_T_2 = {uop_imm_packed_hi, _uop_imm_packed_T_1}; // @[decode.scala:584:{24,51}]
assign uop_imm_packed = _uop_imm_packed_T_2; // @[decode.scala:479:17, :584:24]
assign _uop_is_jal_T = uop_uopc == 7'h25; // @[decode.scala:479:17, :589:35]
assign uop_is_jal = _uop_is_jal_T; // @[decode.scala:479:17, :589:35]
assign _uop_is_jalr_T = uop_uopc == 7'h26; // @[decode.scala:479:17, :590:35]
assign uop_is_jalr = _uop_is_jalr_T; // @[decode.scala:479:17, :590:35]
assign io_deq_uop_uopc = io_deq_uop_uopc_0; // @[decode.scala:474:7]
assign io_deq_uop_inst = io_deq_uop_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_inst = io_deq_uop_debug_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_is_rvc = io_deq_uop_is_rvc_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_pc = io_deq_uop_debug_pc_0; // @[decode.scala:474:7]
assign io_deq_uop_iq_type = io_deq_uop_iq_type_0; // @[decode.scala:474:7]
assign io_deq_uop_fu_code = io_deq_uop_fu_code_0; // @[decode.scala:474:7]
assign io_deq_uop_is_br = io_deq_uop_is_br_0; // @[decode.scala:474:7]
assign io_deq_uop_is_jalr = io_deq_uop_is_jalr_0; // @[decode.scala:474:7]
assign io_deq_uop_is_jal = io_deq_uop_is_jal_0; // @[decode.scala:474:7]
assign io_deq_uop_is_sfb = io_deq_uop_is_sfb_0; // @[decode.scala:474:7]
assign io_deq_uop_ftq_idx = io_deq_uop_ftq_idx_0; // @[decode.scala:474:7]
assign io_deq_uop_edge_inst = io_deq_uop_edge_inst_0; // @[decode.scala:474:7]
assign io_deq_uop_pc_lob = io_deq_uop_pc_lob_0; // @[decode.scala:474:7]
assign io_deq_uop_taken = io_deq_uop_taken_0; // @[decode.scala:474:7]
assign io_deq_uop_imm_packed = io_deq_uop_imm_packed_0; // @[decode.scala:474:7]
assign io_deq_uop_exception = io_deq_uop_exception_0; // @[decode.scala:474:7]
assign io_deq_uop_exc_cause = io_deq_uop_exc_cause_0; // @[decode.scala:474:7]
assign io_deq_uop_bypassable = io_deq_uop_bypassable_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_cmd = io_deq_uop_mem_cmd_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_size = io_deq_uop_mem_size_0; // @[decode.scala:474:7]
assign io_deq_uop_mem_signed = io_deq_uop_mem_signed_0; // @[decode.scala:474:7]
assign io_deq_uop_is_fence = io_deq_uop_is_fence_0; // @[decode.scala:474:7]
assign io_deq_uop_is_fencei = io_deq_uop_is_fencei_0; // @[decode.scala:474:7]
assign io_deq_uop_is_amo = io_deq_uop_is_amo_0; // @[decode.scala:474:7]
assign io_deq_uop_uses_ldq = io_deq_uop_uses_ldq_0; // @[decode.scala:474:7]
assign io_deq_uop_uses_stq = io_deq_uop_uses_stq_0; // @[decode.scala:474:7]
assign io_deq_uop_is_sys_pc2epc = io_deq_uop_is_sys_pc2epc_0; // @[decode.scala:474:7]
assign io_deq_uop_is_unique = io_deq_uop_is_unique_0; // @[decode.scala:474:7]
assign io_deq_uop_flush_on_commit = io_deq_uop_flush_on_commit_0; // @[decode.scala:474:7]
assign io_deq_uop_ldst = io_deq_uop_ldst_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs1 = io_deq_uop_lrs1_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs2 = io_deq_uop_lrs2_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs3 = io_deq_uop_lrs3_0; // @[decode.scala:474:7]
assign io_deq_uop_ldst_val = io_deq_uop_ldst_val_0; // @[decode.scala:474:7]
assign io_deq_uop_dst_rtype = io_deq_uop_dst_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs1_rtype = io_deq_uop_lrs1_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_lrs2_rtype = io_deq_uop_lrs2_rtype_0; // @[decode.scala:474:7]
assign io_deq_uop_frs3_en = io_deq_uop_frs3_en_0; // @[decode.scala:474:7]
assign io_deq_uop_fp_val = io_deq_uop_fp_val_0; // @[decode.scala:474:7]
assign io_deq_uop_fp_single = io_deq_uop_fp_single_0; // @[decode.scala:474:7]
assign io_deq_uop_xcpt_pf_if = io_deq_uop_xcpt_pf_if_0; // @[decode.scala:474:7]
assign io_deq_uop_xcpt_ae_if = io_deq_uop_xcpt_ae_if_0; // @[decode.scala:474:7]
assign io_deq_uop_bp_debug_if = io_deq_uop_bp_debug_if_0; // @[decode.scala:474:7]
assign io_deq_uop_bp_xcpt_if = io_deq_uop_bp_xcpt_if_0; // @[decode.scala:474:7]
assign io_deq_uop_debug_fsrc = io_deq_uop_debug_fsrc_0; // @[decode.scala:474:7]
assign io_csr_decode_inst = io_csr_decode_inst_0; // @[decode.scala:474:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_8 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<6>, vc_free : UInt<6>}}
wire _in_flight_WIRE : UInt<1>[6]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
regreset in_flight : UInt<1>[6], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(_T_12, _T_19)
node _T_35 = or(_T_34, _T_26)
node _T_36 = or(_T_35, _T_33)
node _T_37 = or(_T_5, _T_36)
node _T_38 = asUInt(reset)
node _T_39 = eq(_T_38, UInt<1>(0h0))
when _T_39 :
node _T_40 = eq(_T_37, UInt<1>(0h0))
when _T_40 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_37, UInt<1>(0h1), "") : assert_1
node _T_41 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hc))
node _T_43 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_48 = and(_T_46, _T_47)
node _T_49 = or(_T_41, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_49, UInt<1>(0h1), "") : assert_2
node _T_53 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_63 = and(_T_61, _T_62)
node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_70 = and(_T_68, _T_69)
node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_76 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_77 = and(_T_75, _T_76)
node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_81 = and(_T_79, _T_80)
node _T_82 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_83 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_86 = and(_T_84, _T_85)
node _T_87 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_88 = and(_T_86, _T_87)
node _T_89 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_90 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_91 = and(_T_89, _T_90)
node _T_92 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_97 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_98 = and(_T_96, _T_97)
node _T_99 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_100 = and(_T_98, _T_99)
node _T_101 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_102 = and(_T_100, _T_101)
node _T_103 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_104 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_105 = and(_T_103, _T_104)
node _T_106 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_107 = and(_T_105, _T_106)
node _T_108 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_109 = and(_T_107, _T_108)
node _T_110 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_111 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_112 = and(_T_110, _T_111)
node _T_113 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_114 = and(_T_112, _T_113)
node _T_115 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_116 = and(_T_114, _T_115)
node _T_117 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_118 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_121 = and(_T_119, _T_120)
node _T_122 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_123 = and(_T_121, _T_122)
node _T_124 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_125 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_132 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_139 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_146 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_149 = and(_T_147, _T_148)
node _T_150 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_151 = and(_T_149, _T_150)
node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_153 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_156 = and(_T_154, _T_155)
node _T_157 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_160 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_165 = and(_T_163, _T_164)
node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_167 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_170 = and(_T_168, _T_169)
node _T_171 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_172 = and(_T_170, _T_171)
node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_174 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_181 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_188 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_191 = and(_T_189, _T_190)
node _T_192 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_195 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_198 = and(_T_196, _T_197)
node _T_199 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_202 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_205 = and(_T_203, _T_204)
node _T_206 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_209 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_212 = and(_T_210, _T_211)
node _T_213 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_216 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_219 = and(_T_217, _T_218)
node _T_220 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_223 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_230 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_233 = and(_T_231, _T_232)
node _T_234 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_237 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_242 = and(_T_240, _T_241)
node _T_243 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_244 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_249 = and(_T_247, _T_248)
node _T_250 = or(_T_60, _T_67)
node _T_251 = or(_T_250, _T_74)
node _T_252 = or(_T_251, _T_81)
node _T_253 = or(_T_252, _T_88)
node _T_254 = or(_T_253, _T_95)
node _T_255 = or(_T_254, _T_102)
node _T_256 = or(_T_255, _T_109)
node _T_257 = or(_T_256, _T_116)
node _T_258 = or(_T_257, _T_123)
node _T_259 = or(_T_258, _T_130)
node _T_260 = or(_T_259, _T_137)
node _T_261 = or(_T_260, _T_144)
node _T_262 = or(_T_261, _T_151)
node _T_263 = or(_T_262, _T_158)
node _T_264 = or(_T_263, _T_165)
node _T_265 = or(_T_264, _T_172)
node _T_266 = or(_T_265, _T_179)
node _T_267 = or(_T_266, _T_186)
node _T_268 = or(_T_267, _T_193)
node _T_269 = or(_T_268, _T_200)
node _T_270 = or(_T_269, _T_207)
node _T_271 = or(_T_270, _T_214)
node _T_272 = or(_T_271, _T_221)
node _T_273 = or(_T_272, _T_228)
node _T_274 = or(_T_273, _T_235)
node _T_275 = or(_T_274, _T_242)
node _T_276 = or(_T_275, _T_249)
node _T_277 = or(_T_53, _T_276)
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_277, UInt<1>(0h1), "") : assert_3
node _T_281 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_282 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_283 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_284 = and(_T_282, _T_283)
node _T_285 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_286 = and(_T_284, _T_285)
node _T_287 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_290 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_291 = and(_T_289, _T_290)
node _T_292 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_297 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_302 = and(_T_300, _T_301)
node _T_303 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_304 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_305 = and(_T_303, _T_304)
node _T_306 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_309 = and(_T_307, _T_308)
node _T_310 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_311 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_312 = and(_T_310, _T_311)
node _T_313 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_316 = and(_T_314, _T_315)
node _T_317 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_318 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_323 = and(_T_321, _T_322)
node _T_324 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_325 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_330 = and(_T_328, _T_329)
node _T_331 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_332 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_335 = and(_T_333, _T_334)
node _T_336 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_339 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_346 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_353 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_360 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_367 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_374 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_381 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_388 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_395 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_400 = and(_T_398, _T_399)
node _T_401 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_402 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_407 = and(_T_405, _T_406)
node _T_408 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_409 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_414 = and(_T_412, _T_413)
node _T_415 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_416 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_421 = and(_T_419, _T_420)
node _T_422 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_423 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_428 = and(_T_426, _T_427)
node _T_429 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_430 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_435 = and(_T_433, _T_434)
node _T_436 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_437 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_444 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_449 = and(_T_447, _T_448)
node _T_450 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_451 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_456 = and(_T_454, _T_455)
node _T_457 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_458 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_463 = and(_T_461, _T_462)
node _T_464 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_465 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_466 = and(_T_464, _T_465)
node _T_467 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_470 = and(_T_468, _T_469)
node _T_471 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_472 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_475 = and(_T_473, _T_474)
node _T_476 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_479 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_484 = and(_T_482, _T_483)
node _T_485 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_486 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_491 = and(_T_489, _T_490)
node _T_492 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_493 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_498 = and(_T_496, _T_497)
node _T_499 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_500 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_505 = and(_T_503, _T_504)
node _T_506 = or(_T_288, _T_295)
node _T_507 = or(_T_506, _T_302)
node _T_508 = or(_T_507, _T_309)
node _T_509 = or(_T_508, _T_316)
node _T_510 = or(_T_509, _T_323)
node _T_511 = or(_T_510, _T_330)
node _T_512 = or(_T_511, _T_337)
node _T_513 = or(_T_512, _T_344)
node _T_514 = or(_T_513, _T_351)
node _T_515 = or(_T_514, _T_358)
node _T_516 = or(_T_515, _T_365)
node _T_517 = or(_T_516, _T_372)
node _T_518 = or(_T_517, _T_379)
node _T_519 = or(_T_518, _T_386)
node _T_520 = or(_T_519, _T_393)
node _T_521 = or(_T_520, _T_400)
node _T_522 = or(_T_521, _T_407)
node _T_523 = or(_T_522, _T_414)
node _T_524 = or(_T_523, _T_421)
node _T_525 = or(_T_524, _T_428)
node _T_526 = or(_T_525, _T_435)
node _T_527 = or(_T_526, _T_442)
node _T_528 = or(_T_527, _T_449)
node _T_529 = or(_T_528, _T_456)
node _T_530 = or(_T_529, _T_463)
node _T_531 = or(_T_530, _T_470)
node _T_532 = or(_T_531, _T_477)
node _T_533 = or(_T_532, _T_484)
node _T_534 = or(_T_533, _T_491)
node _T_535 = or(_T_534, _T_498)
node _T_536 = or(_T_535, _T_505)
node _T_537 = or(_T_281, _T_536)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_537, UInt<1>(0h1), "") : assert_4
node _T_541 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_543 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _T_547 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_548 = and(_T_546, _T_547)
node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_550 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_553 = and(_T_551, _T_552)
node _T_554 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_557 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_558 = and(_T_556, _T_557)
node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_560 = and(_T_558, _T_559)
node _T_561 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_564 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_565 = and(_T_563, _T_564)
node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_571 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_572 = and(_T_570, _T_571)
node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_578 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
node _T_584 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_585 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_586 = and(_T_584, _T_585)
node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_588 = and(_T_586, _T_587)
node _T_589 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_592 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_593 = and(_T_591, _T_592)
node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_595 = and(_T_593, _T_594)
node _T_596 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_597 = and(_T_595, _T_596)
node _T_598 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_599 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_600 = and(_T_598, _T_599)
node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_602 = and(_T_600, _T_601)
node _T_603 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_604 = and(_T_602, _T_603)
node _T_605 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_606 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_609 = and(_T_607, _T_608)
node _T_610 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_613 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_616 = and(_T_614, _T_615)
node _T_617 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_618 = and(_T_616, _T_617)
node _T_619 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_620 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_623 = and(_T_621, _T_622)
node _T_624 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_625 = and(_T_623, _T_624)
node _T_626 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_627 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_628 = and(_T_626, _T_627)
node _T_629 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_630 = and(_T_628, _T_629)
node _T_631 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_632 = and(_T_630, _T_631)
node _T_633 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_634 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_635 = and(_T_633, _T_634)
node _T_636 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_639 = and(_T_637, _T_638)
node _T_640 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_641 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_642 = and(_T_640, _T_641)
node _T_643 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_644 = and(_T_642, _T_643)
node _T_645 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_648 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_649 = and(_T_647, _T_648)
node _T_650 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_651 = and(_T_649, _T_650)
node _T_652 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_653 = and(_T_651, _T_652)
node _T_654 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_655 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_656 = and(_T_654, _T_655)
node _T_657 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_662 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_663 = and(_T_661, _T_662)
node _T_664 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_667 = and(_T_665, _T_666)
node _T_668 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_669 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_670 = and(_T_668, _T_669)
node _T_671 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_672 = and(_T_670, _T_671)
node _T_673 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_674 = and(_T_672, _T_673)
node _T_675 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_676 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_679 = and(_T_677, _T_678)
node _T_680 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_681 = and(_T_679, _T_680)
node _T_682 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_683 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_684 = and(_T_682, _T_683)
node _T_685 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_688 = and(_T_686, _T_687)
node _T_689 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_690 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_691 = and(_T_689, _T_690)
node _T_692 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_693 = and(_T_691, _T_692)
node _T_694 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_695 = and(_T_693, _T_694)
node _T_696 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_697 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_698 = and(_T_696, _T_697)
node _T_699 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_700 = and(_T_698, _T_699)
node _T_701 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_702 = and(_T_700, _T_701)
node _T_703 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_704 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_707 = and(_T_705, _T_706)
node _T_708 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_709 = and(_T_707, _T_708)
node _T_710 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_711 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_716 = and(_T_714, _T_715)
node _T_717 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_718 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_719 = and(_T_717, _T_718)
node _T_720 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_721 = and(_T_719, _T_720)
node _T_722 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
node _T_724 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_725 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_726 = and(_T_724, _T_725)
node _T_727 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_728 = and(_T_726, _T_727)
node _T_729 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_730 = and(_T_728, _T_729)
node _T_731 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_732 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_733 = and(_T_731, _T_732)
node _T_734 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_735 = and(_T_733, _T_734)
node _T_736 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_737 = and(_T_735, _T_736)
node _T_738 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_739 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_740 = and(_T_738, _T_739)
node _T_741 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_744 = and(_T_742, _T_743)
node _T_745 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_746 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_749 = and(_T_747, _T_748)
node _T_750 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_751 = and(_T_749, _T_750)
node _T_752 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_753 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_754 = and(_T_752, _T_753)
node _T_755 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_760 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_761 = and(_T_759, _T_760)
node _T_762 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_765 = and(_T_763, _T_764)
node _T_766 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_767 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_768 = and(_T_766, _T_767)
node _T_769 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_774 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_779 = and(_T_777, _T_778)
node _T_780 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_781 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_782 = and(_T_780, _T_781)
node _T_783 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_784 = and(_T_782, _T_783)
node _T_785 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_786 = and(_T_784, _T_785)
node _T_787 = or(_T_548, _T_555)
node _T_788 = or(_T_787, _T_562)
node _T_789 = or(_T_788, _T_569)
node _T_790 = or(_T_789, _T_576)
node _T_791 = or(_T_790, _T_583)
node _T_792 = or(_T_791, _T_590)
node _T_793 = or(_T_792, _T_597)
node _T_794 = or(_T_793, _T_604)
node _T_795 = or(_T_794, _T_611)
node _T_796 = or(_T_795, _T_618)
node _T_797 = or(_T_796, _T_625)
node _T_798 = or(_T_797, _T_632)
node _T_799 = or(_T_798, _T_639)
node _T_800 = or(_T_799, _T_646)
node _T_801 = or(_T_800, _T_653)
node _T_802 = or(_T_801, _T_660)
node _T_803 = or(_T_802, _T_667)
node _T_804 = or(_T_803, _T_674)
node _T_805 = or(_T_804, _T_681)
node _T_806 = or(_T_805, _T_688)
node _T_807 = or(_T_806, _T_695)
node _T_808 = or(_T_807, _T_702)
node _T_809 = or(_T_808, _T_709)
node _T_810 = or(_T_809, _T_716)
node _T_811 = or(_T_810, _T_723)
node _T_812 = or(_T_811, _T_730)
node _T_813 = or(_T_812, _T_737)
node _T_814 = or(_T_813, _T_744)
node _T_815 = or(_T_814, _T_751)
node _T_816 = or(_T_815, _T_758)
node _T_817 = or(_T_816, _T_765)
node _T_818 = or(_T_817, _T_772)
node _T_819 = or(_T_818, _T_779)
node _T_820 = or(_T_819, _T_786)
node _T_821 = or(_T_541, _T_820)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_821, UInt<1>(0h1), "") : assert_5
node _T_825 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_826 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_827 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_828 = and(_T_826, _T_827)
node _T_829 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_834 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_835 = and(_T_833, _T_834)
node _T_836 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_841 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_842 = and(_T_840, _T_841)
node _T_843 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_844 = and(_T_842, _T_843)
node _T_845 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
node _T_847 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_848 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_853 = and(_T_851, _T_852)
node _T_854 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_855 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_856 = and(_T_854, _T_855)
node _T_857 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_860 = and(_T_858, _T_859)
node _T_861 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_862 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_863 = and(_T_861, _T_862)
node _T_864 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_865 = and(_T_863, _T_864)
node _T_866 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_867 = and(_T_865, _T_866)
node _T_868 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_869 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_870 = and(_T_868, _T_869)
node _T_871 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_876 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_877 = and(_T_875, _T_876)
node _T_878 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_883 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_884 = and(_T_882, _T_883)
node _T_885 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_886 = and(_T_884, _T_885)
node _T_887 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_888 = and(_T_886, _T_887)
node _T_889 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_890 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_891 = and(_T_889, _T_890)
node _T_892 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_893 = and(_T_891, _T_892)
node _T_894 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_895 = and(_T_893, _T_894)
node _T_896 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_897 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_898 = and(_T_896, _T_897)
node _T_899 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_900 = and(_T_898, _T_899)
node _T_901 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_902 = and(_T_900, _T_901)
node _T_903 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_904 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_905 = and(_T_903, _T_904)
node _T_906 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_907 = and(_T_905, _T_906)
node _T_908 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_909 = and(_T_907, _T_908)
node _T_910 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_911 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_912 = and(_T_910, _T_911)
node _T_913 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_918 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_919 = and(_T_917, _T_918)
node _T_920 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_921 = and(_T_919, _T_920)
node _T_922 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_923 = and(_T_921, _T_922)
node _T_924 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_925 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_926 = and(_T_924, _T_925)
node _T_927 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_928 = and(_T_926, _T_927)
node _T_929 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_930 = and(_T_928, _T_929)
node _T_931 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_932 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_933 = and(_T_931, _T_932)
node _T_934 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_935 = and(_T_933, _T_934)
node _T_936 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_937 = and(_T_935, _T_936)
node _T_938 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_939 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_940 = and(_T_938, _T_939)
node _T_941 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_944 = and(_T_942, _T_943)
node _T_945 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_946 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_947 = and(_T_945, _T_946)
node _T_948 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
node _T_950 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_953 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_954 = and(_T_952, _T_953)
node _T_955 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_958 = and(_T_956, _T_957)
node _T_959 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_960 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_963 = and(_T_961, _T_962)
node _T_964 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_965 = and(_T_963, _T_964)
node _T_966 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_967 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_968 = and(_T_966, _T_967)
node _T_969 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_970 = and(_T_968, _T_969)
node _T_971 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_972 = and(_T_970, _T_971)
node _T_973 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_974 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_975 = and(_T_973, _T_974)
node _T_976 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_977 = and(_T_975, _T_976)
node _T_978 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_979 = and(_T_977, _T_978)
node _T_980 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_981 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_982 = and(_T_980, _T_981)
node _T_983 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_984 = and(_T_982, _T_983)
node _T_985 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_986 = and(_T_984, _T_985)
node _T_987 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_988 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_989 = and(_T_987, _T_988)
node _T_990 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_991 = and(_T_989, _T_990)
node _T_992 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_993 = and(_T_991, _T_992)
node _T_994 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_995 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_996 = and(_T_994, _T_995)
node _T_997 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_998 = and(_T_996, _T_997)
node _T_999 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1000 = and(_T_998, _T_999)
node _T_1001 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1002 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_1003 = and(_T_1001, _T_1002)
node _T_1004 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1007 = and(_T_1005, _T_1006)
node _T_1008 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_1009 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1010 = and(_T_1008, _T_1009)
node _T_1011 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1012 = and(_T_1010, _T_1011)
node _T_1013 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1014 = and(_T_1012, _T_1013)
node _T_1015 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_1016 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_1017 = and(_T_1015, _T_1016)
node _T_1018 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_1023 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1024 = and(_T_1022, _T_1023)
node _T_1025 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1026 = and(_T_1024, _T_1025)
node _T_1027 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_1030 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1033 = and(_T_1031, _T_1032)
node _T_1034 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1035 = and(_T_1033, _T_1034)
node _T_1036 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1037 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_1038 = and(_T_1036, _T_1037)
node _T_1039 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_1044 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_1045 = and(_T_1043, _T_1044)
node _T_1046 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_1051 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1054 = and(_T_1052, _T_1053)
node _T_1055 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_1058 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_1059 = and(_T_1057, _T_1058)
node _T_1060 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1063 = and(_T_1061, _T_1062)
node _T_1064 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_1065 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1070 = and(_T_1068, _T_1069)
node _T_1071 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_1072 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_1073 = and(_T_1071, _T_1072)
node _T_1074 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1075 = and(_T_1073, _T_1074)
node _T_1076 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1077 = and(_T_1075, _T_1076)
node _T_1078 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_1079 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1086 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1089 = and(_T_1087, _T_1088)
node _T_1090 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1091 = and(_T_1089, _T_1090)
node _T_1092 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_1093 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1098 = and(_T_1096, _T_1097)
node _T_1099 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_1100 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_1101 = and(_T_1099, _T_1100)
node _T_1102 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1103 = and(_T_1101, _T_1102)
node _T_1104 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1105 = and(_T_1103, _T_1104)
node _T_1106 = or(_T_832, _T_839)
node _T_1107 = or(_T_1106, _T_846)
node _T_1108 = or(_T_1107, _T_853)
node _T_1109 = or(_T_1108, _T_860)
node _T_1110 = or(_T_1109, _T_867)
node _T_1111 = or(_T_1110, _T_874)
node _T_1112 = or(_T_1111, _T_881)
node _T_1113 = or(_T_1112, _T_888)
node _T_1114 = or(_T_1113, _T_895)
node _T_1115 = or(_T_1114, _T_902)
node _T_1116 = or(_T_1115, _T_909)
node _T_1117 = or(_T_1116, _T_916)
node _T_1118 = or(_T_1117, _T_923)
node _T_1119 = or(_T_1118, _T_930)
node _T_1120 = or(_T_1119, _T_937)
node _T_1121 = or(_T_1120, _T_944)
node _T_1122 = or(_T_1121, _T_951)
node _T_1123 = or(_T_1122, _T_958)
node _T_1124 = or(_T_1123, _T_965)
node _T_1125 = or(_T_1124, _T_972)
node _T_1126 = or(_T_1125, _T_979)
node _T_1127 = or(_T_1126, _T_986)
node _T_1128 = or(_T_1127, _T_993)
node _T_1129 = or(_T_1128, _T_1000)
node _T_1130 = or(_T_1129, _T_1007)
node _T_1131 = or(_T_1130, _T_1014)
node _T_1132 = or(_T_1131, _T_1021)
node _T_1133 = or(_T_1132, _T_1028)
node _T_1134 = or(_T_1133, _T_1035)
node _T_1135 = or(_T_1134, _T_1042)
node _T_1136 = or(_T_1135, _T_1049)
node _T_1137 = or(_T_1136, _T_1056)
node _T_1138 = or(_T_1137, _T_1063)
node _T_1139 = or(_T_1138, _T_1070)
node _T_1140 = or(_T_1139, _T_1077)
node _T_1141 = or(_T_1140, _T_1084)
node _T_1142 = or(_T_1141, _T_1091)
node _T_1143 = or(_T_1142, _T_1098)
node _T_1144 = or(_T_1143, _T_1105)
node _T_1145 = or(_T_825, _T_1144)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_6 | module NoCMonitor_8( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module ComposedBranchPredictorBank_1 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
node _s0_pc_T = not(io.f0_pc)
node _s0_pc_T_1 = or(_s0_pc_T, UInt<3>(0h7))
node s0_pc = not(_s0_pc_T_1)
reg s1_pc : UInt, clock
connect s1_pc, s0_pc
reg s2_pc : UInt, clock
connect s2_pc, s1_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
node _s1_update_bits_pc_T = not(io.update.bits.pc)
node _s1_update_bits_pc_T_1 = or(_s1_update_bits_pc_T, UInt<3>(0h7))
node _s1_update_bits_pc_T_2 = not(_s1_update_bits_pc_T_1)
connect s1_update.bits.pc, _s1_update_bits_pc_T_2
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
inst loop of LoopBranchPredictorBank_1
connect loop.clock, clock
connect loop.reset, reset
inst tage of TageBranchPredictorBank_1
connect tage.clock, clock
connect tage.reset, reset
inst btb of BTBBranchPredictorBank_1
connect btb.clock, clock
connect btb.reset, reset
inst bim of BIMBranchPredictorBank_1
connect bim.clock, clock
connect bim.reset, reset
inst ubtb of FA2MicroBTBBranchPredictorBank_1
connect ubtb.clock, clock
connect ubtb.reset, reset
invalidate loop.io.update.bits.meta
invalidate loop.io.update.bits.target
invalidate loop.io.update.bits.lhist
invalidate loop.io.update.bits.ghist
invalidate loop.io.update.bits.cfi_is_jalr
invalidate loop.io.update.bits.cfi_is_jal
invalidate loop.io.update.bits.cfi_is_br
invalidate loop.io.update.bits.cfi_mispredicted
invalidate loop.io.update.bits.cfi_taken
invalidate loop.io.update.bits.cfi_idx.bits
invalidate loop.io.update.bits.cfi_idx.valid
invalidate loop.io.update.bits.br_mask
invalidate loop.io.update.bits.pc
invalidate loop.io.update.bits.btb_mispredicts
invalidate loop.io.update.bits.is_repair_update
invalidate loop.io.update.bits.is_mispredict_update
invalidate loop.io.update.valid
invalidate loop.io.f3_fire
invalidate loop.io.f3_meta
invalidate loop.io.resp.f3[0].predicted_pc.bits
invalidate loop.io.resp.f3[0].predicted_pc.valid
invalidate loop.io.resp.f3[0].is_jal
invalidate loop.io.resp.f3[0].is_br
invalidate loop.io.resp.f3[0].taken
invalidate loop.io.resp.f3[1].predicted_pc.bits
invalidate loop.io.resp.f3[1].predicted_pc.valid
invalidate loop.io.resp.f3[1].is_jal
invalidate loop.io.resp.f3[1].is_br
invalidate loop.io.resp.f3[1].taken
invalidate loop.io.resp.f3[2].predicted_pc.bits
invalidate loop.io.resp.f3[2].predicted_pc.valid
invalidate loop.io.resp.f3[2].is_jal
invalidate loop.io.resp.f3[2].is_br
invalidate loop.io.resp.f3[2].taken
invalidate loop.io.resp.f3[3].predicted_pc.bits
invalidate loop.io.resp.f3[3].predicted_pc.valid
invalidate loop.io.resp.f3[3].is_jal
invalidate loop.io.resp.f3[3].is_br
invalidate loop.io.resp.f3[3].taken
invalidate loop.io.resp.f2[0].predicted_pc.bits
invalidate loop.io.resp.f2[0].predicted_pc.valid
invalidate loop.io.resp.f2[0].is_jal
invalidate loop.io.resp.f2[0].is_br
invalidate loop.io.resp.f2[0].taken
invalidate loop.io.resp.f2[1].predicted_pc.bits
invalidate loop.io.resp.f2[1].predicted_pc.valid
invalidate loop.io.resp.f2[1].is_jal
invalidate loop.io.resp.f2[1].is_br
invalidate loop.io.resp.f2[1].taken
invalidate loop.io.resp.f2[2].predicted_pc.bits
invalidate loop.io.resp.f2[2].predicted_pc.valid
invalidate loop.io.resp.f2[2].is_jal
invalidate loop.io.resp.f2[2].is_br
invalidate loop.io.resp.f2[2].taken
invalidate loop.io.resp.f2[3].predicted_pc.bits
invalidate loop.io.resp.f2[3].predicted_pc.valid
invalidate loop.io.resp.f2[3].is_jal
invalidate loop.io.resp.f2[3].is_br
invalidate loop.io.resp.f2[3].taken
invalidate loop.io.resp.f1[0].predicted_pc.bits
invalidate loop.io.resp.f1[0].predicted_pc.valid
invalidate loop.io.resp.f1[0].is_jal
invalidate loop.io.resp.f1[0].is_br
invalidate loop.io.resp.f1[0].taken
invalidate loop.io.resp.f1[1].predicted_pc.bits
invalidate loop.io.resp.f1[1].predicted_pc.valid
invalidate loop.io.resp.f1[1].is_jal
invalidate loop.io.resp.f1[1].is_br
invalidate loop.io.resp.f1[1].taken
invalidate loop.io.resp.f1[2].predicted_pc.bits
invalidate loop.io.resp.f1[2].predicted_pc.valid
invalidate loop.io.resp.f1[2].is_jal
invalidate loop.io.resp.f1[2].is_br
invalidate loop.io.resp.f1[2].taken
invalidate loop.io.resp.f1[3].predicted_pc.bits
invalidate loop.io.resp.f1[3].predicted_pc.valid
invalidate loop.io.resp.f1[3].is_jal
invalidate loop.io.resp.f1[3].is_br
invalidate loop.io.resp.f1[3].taken
invalidate loop.io.resp_in[0].f3[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[0].is_jal
invalidate loop.io.resp_in[0].f3[0].is_br
invalidate loop.io.resp_in[0].f3[0].taken
invalidate loop.io.resp_in[0].f3[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[1].is_jal
invalidate loop.io.resp_in[0].f3[1].is_br
invalidate loop.io.resp_in[0].f3[1].taken
invalidate loop.io.resp_in[0].f3[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[2].is_jal
invalidate loop.io.resp_in[0].f3[2].is_br
invalidate loop.io.resp_in[0].f3[2].taken
invalidate loop.io.resp_in[0].f3[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f3[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f3[3].is_jal
invalidate loop.io.resp_in[0].f3[3].is_br
invalidate loop.io.resp_in[0].f3[3].taken
invalidate loop.io.resp_in[0].f2[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[0].is_jal
invalidate loop.io.resp_in[0].f2[0].is_br
invalidate loop.io.resp_in[0].f2[0].taken
invalidate loop.io.resp_in[0].f2[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[1].is_jal
invalidate loop.io.resp_in[0].f2[1].is_br
invalidate loop.io.resp_in[0].f2[1].taken
invalidate loop.io.resp_in[0].f2[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[2].is_jal
invalidate loop.io.resp_in[0].f2[2].is_br
invalidate loop.io.resp_in[0].f2[2].taken
invalidate loop.io.resp_in[0].f2[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f2[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f2[3].is_jal
invalidate loop.io.resp_in[0].f2[3].is_br
invalidate loop.io.resp_in[0].f2[3].taken
invalidate loop.io.resp_in[0].f1[0].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[0].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[0].is_jal
invalidate loop.io.resp_in[0].f1[0].is_br
invalidate loop.io.resp_in[0].f1[0].taken
invalidate loop.io.resp_in[0].f1[1].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[1].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[1].is_jal
invalidate loop.io.resp_in[0].f1[1].is_br
invalidate loop.io.resp_in[0].f1[1].taken
invalidate loop.io.resp_in[0].f1[2].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[2].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[2].is_jal
invalidate loop.io.resp_in[0].f1[2].is_br
invalidate loop.io.resp_in[0].f1[2].taken
invalidate loop.io.resp_in[0].f1[3].predicted_pc.bits
invalidate loop.io.resp_in[0].f1[3].predicted_pc.valid
invalidate loop.io.resp_in[0].f1[3].is_jal
invalidate loop.io.resp_in[0].f1[3].is_br
invalidate loop.io.resp_in[0].f1[3].taken
invalidate loop.io.f1_lhist
invalidate loop.io.f1_ghist
invalidate loop.io.f0_mask
invalidate loop.io.f0_pc
invalidate loop.io.f0_valid
invalidate tage.io.update.bits.meta
invalidate tage.io.update.bits.target
invalidate tage.io.update.bits.lhist
invalidate tage.io.update.bits.ghist
invalidate tage.io.update.bits.cfi_is_jalr
invalidate tage.io.update.bits.cfi_is_jal
invalidate tage.io.update.bits.cfi_is_br
invalidate tage.io.update.bits.cfi_mispredicted
invalidate tage.io.update.bits.cfi_taken
invalidate tage.io.update.bits.cfi_idx.bits
invalidate tage.io.update.bits.cfi_idx.valid
invalidate tage.io.update.bits.br_mask
invalidate tage.io.update.bits.pc
invalidate tage.io.update.bits.btb_mispredicts
invalidate tage.io.update.bits.is_repair_update
invalidate tage.io.update.bits.is_mispredict_update
invalidate tage.io.update.valid
invalidate tage.io.f3_fire
invalidate tage.io.f3_meta
invalidate tage.io.resp.f3[0].predicted_pc.bits
invalidate tage.io.resp.f3[0].predicted_pc.valid
invalidate tage.io.resp.f3[0].is_jal
invalidate tage.io.resp.f3[0].is_br
invalidate tage.io.resp.f3[0].taken
invalidate tage.io.resp.f3[1].predicted_pc.bits
invalidate tage.io.resp.f3[1].predicted_pc.valid
invalidate tage.io.resp.f3[1].is_jal
invalidate tage.io.resp.f3[1].is_br
invalidate tage.io.resp.f3[1].taken
invalidate tage.io.resp.f3[2].predicted_pc.bits
invalidate tage.io.resp.f3[2].predicted_pc.valid
invalidate tage.io.resp.f3[2].is_jal
invalidate tage.io.resp.f3[2].is_br
invalidate tage.io.resp.f3[2].taken
invalidate tage.io.resp.f3[3].predicted_pc.bits
invalidate tage.io.resp.f3[3].predicted_pc.valid
invalidate tage.io.resp.f3[3].is_jal
invalidate tage.io.resp.f3[3].is_br
invalidate tage.io.resp.f3[3].taken
invalidate tage.io.resp.f2[0].predicted_pc.bits
invalidate tage.io.resp.f2[0].predicted_pc.valid
invalidate tage.io.resp.f2[0].is_jal
invalidate tage.io.resp.f2[0].is_br
invalidate tage.io.resp.f2[0].taken
invalidate tage.io.resp.f2[1].predicted_pc.bits
invalidate tage.io.resp.f2[1].predicted_pc.valid
invalidate tage.io.resp.f2[1].is_jal
invalidate tage.io.resp.f2[1].is_br
invalidate tage.io.resp.f2[1].taken
invalidate tage.io.resp.f2[2].predicted_pc.bits
invalidate tage.io.resp.f2[2].predicted_pc.valid
invalidate tage.io.resp.f2[2].is_jal
invalidate tage.io.resp.f2[2].is_br
invalidate tage.io.resp.f2[2].taken
invalidate tage.io.resp.f2[3].predicted_pc.bits
invalidate tage.io.resp.f2[3].predicted_pc.valid
invalidate tage.io.resp.f2[3].is_jal
invalidate tage.io.resp.f2[3].is_br
invalidate tage.io.resp.f2[3].taken
invalidate tage.io.resp.f1[0].predicted_pc.bits
invalidate tage.io.resp.f1[0].predicted_pc.valid
invalidate tage.io.resp.f1[0].is_jal
invalidate tage.io.resp.f1[0].is_br
invalidate tage.io.resp.f1[0].taken
invalidate tage.io.resp.f1[1].predicted_pc.bits
invalidate tage.io.resp.f1[1].predicted_pc.valid
invalidate tage.io.resp.f1[1].is_jal
invalidate tage.io.resp.f1[1].is_br
invalidate tage.io.resp.f1[1].taken
invalidate tage.io.resp.f1[2].predicted_pc.bits
invalidate tage.io.resp.f1[2].predicted_pc.valid
invalidate tage.io.resp.f1[2].is_jal
invalidate tage.io.resp.f1[2].is_br
invalidate tage.io.resp.f1[2].taken
invalidate tage.io.resp.f1[3].predicted_pc.bits
invalidate tage.io.resp.f1[3].predicted_pc.valid
invalidate tage.io.resp.f1[3].is_jal
invalidate tage.io.resp.f1[3].is_br
invalidate tage.io.resp.f1[3].taken
invalidate tage.io.resp_in[0].f3[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[0].is_jal
invalidate tage.io.resp_in[0].f3[0].is_br
invalidate tage.io.resp_in[0].f3[0].taken
invalidate tage.io.resp_in[0].f3[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[1].is_jal
invalidate tage.io.resp_in[0].f3[1].is_br
invalidate tage.io.resp_in[0].f3[1].taken
invalidate tage.io.resp_in[0].f3[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[2].is_jal
invalidate tage.io.resp_in[0].f3[2].is_br
invalidate tage.io.resp_in[0].f3[2].taken
invalidate tage.io.resp_in[0].f3[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f3[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f3[3].is_jal
invalidate tage.io.resp_in[0].f3[3].is_br
invalidate tage.io.resp_in[0].f3[3].taken
invalidate tage.io.resp_in[0].f2[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[0].is_jal
invalidate tage.io.resp_in[0].f2[0].is_br
invalidate tage.io.resp_in[0].f2[0].taken
invalidate tage.io.resp_in[0].f2[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[1].is_jal
invalidate tage.io.resp_in[0].f2[1].is_br
invalidate tage.io.resp_in[0].f2[1].taken
invalidate tage.io.resp_in[0].f2[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[2].is_jal
invalidate tage.io.resp_in[0].f2[2].is_br
invalidate tage.io.resp_in[0].f2[2].taken
invalidate tage.io.resp_in[0].f2[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f2[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f2[3].is_jal
invalidate tage.io.resp_in[0].f2[3].is_br
invalidate tage.io.resp_in[0].f2[3].taken
invalidate tage.io.resp_in[0].f1[0].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[0].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[0].is_jal
invalidate tage.io.resp_in[0].f1[0].is_br
invalidate tage.io.resp_in[0].f1[0].taken
invalidate tage.io.resp_in[0].f1[1].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[1].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[1].is_jal
invalidate tage.io.resp_in[0].f1[1].is_br
invalidate tage.io.resp_in[0].f1[1].taken
invalidate tage.io.resp_in[0].f1[2].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[2].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[2].is_jal
invalidate tage.io.resp_in[0].f1[2].is_br
invalidate tage.io.resp_in[0].f1[2].taken
invalidate tage.io.resp_in[0].f1[3].predicted_pc.bits
invalidate tage.io.resp_in[0].f1[3].predicted_pc.valid
invalidate tage.io.resp_in[0].f1[3].is_jal
invalidate tage.io.resp_in[0].f1[3].is_br
invalidate tage.io.resp_in[0].f1[3].taken
invalidate tage.io.f1_lhist
invalidate tage.io.f1_ghist
invalidate tage.io.f0_mask
invalidate tage.io.f0_pc
invalidate tage.io.f0_valid
invalidate btb.io.update.bits.meta
invalidate btb.io.update.bits.target
invalidate btb.io.update.bits.lhist
invalidate btb.io.update.bits.ghist
invalidate btb.io.update.bits.cfi_is_jalr
invalidate btb.io.update.bits.cfi_is_jal
invalidate btb.io.update.bits.cfi_is_br
invalidate btb.io.update.bits.cfi_mispredicted
invalidate btb.io.update.bits.cfi_taken
invalidate btb.io.update.bits.cfi_idx.bits
invalidate btb.io.update.bits.cfi_idx.valid
invalidate btb.io.update.bits.br_mask
invalidate btb.io.update.bits.pc
invalidate btb.io.update.bits.btb_mispredicts
invalidate btb.io.update.bits.is_repair_update
invalidate btb.io.update.bits.is_mispredict_update
invalidate btb.io.update.valid
invalidate btb.io.f3_fire
invalidate btb.io.f3_meta
invalidate btb.io.resp.f3[0].predicted_pc.bits
invalidate btb.io.resp.f3[0].predicted_pc.valid
invalidate btb.io.resp.f3[0].is_jal
invalidate btb.io.resp.f3[0].is_br
invalidate btb.io.resp.f3[0].taken
invalidate btb.io.resp.f3[1].predicted_pc.bits
invalidate btb.io.resp.f3[1].predicted_pc.valid
invalidate btb.io.resp.f3[1].is_jal
invalidate btb.io.resp.f3[1].is_br
invalidate btb.io.resp.f3[1].taken
invalidate btb.io.resp.f3[2].predicted_pc.bits
invalidate btb.io.resp.f3[2].predicted_pc.valid
invalidate btb.io.resp.f3[2].is_jal
invalidate btb.io.resp.f3[2].is_br
invalidate btb.io.resp.f3[2].taken
invalidate btb.io.resp.f3[3].predicted_pc.bits
invalidate btb.io.resp.f3[3].predicted_pc.valid
invalidate btb.io.resp.f3[3].is_jal
invalidate btb.io.resp.f3[3].is_br
invalidate btb.io.resp.f3[3].taken
invalidate btb.io.resp.f2[0].predicted_pc.bits
invalidate btb.io.resp.f2[0].predicted_pc.valid
invalidate btb.io.resp.f2[0].is_jal
invalidate btb.io.resp.f2[0].is_br
invalidate btb.io.resp.f2[0].taken
invalidate btb.io.resp.f2[1].predicted_pc.bits
invalidate btb.io.resp.f2[1].predicted_pc.valid
invalidate btb.io.resp.f2[1].is_jal
invalidate btb.io.resp.f2[1].is_br
invalidate btb.io.resp.f2[1].taken
invalidate btb.io.resp.f2[2].predicted_pc.bits
invalidate btb.io.resp.f2[2].predicted_pc.valid
invalidate btb.io.resp.f2[2].is_jal
invalidate btb.io.resp.f2[2].is_br
invalidate btb.io.resp.f2[2].taken
invalidate btb.io.resp.f2[3].predicted_pc.bits
invalidate btb.io.resp.f2[3].predicted_pc.valid
invalidate btb.io.resp.f2[3].is_jal
invalidate btb.io.resp.f2[3].is_br
invalidate btb.io.resp.f2[3].taken
invalidate btb.io.resp.f1[0].predicted_pc.bits
invalidate btb.io.resp.f1[0].predicted_pc.valid
invalidate btb.io.resp.f1[0].is_jal
invalidate btb.io.resp.f1[0].is_br
invalidate btb.io.resp.f1[0].taken
invalidate btb.io.resp.f1[1].predicted_pc.bits
invalidate btb.io.resp.f1[1].predicted_pc.valid
invalidate btb.io.resp.f1[1].is_jal
invalidate btb.io.resp.f1[1].is_br
invalidate btb.io.resp.f1[1].taken
invalidate btb.io.resp.f1[2].predicted_pc.bits
invalidate btb.io.resp.f1[2].predicted_pc.valid
invalidate btb.io.resp.f1[2].is_jal
invalidate btb.io.resp.f1[2].is_br
invalidate btb.io.resp.f1[2].taken
invalidate btb.io.resp.f1[3].predicted_pc.bits
invalidate btb.io.resp.f1[3].predicted_pc.valid
invalidate btb.io.resp.f1[3].is_jal
invalidate btb.io.resp.f1[3].is_br
invalidate btb.io.resp.f1[3].taken
invalidate btb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[0].is_jal
invalidate btb.io.resp_in[0].f3[0].is_br
invalidate btb.io.resp_in[0].f3[0].taken
invalidate btb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[1].is_jal
invalidate btb.io.resp_in[0].f3[1].is_br
invalidate btb.io.resp_in[0].f3[1].taken
invalidate btb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[2].is_jal
invalidate btb.io.resp_in[0].f3[2].is_br
invalidate btb.io.resp_in[0].f3[2].taken
invalidate btb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f3[3].is_jal
invalidate btb.io.resp_in[0].f3[3].is_br
invalidate btb.io.resp_in[0].f3[3].taken
invalidate btb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[0].is_jal
invalidate btb.io.resp_in[0].f2[0].is_br
invalidate btb.io.resp_in[0].f2[0].taken
invalidate btb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[1].is_jal
invalidate btb.io.resp_in[0].f2[1].is_br
invalidate btb.io.resp_in[0].f2[1].taken
invalidate btb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[2].is_jal
invalidate btb.io.resp_in[0].f2[2].is_br
invalidate btb.io.resp_in[0].f2[2].taken
invalidate btb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f2[3].is_jal
invalidate btb.io.resp_in[0].f2[3].is_br
invalidate btb.io.resp_in[0].f2[3].taken
invalidate btb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[0].is_jal
invalidate btb.io.resp_in[0].f1[0].is_br
invalidate btb.io.resp_in[0].f1[0].taken
invalidate btb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[1].is_jal
invalidate btb.io.resp_in[0].f1[1].is_br
invalidate btb.io.resp_in[0].f1[1].taken
invalidate btb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[2].is_jal
invalidate btb.io.resp_in[0].f1[2].is_br
invalidate btb.io.resp_in[0].f1[2].taken
invalidate btb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate btb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate btb.io.resp_in[0].f1[3].is_jal
invalidate btb.io.resp_in[0].f1[3].is_br
invalidate btb.io.resp_in[0].f1[3].taken
invalidate btb.io.f1_lhist
invalidate btb.io.f1_ghist
invalidate btb.io.f0_mask
invalidate btb.io.f0_pc
invalidate btb.io.f0_valid
invalidate ubtb.io.update.bits.meta
invalidate ubtb.io.update.bits.target
invalidate ubtb.io.update.bits.lhist
invalidate ubtb.io.update.bits.ghist
invalidate ubtb.io.update.bits.cfi_is_jalr
invalidate ubtb.io.update.bits.cfi_is_jal
invalidate ubtb.io.update.bits.cfi_is_br
invalidate ubtb.io.update.bits.cfi_mispredicted
invalidate ubtb.io.update.bits.cfi_taken
invalidate ubtb.io.update.bits.cfi_idx.bits
invalidate ubtb.io.update.bits.cfi_idx.valid
invalidate ubtb.io.update.bits.br_mask
invalidate ubtb.io.update.bits.pc
invalidate ubtb.io.update.bits.btb_mispredicts
invalidate ubtb.io.update.bits.is_repair_update
invalidate ubtb.io.update.bits.is_mispredict_update
invalidate ubtb.io.update.valid
invalidate ubtb.io.f3_fire
invalidate ubtb.io.f3_meta
invalidate ubtb.io.resp.f3[0].predicted_pc.bits
invalidate ubtb.io.resp.f3[0].predicted_pc.valid
invalidate ubtb.io.resp.f3[0].is_jal
invalidate ubtb.io.resp.f3[0].is_br
invalidate ubtb.io.resp.f3[0].taken
invalidate ubtb.io.resp.f3[1].predicted_pc.bits
invalidate ubtb.io.resp.f3[1].predicted_pc.valid
invalidate ubtb.io.resp.f3[1].is_jal
invalidate ubtb.io.resp.f3[1].is_br
invalidate ubtb.io.resp.f3[1].taken
invalidate ubtb.io.resp.f3[2].predicted_pc.bits
invalidate ubtb.io.resp.f3[2].predicted_pc.valid
invalidate ubtb.io.resp.f3[2].is_jal
invalidate ubtb.io.resp.f3[2].is_br
invalidate ubtb.io.resp.f3[2].taken
invalidate ubtb.io.resp.f3[3].predicted_pc.bits
invalidate ubtb.io.resp.f3[3].predicted_pc.valid
invalidate ubtb.io.resp.f3[3].is_jal
invalidate ubtb.io.resp.f3[3].is_br
invalidate ubtb.io.resp.f3[3].taken
invalidate ubtb.io.resp.f2[0].predicted_pc.bits
invalidate ubtb.io.resp.f2[0].predicted_pc.valid
invalidate ubtb.io.resp.f2[0].is_jal
invalidate ubtb.io.resp.f2[0].is_br
invalidate ubtb.io.resp.f2[0].taken
invalidate ubtb.io.resp.f2[1].predicted_pc.bits
invalidate ubtb.io.resp.f2[1].predicted_pc.valid
invalidate ubtb.io.resp.f2[1].is_jal
invalidate ubtb.io.resp.f2[1].is_br
invalidate ubtb.io.resp.f2[1].taken
invalidate ubtb.io.resp.f2[2].predicted_pc.bits
invalidate ubtb.io.resp.f2[2].predicted_pc.valid
invalidate ubtb.io.resp.f2[2].is_jal
invalidate ubtb.io.resp.f2[2].is_br
invalidate ubtb.io.resp.f2[2].taken
invalidate ubtb.io.resp.f2[3].predicted_pc.bits
invalidate ubtb.io.resp.f2[3].predicted_pc.valid
invalidate ubtb.io.resp.f2[3].is_jal
invalidate ubtb.io.resp.f2[3].is_br
invalidate ubtb.io.resp.f2[3].taken
invalidate ubtb.io.resp.f1[0].predicted_pc.bits
invalidate ubtb.io.resp.f1[0].predicted_pc.valid
invalidate ubtb.io.resp.f1[0].is_jal
invalidate ubtb.io.resp.f1[0].is_br
invalidate ubtb.io.resp.f1[0].taken
invalidate ubtb.io.resp.f1[1].predicted_pc.bits
invalidate ubtb.io.resp.f1[1].predicted_pc.valid
invalidate ubtb.io.resp.f1[1].is_jal
invalidate ubtb.io.resp.f1[1].is_br
invalidate ubtb.io.resp.f1[1].taken
invalidate ubtb.io.resp.f1[2].predicted_pc.bits
invalidate ubtb.io.resp.f1[2].predicted_pc.valid
invalidate ubtb.io.resp.f1[2].is_jal
invalidate ubtb.io.resp.f1[2].is_br
invalidate ubtb.io.resp.f1[2].taken
invalidate ubtb.io.resp.f1[3].predicted_pc.bits
invalidate ubtb.io.resp.f1[3].predicted_pc.valid
invalidate ubtb.io.resp.f1[3].is_jal
invalidate ubtb.io.resp.f1[3].is_br
invalidate ubtb.io.resp.f1[3].taken
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[0].is_jal
invalidate ubtb.io.resp_in[0].f3[0].is_br
invalidate ubtb.io.resp_in[0].f3[0].taken
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[1].is_jal
invalidate ubtb.io.resp_in[0].f3[1].is_br
invalidate ubtb.io.resp_in[0].f3[1].taken
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[2].is_jal
invalidate ubtb.io.resp_in[0].f3[2].is_br
invalidate ubtb.io.resp_in[0].f3[2].taken
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f3[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f3[3].is_jal
invalidate ubtb.io.resp_in[0].f3[3].is_br
invalidate ubtb.io.resp_in[0].f3[3].taken
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[0].is_jal
invalidate ubtb.io.resp_in[0].f2[0].is_br
invalidate ubtb.io.resp_in[0].f2[0].taken
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[1].is_jal
invalidate ubtb.io.resp_in[0].f2[1].is_br
invalidate ubtb.io.resp_in[0].f2[1].taken
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[2].is_jal
invalidate ubtb.io.resp_in[0].f2[2].is_br
invalidate ubtb.io.resp_in[0].f2[2].taken
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f2[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f2[3].is_jal
invalidate ubtb.io.resp_in[0].f2[3].is_br
invalidate ubtb.io.resp_in[0].f2[3].taken
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[0].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[0].is_jal
invalidate ubtb.io.resp_in[0].f1[0].is_br
invalidate ubtb.io.resp_in[0].f1[0].taken
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[1].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[1].is_jal
invalidate ubtb.io.resp_in[0].f1[1].is_br
invalidate ubtb.io.resp_in[0].f1[1].taken
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[2].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[2].is_jal
invalidate ubtb.io.resp_in[0].f1[2].is_br
invalidate ubtb.io.resp_in[0].f1[2].taken
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.bits
invalidate ubtb.io.resp_in[0].f1[3].predicted_pc.valid
invalidate ubtb.io.resp_in[0].f1[3].is_jal
invalidate ubtb.io.resp_in[0].f1[3].is_br
invalidate ubtb.io.resp_in[0].f1[3].taken
invalidate ubtb.io.f1_lhist
invalidate ubtb.io.f1_ghist
invalidate ubtb.io.f0_mask
invalidate ubtb.io.f0_pc
invalidate ubtb.io.f0_valid
invalidate bim.io.update.bits.meta
invalidate bim.io.update.bits.target
invalidate bim.io.update.bits.lhist
invalidate bim.io.update.bits.ghist
invalidate bim.io.update.bits.cfi_is_jalr
invalidate bim.io.update.bits.cfi_is_jal
invalidate bim.io.update.bits.cfi_is_br
invalidate bim.io.update.bits.cfi_mispredicted
invalidate bim.io.update.bits.cfi_taken
invalidate bim.io.update.bits.cfi_idx.bits
invalidate bim.io.update.bits.cfi_idx.valid
invalidate bim.io.update.bits.br_mask
invalidate bim.io.update.bits.pc
invalidate bim.io.update.bits.btb_mispredicts
invalidate bim.io.update.bits.is_repair_update
invalidate bim.io.update.bits.is_mispredict_update
invalidate bim.io.update.valid
invalidate bim.io.f3_fire
invalidate bim.io.f3_meta
invalidate bim.io.resp.f3[0].predicted_pc.bits
invalidate bim.io.resp.f3[0].predicted_pc.valid
invalidate bim.io.resp.f3[0].is_jal
invalidate bim.io.resp.f3[0].is_br
invalidate bim.io.resp.f3[0].taken
invalidate bim.io.resp.f3[1].predicted_pc.bits
invalidate bim.io.resp.f3[1].predicted_pc.valid
invalidate bim.io.resp.f3[1].is_jal
invalidate bim.io.resp.f3[1].is_br
invalidate bim.io.resp.f3[1].taken
invalidate bim.io.resp.f3[2].predicted_pc.bits
invalidate bim.io.resp.f3[2].predicted_pc.valid
invalidate bim.io.resp.f3[2].is_jal
invalidate bim.io.resp.f3[2].is_br
invalidate bim.io.resp.f3[2].taken
invalidate bim.io.resp.f3[3].predicted_pc.bits
invalidate bim.io.resp.f3[3].predicted_pc.valid
invalidate bim.io.resp.f3[3].is_jal
invalidate bim.io.resp.f3[3].is_br
invalidate bim.io.resp.f3[3].taken
invalidate bim.io.resp.f2[0].predicted_pc.bits
invalidate bim.io.resp.f2[0].predicted_pc.valid
invalidate bim.io.resp.f2[0].is_jal
invalidate bim.io.resp.f2[0].is_br
invalidate bim.io.resp.f2[0].taken
invalidate bim.io.resp.f2[1].predicted_pc.bits
invalidate bim.io.resp.f2[1].predicted_pc.valid
invalidate bim.io.resp.f2[1].is_jal
invalidate bim.io.resp.f2[1].is_br
invalidate bim.io.resp.f2[1].taken
invalidate bim.io.resp.f2[2].predicted_pc.bits
invalidate bim.io.resp.f2[2].predicted_pc.valid
invalidate bim.io.resp.f2[2].is_jal
invalidate bim.io.resp.f2[2].is_br
invalidate bim.io.resp.f2[2].taken
invalidate bim.io.resp.f2[3].predicted_pc.bits
invalidate bim.io.resp.f2[3].predicted_pc.valid
invalidate bim.io.resp.f2[3].is_jal
invalidate bim.io.resp.f2[3].is_br
invalidate bim.io.resp.f2[3].taken
invalidate bim.io.resp.f1[0].predicted_pc.bits
invalidate bim.io.resp.f1[0].predicted_pc.valid
invalidate bim.io.resp.f1[0].is_jal
invalidate bim.io.resp.f1[0].is_br
invalidate bim.io.resp.f1[0].taken
invalidate bim.io.resp.f1[1].predicted_pc.bits
invalidate bim.io.resp.f1[1].predicted_pc.valid
invalidate bim.io.resp.f1[1].is_jal
invalidate bim.io.resp.f1[1].is_br
invalidate bim.io.resp.f1[1].taken
invalidate bim.io.resp.f1[2].predicted_pc.bits
invalidate bim.io.resp.f1[2].predicted_pc.valid
invalidate bim.io.resp.f1[2].is_jal
invalidate bim.io.resp.f1[2].is_br
invalidate bim.io.resp.f1[2].taken
invalidate bim.io.resp.f1[3].predicted_pc.bits
invalidate bim.io.resp.f1[3].predicted_pc.valid
invalidate bim.io.resp.f1[3].is_jal
invalidate bim.io.resp.f1[3].is_br
invalidate bim.io.resp.f1[3].taken
invalidate bim.io.resp_in[0].f3[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[0].is_jal
invalidate bim.io.resp_in[0].f3[0].is_br
invalidate bim.io.resp_in[0].f3[0].taken
invalidate bim.io.resp_in[0].f3[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[1].is_jal
invalidate bim.io.resp_in[0].f3[1].is_br
invalidate bim.io.resp_in[0].f3[1].taken
invalidate bim.io.resp_in[0].f3[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[2].is_jal
invalidate bim.io.resp_in[0].f3[2].is_br
invalidate bim.io.resp_in[0].f3[2].taken
invalidate bim.io.resp_in[0].f3[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f3[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f3[3].is_jal
invalidate bim.io.resp_in[0].f3[3].is_br
invalidate bim.io.resp_in[0].f3[3].taken
invalidate bim.io.resp_in[0].f2[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[0].is_jal
invalidate bim.io.resp_in[0].f2[0].is_br
invalidate bim.io.resp_in[0].f2[0].taken
invalidate bim.io.resp_in[0].f2[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[1].is_jal
invalidate bim.io.resp_in[0].f2[1].is_br
invalidate bim.io.resp_in[0].f2[1].taken
invalidate bim.io.resp_in[0].f2[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[2].is_jal
invalidate bim.io.resp_in[0].f2[2].is_br
invalidate bim.io.resp_in[0].f2[2].taken
invalidate bim.io.resp_in[0].f2[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f2[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f2[3].is_jal
invalidate bim.io.resp_in[0].f2[3].is_br
invalidate bim.io.resp_in[0].f2[3].taken
invalidate bim.io.resp_in[0].f1[0].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[0].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[0].is_jal
invalidate bim.io.resp_in[0].f1[0].is_br
invalidate bim.io.resp_in[0].f1[0].taken
invalidate bim.io.resp_in[0].f1[1].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[1].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[1].is_jal
invalidate bim.io.resp_in[0].f1[1].is_br
invalidate bim.io.resp_in[0].f1[1].taken
invalidate bim.io.resp_in[0].f1[2].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[2].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[2].is_jal
invalidate bim.io.resp_in[0].f1[2].is_br
invalidate bim.io.resp_in[0].f1[2].taken
invalidate bim.io.resp_in[0].f1[3].predicted_pc.bits
invalidate bim.io.resp_in[0].f1[3].predicted_pc.valid
invalidate bim.io.resp_in[0].f1[3].is_jal
invalidate bim.io.resp_in[0].f1[3].is_br
invalidate bim.io.resp_in[0].f1[3].taken
invalidate bim.io.f1_lhist
invalidate bim.io.f1_ghist
invalidate bim.io.f0_mask
invalidate bim.io.f0_pc
invalidate bim.io.f0_valid
connect ubtb.io.resp_in[0].f3[0].predicted_pc.bits, io.resp_in[0].f3[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[0].predicted_pc.valid, io.resp_in[0].f3[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[0].is_jal, io.resp_in[0].f3[0].is_jal
connect ubtb.io.resp_in[0].f3[0].is_br, io.resp_in[0].f3[0].is_br
connect ubtb.io.resp_in[0].f3[0].taken, io.resp_in[0].f3[0].taken
connect ubtb.io.resp_in[0].f3[1].predicted_pc.bits, io.resp_in[0].f3[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[1].predicted_pc.valid, io.resp_in[0].f3[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[1].is_jal, io.resp_in[0].f3[1].is_jal
connect ubtb.io.resp_in[0].f3[1].is_br, io.resp_in[0].f3[1].is_br
connect ubtb.io.resp_in[0].f3[1].taken, io.resp_in[0].f3[1].taken
connect ubtb.io.resp_in[0].f3[2].predicted_pc.bits, io.resp_in[0].f3[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[2].predicted_pc.valid, io.resp_in[0].f3[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[2].is_jal, io.resp_in[0].f3[2].is_jal
connect ubtb.io.resp_in[0].f3[2].is_br, io.resp_in[0].f3[2].is_br
connect ubtb.io.resp_in[0].f3[2].taken, io.resp_in[0].f3[2].taken
connect ubtb.io.resp_in[0].f3[3].predicted_pc.bits, io.resp_in[0].f3[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f3[3].predicted_pc.valid, io.resp_in[0].f3[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f3[3].is_jal, io.resp_in[0].f3[3].is_jal
connect ubtb.io.resp_in[0].f3[3].is_br, io.resp_in[0].f3[3].is_br
connect ubtb.io.resp_in[0].f3[3].taken, io.resp_in[0].f3[3].taken
connect ubtb.io.resp_in[0].f2[0].predicted_pc.bits, io.resp_in[0].f2[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[0].is_jal, io.resp_in[0].f2[0].is_jal
connect ubtb.io.resp_in[0].f2[0].is_br, io.resp_in[0].f2[0].is_br
connect ubtb.io.resp_in[0].f2[0].taken, io.resp_in[0].f2[0].taken
connect ubtb.io.resp_in[0].f2[1].predicted_pc.bits, io.resp_in[0].f2[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[1].is_jal, io.resp_in[0].f2[1].is_jal
connect ubtb.io.resp_in[0].f2[1].is_br, io.resp_in[0].f2[1].is_br
connect ubtb.io.resp_in[0].f2[1].taken, io.resp_in[0].f2[1].taken
connect ubtb.io.resp_in[0].f2[2].predicted_pc.bits, io.resp_in[0].f2[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[2].is_jal, io.resp_in[0].f2[2].is_jal
connect ubtb.io.resp_in[0].f2[2].is_br, io.resp_in[0].f2[2].is_br
connect ubtb.io.resp_in[0].f2[2].taken, io.resp_in[0].f2[2].taken
connect ubtb.io.resp_in[0].f2[3].predicted_pc.bits, io.resp_in[0].f2[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f2[3].is_jal, io.resp_in[0].f2[3].is_jal
connect ubtb.io.resp_in[0].f2[3].is_br, io.resp_in[0].f2[3].is_br
connect ubtb.io.resp_in[0].f2[3].taken, io.resp_in[0].f2[3].taken
connect ubtb.io.resp_in[0].f1[0].predicted_pc.bits, io.resp_in[0].f1[0].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[0].predicted_pc.valid, io.resp_in[0].f1[0].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[0].is_jal, io.resp_in[0].f1[0].is_jal
connect ubtb.io.resp_in[0].f1[0].is_br, io.resp_in[0].f1[0].is_br
connect ubtb.io.resp_in[0].f1[0].taken, io.resp_in[0].f1[0].taken
connect ubtb.io.resp_in[0].f1[1].predicted_pc.bits, io.resp_in[0].f1[1].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[1].predicted_pc.valid, io.resp_in[0].f1[1].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[1].is_jal, io.resp_in[0].f1[1].is_jal
connect ubtb.io.resp_in[0].f1[1].is_br, io.resp_in[0].f1[1].is_br
connect ubtb.io.resp_in[0].f1[1].taken, io.resp_in[0].f1[1].taken
connect ubtb.io.resp_in[0].f1[2].predicted_pc.bits, io.resp_in[0].f1[2].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[2].predicted_pc.valid, io.resp_in[0].f1[2].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[2].is_jal, io.resp_in[0].f1[2].is_jal
connect ubtb.io.resp_in[0].f1[2].is_br, io.resp_in[0].f1[2].is_br
connect ubtb.io.resp_in[0].f1[2].taken, io.resp_in[0].f1[2].taken
connect ubtb.io.resp_in[0].f1[3].predicted_pc.bits, io.resp_in[0].f1[3].predicted_pc.bits
connect ubtb.io.resp_in[0].f1[3].predicted_pc.valid, io.resp_in[0].f1[3].predicted_pc.valid
connect ubtb.io.resp_in[0].f1[3].is_jal, io.resp_in[0].f1[3].is_jal
connect ubtb.io.resp_in[0].f1[3].is_br, io.resp_in[0].f1[3].is_br
connect ubtb.io.resp_in[0].f1[3].taken, io.resp_in[0].f1[3].taken
connect bim.io.resp_in[0].f3[0].predicted_pc.bits, ubtb.io.resp.f3[0].predicted_pc.bits
connect bim.io.resp_in[0].f3[0].predicted_pc.valid, ubtb.io.resp.f3[0].predicted_pc.valid
connect bim.io.resp_in[0].f3[0].is_jal, ubtb.io.resp.f3[0].is_jal
connect bim.io.resp_in[0].f3[0].is_br, ubtb.io.resp.f3[0].is_br
connect bim.io.resp_in[0].f3[0].taken, ubtb.io.resp.f3[0].taken
connect bim.io.resp_in[0].f3[1].predicted_pc.bits, ubtb.io.resp.f3[1].predicted_pc.bits
connect bim.io.resp_in[0].f3[1].predicted_pc.valid, ubtb.io.resp.f3[1].predicted_pc.valid
connect bim.io.resp_in[0].f3[1].is_jal, ubtb.io.resp.f3[1].is_jal
connect bim.io.resp_in[0].f3[1].is_br, ubtb.io.resp.f3[1].is_br
connect bim.io.resp_in[0].f3[1].taken, ubtb.io.resp.f3[1].taken
connect bim.io.resp_in[0].f3[2].predicted_pc.bits, ubtb.io.resp.f3[2].predicted_pc.bits
connect bim.io.resp_in[0].f3[2].predicted_pc.valid, ubtb.io.resp.f3[2].predicted_pc.valid
connect bim.io.resp_in[0].f3[2].is_jal, ubtb.io.resp.f3[2].is_jal
connect bim.io.resp_in[0].f3[2].is_br, ubtb.io.resp.f3[2].is_br
connect bim.io.resp_in[0].f3[2].taken, ubtb.io.resp.f3[2].taken
connect bim.io.resp_in[0].f3[3].predicted_pc.bits, ubtb.io.resp.f3[3].predicted_pc.bits
connect bim.io.resp_in[0].f3[3].predicted_pc.valid, ubtb.io.resp.f3[3].predicted_pc.valid
connect bim.io.resp_in[0].f3[3].is_jal, ubtb.io.resp.f3[3].is_jal
connect bim.io.resp_in[0].f3[3].is_br, ubtb.io.resp.f3[3].is_br
connect bim.io.resp_in[0].f3[3].taken, ubtb.io.resp.f3[3].taken
connect bim.io.resp_in[0].f2[0].predicted_pc.bits, ubtb.io.resp.f2[0].predicted_pc.bits
connect bim.io.resp_in[0].f2[0].predicted_pc.valid, ubtb.io.resp.f2[0].predicted_pc.valid
connect bim.io.resp_in[0].f2[0].is_jal, ubtb.io.resp.f2[0].is_jal
connect bim.io.resp_in[0].f2[0].is_br, ubtb.io.resp.f2[0].is_br
connect bim.io.resp_in[0].f2[0].taken, ubtb.io.resp.f2[0].taken
connect bim.io.resp_in[0].f2[1].predicted_pc.bits, ubtb.io.resp.f2[1].predicted_pc.bits
connect bim.io.resp_in[0].f2[1].predicted_pc.valid, ubtb.io.resp.f2[1].predicted_pc.valid
connect bim.io.resp_in[0].f2[1].is_jal, ubtb.io.resp.f2[1].is_jal
connect bim.io.resp_in[0].f2[1].is_br, ubtb.io.resp.f2[1].is_br
connect bim.io.resp_in[0].f2[1].taken, ubtb.io.resp.f2[1].taken
connect bim.io.resp_in[0].f2[2].predicted_pc.bits, ubtb.io.resp.f2[2].predicted_pc.bits
connect bim.io.resp_in[0].f2[2].predicted_pc.valid, ubtb.io.resp.f2[2].predicted_pc.valid
connect bim.io.resp_in[0].f2[2].is_jal, ubtb.io.resp.f2[2].is_jal
connect bim.io.resp_in[0].f2[2].is_br, ubtb.io.resp.f2[2].is_br
connect bim.io.resp_in[0].f2[2].taken, ubtb.io.resp.f2[2].taken
connect bim.io.resp_in[0].f2[3].predicted_pc.bits, ubtb.io.resp.f2[3].predicted_pc.bits
connect bim.io.resp_in[0].f2[3].predicted_pc.valid, ubtb.io.resp.f2[3].predicted_pc.valid
connect bim.io.resp_in[0].f2[3].is_jal, ubtb.io.resp.f2[3].is_jal
connect bim.io.resp_in[0].f2[3].is_br, ubtb.io.resp.f2[3].is_br
connect bim.io.resp_in[0].f2[3].taken, ubtb.io.resp.f2[3].taken
connect bim.io.resp_in[0].f1[0].predicted_pc.bits, ubtb.io.resp.f1[0].predicted_pc.bits
connect bim.io.resp_in[0].f1[0].predicted_pc.valid, ubtb.io.resp.f1[0].predicted_pc.valid
connect bim.io.resp_in[0].f1[0].is_jal, ubtb.io.resp.f1[0].is_jal
connect bim.io.resp_in[0].f1[0].is_br, ubtb.io.resp.f1[0].is_br
connect bim.io.resp_in[0].f1[0].taken, ubtb.io.resp.f1[0].taken
connect bim.io.resp_in[0].f1[1].predicted_pc.bits, ubtb.io.resp.f1[1].predicted_pc.bits
connect bim.io.resp_in[0].f1[1].predicted_pc.valid, ubtb.io.resp.f1[1].predicted_pc.valid
connect bim.io.resp_in[0].f1[1].is_jal, ubtb.io.resp.f1[1].is_jal
connect bim.io.resp_in[0].f1[1].is_br, ubtb.io.resp.f1[1].is_br
connect bim.io.resp_in[0].f1[1].taken, ubtb.io.resp.f1[1].taken
connect bim.io.resp_in[0].f1[2].predicted_pc.bits, ubtb.io.resp.f1[2].predicted_pc.bits
connect bim.io.resp_in[0].f1[2].predicted_pc.valid, ubtb.io.resp.f1[2].predicted_pc.valid
connect bim.io.resp_in[0].f1[2].is_jal, ubtb.io.resp.f1[2].is_jal
connect bim.io.resp_in[0].f1[2].is_br, ubtb.io.resp.f1[2].is_br
connect bim.io.resp_in[0].f1[2].taken, ubtb.io.resp.f1[2].taken
connect bim.io.resp_in[0].f1[3].predicted_pc.bits, ubtb.io.resp.f1[3].predicted_pc.bits
connect bim.io.resp_in[0].f1[3].predicted_pc.valid, ubtb.io.resp.f1[3].predicted_pc.valid
connect bim.io.resp_in[0].f1[3].is_jal, ubtb.io.resp.f1[3].is_jal
connect bim.io.resp_in[0].f1[3].is_br, ubtb.io.resp.f1[3].is_br
connect bim.io.resp_in[0].f1[3].taken, ubtb.io.resp.f1[3].taken
connect btb.io.resp_in[0].f3[0].predicted_pc.bits, bim.io.resp.f3[0].predicted_pc.bits
connect btb.io.resp_in[0].f3[0].predicted_pc.valid, bim.io.resp.f3[0].predicted_pc.valid
connect btb.io.resp_in[0].f3[0].is_jal, bim.io.resp.f3[0].is_jal
connect btb.io.resp_in[0].f3[0].is_br, bim.io.resp.f3[0].is_br
connect btb.io.resp_in[0].f3[0].taken, bim.io.resp.f3[0].taken
connect btb.io.resp_in[0].f3[1].predicted_pc.bits, bim.io.resp.f3[1].predicted_pc.bits
connect btb.io.resp_in[0].f3[1].predicted_pc.valid, bim.io.resp.f3[1].predicted_pc.valid
connect btb.io.resp_in[0].f3[1].is_jal, bim.io.resp.f3[1].is_jal
connect btb.io.resp_in[0].f3[1].is_br, bim.io.resp.f3[1].is_br
connect btb.io.resp_in[0].f3[1].taken, bim.io.resp.f3[1].taken
connect btb.io.resp_in[0].f3[2].predicted_pc.bits, bim.io.resp.f3[2].predicted_pc.bits
connect btb.io.resp_in[0].f3[2].predicted_pc.valid, bim.io.resp.f3[2].predicted_pc.valid
connect btb.io.resp_in[0].f3[2].is_jal, bim.io.resp.f3[2].is_jal
connect btb.io.resp_in[0].f3[2].is_br, bim.io.resp.f3[2].is_br
connect btb.io.resp_in[0].f3[2].taken, bim.io.resp.f3[2].taken
connect btb.io.resp_in[0].f3[3].predicted_pc.bits, bim.io.resp.f3[3].predicted_pc.bits
connect btb.io.resp_in[0].f3[3].predicted_pc.valid, bim.io.resp.f3[3].predicted_pc.valid
connect btb.io.resp_in[0].f3[3].is_jal, bim.io.resp.f3[3].is_jal
connect btb.io.resp_in[0].f3[3].is_br, bim.io.resp.f3[3].is_br
connect btb.io.resp_in[0].f3[3].taken, bim.io.resp.f3[3].taken
connect btb.io.resp_in[0].f2[0].predicted_pc.bits, bim.io.resp.f2[0].predicted_pc.bits
connect btb.io.resp_in[0].f2[0].predicted_pc.valid, bim.io.resp.f2[0].predicted_pc.valid
connect btb.io.resp_in[0].f2[0].is_jal, bim.io.resp.f2[0].is_jal
connect btb.io.resp_in[0].f2[0].is_br, bim.io.resp.f2[0].is_br
connect btb.io.resp_in[0].f2[0].taken, bim.io.resp.f2[0].taken
connect btb.io.resp_in[0].f2[1].predicted_pc.bits, bim.io.resp.f2[1].predicted_pc.bits
connect btb.io.resp_in[0].f2[1].predicted_pc.valid, bim.io.resp.f2[1].predicted_pc.valid
connect btb.io.resp_in[0].f2[1].is_jal, bim.io.resp.f2[1].is_jal
connect btb.io.resp_in[0].f2[1].is_br, bim.io.resp.f2[1].is_br
connect btb.io.resp_in[0].f2[1].taken, bim.io.resp.f2[1].taken
connect btb.io.resp_in[0].f2[2].predicted_pc.bits, bim.io.resp.f2[2].predicted_pc.bits
connect btb.io.resp_in[0].f2[2].predicted_pc.valid, bim.io.resp.f2[2].predicted_pc.valid
connect btb.io.resp_in[0].f2[2].is_jal, bim.io.resp.f2[2].is_jal
connect btb.io.resp_in[0].f2[2].is_br, bim.io.resp.f2[2].is_br
connect btb.io.resp_in[0].f2[2].taken, bim.io.resp.f2[2].taken
connect btb.io.resp_in[0].f2[3].predicted_pc.bits, bim.io.resp.f2[3].predicted_pc.bits
connect btb.io.resp_in[0].f2[3].predicted_pc.valid, bim.io.resp.f2[3].predicted_pc.valid
connect btb.io.resp_in[0].f2[3].is_jal, bim.io.resp.f2[3].is_jal
connect btb.io.resp_in[0].f2[3].is_br, bim.io.resp.f2[3].is_br
connect btb.io.resp_in[0].f2[3].taken, bim.io.resp.f2[3].taken
connect btb.io.resp_in[0].f1[0].predicted_pc.bits, bim.io.resp.f1[0].predicted_pc.bits
connect btb.io.resp_in[0].f1[0].predicted_pc.valid, bim.io.resp.f1[0].predicted_pc.valid
connect btb.io.resp_in[0].f1[0].is_jal, bim.io.resp.f1[0].is_jal
connect btb.io.resp_in[0].f1[0].is_br, bim.io.resp.f1[0].is_br
connect btb.io.resp_in[0].f1[0].taken, bim.io.resp.f1[0].taken
connect btb.io.resp_in[0].f1[1].predicted_pc.bits, bim.io.resp.f1[1].predicted_pc.bits
connect btb.io.resp_in[0].f1[1].predicted_pc.valid, bim.io.resp.f1[1].predicted_pc.valid
connect btb.io.resp_in[0].f1[1].is_jal, bim.io.resp.f1[1].is_jal
connect btb.io.resp_in[0].f1[1].is_br, bim.io.resp.f1[1].is_br
connect btb.io.resp_in[0].f1[1].taken, bim.io.resp.f1[1].taken
connect btb.io.resp_in[0].f1[2].predicted_pc.bits, bim.io.resp.f1[2].predicted_pc.bits
connect btb.io.resp_in[0].f1[2].predicted_pc.valid, bim.io.resp.f1[2].predicted_pc.valid
connect btb.io.resp_in[0].f1[2].is_jal, bim.io.resp.f1[2].is_jal
connect btb.io.resp_in[0].f1[2].is_br, bim.io.resp.f1[2].is_br
connect btb.io.resp_in[0].f1[2].taken, bim.io.resp.f1[2].taken
connect btb.io.resp_in[0].f1[3].predicted_pc.bits, bim.io.resp.f1[3].predicted_pc.bits
connect btb.io.resp_in[0].f1[3].predicted_pc.valid, bim.io.resp.f1[3].predicted_pc.valid
connect btb.io.resp_in[0].f1[3].is_jal, bim.io.resp.f1[3].is_jal
connect btb.io.resp_in[0].f1[3].is_br, bim.io.resp.f1[3].is_br
connect btb.io.resp_in[0].f1[3].taken, bim.io.resp.f1[3].taken
connect tage.io.resp_in[0].f3[0].predicted_pc.bits, btb.io.resp.f3[0].predicted_pc.bits
connect tage.io.resp_in[0].f3[0].predicted_pc.valid, btb.io.resp.f3[0].predicted_pc.valid
connect tage.io.resp_in[0].f3[0].is_jal, btb.io.resp.f3[0].is_jal
connect tage.io.resp_in[0].f3[0].is_br, btb.io.resp.f3[0].is_br
connect tage.io.resp_in[0].f3[0].taken, btb.io.resp.f3[0].taken
connect tage.io.resp_in[0].f3[1].predicted_pc.bits, btb.io.resp.f3[1].predicted_pc.bits
connect tage.io.resp_in[0].f3[1].predicted_pc.valid, btb.io.resp.f3[1].predicted_pc.valid
connect tage.io.resp_in[0].f3[1].is_jal, btb.io.resp.f3[1].is_jal
connect tage.io.resp_in[0].f3[1].is_br, btb.io.resp.f3[1].is_br
connect tage.io.resp_in[0].f3[1].taken, btb.io.resp.f3[1].taken
connect tage.io.resp_in[0].f3[2].predicted_pc.bits, btb.io.resp.f3[2].predicted_pc.bits
connect tage.io.resp_in[0].f3[2].predicted_pc.valid, btb.io.resp.f3[2].predicted_pc.valid
connect tage.io.resp_in[0].f3[2].is_jal, btb.io.resp.f3[2].is_jal
connect tage.io.resp_in[0].f3[2].is_br, btb.io.resp.f3[2].is_br
connect tage.io.resp_in[0].f3[2].taken, btb.io.resp.f3[2].taken
connect tage.io.resp_in[0].f3[3].predicted_pc.bits, btb.io.resp.f3[3].predicted_pc.bits
connect tage.io.resp_in[0].f3[3].predicted_pc.valid, btb.io.resp.f3[3].predicted_pc.valid
connect tage.io.resp_in[0].f3[3].is_jal, btb.io.resp.f3[3].is_jal
connect tage.io.resp_in[0].f3[3].is_br, btb.io.resp.f3[3].is_br
connect tage.io.resp_in[0].f3[3].taken, btb.io.resp.f3[3].taken
connect tage.io.resp_in[0].f2[0].predicted_pc.bits, btb.io.resp.f2[0].predicted_pc.bits
connect tage.io.resp_in[0].f2[0].predicted_pc.valid, btb.io.resp.f2[0].predicted_pc.valid
connect tage.io.resp_in[0].f2[0].is_jal, btb.io.resp.f2[0].is_jal
connect tage.io.resp_in[0].f2[0].is_br, btb.io.resp.f2[0].is_br
connect tage.io.resp_in[0].f2[0].taken, btb.io.resp.f2[0].taken
connect tage.io.resp_in[0].f2[1].predicted_pc.bits, btb.io.resp.f2[1].predicted_pc.bits
connect tage.io.resp_in[0].f2[1].predicted_pc.valid, btb.io.resp.f2[1].predicted_pc.valid
connect tage.io.resp_in[0].f2[1].is_jal, btb.io.resp.f2[1].is_jal
connect tage.io.resp_in[0].f2[1].is_br, btb.io.resp.f2[1].is_br
connect tage.io.resp_in[0].f2[1].taken, btb.io.resp.f2[1].taken
connect tage.io.resp_in[0].f2[2].predicted_pc.bits, btb.io.resp.f2[2].predicted_pc.bits
connect tage.io.resp_in[0].f2[2].predicted_pc.valid, btb.io.resp.f2[2].predicted_pc.valid
connect tage.io.resp_in[0].f2[2].is_jal, btb.io.resp.f2[2].is_jal
connect tage.io.resp_in[0].f2[2].is_br, btb.io.resp.f2[2].is_br
connect tage.io.resp_in[0].f2[2].taken, btb.io.resp.f2[2].taken
connect tage.io.resp_in[0].f2[3].predicted_pc.bits, btb.io.resp.f2[3].predicted_pc.bits
connect tage.io.resp_in[0].f2[3].predicted_pc.valid, btb.io.resp.f2[3].predicted_pc.valid
connect tage.io.resp_in[0].f2[3].is_jal, btb.io.resp.f2[3].is_jal
connect tage.io.resp_in[0].f2[3].is_br, btb.io.resp.f2[3].is_br
connect tage.io.resp_in[0].f2[3].taken, btb.io.resp.f2[3].taken
connect tage.io.resp_in[0].f1[0].predicted_pc.bits, btb.io.resp.f1[0].predicted_pc.bits
connect tage.io.resp_in[0].f1[0].predicted_pc.valid, btb.io.resp.f1[0].predicted_pc.valid
connect tage.io.resp_in[0].f1[0].is_jal, btb.io.resp.f1[0].is_jal
connect tage.io.resp_in[0].f1[0].is_br, btb.io.resp.f1[0].is_br
connect tage.io.resp_in[0].f1[0].taken, btb.io.resp.f1[0].taken
connect tage.io.resp_in[0].f1[1].predicted_pc.bits, btb.io.resp.f1[1].predicted_pc.bits
connect tage.io.resp_in[0].f1[1].predicted_pc.valid, btb.io.resp.f1[1].predicted_pc.valid
connect tage.io.resp_in[0].f1[1].is_jal, btb.io.resp.f1[1].is_jal
connect tage.io.resp_in[0].f1[1].is_br, btb.io.resp.f1[1].is_br
connect tage.io.resp_in[0].f1[1].taken, btb.io.resp.f1[1].taken
connect tage.io.resp_in[0].f1[2].predicted_pc.bits, btb.io.resp.f1[2].predicted_pc.bits
connect tage.io.resp_in[0].f1[2].predicted_pc.valid, btb.io.resp.f1[2].predicted_pc.valid
connect tage.io.resp_in[0].f1[2].is_jal, btb.io.resp.f1[2].is_jal
connect tage.io.resp_in[0].f1[2].is_br, btb.io.resp.f1[2].is_br
connect tage.io.resp_in[0].f1[2].taken, btb.io.resp.f1[2].taken
connect tage.io.resp_in[0].f1[3].predicted_pc.bits, btb.io.resp.f1[3].predicted_pc.bits
connect tage.io.resp_in[0].f1[3].predicted_pc.valid, btb.io.resp.f1[3].predicted_pc.valid
connect tage.io.resp_in[0].f1[3].is_jal, btb.io.resp.f1[3].is_jal
connect tage.io.resp_in[0].f1[3].is_br, btb.io.resp.f1[3].is_br
connect tage.io.resp_in[0].f1[3].taken, btb.io.resp.f1[3].taken
connect loop.io.resp_in[0].f3[0].predicted_pc.bits, tage.io.resp.f3[0].predicted_pc.bits
connect loop.io.resp_in[0].f3[0].predicted_pc.valid, tage.io.resp.f3[0].predicted_pc.valid
connect loop.io.resp_in[0].f3[0].is_jal, tage.io.resp.f3[0].is_jal
connect loop.io.resp_in[0].f3[0].is_br, tage.io.resp.f3[0].is_br
connect loop.io.resp_in[0].f3[0].taken, tage.io.resp.f3[0].taken
connect loop.io.resp_in[0].f3[1].predicted_pc.bits, tage.io.resp.f3[1].predicted_pc.bits
connect loop.io.resp_in[0].f3[1].predicted_pc.valid, tage.io.resp.f3[1].predicted_pc.valid
connect loop.io.resp_in[0].f3[1].is_jal, tage.io.resp.f3[1].is_jal
connect loop.io.resp_in[0].f3[1].is_br, tage.io.resp.f3[1].is_br
connect loop.io.resp_in[0].f3[1].taken, tage.io.resp.f3[1].taken
connect loop.io.resp_in[0].f3[2].predicted_pc.bits, tage.io.resp.f3[2].predicted_pc.bits
connect loop.io.resp_in[0].f3[2].predicted_pc.valid, tage.io.resp.f3[2].predicted_pc.valid
connect loop.io.resp_in[0].f3[2].is_jal, tage.io.resp.f3[2].is_jal
connect loop.io.resp_in[0].f3[2].is_br, tage.io.resp.f3[2].is_br
connect loop.io.resp_in[0].f3[2].taken, tage.io.resp.f3[2].taken
connect loop.io.resp_in[0].f3[3].predicted_pc.bits, tage.io.resp.f3[3].predicted_pc.bits
connect loop.io.resp_in[0].f3[3].predicted_pc.valid, tage.io.resp.f3[3].predicted_pc.valid
connect loop.io.resp_in[0].f3[3].is_jal, tage.io.resp.f3[3].is_jal
connect loop.io.resp_in[0].f3[3].is_br, tage.io.resp.f3[3].is_br
connect loop.io.resp_in[0].f3[3].taken, tage.io.resp.f3[3].taken
connect loop.io.resp_in[0].f2[0].predicted_pc.bits, tage.io.resp.f2[0].predicted_pc.bits
connect loop.io.resp_in[0].f2[0].predicted_pc.valid, tage.io.resp.f2[0].predicted_pc.valid
connect loop.io.resp_in[0].f2[0].is_jal, tage.io.resp.f2[0].is_jal
connect loop.io.resp_in[0].f2[0].is_br, tage.io.resp.f2[0].is_br
connect loop.io.resp_in[0].f2[0].taken, tage.io.resp.f2[0].taken
connect loop.io.resp_in[0].f2[1].predicted_pc.bits, tage.io.resp.f2[1].predicted_pc.bits
connect loop.io.resp_in[0].f2[1].predicted_pc.valid, tage.io.resp.f2[1].predicted_pc.valid
connect loop.io.resp_in[0].f2[1].is_jal, tage.io.resp.f2[1].is_jal
connect loop.io.resp_in[0].f2[1].is_br, tage.io.resp.f2[1].is_br
connect loop.io.resp_in[0].f2[1].taken, tage.io.resp.f2[1].taken
connect loop.io.resp_in[0].f2[2].predicted_pc.bits, tage.io.resp.f2[2].predicted_pc.bits
connect loop.io.resp_in[0].f2[2].predicted_pc.valid, tage.io.resp.f2[2].predicted_pc.valid
connect loop.io.resp_in[0].f2[2].is_jal, tage.io.resp.f2[2].is_jal
connect loop.io.resp_in[0].f2[2].is_br, tage.io.resp.f2[2].is_br
connect loop.io.resp_in[0].f2[2].taken, tage.io.resp.f2[2].taken
connect loop.io.resp_in[0].f2[3].predicted_pc.bits, tage.io.resp.f2[3].predicted_pc.bits
connect loop.io.resp_in[0].f2[3].predicted_pc.valid, tage.io.resp.f2[3].predicted_pc.valid
connect loop.io.resp_in[0].f2[3].is_jal, tage.io.resp.f2[3].is_jal
connect loop.io.resp_in[0].f2[3].is_br, tage.io.resp.f2[3].is_br
connect loop.io.resp_in[0].f2[3].taken, tage.io.resp.f2[3].taken
connect loop.io.resp_in[0].f1[0].predicted_pc.bits, tage.io.resp.f1[0].predicted_pc.bits
connect loop.io.resp_in[0].f1[0].predicted_pc.valid, tage.io.resp.f1[0].predicted_pc.valid
connect loop.io.resp_in[0].f1[0].is_jal, tage.io.resp.f1[0].is_jal
connect loop.io.resp_in[0].f1[0].is_br, tage.io.resp.f1[0].is_br
connect loop.io.resp_in[0].f1[0].taken, tage.io.resp.f1[0].taken
connect loop.io.resp_in[0].f1[1].predicted_pc.bits, tage.io.resp.f1[1].predicted_pc.bits
connect loop.io.resp_in[0].f1[1].predicted_pc.valid, tage.io.resp.f1[1].predicted_pc.valid
connect loop.io.resp_in[0].f1[1].is_jal, tage.io.resp.f1[1].is_jal
connect loop.io.resp_in[0].f1[1].is_br, tage.io.resp.f1[1].is_br
connect loop.io.resp_in[0].f1[1].taken, tage.io.resp.f1[1].taken
connect loop.io.resp_in[0].f1[2].predicted_pc.bits, tage.io.resp.f1[2].predicted_pc.bits
connect loop.io.resp_in[0].f1[2].predicted_pc.valid, tage.io.resp.f1[2].predicted_pc.valid
connect loop.io.resp_in[0].f1[2].is_jal, tage.io.resp.f1[2].is_jal
connect loop.io.resp_in[0].f1[2].is_br, tage.io.resp.f1[2].is_br
connect loop.io.resp_in[0].f1[2].taken, tage.io.resp.f1[2].taken
connect loop.io.resp_in[0].f1[3].predicted_pc.bits, tage.io.resp.f1[3].predicted_pc.bits
connect loop.io.resp_in[0].f1[3].predicted_pc.valid, tage.io.resp.f1[3].predicted_pc.valid
connect loop.io.resp_in[0].f1[3].is_jal, tage.io.resp.f1[3].is_jal
connect loop.io.resp_in[0].f1[3].is_br, tage.io.resp.f1[3].is_br
connect loop.io.resp_in[0].f1[3].taken, tage.io.resp.f1[3].taken
connect io.resp, loop.io.resp
connect loop.io.f0_valid, io.f0_valid
connect loop.io.f0_pc, io.f0_pc
connect loop.io.f0_mask, io.f0_mask
connect loop.io.f1_ghist, io.f1_ghist
connect loop.io.f1_lhist, io.f1_lhist
connect loop.io.f3_fire, io.f3_fire
node _T = shl(UInt<1>(0h0), 40)
node _T_1 = bits(loop.io.f3_meta, 39, 0)
node _T_2 = or(_T, _T_1)
connect tage.io.f0_valid, io.f0_valid
connect tage.io.f0_pc, io.f0_pc
connect tage.io.f0_mask, io.f0_mask
connect tage.io.f1_ghist, io.f1_ghist
connect tage.io.f1_lhist, io.f1_lhist
connect tage.io.f3_fire, io.f3_fire
node _T_3 = shl(_T_2, 56)
node _T_4 = bits(tage.io.f3_meta, 55, 0)
node _T_5 = or(_T_3, _T_4)
connect btb.io.f0_valid, io.f0_valid
connect btb.io.f0_pc, io.f0_pc
connect btb.io.f0_mask, io.f0_mask
connect btb.io.f1_ghist, io.f1_ghist
connect btb.io.f1_lhist, io.f1_lhist
connect btb.io.f3_fire, io.f3_fire
node _T_6 = shl(_T_5, 1)
node _T_7 = bits(btb.io.f3_meta, 0, 0)
node _T_8 = or(_T_6, _T_7)
connect ubtb.io.f0_valid, io.f0_valid
connect ubtb.io.f0_pc, io.f0_pc
connect ubtb.io.f0_mask, io.f0_mask
connect ubtb.io.f1_ghist, io.f1_ghist
connect ubtb.io.f1_lhist, io.f1_lhist
connect ubtb.io.f3_fire, io.f3_fire
node _T_9 = shl(_T_8, 1)
node _T_10 = bits(ubtb.io.f3_meta, 0, 0)
node _T_11 = or(_T_9, _T_10)
connect bim.io.f0_valid, io.f0_valid
connect bim.io.f0_pc, io.f0_pc
connect bim.io.f0_mask, io.f0_mask
connect bim.io.f1_ghist, io.f1_ghist
connect bim.io.f1_lhist, io.f1_lhist
connect bim.io.f3_fire, io.f3_fire
node _T_12 = shl(_T_11, 8)
node _T_13 = bits(bim.io.f3_meta, 7, 0)
node _T_14 = or(_T_12, _T_13)
connect io.f3_meta, _T_14
connect bim.io.update.bits.meta, io.update.bits.meta
connect bim.io.update.bits.target, io.update.bits.target
connect bim.io.update.bits.lhist, io.update.bits.lhist
connect bim.io.update.bits.ghist, io.update.bits.ghist
connect bim.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect bim.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect bim.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect bim.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect bim.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect bim.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect bim.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect bim.io.update.bits.br_mask, io.update.bits.br_mask
connect bim.io.update.bits.pc, io.update.bits.pc
connect bim.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect bim.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect bim.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect bim.io.update.valid, io.update.valid
connect bim.io.update.bits.meta, io.update.bits.meta
node _T_15 = shr(io.update.bits.meta, 8)
connect ubtb.io.update.bits.meta, io.update.bits.meta
connect ubtb.io.update.bits.target, io.update.bits.target
connect ubtb.io.update.bits.lhist, io.update.bits.lhist
connect ubtb.io.update.bits.ghist, io.update.bits.ghist
connect ubtb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect ubtb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect ubtb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect ubtb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect ubtb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect ubtb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect ubtb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect ubtb.io.update.bits.br_mask, io.update.bits.br_mask
connect ubtb.io.update.bits.pc, io.update.bits.pc
connect ubtb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect ubtb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect ubtb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect ubtb.io.update.valid, io.update.valid
connect ubtb.io.update.bits.meta, _T_15
node _T_16 = shr(_T_15, 1)
connect btb.io.update.bits.meta, io.update.bits.meta
connect btb.io.update.bits.target, io.update.bits.target
connect btb.io.update.bits.lhist, io.update.bits.lhist
connect btb.io.update.bits.ghist, io.update.bits.ghist
connect btb.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect btb.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect btb.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect btb.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect btb.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect btb.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect btb.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect btb.io.update.bits.br_mask, io.update.bits.br_mask
connect btb.io.update.bits.pc, io.update.bits.pc
connect btb.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect btb.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect btb.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect btb.io.update.valid, io.update.valid
connect btb.io.update.bits.meta, _T_16
node _T_17 = shr(_T_16, 1)
connect tage.io.update.bits.meta, io.update.bits.meta
connect tage.io.update.bits.target, io.update.bits.target
connect tage.io.update.bits.lhist, io.update.bits.lhist
connect tage.io.update.bits.ghist, io.update.bits.ghist
connect tage.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect tage.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect tage.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect tage.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect tage.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect tage.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect tage.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect tage.io.update.bits.br_mask, io.update.bits.br_mask
connect tage.io.update.bits.pc, io.update.bits.pc
connect tage.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect tage.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect tage.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect tage.io.update.valid, io.update.valid
connect tage.io.update.bits.meta, _T_17
node _T_18 = shr(_T_17, 56)
connect loop.io.update.bits.meta, io.update.bits.meta
connect loop.io.update.bits.target, io.update.bits.target
connect loop.io.update.bits.lhist, io.update.bits.lhist
connect loop.io.update.bits.ghist, io.update.bits.ghist
connect loop.io.update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect loop.io.update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect loop.io.update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect loop.io.update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect loop.io.update.bits.cfi_taken, io.update.bits.cfi_taken
connect loop.io.update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect loop.io.update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect loop.io.update.bits.br_mask, io.update.bits.br_mask
connect loop.io.update.bits.pc, io.update.bits.pc
connect loop.io.update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect loop.io.update.bits.is_repair_update, io.update.bits.is_repair_update
connect loop.io.update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect loop.io.update.valid, io.update.valid
connect loop.io.update.bits.meta, _T_18
node _T_19 = shr(_T_18, 40) | module ComposedBranchPredictorBank_1( // @[composer.scala:14:7]
input clock, // @[composer.scala:14:7]
input reset, // @[composer.scala:14:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire _ubtb_io_resp_f1_0_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_0_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_0_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_1_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_1_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_1_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_2_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_2_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_2_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_3_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_3_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_3_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_0_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_0_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_0_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_1_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_1_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_1_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_2_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_2_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_2_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_3_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_3_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_3_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_0_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_0_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_0_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_1_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_1_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_1_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_2_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_2_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_2_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_3_taken; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_3_is_br; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_3_is_jal; // @[config-mixins.scala:599:26]
wire _ubtb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:599:26]
wire [39:0] _ubtb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:599:26]
wire [119:0] _ubtb_io_f3_meta; // @[config-mixins.scala:599:26]
wire _bim_io_resp_f1_0_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_0_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_0_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_1_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_1_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_1_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_2_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_2_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_2_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_3_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_3_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_3_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_0_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_0_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_0_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_1_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_1_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_1_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_2_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_2_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_2_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_3_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_3_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_3_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_0_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_0_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_0_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_1_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_1_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_1_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_2_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_2_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_2_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_3_taken; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_3_is_br; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_3_is_jal; // @[config-mixins.scala:598:25]
wire _bim_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:598:25]
wire [39:0] _bim_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:598:25]
wire [119:0] _bim_io_f3_meta; // @[config-mixins.scala:598:25]
wire _btb_io_resp_f1_0_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_0_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_0_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_1_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_1_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_1_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_2_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_2_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_2_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_3_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_3_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_3_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_0_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_0_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_0_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_1_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_1_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_1_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_2_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_2_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_2_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_3_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_3_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_3_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_0_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_0_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_0_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_1_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_1_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_1_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_2_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_2_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_2_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_3_taken; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_3_is_br; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_3_is_jal; // @[config-mixins.scala:597:25]
wire _btb_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:597:25]
wire [39:0] _btb_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:597:25]
wire [119:0] _btb_io_f3_meta; // @[config-mixins.scala:597:25]
wire _tage_io_resp_f1_0_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_0_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_0_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_0_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f1_0_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_1_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_1_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_1_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_1_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f1_1_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_2_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_2_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_2_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_2_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f1_2_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_3_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_3_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_3_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f1_3_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f1_3_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_0_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_0_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_0_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_0_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f2_0_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_1_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_1_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_1_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_1_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f2_1_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_2_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_2_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_2_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_2_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f2_2_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_3_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_3_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_3_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f2_3_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f2_3_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_0_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_0_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_0_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_0_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f3_0_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_1_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_1_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_1_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_1_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f3_1_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_2_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_2_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_2_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_2_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f3_2_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_3_taken; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_3_is_br; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_3_is_jal; // @[config-mixins.scala:596:26]
wire _tage_io_resp_f3_3_predicted_pc_valid; // @[config-mixins.scala:596:26]
wire [39:0] _tage_io_resp_f3_3_predicted_pc_bits; // @[config-mixins.scala:596:26]
wire [119:0] _tage_io_f3_meta; // @[config-mixins.scala:596:26]
wire [119:0] _loop_io_f3_meta; // @[config-mixins.scala:595:26]
wire io_f0_valid_0 = io_f0_valid; // @[composer.scala:14:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[composer.scala:14:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[composer.scala:14:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[composer.scala:14:7]
wire io_f3_fire_0 = io_f3_fire; // @[composer.scala:14:7]
wire io_update_valid_0 = io_update_valid; // @[composer.scala:14:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[composer.scala:14:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[composer.scala:14:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[composer.scala:14:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[composer.scala:14:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[composer.scala:14:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[composer.scala:14:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[composer.scala:14:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[composer.scala:14:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[composer.scala:14:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[composer.scala:14:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[composer.scala:14:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[composer.scala:14:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[composer.scala:14:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[composer.scala:14:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits = 40'h0; // @[predictor.scala:140:14]
wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f1_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f2_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_0_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_1_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_2_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_taken = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_br = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_is_jal = 1'h0; // @[predictor.scala:140:14]
wire io_resp_in_0_f3_3_predicted_pc_valid = 1'h0; // @[predictor.scala:140:14]
wire io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f1_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f2_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_0_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_1_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_2_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
wire io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
wire io_resp_f3_3_taken_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
wire io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
wire [119:0] io_f3_meta_0; // @[composer.scala:14:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:149:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
wire [39:0] _s0_pc_T = ~io_f0_pc_0; // @[frontend.scala:147:33]
wire [39:0] _s0_pc_T_1 = {_s0_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}]
wire [39:0] s0_pc = ~_s0_pc_T_1; // @[frontend.scala:147:{31,39}]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
reg [39:0] s2_pc; // @[predictor.scala:179:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:149:35]
reg s1_update_valid; // @[predictor.scala:185:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:185:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:185:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:185:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:185:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:185:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:185:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:185:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:185:30]
reg s1_update_bits_lhist; // @[predictor.scala:185:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:185:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:185:30]
wire [39:0] _s1_update_bits_pc_T = ~io_update_bits_pc_0; // @[frontend.scala:147:33]
wire [39:0] _s1_update_bits_pc_T_1 = {_s1_update_bits_pc_T[39:3], 3'h7}; // @[frontend.scala:147:{33,39}]
wire [39:0] _s1_update_bits_pc_T_2 = ~_s1_update_bits_pc_T_1; // @[frontend.scala:147:{31,39}]
reg [35:0] s1_update_idx; // @[predictor.scala:187:30]
reg s1_update_valid_0; // @[predictor.scala:188:32]
assign io_f3_meta_0 = {14'h0, _loop_io_f3_meta[39:0], _tage_io_f3_meta[55:0], _btb_io_f3_meta[0], _ubtb_io_f3_meta[0], _bim_io_f3_meta[7:0]}; // @[composer.scala:14:7, :31:49, :36:14]
always @(posedge clock) begin // @[composer.scala:14:7]
s1_idx <= s0_idx; // @[frontend.scala:149:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= s0_pc; // @[frontend.scala:147:31]
s2_pc <= s1_pc; // @[predictor.scala:178:22, :179:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:185:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:185:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:185:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:185:30]
s1_update_bits_pc <= _s1_update_bits_pc_T_2; // @[frontend.scala:147:31]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:185:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:185:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:185:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:185:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:185:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:185:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:149:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:188:32]
always @(posedge)
LoopBranchPredictorBank_1 loop ( // @[config-mixins.scala:595:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_tage_io_resp_f1_0_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_0_is_br (_tage_io_resp_f1_0_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_0_is_jal (_tage_io_resp_f1_0_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_1_taken (_tage_io_resp_f1_1_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_1_is_br (_tage_io_resp_f1_1_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_1_is_jal (_tage_io_resp_f1_1_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_2_taken (_tage_io_resp_f1_2_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_2_is_br (_tage_io_resp_f1_2_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_2_is_jal (_tage_io_resp_f1_2_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_3_taken (_tage_io_resp_f1_3_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_3_is_br (_tage_io_resp_f1_3_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_3_is_jal (_tage_io_resp_f1_3_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_0_taken (_tage_io_resp_f2_0_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_0_is_br (_tage_io_resp_f2_0_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_0_is_jal (_tage_io_resp_f2_0_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_1_taken (_tage_io_resp_f2_1_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_1_is_br (_tage_io_resp_f2_1_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_1_is_jal (_tage_io_resp_f2_1_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_2_taken (_tage_io_resp_f2_2_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_2_is_br (_tage_io_resp_f2_2_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_2_is_jal (_tage_io_resp_f2_2_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_3_taken (_tage_io_resp_f2_3_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_3_is_br (_tage_io_resp_f2_3_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_3_is_jal (_tage_io_resp_f2_3_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_0_taken (_tage_io_resp_f3_0_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_0_is_br (_tage_io_resp_f3_0_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_0_is_jal (_tage_io_resp_f3_0_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_1_taken (_tage_io_resp_f3_1_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_1_is_br (_tage_io_resp_f3_1_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_1_is_jal (_tage_io_resp_f3_1_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_2_taken (_tage_io_resp_f3_2_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_2_is_br (_tage_io_resp_f3_2_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_2_is_jal (_tage_io_resp_f3_2_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_3_taken (_tage_io_resp_f3_3_taken), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_3_is_br (_tage_io_resp_f3_3_is_br), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_3_is_jal (_tage_io_resp_f3_3_is_jal), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:596:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:596:26]
.io_resp_f1_0_taken (io_resp_f1_0_taken_0),
.io_resp_f1_0_is_br (io_resp_f1_0_is_br_0),
.io_resp_f1_0_is_jal (io_resp_f1_0_is_jal_0),
.io_resp_f1_0_predicted_pc_valid (io_resp_f1_0_predicted_pc_valid_0),
.io_resp_f1_0_predicted_pc_bits (io_resp_f1_0_predicted_pc_bits_0),
.io_resp_f1_1_taken (io_resp_f1_1_taken_0),
.io_resp_f1_1_is_br (io_resp_f1_1_is_br_0),
.io_resp_f1_1_is_jal (io_resp_f1_1_is_jal_0),
.io_resp_f1_1_predicted_pc_valid (io_resp_f1_1_predicted_pc_valid_0),
.io_resp_f1_1_predicted_pc_bits (io_resp_f1_1_predicted_pc_bits_0),
.io_resp_f1_2_taken (io_resp_f1_2_taken_0),
.io_resp_f1_2_is_br (io_resp_f1_2_is_br_0),
.io_resp_f1_2_is_jal (io_resp_f1_2_is_jal_0),
.io_resp_f1_2_predicted_pc_valid (io_resp_f1_2_predicted_pc_valid_0),
.io_resp_f1_2_predicted_pc_bits (io_resp_f1_2_predicted_pc_bits_0),
.io_resp_f1_3_taken (io_resp_f1_3_taken_0),
.io_resp_f1_3_is_br (io_resp_f1_3_is_br_0),
.io_resp_f1_3_is_jal (io_resp_f1_3_is_jal_0),
.io_resp_f1_3_predicted_pc_valid (io_resp_f1_3_predicted_pc_valid_0),
.io_resp_f1_3_predicted_pc_bits (io_resp_f1_3_predicted_pc_bits_0),
.io_resp_f2_0_taken (io_resp_f2_0_taken_0),
.io_resp_f2_0_is_br (io_resp_f2_0_is_br_0),
.io_resp_f2_0_is_jal (io_resp_f2_0_is_jal_0),
.io_resp_f2_0_predicted_pc_valid (io_resp_f2_0_predicted_pc_valid_0),
.io_resp_f2_0_predicted_pc_bits (io_resp_f2_0_predicted_pc_bits_0),
.io_resp_f2_1_taken (io_resp_f2_1_taken_0),
.io_resp_f2_1_is_br (io_resp_f2_1_is_br_0),
.io_resp_f2_1_is_jal (io_resp_f2_1_is_jal_0),
.io_resp_f2_1_predicted_pc_valid (io_resp_f2_1_predicted_pc_valid_0),
.io_resp_f2_1_predicted_pc_bits (io_resp_f2_1_predicted_pc_bits_0),
.io_resp_f2_2_taken (io_resp_f2_2_taken_0),
.io_resp_f2_2_is_br (io_resp_f2_2_is_br_0),
.io_resp_f2_2_is_jal (io_resp_f2_2_is_jal_0),
.io_resp_f2_2_predicted_pc_valid (io_resp_f2_2_predicted_pc_valid_0),
.io_resp_f2_2_predicted_pc_bits (io_resp_f2_2_predicted_pc_bits_0),
.io_resp_f2_3_taken (io_resp_f2_3_taken_0),
.io_resp_f2_3_is_br (io_resp_f2_3_is_br_0),
.io_resp_f2_3_is_jal (io_resp_f2_3_is_jal_0),
.io_resp_f2_3_predicted_pc_valid (io_resp_f2_3_predicted_pc_valid_0),
.io_resp_f2_3_predicted_pc_bits (io_resp_f2_3_predicted_pc_bits_0),
.io_resp_f3_0_taken (io_resp_f3_0_taken_0),
.io_resp_f3_0_is_br (io_resp_f3_0_is_br_0),
.io_resp_f3_0_is_jal (io_resp_f3_0_is_jal_0),
.io_resp_f3_0_predicted_pc_valid (io_resp_f3_0_predicted_pc_valid_0),
.io_resp_f3_0_predicted_pc_bits (io_resp_f3_0_predicted_pc_bits_0),
.io_resp_f3_1_taken (io_resp_f3_1_taken_0),
.io_resp_f3_1_is_br (io_resp_f3_1_is_br_0),
.io_resp_f3_1_is_jal (io_resp_f3_1_is_jal_0),
.io_resp_f3_1_predicted_pc_valid (io_resp_f3_1_predicted_pc_valid_0),
.io_resp_f3_1_predicted_pc_bits (io_resp_f3_1_predicted_pc_bits_0),
.io_resp_f3_2_taken (io_resp_f3_2_taken_0),
.io_resp_f3_2_is_br (io_resp_f3_2_is_br_0),
.io_resp_f3_2_is_jal (io_resp_f3_2_is_jal_0),
.io_resp_f3_2_predicted_pc_valid (io_resp_f3_2_predicted_pc_valid_0),
.io_resp_f3_2_predicted_pc_bits (io_resp_f3_2_predicted_pc_bits_0),
.io_resp_f3_3_taken (io_resp_f3_3_taken_0),
.io_resp_f3_3_is_br (io_resp_f3_3_is_br_0),
.io_resp_f3_3_is_jal (io_resp_f3_3_is_jal_0),
.io_resp_f3_3_predicted_pc_valid (io_resp_f3_3_predicted_pc_valid_0),
.io_resp_f3_3_predicted_pc_bits (io_resp_f3_3_predicted_pc_bits_0),
.io_f3_meta (_loop_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({66'h0, io_update_bits_meta_0[119:66]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:595:26]
TageBranchPredictorBank_1 tage ( // @[config-mixins.scala:596:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_btb_io_resp_f1_0_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_0_is_br (_btb_io_resp_f1_0_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_0_is_jal (_btb_io_resp_f1_0_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_1_taken (_btb_io_resp_f1_1_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_1_is_br (_btb_io_resp_f1_1_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_1_is_jal (_btb_io_resp_f1_1_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_2_taken (_btb_io_resp_f1_2_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_2_is_br (_btb_io_resp_f1_2_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_2_is_jal (_btb_io_resp_f1_2_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_3_taken (_btb_io_resp_f1_3_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_3_is_br (_btb_io_resp_f1_3_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_3_is_jal (_btb_io_resp_f1_3_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_0_taken (_btb_io_resp_f2_0_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_0_is_br (_btb_io_resp_f2_0_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_0_is_jal (_btb_io_resp_f2_0_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_1_taken (_btb_io_resp_f2_1_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_1_is_br (_btb_io_resp_f2_1_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_1_is_jal (_btb_io_resp_f2_1_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_2_taken (_btb_io_resp_f2_2_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_2_is_br (_btb_io_resp_f2_2_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_2_is_jal (_btb_io_resp_f2_2_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_3_taken (_btb_io_resp_f2_3_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_3_is_br (_btb_io_resp_f2_3_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_3_is_jal (_btb_io_resp_f2_3_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_0_taken (_btb_io_resp_f3_0_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_0_is_br (_btb_io_resp_f3_0_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_0_is_jal (_btb_io_resp_f3_0_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_1_taken (_btb_io_resp_f3_1_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_1_is_br (_btb_io_resp_f3_1_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_1_is_jal (_btb_io_resp_f3_1_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_2_taken (_btb_io_resp_f3_2_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_2_is_br (_btb_io_resp_f3_2_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_2_is_jal (_btb_io_resp_f3_2_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_3_taken (_btb_io_resp_f3_3_taken), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_3_is_br (_btb_io_resp_f3_3_is_br), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_3_is_jal (_btb_io_resp_f3_3_is_jal), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:597:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:597:25]
.io_resp_f1_0_taken (_tage_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_tage_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_tage_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_tage_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_tage_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_tage_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_tage_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_tage_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_tage_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_tage_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_tage_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_tage_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_tage_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_tage_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_tage_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_tage_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_tage_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_tage_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_tage_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_tage_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_tage_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_tage_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_tage_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_tage_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_tage_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_tage_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_tage_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_tage_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_tage_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_tage_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_tage_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_tage_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_tage_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_tage_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_tage_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_tage_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_tage_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_tage_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_tage_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_tage_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_tage_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_tage_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_tage_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_tage_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_tage_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_tage_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_tage_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_tage_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_tage_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_tage_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_tage_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_tage_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_tage_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_tage_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_tage_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_tage_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_tage_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_tage_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_tage_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_tage_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_tage_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({10'h0, io_update_bits_meta_0[119:10]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:596:26]
BTBBranchPredictorBank_1 btb ( // @[config-mixins.scala:597:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_bim_io_resp_f1_0_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_0_is_br (_bim_io_resp_f1_0_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_0_is_jal (_bim_io_resp_f1_0_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_1_taken (_bim_io_resp_f1_1_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_1_is_br (_bim_io_resp_f1_1_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_1_is_jal (_bim_io_resp_f1_1_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_2_taken (_bim_io_resp_f1_2_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_2_is_br (_bim_io_resp_f1_2_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_2_is_jal (_bim_io_resp_f1_2_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_3_taken (_bim_io_resp_f1_3_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_3_is_br (_bim_io_resp_f1_3_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_3_is_jal (_bim_io_resp_f1_3_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_0_taken (_bim_io_resp_f2_0_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_0_is_br (_bim_io_resp_f2_0_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_0_is_jal (_bim_io_resp_f2_0_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_1_taken (_bim_io_resp_f2_1_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_1_is_br (_bim_io_resp_f2_1_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_1_is_jal (_bim_io_resp_f2_1_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_2_taken (_bim_io_resp_f2_2_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_2_is_br (_bim_io_resp_f2_2_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_2_is_jal (_bim_io_resp_f2_2_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_3_taken (_bim_io_resp_f2_3_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_3_is_br (_bim_io_resp_f2_3_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_3_is_jal (_bim_io_resp_f2_3_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_0_taken (_bim_io_resp_f3_0_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_0_is_br (_bim_io_resp_f3_0_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_0_is_jal (_bim_io_resp_f3_0_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_1_taken (_bim_io_resp_f3_1_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_1_is_br (_bim_io_resp_f3_1_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_1_is_jal (_bim_io_resp_f3_1_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_2_taken (_bim_io_resp_f3_2_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_2_is_br (_bim_io_resp_f3_2_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_2_is_jal (_bim_io_resp_f3_2_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_3_taken (_bim_io_resp_f3_3_taken), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_3_is_br (_bim_io_resp_f3_3_is_br), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_3_is_jal (_bim_io_resp_f3_3_is_jal), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:598:25]
.io_resp_in_0_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:598:25]
.io_resp_f1_0_taken (_btb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_btb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_btb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_btb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_btb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_btb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_btb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_btb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_btb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_btb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_btb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_btb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_btb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_btb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_btb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_btb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_btb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_btb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_btb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_btb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_btb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_btb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_btb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_btb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_btb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_btb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_btb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_btb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_btb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_btb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_btb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_btb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_btb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_btb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_btb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_btb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_btb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_btb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_btb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_btb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_btb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_btb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_btb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_btb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_btb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_btb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_btb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_btb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_btb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_btb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_btb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_btb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_btb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_btb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_btb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_btb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_btb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_btb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_btb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_btb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_btb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({9'h0, io_update_bits_meta_0[119:9]}) // @[composer.scala:14:7, :42:27, :43:31]
); // @[config-mixins.scala:597:25]
BIMBranchPredictorBank_1 bim ( // @[config-mixins.scala:598:25]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_in_0_f1_0_taken (_ubtb_io_resp_f1_0_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_0_is_br (_ubtb_io_resp_f1_0_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_1_taken (_ubtb_io_resp_f1_1_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_1_is_br (_ubtb_io_resp_f1_1_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_2_taken (_ubtb_io_resp_f1_2_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_2_is_br (_ubtb_io_resp_f1_2_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_3_taken (_ubtb_io_resp_f1_3_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_3_is_br (_ubtb_io_resp_f1_3_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_0_taken (_ubtb_io_resp_f2_0_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_0_is_br (_ubtb_io_resp_f2_0_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_1_taken (_ubtb_io_resp_f2_1_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_1_is_br (_ubtb_io_resp_f2_1_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_2_taken (_ubtb_io_resp_f2_2_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_2_is_br (_ubtb_io_resp_f2_2_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_3_taken (_ubtb_io_resp_f2_3_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_3_is_br (_ubtb_io_resp_f2_3_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_0_taken (_ubtb_io_resp_f3_0_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_0_is_br (_ubtb_io_resp_f3_0_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_1_taken (_ubtb_io_resp_f3_1_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_1_is_br (_ubtb_io_resp_f3_1_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_2_taken (_ubtb_io_resp_f3_2_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_2_is_br (_ubtb_io_resp_f3_2_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_3_taken (_ubtb_io_resp_f3_3_taken), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_3_is_br (_ubtb_io_resp_f3_3_is_br), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid), // @[config-mixins.scala:599:26]
.io_resp_in_0_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits), // @[config-mixins.scala:599:26]
.io_resp_f1_0_taken (_bim_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_bim_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_bim_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_bim_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_bim_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_bim_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_bim_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_bim_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_bim_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_bim_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_bim_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_bim_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_bim_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_bim_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_bim_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_bim_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_bim_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_bim_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_bim_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_bim_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_bim_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_bim_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_bim_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_bim_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_bim_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_bim_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_bim_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_bim_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_bim_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_bim_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_bim_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_bim_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_bim_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_bim_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_bim_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_bim_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_bim_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_bim_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_bim_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_bim_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_bim_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_bim_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_bim_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_bim_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_bim_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_bim_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_bim_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_bim_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_bim_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_bim_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_bim_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_bim_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_bim_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_bim_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_bim_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_bim_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_bim_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_bim_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_bim_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_bim_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_bim_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta (io_update_bits_meta_0) // @[composer.scala:14:7]
); // @[config-mixins.scala:598:25]
FA2MicroBTBBranchPredictorBank_1 ubtb ( // @[config-mixins.scala:599:26]
.clock (clock),
.reset (reset),
.io_f0_valid (io_f0_valid_0), // @[composer.scala:14:7]
.io_f0_pc (io_f0_pc_0), // @[composer.scala:14:7]
.io_f0_mask (io_f0_mask_0), // @[composer.scala:14:7]
.io_f1_ghist (io_f1_ghist_0), // @[composer.scala:14:7]
.io_resp_f1_0_taken (_ubtb_io_resp_f1_0_taken),
.io_resp_f1_0_is_br (_ubtb_io_resp_f1_0_is_br),
.io_resp_f1_0_is_jal (_ubtb_io_resp_f1_0_is_jal),
.io_resp_f1_0_predicted_pc_valid (_ubtb_io_resp_f1_0_predicted_pc_valid),
.io_resp_f1_0_predicted_pc_bits (_ubtb_io_resp_f1_0_predicted_pc_bits),
.io_resp_f1_1_taken (_ubtb_io_resp_f1_1_taken),
.io_resp_f1_1_is_br (_ubtb_io_resp_f1_1_is_br),
.io_resp_f1_1_is_jal (_ubtb_io_resp_f1_1_is_jal),
.io_resp_f1_1_predicted_pc_valid (_ubtb_io_resp_f1_1_predicted_pc_valid),
.io_resp_f1_1_predicted_pc_bits (_ubtb_io_resp_f1_1_predicted_pc_bits),
.io_resp_f1_2_taken (_ubtb_io_resp_f1_2_taken),
.io_resp_f1_2_is_br (_ubtb_io_resp_f1_2_is_br),
.io_resp_f1_2_is_jal (_ubtb_io_resp_f1_2_is_jal),
.io_resp_f1_2_predicted_pc_valid (_ubtb_io_resp_f1_2_predicted_pc_valid),
.io_resp_f1_2_predicted_pc_bits (_ubtb_io_resp_f1_2_predicted_pc_bits),
.io_resp_f1_3_taken (_ubtb_io_resp_f1_3_taken),
.io_resp_f1_3_is_br (_ubtb_io_resp_f1_3_is_br),
.io_resp_f1_3_is_jal (_ubtb_io_resp_f1_3_is_jal),
.io_resp_f1_3_predicted_pc_valid (_ubtb_io_resp_f1_3_predicted_pc_valid),
.io_resp_f1_3_predicted_pc_bits (_ubtb_io_resp_f1_3_predicted_pc_bits),
.io_resp_f2_0_taken (_ubtb_io_resp_f2_0_taken),
.io_resp_f2_0_is_br (_ubtb_io_resp_f2_0_is_br),
.io_resp_f2_0_is_jal (_ubtb_io_resp_f2_0_is_jal),
.io_resp_f2_0_predicted_pc_valid (_ubtb_io_resp_f2_0_predicted_pc_valid),
.io_resp_f2_0_predicted_pc_bits (_ubtb_io_resp_f2_0_predicted_pc_bits),
.io_resp_f2_1_taken (_ubtb_io_resp_f2_1_taken),
.io_resp_f2_1_is_br (_ubtb_io_resp_f2_1_is_br),
.io_resp_f2_1_is_jal (_ubtb_io_resp_f2_1_is_jal),
.io_resp_f2_1_predicted_pc_valid (_ubtb_io_resp_f2_1_predicted_pc_valid),
.io_resp_f2_1_predicted_pc_bits (_ubtb_io_resp_f2_1_predicted_pc_bits),
.io_resp_f2_2_taken (_ubtb_io_resp_f2_2_taken),
.io_resp_f2_2_is_br (_ubtb_io_resp_f2_2_is_br),
.io_resp_f2_2_is_jal (_ubtb_io_resp_f2_2_is_jal),
.io_resp_f2_2_predicted_pc_valid (_ubtb_io_resp_f2_2_predicted_pc_valid),
.io_resp_f2_2_predicted_pc_bits (_ubtb_io_resp_f2_2_predicted_pc_bits),
.io_resp_f2_3_taken (_ubtb_io_resp_f2_3_taken),
.io_resp_f2_3_is_br (_ubtb_io_resp_f2_3_is_br),
.io_resp_f2_3_is_jal (_ubtb_io_resp_f2_3_is_jal),
.io_resp_f2_3_predicted_pc_valid (_ubtb_io_resp_f2_3_predicted_pc_valid),
.io_resp_f2_3_predicted_pc_bits (_ubtb_io_resp_f2_3_predicted_pc_bits),
.io_resp_f3_0_taken (_ubtb_io_resp_f3_0_taken),
.io_resp_f3_0_is_br (_ubtb_io_resp_f3_0_is_br),
.io_resp_f3_0_is_jal (_ubtb_io_resp_f3_0_is_jal),
.io_resp_f3_0_predicted_pc_valid (_ubtb_io_resp_f3_0_predicted_pc_valid),
.io_resp_f3_0_predicted_pc_bits (_ubtb_io_resp_f3_0_predicted_pc_bits),
.io_resp_f3_1_taken (_ubtb_io_resp_f3_1_taken),
.io_resp_f3_1_is_br (_ubtb_io_resp_f3_1_is_br),
.io_resp_f3_1_is_jal (_ubtb_io_resp_f3_1_is_jal),
.io_resp_f3_1_predicted_pc_valid (_ubtb_io_resp_f3_1_predicted_pc_valid),
.io_resp_f3_1_predicted_pc_bits (_ubtb_io_resp_f3_1_predicted_pc_bits),
.io_resp_f3_2_taken (_ubtb_io_resp_f3_2_taken),
.io_resp_f3_2_is_br (_ubtb_io_resp_f3_2_is_br),
.io_resp_f3_2_is_jal (_ubtb_io_resp_f3_2_is_jal),
.io_resp_f3_2_predicted_pc_valid (_ubtb_io_resp_f3_2_predicted_pc_valid),
.io_resp_f3_2_predicted_pc_bits (_ubtb_io_resp_f3_2_predicted_pc_bits),
.io_resp_f3_3_taken (_ubtb_io_resp_f3_3_taken),
.io_resp_f3_3_is_br (_ubtb_io_resp_f3_3_is_br),
.io_resp_f3_3_is_jal (_ubtb_io_resp_f3_3_is_jal),
.io_resp_f3_3_predicted_pc_valid (_ubtb_io_resp_f3_3_predicted_pc_valid),
.io_resp_f3_3_predicted_pc_bits (_ubtb_io_resp_f3_3_predicted_pc_bits),
.io_f3_meta (_ubtb_io_f3_meta),
.io_f3_fire (io_f3_fire_0), // @[composer.scala:14:7]
.io_update_valid (io_update_valid_0), // @[composer.scala:14:7]
.io_update_bits_is_mispredict_update (io_update_bits_is_mispredict_update_0), // @[composer.scala:14:7]
.io_update_bits_is_repair_update (io_update_bits_is_repair_update_0), // @[composer.scala:14:7]
.io_update_bits_btb_mispredicts (io_update_bits_btb_mispredicts_0), // @[composer.scala:14:7]
.io_update_bits_pc (io_update_bits_pc_0), // @[composer.scala:14:7]
.io_update_bits_br_mask (io_update_bits_br_mask_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_valid (io_update_bits_cfi_idx_valid_0), // @[composer.scala:14:7]
.io_update_bits_cfi_idx_bits (io_update_bits_cfi_idx_bits_0), // @[composer.scala:14:7]
.io_update_bits_cfi_taken (io_update_bits_cfi_taken_0), // @[composer.scala:14:7]
.io_update_bits_cfi_mispredicted (io_update_bits_cfi_mispredicted_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_br (io_update_bits_cfi_is_br_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jal (io_update_bits_cfi_is_jal_0), // @[composer.scala:14:7]
.io_update_bits_cfi_is_jalr (io_update_bits_cfi_is_jalr_0), // @[composer.scala:14:7]
.io_update_bits_ghist (io_update_bits_ghist_0), // @[composer.scala:14:7]
.io_update_bits_lhist (io_update_bits_lhist_0), // @[composer.scala:14:7]
.io_update_bits_target (io_update_bits_target_0), // @[composer.scala:14:7]
.io_update_bits_meta ({8'h0, io_update_bits_meta_0[119:8]}) // @[composer.scala:14:7, :31:22, :42:27, :43:31]
); // @[config-mixins.scala:599:26]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[composer.scala:14:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[composer.scala:14:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[composer.scala:14:7]
assign io_f3_meta = io_f3_meta_0; // @[composer.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_5 :
input clock : Clock
input reset : Reset
output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>}
node default = gt(io.prv, UInt<1>(0h1))
wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect _pmp0_WIRE.mask, UInt<32>(0h0)
connect _pmp0_WIRE.addr, UInt<30>(0h0)
connect _pmp0_WIRE.cfg.r, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.w, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.x, UInt<1>(0h0)
connect _pmp0_WIRE.cfg.a, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.res, UInt<2>(0h0)
connect _pmp0_WIRE.cfg.l, UInt<1>(0h0)
wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp0, _pmp0_WIRE
connect pmp0.cfg.r, default
connect pmp0.cfg.w, default
connect pmp0.cfg.x, default
node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1)
node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0)
node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1)
node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2)
node _res_hit_msbMatch_T = shr(io.addr, 3)
node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1)
node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3))
node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3)
node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3)
node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3)
node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5)
node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6)
node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8)
node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0))
node _res_hit_lsbMatch_T = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1)
node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3))
node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3)
node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0)
node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0)
node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5)
node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6)
node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8)
node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0))
node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch)
node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0)
node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0)
node _res_hit_T_5 = not(_res_hit_T_4)
node _res_hit_msbsLess_T = shr(io.addr, 3)
node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1)
node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3))
node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3)
node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3)
node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5)
node _res_hit_msbsEqual_T = shr(io.addr, 3)
node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1)
node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3))
node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3)
node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3)
node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5)
node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0))
node _res_hit_lsbsLess_T = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5)
node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2)
node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3))
node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4)
node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0)
node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6)
node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess)
node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6)
node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0))
node _res_hit_msbsLess_T_6 = shr(io.addr, 3)
node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7)
node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3))
node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9)
node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3)
node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11)
node _res_hit_msbsEqual_T_7 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2)
node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8)
node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3))
node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10)
node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3)
node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12)
node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0))
node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0))
node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2)
node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9)
node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3))
node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11)
node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0)
node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13)
node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1)
node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9)
node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10)
node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11)
node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12)
node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0))
node res_ignore = and(default, _res_ignore_T)
node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0)
node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1)
node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1)
node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3)
node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3)
node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5)
node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8)
node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10)
node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0)
node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13)
node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14)
node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16)
node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1)
node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3)
node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3)
node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5)
node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2)
node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8)
node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10)
node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0)
node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask)
node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14)
node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0))
node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16)
node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound)
node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0)
node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T)
node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1)
node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0))
node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1)
node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned)
node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0))
node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1))
node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r)
node _res_T_6 = eq(_res_T_5, UInt<1>(0h0))
node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r)
node _res_T_8 = eq(_res_T_7, UInt<1>(0h1))
node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r)
node _res_T_10 = eq(_res_T_9, UInt<2>(0h3))
node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r)
node _res_T_12 = eq(_res_T_11, UInt<3>(0h4))
node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r)
node _res_T_14 = eq(_res_T_13, UInt<3>(0h5))
node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w)
node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r)
node _res_T_16 = eq(_res_T_15, UInt<3>(0h7))
node _res_T_17 = eq(res_ignore, UInt<1>(0h0))
node _res_T_18 = and(_res_T_17, res_hit)
node _res_T_19 = and(_res_T_18, res_aligned)
node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_21 = and(_res_T_19, _res_T_20)
node _res_T_22 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_23 = and(_res_T_22, res_aligned)
node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1))
node _res_T_25 = and(_res_T_23, _res_T_24)
node _res_T_26 = eq(res_ignore, UInt<1>(0h0))
node _res_T_27 = and(_res_T_26, res_hit)
node _res_T_28 = and(_res_T_27, res_aligned)
node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_30 = and(_res_T_28, _res_T_29)
node _res_T_31 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_32 = and(_res_T_31, res_aligned)
node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2))
node _res_T_34 = and(_res_T_32, _res_T_33)
node _res_T_35 = eq(res_ignore, UInt<1>(0h0))
node _res_T_36 = and(_res_T_35, res_hit)
node _res_T_37 = and(_res_T_36, res_aligned)
node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_39 = and(_res_T_37, _res_T_38)
node _res_T_40 = and(io.pmp[7].cfg.l, res_hit)
node _res_T_41 = and(_res_T_40, res_aligned)
node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3))
node _res_T_43 = and(_res_T_41, _res_T_42)
wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur, io.pmp[7]
node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore)
node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T)
connect res_cur.cfg.r, _res_cur_cfg_r_T_1
node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore)
node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T)
connect res_cur.cfg.w, _res_cur_cfg_w_T_1
node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore)
node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T)
connect res_cur.cfg.x, _res_cur_cfg_x_T_1
node _res_T_44 = mux(res_hit, res_cur, pmp0)
node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1)
node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0)
node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4)
node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5)
node _res_hit_msbMatch_T_10 = shr(io.addr, 3)
node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11)
node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3))
node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13)
node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3)
node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3)
node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15)
node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16)
node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18)
node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0))
node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11)
node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3))
node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13)
node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0)
node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0)
node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15)
node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16)
node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18)
node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0))
node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1)
node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0)
node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0)
node _res_hit_T_18 = not(_res_hit_T_17)
node _res_hit_msbsLess_T_12 = shr(io.addr, 3)
node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13)
node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3))
node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15)
node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3)
node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17)
node _res_hit_msbsEqual_T_14 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15)
node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3))
node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17)
node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3)
node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19)
node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0))
node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18)
node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16)
node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3))
node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18)
node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0)
node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20)
node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2)
node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19)
node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0))
node _res_hit_msbsLess_T_18 = shr(io.addr, 3)
node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19)
node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3))
node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21)
node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3)
node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23)
node _res_hit_msbsEqual_T_21 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2)
node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22)
node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3))
node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24)
node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3)
node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26)
node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0))
node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0))
node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2)
node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23)
node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3))
node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25)
node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0)
node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27)
node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3)
node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22)
node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23)
node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24)
node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25)
node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0))
node res_ignore_1 = and(default, _res_ignore_T_1)
node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0)
node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3)
node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18)
node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20)
node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3)
node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22)
node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25)
node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27)
node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0)
node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30)
node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31)
node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33)
node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18)
node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20)
node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3)
node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22)
node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2)
node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25)
node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27)
node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0)
node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1)
node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31)
node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33)
node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1)
node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0)
node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3)
node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4)
node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0))
node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1)
node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1)
node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0))
node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1))
node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r)
node _res_T_51 = eq(_res_T_50, UInt<1>(0h0))
node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r)
node _res_T_53 = eq(_res_T_52, UInt<1>(0h1))
node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r)
node _res_T_55 = eq(_res_T_54, UInt<2>(0h3))
node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r)
node _res_T_57 = eq(_res_T_56, UInt<3>(0h4))
node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r)
node _res_T_59 = eq(_res_T_58, UInt<3>(0h5))
node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w)
node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r)
node _res_T_61 = eq(_res_T_60, UInt<3>(0h7))
node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_63 = and(_res_T_62, res_hit_1)
node _res_T_64 = and(_res_T_63, res_aligned_1)
node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_66 = and(_res_T_64, _res_T_65)
node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_68 = and(_res_T_67, res_aligned_1)
node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1))
node _res_T_70 = and(_res_T_68, _res_T_69)
node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_72 = and(_res_T_71, res_hit_1)
node _res_T_73 = and(_res_T_72, res_aligned_1)
node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_75 = and(_res_T_73, _res_T_74)
node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_77 = and(_res_T_76, res_aligned_1)
node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2))
node _res_T_79 = and(_res_T_77, _res_T_78)
node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0))
node _res_T_81 = and(_res_T_80, res_hit_1)
node _res_T_82 = and(_res_T_81, res_aligned_1)
node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_84 = and(_res_T_82, _res_T_83)
node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1)
node _res_T_86 = and(_res_T_85, res_aligned_1)
node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3))
node _res_T_88 = and(_res_T_86, _res_T_87)
wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_1, io.pmp[6]
node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1)
node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2)
connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3
node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1)
node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2)
connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3
node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1)
node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2)
connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3
node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44)
node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1)
node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0)
node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7)
node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8)
node _res_hit_msbMatch_T_20 = shr(io.addr, 3)
node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21)
node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3))
node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23)
node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3)
node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3)
node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25)
node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26)
node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28)
node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0))
node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21)
node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3))
node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23)
node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0)
node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0)
node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25)
node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26)
node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28)
node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0))
node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2)
node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0)
node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0)
node _res_hit_T_31 = not(_res_hit_T_30)
node _res_hit_msbsLess_T_24 = shr(io.addr, 3)
node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25)
node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3))
node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27)
node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3)
node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29)
node _res_hit_msbsEqual_T_28 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29)
node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3))
node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31)
node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3)
node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33)
node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0))
node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31)
node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30)
node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3))
node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32)
node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0)
node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34)
node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4)
node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32)
node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0))
node _res_hit_msbsLess_T_30 = shr(io.addr, 3)
node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31)
node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3))
node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33)
node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3)
node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35)
node _res_hit_msbsEqual_T_35 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2)
node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36)
node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3))
node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38)
node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3)
node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40)
node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0))
node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0))
node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2)
node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37)
node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3))
node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39)
node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0)
node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41)
node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5)
node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35)
node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36)
node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37)
node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38)
node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0))
node res_ignore_2 = and(default, _res_ignore_T_2)
node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0)
node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5)
node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35)
node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37)
node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3)
node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39)
node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42)
node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44)
node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0)
node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47)
node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48)
node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50)
node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35)
node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37)
node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3)
node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39)
node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2)
node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42)
node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44)
node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0)
node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2)
node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48)
node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50)
node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2)
node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0)
node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6)
node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7)
node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0))
node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1)
node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2)
node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0))
node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1))
node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r)
node _res_T_96 = eq(_res_T_95, UInt<1>(0h0))
node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r)
node _res_T_98 = eq(_res_T_97, UInt<1>(0h1))
node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r)
node _res_T_100 = eq(_res_T_99, UInt<2>(0h3))
node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r)
node _res_T_102 = eq(_res_T_101, UInt<3>(0h4))
node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r)
node _res_T_104 = eq(_res_T_103, UInt<3>(0h5))
node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w)
node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r)
node _res_T_106 = eq(_res_T_105, UInt<3>(0h7))
node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_108 = and(_res_T_107, res_hit_2)
node _res_T_109 = and(_res_T_108, res_aligned_2)
node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_111 = and(_res_T_109, _res_T_110)
node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_113 = and(_res_T_112, res_aligned_2)
node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1))
node _res_T_115 = and(_res_T_113, _res_T_114)
node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_117 = and(_res_T_116, res_hit_2)
node _res_T_118 = and(_res_T_117, res_aligned_2)
node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_120 = and(_res_T_118, _res_T_119)
node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_122 = and(_res_T_121, res_aligned_2)
node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2))
node _res_T_124 = and(_res_T_122, _res_T_123)
node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0))
node _res_T_126 = and(_res_T_125, res_hit_2)
node _res_T_127 = and(_res_T_126, res_aligned_2)
node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_129 = and(_res_T_127, _res_T_128)
node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2)
node _res_T_131 = and(_res_T_130, res_aligned_2)
node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3))
node _res_T_133 = and(_res_T_131, _res_T_132)
wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_2, io.pmp[5]
node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2)
node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4)
connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5
node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2)
node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4)
connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5
node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2)
node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4)
connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5
node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89)
node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1)
node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0)
node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10)
node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11)
node _res_hit_msbMatch_T_30 = shr(io.addr, 3)
node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31)
node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3))
node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33)
node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3)
node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3)
node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35)
node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36)
node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38)
node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0))
node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31)
node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3))
node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33)
node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0)
node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0)
node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35)
node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36)
node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38)
node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0))
node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3)
node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0)
node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0)
node _res_hit_T_44 = not(_res_hit_T_43)
node _res_hit_msbsLess_T_36 = shr(io.addr, 3)
node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37)
node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3))
node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39)
node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3)
node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41)
node _res_hit_msbsEqual_T_42 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43)
node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3))
node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45)
node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3)
node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47)
node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0))
node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44)
node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44)
node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3))
node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46)
node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0)
node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48)
node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6)
node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45)
node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0))
node _res_hit_msbsLess_T_42 = shr(io.addr, 3)
node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43)
node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3))
node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45)
node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3)
node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47)
node _res_hit_msbsEqual_T_49 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2)
node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50)
node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3))
node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52)
node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3)
node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54)
node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0))
node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0))
node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2)
node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51)
node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3))
node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53)
node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0)
node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55)
node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7)
node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48)
node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49)
node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50)
node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51)
node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0))
node res_ignore_3 = and(default, _res_ignore_T_3)
node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0)
node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7)
node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52)
node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54)
node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3)
node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56)
node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59)
node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61)
node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0)
node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64)
node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65)
node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67)
node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52)
node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54)
node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3)
node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56)
node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2)
node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59)
node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61)
node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0)
node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3)
node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65)
node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67)
node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3)
node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0)
node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9)
node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10)
node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0))
node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1)
node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3)
node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0))
node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1))
node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r)
node _res_T_141 = eq(_res_T_140, UInt<1>(0h0))
node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r)
node _res_T_143 = eq(_res_T_142, UInt<1>(0h1))
node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r)
node _res_T_145 = eq(_res_T_144, UInt<2>(0h3))
node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r)
node _res_T_147 = eq(_res_T_146, UInt<3>(0h4))
node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r)
node _res_T_149 = eq(_res_T_148, UInt<3>(0h5))
node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w)
node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r)
node _res_T_151 = eq(_res_T_150, UInt<3>(0h7))
node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_153 = and(_res_T_152, res_hit_3)
node _res_T_154 = and(_res_T_153, res_aligned_3)
node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_156 = and(_res_T_154, _res_T_155)
node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_158 = and(_res_T_157, res_aligned_3)
node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1))
node _res_T_160 = and(_res_T_158, _res_T_159)
node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_162 = and(_res_T_161, res_hit_3)
node _res_T_163 = and(_res_T_162, res_aligned_3)
node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_165 = and(_res_T_163, _res_T_164)
node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_167 = and(_res_T_166, res_aligned_3)
node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2))
node _res_T_169 = and(_res_T_167, _res_T_168)
node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0))
node _res_T_171 = and(_res_T_170, res_hit_3)
node _res_T_172 = and(_res_T_171, res_aligned_3)
node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_174 = and(_res_T_172, _res_T_173)
node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3)
node _res_T_176 = and(_res_T_175, res_aligned_3)
node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3))
node _res_T_178 = and(_res_T_176, _res_T_177)
wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_3, io.pmp[4]
node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3)
node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6)
connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7
node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3)
node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6)
connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7
node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3)
node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6)
connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7
node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134)
node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1)
node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0)
node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13)
node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14)
node _res_hit_msbMatch_T_40 = shr(io.addr, 3)
node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41)
node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3))
node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43)
node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3)
node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3)
node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45)
node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46)
node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48)
node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0))
node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41)
node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3))
node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43)
node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0)
node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0)
node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45)
node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46)
node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48)
node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0))
node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4)
node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0)
node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0)
node _res_hit_T_57 = not(_res_hit_T_56)
node _res_hit_msbsLess_T_48 = shr(io.addr, 3)
node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49)
node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3))
node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51)
node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3)
node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53)
node _res_hit_msbsEqual_T_56 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57)
node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3))
node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59)
node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3)
node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61)
node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0))
node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57)
node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58)
node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3))
node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60)
node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0)
node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62)
node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8)
node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58)
node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0))
node _res_hit_msbsLess_T_54 = shr(io.addr, 3)
node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55)
node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3))
node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57)
node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3)
node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59)
node _res_hit_msbsEqual_T_63 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2)
node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64)
node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3))
node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66)
node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3)
node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68)
node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0))
node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0))
node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2)
node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65)
node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3))
node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67)
node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0)
node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69)
node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9)
node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61)
node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62)
node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63)
node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64)
node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0))
node res_ignore_4 = and(default, _res_ignore_T_4)
node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0)
node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9)
node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69)
node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71)
node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3)
node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73)
node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76)
node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78)
node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0)
node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81)
node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82)
node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84)
node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69)
node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71)
node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3)
node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73)
node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2)
node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76)
node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78)
node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0)
node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4)
node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82)
node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84)
node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4)
node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0)
node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12)
node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13)
node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0))
node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1)
node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4)
node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0))
node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1))
node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r)
node _res_T_186 = eq(_res_T_185, UInt<1>(0h0))
node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r)
node _res_T_188 = eq(_res_T_187, UInt<1>(0h1))
node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r)
node _res_T_190 = eq(_res_T_189, UInt<2>(0h3))
node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r)
node _res_T_192 = eq(_res_T_191, UInt<3>(0h4))
node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r)
node _res_T_194 = eq(_res_T_193, UInt<3>(0h5))
node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w)
node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r)
node _res_T_196 = eq(_res_T_195, UInt<3>(0h7))
node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_198 = and(_res_T_197, res_hit_4)
node _res_T_199 = and(_res_T_198, res_aligned_4)
node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_201 = and(_res_T_199, _res_T_200)
node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_203 = and(_res_T_202, res_aligned_4)
node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1))
node _res_T_205 = and(_res_T_203, _res_T_204)
node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_207 = and(_res_T_206, res_hit_4)
node _res_T_208 = and(_res_T_207, res_aligned_4)
node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_210 = and(_res_T_208, _res_T_209)
node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_212 = and(_res_T_211, res_aligned_4)
node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2))
node _res_T_214 = and(_res_T_212, _res_T_213)
node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0))
node _res_T_216 = and(_res_T_215, res_hit_4)
node _res_T_217 = and(_res_T_216, res_aligned_4)
node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_219 = and(_res_T_217, _res_T_218)
node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4)
node _res_T_221 = and(_res_T_220, res_aligned_4)
node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3))
node _res_T_223 = and(_res_T_221, _res_T_222)
wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_4, io.pmp[3]
node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4)
node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8)
connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9
node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4)
node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8)
connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9
node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4)
node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8)
connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9
node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179)
node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1)
node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0)
node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16)
node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17)
node _res_hit_msbMatch_T_50 = shr(io.addr, 3)
node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51)
node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3))
node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53)
node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3)
node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3)
node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55)
node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56)
node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58)
node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0))
node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51)
node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3))
node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53)
node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0)
node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0)
node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55)
node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56)
node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58)
node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0))
node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5)
node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0)
node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0)
node _res_hit_T_70 = not(_res_hit_T_69)
node _res_hit_msbsLess_T_60 = shr(io.addr, 3)
node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61)
node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3))
node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63)
node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3)
node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65)
node _res_hit_msbsEqual_T_70 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71)
node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3))
node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73)
node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3)
node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75)
node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0))
node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70)
node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72)
node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3))
node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74)
node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0)
node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76)
node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10)
node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71)
node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0))
node _res_hit_msbsLess_T_66 = shr(io.addr, 3)
node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67)
node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3))
node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69)
node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3)
node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71)
node _res_hit_msbsEqual_T_77 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2)
node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78)
node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3))
node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80)
node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3)
node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82)
node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0))
node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0))
node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2)
node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79)
node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3))
node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81)
node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0)
node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83)
node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11)
node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74)
node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75)
node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76)
node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77)
node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0))
node res_ignore_5 = and(default, _res_ignore_T_5)
node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0)
node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11)
node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86)
node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88)
node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3)
node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90)
node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93)
node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95)
node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0)
node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98)
node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99)
node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101)
node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86)
node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88)
node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3)
node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90)
node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2)
node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93)
node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95)
node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0)
node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5)
node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99)
node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101)
node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5)
node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0)
node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15)
node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16)
node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0))
node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1)
node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5)
node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0))
node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1))
node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r)
node _res_T_231 = eq(_res_T_230, UInt<1>(0h0))
node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r)
node _res_T_233 = eq(_res_T_232, UInt<1>(0h1))
node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r)
node _res_T_235 = eq(_res_T_234, UInt<2>(0h3))
node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r)
node _res_T_237 = eq(_res_T_236, UInt<3>(0h4))
node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r)
node _res_T_239 = eq(_res_T_238, UInt<3>(0h5))
node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w)
node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r)
node _res_T_241 = eq(_res_T_240, UInt<3>(0h7))
node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_243 = and(_res_T_242, res_hit_5)
node _res_T_244 = and(_res_T_243, res_aligned_5)
node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_246 = and(_res_T_244, _res_T_245)
node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_248 = and(_res_T_247, res_aligned_5)
node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1))
node _res_T_250 = and(_res_T_248, _res_T_249)
node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_252 = and(_res_T_251, res_hit_5)
node _res_T_253 = and(_res_T_252, res_aligned_5)
node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_255 = and(_res_T_253, _res_T_254)
node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_257 = and(_res_T_256, res_aligned_5)
node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2))
node _res_T_259 = and(_res_T_257, _res_T_258)
node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0))
node _res_T_261 = and(_res_T_260, res_hit_5)
node _res_T_262 = and(_res_T_261, res_aligned_5)
node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_264 = and(_res_T_262, _res_T_263)
node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5)
node _res_T_266 = and(_res_T_265, res_aligned_5)
node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3))
node _res_T_268 = and(_res_T_266, _res_T_267)
wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_5, io.pmp[2]
node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5)
node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10)
connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11
node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5)
node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10)
connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11
node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5)
node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10)
connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11
node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224)
node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1)
node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0)
node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19)
node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20)
node _res_hit_msbMatch_T_60 = shr(io.addr, 3)
node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61)
node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3))
node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63)
node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3)
node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3)
node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65)
node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66)
node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68)
node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0))
node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61)
node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3))
node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63)
node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0)
node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0)
node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65)
node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66)
node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68)
node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0))
node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6)
node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0)
node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0)
node _res_hit_T_83 = not(_res_hit_T_82)
node _res_hit_msbsLess_T_72 = shr(io.addr, 3)
node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73)
node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3))
node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75)
node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3)
node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77)
node _res_hit_msbsEqual_T_84 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85)
node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3))
node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87)
node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3)
node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89)
node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0))
node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83)
node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86)
node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3))
node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88)
node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0)
node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90)
node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12)
node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84)
node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0))
node _res_hit_msbsLess_T_78 = shr(io.addr, 3)
node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79)
node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3))
node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81)
node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3)
node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83)
node _res_hit_msbsEqual_T_91 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2)
node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92)
node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3))
node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94)
node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3)
node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96)
node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0))
node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0))
node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2)
node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93)
node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3))
node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95)
node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0)
node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97)
node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13)
node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87)
node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88)
node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89)
node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90)
node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0))
node res_ignore_6 = and(default, _res_ignore_T_6)
node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0)
node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13)
node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103)
node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105)
node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3)
node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107)
node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110)
node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112)
node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0)
node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115)
node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116)
node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118)
node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103)
node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105)
node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3)
node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107)
node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2)
node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110)
node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112)
node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0)
node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6)
node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116)
node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118)
node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6)
node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0)
node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18)
node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19)
node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0))
node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1)
node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6)
node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0))
node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1))
node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r)
node _res_T_276 = eq(_res_T_275, UInt<1>(0h0))
node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r)
node _res_T_278 = eq(_res_T_277, UInt<1>(0h1))
node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r)
node _res_T_280 = eq(_res_T_279, UInt<2>(0h3))
node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r)
node _res_T_282 = eq(_res_T_281, UInt<3>(0h4))
node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r)
node _res_T_284 = eq(_res_T_283, UInt<3>(0h5))
node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w)
node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r)
node _res_T_286 = eq(_res_T_285, UInt<3>(0h7))
node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_288 = and(_res_T_287, res_hit_6)
node _res_T_289 = and(_res_T_288, res_aligned_6)
node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_291 = and(_res_T_289, _res_T_290)
node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_293 = and(_res_T_292, res_aligned_6)
node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1))
node _res_T_295 = and(_res_T_293, _res_T_294)
node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_297 = and(_res_T_296, res_hit_6)
node _res_T_298 = and(_res_T_297, res_aligned_6)
node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_300 = and(_res_T_298, _res_T_299)
node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_302 = and(_res_T_301, res_aligned_6)
node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2))
node _res_T_304 = and(_res_T_302, _res_T_303)
node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0))
node _res_T_306 = and(_res_T_305, res_hit_6)
node _res_T_307 = and(_res_T_306, res_aligned_6)
node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_309 = and(_res_T_307, _res_T_308)
node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6)
node _res_T_311 = and(_res_T_310, res_aligned_6)
node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3))
node _res_T_313 = and(_res_T_311, _res_T_312)
wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_6, io.pmp[1]
node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6)
node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12)
connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13
node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6)
node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12)
connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13
node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6)
node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12)
connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13
node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269)
node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1)
node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size)
node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0)
node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22)
node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23)
node _res_hit_msbMatch_T_70 = shr(io.addr, 3)
node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71)
node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3))
node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73)
node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3)
node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3)
node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75)
node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76)
node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78)
node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0))
node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0)
node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71)
node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3))
node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73)
node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0)
node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0)
node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75)
node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76)
node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78)
node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0))
node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7)
node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0)
node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size)
node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0)
node _res_hit_T_96 = not(_res_hit_T_95)
node _res_hit_msbsLess_T_84 = shr(io.addr, 3)
node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2)
node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85)
node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3))
node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87)
node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3)
node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89)
node _res_hit_msbsEqual_T_98 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2)
node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99)
node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3))
node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101)
node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3)
node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103)
node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0))
node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96)
node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2)
node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100)
node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3))
node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102)
node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0)
node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104)
node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14)
node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97)
node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0))
node _res_hit_msbsLess_T_90 = shr(io.addr, 3)
node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91)
node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3))
node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93)
node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3)
node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95)
node _res_hit_msbsEqual_T_105 = shr(io.addr, 3)
node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2)
node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106)
node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3))
node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108)
node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3)
node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110)
node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0))
node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0)
node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0))
node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2)
node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107)
node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3))
node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109)
node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0)
node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111)
node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15)
node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100)
node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101)
node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102)
node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103)
node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0))
node res_ignore_7 = and(default, _res_ignore_T_7)
node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size)
node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0)
node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15)
node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120)
node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122)
node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3)
node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124)
node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2)
node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127)
node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129)
node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0)
node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132)
node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133)
node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135)
node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3)
node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120)
node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122)
node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3)
node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124)
node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0))
node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2)
node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127)
node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3))
node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129)
node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0)
node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0)
node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7)
node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133)
node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0))
node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135)
node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7)
node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0))
node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0)
node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21)
node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22)
node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0))
node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1)
node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7)
node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0))
node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1))
node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r)
node _res_T_321 = eq(_res_T_320, UInt<1>(0h0))
node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r)
node _res_T_323 = eq(_res_T_322, UInt<1>(0h1))
node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r)
node _res_T_325 = eq(_res_T_324, UInt<2>(0h3))
node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r)
node _res_T_327 = eq(_res_T_326, UInt<3>(0h4))
node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r)
node _res_T_329 = eq(_res_T_328, UInt<3>(0h5))
node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w)
node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r)
node _res_T_331 = eq(_res_T_330, UInt<3>(0h7))
node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_333 = and(_res_T_332, res_hit_7)
node _res_T_334 = and(_res_T_333, res_aligned_7)
node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_336 = and(_res_T_334, _res_T_335)
node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_338 = and(_res_T_337, res_aligned_7)
node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1))
node _res_T_340 = and(_res_T_338, _res_T_339)
node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_342 = and(_res_T_341, res_hit_7)
node _res_T_343 = and(_res_T_342, res_aligned_7)
node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_345 = and(_res_T_343, _res_T_344)
node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_347 = and(_res_T_346, res_aligned_7)
node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2))
node _res_T_349 = and(_res_T_347, _res_T_348)
node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0))
node _res_T_351 = and(_res_T_350, res_hit_7)
node _res_T_352 = and(_res_T_351, res_aligned_7)
node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_354 = and(_res_T_352, _res_T_353)
node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7)
node _res_T_356 = and(_res_T_355, res_aligned_7)
node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3))
node _res_T_358 = and(_res_T_356, _res_T_357)
wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect res_cur_7, io.pmp[0]
node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7)
node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14)
connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15
node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7)
node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14)
connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15
node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7)
node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14)
connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15
node res = mux(res_hit_7, res_cur_7, _res_T_314)
connect io.r, res.cfg.r
connect io.w, res.cfg.w
connect io.x, res.cfg.x | module PMPChecker_s3_5( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_14 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_14( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_141 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_151
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_141( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_151 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Core :
input clock : Clock
input reset : Reset
output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip dcpath : { halt : UInt<1>}, imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt}
inst c of CtlPath
connect c.clock, clock
connect c.reset, reset
inst d of DatPath
connect d.clock, clock
connect d.reset, reset
connect d.io.ctl, c.io.ctl
connect c.io.dat, d.io.dat
connect c.io.imem.resp, io.imem.resp
connect io.imem.req.bits, c.io.imem.req.bits
connect io.imem.req.valid, c.io.imem.req.valid
connect c.io.imem.req.ready, io.imem.req.ready
connect d.io.imem.resp, io.imem.resp
connect io.imem.req.bits, d.io.imem.req.bits
connect io.imem.req.valid, d.io.imem.req.valid
connect d.io.imem.req.ready, io.imem.req.ready
connect c.io.dmem.resp, io.dmem.resp
connect io.dmem.req.bits, c.io.dmem.req.bits
connect io.dmem.req.valid, c.io.dmem.req.valid
connect c.io.dmem.req.ready, io.dmem.req.ready
connect d.io.dmem.resp, io.dmem.resp
connect io.dmem.req.bits, d.io.dmem.req.bits
connect io.dmem.req.valid, d.io.dmem.req.valid
connect d.io.dmem.req.ready, io.dmem.req.ready
connect d.io.ddpath, io.ddpath
connect c.io.dcpath, io.dcpath
connect d.io.interrupt.meip, io.interrupt.meip
connect d.io.interrupt.msip, io.interrupt.msip
connect d.io.interrupt.mtip, io.interrupt.mtip
connect d.io.interrupt.debug, io.interrupt.debug
connect d.io.hartid, io.hartid
connect d.io.reset_vector, io.reset_vector | module Core( // @[core.scala:23:7]
input clock, // @[core.scala:23:7]
input reset, // @[core.scala:23:7]
input io_imem_req_ready, // @[core.scala:25:15]
output io_imem_req_valid, // @[core.scala:25:15]
output [31:0] io_imem_req_bits_addr, // @[core.scala:25:15]
input io_imem_resp_valid, // @[core.scala:25:15]
input [31:0] io_imem_resp_bits_data, // @[core.scala:25:15]
input io_dmem_req_ready, // @[core.scala:25:15]
output io_dmem_req_valid, // @[core.scala:25:15]
output [31:0] io_dmem_req_bits_addr, // @[core.scala:25:15]
output [31:0] io_dmem_req_bits_data, // @[core.scala:25:15]
output io_dmem_req_bits_fcn, // @[core.scala:25:15]
output [2:0] io_dmem_req_bits_typ, // @[core.scala:25:15]
input io_dmem_resp_valid, // @[core.scala:25:15]
input [31:0] io_dmem_resp_bits_data, // @[core.scala:25:15]
input io_interrupt_debug, // @[core.scala:25:15]
input io_interrupt_mtip, // @[core.scala:25:15]
input io_interrupt_msip, // @[core.scala:25:15]
input io_interrupt_meip, // @[core.scala:25:15]
input io_hartid // @[core.scala:25:15]
);
wire [31:0] _d_io_dat_dec_inst; // @[core.scala:27:19]
wire _d_io_dat_dec_valid; // @[core.scala:27:19]
wire _d_io_dat_exe_br_eq; // @[core.scala:27:19]
wire _d_io_dat_exe_br_lt; // @[core.scala:27:19]
wire _d_io_dat_exe_br_ltu; // @[core.scala:27:19]
wire [3:0] _d_io_dat_exe_br_type; // @[core.scala:27:19]
wire _d_io_dat_exe_inst_misaligned; // @[core.scala:27:19]
wire _d_io_dat_mem_ctrl_dmem_val; // @[core.scala:27:19]
wire _d_io_dat_mem_data_misaligned; // @[core.scala:27:19]
wire _d_io_dat_mem_store; // @[core.scala:27:19]
wire _d_io_dat_csr_eret; // @[core.scala:27:19]
wire _d_io_dat_csr_interrupt; // @[core.scala:27:19]
wire _c_io_ctl_dec_stall; // @[core.scala:26:19]
wire _c_io_ctl_full_stall; // @[core.scala:26:19]
wire [1:0] _c_io_ctl_exe_pc_sel; // @[core.scala:26:19]
wire [3:0] _c_io_ctl_br_type; // @[core.scala:26:19]
wire _c_io_ctl_if_kill; // @[core.scala:26:19]
wire _c_io_ctl_dec_kill; // @[core.scala:26:19]
wire [1:0] _c_io_ctl_op1_sel; // @[core.scala:26:19]
wire [2:0] _c_io_ctl_op2_sel; // @[core.scala:26:19]
wire [3:0] _c_io_ctl_alu_fun; // @[core.scala:26:19]
wire [1:0] _c_io_ctl_wb_sel; // @[core.scala:26:19]
wire _c_io_ctl_rf_wen; // @[core.scala:26:19]
wire _c_io_ctl_mem_val; // @[core.scala:26:19]
wire [1:0] _c_io_ctl_mem_fcn; // @[core.scala:26:19]
wire [2:0] _c_io_ctl_mem_typ; // @[core.scala:26:19]
wire [2:0] _c_io_ctl_csr_cmd; // @[core.scala:26:19]
wire _c_io_ctl_fencei; // @[core.scala:26:19]
wire _c_io_ctl_pipeline_kill; // @[core.scala:26:19]
wire _c_io_ctl_mem_exception; // @[core.scala:26:19]
wire [31:0] _c_io_ctl_mem_exception_cause; // @[core.scala:26:19]
wire io_imem_req_ready_0 = io_imem_req_ready; // @[core.scala:23:7]
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[core.scala:23:7]
wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[core.scala:23:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[core.scala:23:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[core.scala:23:7]
wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[core.scala:23:7]
wire io_interrupt_debug_0 = io_interrupt_debug; // @[core.scala:23:7]
wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[core.scala:23:7]
wire io_interrupt_msip_0 = io_interrupt_msip; // @[core.scala:23:7]
wire io_interrupt_meip_0 = io_interrupt_meip; // @[core.scala:23:7]
wire io_hartid_0 = io_hartid; // @[core.scala:23:7]
wire [31:0] io_reset_vector = 32'h10000; // @[core.scala:23:7, :25:15, :27:19]
wire [2:0] io_imem_req_bits_typ = 3'h7; // @[core.scala:23:7, :25:15, :27:19]
wire io_ddpath_validreq = 1'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire io_ddpath_resetpc = 1'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire io_dcpath_halt = 1'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire io_imem_req_bits_fcn = 1'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire [31:0] io_ddpath_wdata = 32'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire [31:0] io_ddpath_rdata = 32'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire [31:0] io_imem_req_bits_data = 32'h0; // @[core.scala:23:7, :25:15, :26:19, :27:19]
wire [4:0] io_ddpath_addr = 5'h0; // @[core.scala:23:7, :25:15, :27:19]
wire [31:0] io_imem_req_bits_addr_0; // @[core.scala:23:7]
wire io_imem_req_valid_0; // @[core.scala:23:7]
wire [31:0] io_dmem_req_bits_addr_0; // @[core.scala:23:7]
wire [31:0] io_dmem_req_bits_data_0; // @[core.scala:23:7]
wire io_dmem_req_bits_fcn_0; // @[core.scala:23:7]
wire [2:0] io_dmem_req_bits_typ_0; // @[core.scala:23:7]
wire io_dmem_req_valid_0; // @[core.scala:23:7]
CtlPath c ( // @[core.scala:26:19]
.clock (clock),
.reset (reset),
.io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:23:7]
.io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:23:7]
.io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:23:7]
.io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:23:7]
.io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:23:7]
.io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:23:7]
.io_dat_dec_inst (_d_io_dat_dec_inst), // @[core.scala:27:19]
.io_dat_dec_valid (_d_io_dat_dec_valid), // @[core.scala:27:19]
.io_dat_exe_br_eq (_d_io_dat_exe_br_eq), // @[core.scala:27:19]
.io_dat_exe_br_lt (_d_io_dat_exe_br_lt), // @[core.scala:27:19]
.io_dat_exe_br_ltu (_d_io_dat_exe_br_ltu), // @[core.scala:27:19]
.io_dat_exe_br_type (_d_io_dat_exe_br_type), // @[core.scala:27:19]
.io_dat_exe_inst_misaligned (_d_io_dat_exe_inst_misaligned), // @[core.scala:27:19]
.io_dat_mem_ctrl_dmem_val (_d_io_dat_mem_ctrl_dmem_val), // @[core.scala:27:19]
.io_dat_mem_data_misaligned (_d_io_dat_mem_data_misaligned), // @[core.scala:27:19]
.io_dat_mem_store (_d_io_dat_mem_store), // @[core.scala:27:19]
.io_dat_csr_eret (_d_io_dat_csr_eret), // @[core.scala:27:19]
.io_dat_csr_interrupt (_d_io_dat_csr_interrupt), // @[core.scala:27:19]
.io_ctl_dec_stall (_c_io_ctl_dec_stall),
.io_ctl_full_stall (_c_io_ctl_full_stall),
.io_ctl_exe_pc_sel (_c_io_ctl_exe_pc_sel),
.io_ctl_br_type (_c_io_ctl_br_type),
.io_ctl_if_kill (_c_io_ctl_if_kill),
.io_ctl_dec_kill (_c_io_ctl_dec_kill),
.io_ctl_op1_sel (_c_io_ctl_op1_sel),
.io_ctl_op2_sel (_c_io_ctl_op2_sel),
.io_ctl_alu_fun (_c_io_ctl_alu_fun),
.io_ctl_wb_sel (_c_io_ctl_wb_sel),
.io_ctl_rf_wen (_c_io_ctl_rf_wen),
.io_ctl_mem_val (_c_io_ctl_mem_val),
.io_ctl_mem_fcn (_c_io_ctl_mem_fcn),
.io_ctl_mem_typ (_c_io_ctl_mem_typ),
.io_ctl_csr_cmd (_c_io_ctl_csr_cmd),
.io_ctl_fencei (_c_io_ctl_fencei),
.io_ctl_pipeline_kill (_c_io_ctl_pipeline_kill),
.io_ctl_mem_exception (_c_io_ctl_mem_exception),
.io_ctl_mem_exception_cause (_c_io_ctl_mem_exception_cause)
); // @[core.scala:26:19]
DatPath d ( // @[core.scala:27:19]
.clock (clock),
.reset (reset),
.io_imem_req_ready (io_imem_req_ready_0), // @[core.scala:23:7]
.io_imem_req_valid (io_imem_req_valid_0),
.io_imem_req_bits_addr (io_imem_req_bits_addr_0),
.io_imem_resp_valid (io_imem_resp_valid_0), // @[core.scala:23:7]
.io_imem_resp_bits_data (io_imem_resp_bits_data_0), // @[core.scala:23:7]
.io_dmem_req_ready (io_dmem_req_ready_0), // @[core.scala:23:7]
.io_dmem_req_valid (io_dmem_req_valid_0),
.io_dmem_req_bits_addr (io_dmem_req_bits_addr_0),
.io_dmem_req_bits_data (io_dmem_req_bits_data_0),
.io_dmem_req_bits_fcn (io_dmem_req_bits_fcn_0),
.io_dmem_req_bits_typ (io_dmem_req_bits_typ_0),
.io_dmem_resp_valid (io_dmem_resp_valid_0), // @[core.scala:23:7]
.io_dmem_resp_bits_data (io_dmem_resp_bits_data_0), // @[core.scala:23:7]
.io_ctl_dec_stall (_c_io_ctl_dec_stall), // @[core.scala:26:19]
.io_ctl_full_stall (_c_io_ctl_full_stall), // @[core.scala:26:19]
.io_ctl_exe_pc_sel (_c_io_ctl_exe_pc_sel), // @[core.scala:26:19]
.io_ctl_br_type (_c_io_ctl_br_type), // @[core.scala:26:19]
.io_ctl_if_kill (_c_io_ctl_if_kill), // @[core.scala:26:19]
.io_ctl_dec_kill (_c_io_ctl_dec_kill), // @[core.scala:26:19]
.io_ctl_op1_sel (_c_io_ctl_op1_sel), // @[core.scala:26:19]
.io_ctl_op2_sel (_c_io_ctl_op2_sel), // @[core.scala:26:19]
.io_ctl_alu_fun (_c_io_ctl_alu_fun), // @[core.scala:26:19]
.io_ctl_wb_sel (_c_io_ctl_wb_sel), // @[core.scala:26:19]
.io_ctl_rf_wen (_c_io_ctl_rf_wen), // @[core.scala:26:19]
.io_ctl_mem_val (_c_io_ctl_mem_val), // @[core.scala:26:19]
.io_ctl_mem_fcn (_c_io_ctl_mem_fcn), // @[core.scala:26:19]
.io_ctl_mem_typ (_c_io_ctl_mem_typ), // @[core.scala:26:19]
.io_ctl_csr_cmd (_c_io_ctl_csr_cmd), // @[core.scala:26:19]
.io_ctl_fencei (_c_io_ctl_fencei), // @[core.scala:26:19]
.io_ctl_pipeline_kill (_c_io_ctl_pipeline_kill), // @[core.scala:26:19]
.io_ctl_mem_exception (_c_io_ctl_mem_exception), // @[core.scala:26:19]
.io_ctl_mem_exception_cause (_c_io_ctl_mem_exception_cause), // @[core.scala:26:19]
.io_dat_dec_inst (_d_io_dat_dec_inst),
.io_dat_dec_valid (_d_io_dat_dec_valid),
.io_dat_exe_br_eq (_d_io_dat_exe_br_eq),
.io_dat_exe_br_lt (_d_io_dat_exe_br_lt),
.io_dat_exe_br_ltu (_d_io_dat_exe_br_ltu),
.io_dat_exe_br_type (_d_io_dat_exe_br_type),
.io_dat_exe_inst_misaligned (_d_io_dat_exe_inst_misaligned),
.io_dat_mem_ctrl_dmem_val (_d_io_dat_mem_ctrl_dmem_val),
.io_dat_mem_data_misaligned (_d_io_dat_mem_data_misaligned),
.io_dat_mem_store (_d_io_dat_mem_store),
.io_dat_csr_eret (_d_io_dat_csr_eret),
.io_dat_csr_interrupt (_d_io_dat_csr_interrupt),
.io_interrupt_debug (io_interrupt_debug_0), // @[core.scala:23:7]
.io_interrupt_mtip (io_interrupt_mtip_0), // @[core.scala:23:7]
.io_interrupt_msip (io_interrupt_msip_0), // @[core.scala:23:7]
.io_interrupt_meip (io_interrupt_meip_0), // @[core.scala:23:7]
.io_hartid (io_hartid_0) // @[core.scala:23:7]
); // @[core.scala:27:19]
assign io_imem_req_valid = io_imem_req_valid_0; // @[core.scala:23:7]
assign io_imem_req_bits_addr = io_imem_req_bits_addr_0; // @[core.scala:23:7]
assign io_dmem_req_valid = io_dmem_req_valid_0; // @[core.scala:23:7]
assign io_dmem_req_bits_addr = io_dmem_req_bits_addr_0; // @[core.scala:23:7]
assign io_dmem_req_bits_data = io_dmem_req_bits_data_0; // @[core.scala:23:7]
assign io_dmem_req_bits_fcn = io_dmem_req_bits_fcn_0; // @[core.scala:23:7]
assign io_dmem_req_bits_typ = io_dmem_req_bits_typ_0; // @[core.scala:23:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_71 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}}
inst input_buffer of InputBuffer_71
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter2_RouteComputerReq_25
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4`
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2]
wire vcalloc_vals : UInt<1>[2]
node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0))
node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11)
node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_18 = and(io.router_req.ready, io.router_req.valid)
when _T_18 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1])
when _T_19 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = bits(vcalloc_sel, 0, 0)
node _mask_T_6 = bits(vcalloc_sel, 1, 1)
node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0))
node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0))
node _mask_T_9 = or(_mask_T_7, _mask_T_8)
wire _mask_WIRE : UInt<2>
connect _mask_WIRE, _mask_T_9
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2]
node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2]
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16
connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19
connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[2]
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_34
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_40
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_43
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_46
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_20 = bits(vcalloc_sel, 0, 0)
node _T_21 = and(vcalloc_vals[0], _T_20)
node _T_22 = and(_T_21, io.vcalloc_req.ready)
when _T_22 :
connect states[0].g, UInt<3>(0h3)
node _T_23 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_23 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].vc_sel.`3`[1]
invalidate vcalloc_reqs[1].vc_sel.`4`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready)
node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_3
node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_24 :
node _T_25 = bits(vcalloc_sel, 0, 0)
when _T_25 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[0].g, UInt<3>(0h3)
node _T_26 = bits(vcalloc_sel, 1, 1)
when _T_26 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[1].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_174
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node _credit_available_T = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node _credit_available_T_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node _credit_available_T_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node _credit_available_T_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_hi = cat(states[0].vc_sel.`4`[0], _credit_available_T_3)
node credit_available_hi = cat(credit_available_hi_hi, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi, credit_available_lo)
node _credit_available_T_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node _credit_available_T_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node _credit_available_T_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node _credit_available_T_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_1 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_hi_1 = cat(io.out_credit_available.`4`[0], _credit_available_T_8)
node credit_available_hi_1 = cat(credit_available_hi_hi_1, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_27 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_28 = and(_T_27, input_buffer.io.deq[0].bits.tail)
when _T_28 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`4`[0]
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_5
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5
node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_7
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _vc_sel_WIRE : UInt<1>[2]
node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_4
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_7
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_3 : UInt<1>[2]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_10
connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4
node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_13
connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5
connect vc_sel.`1`, _vc_sel_WIRE_3
wire _vc_sel_WIRE_6 : UInt<1>[2]
node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_16
connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7
node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_19
connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8
connect vc_sel.`2`, _vc_sel_WIRE_6
wire _vc_sel_WIRE_9 : UInt<1>[2]
node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_22
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_25 = or(_vc_sel_T_23, _vc_sel_T_24)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_25
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
connect vc_sel.`3`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_26 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_28 = or(_vc_sel_T_26, _vc_sel_T_27)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_28
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`4`, _vc_sel_WIRE_12
node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_3 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1)
node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0))
node _virt_channel_T_9 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0))
node _virt_channel_T_10 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0))
node _virt_channel_T_11 = mux(channel_oh_3, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_12 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_13 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_10)
node _virt_channel_T_15 = or(_virt_channel_T_14, _virt_channel_T_11)
node _virt_channel_T_16 = or(_virt_channel_T_15, _virt_channel_T_12)
wire virt_channel : UInt<1>
connect virt_channel, _virt_channel_T_16
node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_29 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[0], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].vc_sel.`3`[1]
invalidate states[1].vc_sel.`4`[0]
invalidate states[1].g
node _T_30 = asUInt(reset)
when _T_30 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0) | module InputUnit_71( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget1 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_15
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2)
node hasData = eq(_hasData_opdata_T, UInt<1>(0h0))
node _limit_T = dshl(UInt<3>(0h7), anonIn.a.bits.size)
node _limit_T_1 = bits(_limit_T, 2, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 0)
regreset count : UInt<3>, clock, reset, UInt<3>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
node _enable_T_12 = xor(count, UInt<3>(0h4))
node _enable_T_13 = and(_enable_T_12, limit)
node _enable_T_14 = orr(_enable_T_13)
node enable_4 = eq(_enable_T_14, UInt<1>(0h0))
node _enable_T_15 = xor(count, UInt<3>(0h5))
node _enable_T_16 = and(_enable_T_15, limit)
node _enable_T_17 = orr(_enable_T_16)
node enable_5 = eq(_enable_T_17, UInt<1>(0h0))
node _enable_T_18 = xor(count, UInt<3>(0h6))
node _enable_T_19 = and(_enable_T_18, limit)
node _enable_T_20 = orr(_enable_T_19)
node enable_6 = eq(_enable_T_20, UInt<1>(0h0))
node _enable_T_21 = xor(count, UInt<3>(0h7))
node _enable_T_22 = and(_enable_T_21, limit)
node _enable_T_23 = orr(_enable_T_22)
node enable_7 = eq(_enable_T_23, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg)
node _T = and(anonIn.a.ready, anonIn.a.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonIn_a_ready_T = eq(last, UInt<1>(0h0))
node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T)
connect anonIn.a.ready, _anonIn_a_ready_T_1
node _anonOut_a_valid_T = and(anonIn.a.valid, last)
connect anonOut.a.valid, _anonOut_a_valid_T
connect anonOut.a.bits, anonIn.a.bits
regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T)
node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1)
node _anonOut_a_bits_data_masked_enable_T_2 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_2 = or(enable_2, _anonOut_a_bits_data_masked_enable_T_2)
node _anonOut_a_bits_data_masked_enable_T_3 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_3 = or(enable_3, _anonOut_a_bits_data_masked_enable_T_3)
node _anonOut_a_bits_data_masked_enable_T_4 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_4 = or(enable_4, _anonOut_a_bits_data_masked_enable_T_4)
node _anonOut_a_bits_data_masked_enable_T_5 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_5 = or(enable_5, _anonOut_a_bits_data_masked_enable_T_5)
node _anonOut_a_bits_data_masked_enable_T_6 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_6 = or(enable_6, _anonOut_a_bits_data_masked_enable_T_6)
node _anonOut_a_bits_data_masked_enable_T_7 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_data_masked_enable_7 = or(enable_7, _anonOut_a_bits_data_masked_enable_T_7)
wire anonOut_a_bits_data_odata_0 : UInt
connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_1 : UInt
connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_2 : UInt
connect anonOut_a_bits_data_odata_2, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_3 : UInt
connect anonOut_a_bits_data_odata_3, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_4 : UInt
connect anonOut_a_bits_data_odata_4, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_5 : UInt
connect anonOut_a_bits_data_odata_5, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_6 : UInt
connect anonOut_a_bits_data_odata_6, anonIn.a.bits.data
wire anonOut_a_bits_data_odata_7 : UInt
connect anonOut_a_bits_data_odata_7, anonIn.a.bits.data
reg anonOut_a_bits_data_rdata : UInt<8>[7], clock
node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0])
node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonOut_a_bits_data_rdata[1])
node anonOut_a_bits_data_mdata_2 = mux(anonOut_a_bits_data_masked_enable_2, anonOut_a_bits_data_odata_2, anonOut_a_bits_data_rdata[2])
node anonOut_a_bits_data_mdata_3 = mux(anonOut_a_bits_data_masked_enable_3, anonOut_a_bits_data_odata_3, anonOut_a_bits_data_rdata[3])
node anonOut_a_bits_data_mdata_4 = mux(anonOut_a_bits_data_masked_enable_4, anonOut_a_bits_data_odata_4, anonOut_a_bits_data_rdata[4])
node anonOut_a_bits_data_mdata_5 = mux(anonOut_a_bits_data_masked_enable_5, anonOut_a_bits_data_odata_5, anonOut_a_bits_data_rdata[5])
node anonOut_a_bits_data_mdata_6 = mux(anonOut_a_bits_data_masked_enable_6, anonOut_a_bits_data_odata_6, anonOut_a_bits_data_rdata[6])
node anonOut_a_bits_data_mdata_7 = mux(anonOut_a_bits_data_masked_enable_7, anonOut_a_bits_data_odata_7, anonIn.a.bits.data)
node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1)
when _anonOut_a_bits_data_T_2 :
connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0
connect anonOut_a_bits_data_rdata[1], anonOut_a_bits_data_mdata_1
connect anonOut_a_bits_data_rdata[2], anonOut_a_bits_data_mdata_2
connect anonOut_a_bits_data_rdata[3], anonOut_a_bits_data_mdata_3
connect anonOut_a_bits_data_rdata[4], anonOut_a_bits_data_mdata_4
connect anonOut_a_bits_data_rdata[5], anonOut_a_bits_data_mdata_5
connect anonOut_a_bits_data_rdata[6], anonOut_a_bits_data_mdata_6
node anonOut_a_bits_data_lo_lo = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0)
node anonOut_a_bits_data_lo_hi = cat(anonOut_a_bits_data_mdata_3, anonOut_a_bits_data_mdata_2)
node anonOut_a_bits_data_lo = cat(anonOut_a_bits_data_lo_hi, anonOut_a_bits_data_lo_lo)
node anonOut_a_bits_data_hi_lo = cat(anonOut_a_bits_data_mdata_5, anonOut_a_bits_data_mdata_4)
node anonOut_a_bits_data_hi_hi = cat(anonOut_a_bits_data_mdata_7, anonOut_a_bits_data_mdata_6)
node anonOut_a_bits_data_hi = cat(anonOut_a_bits_data_hi_hi, anonOut_a_bits_data_hi_lo)
node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_hi, anonOut_a_bits_data_lo)
connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3
connect anonOut.a.bits.corrupt, corrupt_out
node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<3>(0h0))
node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0)
node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount)
node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 2, 0)
node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1))
node anonOut_a_bits_mask_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<2>(0h3))
node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2)
node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2)
node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_nbit)
node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2)
node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T)
node anonOut_a_bits_mask_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_bit)
node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2)
node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1)
node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1)
node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1)
node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2)
node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T)
node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2)
node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1)
node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit)
node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2)
node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2)
node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit)
node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2)
node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3)
node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0)
node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0)
node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0))
node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq)
node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T)
node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1)
node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1)
node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2)
node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2)
node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3)
node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3)
node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4)
node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4)
node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5)
node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5)
node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit)
node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6)
node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6)
node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit)
node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7)
node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7)
node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc)
node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2)
node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo)
node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4)
node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6)
node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo)
node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo)
regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T)
node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1)
node _anonOut_a_bits_mask_masked_enable_T_2 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_2 = or(enable_2, _anonOut_a_bits_mask_masked_enable_T_2)
node _anonOut_a_bits_mask_masked_enable_T_3 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_3 = or(enable_3, _anonOut_a_bits_mask_masked_enable_T_3)
node _anonOut_a_bits_mask_masked_enable_T_4 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_4 = or(enable_4, _anonOut_a_bits_mask_masked_enable_T_4)
node _anonOut_a_bits_mask_masked_enable_T_5 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_5 = or(enable_5, _anonOut_a_bits_mask_masked_enable_T_5)
node _anonOut_a_bits_mask_masked_enable_T_6 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_6 = or(enable_6, _anonOut_a_bits_mask_masked_enable_T_6)
node _anonOut_a_bits_mask_masked_enable_T_7 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0))
node anonOut_a_bits_mask_masked_enable_7 = or(enable_7, _anonOut_a_bits_mask_masked_enable_T_7)
wire anonOut_a_bits_mask_odata_0 : UInt
connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_1 : UInt
connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_2 : UInt
connect anonOut_a_bits_mask_odata_2, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_3 : UInt
connect anonOut_a_bits_mask_odata_3, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_4 : UInt
connect anonOut_a_bits_mask_odata_4, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_5 : UInt
connect anonOut_a_bits_mask_odata_5, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_6 : UInt
connect anonOut_a_bits_mask_odata_6, anonIn.a.bits.mask
wire anonOut_a_bits_mask_odata_7 : UInt
connect anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask
reg anonOut_a_bits_mask_rdata : UInt<1>[7], clock
node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0])
node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonOut_a_bits_mask_rdata[1])
node anonOut_a_bits_mask_mdata_2 = mux(anonOut_a_bits_mask_masked_enable_2, anonOut_a_bits_mask_odata_2, anonOut_a_bits_mask_rdata[2])
node anonOut_a_bits_mask_mdata_3 = mux(anonOut_a_bits_mask_masked_enable_3, anonOut_a_bits_mask_odata_3, anonOut_a_bits_mask_rdata[3])
node anonOut_a_bits_mask_mdata_4 = mux(anonOut_a_bits_mask_masked_enable_4, anonOut_a_bits_mask_odata_4, anonOut_a_bits_mask_rdata[4])
node anonOut_a_bits_mask_mdata_5 = mux(anonOut_a_bits_mask_masked_enable_5, anonOut_a_bits_mask_odata_5, anonOut_a_bits_mask_rdata[5])
node anonOut_a_bits_mask_mdata_6 = mux(anonOut_a_bits_mask_masked_enable_6, anonOut_a_bits_mask_odata_6, anonOut_a_bits_mask_rdata[6])
node anonOut_a_bits_mask_mdata_7 = mux(anonOut_a_bits_mask_masked_enable_7, anonOut_a_bits_mask_odata_7, anonIn.a.bits.mask)
node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid)
node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0))
node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2)
when _anonOut_a_bits_mask_T_3 :
connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1)
connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0
connect anonOut_a_bits_mask_rdata[1], anonOut_a_bits_mask_mdata_1
connect anonOut_a_bits_mask_rdata[2], anonOut_a_bits_mask_mdata_2
connect anonOut_a_bits_mask_rdata[3], anonOut_a_bits_mask_mdata_3
connect anonOut_a_bits_mask_rdata[4], anonOut_a_bits_mask_mdata_4
connect anonOut_a_bits_mask_rdata[5], anonOut_a_bits_mask_mdata_5
connect anonOut_a_bits_mask_rdata[6], anonOut_a_bits_mask_mdata_6
node anonOut_a_bits_mask_lo_lo_1 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0)
node anonOut_a_bits_mask_lo_hi_1 = cat(anonOut_a_bits_mask_mdata_3, anonOut_a_bits_mask_mdata_2)
node anonOut_a_bits_mask_lo_1 = cat(anonOut_a_bits_mask_lo_hi_1, anonOut_a_bits_mask_lo_lo_1)
node anonOut_a_bits_mask_hi_lo_1 = cat(anonOut_a_bits_mask_mdata_5, anonOut_a_bits_mask_mdata_4)
node anonOut_a_bits_mask_hi_hi_1 = cat(anonOut_a_bits_mask_mdata_7, anonOut_a_bits_mask_mdata_6)
node anonOut_a_bits_mask_hi_1 = cat(anonOut_a_bits_mask_hi_hi_1, anonOut_a_bits_mask_hi_lo_1)
node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_hi_1, anonOut_a_bits_mask_lo_1)
node _anonOut_a_bits_mask_T_5 = not(UInt<8>(0h0))
node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5)
node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6)
connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleD_a32d64s1k5z4u
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonOut.d
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 63, 8)
node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 7, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node repeat_hasData = bits(cated.bits.opcode, 0, 0)
node _repeat_limit_T = dshl(UInt<3>(0h7), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 2, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 0)
regreset repeat_count : UInt<3>, clock, reset, UInt<3>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonIn.d.ready, anonIn.d.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
reg repeat_sel_sel_sources : UInt<3>[1], clock
node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 2, 0)
node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid)
when _repeat_sel_sel_T :
connect repeat_sel_sel_sources[0], repeat_sel_sel_a_sel
node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, UInt<0>(0h0))
node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T)
reg repeat_sel_hold_r : UInt<3>, clock
when repeat_first :
connect repeat_sel_hold_r, repeat_sel_sel_sources[0]
node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[0], repeat_sel_hold_r)
node _repeat_sel_T = not(repeat_limit)
node repeat_sel = and(repeat_sel_hold, _repeat_sel_T)
node repeat_index = or(repeat_sel, repeat_count)
connect anonIn.d.bits.corrupt, cated.bits.corrupt
connect anonIn.d.bits.data, cated.bits.data
connect anonIn.d.bits.denied, cated.bits.denied
connect anonIn.d.bits.sink, cated.bits.sink
connect anonIn.d.bits.source, cated.bits.source
connect anonIn.d.bits.size, cated.bits.size
connect anonIn.d.bits.param, cated.bits.param
connect anonIn.d.bits.opcode, cated.bits.opcode
connect anonIn.d.valid, cated.valid
connect cated.ready, anonIn.d.ready
node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 7, 0)
node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 15, 8)
node _repeat_anonIn_d_bits_data_mux_T_2 = bits(cated.bits.data, 23, 16)
node _repeat_anonIn_d_bits_data_mux_T_3 = bits(cated.bits.data, 31, 24)
node _repeat_anonIn_d_bits_data_mux_T_4 = bits(cated.bits.data, 39, 32)
node _repeat_anonIn_d_bits_data_mux_T_5 = bits(cated.bits.data, 47, 40)
node _repeat_anonIn_d_bits_data_mux_T_6 = bits(cated.bits.data, 55, 48)
node _repeat_anonIn_d_bits_data_mux_T_7 = bits(cated.bits.data, 63, 56)
wire repeat_anonIn_d_bits_data_mux : UInt<8>[8]
connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T
connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1
connect repeat_anonIn_d_bits_data_mux[2], _repeat_anonIn_d_bits_data_mux_T_2
connect repeat_anonIn_d_bits_data_mux[3], _repeat_anonIn_d_bits_data_mux_T_3
connect repeat_anonIn_d_bits_data_mux[4], _repeat_anonIn_d_bits_data_mux_T_4
connect repeat_anonIn_d_bits_data_mux[5], _repeat_anonIn_d_bits_data_mux_T_5
connect repeat_anonIn_d_bits_data_mux[6], _repeat_anonIn_d_bits_data_mux_T_6
connect repeat_anonIn_d_bits_data_mux[7], _repeat_anonIn_d_bits_data_mux_T_7
connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<8>(0h0)
connect _WIRE.bits.mask, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_10.bits.sink, UInt<5>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget1( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _repeated_repeater_io_deq_valid; // @[Repeater.scala:36:26]
wire [2:0] _repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala:36:26]
wire [1:0] _repeated_repeater_io_deq_bits_param; // @[Repeater.scala:36:26]
wire [3:0] _repeated_repeater_io_deq_bits_size; // @[Repeater.scala:36:26]
wire [4:0] _repeated_repeater_io_deq_bits_sink; // @[Repeater.scala:36:26]
wire _repeated_repeater_io_deq_bits_denied; // @[Repeater.scala:36:26]
wire [63:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire _repeated_repeater_io_deq_bits_corrupt; // @[Repeater.scala:36:26]
wire [17:0] _limit_T = 18'h7 << auto_anon_in_a_bits_size; // @[package.scala:243:71]
reg [2:0] count; // @[WidthWidget.scala:40:27]
wire last = count == ~(_limit_T[2:0]) | auto_anon_in_a_bits_opcode[2]; // @[package.scala:243:{46,71,76}]
wire anonIn_a_ready = auto_anon_out_a_ready | ~last; // @[WidthWidget.scala:42:36, :76:{29,32}]
reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire anonOut_a_bits_data_masked_enable_0 = (count & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_1 = ({count[2:1], ~(count[0])} & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_2 = ({count[2], count[1:0] ^ 2'h2} & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_3 = ({count[2], ~(count[1:0])} & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_4 = ((count ^ 3'h4) & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_5 = ((count ^ 3'h5) & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
wire anonOut_a_bits_data_masked_enable_6 = ((count ^ 3'h6) & ~(_limit_T[2:0])) == 3'h0 | ~anonOut_a_bits_data_rdata_written_once; // @[package.scala:243:{46,71,76}]
reg [7:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_3; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_4; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_5; // @[WidthWidget.scala:66:24]
reg [7:0] anonOut_a_bits_data_rdata_6; // @[WidthWidget.scala:66:24]
wire anonOut_a_bits_mask_sub_sub_sub_0_1 = auto_anon_in_a_bits_size > 4'h2; // @[Misc.scala:206:21]
wire anonOut_a_bits_mask_sub_sub_size = auto_anon_in_a_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49]
wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | anonOut_a_bits_mask_sub_sub_size & ~(auto_anon_in_a_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}]
wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | anonOut_a_bits_mask_sub_sub_size & auto_anon_in_a_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}]
wire anonOut_a_bits_mask_sub_size = auto_anon_in_a_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49]
wire anonOut_a_bits_mask_sub_0_2 = ~(auto_anon_in_a_bits_address[2]) & ~(auto_anon_in_a_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire anonOut_a_bits_mask_sub_1_2 = ~(auto_anon_in_a_bits_address[2]) & auto_anon_in_a_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27]
wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire anonOut_a_bits_mask_sub_2_2 = auto_anon_in_a_bits_address[2] & ~(auto_anon_in_a_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27]
wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire anonOut_a_bits_mask_sub_3_2 = auto_anon_in_a_bits_address[2] & auto_anon_in_a_bits_address[1]; // @[Misc.scala:210:26, :214:27]
wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}]
wire [17:0] _repeat_limit_T = 18'h7 << _repeated_repeater_io_deq_bits_size; // @[package.scala:243:71]
reg [2:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 3'h0; // @[WidthWidget.scala:105:26, :106:25]
wire repeat_last = repeat_count == ~(_repeat_limit_T[2:0]) | ~(_repeated_repeater_io_deq_bits_opcode[0]); // @[package.scala:243:{46,71,76}]
reg [2:0] repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27]
reg [2:0] repeat_sel_hold_r; // @[WidthWidget.scala:121:47]
wire [7:0][7:0] _GEN = {{_repeated_repeater_io_deq_bits_data[63:56]}, {_repeated_repeater_io_deq_bits_data[55:48]}, {_repeated_repeater_io_deq_bits_data[47:40]}, {_repeated_repeater_io_deq_bits_data[39:32]}, {_repeated_repeater_io_deq_bits_data[31:24]}, {_repeated_repeater_io_deq_bits_data[23:16]}, {_repeated_repeater_io_deq_bits_data[15:8]}, {auto_anon_out_d_bits_data[7:0]}}; // @[Repeater.scala:36:26]
wire _repeat_sel_sel_T = anonIn_a_ready & auto_anon_in_a_valid; // @[Decoupled.scala:51:35]
wire _anonOut_a_bits_data_T_2 = _repeat_sel_sel_T & ~last; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
count <= 3'h0; // @[WidthWidget.scala:40:27]
anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
repeat_count <= 3'h0; // @[WidthWidget.scala:105:26]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35]
count <= last ? 3'h0 : count + 3'h1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
if (auto_anon_in_d_ready & _repeated_repeater_io_deq_valid) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 3'h0 : repeat_count + 3'h1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
end
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_0) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_0 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_1) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_1 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_2) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_2 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_3) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_3 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_4) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_4 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_5) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_5 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_anonOut_a_bits_data_T_2 & anonOut_a_bits_data_masked_enable_6) // @[WidthWidget.scala:63:42, :66:24, :68:88, :69:{23,33}, :71:56]
anonOut_a_bits_data_rdata_6 <= auto_anon_in_a_bits_data; // @[WidthWidget.scala:66:24]
if (_repeat_sel_sel_T) // @[Decoupled.scala:51:35]
repeat_sel_sel_sources_0 <= auto_anon_in_a_bits_address[2:0]; // @[WidthWidget.scala:187:27, :188:38]
if (repeat_first) // @[WidthWidget.scala:106:25]
repeat_sel_hold_r <= repeat_sel_sel_sources_0; // @[WidthWidget.scala:121:47, :187:27]
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_205 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_205( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_66 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 4)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 4)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_64 = shr(io.in.a.bits.source, 4)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_77 = shr(io.in.a.bits.source, 4)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<4>(0h8))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<4>(0h9))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<4>(0ha))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<4>(0hb))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_164 = shr(io.in.a.bits.source, 4)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_170 = shr(io.in.a.bits.source, 4)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_177 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_178 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<4>(0h8))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<4>(0h9))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<4>(0ha))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<4>(0hb))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h1))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_235 = shr(io.in.a.bits.source, 4)
node _T_236 = eq(_T_235, UInt<1>(0h0))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_242 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_243 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_234
connect _WIRE[6], _T_240
connect _WIRE[7], _T_241
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], _T_245, UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<4>(0h8))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<4>(0h9))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<4>(0ha))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<4>(0hb))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_334 = shr(io.in.a.bits.source, 4)
node _T_335 = eq(_T_334, UInt<1>(0h1))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_340 = shr(io.in.a.bits.source, 4)
node _T_341 = eq(_T_340, UInt<1>(0h0))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_339)
node _T_355 = or(_T_354, _T_345)
node _T_356 = or(_T_355, _T_346)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<4>(0h8))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<4>(0h9))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<4>(0ha))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<4>(0hb))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_399 = shr(io.in.a.bits.source, 4)
node _T_400 = eq(_T_399, UInt<1>(0h1))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_405 = shr(io.in.a.bits.source, 4)
node _T_406 = eq(_T_405, UInt<1>(0h0))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_412 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_413 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_404
connect _WIRE_2[6], _T_410
connect _WIRE_2[7], _T_411
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], _T_415, UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<4>(0h8))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<4>(0h9))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<4>(0ha))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<4>(0hb))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_508 = shr(io.in.a.bits.source, 4)
node _T_509 = eq(_T_508, UInt<1>(0h1))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_514 = shr(io.in.a.bits.source, 4)
node _T_515 = eq(_T_514, UInt<1>(0h0))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_513)
node _T_529 = or(_T_528, _T_519)
node _T_530 = or(_T_529, _T_520)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<4>(0h8))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<4>(0h9))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<4>(0ha))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<4>(0hb))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_600 = shr(io.in.a.bits.source, 4)
node _T_601 = eq(_T_600, UInt<1>(0h1))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_605 = and(_T_603, _T_604)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_606 = shr(io.in.a.bits.source, 4)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_614 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_605)
node _T_621 = or(_T_620, _T_611)
node _T_622 = or(_T_621, _T_612)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<13>(0h1000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<4>(0h8))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<4>(0h9))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<4>(0ha))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<4>(0hb))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_686 = shr(io.in.a.bits.source, 4)
node _T_687 = eq(_T_686, UInt<1>(0h1))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_692 = shr(io.in.a.bits.source, 4)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_699 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_700 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_691)
node _T_707 = or(_T_706, _T_697)
node _T_708 = or(_T_707, _T_698)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<13>(0h1000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<4>(0h8))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<4>(0h9))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<4>(0ha))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<4>(0hb))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_774 = shr(io.in.a.bits.source, 4)
node _T_775 = eq(_T_774, UInt<1>(0h1))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_780 = shr(io.in.a.bits.source, 4)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_787 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_788 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_779)
node _T_795 = or(_T_794, _T_785)
node _T_796 = or(_T_795, _T_786)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = and(_T_801, _T_809)
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_T_810, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_810, UInt<1>(0h1), "") : assert_36
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(source_ok, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(is_aligned, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_820, UInt<1>(0h1), "") : assert_39
node _T_824 = eq(io.in.a.bits.mask, mask)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_824, UInt<1>(0h1), "") : assert_40
node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_828 :
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<4>(0h8))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<4>(0h9))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<4>(0ha))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<4>(0hb))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_857 = shr(io.in.a.bits.source, 4)
node _T_858 = eq(_T_857, UInt<1>(0h1))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_863 = shr(io.in.a.bits.source, 4)
node _T_864 = eq(_T_863, UInt<1>(0h0))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_868 = and(_T_866, _T_867)
node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_873 = or(_T_832, _T_838)
node _T_874 = or(_T_873, _T_844)
node _T_875 = or(_T_874, _T_850)
node _T_876 = or(_T_875, _T_856)
node _T_877 = or(_T_876, _T_862)
node _T_878 = or(_T_877, _T_868)
node _T_879 = or(_T_878, _T_869)
node _T_880 = or(_T_879, _T_870)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = and(_T_831, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = and(_T_885, _T_890)
node _T_892 = or(UInt<1>(0h0), _T_891)
node _T_893 = and(_T_884, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_893, UInt<1>(0h1), "") : assert_41
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_903, UInt<1>(0h1), "") : assert_44
node _T_907 = eq(io.in.a.bits.mask, mask)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_907, UInt<1>(0h1), "") : assert_45
node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_911 :
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_916 = shr(io.in.a.bits.source, 2)
node _T_917 = eq(_T_916, UInt<4>(0h8))
node _T_918 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_919 = and(_T_917, _T_918)
node _T_920 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_921 = and(_T_919, _T_920)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<4>(0h9))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<4>(0ha))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<4>(0hb))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_940 = shr(io.in.a.bits.source, 4)
node _T_941 = eq(_T_940, UInt<1>(0h1))
node _T_942 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_943 = and(_T_941, _T_942)
node _T_944 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_945 = and(_T_943, _T_944)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_946 = shr(io.in.a.bits.source, 4)
node _T_947 = eq(_T_946, UInt<1>(0h0))
node _T_948 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_949 = and(_T_947, _T_948)
node _T_950 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_953 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_954 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_956 = or(_T_915, _T_921)
node _T_957 = or(_T_956, _T_927)
node _T_958 = or(_T_957, _T_933)
node _T_959 = or(_T_958, _T_939)
node _T_960 = or(_T_959, _T_945)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_952)
node _T_963 = or(_T_962, _T_953)
node _T_964 = or(_T_963, _T_954)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_914, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<13>(0h1000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = and(_T_968, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = and(_T_967, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_976, UInt<1>(0h1), "") : assert_46
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_986, UInt<1>(0h1), "") : assert_49
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_990, UInt<1>(0h1), "") : assert_50
node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_994, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_998, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<4>(0h8))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<4>(0h9))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<4>(0ha))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<4>(0hb))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 4)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 4)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54
node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55
node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57
node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1022 :
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(source_ok_1, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(sink_ok, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60
node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61
node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62
node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64
node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1050 :
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok_1, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(sink_ok, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67
node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68
node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69
node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1070 = or(_T_1069, io.in.d.bits.corrupt)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70
node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71
node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(source_ok_1, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(_T_1083, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73
node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74
node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1092 = or(UInt<1>(0h0), _T_1091)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75
node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1096 :
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(source_ok_1, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(_T_1104, io.in.d.bits.corrupt)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h0), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79
node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81
node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82
node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1143 = eq(a_first, UInt<1>(0h0))
node _T_1144 = and(io.in.a.valid, _T_1143)
when _T_1144 :
node _T_1145 = eq(io.in.a.bits.opcode, opcode)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87
node _T_1149 = eq(io.in.a.bits.param, param)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88
node _T_1153 = eq(io.in.a.bits.size, size)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89
node _T_1157 = eq(io.in.a.bits.source, source)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90
node _T_1161 = eq(io.in.a.bits.address, address)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91
node _T_1165 = and(io.in.a.ready, io.in.a.valid)
node _T_1166 = and(_T_1165, a_first)
when _T_1166 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1167 = eq(d_first, UInt<1>(0h0))
node _T_1168 = and(io.in.d.valid, _T_1167)
when _T_1168 :
node _T_1169 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92
node _T_1173 = eq(io.in.d.bits.param, param_1)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93
node _T_1177 = eq(io.in.d.bits.size, size_1)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94
node _T_1181 = eq(io.in.d.bits.source, source_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95
node _T_1185 = eq(io.in.d.bits.sink, sink)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96
node _T_1189 = eq(io.in.d.bits.denied, denied)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97
node _T_1193 = and(io.in.d.ready, io.in.d.valid)
node _T_1194 = and(_T_1193, d_first)
when _T_1194 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1195 = and(io.in.a.valid, a_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
when _T_1196 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1197 = and(io.in.a.ready, io.in.a.valid)
node _T_1198 = and(_T_1197, a_first_1)
node _T_1199 = and(_T_1198, UInt<1>(0h1))
when _T_1199 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1200 = dshr(inflight, io.in.a.bits.source)
node _T_1201 = bits(_T_1200, 0, 0)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1206 = and(io.in.d.valid, d_first_1)
node _T_1207 = and(_T_1206, UInt<1>(0h1))
node _T_1208 = eq(d_release_ack, UInt<1>(0h0))
node _T_1209 = and(_T_1207, _T_1208)
when _T_1209 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1210 = and(io.in.d.ready, io.in.d.valid)
node _T_1211 = and(_T_1210, d_first_1)
node _T_1212 = and(_T_1211, UInt<1>(0h1))
node _T_1213 = eq(d_release_ack, UInt<1>(0h0))
node _T_1214 = and(_T_1212, _T_1213)
when _T_1214 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1219 = dshr(inflight, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100
node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101
else :
node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102
node _T_1241 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103
node _T_1245 = and(io.in.d.valid, d_first_1)
node _T_1246 = and(_T_1245, a_first_1)
node _T_1247 = and(_T_1246, io.in.a.valid)
node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1253 = or(_T_1252, io.in.a.ready)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_136
node _T_1257 = orr(inflight)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
node _T_1259 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1260 = or(_T_1258, _T_1259)
node _T_1261 = lt(watchdog, plusarg_reader.out)
node _T_1262 = or(_T_1260, _T_1261)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1266 = and(io.in.a.ready, io.in.a.valid)
node _T_1267 = and(io.in.d.ready, io.in.d.valid)
node _T_1268 = or(_T_1266, _T_1267)
when _T_1268 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1269 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1270 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1271 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1272 = and(_T_1270, _T_1271)
node _T_1273 = and(_T_1269, _T_1272)
when _T_1273 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1274 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1275 = and(_T_1274, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1276 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1277 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1278 = and(_T_1276, _T_1277)
node _T_1279 = and(_T_1275, _T_1278)
when _T_1279 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1280 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1281 = bits(_T_1280, 0, 0)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1286 = and(io.in.d.valid, d_first_2)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
node _T_1288 = and(_T_1287, d_release_ack_1)
when _T_1288 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1289 = and(io.in.d.ready, io.in.d.valid)
node _T_1290 = and(_T_1289, d_first_2)
node _T_1291 = and(_T_1290, UInt<1>(0h1))
node _T_1292 = and(_T_1291, d_release_ack_1)
when _T_1292 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1296 = dshr(inflight_1, io.in.d.bits.source)
node _T_1297 = bits(_T_1296, 0, 0)
node _T_1298 = or(_T_1297, same_cycle_resp_1)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1302 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_108
else :
node _T_1306 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_109
node _T_1310 = and(io.in.d.valid, d_first_2)
node _T_1311 = and(_T_1310, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1312 = and(_T_1311, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1313 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1314 = and(_T_1312, _T_1313)
node _T_1315 = and(_T_1314, d_release_ack_1)
node _T_1316 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1317 = and(_T_1315, _T_1316)
when _T_1317 :
node _T_1318 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1319 = or(_T_1318, _WIRE_27.ready)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_137
node _T_1323 = orr(inflight_1)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
node _T_1325 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1326 = or(_T_1324, _T_1325)
node _T_1327 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1328 = or(_T_1326, _T_1327)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1332 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1333 = and(io.in.d.ready, io.in.d.valid)
node _T_1334 = or(_T_1332, _T_1333)
when _T_1334 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_66( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_56 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_112
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_113
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_56( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_49 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = and(_T_11, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_24 :
node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_35 = cvt(_T_34)
node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000)))
node _T_37 = asSInt(_T_36)
node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0)))
node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_40 = cvt(_T_39)
node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000)))
node _T_42 = asSInt(_T_41)
node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0)))
node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_45 = cvt(_T_44)
node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000)))
node _T_47 = asSInt(_T_46)
node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0)))
node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_50 = cvt(_T_49)
node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000)))
node _T_52 = asSInt(_T_51)
node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0)))
node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<27>(0h4000000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<13>(0h1000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = or(_T_38, _T_43)
node _T_75 = or(_T_74, _T_48)
node _T_76 = or(_T_75, _T_53)
node _T_77 = or(_T_76, _T_58)
node _T_78 = or(_T_77, _T_63)
node _T_79 = or(_T_78, _T_68)
node _T_80 = or(_T_79, _T_73)
node _T_81 = and(_T_33, _T_80)
node _T_82 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_83 = or(UInt<1>(0h0), _T_82)
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<17>(0h10000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<29>(0h10000000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_88, _T_93)
node _T_95 = and(_T_83, _T_94)
node _T_96 = or(UInt<1>(0h0), _T_81)
node _T_97 = or(_T_96, _T_95)
node _T_98 = and(_T_32, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_98, UInt<1>(0h1), "") : assert_2
node _T_102 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_103 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE : UInt<1>[2]
connect _WIRE[0], _T_102
connect _WIRE[1], _T_103
node _T_104 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_105 = mux(_WIRE[0], _T_104, UInt<1>(0h0))
node _T_106 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = or(_T_105, _T_106)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_107
node _T_108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_110 = and(_T_108, _T_109)
node _T_111 = or(UInt<1>(0h0), _T_110)
node _T_112 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<14>(0h2000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<17>(0h10000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<27>(0h4000000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<13>(0h1000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<29>(0h10000000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = or(_T_116, _T_121)
node _T_163 = or(_T_162, _T_126)
node _T_164 = or(_T_163, _T_131)
node _T_165 = or(_T_164, _T_136)
node _T_166 = or(_T_165, _T_141)
node _T_167 = or(_T_166, _T_146)
node _T_168 = or(_T_167, _T_151)
node _T_169 = or(_T_168, _T_156)
node _T_170 = or(_T_169, _T_161)
node _T_171 = and(_T_111, _T_170)
node _T_172 = or(UInt<1>(0h0), _T_171)
node _T_173 = and(_WIRE_1, _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_173, UInt<1>(0h1), "") : assert_3
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(source_ok, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_180 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_180, UInt<1>(0h1), "") : assert_5
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(is_aligned, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_187 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_187, UInt<1>(0h1), "") : assert_7
node _T_191 = not(io.in.a.bits.mask)
node _T_192 = eq(_T_191, UInt<1>(0h0))
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_T_192, UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_192, UInt<1>(0h1), "") : assert_8
node _T_196 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_197 = asUInt(reset)
node _T_198 = eq(_T_197, UInt<1>(0h0))
when _T_198 :
node _T_199 = eq(_T_196, UInt<1>(0h0))
when _T_199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_196, UInt<1>(0h1), "") : assert_9
node _T_200 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_200 :
node _T_201 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_202 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_205 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_206 = or(_T_204, _T_205)
node _T_207 = and(_T_203, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<14>(0h2000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<18>(0h2f000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<17>(0h10000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<13>(0h1000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_241 = cvt(_T_240)
node _T_242 = and(_T_241, asSInt(UInt<27>(0h4000000)))
node _T_243 = asSInt(_T_242)
node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<13>(0h1000)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = or(_T_214, _T_219)
node _T_251 = or(_T_250, _T_224)
node _T_252 = or(_T_251, _T_229)
node _T_253 = or(_T_252, _T_234)
node _T_254 = or(_T_253, _T_239)
node _T_255 = or(_T_254, _T_244)
node _T_256 = or(_T_255, _T_249)
node _T_257 = and(_T_209, _T_256)
node _T_258 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_259 = or(UInt<1>(0h0), _T_258)
node _T_260 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<17>(0h10000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<29>(0h10000000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = or(_T_264, _T_269)
node _T_271 = and(_T_259, _T_270)
node _T_272 = or(UInt<1>(0h0), _T_257)
node _T_273 = or(_T_272, _T_271)
node _T_274 = and(_T_208, _T_273)
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_274, UInt<1>(0h1), "") : assert_10
node _T_278 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h1))
wire _WIRE_2 : UInt<1>[2]
connect _WIRE_2[0], _T_278
connect _WIRE_2[1], _T_279
node _T_280 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_281 = mux(_WIRE_2[0], _T_280, UInt<1>(0h0))
node _T_282 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = or(_T_281, _T_282)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_283
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<14>(0h2000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<13>(0h1000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<17>(0h10000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<18>(0h2f000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<13>(0h1000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<27>(0h4000000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<29>(0h10000000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = or(_T_292, _T_297)
node _T_339 = or(_T_338, _T_302)
node _T_340 = or(_T_339, _T_307)
node _T_341 = or(_T_340, _T_312)
node _T_342 = or(_T_341, _T_317)
node _T_343 = or(_T_342, _T_322)
node _T_344 = or(_T_343, _T_327)
node _T_345 = or(_T_344, _T_332)
node _T_346 = or(_T_345, _T_337)
node _T_347 = and(_T_287, _T_346)
node _T_348 = or(UInt<1>(0h0), _T_347)
node _T_349 = and(_WIRE_3, _T_348)
node _T_350 = asUInt(reset)
node _T_351 = eq(_T_350, UInt<1>(0h0))
when _T_351 :
node _T_352 = eq(_T_349, UInt<1>(0h0))
when _T_352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_349, UInt<1>(0h1), "") : assert_11
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(source_ok, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_356 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_357 = asUInt(reset)
node _T_358 = eq(_T_357, UInt<1>(0h0))
when _T_358 :
node _T_359 = eq(_T_356, UInt<1>(0h0))
when _T_359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_356, UInt<1>(0h1), "") : assert_13
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(is_aligned, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_363 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_363, UInt<1>(0h1), "") : assert_15
node _T_367 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_367, UInt<1>(0h1), "") : assert_16
node _T_371 = not(io.in.a.bits.mask)
node _T_372 = eq(_T_371, UInt<1>(0h0))
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_372, UInt<1>(0h1), "") : assert_17
node _T_376 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_376, UInt<1>(0h1), "") : assert_18
node _T_380 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_380 :
node _T_381 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_382 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_385 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_386 = or(_T_384, _T_385)
node _T_387 = and(_T_383, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(_T_388, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_388, UInt<1>(0h1), "") : assert_19
node _T_392 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_393 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_394 = and(_T_392, _T_393)
node _T_395 = or(UInt<1>(0h0), _T_394)
node _T_396 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_397 = cvt(_T_396)
node _T_398 = and(_T_397, asSInt(UInt<13>(0h1000)))
node _T_399 = asSInt(_T_398)
node _T_400 = eq(_T_399, asSInt(UInt<1>(0h0)))
node _T_401 = and(_T_395, _T_400)
node _T_402 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_403 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_404 = and(_T_402, _T_403)
node _T_405 = or(UInt<1>(0h0), _T_404)
node _T_406 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_407 = cvt(_T_406)
node _T_408 = and(_T_407, asSInt(UInt<14>(0h2000)))
node _T_409 = asSInt(_T_408)
node _T_410 = eq(_T_409, asSInt(UInt<1>(0h0)))
node _T_411 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_412 = cvt(_T_411)
node _T_413 = and(_T_412, asSInt(UInt<17>(0h10000)))
node _T_414 = asSInt(_T_413)
node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0)))
node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_417 = cvt(_T_416)
node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000)))
node _T_419 = asSInt(_T_418)
node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0)))
node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_422 = cvt(_T_421)
node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000)))
node _T_424 = asSInt(_T_423)
node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0)))
node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_427 = cvt(_T_426)
node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000)))
node _T_429 = asSInt(_T_428)
node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0)))
node _T_431 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_432 = cvt(_T_431)
node _T_433 = and(_T_432, asSInt(UInt<17>(0h10000)))
node _T_434 = asSInt(_T_433)
node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0)))
node _T_436 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_437 = cvt(_T_436)
node _T_438 = and(_T_437, asSInt(UInt<27>(0h4000000)))
node _T_439 = asSInt(_T_438)
node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0)))
node _T_441 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<13>(0h1000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<29>(0h10000000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = or(_T_410, _T_415)
node _T_452 = or(_T_451, _T_420)
node _T_453 = or(_T_452, _T_425)
node _T_454 = or(_T_453, _T_430)
node _T_455 = or(_T_454, _T_435)
node _T_456 = or(_T_455, _T_440)
node _T_457 = or(_T_456, _T_445)
node _T_458 = or(_T_457, _T_450)
node _T_459 = and(_T_405, _T_458)
node _T_460 = or(UInt<1>(0h0), _T_401)
node _T_461 = or(_T_460, _T_459)
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_T_461, UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_461, UInt<1>(0h1), "") : assert_20
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(source_ok, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(is_aligned, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_471 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_471, UInt<1>(0h1), "") : assert_23
node _T_475 = eq(io.in.a.bits.mask, mask)
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_475, UInt<1>(0h1), "") : assert_24
node _T_479 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_479, UInt<1>(0h1), "") : assert_25
node _T_483 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_483 :
node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_485 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_486 = and(_T_484, _T_485)
node _T_487 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_488 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_489 = or(_T_487, _T_488)
node _T_490 = and(_T_486, _T_489)
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_494 = and(_T_492, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_497 = cvt(_T_496)
node _T_498 = and(_T_497, asSInt(UInt<13>(0h1000)))
node _T_499 = asSInt(_T_498)
node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0)))
node _T_501 = and(_T_495, _T_500)
node _T_502 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_503 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_504 = and(_T_502, _T_503)
node _T_505 = or(UInt<1>(0h0), _T_504)
node _T_506 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_507 = cvt(_T_506)
node _T_508 = and(_T_507, asSInt(UInt<14>(0h2000)))
node _T_509 = asSInt(_T_508)
node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0)))
node _T_511 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<18>(0h2f000)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<17>(0h10000)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<27>(0h4000000)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<13>(0h1000)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_542 = cvt(_T_541)
node _T_543 = and(_T_542, asSInt(UInt<29>(0h10000000)))
node _T_544 = asSInt(_T_543)
node _T_545 = eq(_T_544, asSInt(UInt<1>(0h0)))
node _T_546 = or(_T_510, _T_515)
node _T_547 = or(_T_546, _T_520)
node _T_548 = or(_T_547, _T_525)
node _T_549 = or(_T_548, _T_530)
node _T_550 = or(_T_549, _T_535)
node _T_551 = or(_T_550, _T_540)
node _T_552 = or(_T_551, _T_545)
node _T_553 = and(_T_505, _T_552)
node _T_554 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_555 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<17>(0h10000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = and(_T_554, _T_559)
node _T_561 = or(UInt<1>(0h0), _T_501)
node _T_562 = or(_T_561, _T_553)
node _T_563 = or(_T_562, _T_560)
node _T_564 = and(_T_491, _T_563)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_564, UInt<1>(0h1), "") : assert_26
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(source_ok, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(is_aligned, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_574 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_574, UInt<1>(0h1), "") : assert_29
node _T_578 = eq(io.in.a.bits.mask, mask)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_578, UInt<1>(0h1), "") : assert_30
node _T_582 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_582 :
node _T_583 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_584 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_585 = and(_T_583, _T_584)
node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_587 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(_T_585, _T_588)
node _T_590 = or(UInt<1>(0h0), _T_589)
node _T_591 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_592 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_593 = and(_T_591, _T_592)
node _T_594 = or(UInt<1>(0h0), _T_593)
node _T_595 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_596 = cvt(_T_595)
node _T_597 = and(_T_596, asSInt(UInt<13>(0h1000)))
node _T_598 = asSInt(_T_597)
node _T_599 = eq(_T_598, asSInt(UInt<1>(0h0)))
node _T_600 = and(_T_594, _T_599)
node _T_601 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_602 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_603 = and(_T_601, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_603)
node _T_605 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_606 = cvt(_T_605)
node _T_607 = and(_T_606, asSInt(UInt<14>(0h2000)))
node _T_608 = asSInt(_T_607)
node _T_609 = eq(_T_608, asSInt(UInt<1>(0h0)))
node _T_610 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_611 = cvt(_T_610)
node _T_612 = and(_T_611, asSInt(UInt<18>(0h2f000)))
node _T_613 = asSInt(_T_612)
node _T_614 = eq(_T_613, asSInt(UInt<1>(0h0)))
node _T_615 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_616 = cvt(_T_615)
node _T_617 = and(_T_616, asSInt(UInt<17>(0h10000)))
node _T_618 = asSInt(_T_617)
node _T_619 = eq(_T_618, asSInt(UInt<1>(0h0)))
node _T_620 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_621 = cvt(_T_620)
node _T_622 = and(_T_621, asSInt(UInt<13>(0h1000)))
node _T_623 = asSInt(_T_622)
node _T_624 = eq(_T_623, asSInt(UInt<1>(0h0)))
node _T_625 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_626 = cvt(_T_625)
node _T_627 = and(_T_626, asSInt(UInt<17>(0h10000)))
node _T_628 = asSInt(_T_627)
node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0)))
node _T_630 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_631 = cvt(_T_630)
node _T_632 = and(_T_631, asSInt(UInt<27>(0h4000000)))
node _T_633 = asSInt(_T_632)
node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0)))
node _T_635 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_636 = cvt(_T_635)
node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000)))
node _T_638 = asSInt(_T_637)
node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0)))
node _T_640 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_641 = cvt(_T_640)
node _T_642 = and(_T_641, asSInt(UInt<29>(0h10000000)))
node _T_643 = asSInt(_T_642)
node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0)))
node _T_645 = or(_T_609, _T_614)
node _T_646 = or(_T_645, _T_619)
node _T_647 = or(_T_646, _T_624)
node _T_648 = or(_T_647, _T_629)
node _T_649 = or(_T_648, _T_634)
node _T_650 = or(_T_649, _T_639)
node _T_651 = or(_T_650, _T_644)
node _T_652 = and(_T_604, _T_651)
node _T_653 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_654 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_655 = cvt(_T_654)
node _T_656 = and(_T_655, asSInt(UInt<17>(0h10000)))
node _T_657 = asSInt(_T_656)
node _T_658 = eq(_T_657, asSInt(UInt<1>(0h0)))
node _T_659 = and(_T_653, _T_658)
node _T_660 = or(UInt<1>(0h0), _T_600)
node _T_661 = or(_T_660, _T_652)
node _T_662 = or(_T_661, _T_659)
node _T_663 = and(_T_590, _T_662)
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(_T_663, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_663, UInt<1>(0h1), "") : assert_31
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(source_ok, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(is_aligned, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_673 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_673, UInt<1>(0h1), "") : assert_34
node _T_677 = not(mask)
node _T_678 = and(io.in.a.bits.mask, _T_677)
node _T_679 = eq(_T_678, UInt<1>(0h0))
node _T_680 = asUInt(reset)
node _T_681 = eq(_T_680, UInt<1>(0h0))
when _T_681 :
node _T_682 = eq(_T_679, UInt<1>(0h0))
when _T_682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_679, UInt<1>(0h1), "") : assert_35
node _T_683 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_683 :
node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_685 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_688 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_689 = or(_T_687, _T_688)
node _T_690 = and(_T_686, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_693 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(UInt<1>(0h0), _T_694)
node _T_696 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<14>(0h2000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_702 = cvt(_T_701)
node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000)))
node _T_704 = asSInt(_T_703)
node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0)))
node _T_706 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<18>(0h2f000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<17>(0h10000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<17>(0h10000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<27>(0h4000000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<29>(0h10000000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = or(_T_700, _T_705)
node _T_742 = or(_T_741, _T_710)
node _T_743 = or(_T_742, _T_715)
node _T_744 = or(_T_743, _T_720)
node _T_745 = or(_T_744, _T_725)
node _T_746 = or(_T_745, _T_730)
node _T_747 = or(_T_746, _T_735)
node _T_748 = or(_T_747, _T_740)
node _T_749 = and(_T_695, _T_748)
node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = and(_T_750, _T_755)
node _T_757 = or(UInt<1>(0h0), _T_749)
node _T_758 = or(_T_757, _T_756)
node _T_759 = and(_T_691, _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_759, UInt<1>(0h1), "") : assert_36
node _T_763 = asUInt(reset)
node _T_764 = eq(_T_763, UInt<1>(0h0))
when _T_764 :
node _T_765 = eq(source_ok, UInt<1>(0h0))
when _T_765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_766 = asUInt(reset)
node _T_767 = eq(_T_766, UInt<1>(0h0))
when _T_767 :
node _T_768 = eq(is_aligned, UInt<1>(0h0))
when _T_768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_769 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_770 = asUInt(reset)
node _T_771 = eq(_T_770, UInt<1>(0h0))
when _T_771 :
node _T_772 = eq(_T_769, UInt<1>(0h0))
when _T_772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_769, UInt<1>(0h1), "") : assert_39
node _T_773 = eq(io.in.a.bits.mask, mask)
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_773, UInt<1>(0h1), "") : assert_40
node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_777 :
node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_782 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_783 = or(_T_781, _T_782)
node _T_784 = and(_T_780, _T_783)
node _T_785 = or(UInt<1>(0h0), _T_784)
node _T_786 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_787 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_788 = and(_T_786, _T_787)
node _T_789 = or(UInt<1>(0h0), _T_788)
node _T_790 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<14>(0h2000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<13>(0h1000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<18>(0h2f000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_806 = cvt(_T_805)
node _T_807 = and(_T_806, asSInt(UInt<17>(0h10000)))
node _T_808 = asSInt(_T_807)
node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0)))
node _T_810 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_811 = cvt(_T_810)
node _T_812 = and(_T_811, asSInt(UInt<13>(0h1000)))
node _T_813 = asSInt(_T_812)
node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0)))
node _T_815 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_816 = cvt(_T_815)
node _T_817 = and(_T_816, asSInt(UInt<17>(0h10000)))
node _T_818 = asSInt(_T_817)
node _T_819 = eq(_T_818, asSInt(UInt<1>(0h0)))
node _T_820 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_821 = cvt(_T_820)
node _T_822 = and(_T_821, asSInt(UInt<27>(0h4000000)))
node _T_823 = asSInt(_T_822)
node _T_824 = eq(_T_823, asSInt(UInt<1>(0h0)))
node _T_825 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_826 = cvt(_T_825)
node _T_827 = and(_T_826, asSInt(UInt<13>(0h1000)))
node _T_828 = asSInt(_T_827)
node _T_829 = eq(_T_828, asSInt(UInt<1>(0h0)))
node _T_830 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_831 = cvt(_T_830)
node _T_832 = and(_T_831, asSInt(UInt<29>(0h10000000)))
node _T_833 = asSInt(_T_832)
node _T_834 = eq(_T_833, asSInt(UInt<1>(0h0)))
node _T_835 = or(_T_794, _T_799)
node _T_836 = or(_T_835, _T_804)
node _T_837 = or(_T_836, _T_809)
node _T_838 = or(_T_837, _T_814)
node _T_839 = or(_T_838, _T_819)
node _T_840 = or(_T_839, _T_824)
node _T_841 = or(_T_840, _T_829)
node _T_842 = or(_T_841, _T_834)
node _T_843 = and(_T_789, _T_842)
node _T_844 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_845 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_846 = cvt(_T_845)
node _T_847 = and(_T_846, asSInt(UInt<17>(0h10000)))
node _T_848 = asSInt(_T_847)
node _T_849 = eq(_T_848, asSInt(UInt<1>(0h0)))
node _T_850 = and(_T_844, _T_849)
node _T_851 = or(UInt<1>(0h0), _T_843)
node _T_852 = or(_T_851, _T_850)
node _T_853 = and(_T_785, _T_852)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_853, UInt<1>(0h1), "") : assert_41
node _T_857 = asUInt(reset)
node _T_858 = eq(_T_857, UInt<1>(0h0))
when _T_858 :
node _T_859 = eq(source_ok, UInt<1>(0h0))
when _T_859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(is_aligned, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_863 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_863, UInt<1>(0h1), "") : assert_44
node _T_867 = eq(io.in.a.bits.mask, mask)
node _T_868 = asUInt(reset)
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(_T_867, UInt<1>(0h0))
when _T_870 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_867, UInt<1>(0h1), "") : assert_45
node _T_871 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_871 :
node _T_872 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_873 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_876 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_877 = or(_T_875, _T_876)
node _T_878 = and(_T_874, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_881 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_882 = and(_T_880, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_882)
node _T_884 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = and(_T_883, _T_888)
node _T_890 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_891 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<14>(0h2000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<17>(0h10000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<18>(0h2f000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_912 = cvt(_T_911)
node _T_913 = and(_T_912, asSInt(UInt<13>(0h1000)))
node _T_914 = asSInt(_T_913)
node _T_915 = eq(_T_914, asSInt(UInt<1>(0h0)))
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<27>(0h4000000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<13>(0h1000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_895, _T_900)
node _T_927 = or(_T_926, _T_905)
node _T_928 = or(_T_927, _T_910)
node _T_929 = or(_T_928, _T_915)
node _T_930 = or(_T_929, _T_920)
node _T_931 = or(_T_930, _T_925)
node _T_932 = and(_T_890, _T_931)
node _T_933 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_934 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_935 = and(_T_933, _T_934)
node _T_936 = or(UInt<1>(0h0), _T_935)
node _T_937 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<17>(0h10000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_943 = cvt(_T_942)
node _T_944 = and(_T_943, asSInt(UInt<29>(0h10000000)))
node _T_945 = asSInt(_T_944)
node _T_946 = eq(_T_945, asSInt(UInt<1>(0h0)))
node _T_947 = or(_T_941, _T_946)
node _T_948 = and(_T_936, _T_947)
node _T_949 = or(UInt<1>(0h0), _T_889)
node _T_950 = or(_T_949, _T_932)
node _T_951 = or(_T_950, _T_948)
node _T_952 = and(_T_879, _T_951)
node _T_953 = asUInt(reset)
node _T_954 = eq(_T_953, UInt<1>(0h0))
when _T_954 :
node _T_955 = eq(_T_952, UInt<1>(0h0))
when _T_955 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_952, UInt<1>(0h1), "") : assert_46
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(source_ok, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(is_aligned, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_962 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(_T_962, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_962, UInt<1>(0h1), "") : assert_49
node _T_966 = eq(io.in.a.bits.mask, mask)
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_966, UInt<1>(0h1), "") : assert_50
node _T_970 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_970, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_974 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(_T_974, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_974, UInt<1>(0h1), "") : assert_52
node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_2
connect _source_ok_WIRE_1[1], _source_ok_T_3
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_978 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_978 :
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(source_ok_1, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_982 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_982, UInt<1>(0h1), "") : assert_54
node _T_986 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_986, UInt<1>(0h1), "") : assert_55
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_990, UInt<1>(0h1), "") : assert_56
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_994, UInt<1>(0h1), "") : assert_57
node _T_998 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_998 :
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(source_ok_1, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(sink_ok, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1005 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_60
node _T_1009 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1010 = asUInt(reset)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
when _T_1011 :
node _T_1012 = eq(_T_1009, UInt<1>(0h0))
when _T_1012 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1009, UInt<1>(0h1), "") : assert_61
node _T_1013 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_62
node _T_1017 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1018 = asUInt(reset)
node _T_1019 = eq(_T_1018, UInt<1>(0h0))
when _T_1019 :
node _T_1020 = eq(_T_1017, UInt<1>(0h0))
when _T_1020 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1017, UInt<1>(0h1), "") : assert_63
node _T_1021 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1022 = or(UInt<1>(0h1), _T_1021)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_64
node _T_1026 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1026 :
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(source_ok_1, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(sink_ok, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1033 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_67
node _T_1037 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_68
node _T_1041 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_69
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(_T_1045, io.in.d.bits.corrupt)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_70
node _T_1050 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1051 = or(UInt<1>(0h1), _T_1050)
node _T_1052 = asUInt(reset)
node _T_1053 = eq(_T_1052, UInt<1>(0h0))
when _T_1053 :
node _T_1054 = eq(_T_1051, UInt<1>(0h0))
when _T_1054 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1051, UInt<1>(0h1), "") : assert_71
node _T_1055 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = asUInt(reset)
node _T_1057 = eq(_T_1056, UInt<1>(0h0))
when _T_1057 :
node _T_1058 = eq(source_ok_1, UInt<1>(0h0))
when _T_1058 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1059 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_73
node _T_1063 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_74
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h1), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_75
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_77
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = or(_T_1080, io.in.d.bits.corrupt)
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_T_1081, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1081, UInt<1>(0h1), "") : assert_78
node _T_1085 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1086 = or(UInt<1>(0h1), _T_1085)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_79
node _T_1090 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1090 :
node _T_1091 = asUInt(reset)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
when _T_1092 :
node _T_1093 = eq(source_ok_1, UInt<1>(0h0))
when _T_1093 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1094 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_81
node _T_1098 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_82
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h1), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1107 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(_T_1107, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1107, UInt<1>(0h1), "") : assert_84
node _T_1111 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
node _T_1113 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1114 = cvt(_T_1113)
node _T_1115 = and(_T_1114, asSInt(UInt<1>(0h0)))
node _T_1116 = asSInt(_T_1115)
node _T_1117 = eq(_T_1116, asSInt(UInt<1>(0h0)))
node _T_1118 = or(_T_1112, _T_1117)
node _T_1119 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
node _T_1121 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1122 = cvt(_T_1121)
node _T_1123 = and(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = asSInt(_T_1123)
node _T_1125 = eq(_T_1124, asSInt(UInt<1>(0h0)))
node _T_1126 = or(_T_1120, _T_1125)
node _T_1127 = and(_T_1118, _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _legal_source_WIRE : UInt<1>[2]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
node _legal_source_T_2 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_3 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_4 = or(_legal_source_T_2, _legal_source_T_3)
wire _legal_source_WIRE_1 : UInt<1>
connect _legal_source_WIRE_1, _legal_source_T_4
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1131 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1131 :
node _T_1132 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1133 = eq(io.in.b.bits.source, UInt<1>(0h1))
wire _WIRE_4 : UInt<1>[2]
connect _WIRE_4[0], _T_1132
connect _WIRE_4[1], _T_1133
node _T_1134 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1135 = mux(_WIRE_4[0], _T_1134, UInt<1>(0h0))
node _T_1136 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1137 = or(_T_1135, _T_1136)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1137
node _T_1138 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1139 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1140 = and(_T_1138, _T_1139)
node _T_1141 = or(UInt<1>(0h0), _T_1140)
node _T_1142 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1143 = cvt(_T_1142)
node _T_1144 = and(_T_1143, asSInt(UInt<14>(0h2000)))
node _T_1145 = asSInt(_T_1144)
node _T_1146 = eq(_T_1145, asSInt(UInt<1>(0h0)))
node _T_1147 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<13>(0h1000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1153 = cvt(_T_1152)
node _T_1154 = and(_T_1153, asSInt(UInt<17>(0h10000)))
node _T_1155 = asSInt(_T_1154)
node _T_1156 = eq(_T_1155, asSInt(UInt<1>(0h0)))
node _T_1157 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1158 = cvt(_T_1157)
node _T_1159 = and(_T_1158, asSInt(UInt<18>(0h2f000)))
node _T_1160 = asSInt(_T_1159)
node _T_1161 = eq(_T_1160, asSInt(UInt<1>(0h0)))
node _T_1162 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1163 = cvt(_T_1162)
node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000)))
node _T_1165 = asSInt(_T_1164)
node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0)))
node _T_1167 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1168 = cvt(_T_1167)
node _T_1169 = and(_T_1168, asSInt(UInt<13>(0h1000)))
node _T_1170 = asSInt(_T_1169)
node _T_1171 = eq(_T_1170, asSInt(UInt<1>(0h0)))
node _T_1172 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1173 = cvt(_T_1172)
node _T_1174 = and(_T_1173, asSInt(UInt<17>(0h10000)))
node _T_1175 = asSInt(_T_1174)
node _T_1176 = eq(_T_1175, asSInt(UInt<1>(0h0)))
node _T_1177 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1178 = cvt(_T_1177)
node _T_1179 = and(_T_1178, asSInt(UInt<27>(0h4000000)))
node _T_1180 = asSInt(_T_1179)
node _T_1181 = eq(_T_1180, asSInt(UInt<1>(0h0)))
node _T_1182 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1183 = cvt(_T_1182)
node _T_1184 = and(_T_1183, asSInt(UInt<13>(0h1000)))
node _T_1185 = asSInt(_T_1184)
node _T_1186 = eq(_T_1185, asSInt(UInt<1>(0h0)))
node _T_1187 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1188 = cvt(_T_1187)
node _T_1189 = and(_T_1188, asSInt(UInt<29>(0h10000000)))
node _T_1190 = asSInt(_T_1189)
node _T_1191 = eq(_T_1190, asSInt(UInt<1>(0h0)))
node _T_1192 = or(_T_1146, _T_1151)
node _T_1193 = or(_T_1192, _T_1156)
node _T_1194 = or(_T_1193, _T_1161)
node _T_1195 = or(_T_1194, _T_1166)
node _T_1196 = or(_T_1195, _T_1171)
node _T_1197 = or(_T_1196, _T_1176)
node _T_1198 = or(_T_1197, _T_1181)
node _T_1199 = or(_T_1198, _T_1186)
node _T_1200 = or(_T_1199, _T_1191)
node _T_1201 = and(_T_1141, _T_1200)
node _T_1202 = or(UInt<1>(0h0), _T_1201)
node _T_1203 = and(_WIRE_5, _T_1202)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(address_ok, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(legal_source, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1216 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90
node _T_1220 = eq(io.in.b.bits.mask, mask_1)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91
node _T_1224 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_92
node _T_1228 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1228 :
node _T_1229 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1230 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1231 = and(_T_1229, _T_1230)
node _T_1232 = or(UInt<1>(0h0), _T_1231)
node _T_1233 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1234 = cvt(_T_1233)
node _T_1235 = and(_T_1234, asSInt(UInt<14>(0h2000)))
node _T_1236 = asSInt(_T_1235)
node _T_1237 = eq(_T_1236, asSInt(UInt<1>(0h0)))
node _T_1238 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1239 = cvt(_T_1238)
node _T_1240 = and(_T_1239, asSInt(UInt<13>(0h1000)))
node _T_1241 = asSInt(_T_1240)
node _T_1242 = eq(_T_1241, asSInt(UInt<1>(0h0)))
node _T_1243 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1244 = cvt(_T_1243)
node _T_1245 = and(_T_1244, asSInt(UInt<17>(0h10000)))
node _T_1246 = asSInt(_T_1245)
node _T_1247 = eq(_T_1246, asSInt(UInt<1>(0h0)))
node _T_1248 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1249 = cvt(_T_1248)
node _T_1250 = and(_T_1249, asSInt(UInt<18>(0h2f000)))
node _T_1251 = asSInt(_T_1250)
node _T_1252 = eq(_T_1251, asSInt(UInt<1>(0h0)))
node _T_1253 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1254 = cvt(_T_1253)
node _T_1255 = and(_T_1254, asSInt(UInt<17>(0h10000)))
node _T_1256 = asSInt(_T_1255)
node _T_1257 = eq(_T_1256, asSInt(UInt<1>(0h0)))
node _T_1258 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1259 = cvt(_T_1258)
node _T_1260 = and(_T_1259, asSInt(UInt<13>(0h1000)))
node _T_1261 = asSInt(_T_1260)
node _T_1262 = eq(_T_1261, asSInt(UInt<1>(0h0)))
node _T_1263 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1264 = cvt(_T_1263)
node _T_1265 = and(_T_1264, asSInt(UInt<17>(0h10000)))
node _T_1266 = asSInt(_T_1265)
node _T_1267 = eq(_T_1266, asSInt(UInt<1>(0h0)))
node _T_1268 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1269 = cvt(_T_1268)
node _T_1270 = and(_T_1269, asSInt(UInt<27>(0h4000000)))
node _T_1271 = asSInt(_T_1270)
node _T_1272 = eq(_T_1271, asSInt(UInt<1>(0h0)))
node _T_1273 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1274 = cvt(_T_1273)
node _T_1275 = and(_T_1274, asSInt(UInt<13>(0h1000)))
node _T_1276 = asSInt(_T_1275)
node _T_1277 = eq(_T_1276, asSInt(UInt<1>(0h0)))
node _T_1278 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1279 = cvt(_T_1278)
node _T_1280 = and(_T_1279, asSInt(UInt<29>(0h10000000)))
node _T_1281 = asSInt(_T_1280)
node _T_1282 = eq(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = or(_T_1237, _T_1242)
node _T_1284 = or(_T_1283, _T_1247)
node _T_1285 = or(_T_1284, _T_1252)
node _T_1286 = or(_T_1285, _T_1257)
node _T_1287 = or(_T_1286, _T_1262)
node _T_1288 = or(_T_1287, _T_1267)
node _T_1289 = or(_T_1288, _T_1272)
node _T_1290 = or(_T_1289, _T_1277)
node _T_1291 = or(_T_1290, _T_1282)
node _T_1292 = and(_T_1232, _T_1291)
node _T_1293 = or(UInt<1>(0h0), _T_1292)
node _T_1294 = and(UInt<1>(0h0), _T_1293)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_93
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(address_ok, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(legal_source, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1307 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_97
node _T_1311 = eq(io.in.b.bits.mask, mask_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_98
node _T_1315 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_99
node _T_1319 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1321 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1322 = and(_T_1320, _T_1321)
node _T_1323 = or(UInt<1>(0h0), _T_1322)
node _T_1324 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<14>(0h2000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1330 = cvt(_T_1329)
node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000)))
node _T_1332 = asSInt(_T_1331)
node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0)))
node _T_1334 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1335 = cvt(_T_1334)
node _T_1336 = and(_T_1335, asSInt(UInt<17>(0h10000)))
node _T_1337 = asSInt(_T_1336)
node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0)))
node _T_1339 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1340 = cvt(_T_1339)
node _T_1341 = and(_T_1340, asSInt(UInt<18>(0h2f000)))
node _T_1342 = asSInt(_T_1341)
node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0)))
node _T_1344 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1345 = cvt(_T_1344)
node _T_1346 = and(_T_1345, asSInt(UInt<17>(0h10000)))
node _T_1347 = asSInt(_T_1346)
node _T_1348 = eq(_T_1347, asSInt(UInt<1>(0h0)))
node _T_1349 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1350 = cvt(_T_1349)
node _T_1351 = and(_T_1350, asSInt(UInt<13>(0h1000)))
node _T_1352 = asSInt(_T_1351)
node _T_1353 = eq(_T_1352, asSInt(UInt<1>(0h0)))
node _T_1354 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1355 = cvt(_T_1354)
node _T_1356 = and(_T_1355, asSInt(UInt<17>(0h10000)))
node _T_1357 = asSInt(_T_1356)
node _T_1358 = eq(_T_1357, asSInt(UInt<1>(0h0)))
node _T_1359 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1360 = cvt(_T_1359)
node _T_1361 = and(_T_1360, asSInt(UInt<27>(0h4000000)))
node _T_1362 = asSInt(_T_1361)
node _T_1363 = eq(_T_1362, asSInt(UInt<1>(0h0)))
node _T_1364 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1365 = cvt(_T_1364)
node _T_1366 = and(_T_1365, asSInt(UInt<13>(0h1000)))
node _T_1367 = asSInt(_T_1366)
node _T_1368 = eq(_T_1367, asSInt(UInt<1>(0h0)))
node _T_1369 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1370 = cvt(_T_1369)
node _T_1371 = and(_T_1370, asSInt(UInt<29>(0h10000000)))
node _T_1372 = asSInt(_T_1371)
node _T_1373 = eq(_T_1372, asSInt(UInt<1>(0h0)))
node _T_1374 = or(_T_1328, _T_1333)
node _T_1375 = or(_T_1374, _T_1338)
node _T_1376 = or(_T_1375, _T_1343)
node _T_1377 = or(_T_1376, _T_1348)
node _T_1378 = or(_T_1377, _T_1353)
node _T_1379 = or(_T_1378, _T_1358)
node _T_1380 = or(_T_1379, _T_1363)
node _T_1381 = or(_T_1380, _T_1368)
node _T_1382 = or(_T_1381, _T_1373)
node _T_1383 = and(_T_1323, _T_1382)
node _T_1384 = or(UInt<1>(0h0), _T_1383)
node _T_1385 = and(UInt<1>(0h0), _T_1384)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_100
node _T_1389 = asUInt(reset)
node _T_1390 = eq(_T_1389, UInt<1>(0h0))
when _T_1390 :
node _T_1391 = eq(address_ok, UInt<1>(0h0))
when _T_1391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(legal_source, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1395 = asUInt(reset)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
when _T_1396 :
node _T_1397 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1398 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_104
node _T_1402 = eq(io.in.b.bits.mask, mask_1)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_105
node _T_1406 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1406 :
node _T_1407 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1408 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1409 = and(_T_1407, _T_1408)
node _T_1410 = or(UInt<1>(0h0), _T_1409)
node _T_1411 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<14>(0h2000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1422 = cvt(_T_1421)
node _T_1423 = and(_T_1422, asSInt(UInt<17>(0h10000)))
node _T_1424 = asSInt(_T_1423)
node _T_1425 = eq(_T_1424, asSInt(UInt<1>(0h0)))
node _T_1426 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1427 = cvt(_T_1426)
node _T_1428 = and(_T_1427, asSInt(UInt<18>(0h2f000)))
node _T_1429 = asSInt(_T_1428)
node _T_1430 = eq(_T_1429, asSInt(UInt<1>(0h0)))
node _T_1431 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1432 = cvt(_T_1431)
node _T_1433 = and(_T_1432, asSInt(UInt<17>(0h10000)))
node _T_1434 = asSInt(_T_1433)
node _T_1435 = eq(_T_1434, asSInt(UInt<1>(0h0)))
node _T_1436 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1437 = cvt(_T_1436)
node _T_1438 = and(_T_1437, asSInt(UInt<13>(0h1000)))
node _T_1439 = asSInt(_T_1438)
node _T_1440 = eq(_T_1439, asSInt(UInt<1>(0h0)))
node _T_1441 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1442 = cvt(_T_1441)
node _T_1443 = and(_T_1442, asSInt(UInt<17>(0h10000)))
node _T_1444 = asSInt(_T_1443)
node _T_1445 = eq(_T_1444, asSInt(UInt<1>(0h0)))
node _T_1446 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1447 = cvt(_T_1446)
node _T_1448 = and(_T_1447, asSInt(UInt<27>(0h4000000)))
node _T_1449 = asSInt(_T_1448)
node _T_1450 = eq(_T_1449, asSInt(UInt<1>(0h0)))
node _T_1451 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1452 = cvt(_T_1451)
node _T_1453 = and(_T_1452, asSInt(UInt<13>(0h1000)))
node _T_1454 = asSInt(_T_1453)
node _T_1455 = eq(_T_1454, asSInt(UInt<1>(0h0)))
node _T_1456 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1457 = cvt(_T_1456)
node _T_1458 = and(_T_1457, asSInt(UInt<29>(0h10000000)))
node _T_1459 = asSInt(_T_1458)
node _T_1460 = eq(_T_1459, asSInt(UInt<1>(0h0)))
node _T_1461 = or(_T_1415, _T_1420)
node _T_1462 = or(_T_1461, _T_1425)
node _T_1463 = or(_T_1462, _T_1430)
node _T_1464 = or(_T_1463, _T_1435)
node _T_1465 = or(_T_1464, _T_1440)
node _T_1466 = or(_T_1465, _T_1445)
node _T_1467 = or(_T_1466, _T_1450)
node _T_1468 = or(_T_1467, _T_1455)
node _T_1469 = or(_T_1468, _T_1460)
node _T_1470 = and(_T_1410, _T_1469)
node _T_1471 = or(UInt<1>(0h0), _T_1470)
node _T_1472 = and(UInt<1>(0h0), _T_1471)
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_106
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(address_ok, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(legal_source, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1485 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_110
node _T_1489 = not(mask_1)
node _T_1490 = and(io.in.b.bits.mask, _T_1489)
node _T_1491 = eq(_T_1490, UInt<1>(0h0))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_111
node _T_1495 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1495 :
node _T_1496 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1497 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1498 = and(_T_1496, _T_1497)
node _T_1499 = or(UInt<1>(0h0), _T_1498)
node _T_1500 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1501 = cvt(_T_1500)
node _T_1502 = and(_T_1501, asSInt(UInt<14>(0h2000)))
node _T_1503 = asSInt(_T_1502)
node _T_1504 = eq(_T_1503, asSInt(UInt<1>(0h0)))
node _T_1505 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1506 = cvt(_T_1505)
node _T_1507 = and(_T_1506, asSInt(UInt<13>(0h1000)))
node _T_1508 = asSInt(_T_1507)
node _T_1509 = eq(_T_1508, asSInt(UInt<1>(0h0)))
node _T_1510 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1511 = cvt(_T_1510)
node _T_1512 = and(_T_1511, asSInt(UInt<17>(0h10000)))
node _T_1513 = asSInt(_T_1512)
node _T_1514 = eq(_T_1513, asSInt(UInt<1>(0h0)))
node _T_1515 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1516 = cvt(_T_1515)
node _T_1517 = and(_T_1516, asSInt(UInt<18>(0h2f000)))
node _T_1518 = asSInt(_T_1517)
node _T_1519 = eq(_T_1518, asSInt(UInt<1>(0h0)))
node _T_1520 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1521 = cvt(_T_1520)
node _T_1522 = and(_T_1521, asSInt(UInt<17>(0h10000)))
node _T_1523 = asSInt(_T_1522)
node _T_1524 = eq(_T_1523, asSInt(UInt<1>(0h0)))
node _T_1525 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1526 = cvt(_T_1525)
node _T_1527 = and(_T_1526, asSInt(UInt<13>(0h1000)))
node _T_1528 = asSInt(_T_1527)
node _T_1529 = eq(_T_1528, asSInt(UInt<1>(0h0)))
node _T_1530 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1531 = cvt(_T_1530)
node _T_1532 = and(_T_1531, asSInt(UInt<17>(0h10000)))
node _T_1533 = asSInt(_T_1532)
node _T_1534 = eq(_T_1533, asSInt(UInt<1>(0h0)))
node _T_1535 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1536 = cvt(_T_1535)
node _T_1537 = and(_T_1536, asSInt(UInt<27>(0h4000000)))
node _T_1538 = asSInt(_T_1537)
node _T_1539 = eq(_T_1538, asSInt(UInt<1>(0h0)))
node _T_1540 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1541 = cvt(_T_1540)
node _T_1542 = and(_T_1541, asSInt(UInt<13>(0h1000)))
node _T_1543 = asSInt(_T_1542)
node _T_1544 = eq(_T_1543, asSInt(UInt<1>(0h0)))
node _T_1545 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1546 = cvt(_T_1545)
node _T_1547 = and(_T_1546, asSInt(UInt<29>(0h10000000)))
node _T_1548 = asSInt(_T_1547)
node _T_1549 = eq(_T_1548, asSInt(UInt<1>(0h0)))
node _T_1550 = or(_T_1504, _T_1509)
node _T_1551 = or(_T_1550, _T_1514)
node _T_1552 = or(_T_1551, _T_1519)
node _T_1553 = or(_T_1552, _T_1524)
node _T_1554 = or(_T_1553, _T_1529)
node _T_1555 = or(_T_1554, _T_1534)
node _T_1556 = or(_T_1555, _T_1539)
node _T_1557 = or(_T_1556, _T_1544)
node _T_1558 = or(_T_1557, _T_1549)
node _T_1559 = and(_T_1499, _T_1558)
node _T_1560 = or(UInt<1>(0h0), _T_1559)
node _T_1561 = and(UInt<1>(0h0), _T_1560)
node _T_1562 = asUInt(reset)
node _T_1563 = eq(_T_1562, UInt<1>(0h0))
when _T_1563 :
node _T_1564 = eq(_T_1561, UInt<1>(0h0))
when _T_1564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1561, UInt<1>(0h1), "") : assert_112
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(address_ok, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(legal_source, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1571 = asUInt(reset)
node _T_1572 = eq(_T_1571, UInt<1>(0h0))
when _T_1572 :
node _T_1573 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1574 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_116
node _T_1578 = eq(io.in.b.bits.mask, mask_1)
node _T_1579 = asUInt(reset)
node _T_1580 = eq(_T_1579, UInt<1>(0h0))
when _T_1580 :
node _T_1581 = eq(_T_1578, UInt<1>(0h0))
when _T_1581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1578, UInt<1>(0h1), "") : assert_117
node _T_1582 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1582 :
node _T_1583 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1584 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1585 = and(_T_1583, _T_1584)
node _T_1586 = or(UInt<1>(0h0), _T_1585)
node _T_1587 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1588 = cvt(_T_1587)
node _T_1589 = and(_T_1588, asSInt(UInt<14>(0h2000)))
node _T_1590 = asSInt(_T_1589)
node _T_1591 = eq(_T_1590, asSInt(UInt<1>(0h0)))
node _T_1592 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1593 = cvt(_T_1592)
node _T_1594 = and(_T_1593, asSInt(UInt<13>(0h1000)))
node _T_1595 = asSInt(_T_1594)
node _T_1596 = eq(_T_1595, asSInt(UInt<1>(0h0)))
node _T_1597 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1598 = cvt(_T_1597)
node _T_1599 = and(_T_1598, asSInt(UInt<17>(0h10000)))
node _T_1600 = asSInt(_T_1599)
node _T_1601 = eq(_T_1600, asSInt(UInt<1>(0h0)))
node _T_1602 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1603 = cvt(_T_1602)
node _T_1604 = and(_T_1603, asSInt(UInt<18>(0h2f000)))
node _T_1605 = asSInt(_T_1604)
node _T_1606 = eq(_T_1605, asSInt(UInt<1>(0h0)))
node _T_1607 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1608 = cvt(_T_1607)
node _T_1609 = and(_T_1608, asSInt(UInt<17>(0h10000)))
node _T_1610 = asSInt(_T_1609)
node _T_1611 = eq(_T_1610, asSInt(UInt<1>(0h0)))
node _T_1612 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1613 = cvt(_T_1612)
node _T_1614 = and(_T_1613, asSInt(UInt<13>(0h1000)))
node _T_1615 = asSInt(_T_1614)
node _T_1616 = eq(_T_1615, asSInt(UInt<1>(0h0)))
node _T_1617 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1618 = cvt(_T_1617)
node _T_1619 = and(_T_1618, asSInt(UInt<17>(0h10000)))
node _T_1620 = asSInt(_T_1619)
node _T_1621 = eq(_T_1620, asSInt(UInt<1>(0h0)))
node _T_1622 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1623 = cvt(_T_1622)
node _T_1624 = and(_T_1623, asSInt(UInt<27>(0h4000000)))
node _T_1625 = asSInt(_T_1624)
node _T_1626 = eq(_T_1625, asSInt(UInt<1>(0h0)))
node _T_1627 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1628 = cvt(_T_1627)
node _T_1629 = and(_T_1628, asSInt(UInt<13>(0h1000)))
node _T_1630 = asSInt(_T_1629)
node _T_1631 = eq(_T_1630, asSInt(UInt<1>(0h0)))
node _T_1632 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1633 = cvt(_T_1632)
node _T_1634 = and(_T_1633, asSInt(UInt<29>(0h10000000)))
node _T_1635 = asSInt(_T_1634)
node _T_1636 = eq(_T_1635, asSInt(UInt<1>(0h0)))
node _T_1637 = or(_T_1591, _T_1596)
node _T_1638 = or(_T_1637, _T_1601)
node _T_1639 = or(_T_1638, _T_1606)
node _T_1640 = or(_T_1639, _T_1611)
node _T_1641 = or(_T_1640, _T_1616)
node _T_1642 = or(_T_1641, _T_1621)
node _T_1643 = or(_T_1642, _T_1626)
node _T_1644 = or(_T_1643, _T_1631)
node _T_1645 = or(_T_1644, _T_1636)
node _T_1646 = and(_T_1586, _T_1645)
node _T_1647 = or(UInt<1>(0h0), _T_1646)
node _T_1648 = and(UInt<1>(0h0), _T_1647)
node _T_1649 = asUInt(reset)
node _T_1650 = eq(_T_1649, UInt<1>(0h0))
when _T_1650 :
node _T_1651 = eq(_T_1648, UInt<1>(0h0))
when _T_1651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1648, UInt<1>(0h1), "") : assert_118
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(address_ok, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(legal_source, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1658 = asUInt(reset)
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
when _T_1659 :
node _T_1660 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1661 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1662 = asUInt(reset)
node _T_1663 = eq(_T_1662, UInt<1>(0h0))
when _T_1663 :
node _T_1664 = eq(_T_1661, UInt<1>(0h0))
when _T_1664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1661, UInt<1>(0h1), "") : assert_122
node _T_1665 = eq(io.in.b.bits.mask, mask_1)
node _T_1666 = asUInt(reset)
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
when _T_1667 :
node _T_1668 = eq(_T_1665, UInt<1>(0h0))
when _T_1668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1665, UInt<1>(0h1), "") : assert_123
node _T_1669 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1669 :
node _T_1670 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1671 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1672 = and(_T_1670, _T_1671)
node _T_1673 = or(UInt<1>(0h0), _T_1672)
node _T_1674 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1675 = cvt(_T_1674)
node _T_1676 = and(_T_1675, asSInt(UInt<14>(0h2000)))
node _T_1677 = asSInt(_T_1676)
node _T_1678 = eq(_T_1677, asSInt(UInt<1>(0h0)))
node _T_1679 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1680 = cvt(_T_1679)
node _T_1681 = and(_T_1680, asSInt(UInt<13>(0h1000)))
node _T_1682 = asSInt(_T_1681)
node _T_1683 = eq(_T_1682, asSInt(UInt<1>(0h0)))
node _T_1684 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1685 = cvt(_T_1684)
node _T_1686 = and(_T_1685, asSInt(UInt<17>(0h10000)))
node _T_1687 = asSInt(_T_1686)
node _T_1688 = eq(_T_1687, asSInt(UInt<1>(0h0)))
node _T_1689 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1690 = cvt(_T_1689)
node _T_1691 = and(_T_1690, asSInt(UInt<18>(0h2f000)))
node _T_1692 = asSInt(_T_1691)
node _T_1693 = eq(_T_1692, asSInt(UInt<1>(0h0)))
node _T_1694 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1695 = cvt(_T_1694)
node _T_1696 = and(_T_1695, asSInt(UInt<17>(0h10000)))
node _T_1697 = asSInt(_T_1696)
node _T_1698 = eq(_T_1697, asSInt(UInt<1>(0h0)))
node _T_1699 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1700 = cvt(_T_1699)
node _T_1701 = and(_T_1700, asSInt(UInt<13>(0h1000)))
node _T_1702 = asSInt(_T_1701)
node _T_1703 = eq(_T_1702, asSInt(UInt<1>(0h0)))
node _T_1704 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1705 = cvt(_T_1704)
node _T_1706 = and(_T_1705, asSInt(UInt<17>(0h10000)))
node _T_1707 = asSInt(_T_1706)
node _T_1708 = eq(_T_1707, asSInt(UInt<1>(0h0)))
node _T_1709 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1710 = cvt(_T_1709)
node _T_1711 = and(_T_1710, asSInt(UInt<27>(0h4000000)))
node _T_1712 = asSInt(_T_1711)
node _T_1713 = eq(_T_1712, asSInt(UInt<1>(0h0)))
node _T_1714 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1715 = cvt(_T_1714)
node _T_1716 = and(_T_1715, asSInt(UInt<13>(0h1000)))
node _T_1717 = asSInt(_T_1716)
node _T_1718 = eq(_T_1717, asSInt(UInt<1>(0h0)))
node _T_1719 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1720 = cvt(_T_1719)
node _T_1721 = and(_T_1720, asSInt(UInt<29>(0h10000000)))
node _T_1722 = asSInt(_T_1721)
node _T_1723 = eq(_T_1722, asSInt(UInt<1>(0h0)))
node _T_1724 = or(_T_1678, _T_1683)
node _T_1725 = or(_T_1724, _T_1688)
node _T_1726 = or(_T_1725, _T_1693)
node _T_1727 = or(_T_1726, _T_1698)
node _T_1728 = or(_T_1727, _T_1703)
node _T_1729 = or(_T_1728, _T_1708)
node _T_1730 = or(_T_1729, _T_1713)
node _T_1731 = or(_T_1730, _T_1718)
node _T_1732 = or(_T_1731, _T_1723)
node _T_1733 = and(_T_1673, _T_1732)
node _T_1734 = or(UInt<1>(0h0), _T_1733)
node _T_1735 = and(UInt<1>(0h0), _T_1734)
node _T_1736 = asUInt(reset)
node _T_1737 = eq(_T_1736, UInt<1>(0h0))
when _T_1737 :
node _T_1738 = eq(_T_1735, UInt<1>(0h0))
when _T_1738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1735, UInt<1>(0h1), "") : assert_124
node _T_1739 = asUInt(reset)
node _T_1740 = eq(_T_1739, UInt<1>(0h0))
when _T_1740 :
node _T_1741 = eq(address_ok, UInt<1>(0h0))
when _T_1741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1742 = asUInt(reset)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
when _T_1743 :
node _T_1744 = eq(legal_source, UInt<1>(0h0))
when _T_1744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1745 = asUInt(reset)
node _T_1746 = eq(_T_1745, UInt<1>(0h0))
when _T_1746 :
node _T_1747 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1748 = eq(io.in.b.bits.mask, mask_1)
node _T_1749 = asUInt(reset)
node _T_1750 = eq(_T_1749, UInt<1>(0h0))
when _T_1750 :
node _T_1751 = eq(_T_1748, UInt<1>(0h0))
when _T_1751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1748, UInt<1>(0h1), "") : assert_128
node _T_1752 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1753 = asUInt(reset)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
when _T_1754 :
node _T_1755 = eq(_T_1752, UInt<1>(0h0))
when _T_1755 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1752, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1756 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_130
node _source_ok_T_4 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _source_ok_WIRE_2 : UInt<1>[2]
connect _source_ok_WIRE_2[0], _source_ok_T_4
connect _source_ok_WIRE_2[1], _source_ok_T_5
node source_ok_2 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1760 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
node _T_1762 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1763 = cvt(_T_1762)
node _T_1764 = and(_T_1763, asSInt(UInt<1>(0h0)))
node _T_1765 = asSInt(_T_1764)
node _T_1766 = eq(_T_1765, asSInt(UInt<1>(0h0)))
node _T_1767 = or(_T_1761, _T_1766)
node _T_1768 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
node _T_1770 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1771 = cvt(_T_1770)
node _T_1772 = and(_T_1771, asSInt(UInt<1>(0h0)))
node _T_1773 = asSInt(_T_1772)
node _T_1774 = eq(_T_1773, asSInt(UInt<1>(0h0)))
node _T_1775 = or(_T_1769, _T_1774)
node _T_1776 = and(_T_1767, _T_1775)
node _T_1777 = asUInt(reset)
node _T_1778 = eq(_T_1777, UInt<1>(0h0))
when _T_1778 :
node _T_1779 = eq(_T_1776, UInt<1>(0h0))
when _T_1779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1776, UInt<1>(0h1), "") : assert_131
node _T_1780 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1780 :
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(address_ok_1, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1784 = asUInt(reset)
node _T_1785 = eq(_T_1784, UInt<1>(0h0))
when _T_1785 :
node _T_1786 = eq(source_ok_2, UInt<1>(0h0))
when _T_1786 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1787 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(_T_1787, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1787, UInt<1>(0h1), "") : assert_134
node _T_1791 = asUInt(reset)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
when _T_1792 :
node _T_1793 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1794 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(_T_1794, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1794, UInt<1>(0h1), "") : assert_136
node _T_1798 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_137
node _T_1802 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1802 :
node _T_1803 = asUInt(reset)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
when _T_1804 :
node _T_1805 = eq(address_ok_1, UInt<1>(0h0))
when _T_1805 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1806 = asUInt(reset)
node _T_1807 = eq(_T_1806, UInt<1>(0h0))
when _T_1807 :
node _T_1808 = eq(source_ok_2, UInt<1>(0h0))
when _T_1808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1809 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1810 = asUInt(reset)
node _T_1811 = eq(_T_1810, UInt<1>(0h0))
when _T_1811 :
node _T_1812 = eq(_T_1809, UInt<1>(0h0))
when _T_1812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1809, UInt<1>(0h1), "") : assert_140
node _T_1813 = asUInt(reset)
node _T_1814 = eq(_T_1813, UInt<1>(0h0))
when _T_1814 :
node _T_1815 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1816 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1817 = asUInt(reset)
node _T_1818 = eq(_T_1817, UInt<1>(0h0))
when _T_1818 :
node _T_1819 = eq(_T_1816, UInt<1>(0h0))
when _T_1819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1816, UInt<1>(0h1), "") : assert_142
node _T_1820 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1820 :
node _T_1821 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1822 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1823 = and(_T_1821, _T_1822)
node _T_1824 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1825 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1826 = or(_T_1824, _T_1825)
node _T_1827 = and(_T_1823, _T_1826)
node _T_1828 = or(UInt<1>(0h0), _T_1827)
node _T_1829 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1830 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1831 = cvt(_T_1830)
node _T_1832 = and(_T_1831, asSInt(UInt<14>(0h2000)))
node _T_1833 = asSInt(_T_1832)
node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0)))
node _T_1835 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1836 = cvt(_T_1835)
node _T_1837 = and(_T_1836, asSInt(UInt<13>(0h1000)))
node _T_1838 = asSInt(_T_1837)
node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0)))
node _T_1840 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1841 = cvt(_T_1840)
node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000)))
node _T_1843 = asSInt(_T_1842)
node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0)))
node _T_1845 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1846 = cvt(_T_1845)
node _T_1847 = and(_T_1846, asSInt(UInt<18>(0h2f000)))
node _T_1848 = asSInt(_T_1847)
node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0)))
node _T_1850 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1851 = cvt(_T_1850)
node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000)))
node _T_1853 = asSInt(_T_1852)
node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0)))
node _T_1855 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1856 = cvt(_T_1855)
node _T_1857 = and(_T_1856, asSInt(UInt<13>(0h1000)))
node _T_1858 = asSInt(_T_1857)
node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0)))
node _T_1860 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1861 = cvt(_T_1860)
node _T_1862 = and(_T_1861, asSInt(UInt<27>(0h4000000)))
node _T_1863 = asSInt(_T_1862)
node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0)))
node _T_1865 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1866 = cvt(_T_1865)
node _T_1867 = and(_T_1866, asSInt(UInt<13>(0h1000)))
node _T_1868 = asSInt(_T_1867)
node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0)))
node _T_1870 = or(_T_1834, _T_1839)
node _T_1871 = or(_T_1870, _T_1844)
node _T_1872 = or(_T_1871, _T_1849)
node _T_1873 = or(_T_1872, _T_1854)
node _T_1874 = or(_T_1873, _T_1859)
node _T_1875 = or(_T_1874, _T_1864)
node _T_1876 = or(_T_1875, _T_1869)
node _T_1877 = and(_T_1829, _T_1876)
node _T_1878 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1879 = or(UInt<1>(0h0), _T_1878)
node _T_1880 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1881 = cvt(_T_1880)
node _T_1882 = and(_T_1881, asSInt(UInt<17>(0h10000)))
node _T_1883 = asSInt(_T_1882)
node _T_1884 = eq(_T_1883, asSInt(UInt<1>(0h0)))
node _T_1885 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1886 = cvt(_T_1885)
node _T_1887 = and(_T_1886, asSInt(UInt<29>(0h10000000)))
node _T_1888 = asSInt(_T_1887)
node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0)))
node _T_1890 = or(_T_1884, _T_1889)
node _T_1891 = and(_T_1879, _T_1890)
node _T_1892 = or(UInt<1>(0h0), _T_1877)
node _T_1893 = or(_T_1892, _T_1891)
node _T_1894 = and(_T_1828, _T_1893)
node _T_1895 = asUInt(reset)
node _T_1896 = eq(_T_1895, UInt<1>(0h0))
when _T_1896 :
node _T_1897 = eq(_T_1894, UInt<1>(0h0))
when _T_1897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_1894, UInt<1>(0h1), "") : assert_143
node _T_1898 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1899 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_6 : UInt<1>[2]
connect _WIRE_6[0], _T_1898
connect _WIRE_6[1], _T_1899
node _T_1900 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_1901 = mux(_WIRE_6[0], _T_1900, UInt<1>(0h0))
node _T_1902 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1903 = or(_T_1901, _T_1902)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_1903
node _T_1904 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1905 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1906 = and(_T_1904, _T_1905)
node _T_1907 = or(UInt<1>(0h0), _T_1906)
node _T_1908 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1909 = cvt(_T_1908)
node _T_1910 = and(_T_1909, asSInt(UInt<14>(0h2000)))
node _T_1911 = asSInt(_T_1910)
node _T_1912 = eq(_T_1911, asSInt(UInt<1>(0h0)))
node _T_1913 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1914 = cvt(_T_1913)
node _T_1915 = and(_T_1914, asSInt(UInt<13>(0h1000)))
node _T_1916 = asSInt(_T_1915)
node _T_1917 = eq(_T_1916, asSInt(UInt<1>(0h0)))
node _T_1918 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1919 = cvt(_T_1918)
node _T_1920 = and(_T_1919, asSInt(UInt<17>(0h10000)))
node _T_1921 = asSInt(_T_1920)
node _T_1922 = eq(_T_1921, asSInt(UInt<1>(0h0)))
node _T_1923 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1924 = cvt(_T_1923)
node _T_1925 = and(_T_1924, asSInt(UInt<18>(0h2f000)))
node _T_1926 = asSInt(_T_1925)
node _T_1927 = eq(_T_1926, asSInt(UInt<1>(0h0)))
node _T_1928 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1929 = cvt(_T_1928)
node _T_1930 = and(_T_1929, asSInt(UInt<17>(0h10000)))
node _T_1931 = asSInt(_T_1930)
node _T_1932 = eq(_T_1931, asSInt(UInt<1>(0h0)))
node _T_1933 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1934 = cvt(_T_1933)
node _T_1935 = and(_T_1934, asSInt(UInt<13>(0h1000)))
node _T_1936 = asSInt(_T_1935)
node _T_1937 = eq(_T_1936, asSInt(UInt<1>(0h0)))
node _T_1938 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_1939 = cvt(_T_1938)
node _T_1940 = and(_T_1939, asSInt(UInt<17>(0h10000)))
node _T_1941 = asSInt(_T_1940)
node _T_1942 = eq(_T_1941, asSInt(UInt<1>(0h0)))
node _T_1943 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1944 = cvt(_T_1943)
node _T_1945 = and(_T_1944, asSInt(UInt<27>(0h4000000)))
node _T_1946 = asSInt(_T_1945)
node _T_1947 = eq(_T_1946, asSInt(UInt<1>(0h0)))
node _T_1948 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1949 = cvt(_T_1948)
node _T_1950 = and(_T_1949, asSInt(UInt<13>(0h1000)))
node _T_1951 = asSInt(_T_1950)
node _T_1952 = eq(_T_1951, asSInt(UInt<1>(0h0)))
node _T_1953 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_1954 = cvt(_T_1953)
node _T_1955 = and(_T_1954, asSInt(UInt<29>(0h10000000)))
node _T_1956 = asSInt(_T_1955)
node _T_1957 = eq(_T_1956, asSInt(UInt<1>(0h0)))
node _T_1958 = or(_T_1912, _T_1917)
node _T_1959 = or(_T_1958, _T_1922)
node _T_1960 = or(_T_1959, _T_1927)
node _T_1961 = or(_T_1960, _T_1932)
node _T_1962 = or(_T_1961, _T_1937)
node _T_1963 = or(_T_1962, _T_1942)
node _T_1964 = or(_T_1963, _T_1947)
node _T_1965 = or(_T_1964, _T_1952)
node _T_1966 = or(_T_1965, _T_1957)
node _T_1967 = and(_T_1907, _T_1966)
node _T_1968 = or(UInt<1>(0h0), _T_1967)
node _T_1969 = and(_WIRE_7, _T_1968)
node _T_1970 = asUInt(reset)
node _T_1971 = eq(_T_1970, UInt<1>(0h0))
when _T_1971 :
node _T_1972 = eq(_T_1969, UInt<1>(0h0))
when _T_1972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_1969, UInt<1>(0h1), "") : assert_144
node _T_1973 = asUInt(reset)
node _T_1974 = eq(_T_1973, UInt<1>(0h0))
when _T_1974 :
node _T_1975 = eq(source_ok_2, UInt<1>(0h0))
when _T_1975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_1976 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1977 = asUInt(reset)
node _T_1978 = eq(_T_1977, UInt<1>(0h0))
when _T_1978 :
node _T_1979 = eq(_T_1976, UInt<1>(0h0))
when _T_1979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_1976, UInt<1>(0h1), "") : assert_146
node _T_1980 = asUInt(reset)
node _T_1981 = eq(_T_1980, UInt<1>(0h0))
when _T_1981 :
node _T_1982 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_1983 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1984 = asUInt(reset)
node _T_1985 = eq(_T_1984, UInt<1>(0h0))
when _T_1985 :
node _T_1986 = eq(_T_1983, UInt<1>(0h0))
when _T_1986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_1983, UInt<1>(0h1), "") : assert_148
node _T_1987 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1988 = asUInt(reset)
node _T_1989 = eq(_T_1988, UInt<1>(0h0))
when _T_1989 :
node _T_1990 = eq(_T_1987, UInt<1>(0h0))
when _T_1990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_1987, UInt<1>(0h1), "") : assert_149
node _T_1991 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_1991 :
node _T_1992 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1993 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1994 = and(_T_1992, _T_1993)
node _T_1995 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_1996 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_1997 = or(_T_1995, _T_1996)
node _T_1998 = and(_T_1994, _T_1997)
node _T_1999 = or(UInt<1>(0h0), _T_1998)
node _T_2000 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2001 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2002 = cvt(_T_2001)
node _T_2003 = and(_T_2002, asSInt(UInt<14>(0h2000)))
node _T_2004 = asSInt(_T_2003)
node _T_2005 = eq(_T_2004, asSInt(UInt<1>(0h0)))
node _T_2006 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2007 = cvt(_T_2006)
node _T_2008 = and(_T_2007, asSInt(UInt<13>(0h1000)))
node _T_2009 = asSInt(_T_2008)
node _T_2010 = eq(_T_2009, asSInt(UInt<1>(0h0)))
node _T_2011 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2012 = cvt(_T_2011)
node _T_2013 = and(_T_2012, asSInt(UInt<17>(0h10000)))
node _T_2014 = asSInt(_T_2013)
node _T_2015 = eq(_T_2014, asSInt(UInt<1>(0h0)))
node _T_2016 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2017 = cvt(_T_2016)
node _T_2018 = and(_T_2017, asSInt(UInt<18>(0h2f000)))
node _T_2019 = asSInt(_T_2018)
node _T_2020 = eq(_T_2019, asSInt(UInt<1>(0h0)))
node _T_2021 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2022 = cvt(_T_2021)
node _T_2023 = and(_T_2022, asSInt(UInt<17>(0h10000)))
node _T_2024 = asSInt(_T_2023)
node _T_2025 = eq(_T_2024, asSInt(UInt<1>(0h0)))
node _T_2026 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2027 = cvt(_T_2026)
node _T_2028 = and(_T_2027, asSInt(UInt<13>(0h1000)))
node _T_2029 = asSInt(_T_2028)
node _T_2030 = eq(_T_2029, asSInt(UInt<1>(0h0)))
node _T_2031 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2032 = cvt(_T_2031)
node _T_2033 = and(_T_2032, asSInt(UInt<27>(0h4000000)))
node _T_2034 = asSInt(_T_2033)
node _T_2035 = eq(_T_2034, asSInt(UInt<1>(0h0)))
node _T_2036 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2037 = cvt(_T_2036)
node _T_2038 = and(_T_2037, asSInt(UInt<13>(0h1000)))
node _T_2039 = asSInt(_T_2038)
node _T_2040 = eq(_T_2039, asSInt(UInt<1>(0h0)))
node _T_2041 = or(_T_2005, _T_2010)
node _T_2042 = or(_T_2041, _T_2015)
node _T_2043 = or(_T_2042, _T_2020)
node _T_2044 = or(_T_2043, _T_2025)
node _T_2045 = or(_T_2044, _T_2030)
node _T_2046 = or(_T_2045, _T_2035)
node _T_2047 = or(_T_2046, _T_2040)
node _T_2048 = and(_T_2000, _T_2047)
node _T_2049 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2050 = or(UInt<1>(0h0), _T_2049)
node _T_2051 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2052 = cvt(_T_2051)
node _T_2053 = and(_T_2052, asSInt(UInt<17>(0h10000)))
node _T_2054 = asSInt(_T_2053)
node _T_2055 = eq(_T_2054, asSInt(UInt<1>(0h0)))
node _T_2056 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2057 = cvt(_T_2056)
node _T_2058 = and(_T_2057, asSInt(UInt<29>(0h10000000)))
node _T_2059 = asSInt(_T_2058)
node _T_2060 = eq(_T_2059, asSInt(UInt<1>(0h0)))
node _T_2061 = or(_T_2055, _T_2060)
node _T_2062 = and(_T_2050, _T_2061)
node _T_2063 = or(UInt<1>(0h0), _T_2048)
node _T_2064 = or(_T_2063, _T_2062)
node _T_2065 = and(_T_1999, _T_2064)
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_150
node _T_2069 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2070 = eq(io.in.c.bits.source, UInt<1>(0h1))
wire _WIRE_8 : UInt<1>[2]
connect _WIRE_8[0], _T_2069
connect _WIRE_8[1], _T_2070
node _T_2071 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2072 = mux(_WIRE_8[0], _T_2071, UInt<1>(0h0))
node _T_2073 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2074 = or(_T_2072, _T_2073)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2074
node _T_2075 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2076 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2077 = and(_T_2075, _T_2076)
node _T_2078 = or(UInt<1>(0h0), _T_2077)
node _T_2079 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2080 = cvt(_T_2079)
node _T_2081 = and(_T_2080, asSInt(UInt<14>(0h2000)))
node _T_2082 = asSInt(_T_2081)
node _T_2083 = eq(_T_2082, asSInt(UInt<1>(0h0)))
node _T_2084 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2085 = cvt(_T_2084)
node _T_2086 = and(_T_2085, asSInt(UInt<13>(0h1000)))
node _T_2087 = asSInt(_T_2086)
node _T_2088 = eq(_T_2087, asSInt(UInt<1>(0h0)))
node _T_2089 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2090 = cvt(_T_2089)
node _T_2091 = and(_T_2090, asSInt(UInt<17>(0h10000)))
node _T_2092 = asSInt(_T_2091)
node _T_2093 = eq(_T_2092, asSInt(UInt<1>(0h0)))
node _T_2094 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2095 = cvt(_T_2094)
node _T_2096 = and(_T_2095, asSInt(UInt<18>(0h2f000)))
node _T_2097 = asSInt(_T_2096)
node _T_2098 = eq(_T_2097, asSInt(UInt<1>(0h0)))
node _T_2099 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2100 = cvt(_T_2099)
node _T_2101 = and(_T_2100, asSInt(UInt<17>(0h10000)))
node _T_2102 = asSInt(_T_2101)
node _T_2103 = eq(_T_2102, asSInt(UInt<1>(0h0)))
node _T_2104 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2105 = cvt(_T_2104)
node _T_2106 = and(_T_2105, asSInt(UInt<13>(0h1000)))
node _T_2107 = asSInt(_T_2106)
node _T_2108 = eq(_T_2107, asSInt(UInt<1>(0h0)))
node _T_2109 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2110 = cvt(_T_2109)
node _T_2111 = and(_T_2110, asSInt(UInt<17>(0h10000)))
node _T_2112 = asSInt(_T_2111)
node _T_2113 = eq(_T_2112, asSInt(UInt<1>(0h0)))
node _T_2114 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2115 = cvt(_T_2114)
node _T_2116 = and(_T_2115, asSInt(UInt<27>(0h4000000)))
node _T_2117 = asSInt(_T_2116)
node _T_2118 = eq(_T_2117, asSInt(UInt<1>(0h0)))
node _T_2119 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2120 = cvt(_T_2119)
node _T_2121 = and(_T_2120, asSInt(UInt<13>(0h1000)))
node _T_2122 = asSInt(_T_2121)
node _T_2123 = eq(_T_2122, asSInt(UInt<1>(0h0)))
node _T_2124 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2125 = cvt(_T_2124)
node _T_2126 = and(_T_2125, asSInt(UInt<29>(0h10000000)))
node _T_2127 = asSInt(_T_2126)
node _T_2128 = eq(_T_2127, asSInt(UInt<1>(0h0)))
node _T_2129 = or(_T_2083, _T_2088)
node _T_2130 = or(_T_2129, _T_2093)
node _T_2131 = or(_T_2130, _T_2098)
node _T_2132 = or(_T_2131, _T_2103)
node _T_2133 = or(_T_2132, _T_2108)
node _T_2134 = or(_T_2133, _T_2113)
node _T_2135 = or(_T_2134, _T_2118)
node _T_2136 = or(_T_2135, _T_2123)
node _T_2137 = or(_T_2136, _T_2128)
node _T_2138 = and(_T_2078, _T_2137)
node _T_2139 = or(UInt<1>(0h0), _T_2138)
node _T_2140 = and(_WIRE_9, _T_2139)
node _T_2141 = asUInt(reset)
node _T_2142 = eq(_T_2141, UInt<1>(0h0))
when _T_2142 :
node _T_2143 = eq(_T_2140, UInt<1>(0h0))
when _T_2143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2140, UInt<1>(0h1), "") : assert_151
node _T_2144 = asUInt(reset)
node _T_2145 = eq(_T_2144, UInt<1>(0h0))
when _T_2145 :
node _T_2146 = eq(source_ok_2, UInt<1>(0h0))
when _T_2146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2147 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2148 = asUInt(reset)
node _T_2149 = eq(_T_2148, UInt<1>(0h0))
when _T_2149 :
node _T_2150 = eq(_T_2147, UInt<1>(0h0))
when _T_2150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2147, UInt<1>(0h1), "") : assert_153
node _T_2151 = asUInt(reset)
node _T_2152 = eq(_T_2151, UInt<1>(0h0))
when _T_2152 :
node _T_2153 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2154 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2155 = asUInt(reset)
node _T_2156 = eq(_T_2155, UInt<1>(0h0))
when _T_2156 :
node _T_2157 = eq(_T_2154, UInt<1>(0h0))
when _T_2157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2154, UInt<1>(0h1), "") : assert_155
node _T_2158 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2158 :
node _T_2159 = asUInt(reset)
node _T_2160 = eq(_T_2159, UInt<1>(0h0))
when _T_2160 :
node _T_2161 = eq(address_ok_1, UInt<1>(0h0))
when _T_2161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2162 = asUInt(reset)
node _T_2163 = eq(_T_2162, UInt<1>(0h0))
when _T_2163 :
node _T_2164 = eq(source_ok_2, UInt<1>(0h0))
when _T_2164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2165 = asUInt(reset)
node _T_2166 = eq(_T_2165, UInt<1>(0h0))
when _T_2166 :
node _T_2167 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2168 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2169 = asUInt(reset)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
when _T_2170 :
node _T_2171 = eq(_T_2168, UInt<1>(0h0))
when _T_2171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2168, UInt<1>(0h1), "") : assert_159
node _T_2172 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2173 = asUInt(reset)
node _T_2174 = eq(_T_2173, UInt<1>(0h0))
when _T_2174 :
node _T_2175 = eq(_T_2172, UInt<1>(0h0))
when _T_2175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2172, UInt<1>(0h1), "") : assert_160
node _T_2176 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2176 :
node _T_2177 = asUInt(reset)
node _T_2178 = eq(_T_2177, UInt<1>(0h0))
when _T_2178 :
node _T_2179 = eq(address_ok_1, UInt<1>(0h0))
when _T_2179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2180 = asUInt(reset)
node _T_2181 = eq(_T_2180, UInt<1>(0h0))
when _T_2181 :
node _T_2182 = eq(source_ok_2, UInt<1>(0h0))
when _T_2182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2183 = asUInt(reset)
node _T_2184 = eq(_T_2183, UInt<1>(0h0))
when _T_2184 :
node _T_2185 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2186 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2187 = asUInt(reset)
node _T_2188 = eq(_T_2187, UInt<1>(0h0))
when _T_2188 :
node _T_2189 = eq(_T_2186, UInt<1>(0h0))
when _T_2189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2186, UInt<1>(0h1), "") : assert_164
node _T_2190 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2190 :
node _T_2191 = asUInt(reset)
node _T_2192 = eq(_T_2191, UInt<1>(0h0))
when _T_2192 :
node _T_2193 = eq(address_ok_1, UInt<1>(0h0))
when _T_2193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2194 = asUInt(reset)
node _T_2195 = eq(_T_2194, UInt<1>(0h0))
when _T_2195 :
node _T_2196 = eq(source_ok_2, UInt<1>(0h0))
when _T_2196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2197 = asUInt(reset)
node _T_2198 = eq(_T_2197, UInt<1>(0h0))
when _T_2198 :
node _T_2199 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2200 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2201 = asUInt(reset)
node _T_2202 = eq(_T_2201, UInt<1>(0h0))
when _T_2202 :
node _T_2203 = eq(_T_2200, UInt<1>(0h0))
when _T_2203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2200, UInt<1>(0h1), "") : assert_168
node _T_2204 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2205 = asUInt(reset)
node _T_2206 = eq(_T_2205, UInt<1>(0h0))
when _T_2206 :
node _T_2207 = eq(_T_2204, UInt<1>(0h0))
when _T_2207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2204, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2208 = asUInt(reset)
node _T_2209 = eq(_T_2208, UInt<1>(0h0))
when _T_2209 :
node _T_2210 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2210 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2211 = eq(a_first, UInt<1>(0h0))
node _T_2212 = and(io.in.a.valid, _T_2211)
when _T_2212 :
node _T_2213 = eq(io.in.a.bits.opcode, opcode)
node _T_2214 = asUInt(reset)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
when _T_2215 :
node _T_2216 = eq(_T_2213, UInt<1>(0h0))
when _T_2216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2213, UInt<1>(0h1), "") : assert_171
node _T_2217 = eq(io.in.a.bits.param, param)
node _T_2218 = asUInt(reset)
node _T_2219 = eq(_T_2218, UInt<1>(0h0))
when _T_2219 :
node _T_2220 = eq(_T_2217, UInt<1>(0h0))
when _T_2220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2217, UInt<1>(0h1), "") : assert_172
node _T_2221 = eq(io.in.a.bits.size, size)
node _T_2222 = asUInt(reset)
node _T_2223 = eq(_T_2222, UInt<1>(0h0))
when _T_2223 :
node _T_2224 = eq(_T_2221, UInt<1>(0h0))
when _T_2224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2221, UInt<1>(0h1), "") : assert_173
node _T_2225 = eq(io.in.a.bits.source, source)
node _T_2226 = asUInt(reset)
node _T_2227 = eq(_T_2226, UInt<1>(0h0))
when _T_2227 :
node _T_2228 = eq(_T_2225, UInt<1>(0h0))
when _T_2228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2225, UInt<1>(0h1), "") : assert_174
node _T_2229 = eq(io.in.a.bits.address, address)
node _T_2230 = asUInt(reset)
node _T_2231 = eq(_T_2230, UInt<1>(0h0))
when _T_2231 :
node _T_2232 = eq(_T_2229, UInt<1>(0h0))
when _T_2232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2229, UInt<1>(0h1), "") : assert_175
node _T_2233 = and(io.in.a.ready, io.in.a.valid)
node _T_2234 = and(_T_2233, a_first)
when _T_2234 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2235 = eq(d_first, UInt<1>(0h0))
node _T_2236 = and(io.in.d.valid, _T_2235)
when _T_2236 :
node _T_2237 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2238 = asUInt(reset)
node _T_2239 = eq(_T_2238, UInt<1>(0h0))
when _T_2239 :
node _T_2240 = eq(_T_2237, UInt<1>(0h0))
when _T_2240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2237, UInt<1>(0h1), "") : assert_176
node _T_2241 = eq(io.in.d.bits.param, param_1)
node _T_2242 = asUInt(reset)
node _T_2243 = eq(_T_2242, UInt<1>(0h0))
when _T_2243 :
node _T_2244 = eq(_T_2241, UInt<1>(0h0))
when _T_2244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2241, UInt<1>(0h1), "") : assert_177
node _T_2245 = eq(io.in.d.bits.size, size_1)
node _T_2246 = asUInt(reset)
node _T_2247 = eq(_T_2246, UInt<1>(0h0))
when _T_2247 :
node _T_2248 = eq(_T_2245, UInt<1>(0h0))
when _T_2248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2245, UInt<1>(0h1), "") : assert_178
node _T_2249 = eq(io.in.d.bits.source, source_1)
node _T_2250 = asUInt(reset)
node _T_2251 = eq(_T_2250, UInt<1>(0h0))
when _T_2251 :
node _T_2252 = eq(_T_2249, UInt<1>(0h0))
when _T_2252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2249, UInt<1>(0h1), "") : assert_179
node _T_2253 = eq(io.in.d.bits.sink, sink)
node _T_2254 = asUInt(reset)
node _T_2255 = eq(_T_2254, UInt<1>(0h0))
when _T_2255 :
node _T_2256 = eq(_T_2253, UInt<1>(0h0))
when _T_2256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2253, UInt<1>(0h1), "") : assert_180
node _T_2257 = eq(io.in.d.bits.denied, denied)
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(_T_2257, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2257, UInt<1>(0h1), "") : assert_181
node _T_2261 = and(io.in.d.ready, io.in.d.valid)
node _T_2262 = and(_T_2261, d_first)
when _T_2262 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2263 = eq(b_first, UInt<1>(0h0))
node _T_2264 = and(io.in.b.valid, _T_2263)
when _T_2264 :
node _T_2265 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2266 = asUInt(reset)
node _T_2267 = eq(_T_2266, UInt<1>(0h0))
when _T_2267 :
node _T_2268 = eq(_T_2265, UInt<1>(0h0))
when _T_2268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2265, UInt<1>(0h1), "") : assert_182
node _T_2269 = eq(io.in.b.bits.param, param_2)
node _T_2270 = asUInt(reset)
node _T_2271 = eq(_T_2270, UInt<1>(0h0))
when _T_2271 :
node _T_2272 = eq(_T_2269, UInt<1>(0h0))
when _T_2272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2269, UInt<1>(0h1), "") : assert_183
node _T_2273 = eq(io.in.b.bits.size, size_2)
node _T_2274 = asUInt(reset)
node _T_2275 = eq(_T_2274, UInt<1>(0h0))
when _T_2275 :
node _T_2276 = eq(_T_2273, UInt<1>(0h0))
when _T_2276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2273, UInt<1>(0h1), "") : assert_184
node _T_2277 = eq(io.in.b.bits.source, source_2)
node _T_2278 = asUInt(reset)
node _T_2279 = eq(_T_2278, UInt<1>(0h0))
when _T_2279 :
node _T_2280 = eq(_T_2277, UInt<1>(0h0))
when _T_2280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2277, UInt<1>(0h1), "") : assert_185
node _T_2281 = eq(io.in.b.bits.address, address_1)
node _T_2282 = asUInt(reset)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
node _T_2284 = eq(_T_2281, UInt<1>(0h0))
when _T_2284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2281, UInt<1>(0h1), "") : assert_186
node _T_2285 = and(io.in.b.ready, io.in.b.valid)
node _T_2286 = and(_T_2285, b_first)
when _T_2286 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2287 = eq(c_first, UInt<1>(0h0))
node _T_2288 = and(io.in.c.valid, _T_2287)
when _T_2288 :
node _T_2289 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2290 = asUInt(reset)
node _T_2291 = eq(_T_2290, UInt<1>(0h0))
when _T_2291 :
node _T_2292 = eq(_T_2289, UInt<1>(0h0))
when _T_2292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2289, UInt<1>(0h1), "") : assert_187
node _T_2293 = eq(io.in.c.bits.param, param_3)
node _T_2294 = asUInt(reset)
node _T_2295 = eq(_T_2294, UInt<1>(0h0))
when _T_2295 :
node _T_2296 = eq(_T_2293, UInt<1>(0h0))
when _T_2296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2293, UInt<1>(0h1), "") : assert_188
node _T_2297 = eq(io.in.c.bits.size, size_3)
node _T_2298 = asUInt(reset)
node _T_2299 = eq(_T_2298, UInt<1>(0h0))
when _T_2299 :
node _T_2300 = eq(_T_2297, UInt<1>(0h0))
when _T_2300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2297, UInt<1>(0h1), "") : assert_189
node _T_2301 = eq(io.in.c.bits.source, source_3)
node _T_2302 = asUInt(reset)
node _T_2303 = eq(_T_2302, UInt<1>(0h0))
when _T_2303 :
node _T_2304 = eq(_T_2301, UInt<1>(0h0))
when _T_2304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2301, UInt<1>(0h1), "") : assert_190
node _T_2305 = eq(io.in.c.bits.address, address_2)
node _T_2306 = asUInt(reset)
node _T_2307 = eq(_T_2306, UInt<1>(0h0))
when _T_2307 :
node _T_2308 = eq(_T_2305, UInt<1>(0h0))
when _T_2308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2305, UInt<1>(0h1), "") : assert_191
node _T_2309 = and(io.in.c.ready, io.in.c.valid)
node _T_2310 = and(_T_2309, c_first)
when _T_2310 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2>
connect a_set, UInt<2>(0h0)
wire a_set_wo_ready : UInt<2>
connect a_set_wo_ready, UInt<2>(0h0)
wire a_opcodes_set : UInt<8>
connect a_opcodes_set, UInt<8>(0h0)
wire a_sizes_set : UInt<16>
connect a_sizes_set, UInt<16>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2311 = and(io.in.a.valid, a_first_1)
node _T_2312 = and(_T_2311, UInt<1>(0h1))
when _T_2312 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2313 = and(io.in.a.ready, io.in.a.valid)
node _T_2314 = and(_T_2313, a_first_1)
node _T_2315 = and(_T_2314, UInt<1>(0h1))
when _T_2315 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2316 = dshr(inflight, io.in.a.bits.source)
node _T_2317 = bits(_T_2316, 0, 0)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
node _T_2319 = asUInt(reset)
node _T_2320 = eq(_T_2319, UInt<1>(0h0))
when _T_2320 :
node _T_2321 = eq(_T_2318, UInt<1>(0h0))
when _T_2321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2318, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<2>
connect d_clr, UInt<2>(0h0)
wire d_clr_wo_ready : UInt<2>
connect d_clr_wo_ready, UInt<2>(0h0)
wire d_opcodes_clr : UInt<8>
connect d_opcodes_clr, UInt<8>(0h0)
wire d_sizes_clr : UInt<16>
connect d_sizes_clr, UInt<16>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2322 = and(io.in.d.valid, d_first_1)
node _T_2323 = and(_T_2322, UInt<1>(0h1))
node _T_2324 = eq(d_release_ack, UInt<1>(0h0))
node _T_2325 = and(_T_2323, _T_2324)
when _T_2325 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2326 = and(io.in.d.ready, io.in.d.valid)
node _T_2327 = and(_T_2326, d_first_1)
node _T_2328 = and(_T_2327, UInt<1>(0h1))
node _T_2329 = eq(d_release_ack, UInt<1>(0h0))
node _T_2330 = and(_T_2328, _T_2329)
when _T_2330 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2331 = and(io.in.d.valid, d_first_1)
node _T_2332 = and(_T_2331, UInt<1>(0h1))
node _T_2333 = eq(d_release_ack, UInt<1>(0h0))
node _T_2334 = and(_T_2332, _T_2333)
when _T_2334 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2335 = dshr(inflight, io.in.d.bits.source)
node _T_2336 = bits(_T_2335, 0, 0)
node _T_2337 = or(_T_2336, same_cycle_resp)
node _T_2338 = asUInt(reset)
node _T_2339 = eq(_T_2338, UInt<1>(0h0))
when _T_2339 :
node _T_2340 = eq(_T_2337, UInt<1>(0h0))
when _T_2340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2337, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2341 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2342 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2343 = or(_T_2341, _T_2342)
node _T_2344 = asUInt(reset)
node _T_2345 = eq(_T_2344, UInt<1>(0h0))
when _T_2345 :
node _T_2346 = eq(_T_2343, UInt<1>(0h0))
when _T_2346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2343, UInt<1>(0h1), "") : assert_194
node _T_2347 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2348 = asUInt(reset)
node _T_2349 = eq(_T_2348, UInt<1>(0h0))
when _T_2349 :
node _T_2350 = eq(_T_2347, UInt<1>(0h0))
when _T_2350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2347, UInt<1>(0h1), "") : assert_195
else :
node _T_2351 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2352 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2353 = or(_T_2351, _T_2352)
node _T_2354 = asUInt(reset)
node _T_2355 = eq(_T_2354, UInt<1>(0h0))
when _T_2355 :
node _T_2356 = eq(_T_2353, UInt<1>(0h0))
when _T_2356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2353, UInt<1>(0h1), "") : assert_196
node _T_2357 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2358 = asUInt(reset)
node _T_2359 = eq(_T_2358, UInt<1>(0h0))
when _T_2359 :
node _T_2360 = eq(_T_2357, UInt<1>(0h0))
when _T_2360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2357, UInt<1>(0h1), "") : assert_197
node _T_2361 = and(io.in.d.valid, d_first_1)
node _T_2362 = and(_T_2361, a_first_1)
node _T_2363 = and(_T_2362, io.in.a.valid)
node _T_2364 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2365 = and(_T_2363, _T_2364)
node _T_2366 = eq(d_release_ack, UInt<1>(0h0))
node _T_2367 = and(_T_2365, _T_2366)
when _T_2367 :
node _T_2368 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2369 = or(_T_2368, io.in.a.ready)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_198
node _T_2373 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2374 = orr(a_set_wo_ready)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
node _T_2376 = or(_T_2373, _T_2375)
node _T_2377 = asUInt(reset)
node _T_2378 = eq(_T_2377, UInt<1>(0h0))
when _T_2378 :
node _T_2379 = eq(_T_2376, UInt<1>(0h0))
when _T_2379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2376, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_100
node _T_2380 = orr(inflight)
node _T_2381 = eq(_T_2380, UInt<1>(0h0))
node _T_2382 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2383 = or(_T_2381, _T_2382)
node _T_2384 = lt(watchdog, plusarg_reader.out)
node _T_2385 = or(_T_2383, _T_2384)
node _T_2386 = asUInt(reset)
node _T_2387 = eq(_T_2386, UInt<1>(0h0))
when _T_2387 :
node _T_2388 = eq(_T_2385, UInt<1>(0h0))
when _T_2388 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2385, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2389 = and(io.in.a.ready, io.in.a.valid)
node _T_2390 = and(io.in.d.ready, io.in.d.valid)
node _T_2391 = or(_T_2389, _T_2390)
when _T_2391 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2>
connect c_set, UInt<2>(0h0)
wire c_set_wo_ready : UInt<2>
connect c_set_wo_ready, UInt<2>(0h0)
wire c_opcodes_set : UInt<8>
connect c_opcodes_set, UInt<8>(0h0)
wire c_sizes_set : UInt<16>
connect c_sizes_set, UInt<16>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2392 = and(io.in.c.valid, c_first_1)
node _T_2393 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2394 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2395 = and(_T_2393, _T_2394)
node _T_2396 = and(_T_2392, _T_2395)
when _T_2396 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2397 = and(io.in.c.ready, io.in.c.valid)
node _T_2398 = and(_T_2397, c_first_1)
node _T_2399 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2400 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2401 = and(_T_2399, _T_2400)
node _T_2402 = and(_T_2398, _T_2401)
when _T_2402 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2403 = dshr(inflight_1, io.in.c.bits.source)
node _T_2404 = bits(_T_2403, 0, 0)
node _T_2405 = eq(_T_2404, UInt<1>(0h0))
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2>
connect d_clr_1, UInt<2>(0h0)
wire d_clr_wo_ready_1 : UInt<2>
connect d_clr_wo_ready_1, UInt<2>(0h0)
wire d_opcodes_clr_1 : UInt<8>
connect d_opcodes_clr_1, UInt<8>(0h0)
wire d_sizes_clr_1 : UInt<16>
connect d_sizes_clr_1, UInt<16>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2409 = and(io.in.d.valid, d_first_2)
node _T_2410 = and(_T_2409, UInt<1>(0h1))
node _T_2411 = and(_T_2410, d_release_ack_1)
when _T_2411 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2412 = and(io.in.d.ready, io.in.d.valid)
node _T_2413 = and(_T_2412, d_first_2)
node _T_2414 = and(_T_2413, UInt<1>(0h1))
node _T_2415 = and(_T_2414, d_release_ack_1)
when _T_2415 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2416 = and(io.in.d.valid, d_first_2)
node _T_2417 = and(_T_2416, UInt<1>(0h1))
node _T_2418 = and(_T_2417, d_release_ack_1)
when _T_2418 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2419 = dshr(inflight_1, io.in.d.bits.source)
node _T_2420 = bits(_T_2419, 0, 0)
node _T_2421 = or(_T_2420, same_cycle_resp_1)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2425 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_203
else :
node _T_2429 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_204
node _T_2433 = and(io.in.d.valid, d_first_2)
node _T_2434 = and(_T_2433, c_first_1)
node _T_2435 = and(_T_2434, io.in.c.valid)
node _T_2436 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2437 = and(_T_2435, _T_2436)
node _T_2438 = and(_T_2437, d_release_ack_1)
node _T_2439 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2440 = and(_T_2438, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2442 = or(_T_2441, io.in.c.ready)
node _T_2443 = asUInt(reset)
node _T_2444 = eq(_T_2443, UInt<1>(0h0))
when _T_2444 :
node _T_2445 = eq(_T_2442, UInt<1>(0h0))
when _T_2445 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2442, UInt<1>(0h1), "") : assert_205
node _T_2446 = orr(c_set_wo_ready)
when _T_2446 :
node _T_2447 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2448 = asUInt(reset)
node _T_2449 = eq(_T_2448, UInt<1>(0h0))
when _T_2449 :
node _T_2450 = eq(_T_2447, UInt<1>(0h0))
when _T_2450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2447, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_101
node _T_2451 = orr(inflight_1)
node _T_2452 = eq(_T_2451, UInt<1>(0h0))
node _T_2453 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2454 = or(_T_2452, _T_2453)
node _T_2455 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2456 = or(_T_2454, _T_2455)
node _T_2457 = asUInt(reset)
node _T_2458 = eq(_T_2457, UInt<1>(0h0))
when _T_2458 :
node _T_2459 = eq(_T_2456, UInt<1>(0h0))
when _T_2459 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2456, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2460 = and(io.in.c.ready, io.in.c.valid)
node _T_2461 = and(io.in.d.ready, io.in.d.valid)
node _T_2462 = or(_T_2460, _T_2461)
when _T_2462 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2463 = and(io.in.d.ready, io.in.d.valid)
node _T_2464 = and(_T_2463, d_first_3)
node _T_2465 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2466 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2467 = eq(_T_2466, UInt<1>(0h0))
node _T_2468 = and(_T_2465, _T_2467)
node _T_2469 = and(_T_2464, _T_2468)
when _T_2469 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2470 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2471 = bits(_T_2470, 0, 0)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(_T_2472, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2472, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2476 = and(io.in.e.ready, io.in.e.valid)
node _T_2477 = and(_T_2476, UInt<1>(0h1))
node _T_2478 = and(_T_2477, UInt<1>(0h1))
when _T_2478 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2479 = or(d_set, inflight_2)
node _T_2480 = dshr(_T_2479, io.in.e.bits.sink)
node _T_2481 = bits(_T_2480, 0, 0)
node _T_2482 = asUInt(reset)
node _T_2483 = eq(_T_2482, UInt<1>(0h0))
when _T_2483 :
node _T_2484 = eq(_T_2481, UInt<1>(0h0))
when _T_2484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/HellaCache.scala:280:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2481, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8
extmodule plusarg_reader_102 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_103 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLMonitor_49( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7]
wire io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _legal_source_T_2 = 1'h0; // @[Mux.scala:30:73]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34]
wire _legal_source_T_1 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_5 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire _source_ok_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71]
assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71]
assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10]
wire _legal_source_T = ~io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_1 = _legal_source_T_1; // @[Parameters.scala:1138:31]
wire _legal_source_T_3 = _legal_source_WIRE_1; // @[Mux.scala:30:73]
wire _legal_source_T_4 = _legal_source_T_3; // @[Mux.scala:30:73]
wire _legal_source_WIRE_1_0 = _legal_source_T_4; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire _source_ok_T_4 = ~io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_4; // @[Parameters.scala:1138:31]
wire _source_ok_WIRE_2_1 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire source_ok_2 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire _T_2389 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2389; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2389; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2463 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2463; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2463; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2460 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2460; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2460; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [15:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] a_set; // @[Monitor.scala:626:34]
wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [15:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99]
wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_21 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_22 = 2'h1 << _GEN_21; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_22; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_22; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2315 = _T_2389 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2315 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2315 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2315 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2315 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_2315 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1:0] d_clr; // @[Monitor.scala:664:34]
wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_23 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_23; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_23; // @[Monitor.scala:673:46, :783:46]
wire _T_2361 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_24 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_25 = 2'h1 << _GEN_24; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_25; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_25; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2361 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2330 = _T_2463 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2330 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2330 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2330 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] c_set; // @[Monitor.scala:738:34]
wire [1:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [7:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [15:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [1:0] _GEN_26 = {1'h0, io_in_c_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_27 = 2'h1 << _GEN_26; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_27; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_27; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_2402 = _T_2460 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2402 ? _c_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2402 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2402 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [3:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [18:0] _c_opcodes_set_T_1 = {15'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:754:40, :767:{54,79}]
assign c_opcodes_set = _T_2402 ? _c_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [3:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [19:0] _c_sizes_set_T_1 = {15'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:755:40, :768:{52,77}]
assign c_sizes_set = _T_2402 ? _c_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [1:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2433 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2433 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire _T_2415 = _T_2463 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2415 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2415 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2415 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2469 = _T_2463 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_28 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_28; // @[OneHot.scala:58:35]
assign d_set = _T_2469 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2478 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_29 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_29; // @[OneHot.scala:58:35]
assign e_clr = _T_2478 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_47 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0hf))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0hf))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h1))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0hf))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_17 = shr(io.in.a.bits.source, 4)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<4>(0hf))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _T_30 = and(_T_16, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_30, UInt<1>(0h1), "") : assert_1
node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_34 :
node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_37 = and(_T_35, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_38 = shr(io.in.a.bits.source, 4)
node _T_39 = eq(_T_38, UInt<1>(0h1))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<4>(0hf))
node _T_43 = and(_T_41, _T_42)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_44 = shr(io.in.a.bits.source, 4)
node _T_45 = eq(_T_44, UInt<1>(0h0))
node _T_46 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_47 = and(_T_45, _T_46)
node _T_48 = leq(uncommonBits_3, UInt<4>(0hf))
node _T_49 = and(_T_47, _T_48)
node _T_50 = or(_T_43, _T_49)
node _T_51 = and(_T_37, _T_50)
node _T_52 = or(UInt<1>(0h0), _T_51)
node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<27>(0h4000000)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<13>(0h1000)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = or(_T_58, _T_63)
node _T_95 = or(_T_94, _T_68)
node _T_96 = or(_T_95, _T_73)
node _T_97 = or(_T_96, _T_78)
node _T_98 = or(_T_97, _T_83)
node _T_99 = or(_T_98, _T_88)
node _T_100 = or(_T_99, _T_93)
node _T_101 = and(_T_53, _T_100)
node _T_102 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_103 = or(UInt<1>(0h0), _T_102)
node _T_104 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_105 = cvt(_T_104)
node _T_106 = and(_T_105, asSInt(UInt<17>(0h10000)))
node _T_107 = asSInt(_T_106)
node _T_108 = eq(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_110 = cvt(_T_109)
node _T_111 = and(_T_110, asSInt(UInt<29>(0h10000000)))
node _T_112 = asSInt(_T_111)
node _T_113 = eq(_T_112, asSInt(UInt<1>(0h0)))
node _T_114 = or(_T_108, _T_113)
node _T_115 = and(_T_103, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_101)
node _T_117 = or(_T_116, _T_115)
node _T_118 = and(_T_52, _T_117)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_118, UInt<1>(0h1), "") : assert_2
node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_124 = and(_T_122, _T_123)
node _T_125 = or(UInt<1>(0h0), _T_124)
node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = or(_T_130, _T_135)
node _T_177 = or(_T_176, _T_140)
node _T_178 = or(_T_177, _T_145)
node _T_179 = or(_T_178, _T_150)
node _T_180 = or(_T_179, _T_155)
node _T_181 = or(_T_180, _T_160)
node _T_182 = or(_T_181, _T_165)
node _T_183 = or(_T_182, _T_170)
node _T_184 = or(_T_183, _T_175)
node _T_185 = and(_T_125, _T_184)
node _T_186 = or(UInt<1>(0h0), _T_185)
node _T_187 = and(UInt<1>(0h0), _T_186)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_187, UInt<1>(0h1), "") : assert_3
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(source_ok, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_194 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_194, UInt<1>(0h1), "") : assert_5
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(is_aligned, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_202 = asUInt(reset)
node _T_203 = eq(_T_202, UInt<1>(0h0))
when _T_203 :
node _T_204 = eq(_T_201, UInt<1>(0h0))
when _T_204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_201, UInt<1>(0h1), "") : assert_7
node _T_205 = not(io.in.a.bits.mask)
node _T_206 = eq(_T_205, UInt<1>(0h0))
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_T_206, UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_206, UInt<1>(0h1), "") : assert_8
node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_211 = asUInt(reset)
node _T_212 = eq(_T_211, UInt<1>(0h0))
when _T_212 :
node _T_213 = eq(_T_210, UInt<1>(0h0))
when _T_213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_210, UInt<1>(0h1), "") : assert_9
node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_214 :
node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_217 = and(_T_215, _T_216)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_218 = shr(io.in.a.bits.source, 4)
node _T_219 = eq(_T_218, UInt<1>(0h1))
node _T_220 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_221 = and(_T_219, _T_220)
node _T_222 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_223 = and(_T_221, _T_222)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_224 = shr(io.in.a.bits.source, 4)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_229 = and(_T_227, _T_228)
node _T_230 = or(_T_223, _T_229)
node _T_231 = and(_T_217, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<18>(0h2f000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<17>(0h10000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<13>(0h1000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<27>(0h4000000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = or(_T_238, _T_243)
node _T_275 = or(_T_274, _T_248)
node _T_276 = or(_T_275, _T_253)
node _T_277 = or(_T_276, _T_258)
node _T_278 = or(_T_277, _T_263)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_273)
node _T_281 = and(_T_233, _T_280)
node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<17>(0h10000)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_290 = cvt(_T_289)
node _T_291 = and(_T_290, asSInt(UInt<29>(0h10000000)))
node _T_292 = asSInt(_T_291)
node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0)))
node _T_294 = or(_T_288, _T_293)
node _T_295 = and(_T_283, _T_294)
node _T_296 = or(UInt<1>(0h0), _T_281)
node _T_297 = or(_T_296, _T_295)
node _T_298 = and(_T_232, _T_297)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_298, UInt<1>(0h1), "") : assert_10
node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_304 = and(_T_302, _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_307 = cvt(_T_306)
node _T_308 = and(_T_307, asSInt(UInt<14>(0h2000)))
node _T_309 = asSInt(_T_308)
node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0)))
node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_317 = cvt(_T_316)
node _T_318 = and(_T_317, asSInt(UInt<17>(0h10000)))
node _T_319 = asSInt(_T_318)
node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0)))
node _T_321 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_322 = cvt(_T_321)
node _T_323 = and(_T_322, asSInt(UInt<18>(0h2f000)))
node _T_324 = asSInt(_T_323)
node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0)))
node _T_326 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<17>(0h10000)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<13>(0h1000)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<27>(0h4000000)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<13>(0h1000)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<29>(0h10000000)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_310, _T_315)
node _T_357 = or(_T_356, _T_320)
node _T_358 = or(_T_357, _T_325)
node _T_359 = or(_T_358, _T_330)
node _T_360 = or(_T_359, _T_335)
node _T_361 = or(_T_360, _T_340)
node _T_362 = or(_T_361, _T_345)
node _T_363 = or(_T_362, _T_350)
node _T_364 = or(_T_363, _T_355)
node _T_365 = and(_T_305, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = and(UInt<1>(0h0), _T_366)
node _T_368 = asUInt(reset)
node _T_369 = eq(_T_368, UInt<1>(0h0))
when _T_369 :
node _T_370 = eq(_T_367, UInt<1>(0h0))
when _T_370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_367, UInt<1>(0h1), "") : assert_11
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(source_ok, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_374 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_374, UInt<1>(0h1), "") : assert_13
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(is_aligned, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_381 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_381, UInt<1>(0h1), "") : assert_15
node _T_385 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_385, UInt<1>(0h1), "") : assert_16
node _T_389 = not(io.in.a.bits.mask)
node _T_390 = eq(_T_389, UInt<1>(0h0))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_390, UInt<1>(0h1), "") : assert_17
node _T_394 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_T_394, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_394, UInt<1>(0h1), "") : assert_18
node _T_398 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_398 :
node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_400 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_401 = and(_T_399, _T_400)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_402 = shr(io.in.a.bits.source, 4)
node _T_403 = eq(_T_402, UInt<1>(0h1))
node _T_404 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_405 = and(_T_403, _T_404)
node _T_406 = leq(uncommonBits_6, UInt<4>(0hf))
node _T_407 = and(_T_405, _T_406)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_408 = shr(io.in.a.bits.source, 4)
node _T_409 = eq(_T_408, UInt<1>(0h0))
node _T_410 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_411 = and(_T_409, _T_410)
node _T_412 = leq(uncommonBits_7, UInt<4>(0hf))
node _T_413 = and(_T_411, _T_412)
node _T_414 = or(_T_407, _T_413)
node _T_415 = and(_T_401, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_416, UInt<1>(0h1), "") : assert_19
node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_422 = and(_T_420, _T_421)
node _T_423 = or(UInt<1>(0h0), _T_422)
node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = and(_T_423, _T_428)
node _T_430 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_431 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_432 = and(_T_430, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_432)
node _T_434 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<14>(0h2000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<18>(0h2f000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_450 = cvt(_T_449)
node _T_451 = and(_T_450, asSInt(UInt<17>(0h10000)))
node _T_452 = asSInt(_T_451)
node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0)))
node _T_454 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_455 = cvt(_T_454)
node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000)))
node _T_457 = asSInt(_T_456)
node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0)))
node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<27>(0h4000000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_470 = cvt(_T_469)
node _T_471 = and(_T_470, asSInt(UInt<13>(0h1000)))
node _T_472 = asSInt(_T_471)
node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0)))
node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_475 = cvt(_T_474)
node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000)))
node _T_477 = asSInt(_T_476)
node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0)))
node _T_479 = or(_T_438, _T_443)
node _T_480 = or(_T_479, _T_448)
node _T_481 = or(_T_480, _T_453)
node _T_482 = or(_T_481, _T_458)
node _T_483 = or(_T_482, _T_463)
node _T_484 = or(_T_483, _T_468)
node _T_485 = or(_T_484, _T_473)
node _T_486 = or(_T_485, _T_478)
node _T_487 = and(_T_433, _T_486)
node _T_488 = or(UInt<1>(0h0), _T_429)
node _T_489 = or(_T_488, _T_487)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_489, UInt<1>(0h1), "") : assert_20
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(source_ok, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(is_aligned, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_499 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_499, UInt<1>(0h1), "") : assert_23
node _T_503 = eq(io.in.a.bits.mask, mask)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_503, UInt<1>(0h1), "") : assert_24
node _T_507 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_T_507, UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_507, UInt<1>(0h1), "") : assert_25
node _T_511 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_511 :
node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_514 = and(_T_512, _T_513)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_515 = shr(io.in.a.bits.source, 4)
node _T_516 = eq(_T_515, UInt<1>(0h1))
node _T_517 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_518 = and(_T_516, _T_517)
node _T_519 = leq(uncommonBits_8, UInt<4>(0hf))
node _T_520 = and(_T_518, _T_519)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0)
node _T_521 = shr(io.in.a.bits.source, 4)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_524 = and(_T_522, _T_523)
node _T_525 = leq(uncommonBits_9, UInt<4>(0hf))
node _T_526 = and(_T_524, _T_525)
node _T_527 = or(_T_520, _T_526)
node _T_528 = and(_T_514, _T_527)
node _T_529 = or(UInt<1>(0h0), _T_528)
node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_532 = and(_T_530, _T_531)
node _T_533 = or(UInt<1>(0h0), _T_532)
node _T_534 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<13>(0h1000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = and(_T_533, _T_538)
node _T_540 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_541 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_542 = and(_T_540, _T_541)
node _T_543 = or(UInt<1>(0h0), _T_542)
node _T_544 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<14>(0h2000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_550 = cvt(_T_549)
node _T_551 = and(_T_550, asSInt(UInt<18>(0h2f000)))
node _T_552 = asSInt(_T_551)
node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0)))
node _T_554 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_560 = cvt(_T_559)
node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000)))
node _T_562 = asSInt(_T_561)
node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0)))
node _T_564 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<27>(0h4000000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<13>(0h1000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<29>(0h10000000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = or(_T_548, _T_553)
node _T_585 = or(_T_584, _T_558)
node _T_586 = or(_T_585, _T_563)
node _T_587 = or(_T_586, _T_568)
node _T_588 = or(_T_587, _T_573)
node _T_589 = or(_T_588, _T_578)
node _T_590 = or(_T_589, _T_583)
node _T_591 = and(_T_543, _T_590)
node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_594 = cvt(_T_593)
node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000)))
node _T_596 = asSInt(_T_595)
node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0)))
node _T_598 = and(_T_592, _T_597)
node _T_599 = or(UInt<1>(0h0), _T_539)
node _T_600 = or(_T_599, _T_591)
node _T_601 = or(_T_600, _T_598)
node _T_602 = and(_T_529, _T_601)
node _T_603 = asUInt(reset)
node _T_604 = eq(_T_603, UInt<1>(0h0))
when _T_604 :
node _T_605 = eq(_T_602, UInt<1>(0h0))
when _T_605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_602, UInt<1>(0h1), "") : assert_26
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(source_ok, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(is_aligned, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_612, UInt<1>(0h1), "") : assert_29
node _T_616 = eq(io.in.a.bits.mask, mask)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_616, UInt<1>(0h1), "") : assert_30
node _T_620 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_620 :
node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_624 = shr(io.in.a.bits.source, 4)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_630 = shr(io.in.a.bits.source, 4)
node _T_631 = eq(_T_630, UInt<1>(0h0))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_635 = and(_T_633, _T_634)
node _T_636 = or(_T_629, _T_635)
node _T_637 = and(_T_623, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_640 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_641 = and(_T_639, _T_640)
node _T_642 = or(UInt<1>(0h0), _T_641)
node _T_643 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = and(_T_642, _T_647)
node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_651 = and(_T_649, _T_650)
node _T_652 = or(UInt<1>(0h0), _T_651)
node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<18>(0h2f000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<17>(0h10000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<29>(0h10000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = or(_T_657, _T_662)
node _T_694 = or(_T_693, _T_667)
node _T_695 = or(_T_694, _T_672)
node _T_696 = or(_T_695, _T_677)
node _T_697 = or(_T_696, _T_682)
node _T_698 = or(_T_697, _T_687)
node _T_699 = or(_T_698, _T_692)
node _T_700 = and(_T_652, _T_699)
node _T_701 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_702 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = and(_T_701, _T_706)
node _T_708 = or(UInt<1>(0h0), _T_648)
node _T_709 = or(_T_708, _T_700)
node _T_710 = or(_T_709, _T_707)
node _T_711 = and(_T_638, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_711, UInt<1>(0h1), "") : assert_31
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_721 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_721, UInt<1>(0h1), "") : assert_34
node _T_725 = not(mask)
node _T_726 = and(io.in.a.bits.mask, _T_725)
node _T_727 = eq(_T_726, UInt<1>(0h0))
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_727, UInt<1>(0h1), "") : assert_35
node _T_731 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_731 :
node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_733 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_734 = and(_T_732, _T_733)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0)
node _T_735 = shr(io.in.a.bits.source, 4)
node _T_736 = eq(_T_735, UInt<1>(0h1))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_12, UInt<4>(0hf))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0)
node _T_741 = shr(io.in.a.bits.source, 4)
node _T_742 = eq(_T_741, UInt<1>(0h0))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_13, UInt<4>(0hf))
node _T_746 = and(_T_744, _T_745)
node _T_747 = or(_T_740, _T_746)
node _T_748 = and(_T_734, _T_747)
node _T_749 = or(UInt<1>(0h0), _T_748)
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_755 = cvt(_T_754)
node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000)))
node _T_757 = asSInt(_T_756)
node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0)))
node _T_759 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_760 = cvt(_T_759)
node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000)))
node _T_762 = asSInt(_T_761)
node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0)))
node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_765 = cvt(_T_764)
node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000)))
node _T_767 = asSInt(_T_766)
node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0)))
node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_770 = cvt(_T_769)
node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000)))
node _T_772 = asSInt(_T_771)
node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0)))
node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_775 = cvt(_T_774)
node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000)))
node _T_777 = asSInt(_T_776)
node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0)))
node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_785 = cvt(_T_784)
node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000)))
node _T_787 = asSInt(_T_786)
node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0)))
node _T_789 = or(_T_758, _T_763)
node _T_790 = or(_T_789, _T_768)
node _T_791 = or(_T_790, _T_773)
node _T_792 = or(_T_791, _T_778)
node _T_793 = or(_T_792, _T_783)
node _T_794 = or(_T_793, _T_788)
node _T_795 = and(_T_753, _T_794)
node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = and(_T_796, _T_801)
node _T_803 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_804 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_805 = and(_T_803, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_805)
node _T_807 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_808 = cvt(_T_807)
node _T_809 = and(_T_808, asSInt(UInt<17>(0h10000)))
node _T_810 = asSInt(_T_809)
node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0)))
node _T_812 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<29>(0h10000000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = or(_T_811, _T_816)
node _T_818 = and(_T_806, _T_817)
node _T_819 = or(UInt<1>(0h0), _T_795)
node _T_820 = or(_T_819, _T_802)
node _T_821 = or(_T_820, _T_818)
node _T_822 = and(_T_749, _T_821)
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_822, UInt<1>(0h1), "") : assert_36
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(source_ok, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(is_aligned, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_832, UInt<1>(0h1), "") : assert_39
node _T_836 = eq(io.in.a.bits.mask, mask)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_836, UInt<1>(0h1), "") : assert_40
node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_840 :
node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_843 = and(_T_841, _T_842)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0)
node _T_844 = shr(io.in.a.bits.source, 4)
node _T_845 = eq(_T_844, UInt<1>(0h1))
node _T_846 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_847 = and(_T_845, _T_846)
node _T_848 = leq(uncommonBits_14, UInt<4>(0hf))
node _T_849 = and(_T_847, _T_848)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0)
node _T_850 = shr(io.in.a.bits.source, 4)
node _T_851 = eq(_T_850, UInt<1>(0h0))
node _T_852 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_853 = and(_T_851, _T_852)
node _T_854 = leq(uncommonBits_15, UInt<4>(0hf))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(_T_849, _T_855)
node _T_857 = and(_T_843, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_860 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_861 = and(_T_859, _T_860)
node _T_862 = or(UInt<1>(0h0), _T_861)
node _T_863 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_864 = cvt(_T_863)
node _T_865 = and(_T_864, asSInt(UInt<14>(0h2000)))
node _T_866 = asSInt(_T_865)
node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0)))
node _T_868 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<13>(0h1000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<18>(0h2f000)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_879 = cvt(_T_878)
node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000)))
node _T_881 = asSInt(_T_880)
node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0)))
node _T_883 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_884 = cvt(_T_883)
node _T_885 = and(_T_884, asSInt(UInt<13>(0h1000)))
node _T_886 = asSInt(_T_885)
node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0)))
node _T_888 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_889 = cvt(_T_888)
node _T_890 = and(_T_889, asSInt(UInt<27>(0h4000000)))
node _T_891 = asSInt(_T_890)
node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0)))
node _T_893 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_894 = cvt(_T_893)
node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000)))
node _T_896 = asSInt(_T_895)
node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0)))
node _T_898 = or(_T_867, _T_872)
node _T_899 = or(_T_898, _T_877)
node _T_900 = or(_T_899, _T_882)
node _T_901 = or(_T_900, _T_887)
node _T_902 = or(_T_901, _T_892)
node _T_903 = or(_T_902, _T_897)
node _T_904 = and(_T_862, _T_903)
node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_906 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = and(_T_905, _T_910)
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_914 = and(_T_912, _T_913)
node _T_915 = or(UInt<1>(0h0), _T_914)
node _T_916 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_917 = cvt(_T_916)
node _T_918 = and(_T_917, asSInt(UInt<17>(0h10000)))
node _T_919 = asSInt(_T_918)
node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0)))
node _T_921 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<29>(0h10000000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = or(_T_920, _T_925)
node _T_927 = and(_T_915, _T_926)
node _T_928 = or(UInt<1>(0h0), _T_904)
node _T_929 = or(_T_928, _T_911)
node _T_930 = or(_T_929, _T_927)
node _T_931 = and(_T_858, _T_930)
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(_T_931, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_931, UInt<1>(0h1), "") : assert_41
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(source_ok, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(is_aligned, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_941 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_941, UInt<1>(0h1), "") : assert_44
node _T_945 = eq(io.in.a.bits.mask, mask)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_945, UInt<1>(0h1), "") : assert_45
node _T_949 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_949 :
node _T_950 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_951 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_952 = and(_T_950, _T_951)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_953 = shr(io.in.a.bits.source, 4)
node _T_954 = eq(_T_953, UInt<1>(0h1))
node _T_955 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_956 = and(_T_954, _T_955)
node _T_957 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_958 = and(_T_956, _T_957)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_959 = shr(io.in.a.bits.source, 4)
node _T_960 = eq(_T_959, UInt<1>(0h0))
node _T_961 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_962 = and(_T_960, _T_961)
node _T_963 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_964 = and(_T_962, _T_963)
node _T_965 = or(_T_958, _T_964)
node _T_966 = and(_T_952, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_969 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_970 = and(_T_968, _T_969)
node _T_971 = or(UInt<1>(0h0), _T_970)
node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = and(_T_971, _T_976)
node _T_978 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_979 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_980 = cvt(_T_979)
node _T_981 = and(_T_980, asSInt(UInt<14>(0h2000)))
node _T_982 = asSInt(_T_981)
node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0)))
node _T_984 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<17>(0h10000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<18>(0h2f000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<13>(0h1000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<27>(0h4000000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = or(_T_983, _T_988)
node _T_1015 = or(_T_1014, _T_993)
node _T_1016 = or(_T_1015, _T_998)
node _T_1017 = or(_T_1016, _T_1003)
node _T_1018 = or(_T_1017, _T_1008)
node _T_1019 = or(_T_1018, _T_1013)
node _T_1020 = and(_T_978, _T_1019)
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = or(UInt<1>(0h0), _T_1023)
node _T_1025 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<29>(0h10000000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = or(_T_1029, _T_1034)
node _T_1036 = and(_T_1024, _T_1035)
node _T_1037 = or(UInt<1>(0h0), _T_977)
node _T_1038 = or(_T_1037, _T_1020)
node _T_1039 = or(_T_1038, _T_1036)
node _T_1040 = and(_T_967, _T_1039)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_46
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(is_aligned, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1050 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_49
node _T_1054 = eq(io.in.a.bits.mask, mask)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_50
node _T_1058 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1062 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1063 = asUInt(reset)
node _T_1064 = eq(_T_1063, UInt<1>(0h0))
when _T_1064 :
node _T_1065 = eq(_T_1062, UInt<1>(0h0))
when _T_1065 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1062, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0)
node _source_ok_T_12 = shr(io.in.d.bits.source, 4)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0hf))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0)
node _source_ok_T_18 = shr(io.in.d.bits.source, 4)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<4>(0hf))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_17
connect _source_ok_WIRE_1[1], _source_ok_T_23
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_1066 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1066 :
node _T_1067 = asUInt(reset)
node _T_1068 = eq(_T_1067, UInt<1>(0h0))
when _T_1068 :
node _T_1069 = eq(source_ok_1, UInt<1>(0h0))
when _T_1069 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1070 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_54
node _T_1074 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_55
node _T_1078 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_56
node _T_1082 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1083 = asUInt(reset)
node _T_1084 = eq(_T_1083, UInt<1>(0h0))
when _T_1084 :
node _T_1085 = eq(_T_1082, UInt<1>(0h0))
when _T_1085 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1082, UInt<1>(0h1), "") : assert_57
node _T_1086 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1086 :
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(source_ok_1, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(sink_ok, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1093 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_60
node _T_1097 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1098 = asUInt(reset)
node _T_1099 = eq(_T_1098, UInt<1>(0h0))
when _T_1099 :
node _T_1100 = eq(_T_1097, UInt<1>(0h0))
when _T_1100 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1097, UInt<1>(0h1), "") : assert_61
node _T_1101 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1102 = asUInt(reset)
node _T_1103 = eq(_T_1102, UInt<1>(0h0))
when _T_1103 :
node _T_1104 = eq(_T_1101, UInt<1>(0h0))
when _T_1104 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1101, UInt<1>(0h1), "") : assert_62
node _T_1105 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_63
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h1), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_64
node _T_1114 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(sink_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1121 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_67
node _T_1125 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_68
node _T_1129 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_69
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(_T_1133, io.in.d.bits.corrupt)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_70
node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1139 = or(UInt<1>(0h1), _T_1138)
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_71
node _T_1143 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(source_ok_1, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_73
node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_74
node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1156 = or(UInt<1>(0h1), _T_1155)
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_75
node _T_1160 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1164 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_77
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(_T_1168, io.in.d.bits.corrupt)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_78
node _T_1173 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1174 = or(UInt<1>(0h1), _T_1173)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_79
node _T_1178 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1178 :
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(source_ok_1, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_81
node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_82
node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1191 = or(UInt<1>(0h1), _T_1190)
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(_T_1191, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1191, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1195 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1199 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1203 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1207 = eq(a_first, UInt<1>(0h0))
node _T_1208 = and(io.in.a.valid, _T_1207)
when _T_1208 :
node _T_1209 = eq(io.in.a.bits.opcode, opcode)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_87
node _T_1213 = eq(io.in.a.bits.param, param)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_88
node _T_1217 = eq(io.in.a.bits.size, size)
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_89
node _T_1221 = eq(io.in.a.bits.source, source)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_90
node _T_1225 = eq(io.in.a.bits.address, address)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_91
node _T_1229 = and(io.in.a.ready, io.in.a.valid)
node _T_1230 = and(_T_1229, a_first)
when _T_1230 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1231 = eq(d_first, UInt<1>(0h0))
node _T_1232 = and(io.in.d.valid, _T_1231)
when _T_1232 :
node _T_1233 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_92
node _T_1237 = eq(io.in.d.bits.param, param_1)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_93
node _T_1241 = eq(io.in.d.bits.size, size_1)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_94
node _T_1245 = eq(io.in.d.bits.source, source_1)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_95
node _T_1249 = eq(io.in.d.bits.sink, sink)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_96
node _T_1253 = eq(io.in.d.bits.denied, denied)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_97
node _T_1257 = and(io.in.d.ready, io.in.d.valid)
node _T_1258 = and(_T_1257, d_first)
when _T_1258 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<32>
connect a_set, UInt<32>(0h0)
wire a_set_wo_ready : UInt<32>
connect a_set_wo_ready, UInt<32>(0h0)
wire a_opcodes_set : UInt<128>
connect a_opcodes_set, UInt<128>(0h0)
wire a_sizes_set : UInt<256>
connect a_sizes_set, UInt<256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1259 = and(io.in.a.valid, a_first_1)
node _T_1260 = and(_T_1259, UInt<1>(0h1))
when _T_1260 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1261 = and(io.in.a.ready, io.in.a.valid)
node _T_1262 = and(_T_1261, a_first_1)
node _T_1263 = and(_T_1262, UInt<1>(0h1))
when _T_1263 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1264 = dshr(inflight, io.in.a.bits.source)
node _T_1265 = bits(_T_1264, 0, 0)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<32>
connect d_clr, UInt<32>(0h0)
wire d_clr_wo_ready : UInt<32>
connect d_clr_wo_ready, UInt<32>(0h0)
wire d_opcodes_clr : UInt<128>
connect d_opcodes_clr, UInt<128>(0h0)
wire d_sizes_clr : UInt<256>
connect d_sizes_clr, UInt<256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1270 = and(io.in.d.valid, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = and(_T_1274, d_first_1)
node _T_1276 = and(_T_1275, UInt<1>(0h1))
node _T_1277 = eq(d_release_ack, UInt<1>(0h0))
node _T_1278 = and(_T_1276, _T_1277)
when _T_1278 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1279 = and(io.in.d.valid, d_first_1)
node _T_1280 = and(_T_1279, UInt<1>(0h1))
node _T_1281 = eq(d_release_ack, UInt<1>(0h0))
node _T_1282 = and(_T_1280, _T_1281)
when _T_1282 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1283 = dshr(inflight, io.in.d.bits.source)
node _T_1284 = bits(_T_1283, 0, 0)
node _T_1285 = or(_T_1284, same_cycle_resp)
node _T_1286 = asUInt(reset)
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
when _T_1287 :
node _T_1288 = eq(_T_1285, UInt<1>(0h0))
when _T_1288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1285, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1289 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1290 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1291 = or(_T_1289, _T_1290)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100
node _T_1295 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_101
else :
node _T_1299 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1300 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1301 = or(_T_1299, _T_1300)
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_102
node _T_1305 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_103
node _T_1309 = and(io.in.d.valid, d_first_1)
node _T_1310 = and(_T_1309, a_first_1)
node _T_1311 = and(_T_1310, io.in.a.valid)
node _T_1312 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = eq(d_release_ack, UInt<1>(0h0))
node _T_1315 = and(_T_1313, _T_1314)
when _T_1315 :
node _T_1316 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1317 = or(_T_1316, io.in.a.ready)
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(_T_1317, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1317, UInt<1>(0h1), "") : assert_104
node _T_1321 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1322 = orr(a_set_wo_ready)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
node _T_1324 = or(_T_1321, _T_1323)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_94
node _T_1328 = orr(inflight)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
node _T_1330 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1331 = or(_T_1329, _T_1330)
node _T_1332 = lt(watchdog, plusarg_reader.out)
node _T_1333 = or(_T_1331, _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1337 = and(io.in.a.ready, io.in.a.valid)
node _T_1338 = and(io.in.d.ready, io.in.d.valid)
node _T_1339 = or(_T_1337, _T_1338)
when _T_1339 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0)
regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<32>
connect c_set, UInt<32>(0h0)
wire c_set_wo_ready : UInt<32>
connect c_set_wo_ready, UInt<32>(0h0)
wire c_opcodes_set : UInt<128>
connect c_opcodes_set, UInt<128>(0h0)
wire c_sizes_set : UInt<256>
connect c_sizes_set, UInt<256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1340 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1341 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1342 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1343 = and(_T_1341, _T_1342)
node _T_1344 = and(_T_1340, _T_1343)
when _T_1344 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1345 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1346 = and(_T_1345, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1347 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1348 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1349 = and(_T_1347, _T_1348)
node _T_1350 = and(_T_1346, _T_1349)
when _T_1350 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1351 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1352 = bits(_T_1351, 0, 0)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<32>
connect d_clr_1, UInt<32>(0h0)
wire d_clr_wo_ready_1 : UInt<32>
connect d_clr_wo_ready_1, UInt<32>(0h0)
wire d_opcodes_clr_1 : UInt<128>
connect d_opcodes_clr_1, UInt<128>(0h0)
wire d_sizes_clr_1 : UInt<256>
connect d_sizes_clr_1, UInt<256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1357 = and(io.in.d.valid, d_first_2)
node _T_1358 = and(_T_1357, UInt<1>(0h1))
node _T_1359 = and(_T_1358, d_release_ack_1)
when _T_1359 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1360 = and(io.in.d.ready, io.in.d.valid)
node _T_1361 = and(_T_1360, d_first_2)
node _T_1362 = and(_T_1361, UInt<1>(0h1))
node _T_1363 = and(_T_1362, d_release_ack_1)
when _T_1363 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1364 = and(io.in.d.valid, d_first_2)
node _T_1365 = and(_T_1364, UInt<1>(0h1))
node _T_1366 = and(_T_1365, d_release_ack_1)
when _T_1366 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1367 = dshr(inflight_1, io.in.d.bits.source)
node _T_1368 = bits(_T_1367, 0, 0)
node _T_1369 = or(_T_1368, same_cycle_resp_1)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1373 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_109
else :
node _T_1377 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_110
node _T_1381 = and(io.in.d.valid, d_first_2)
node _T_1382 = and(_T_1381, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1383 = and(_T_1382, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1384 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1385 = and(_T_1383, _T_1384)
node _T_1386 = and(_T_1385, d_release_ack_1)
node _T_1387 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1388 = and(_T_1386, _T_1387)
when _T_1388 :
node _T_1389 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1390 = or(_T_1389, _WIRE_23.ready)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_111
node _T_1394 = orr(c_set_wo_ready)
when _T_1394 :
node _T_1395 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_95
node _T_1399 = orr(inflight_1)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
node _T_1401 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1404 = or(_T_1402, _T_1403)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/gemmini/src/main/scala/gemmini/Scratchpad.scala:202:65)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1408 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1409 = and(io.in.d.ready, io.in.d.valid)
node _T_1410 = or(_T_1408, _T_1409)
when _T_1410 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_47( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_6 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21]
wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_12 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_18 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1263 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1278 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module LCG_1 :
input clock : Clock
input reset : Reset
output io : { out : UInt<5>, flip inc : UInt<1>}
inst outs_lcg of LCG16_1
connect outs_lcg.clock, clock
connect outs_lcg.reset, reset
connect outs_lcg.io.inc, io.inc
connect io.out, outs_lcg.io.out | module LCG_1( // @[LCG.scala:30:7]
input clock, // @[LCG.scala:30:7]
input reset, // @[LCG.scala:30:7]
output [4:0] io_out // @[LCG.scala:31:14]
);
wire [15:0] _outs_lcg_io_out; // @[LCG.scala:43:21]
wire io_inc = 1'h1; // @[LCG.scala:30:7, :31:14, :43:21]
wire [4:0] io_out_0; // @[LCG.scala:30:7]
assign io_out_0 = _outs_lcg_io_out[4:0]; // @[LCG.scala:30:7, :38:10, :43:21]
LCG16_1 outs_lcg ( // @[LCG.scala:43:21]
.clock (clock),
.reset (reset),
.io_out (_outs_lcg_io_out)
); // @[LCG.scala:43:21]
assign io_out = io_out_0; // @[LCG.scala:30:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RotatingSingleVCAllocator_5 :
input clock : Clock
input reset : Reset
output io : { req : { flip `4` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}}, resp : { `4` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `3` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `2` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `1` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, `0` : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, channel_status : { flip `5` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `4` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip `3` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip `2` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip `1` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip `0` : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3]}, out_allocs : { `5` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `4` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], `3` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], `2` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], `1` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], `0` : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3]}}
regreset mask : UInt<5>, clock, reset, UInt<5>(0h0)
wire in_arb_reqs : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}[5]
wire in_arb_vals : UInt<1>[5]
node in_arb_filter_lo = cat(in_arb_vals[1], in_arb_vals[0])
node in_arb_filter_hi_hi = cat(in_arb_vals[4], in_arb_vals[3])
node in_arb_filter_hi = cat(in_arb_filter_hi_hi, in_arb_vals[2])
node _in_arb_filter_T = cat(in_arb_filter_hi, in_arb_filter_lo)
node in_arb_filter_lo_1 = cat(in_arb_vals[1], in_arb_vals[0])
node in_arb_filter_hi_hi_1 = cat(in_arb_vals[4], in_arb_vals[3])
node in_arb_filter_hi_1 = cat(in_arb_filter_hi_hi_1, in_arb_vals[2])
node _in_arb_filter_T_1 = cat(in_arb_filter_hi_1, in_arb_filter_lo_1)
node _in_arb_filter_T_2 = not(mask)
node _in_arb_filter_T_3 = and(_in_arb_filter_T_1, _in_arb_filter_T_2)
node _in_arb_filter_T_4 = cat(_in_arb_filter_T, _in_arb_filter_T_3)
node _in_arb_filter_T_5 = bits(_in_arb_filter_T_4, 0, 0)
node _in_arb_filter_T_6 = bits(_in_arb_filter_T_4, 1, 1)
node _in_arb_filter_T_7 = bits(_in_arb_filter_T_4, 2, 2)
node _in_arb_filter_T_8 = bits(_in_arb_filter_T_4, 3, 3)
node _in_arb_filter_T_9 = bits(_in_arb_filter_T_4, 4, 4)
node _in_arb_filter_T_10 = bits(_in_arb_filter_T_4, 5, 5)
node _in_arb_filter_T_11 = bits(_in_arb_filter_T_4, 6, 6)
node _in_arb_filter_T_12 = bits(_in_arb_filter_T_4, 7, 7)
node _in_arb_filter_T_13 = bits(_in_arb_filter_T_4, 8, 8)
node _in_arb_filter_T_14 = bits(_in_arb_filter_T_4, 9, 9)
node _in_arb_filter_T_15 = mux(_in_arb_filter_T_14, UInt<10>(0h200), UInt<10>(0h0))
node _in_arb_filter_T_16 = mux(_in_arb_filter_T_13, UInt<10>(0h100), _in_arb_filter_T_15)
node _in_arb_filter_T_17 = mux(_in_arb_filter_T_12, UInt<10>(0h80), _in_arb_filter_T_16)
node _in_arb_filter_T_18 = mux(_in_arb_filter_T_11, UInt<10>(0h40), _in_arb_filter_T_17)
node _in_arb_filter_T_19 = mux(_in_arb_filter_T_10, UInt<10>(0h20), _in_arb_filter_T_18)
node _in_arb_filter_T_20 = mux(_in_arb_filter_T_9, UInt<10>(0h10), _in_arb_filter_T_19)
node _in_arb_filter_T_21 = mux(_in_arb_filter_T_8, UInt<10>(0h8), _in_arb_filter_T_20)
node _in_arb_filter_T_22 = mux(_in_arb_filter_T_7, UInt<10>(0h4), _in_arb_filter_T_21)
node _in_arb_filter_T_23 = mux(_in_arb_filter_T_6, UInt<10>(0h2), _in_arb_filter_T_22)
node in_arb_filter = mux(_in_arb_filter_T_5, UInt<10>(0h1), _in_arb_filter_T_23)
node _in_arb_sel_T = bits(in_arb_filter, 4, 0)
node _in_arb_sel_T_1 = shr(in_arb_filter, 5)
node in_arb_sel = or(_in_arb_sel_T, _in_arb_sel_T_1)
node _T = or(in_arb_vals[0], in_arb_vals[1])
node _T_1 = or(_T, in_arb_vals[2])
node _T_2 = or(_T_1, in_arb_vals[3])
node _T_3 = or(_T_2, in_arb_vals[4])
when _T_3 :
node _mask_T = not(UInt<1>(0h0))
node _mask_T_1 = not(UInt<2>(0h0))
node _mask_T_2 = not(UInt<3>(0h0))
node _mask_T_3 = not(UInt<4>(0h0))
node _mask_T_4 = not(UInt<5>(0h0))
node _mask_T_5 = bits(in_arb_sel, 0, 0)
node _mask_T_6 = bits(in_arb_sel, 1, 1)
node _mask_T_7 = bits(in_arb_sel, 2, 2)
node _mask_T_8 = bits(in_arb_sel, 3, 3)
node _mask_T_9 = bits(in_arb_sel, 4, 4)
node _mask_T_10 = mux(_mask_T_5, _mask_T, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_6, _mask_T_1, UInt<1>(0h0))
node _mask_T_12 = mux(_mask_T_7, _mask_T_2, UInt<1>(0h0))
node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0))
node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0))
node _mask_T_15 = or(_mask_T_10, _mask_T_11)
node _mask_T_16 = or(_mask_T_15, _mask_T_12)
node _mask_T_17 = or(_mask_T_16, _mask_T_13)
node _mask_T_18 = or(_mask_T_17, _mask_T_14)
wire _mask_WIRE : UInt<5>
connect _mask_WIRE, _mask_T_18
connect mask, _mask_WIRE
node _in_arb_reqs_0_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_0_T_1 = and(io.req.`0`.bits.vc_sel.`0`[0], _in_arb_reqs_0_0_0_T)
connect in_arb_reqs[0].`0`[0], _in_arb_reqs_0_0_0_T_1
node _in_arb_reqs_0_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_1_T_1 = and(io.req.`0`.bits.vc_sel.`0`[1], _in_arb_reqs_0_0_1_T)
connect in_arb_reqs[0].`0`[1], _in_arb_reqs_0_0_1_T_1
node _in_arb_reqs_0_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_0_2_T_1 = and(io.req.`0`.bits.vc_sel.`0`[2], _in_arb_reqs_0_0_2_T)
connect in_arb_reqs[0].`0`[2], _in_arb_reqs_0_0_2_T_1
node _in_arb_reqs_0_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_0_T_1 = and(io.req.`0`.bits.vc_sel.`1`[0], _in_arb_reqs_0_1_0_T)
connect in_arb_reqs[0].`1`[0], _in_arb_reqs_0_1_0_T_1
node _in_arb_reqs_0_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_1_T_1 = and(io.req.`0`.bits.vc_sel.`1`[1], _in_arb_reqs_0_1_1_T)
connect in_arb_reqs[0].`1`[1], _in_arb_reqs_0_1_1_T_1
node _in_arb_reqs_0_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_1_2_T_1 = and(io.req.`0`.bits.vc_sel.`1`[2], _in_arb_reqs_0_1_2_T)
connect in_arb_reqs[0].`1`[2], _in_arb_reqs_0_1_2_T_1
node _in_arb_reqs_0_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_0_T_1 = and(io.req.`0`.bits.vc_sel.`2`[0], _in_arb_reqs_0_2_0_T)
connect in_arb_reqs[0].`2`[0], _in_arb_reqs_0_2_0_T_1
node _in_arb_reqs_0_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_1_T_1 = and(io.req.`0`.bits.vc_sel.`2`[1], _in_arb_reqs_0_2_1_T)
connect in_arb_reqs[0].`2`[1], _in_arb_reqs_0_2_1_T_1
node _in_arb_reqs_0_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_2_2_T_1 = and(io.req.`0`.bits.vc_sel.`2`[2], _in_arb_reqs_0_2_2_T)
connect in_arb_reqs[0].`2`[2], _in_arb_reqs_0_2_2_T_1
node _in_arb_reqs_0_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_0_T_1 = and(io.req.`0`.bits.vc_sel.`3`[0], _in_arb_reqs_0_3_0_T)
connect in_arb_reqs[0].`3`[0], _in_arb_reqs_0_3_0_T_1
node _in_arb_reqs_0_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_1_T_1 = and(io.req.`0`.bits.vc_sel.`3`[1], _in_arb_reqs_0_3_1_T)
connect in_arb_reqs[0].`3`[1], _in_arb_reqs_0_3_1_T_1
node _in_arb_reqs_0_3_2_T = eq(io.channel_status.`3`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_3_2_T_1 = and(io.req.`0`.bits.vc_sel.`3`[2], _in_arb_reqs_0_3_2_T)
connect in_arb_reqs[0].`3`[2], _in_arb_reqs_0_3_2_T_1
node _in_arb_reqs_0_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_4_0_T_1 = and(io.req.`0`.bits.vc_sel.`4`[0], _in_arb_reqs_0_4_0_T)
connect in_arb_reqs[0].`4`[0], _in_arb_reqs_0_4_0_T_1
node _in_arb_reqs_0_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_0_5_0_T_1 = and(io.req.`0`.bits.vc_sel.`5`[0], _in_arb_reqs_0_5_0_T)
connect in_arb_reqs[0].`5`[0], _in_arb_reqs_0_5_0_T_1
node _in_arb_vals_0_T = or(in_arb_reqs[0].`0`[0], in_arb_reqs[0].`0`[1])
node _in_arb_vals_0_T_1 = or(_in_arb_vals_0_T, in_arb_reqs[0].`0`[2])
node _in_arb_vals_0_T_2 = or(in_arb_reqs[0].`1`[0], in_arb_reqs[0].`1`[1])
node _in_arb_vals_0_T_3 = or(_in_arb_vals_0_T_2, in_arb_reqs[0].`1`[2])
node _in_arb_vals_0_T_4 = or(in_arb_reqs[0].`2`[0], in_arb_reqs[0].`2`[1])
node _in_arb_vals_0_T_5 = or(_in_arb_vals_0_T_4, in_arb_reqs[0].`2`[2])
node _in_arb_vals_0_T_6 = or(in_arb_reqs[0].`3`[0], in_arb_reqs[0].`3`[1])
node _in_arb_vals_0_T_7 = or(_in_arb_vals_0_T_6, in_arb_reqs[0].`3`[2])
node _in_arb_vals_0_T_8 = or(_in_arb_vals_0_T_1, _in_arb_vals_0_T_3)
node _in_arb_vals_0_T_9 = or(_in_arb_vals_0_T_8, _in_arb_vals_0_T_5)
node _in_arb_vals_0_T_10 = or(_in_arb_vals_0_T_9, _in_arb_vals_0_T_7)
node _in_arb_vals_0_T_11 = or(_in_arb_vals_0_T_10, in_arb_reqs[0].`4`[0])
node _in_arb_vals_0_T_12 = or(_in_arb_vals_0_T_11, in_arb_reqs[0].`5`[0])
node _in_arb_vals_0_T_13 = and(io.req.`0`.valid, _in_arb_vals_0_T_12)
connect in_arb_vals[0], _in_arb_vals_0_T_13
node _in_arb_reqs_1_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_0_T_1 = and(io.req.`1`.bits.vc_sel.`0`[0], _in_arb_reqs_1_0_0_T)
connect in_arb_reqs[1].`0`[0], _in_arb_reqs_1_0_0_T_1
node _in_arb_reqs_1_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_1_T_1 = and(io.req.`1`.bits.vc_sel.`0`[1], _in_arb_reqs_1_0_1_T)
connect in_arb_reqs[1].`0`[1], _in_arb_reqs_1_0_1_T_1
node _in_arb_reqs_1_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_0_2_T_1 = and(io.req.`1`.bits.vc_sel.`0`[2], _in_arb_reqs_1_0_2_T)
connect in_arb_reqs[1].`0`[2], _in_arb_reqs_1_0_2_T_1
node _in_arb_reqs_1_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_0_T_1 = and(io.req.`1`.bits.vc_sel.`1`[0], _in_arb_reqs_1_1_0_T)
connect in_arb_reqs[1].`1`[0], _in_arb_reqs_1_1_0_T_1
node _in_arb_reqs_1_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_1_T_1 = and(io.req.`1`.bits.vc_sel.`1`[1], _in_arb_reqs_1_1_1_T)
connect in_arb_reqs[1].`1`[1], _in_arb_reqs_1_1_1_T_1
node _in_arb_reqs_1_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_1_2_T_1 = and(io.req.`1`.bits.vc_sel.`1`[2], _in_arb_reqs_1_1_2_T)
connect in_arb_reqs[1].`1`[2], _in_arb_reqs_1_1_2_T_1
node _in_arb_reqs_1_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_0_T_1 = and(io.req.`1`.bits.vc_sel.`2`[0], _in_arb_reqs_1_2_0_T)
connect in_arb_reqs[1].`2`[0], _in_arb_reqs_1_2_0_T_1
node _in_arb_reqs_1_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_1_T_1 = and(io.req.`1`.bits.vc_sel.`2`[1], _in_arb_reqs_1_2_1_T)
connect in_arb_reqs[1].`2`[1], _in_arb_reqs_1_2_1_T_1
node _in_arb_reqs_1_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_2_2_T_1 = and(io.req.`1`.bits.vc_sel.`2`[2], _in_arb_reqs_1_2_2_T)
connect in_arb_reqs[1].`2`[2], _in_arb_reqs_1_2_2_T_1
node _in_arb_reqs_1_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_0_T_1 = and(io.req.`1`.bits.vc_sel.`3`[0], _in_arb_reqs_1_3_0_T)
connect in_arb_reqs[1].`3`[0], _in_arb_reqs_1_3_0_T_1
node _in_arb_reqs_1_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_1_T_1 = and(io.req.`1`.bits.vc_sel.`3`[1], _in_arb_reqs_1_3_1_T)
connect in_arb_reqs[1].`3`[1], _in_arb_reqs_1_3_1_T_1
node _in_arb_reqs_1_3_2_T = eq(io.channel_status.`3`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_3_2_T_1 = and(io.req.`1`.bits.vc_sel.`3`[2], _in_arb_reqs_1_3_2_T)
connect in_arb_reqs[1].`3`[2], _in_arb_reqs_1_3_2_T_1
node _in_arb_reqs_1_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_4_0_T_1 = and(io.req.`1`.bits.vc_sel.`4`[0], _in_arb_reqs_1_4_0_T)
connect in_arb_reqs[1].`4`[0], _in_arb_reqs_1_4_0_T_1
node _in_arb_reqs_1_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_1_5_0_T_1 = and(io.req.`1`.bits.vc_sel.`5`[0], _in_arb_reqs_1_5_0_T)
connect in_arb_reqs[1].`5`[0], _in_arb_reqs_1_5_0_T_1
node _in_arb_vals_1_T = or(in_arb_reqs[1].`0`[0], in_arb_reqs[1].`0`[1])
node _in_arb_vals_1_T_1 = or(_in_arb_vals_1_T, in_arb_reqs[1].`0`[2])
node _in_arb_vals_1_T_2 = or(in_arb_reqs[1].`1`[0], in_arb_reqs[1].`1`[1])
node _in_arb_vals_1_T_3 = or(_in_arb_vals_1_T_2, in_arb_reqs[1].`1`[2])
node _in_arb_vals_1_T_4 = or(in_arb_reqs[1].`2`[0], in_arb_reqs[1].`2`[1])
node _in_arb_vals_1_T_5 = or(_in_arb_vals_1_T_4, in_arb_reqs[1].`2`[2])
node _in_arb_vals_1_T_6 = or(in_arb_reqs[1].`3`[0], in_arb_reqs[1].`3`[1])
node _in_arb_vals_1_T_7 = or(_in_arb_vals_1_T_6, in_arb_reqs[1].`3`[2])
node _in_arb_vals_1_T_8 = or(_in_arb_vals_1_T_1, _in_arb_vals_1_T_3)
node _in_arb_vals_1_T_9 = or(_in_arb_vals_1_T_8, _in_arb_vals_1_T_5)
node _in_arb_vals_1_T_10 = or(_in_arb_vals_1_T_9, _in_arb_vals_1_T_7)
node _in_arb_vals_1_T_11 = or(_in_arb_vals_1_T_10, in_arb_reqs[1].`4`[0])
node _in_arb_vals_1_T_12 = or(_in_arb_vals_1_T_11, in_arb_reqs[1].`5`[0])
node _in_arb_vals_1_T_13 = and(io.req.`1`.valid, _in_arb_vals_1_T_12)
connect in_arb_vals[1], _in_arb_vals_1_T_13
node _in_arb_reqs_2_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_0_T_1 = and(io.req.`2`.bits.vc_sel.`0`[0], _in_arb_reqs_2_0_0_T)
connect in_arb_reqs[2].`0`[0], _in_arb_reqs_2_0_0_T_1
node _in_arb_reqs_2_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_1_T_1 = and(io.req.`2`.bits.vc_sel.`0`[1], _in_arb_reqs_2_0_1_T)
connect in_arb_reqs[2].`0`[1], _in_arb_reqs_2_0_1_T_1
node _in_arb_reqs_2_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_0_2_T_1 = and(io.req.`2`.bits.vc_sel.`0`[2], _in_arb_reqs_2_0_2_T)
connect in_arb_reqs[2].`0`[2], _in_arb_reqs_2_0_2_T_1
node _in_arb_reqs_2_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_0_T_1 = and(io.req.`2`.bits.vc_sel.`1`[0], _in_arb_reqs_2_1_0_T)
connect in_arb_reqs[2].`1`[0], _in_arb_reqs_2_1_0_T_1
node _in_arb_reqs_2_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_1_T_1 = and(io.req.`2`.bits.vc_sel.`1`[1], _in_arb_reqs_2_1_1_T)
connect in_arb_reqs[2].`1`[1], _in_arb_reqs_2_1_1_T_1
node _in_arb_reqs_2_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_1_2_T_1 = and(io.req.`2`.bits.vc_sel.`1`[2], _in_arb_reqs_2_1_2_T)
connect in_arb_reqs[2].`1`[2], _in_arb_reqs_2_1_2_T_1
node _in_arb_reqs_2_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_0_T_1 = and(io.req.`2`.bits.vc_sel.`2`[0], _in_arb_reqs_2_2_0_T)
connect in_arb_reqs[2].`2`[0], _in_arb_reqs_2_2_0_T_1
node _in_arb_reqs_2_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_1_T_1 = and(io.req.`2`.bits.vc_sel.`2`[1], _in_arb_reqs_2_2_1_T)
connect in_arb_reqs[2].`2`[1], _in_arb_reqs_2_2_1_T_1
node _in_arb_reqs_2_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_2_2_T_1 = and(io.req.`2`.bits.vc_sel.`2`[2], _in_arb_reqs_2_2_2_T)
connect in_arb_reqs[2].`2`[2], _in_arb_reqs_2_2_2_T_1
node _in_arb_reqs_2_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_0_T_1 = and(io.req.`2`.bits.vc_sel.`3`[0], _in_arb_reqs_2_3_0_T)
connect in_arb_reqs[2].`3`[0], _in_arb_reqs_2_3_0_T_1
node _in_arb_reqs_2_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_1_T_1 = and(io.req.`2`.bits.vc_sel.`3`[1], _in_arb_reqs_2_3_1_T)
connect in_arb_reqs[2].`3`[1], _in_arb_reqs_2_3_1_T_1
node _in_arb_reqs_2_3_2_T = eq(io.channel_status.`3`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_3_2_T_1 = and(io.req.`2`.bits.vc_sel.`3`[2], _in_arb_reqs_2_3_2_T)
connect in_arb_reqs[2].`3`[2], _in_arb_reqs_2_3_2_T_1
node _in_arb_reqs_2_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_4_0_T_1 = and(io.req.`2`.bits.vc_sel.`4`[0], _in_arb_reqs_2_4_0_T)
connect in_arb_reqs[2].`4`[0], _in_arb_reqs_2_4_0_T_1
node _in_arb_reqs_2_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_2_5_0_T_1 = and(io.req.`2`.bits.vc_sel.`5`[0], _in_arb_reqs_2_5_0_T)
connect in_arb_reqs[2].`5`[0], _in_arb_reqs_2_5_0_T_1
node _in_arb_vals_2_T = or(in_arb_reqs[2].`0`[0], in_arb_reqs[2].`0`[1])
node _in_arb_vals_2_T_1 = or(_in_arb_vals_2_T, in_arb_reqs[2].`0`[2])
node _in_arb_vals_2_T_2 = or(in_arb_reqs[2].`1`[0], in_arb_reqs[2].`1`[1])
node _in_arb_vals_2_T_3 = or(_in_arb_vals_2_T_2, in_arb_reqs[2].`1`[2])
node _in_arb_vals_2_T_4 = or(in_arb_reqs[2].`2`[0], in_arb_reqs[2].`2`[1])
node _in_arb_vals_2_T_5 = or(_in_arb_vals_2_T_4, in_arb_reqs[2].`2`[2])
node _in_arb_vals_2_T_6 = or(in_arb_reqs[2].`3`[0], in_arb_reqs[2].`3`[1])
node _in_arb_vals_2_T_7 = or(_in_arb_vals_2_T_6, in_arb_reqs[2].`3`[2])
node _in_arb_vals_2_T_8 = or(_in_arb_vals_2_T_1, _in_arb_vals_2_T_3)
node _in_arb_vals_2_T_9 = or(_in_arb_vals_2_T_8, _in_arb_vals_2_T_5)
node _in_arb_vals_2_T_10 = or(_in_arb_vals_2_T_9, _in_arb_vals_2_T_7)
node _in_arb_vals_2_T_11 = or(_in_arb_vals_2_T_10, in_arb_reqs[2].`4`[0])
node _in_arb_vals_2_T_12 = or(_in_arb_vals_2_T_11, in_arb_reqs[2].`5`[0])
node _in_arb_vals_2_T_13 = and(io.req.`2`.valid, _in_arb_vals_2_T_12)
connect in_arb_vals[2], _in_arb_vals_2_T_13
node _in_arb_reqs_3_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_0_T_1 = and(io.req.`3`.bits.vc_sel.`0`[0], _in_arb_reqs_3_0_0_T)
connect in_arb_reqs[3].`0`[0], _in_arb_reqs_3_0_0_T_1
node _in_arb_reqs_3_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_1_T_1 = and(io.req.`3`.bits.vc_sel.`0`[1], _in_arb_reqs_3_0_1_T)
connect in_arb_reqs[3].`0`[1], _in_arb_reqs_3_0_1_T_1
node _in_arb_reqs_3_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_0_2_T_1 = and(io.req.`3`.bits.vc_sel.`0`[2], _in_arb_reqs_3_0_2_T)
connect in_arb_reqs[3].`0`[2], _in_arb_reqs_3_0_2_T_1
node _in_arb_reqs_3_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_0_T_1 = and(io.req.`3`.bits.vc_sel.`1`[0], _in_arb_reqs_3_1_0_T)
connect in_arb_reqs[3].`1`[0], _in_arb_reqs_3_1_0_T_1
node _in_arb_reqs_3_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_1_T_1 = and(io.req.`3`.bits.vc_sel.`1`[1], _in_arb_reqs_3_1_1_T)
connect in_arb_reqs[3].`1`[1], _in_arb_reqs_3_1_1_T_1
node _in_arb_reqs_3_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_1_2_T_1 = and(io.req.`3`.bits.vc_sel.`1`[2], _in_arb_reqs_3_1_2_T)
connect in_arb_reqs[3].`1`[2], _in_arb_reqs_3_1_2_T_1
node _in_arb_reqs_3_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_0_T_1 = and(io.req.`3`.bits.vc_sel.`2`[0], _in_arb_reqs_3_2_0_T)
connect in_arb_reqs[3].`2`[0], _in_arb_reqs_3_2_0_T_1
node _in_arb_reqs_3_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_1_T_1 = and(io.req.`3`.bits.vc_sel.`2`[1], _in_arb_reqs_3_2_1_T)
connect in_arb_reqs[3].`2`[1], _in_arb_reqs_3_2_1_T_1
node _in_arb_reqs_3_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_2_2_T_1 = and(io.req.`3`.bits.vc_sel.`2`[2], _in_arb_reqs_3_2_2_T)
connect in_arb_reqs[3].`2`[2], _in_arb_reqs_3_2_2_T_1
node _in_arb_reqs_3_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_0_T_1 = and(io.req.`3`.bits.vc_sel.`3`[0], _in_arb_reqs_3_3_0_T)
connect in_arb_reqs[3].`3`[0], _in_arb_reqs_3_3_0_T_1
node _in_arb_reqs_3_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_1_T_1 = and(io.req.`3`.bits.vc_sel.`3`[1], _in_arb_reqs_3_3_1_T)
connect in_arb_reqs[3].`3`[1], _in_arb_reqs_3_3_1_T_1
node _in_arb_reqs_3_3_2_T = eq(io.channel_status.`3`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_3_2_T_1 = and(io.req.`3`.bits.vc_sel.`3`[2], _in_arb_reqs_3_3_2_T)
connect in_arb_reqs[3].`3`[2], _in_arb_reqs_3_3_2_T_1
node _in_arb_reqs_3_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_4_0_T_1 = and(io.req.`3`.bits.vc_sel.`4`[0], _in_arb_reqs_3_4_0_T)
connect in_arb_reqs[3].`4`[0], _in_arb_reqs_3_4_0_T_1
node _in_arb_reqs_3_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_3_5_0_T_1 = and(io.req.`3`.bits.vc_sel.`5`[0], _in_arb_reqs_3_5_0_T)
connect in_arb_reqs[3].`5`[0], _in_arb_reqs_3_5_0_T_1
node _in_arb_vals_3_T = or(in_arb_reqs[3].`0`[0], in_arb_reqs[3].`0`[1])
node _in_arb_vals_3_T_1 = or(_in_arb_vals_3_T, in_arb_reqs[3].`0`[2])
node _in_arb_vals_3_T_2 = or(in_arb_reqs[3].`1`[0], in_arb_reqs[3].`1`[1])
node _in_arb_vals_3_T_3 = or(_in_arb_vals_3_T_2, in_arb_reqs[3].`1`[2])
node _in_arb_vals_3_T_4 = or(in_arb_reqs[3].`2`[0], in_arb_reqs[3].`2`[1])
node _in_arb_vals_3_T_5 = or(_in_arb_vals_3_T_4, in_arb_reqs[3].`2`[2])
node _in_arb_vals_3_T_6 = or(in_arb_reqs[3].`3`[0], in_arb_reqs[3].`3`[1])
node _in_arb_vals_3_T_7 = or(_in_arb_vals_3_T_6, in_arb_reqs[3].`3`[2])
node _in_arb_vals_3_T_8 = or(_in_arb_vals_3_T_1, _in_arb_vals_3_T_3)
node _in_arb_vals_3_T_9 = or(_in_arb_vals_3_T_8, _in_arb_vals_3_T_5)
node _in_arb_vals_3_T_10 = or(_in_arb_vals_3_T_9, _in_arb_vals_3_T_7)
node _in_arb_vals_3_T_11 = or(_in_arb_vals_3_T_10, in_arb_reqs[3].`4`[0])
node _in_arb_vals_3_T_12 = or(_in_arb_vals_3_T_11, in_arb_reqs[3].`5`[0])
node _in_arb_vals_3_T_13 = and(io.req.`3`.valid, _in_arb_vals_3_T_12)
connect in_arb_vals[3], _in_arb_vals_3_T_13
node _in_arb_reqs_4_0_0_T = eq(io.channel_status.`0`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_0_T_1 = and(io.req.`4`.bits.vc_sel.`0`[0], _in_arb_reqs_4_0_0_T)
connect in_arb_reqs[4].`0`[0], _in_arb_reqs_4_0_0_T_1
node _in_arb_reqs_4_0_1_T = eq(io.channel_status.`0`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_1_T_1 = and(io.req.`4`.bits.vc_sel.`0`[1], _in_arb_reqs_4_0_1_T)
connect in_arb_reqs[4].`0`[1], _in_arb_reqs_4_0_1_T_1
node _in_arb_reqs_4_0_2_T = eq(io.channel_status.`0`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_0_2_T_1 = and(io.req.`4`.bits.vc_sel.`0`[2], _in_arb_reqs_4_0_2_T)
connect in_arb_reqs[4].`0`[2], _in_arb_reqs_4_0_2_T_1
node _in_arb_reqs_4_1_0_T = eq(io.channel_status.`1`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_0_T_1 = and(io.req.`4`.bits.vc_sel.`1`[0], _in_arb_reqs_4_1_0_T)
connect in_arb_reqs[4].`1`[0], _in_arb_reqs_4_1_0_T_1
node _in_arb_reqs_4_1_1_T = eq(io.channel_status.`1`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_1_T_1 = and(io.req.`4`.bits.vc_sel.`1`[1], _in_arb_reqs_4_1_1_T)
connect in_arb_reqs[4].`1`[1], _in_arb_reqs_4_1_1_T_1
node _in_arb_reqs_4_1_2_T = eq(io.channel_status.`1`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_1_2_T_1 = and(io.req.`4`.bits.vc_sel.`1`[2], _in_arb_reqs_4_1_2_T)
connect in_arb_reqs[4].`1`[2], _in_arb_reqs_4_1_2_T_1
node _in_arb_reqs_4_2_0_T = eq(io.channel_status.`2`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_2_0_T_1 = and(io.req.`4`.bits.vc_sel.`2`[0], _in_arb_reqs_4_2_0_T)
connect in_arb_reqs[4].`2`[0], _in_arb_reqs_4_2_0_T_1
node _in_arb_reqs_4_2_1_T = eq(io.channel_status.`2`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_2_1_T_1 = and(io.req.`4`.bits.vc_sel.`2`[1], _in_arb_reqs_4_2_1_T)
connect in_arb_reqs[4].`2`[1], _in_arb_reqs_4_2_1_T_1
node _in_arb_reqs_4_2_2_T = eq(io.channel_status.`2`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_2_2_T_1 = and(io.req.`4`.bits.vc_sel.`2`[2], _in_arb_reqs_4_2_2_T)
connect in_arb_reqs[4].`2`[2], _in_arb_reqs_4_2_2_T_1
node _in_arb_reqs_4_3_0_T = eq(io.channel_status.`3`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_3_0_T_1 = and(io.req.`4`.bits.vc_sel.`3`[0], _in_arb_reqs_4_3_0_T)
connect in_arb_reqs[4].`3`[0], _in_arb_reqs_4_3_0_T_1
node _in_arb_reqs_4_3_1_T = eq(io.channel_status.`3`[1].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_3_1_T_1 = and(io.req.`4`.bits.vc_sel.`3`[1], _in_arb_reqs_4_3_1_T)
connect in_arb_reqs[4].`3`[1], _in_arb_reqs_4_3_1_T_1
node _in_arb_reqs_4_3_2_T = eq(io.channel_status.`3`[2].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_3_2_T_1 = and(io.req.`4`.bits.vc_sel.`3`[2], _in_arb_reqs_4_3_2_T)
connect in_arb_reqs[4].`3`[2], _in_arb_reqs_4_3_2_T_1
node _in_arb_reqs_4_4_0_T = eq(io.channel_status.`4`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_4_0_T_1 = and(io.req.`4`.bits.vc_sel.`4`[0], _in_arb_reqs_4_4_0_T)
connect in_arb_reqs[4].`4`[0], _in_arb_reqs_4_4_0_T_1
node _in_arb_reqs_4_5_0_T = eq(io.channel_status.`5`[0].occupied, UInt<1>(0h0))
node _in_arb_reqs_4_5_0_T_1 = and(io.req.`4`.bits.vc_sel.`5`[0], _in_arb_reqs_4_5_0_T)
connect in_arb_reqs[4].`5`[0], _in_arb_reqs_4_5_0_T_1
node _in_arb_vals_4_T = or(in_arb_reqs[4].`0`[0], in_arb_reqs[4].`0`[1])
node _in_arb_vals_4_T_1 = or(_in_arb_vals_4_T, in_arb_reqs[4].`0`[2])
node _in_arb_vals_4_T_2 = or(in_arb_reqs[4].`1`[0], in_arb_reqs[4].`1`[1])
node _in_arb_vals_4_T_3 = or(_in_arb_vals_4_T_2, in_arb_reqs[4].`1`[2])
node _in_arb_vals_4_T_4 = or(in_arb_reqs[4].`2`[0], in_arb_reqs[4].`2`[1])
node _in_arb_vals_4_T_5 = or(_in_arb_vals_4_T_4, in_arb_reqs[4].`2`[2])
node _in_arb_vals_4_T_6 = or(in_arb_reqs[4].`3`[0], in_arb_reqs[4].`3`[1])
node _in_arb_vals_4_T_7 = or(_in_arb_vals_4_T_6, in_arb_reqs[4].`3`[2])
node _in_arb_vals_4_T_8 = or(_in_arb_vals_4_T_1, _in_arb_vals_4_T_3)
node _in_arb_vals_4_T_9 = or(_in_arb_vals_4_T_8, _in_arb_vals_4_T_5)
node _in_arb_vals_4_T_10 = or(_in_arb_vals_4_T_9, _in_arb_vals_4_T_7)
node _in_arb_vals_4_T_11 = or(_in_arb_vals_4_T_10, in_arb_reqs[4].`4`[0])
node _in_arb_vals_4_T_12 = or(_in_arb_vals_4_T_11, in_arb_reqs[4].`5`[0])
node _in_arb_vals_4_T_13 = and(io.req.`4`.valid, _in_arb_vals_4_T_12)
connect in_arb_vals[4], _in_arb_vals_4_T_13
connect io.req.`0`.ready, UInt<1>(0h0)
connect io.req.`1`.ready, UInt<1>(0h0)
connect io.req.`2`.ready, UInt<1>(0h0)
connect io.req.`3`.ready, UInt<1>(0h0)
connect io.req.`4`.ready, UInt<1>(0h0)
wire in_alloc : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
node _in_flow_T = bits(in_arb_sel, 0, 0)
node _in_flow_T_1 = bits(in_arb_sel, 1, 1)
node _in_flow_T_2 = bits(in_arb_sel, 2, 2)
node _in_flow_T_3 = bits(in_arb_sel, 3, 3)
node _in_flow_T_4 = bits(in_arb_sel, 4, 4)
wire in_flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _in_flow_T_5 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_6 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_7 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_8 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_9 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node_id, UInt<1>(0h0))
node _in_flow_T_10 = or(_in_flow_T_5, _in_flow_T_6)
node _in_flow_T_11 = or(_in_flow_T_10, _in_flow_T_7)
node _in_flow_T_12 = or(_in_flow_T_11, _in_flow_T_8)
node _in_flow_T_13 = or(_in_flow_T_12, _in_flow_T_9)
wire _in_flow_WIRE : UInt<2>
connect _in_flow_WIRE, _in_flow_T_13
connect in_flow.egress_node_id, _in_flow_WIRE
node _in_flow_T_14 = mux(_in_flow_T, io.req.`0`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_15 = mux(_in_flow_T_1, io.req.`1`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_16 = mux(_in_flow_T_2, io.req.`2`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_17 = mux(_in_flow_T_3, io.req.`3`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_18 = mux(_in_flow_T_4, io.req.`4`.bits.flow.egress_node, UInt<1>(0h0))
node _in_flow_T_19 = or(_in_flow_T_14, _in_flow_T_15)
node _in_flow_T_20 = or(_in_flow_T_19, _in_flow_T_16)
node _in_flow_T_21 = or(_in_flow_T_20, _in_flow_T_17)
node _in_flow_T_22 = or(_in_flow_T_21, _in_flow_T_18)
wire _in_flow_WIRE_1 : UInt<4>
connect _in_flow_WIRE_1, _in_flow_T_22
connect in_flow.egress_node, _in_flow_WIRE_1
node _in_flow_T_23 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_24 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_25 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_26 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_27 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node_id, UInt<1>(0h0))
node _in_flow_T_28 = or(_in_flow_T_23, _in_flow_T_24)
node _in_flow_T_29 = or(_in_flow_T_28, _in_flow_T_25)
node _in_flow_T_30 = or(_in_flow_T_29, _in_flow_T_26)
node _in_flow_T_31 = or(_in_flow_T_30, _in_flow_T_27)
wire _in_flow_WIRE_2 : UInt<3>
connect _in_flow_WIRE_2, _in_flow_T_31
connect in_flow.ingress_node_id, _in_flow_WIRE_2
node _in_flow_T_32 = mux(_in_flow_T, io.req.`0`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_33 = mux(_in_flow_T_1, io.req.`1`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_34 = mux(_in_flow_T_2, io.req.`2`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_35 = mux(_in_flow_T_3, io.req.`3`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_36 = mux(_in_flow_T_4, io.req.`4`.bits.flow.ingress_node, UInt<1>(0h0))
node _in_flow_T_37 = or(_in_flow_T_32, _in_flow_T_33)
node _in_flow_T_38 = or(_in_flow_T_37, _in_flow_T_34)
node _in_flow_T_39 = or(_in_flow_T_38, _in_flow_T_35)
node _in_flow_T_40 = or(_in_flow_T_39, _in_flow_T_36)
wire _in_flow_WIRE_3 : UInt<4>
connect _in_flow_WIRE_3, _in_flow_T_40
connect in_flow.ingress_node, _in_flow_WIRE_3
node _in_flow_T_41 = mux(_in_flow_T, io.req.`0`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_42 = mux(_in_flow_T_1, io.req.`1`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_43 = mux(_in_flow_T_2, io.req.`2`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_44 = mux(_in_flow_T_3, io.req.`3`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_45 = mux(_in_flow_T_4, io.req.`4`.bits.flow.vnet_id, UInt<1>(0h0))
node _in_flow_T_46 = or(_in_flow_T_41, _in_flow_T_42)
node _in_flow_T_47 = or(_in_flow_T_46, _in_flow_T_43)
node _in_flow_T_48 = or(_in_flow_T_47, _in_flow_T_44)
node _in_flow_T_49 = or(_in_flow_T_48, _in_flow_T_45)
wire _in_flow_WIRE_4 : UInt<2>
connect _in_flow_WIRE_4, _in_flow_T_49
connect in_flow.vnet_id, _in_flow_WIRE_4
node _in_vc_T = bits(in_arb_sel, 0, 0)
node _in_vc_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_T_4 = bits(in_arb_sel, 4, 4)
node _in_vc_T_5 = mux(_in_vc_T, io.req.`0`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_6 = mux(_in_vc_T_1, io.req.`1`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_7 = mux(_in_vc_T_2, io.req.`2`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_8 = mux(_in_vc_T_3, io.req.`3`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_9 = mux(_in_vc_T_4, io.req.`4`.bits.in_vc, UInt<1>(0h0))
node _in_vc_T_10 = or(_in_vc_T_5, _in_vc_T_6)
node _in_vc_T_11 = or(_in_vc_T_10, _in_vc_T_7)
node _in_vc_T_12 = or(_in_vc_T_11, _in_vc_T_8)
node _in_vc_T_13 = or(_in_vc_T_12, _in_vc_T_9)
wire in_vc : UInt<2>
connect in_vc, _in_vc_T_13
node _in_vc_sel_T = bits(in_arb_sel, 0, 0)
node _in_vc_sel_T_1 = bits(in_arb_sel, 1, 1)
node _in_vc_sel_T_2 = bits(in_arb_sel, 2, 2)
node _in_vc_sel_T_3 = bits(in_arb_sel, 3, 3)
node _in_vc_sel_T_4 = bits(in_arb_sel, 4, 4)
wire in_vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _in_vc_sel_WIRE : UInt<1>[3]
node _in_vc_sel_T_5 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_6 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_7 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_8 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_9 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[0], UInt<1>(0h0))
node _in_vc_sel_T_10 = or(_in_vc_sel_T_5, _in_vc_sel_T_6)
node _in_vc_sel_T_11 = or(_in_vc_sel_T_10, _in_vc_sel_T_7)
node _in_vc_sel_T_12 = or(_in_vc_sel_T_11, _in_vc_sel_T_8)
node _in_vc_sel_T_13 = or(_in_vc_sel_T_12, _in_vc_sel_T_9)
wire _in_vc_sel_WIRE_1 : UInt<1>
connect _in_vc_sel_WIRE_1, _in_vc_sel_T_13
connect _in_vc_sel_WIRE[0], _in_vc_sel_WIRE_1
node _in_vc_sel_T_14 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_15 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_16 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_17 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_18 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[1], UInt<1>(0h0))
node _in_vc_sel_T_19 = or(_in_vc_sel_T_14, _in_vc_sel_T_15)
node _in_vc_sel_T_20 = or(_in_vc_sel_T_19, _in_vc_sel_T_16)
node _in_vc_sel_T_21 = or(_in_vc_sel_T_20, _in_vc_sel_T_17)
node _in_vc_sel_T_22 = or(_in_vc_sel_T_21, _in_vc_sel_T_18)
wire _in_vc_sel_WIRE_2 : UInt<1>
connect _in_vc_sel_WIRE_2, _in_vc_sel_T_22
connect _in_vc_sel_WIRE[1], _in_vc_sel_WIRE_2
node _in_vc_sel_T_23 = mux(_in_vc_sel_T, in_arb_reqs[0].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_24 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_25 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_26 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_27 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`0`[2], UInt<1>(0h0))
node _in_vc_sel_T_28 = or(_in_vc_sel_T_23, _in_vc_sel_T_24)
node _in_vc_sel_T_29 = or(_in_vc_sel_T_28, _in_vc_sel_T_25)
node _in_vc_sel_T_30 = or(_in_vc_sel_T_29, _in_vc_sel_T_26)
node _in_vc_sel_T_31 = or(_in_vc_sel_T_30, _in_vc_sel_T_27)
wire _in_vc_sel_WIRE_3 : UInt<1>
connect _in_vc_sel_WIRE_3, _in_vc_sel_T_31
connect _in_vc_sel_WIRE[2], _in_vc_sel_WIRE_3
connect in_vc_sel.`0`, _in_vc_sel_WIRE
wire _in_vc_sel_WIRE_4 : UInt<1>[3]
node _in_vc_sel_T_32 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_33 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_34 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_35 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_36 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[0], UInt<1>(0h0))
node _in_vc_sel_T_37 = or(_in_vc_sel_T_32, _in_vc_sel_T_33)
node _in_vc_sel_T_38 = or(_in_vc_sel_T_37, _in_vc_sel_T_34)
node _in_vc_sel_T_39 = or(_in_vc_sel_T_38, _in_vc_sel_T_35)
node _in_vc_sel_T_40 = or(_in_vc_sel_T_39, _in_vc_sel_T_36)
wire _in_vc_sel_WIRE_5 : UInt<1>
connect _in_vc_sel_WIRE_5, _in_vc_sel_T_40
connect _in_vc_sel_WIRE_4[0], _in_vc_sel_WIRE_5
node _in_vc_sel_T_41 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_42 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_43 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_44 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_45 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[1], UInt<1>(0h0))
node _in_vc_sel_T_46 = or(_in_vc_sel_T_41, _in_vc_sel_T_42)
node _in_vc_sel_T_47 = or(_in_vc_sel_T_46, _in_vc_sel_T_43)
node _in_vc_sel_T_48 = or(_in_vc_sel_T_47, _in_vc_sel_T_44)
node _in_vc_sel_T_49 = or(_in_vc_sel_T_48, _in_vc_sel_T_45)
wire _in_vc_sel_WIRE_6 : UInt<1>
connect _in_vc_sel_WIRE_6, _in_vc_sel_T_49
connect _in_vc_sel_WIRE_4[1], _in_vc_sel_WIRE_6
node _in_vc_sel_T_50 = mux(_in_vc_sel_T, in_arb_reqs[0].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_51 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_52 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_53 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_54 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`1`[2], UInt<1>(0h0))
node _in_vc_sel_T_55 = or(_in_vc_sel_T_50, _in_vc_sel_T_51)
node _in_vc_sel_T_56 = or(_in_vc_sel_T_55, _in_vc_sel_T_52)
node _in_vc_sel_T_57 = or(_in_vc_sel_T_56, _in_vc_sel_T_53)
node _in_vc_sel_T_58 = or(_in_vc_sel_T_57, _in_vc_sel_T_54)
wire _in_vc_sel_WIRE_7 : UInt<1>
connect _in_vc_sel_WIRE_7, _in_vc_sel_T_58
connect _in_vc_sel_WIRE_4[2], _in_vc_sel_WIRE_7
connect in_vc_sel.`1`, _in_vc_sel_WIRE_4
wire _in_vc_sel_WIRE_8 : UInt<1>[3]
node _in_vc_sel_T_59 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_60 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_61 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_62 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_63 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[0], UInt<1>(0h0))
node _in_vc_sel_T_64 = or(_in_vc_sel_T_59, _in_vc_sel_T_60)
node _in_vc_sel_T_65 = or(_in_vc_sel_T_64, _in_vc_sel_T_61)
node _in_vc_sel_T_66 = or(_in_vc_sel_T_65, _in_vc_sel_T_62)
node _in_vc_sel_T_67 = or(_in_vc_sel_T_66, _in_vc_sel_T_63)
wire _in_vc_sel_WIRE_9 : UInt<1>
connect _in_vc_sel_WIRE_9, _in_vc_sel_T_67
connect _in_vc_sel_WIRE_8[0], _in_vc_sel_WIRE_9
node _in_vc_sel_T_68 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_69 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_70 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_71 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_72 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[1], UInt<1>(0h0))
node _in_vc_sel_T_73 = or(_in_vc_sel_T_68, _in_vc_sel_T_69)
node _in_vc_sel_T_74 = or(_in_vc_sel_T_73, _in_vc_sel_T_70)
node _in_vc_sel_T_75 = or(_in_vc_sel_T_74, _in_vc_sel_T_71)
node _in_vc_sel_T_76 = or(_in_vc_sel_T_75, _in_vc_sel_T_72)
wire _in_vc_sel_WIRE_10 : UInt<1>
connect _in_vc_sel_WIRE_10, _in_vc_sel_T_76
connect _in_vc_sel_WIRE_8[1], _in_vc_sel_WIRE_10
node _in_vc_sel_T_77 = mux(_in_vc_sel_T, in_arb_reqs[0].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_78 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_79 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_80 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_81 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`2`[2], UInt<1>(0h0))
node _in_vc_sel_T_82 = or(_in_vc_sel_T_77, _in_vc_sel_T_78)
node _in_vc_sel_T_83 = or(_in_vc_sel_T_82, _in_vc_sel_T_79)
node _in_vc_sel_T_84 = or(_in_vc_sel_T_83, _in_vc_sel_T_80)
node _in_vc_sel_T_85 = or(_in_vc_sel_T_84, _in_vc_sel_T_81)
wire _in_vc_sel_WIRE_11 : UInt<1>
connect _in_vc_sel_WIRE_11, _in_vc_sel_T_85
connect _in_vc_sel_WIRE_8[2], _in_vc_sel_WIRE_11
connect in_vc_sel.`2`, _in_vc_sel_WIRE_8
wire _in_vc_sel_WIRE_12 : UInt<1>[3]
node _in_vc_sel_T_86 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_87 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_88 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_89 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_90 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[0], UInt<1>(0h0))
node _in_vc_sel_T_91 = or(_in_vc_sel_T_86, _in_vc_sel_T_87)
node _in_vc_sel_T_92 = or(_in_vc_sel_T_91, _in_vc_sel_T_88)
node _in_vc_sel_T_93 = or(_in_vc_sel_T_92, _in_vc_sel_T_89)
node _in_vc_sel_T_94 = or(_in_vc_sel_T_93, _in_vc_sel_T_90)
wire _in_vc_sel_WIRE_13 : UInt<1>
connect _in_vc_sel_WIRE_13, _in_vc_sel_T_94
connect _in_vc_sel_WIRE_12[0], _in_vc_sel_WIRE_13
node _in_vc_sel_T_95 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[1], UInt<1>(0h0))
node _in_vc_sel_T_96 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[1], UInt<1>(0h0))
node _in_vc_sel_T_97 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[1], UInt<1>(0h0))
node _in_vc_sel_T_98 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[1], UInt<1>(0h0))
node _in_vc_sel_T_99 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[1], UInt<1>(0h0))
node _in_vc_sel_T_100 = or(_in_vc_sel_T_95, _in_vc_sel_T_96)
node _in_vc_sel_T_101 = or(_in_vc_sel_T_100, _in_vc_sel_T_97)
node _in_vc_sel_T_102 = or(_in_vc_sel_T_101, _in_vc_sel_T_98)
node _in_vc_sel_T_103 = or(_in_vc_sel_T_102, _in_vc_sel_T_99)
wire _in_vc_sel_WIRE_14 : UInt<1>
connect _in_vc_sel_WIRE_14, _in_vc_sel_T_103
connect _in_vc_sel_WIRE_12[1], _in_vc_sel_WIRE_14
node _in_vc_sel_T_104 = mux(_in_vc_sel_T, in_arb_reqs[0].`3`[2], UInt<1>(0h0))
node _in_vc_sel_T_105 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`3`[2], UInt<1>(0h0))
node _in_vc_sel_T_106 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`3`[2], UInt<1>(0h0))
node _in_vc_sel_T_107 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`3`[2], UInt<1>(0h0))
node _in_vc_sel_T_108 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`3`[2], UInt<1>(0h0))
node _in_vc_sel_T_109 = or(_in_vc_sel_T_104, _in_vc_sel_T_105)
node _in_vc_sel_T_110 = or(_in_vc_sel_T_109, _in_vc_sel_T_106)
node _in_vc_sel_T_111 = or(_in_vc_sel_T_110, _in_vc_sel_T_107)
node _in_vc_sel_T_112 = or(_in_vc_sel_T_111, _in_vc_sel_T_108)
wire _in_vc_sel_WIRE_15 : UInt<1>
connect _in_vc_sel_WIRE_15, _in_vc_sel_T_112
connect _in_vc_sel_WIRE_12[2], _in_vc_sel_WIRE_15
connect in_vc_sel.`3`, _in_vc_sel_WIRE_12
wire _in_vc_sel_WIRE_16 : UInt<1>[1]
node _in_vc_sel_T_113 = mux(_in_vc_sel_T, in_arb_reqs[0].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_114 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_115 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_116 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_117 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`4`[0], UInt<1>(0h0))
node _in_vc_sel_T_118 = or(_in_vc_sel_T_113, _in_vc_sel_T_114)
node _in_vc_sel_T_119 = or(_in_vc_sel_T_118, _in_vc_sel_T_115)
node _in_vc_sel_T_120 = or(_in_vc_sel_T_119, _in_vc_sel_T_116)
node _in_vc_sel_T_121 = or(_in_vc_sel_T_120, _in_vc_sel_T_117)
wire _in_vc_sel_WIRE_17 : UInt<1>
connect _in_vc_sel_WIRE_17, _in_vc_sel_T_121
connect _in_vc_sel_WIRE_16[0], _in_vc_sel_WIRE_17
connect in_vc_sel.`4`, _in_vc_sel_WIRE_16
wire _in_vc_sel_WIRE_18 : UInt<1>[1]
node _in_vc_sel_T_122 = mux(_in_vc_sel_T, in_arb_reqs[0].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_123 = mux(_in_vc_sel_T_1, in_arb_reqs[1].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_124 = mux(_in_vc_sel_T_2, in_arb_reqs[2].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_125 = mux(_in_vc_sel_T_3, in_arb_reqs[3].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_126 = mux(_in_vc_sel_T_4, in_arb_reqs[4].`5`[0], UInt<1>(0h0))
node _in_vc_sel_T_127 = or(_in_vc_sel_T_122, _in_vc_sel_T_123)
node _in_vc_sel_T_128 = or(_in_vc_sel_T_127, _in_vc_sel_T_124)
node _in_vc_sel_T_129 = or(_in_vc_sel_T_128, _in_vc_sel_T_125)
node _in_vc_sel_T_130 = or(_in_vc_sel_T_129, _in_vc_sel_T_126)
wire _in_vc_sel_WIRE_19 : UInt<1>
connect _in_vc_sel_WIRE_19, _in_vc_sel_T_130
connect _in_vc_sel_WIRE_18[0], _in_vc_sel_WIRE_19
connect in_vc_sel.`5`, _in_vc_sel_WIRE_18
node _T_4 = or(in_arb_vals[0], in_arb_vals[1])
node _T_5 = or(_T_4, in_arb_vals[2])
node _T_6 = or(_T_5, in_arb_vals[3])
node _T_7 = or(_T_6, in_arb_vals[4])
node hi = bits(in_arb_sel, 4, 4)
node lo = bits(in_arb_sel, 3, 0)
node _T_8 = orr(hi)
node _T_9 = or(hi, lo)
node hi_1 = bits(_T_9, 3, 2)
node lo_1 = bits(_T_9, 1, 0)
node _T_10 = orr(hi_1)
node _T_11 = or(hi_1, lo_1)
node _T_12 = bits(_T_11, 1, 1)
node _T_13 = cat(_T_10, _T_12)
node _T_14 = cat(_T_8, _T_13)
node _T_15 = and(io.req.`0`.ready, io.req.`0`.valid)
node _T_16 = and(io.req.`1`.ready, io.req.`1`.valid)
node _T_17 = and(io.req.`2`.ready, io.req.`2`.valid)
node _T_18 = and(io.req.`3`.ready, io.req.`3`.valid)
node _T_19 = and(io.req.`4`.ready, io.req.`4`.valid)
node _T_20 = or(_T_15, _T_16)
node _T_21 = or(_T_20, _T_17)
node _T_22 = or(_T_21, _T_18)
node _T_23 = or(_T_22, _T_19)
node hi_2 = cat(in_vc_sel.`0`[2], in_vc_sel.`0`[1])
node _T_24 = cat(hi_2, in_vc_sel.`0`[0])
node hi_3 = cat(in_vc_sel.`1`[2], in_vc_sel.`1`[1])
node _T_25 = cat(hi_3, in_vc_sel.`1`[0])
node hi_4 = cat(in_vc_sel.`2`[2], in_vc_sel.`2`[1])
node _T_26 = cat(hi_4, in_vc_sel.`2`[0])
node hi_5 = cat(in_vc_sel.`3`[2], in_vc_sel.`3`[1])
node _T_27 = cat(hi_5, in_vc_sel.`3`[0])
node lo_hi = cat(_T_26, _T_25)
node lo_2 = cat(lo_hi, _T_24)
node hi_hi = cat(in_vc_sel.`5`[0], in_vc_sel.`4`[0])
node hi_6 = cat(hi_hi, _T_27)
node _T_28 = cat(hi_6, lo_2)
regreset mask_1 : UInt<14>, clock, reset, UInt<14>(0h0)
node _full_T = not(mask_1)
node _full_T_1 = and(_T_28, _full_T)
node full = cat(_T_28, _full_T_1)
node _oh_T = bits(full, 0, 0)
node _oh_T_1 = bits(full, 1, 1)
node _oh_T_2 = bits(full, 2, 2)
node _oh_T_3 = bits(full, 3, 3)
node _oh_T_4 = bits(full, 4, 4)
node _oh_T_5 = bits(full, 5, 5)
node _oh_T_6 = bits(full, 6, 6)
node _oh_T_7 = bits(full, 7, 7)
node _oh_T_8 = bits(full, 8, 8)
node _oh_T_9 = bits(full, 9, 9)
node _oh_T_10 = bits(full, 10, 10)
node _oh_T_11 = bits(full, 11, 11)
node _oh_T_12 = bits(full, 12, 12)
node _oh_T_13 = bits(full, 13, 13)
node _oh_T_14 = bits(full, 14, 14)
node _oh_T_15 = bits(full, 15, 15)
node _oh_T_16 = bits(full, 16, 16)
node _oh_T_17 = bits(full, 17, 17)
node _oh_T_18 = bits(full, 18, 18)
node _oh_T_19 = bits(full, 19, 19)
node _oh_T_20 = bits(full, 20, 20)
node _oh_T_21 = bits(full, 21, 21)
node _oh_T_22 = bits(full, 22, 22)
node _oh_T_23 = bits(full, 23, 23)
node _oh_T_24 = bits(full, 24, 24)
node _oh_T_25 = bits(full, 25, 25)
node _oh_T_26 = bits(full, 26, 26)
node _oh_T_27 = bits(full, 27, 27)
node _oh_T_28 = mux(_oh_T_27, UInt<28>(0h8000000), UInt<28>(0h0))
node _oh_T_29 = mux(_oh_T_26, UInt<28>(0h4000000), _oh_T_28)
node _oh_T_30 = mux(_oh_T_25, UInt<28>(0h2000000), _oh_T_29)
node _oh_T_31 = mux(_oh_T_24, UInt<28>(0h1000000), _oh_T_30)
node _oh_T_32 = mux(_oh_T_23, UInt<28>(0h800000), _oh_T_31)
node _oh_T_33 = mux(_oh_T_22, UInt<28>(0h400000), _oh_T_32)
node _oh_T_34 = mux(_oh_T_21, UInt<28>(0h200000), _oh_T_33)
node _oh_T_35 = mux(_oh_T_20, UInt<28>(0h100000), _oh_T_34)
node _oh_T_36 = mux(_oh_T_19, UInt<28>(0h80000), _oh_T_35)
node _oh_T_37 = mux(_oh_T_18, UInt<28>(0h40000), _oh_T_36)
node _oh_T_38 = mux(_oh_T_17, UInt<28>(0h20000), _oh_T_37)
node _oh_T_39 = mux(_oh_T_16, UInt<28>(0h10000), _oh_T_38)
node _oh_T_40 = mux(_oh_T_15, UInt<28>(0h8000), _oh_T_39)
node _oh_T_41 = mux(_oh_T_14, UInt<28>(0h4000), _oh_T_40)
node _oh_T_42 = mux(_oh_T_13, UInt<28>(0h2000), _oh_T_41)
node _oh_T_43 = mux(_oh_T_12, UInt<28>(0h1000), _oh_T_42)
node _oh_T_44 = mux(_oh_T_11, UInt<28>(0h800), _oh_T_43)
node _oh_T_45 = mux(_oh_T_10, UInt<28>(0h400), _oh_T_44)
node _oh_T_46 = mux(_oh_T_9, UInt<28>(0h200), _oh_T_45)
node _oh_T_47 = mux(_oh_T_8, UInt<28>(0h100), _oh_T_46)
node _oh_T_48 = mux(_oh_T_7, UInt<28>(0h80), _oh_T_47)
node _oh_T_49 = mux(_oh_T_6, UInt<28>(0h40), _oh_T_48)
node _oh_T_50 = mux(_oh_T_5, UInt<28>(0h20), _oh_T_49)
node _oh_T_51 = mux(_oh_T_4, UInt<28>(0h10), _oh_T_50)
node _oh_T_52 = mux(_oh_T_3, UInt<28>(0h8), _oh_T_51)
node _oh_T_53 = mux(_oh_T_2, UInt<28>(0h4), _oh_T_52)
node _oh_T_54 = mux(_oh_T_1, UInt<28>(0h2), _oh_T_53)
node oh = mux(_oh_T, UInt<28>(0h1), _oh_T_54)
node _sel_T = bits(oh, 13, 0)
node _sel_T_1 = shr(oh, 14)
node sel = or(_sel_T, _sel_T_1)
when _T_23 :
node _mask_T_19 = bits(sel, 0, 0)
node _mask_T_20 = not(UInt<1>(0h0))
node _mask_T_21 = bits(sel, 1, 1)
node _mask_T_22 = not(UInt<2>(0h0))
node _mask_T_23 = bits(sel, 2, 2)
node _mask_T_24 = not(UInt<3>(0h0))
node _mask_T_25 = bits(sel, 3, 3)
node _mask_T_26 = not(UInt<4>(0h0))
node _mask_T_27 = bits(sel, 4, 4)
node _mask_T_28 = not(UInt<5>(0h0))
node _mask_T_29 = bits(sel, 5, 5)
node _mask_T_30 = not(UInt<6>(0h0))
node _mask_T_31 = bits(sel, 6, 6)
node _mask_T_32 = not(UInt<7>(0h0))
node _mask_T_33 = bits(sel, 7, 7)
node _mask_T_34 = not(UInt<8>(0h0))
node _mask_T_35 = bits(sel, 8, 8)
node _mask_T_36 = not(UInt<9>(0h0))
node _mask_T_37 = bits(sel, 9, 9)
node _mask_T_38 = not(UInt<10>(0h0))
node _mask_T_39 = bits(sel, 10, 10)
node _mask_T_40 = not(UInt<11>(0h0))
node _mask_T_41 = bits(sel, 11, 11)
node _mask_T_42 = not(UInt<12>(0h0))
node _mask_T_43 = bits(sel, 12, 12)
node _mask_T_44 = not(UInt<13>(0h0))
node _mask_T_45 = bits(sel, 13, 13)
node _mask_T_46 = not(UInt<14>(0h0))
node _mask_T_47 = mux(_mask_T_45, _mask_T_46, UInt<1>(0h0))
node _mask_T_48 = mux(_mask_T_43, _mask_T_44, _mask_T_47)
node _mask_T_49 = mux(_mask_T_41, _mask_T_42, _mask_T_48)
node _mask_T_50 = mux(_mask_T_39, _mask_T_40, _mask_T_49)
node _mask_T_51 = mux(_mask_T_37, _mask_T_38, _mask_T_50)
node _mask_T_52 = mux(_mask_T_35, _mask_T_36, _mask_T_51)
node _mask_T_53 = mux(_mask_T_33, _mask_T_34, _mask_T_52)
node _mask_T_54 = mux(_mask_T_31, _mask_T_32, _mask_T_53)
node _mask_T_55 = mux(_mask_T_29, _mask_T_30, _mask_T_54)
node _mask_T_56 = mux(_mask_T_27, _mask_T_28, _mask_T_55)
node _mask_T_57 = mux(_mask_T_25, _mask_T_26, _mask_T_56)
node _mask_T_58 = mux(_mask_T_23, _mask_T_24, _mask_T_57)
node _mask_T_59 = mux(_mask_T_21, _mask_T_22, _mask_T_58)
node _mask_T_60 = mux(_mask_T_19, _mask_T_20, _mask_T_59)
connect mask_1, _mask_T_60
wire _WIRE : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _WIRE_1 : UInt<14>
connect _WIRE_1, sel
node _T_29 = bits(_WIRE_1, 0, 0)
connect _WIRE.`0`[0], _T_29
node _T_30 = bits(_WIRE_1, 1, 1)
connect _WIRE.`0`[1], _T_30
node _T_31 = bits(_WIRE_1, 2, 2)
connect _WIRE.`0`[2], _T_31
node _T_32 = bits(_WIRE_1, 3, 3)
connect _WIRE.`1`[0], _T_32
node _T_33 = bits(_WIRE_1, 4, 4)
connect _WIRE.`1`[1], _T_33
node _T_34 = bits(_WIRE_1, 5, 5)
connect _WIRE.`1`[2], _T_34
node _T_35 = bits(_WIRE_1, 6, 6)
connect _WIRE.`2`[0], _T_35
node _T_36 = bits(_WIRE_1, 7, 7)
connect _WIRE.`2`[1], _T_36
node _T_37 = bits(_WIRE_1, 8, 8)
connect _WIRE.`2`[2], _T_37
node _T_38 = bits(_WIRE_1, 9, 9)
connect _WIRE.`3`[0], _T_38
node _T_39 = bits(_WIRE_1, 10, 10)
connect _WIRE.`3`[1], _T_39
node _T_40 = bits(_WIRE_1, 11, 11)
connect _WIRE.`3`[2], _T_40
node _T_41 = bits(_WIRE_1, 12, 12)
connect _WIRE.`4`[0], _T_41
node _T_42 = bits(_WIRE_1, 13, 13)
connect _WIRE.`5`[0], _T_42
wire _WIRE_2 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
connect _WIRE_2.`0`[0], UInt<1>(0h0)
connect _WIRE_2.`0`[1], UInt<1>(0h0)
connect _WIRE_2.`0`[2], UInt<1>(0h0)
connect _WIRE_2.`1`[0], UInt<1>(0h0)
connect _WIRE_2.`1`[1], UInt<1>(0h0)
connect _WIRE_2.`1`[2], UInt<1>(0h0)
connect _WIRE_2.`2`[0], UInt<1>(0h0)
connect _WIRE_2.`2`[1], UInt<1>(0h0)
connect _WIRE_2.`2`[2], UInt<1>(0h0)
connect _WIRE_2.`3`[0], UInt<1>(0h0)
connect _WIRE_2.`3`[1], UInt<1>(0h0)
connect _WIRE_2.`3`[2], UInt<1>(0h0)
connect _WIRE_2.`4`[0], UInt<1>(0h0)
connect _WIRE_2.`5`[0], UInt<1>(0h0)
node _T_43 = mux(_T_7, _WIRE, _WIRE_2)
connect in_alloc.`0`, _T_43.`0`
connect in_alloc.`1`, _T_43.`1`
connect in_alloc.`2`, _T_43.`2`
connect in_alloc.`3`, _T_43.`3`
connect in_alloc.`4`, _T_43.`4`
connect in_alloc.`5`, _T_43.`5`
node _io_req_0_ready_T = bits(in_arb_sel, 0, 0)
connect io.req.`0`.ready, _io_req_0_ready_T
connect io.resp.`0`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`0`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`0`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`0`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`0`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`0`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`0`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`0`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`0`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`0`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`0`.vc_sel.`3`[1], in_alloc.`3`[1]
connect io.resp.`0`.vc_sel.`3`[2], in_alloc.`3`[2]
connect io.resp.`0`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`0`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_7 = cat(io.resp.`0`.vc_sel.`0`[2], io.resp.`0`.vc_sel.`0`[1])
node _T_44 = cat(hi_7, io.resp.`0`.vc_sel.`0`[0])
node hi_8 = cat(io.resp.`0`.vc_sel.`1`[2], io.resp.`0`.vc_sel.`1`[1])
node _T_45 = cat(hi_8, io.resp.`0`.vc_sel.`1`[0])
node hi_9 = cat(io.resp.`0`.vc_sel.`2`[2], io.resp.`0`.vc_sel.`2`[1])
node _T_46 = cat(hi_9, io.resp.`0`.vc_sel.`2`[0])
node hi_10 = cat(io.resp.`0`.vc_sel.`3`[2], io.resp.`0`.vc_sel.`3`[1])
node _T_47 = cat(hi_10, io.resp.`0`.vc_sel.`3`[0])
node lo_hi_1 = cat(_T_46, _T_45)
node lo_3 = cat(lo_hi_1, _T_44)
node hi_hi_1 = cat(io.resp.`0`.vc_sel.`5`[0], io.resp.`0`.vc_sel.`4`[0])
node hi_11 = cat(hi_hi_1, _T_47)
node _T_48 = cat(hi_11, lo_3)
node _T_49 = bits(_T_48, 0, 0)
node _T_50 = bits(_T_48, 1, 1)
node _T_51 = bits(_T_48, 2, 2)
node _T_52 = bits(_T_48, 3, 3)
node _T_53 = bits(_T_48, 4, 4)
node _T_54 = bits(_T_48, 5, 5)
node _T_55 = bits(_T_48, 6, 6)
node _T_56 = bits(_T_48, 7, 7)
node _T_57 = bits(_T_48, 8, 8)
node _T_58 = bits(_T_48, 9, 9)
node _T_59 = bits(_T_48, 10, 10)
node _T_60 = bits(_T_48, 11, 11)
node _T_61 = bits(_T_48, 12, 12)
node _T_62 = bits(_T_48, 13, 13)
node _T_63 = add(_T_50, _T_51)
node _T_64 = bits(_T_63, 1, 0)
node _T_65 = add(_T_49, _T_64)
node _T_66 = bits(_T_65, 1, 0)
node _T_67 = add(_T_52, _T_53)
node _T_68 = bits(_T_67, 1, 0)
node _T_69 = add(_T_54, _T_55)
node _T_70 = bits(_T_69, 1, 0)
node _T_71 = add(_T_68, _T_70)
node _T_72 = bits(_T_71, 2, 0)
node _T_73 = add(_T_66, _T_72)
node _T_74 = bits(_T_73, 2, 0)
node _T_75 = add(_T_57, _T_58)
node _T_76 = bits(_T_75, 1, 0)
node _T_77 = add(_T_56, _T_76)
node _T_78 = bits(_T_77, 1, 0)
node _T_79 = add(_T_59, _T_60)
node _T_80 = bits(_T_79, 1, 0)
node _T_81 = add(_T_61, _T_62)
node _T_82 = bits(_T_81, 1, 0)
node _T_83 = add(_T_80, _T_82)
node _T_84 = bits(_T_83, 2, 0)
node _T_85 = add(_T_78, _T_84)
node _T_86 = bits(_T_85, 2, 0)
node _T_87 = add(_T_74, _T_86)
node _T_88 = bits(_T_87, 3, 0)
node _T_89 = leq(_T_88, UInt<1>(0h1))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf
assert(clock, _T_89, UInt<1>(0h1), "") : assert
node _io_req_1_ready_T = bits(in_arb_sel, 1, 1)
connect io.req.`1`.ready, _io_req_1_ready_T
connect io.resp.`1`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`1`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`1`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`1`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`1`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`1`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`1`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`1`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`1`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`1`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`1`.vc_sel.`3`[1], in_alloc.`3`[1]
connect io.resp.`1`.vc_sel.`3`[2], in_alloc.`3`[2]
connect io.resp.`1`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`1`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_12 = cat(io.resp.`1`.vc_sel.`0`[2], io.resp.`1`.vc_sel.`0`[1])
node _T_93 = cat(hi_12, io.resp.`1`.vc_sel.`0`[0])
node hi_13 = cat(io.resp.`1`.vc_sel.`1`[2], io.resp.`1`.vc_sel.`1`[1])
node _T_94 = cat(hi_13, io.resp.`1`.vc_sel.`1`[0])
node hi_14 = cat(io.resp.`1`.vc_sel.`2`[2], io.resp.`1`.vc_sel.`2`[1])
node _T_95 = cat(hi_14, io.resp.`1`.vc_sel.`2`[0])
node hi_15 = cat(io.resp.`1`.vc_sel.`3`[2], io.resp.`1`.vc_sel.`3`[1])
node _T_96 = cat(hi_15, io.resp.`1`.vc_sel.`3`[0])
node lo_hi_2 = cat(_T_95, _T_94)
node lo_4 = cat(lo_hi_2, _T_93)
node hi_hi_2 = cat(io.resp.`1`.vc_sel.`5`[0], io.resp.`1`.vc_sel.`4`[0])
node hi_16 = cat(hi_hi_2, _T_96)
node _T_97 = cat(hi_16, lo_4)
node _T_98 = bits(_T_97, 0, 0)
node _T_99 = bits(_T_97, 1, 1)
node _T_100 = bits(_T_97, 2, 2)
node _T_101 = bits(_T_97, 3, 3)
node _T_102 = bits(_T_97, 4, 4)
node _T_103 = bits(_T_97, 5, 5)
node _T_104 = bits(_T_97, 6, 6)
node _T_105 = bits(_T_97, 7, 7)
node _T_106 = bits(_T_97, 8, 8)
node _T_107 = bits(_T_97, 9, 9)
node _T_108 = bits(_T_97, 10, 10)
node _T_109 = bits(_T_97, 11, 11)
node _T_110 = bits(_T_97, 12, 12)
node _T_111 = bits(_T_97, 13, 13)
node _T_112 = add(_T_99, _T_100)
node _T_113 = bits(_T_112, 1, 0)
node _T_114 = add(_T_98, _T_113)
node _T_115 = bits(_T_114, 1, 0)
node _T_116 = add(_T_101, _T_102)
node _T_117 = bits(_T_116, 1, 0)
node _T_118 = add(_T_103, _T_104)
node _T_119 = bits(_T_118, 1, 0)
node _T_120 = add(_T_117, _T_119)
node _T_121 = bits(_T_120, 2, 0)
node _T_122 = add(_T_115, _T_121)
node _T_123 = bits(_T_122, 2, 0)
node _T_124 = add(_T_106, _T_107)
node _T_125 = bits(_T_124, 1, 0)
node _T_126 = add(_T_105, _T_125)
node _T_127 = bits(_T_126, 1, 0)
node _T_128 = add(_T_108, _T_109)
node _T_129 = bits(_T_128, 1, 0)
node _T_130 = add(_T_110, _T_111)
node _T_131 = bits(_T_130, 1, 0)
node _T_132 = add(_T_129, _T_131)
node _T_133 = bits(_T_132, 2, 0)
node _T_134 = add(_T_127, _T_133)
node _T_135 = bits(_T_134, 2, 0)
node _T_136 = add(_T_123, _T_135)
node _T_137 = bits(_T_136, 3, 0)
node _T_138 = leq(_T_137, UInt<1>(0h1))
node _T_139 = asUInt(reset)
node _T_140 = eq(_T_139, UInt<1>(0h0))
when _T_140 :
node _T_141 = eq(_T_138, UInt<1>(0h0))
when _T_141 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_1
assert(clock, _T_138, UInt<1>(0h1), "") : assert_1
node _io_req_2_ready_T = bits(in_arb_sel, 2, 2)
connect io.req.`2`.ready, _io_req_2_ready_T
connect io.resp.`2`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`2`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`2`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`2`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`2`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`2`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`2`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`2`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`2`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`2`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`2`.vc_sel.`3`[1], in_alloc.`3`[1]
connect io.resp.`2`.vc_sel.`3`[2], in_alloc.`3`[2]
connect io.resp.`2`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`2`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_17 = cat(io.resp.`2`.vc_sel.`0`[2], io.resp.`2`.vc_sel.`0`[1])
node _T_142 = cat(hi_17, io.resp.`2`.vc_sel.`0`[0])
node hi_18 = cat(io.resp.`2`.vc_sel.`1`[2], io.resp.`2`.vc_sel.`1`[1])
node _T_143 = cat(hi_18, io.resp.`2`.vc_sel.`1`[0])
node hi_19 = cat(io.resp.`2`.vc_sel.`2`[2], io.resp.`2`.vc_sel.`2`[1])
node _T_144 = cat(hi_19, io.resp.`2`.vc_sel.`2`[0])
node hi_20 = cat(io.resp.`2`.vc_sel.`3`[2], io.resp.`2`.vc_sel.`3`[1])
node _T_145 = cat(hi_20, io.resp.`2`.vc_sel.`3`[0])
node lo_hi_3 = cat(_T_144, _T_143)
node lo_5 = cat(lo_hi_3, _T_142)
node hi_hi_3 = cat(io.resp.`2`.vc_sel.`5`[0], io.resp.`2`.vc_sel.`4`[0])
node hi_21 = cat(hi_hi_3, _T_145)
node _T_146 = cat(hi_21, lo_5)
node _T_147 = bits(_T_146, 0, 0)
node _T_148 = bits(_T_146, 1, 1)
node _T_149 = bits(_T_146, 2, 2)
node _T_150 = bits(_T_146, 3, 3)
node _T_151 = bits(_T_146, 4, 4)
node _T_152 = bits(_T_146, 5, 5)
node _T_153 = bits(_T_146, 6, 6)
node _T_154 = bits(_T_146, 7, 7)
node _T_155 = bits(_T_146, 8, 8)
node _T_156 = bits(_T_146, 9, 9)
node _T_157 = bits(_T_146, 10, 10)
node _T_158 = bits(_T_146, 11, 11)
node _T_159 = bits(_T_146, 12, 12)
node _T_160 = bits(_T_146, 13, 13)
node _T_161 = add(_T_148, _T_149)
node _T_162 = bits(_T_161, 1, 0)
node _T_163 = add(_T_147, _T_162)
node _T_164 = bits(_T_163, 1, 0)
node _T_165 = add(_T_150, _T_151)
node _T_166 = bits(_T_165, 1, 0)
node _T_167 = add(_T_152, _T_153)
node _T_168 = bits(_T_167, 1, 0)
node _T_169 = add(_T_166, _T_168)
node _T_170 = bits(_T_169, 2, 0)
node _T_171 = add(_T_164, _T_170)
node _T_172 = bits(_T_171, 2, 0)
node _T_173 = add(_T_155, _T_156)
node _T_174 = bits(_T_173, 1, 0)
node _T_175 = add(_T_154, _T_174)
node _T_176 = bits(_T_175, 1, 0)
node _T_177 = add(_T_157, _T_158)
node _T_178 = bits(_T_177, 1, 0)
node _T_179 = add(_T_159, _T_160)
node _T_180 = bits(_T_179, 1, 0)
node _T_181 = add(_T_178, _T_180)
node _T_182 = bits(_T_181, 2, 0)
node _T_183 = add(_T_176, _T_182)
node _T_184 = bits(_T_183, 2, 0)
node _T_185 = add(_T_172, _T_184)
node _T_186 = bits(_T_185, 3, 0)
node _T_187 = leq(_T_186, UInt<1>(0h1))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_2
assert(clock, _T_187, UInt<1>(0h1), "") : assert_2
node _io_req_3_ready_T = bits(in_arb_sel, 3, 3)
connect io.req.`3`.ready, _io_req_3_ready_T
connect io.resp.`3`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`3`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`3`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`3`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`3`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`3`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`3`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`3`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`3`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`3`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`3`.vc_sel.`3`[1], in_alloc.`3`[1]
connect io.resp.`3`.vc_sel.`3`[2], in_alloc.`3`[2]
connect io.resp.`3`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`3`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_22 = cat(io.resp.`3`.vc_sel.`0`[2], io.resp.`3`.vc_sel.`0`[1])
node _T_191 = cat(hi_22, io.resp.`3`.vc_sel.`0`[0])
node hi_23 = cat(io.resp.`3`.vc_sel.`1`[2], io.resp.`3`.vc_sel.`1`[1])
node _T_192 = cat(hi_23, io.resp.`3`.vc_sel.`1`[0])
node hi_24 = cat(io.resp.`3`.vc_sel.`2`[2], io.resp.`3`.vc_sel.`2`[1])
node _T_193 = cat(hi_24, io.resp.`3`.vc_sel.`2`[0])
node hi_25 = cat(io.resp.`3`.vc_sel.`3`[2], io.resp.`3`.vc_sel.`3`[1])
node _T_194 = cat(hi_25, io.resp.`3`.vc_sel.`3`[0])
node lo_hi_4 = cat(_T_193, _T_192)
node lo_6 = cat(lo_hi_4, _T_191)
node hi_hi_4 = cat(io.resp.`3`.vc_sel.`5`[0], io.resp.`3`.vc_sel.`4`[0])
node hi_26 = cat(hi_hi_4, _T_194)
node _T_195 = cat(hi_26, lo_6)
node _T_196 = bits(_T_195, 0, 0)
node _T_197 = bits(_T_195, 1, 1)
node _T_198 = bits(_T_195, 2, 2)
node _T_199 = bits(_T_195, 3, 3)
node _T_200 = bits(_T_195, 4, 4)
node _T_201 = bits(_T_195, 5, 5)
node _T_202 = bits(_T_195, 6, 6)
node _T_203 = bits(_T_195, 7, 7)
node _T_204 = bits(_T_195, 8, 8)
node _T_205 = bits(_T_195, 9, 9)
node _T_206 = bits(_T_195, 10, 10)
node _T_207 = bits(_T_195, 11, 11)
node _T_208 = bits(_T_195, 12, 12)
node _T_209 = bits(_T_195, 13, 13)
node _T_210 = add(_T_197, _T_198)
node _T_211 = bits(_T_210, 1, 0)
node _T_212 = add(_T_196, _T_211)
node _T_213 = bits(_T_212, 1, 0)
node _T_214 = add(_T_199, _T_200)
node _T_215 = bits(_T_214, 1, 0)
node _T_216 = add(_T_201, _T_202)
node _T_217 = bits(_T_216, 1, 0)
node _T_218 = add(_T_215, _T_217)
node _T_219 = bits(_T_218, 2, 0)
node _T_220 = add(_T_213, _T_219)
node _T_221 = bits(_T_220, 2, 0)
node _T_222 = add(_T_204, _T_205)
node _T_223 = bits(_T_222, 1, 0)
node _T_224 = add(_T_203, _T_223)
node _T_225 = bits(_T_224, 1, 0)
node _T_226 = add(_T_206, _T_207)
node _T_227 = bits(_T_226, 1, 0)
node _T_228 = add(_T_208, _T_209)
node _T_229 = bits(_T_228, 1, 0)
node _T_230 = add(_T_227, _T_229)
node _T_231 = bits(_T_230, 2, 0)
node _T_232 = add(_T_225, _T_231)
node _T_233 = bits(_T_232, 2, 0)
node _T_234 = add(_T_221, _T_233)
node _T_235 = bits(_T_234, 3, 0)
node _T_236 = leq(_T_235, UInt<1>(0h1))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_3
assert(clock, _T_236, UInt<1>(0h1), "") : assert_3
node _io_req_4_ready_T = bits(in_arb_sel, 4, 4)
connect io.req.`4`.ready, _io_req_4_ready_T
connect io.resp.`4`.vc_sel.`0`[0], in_alloc.`0`[0]
connect io.resp.`4`.vc_sel.`0`[1], in_alloc.`0`[1]
connect io.resp.`4`.vc_sel.`0`[2], in_alloc.`0`[2]
connect io.resp.`4`.vc_sel.`1`[0], in_alloc.`1`[0]
connect io.resp.`4`.vc_sel.`1`[1], in_alloc.`1`[1]
connect io.resp.`4`.vc_sel.`1`[2], in_alloc.`1`[2]
connect io.resp.`4`.vc_sel.`2`[0], in_alloc.`2`[0]
connect io.resp.`4`.vc_sel.`2`[1], in_alloc.`2`[1]
connect io.resp.`4`.vc_sel.`2`[2], in_alloc.`2`[2]
connect io.resp.`4`.vc_sel.`3`[0], in_alloc.`3`[0]
connect io.resp.`4`.vc_sel.`3`[1], in_alloc.`3`[1]
connect io.resp.`4`.vc_sel.`3`[2], in_alloc.`3`[2]
connect io.resp.`4`.vc_sel.`4`[0], in_alloc.`4`[0]
connect io.resp.`4`.vc_sel.`5`[0], in_alloc.`5`[0]
node hi_27 = cat(io.resp.`4`.vc_sel.`0`[2], io.resp.`4`.vc_sel.`0`[1])
node _T_240 = cat(hi_27, io.resp.`4`.vc_sel.`0`[0])
node hi_28 = cat(io.resp.`4`.vc_sel.`1`[2], io.resp.`4`.vc_sel.`1`[1])
node _T_241 = cat(hi_28, io.resp.`4`.vc_sel.`1`[0])
node hi_29 = cat(io.resp.`4`.vc_sel.`2`[2], io.resp.`4`.vc_sel.`2`[1])
node _T_242 = cat(hi_29, io.resp.`4`.vc_sel.`2`[0])
node hi_30 = cat(io.resp.`4`.vc_sel.`3`[2], io.resp.`4`.vc_sel.`3`[1])
node _T_243 = cat(hi_30, io.resp.`4`.vc_sel.`3`[0])
node lo_hi_5 = cat(_T_242, _T_241)
node lo_7 = cat(lo_hi_5, _T_240)
node hi_hi_5 = cat(io.resp.`4`.vc_sel.`5`[0], io.resp.`4`.vc_sel.`4`[0])
node hi_31 = cat(hi_hi_5, _T_243)
node _T_244 = cat(hi_31, lo_7)
node _T_245 = bits(_T_244, 0, 0)
node _T_246 = bits(_T_244, 1, 1)
node _T_247 = bits(_T_244, 2, 2)
node _T_248 = bits(_T_244, 3, 3)
node _T_249 = bits(_T_244, 4, 4)
node _T_250 = bits(_T_244, 5, 5)
node _T_251 = bits(_T_244, 6, 6)
node _T_252 = bits(_T_244, 7, 7)
node _T_253 = bits(_T_244, 8, 8)
node _T_254 = bits(_T_244, 9, 9)
node _T_255 = bits(_T_244, 10, 10)
node _T_256 = bits(_T_244, 11, 11)
node _T_257 = bits(_T_244, 12, 12)
node _T_258 = bits(_T_244, 13, 13)
node _T_259 = add(_T_246, _T_247)
node _T_260 = bits(_T_259, 1, 0)
node _T_261 = add(_T_245, _T_260)
node _T_262 = bits(_T_261, 1, 0)
node _T_263 = add(_T_248, _T_249)
node _T_264 = bits(_T_263, 1, 0)
node _T_265 = add(_T_250, _T_251)
node _T_266 = bits(_T_265, 1, 0)
node _T_267 = add(_T_264, _T_266)
node _T_268 = bits(_T_267, 2, 0)
node _T_269 = add(_T_262, _T_268)
node _T_270 = bits(_T_269, 2, 0)
node _T_271 = add(_T_253, _T_254)
node _T_272 = bits(_T_271, 1, 0)
node _T_273 = add(_T_252, _T_272)
node _T_274 = bits(_T_273, 1, 0)
node _T_275 = add(_T_255, _T_256)
node _T_276 = bits(_T_275, 1, 0)
node _T_277 = add(_T_257, _T_258)
node _T_278 = bits(_T_277, 1, 0)
node _T_279 = add(_T_276, _T_278)
node _T_280 = bits(_T_279, 2, 0)
node _T_281 = add(_T_274, _T_280)
node _T_282 = bits(_T_281, 2, 0)
node _T_283 = add(_T_270, _T_282)
node _T_284 = bits(_T_283, 3, 0)
node _T_285 = leq(_T_284, UInt<1>(0h1))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SingleVCAllocator.scala:53 assert(PopCount(io.resp(i).vc_sel.asUInt) <= 1.U)\n") : printf_4
assert(clock, _T_285, UInt<1>(0h1), "") : assert_4
connect io.out_allocs.`0`[0].alloc, in_alloc.`0`[0]
connect io.out_allocs.`0`[0].flow, in_flow
connect io.out_allocs.`0`[1].alloc, in_alloc.`0`[1]
connect io.out_allocs.`0`[1].flow, in_flow
connect io.out_allocs.`0`[2].alloc, in_alloc.`0`[2]
connect io.out_allocs.`0`[2].flow, in_flow
connect io.out_allocs.`1`[0].alloc, in_alloc.`1`[0]
connect io.out_allocs.`1`[0].flow, in_flow
connect io.out_allocs.`1`[1].alloc, in_alloc.`1`[1]
connect io.out_allocs.`1`[1].flow, in_flow
connect io.out_allocs.`1`[2].alloc, in_alloc.`1`[2]
connect io.out_allocs.`1`[2].flow, in_flow
connect io.out_allocs.`2`[0].alloc, in_alloc.`2`[0]
connect io.out_allocs.`2`[0].flow, in_flow
connect io.out_allocs.`2`[1].alloc, in_alloc.`2`[1]
connect io.out_allocs.`2`[1].flow, in_flow
connect io.out_allocs.`2`[2].alloc, in_alloc.`2`[2]
connect io.out_allocs.`2`[2].flow, in_flow
connect io.out_allocs.`3`[0].alloc, in_alloc.`3`[0]
connect io.out_allocs.`3`[0].flow, in_flow
connect io.out_allocs.`3`[1].alloc, in_alloc.`3`[1]
connect io.out_allocs.`3`[1].flow, in_flow
connect io.out_allocs.`3`[2].alloc, in_alloc.`3`[2]
connect io.out_allocs.`3`[2].flow, in_flow
connect io.out_allocs.`4`[0].alloc, in_alloc.`4`[0]
connect io.out_allocs.`4`[0].flow, in_flow
connect io.out_allocs.`5`[0].alloc, in_alloc.`5`[0]
connect io.out_allocs.`5`[0].flow, in_flow | module RotatingSingleVCAllocator_5( // @[ISLIP.scala:43:7]
input clock, // @[ISLIP.scala:43:7]
input reset, // @[ISLIP.scala:43:7]
output io_req_4_ready, // @[VCAllocator.scala:49:14]
input io_req_4_valid, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_4_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_3_ready, // @[VCAllocator.scala:49:14]
input io_req_3_valid, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_3_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_2_ready, // @[VCAllocator.scala:49:14]
input io_req_2_valid, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_2_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_1_ready, // @[VCAllocator.scala:49:14]
input io_req_1_valid, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_1_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_req_0_ready, // @[VCAllocator.scala:49:14]
input io_req_0_valid, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_5_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_4_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_2_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_1_2, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_0, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_1, // @[VCAllocator.scala:49:14]
input io_req_0_bits_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_3_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_3_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_2_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_2_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_4_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_3_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_3_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_3_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_1_2, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_2_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_3_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_2_2, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_0, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_1, // @[VCAllocator.scala:49:14]
output io_resp_1_vc_sel_0_2, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_5_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_4_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_0, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_1, // @[VCAllocator.scala:49:14]
output io_resp_0_vc_sel_3_2, // @[VCAllocator.scala:49:14]
input io_channel_status_5_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_4_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_3_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_3_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_3_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_2_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_1_2_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_0_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_1_occupied, // @[VCAllocator.scala:49:14]
input io_channel_status_0_2_occupied, // @[VCAllocator.scala:49:14]
output io_out_allocs_5_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_4_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_3_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_2_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_1_2_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_0_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_1_alloc, // @[VCAllocator.scala:49:14]
output io_out_allocs_0_2_alloc // @[VCAllocator.scala:49:14]
);
wire in_arb_vals_4; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_3; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_2; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_1; // @[SingleVCAllocator.scala:32:39]
wire in_arb_vals_0; // @[SingleVCAllocator.scala:32:39]
reg [4:0] mask; // @[SingleVCAllocator.scala:16:21]
wire [4:0] _in_arb_filter_T_3 = {in_arb_vals_4, in_arb_vals_3, in_arb_vals_2, in_arb_vals_1, in_arb_vals_0} & ~mask; // @[SingleVCAllocator.scala:16:21, :19:{77,84,86}, :32:39]
wire [9:0] in_arb_filter = _in_arb_filter_T_3[0] ? 10'h1 : _in_arb_filter_T_3[1] ? 10'h2 : _in_arb_filter_T_3[2] ? 10'h4 : _in_arb_filter_T_3[3] ? 10'h8 : _in_arb_filter_T_3[4] ? 10'h10 : in_arb_vals_0 ? 10'h20 : in_arb_vals_1 ? 10'h40 : in_arb_vals_2 ? 10'h80 : in_arb_vals_3 ? 10'h100 : {in_arb_vals_4, 9'h0}; // @[OneHot.scala:85:71]
wire [4:0] in_arb_sel = in_arb_filter[4:0] | in_arb_filter[9:5]; // @[Mux.scala:50:70]
wire _GEN = in_arb_vals_0 | in_arb_vals_1 | in_arb_vals_2 | in_arb_vals_3 | in_arb_vals_4; // @[package.scala:81:59]
wire in_arb_reqs_0_0_0 = io_req_0_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_1 = io_req_0_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_0_2 = io_req_0_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_0 = io_req_0_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_1 = io_req_0_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_1_2 = io_req_0_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_0 = io_req_0_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_1 = io_req_0_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_2_2 = io_req_0_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_0 = io_req_0_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_1 = io_req_0_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_3_2 = io_req_0_bits_vc_sel_3_2 & ~io_channel_status_3_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_4_0 = io_req_0_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_0_5_0 = io_req_0_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_0 = io_req_0_valid & (in_arb_reqs_0_0_0 | in_arb_reqs_0_0_1 | in_arb_reqs_0_0_2 | in_arb_reqs_0_1_0 | in_arb_reqs_0_1_1 | in_arb_reqs_0_1_2 | in_arb_reqs_0_2_0 | in_arb_reqs_0_2_1 | in_arb_reqs_0_2_2 | in_arb_reqs_0_3_0 | in_arb_reqs_0_3_1 | in_arb_reqs_0_3_2 | in_arb_reqs_0_4_0 | in_arb_reqs_0_5_0); // @[package.scala:81:59]
wire in_arb_reqs_1_0_0 = io_req_1_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_1 = io_req_1_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_0_2 = io_req_1_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_0 = io_req_1_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_1 = io_req_1_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_1_2 = io_req_1_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_0 = io_req_1_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_1 = io_req_1_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_2_2 = io_req_1_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_0 = io_req_1_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_1 = io_req_1_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_3_2 = io_req_1_bits_vc_sel_3_2 & ~io_channel_status_3_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_4_0 = io_req_1_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_1_5_0 = io_req_1_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_1 = io_req_1_valid & (in_arb_reqs_1_0_0 | in_arb_reqs_1_0_1 | in_arb_reqs_1_0_2 | in_arb_reqs_1_1_0 | in_arb_reqs_1_1_1 | in_arb_reqs_1_1_2 | in_arb_reqs_1_2_0 | in_arb_reqs_1_2_1 | in_arb_reqs_1_2_2 | in_arb_reqs_1_3_0 | in_arb_reqs_1_3_1 | in_arb_reqs_1_3_2 | in_arb_reqs_1_4_0 | in_arb_reqs_1_5_0); // @[package.scala:81:59]
wire in_arb_reqs_2_0_0 = io_req_2_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_1 = io_req_2_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_0_2 = io_req_2_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_0 = io_req_2_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_1 = io_req_2_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_1_2 = io_req_2_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_0 = io_req_2_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_1 = io_req_2_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_2_2 = io_req_2_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_3_0 = io_req_2_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_3_1 = io_req_2_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_3_2 = io_req_2_bits_vc_sel_3_2 & ~io_channel_status_3_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_4_0 = io_req_2_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_2_5_0 = io_req_2_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_2 = io_req_2_valid & (in_arb_reqs_2_0_0 | in_arb_reqs_2_0_1 | in_arb_reqs_2_0_2 | in_arb_reqs_2_1_0 | in_arb_reqs_2_1_1 | in_arb_reqs_2_1_2 | in_arb_reqs_2_2_0 | in_arb_reqs_2_2_1 | in_arb_reqs_2_2_2 | in_arb_reqs_2_3_0 | in_arb_reqs_2_3_1 | in_arb_reqs_2_3_2 | in_arb_reqs_2_4_0 | in_arb_reqs_2_5_0); // @[package.scala:81:59]
wire in_arb_reqs_3_0_0 = io_req_3_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_1 = io_req_3_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_0_2 = io_req_3_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_1_0 = io_req_3_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_1_1 = io_req_3_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_1_2 = io_req_3_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_2_0 = io_req_3_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_2_1 = io_req_3_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_2_2 = io_req_3_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_3_0 = io_req_3_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_3_1 = io_req_3_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_3_2 = io_req_3_bits_vc_sel_3_2 & ~io_channel_status_3_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_4_0 = io_req_3_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_3_5_0 = io_req_3_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_3 = io_req_3_valid & (in_arb_reqs_3_0_0 | in_arb_reqs_3_0_1 | in_arb_reqs_3_0_2 | in_arb_reqs_3_1_0 | in_arb_reqs_3_1_1 | in_arb_reqs_3_1_2 | in_arb_reqs_3_2_0 | in_arb_reqs_3_2_1 | in_arb_reqs_3_2_2 | in_arb_reqs_3_3_0 | in_arb_reqs_3_3_1 | in_arb_reqs_3_3_2 | in_arb_reqs_3_4_0 | in_arb_reqs_3_5_0); // @[package.scala:81:59]
wire in_arb_reqs_4_0_0 = io_req_4_bits_vc_sel_0_0 & ~io_channel_status_0_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_0_1 = io_req_4_bits_vc_sel_0_1 & ~io_channel_status_0_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_0_2 = io_req_4_bits_vc_sel_0_2 & ~io_channel_status_0_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_1_0 = io_req_4_bits_vc_sel_1_0 & ~io_channel_status_1_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_1_1 = io_req_4_bits_vc_sel_1_1 & ~io_channel_status_1_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_1_2 = io_req_4_bits_vc_sel_1_2 & ~io_channel_status_1_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_2_0 = io_req_4_bits_vc_sel_2_0 & ~io_channel_status_2_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_2_1 = io_req_4_bits_vc_sel_2_1 & ~io_channel_status_2_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_2_2 = io_req_4_bits_vc_sel_2_2 & ~io_channel_status_2_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_3_0 = io_req_4_bits_vc_sel_3_0 & ~io_channel_status_3_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_3_1 = io_req_4_bits_vc_sel_3_1 & ~io_channel_status_3_1_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_3_2 = io_req_4_bits_vc_sel_3_2 & ~io_channel_status_3_2_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_4_0 = io_req_4_bits_vc_sel_4_0 & ~io_channel_status_4_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
wire in_arb_reqs_4_5_0 = io_req_4_bits_vc_sel_5_0 & ~io_channel_status_5_0_occupied; // @[SingleVCAllocator.scala:28:{61,64}]
assign in_arb_vals_4 = io_req_4_valid & (in_arb_reqs_4_0_0 | in_arb_reqs_4_0_1 | in_arb_reqs_4_0_2 | in_arb_reqs_4_1_0 | in_arb_reqs_4_1_1 | in_arb_reqs_4_1_2 | in_arb_reqs_4_2_0 | in_arb_reqs_4_2_1 | in_arb_reqs_4_2_2 | in_arb_reqs_4_3_0 | in_arb_reqs_4_3_1 | in_arb_reqs_4_3_2 | in_arb_reqs_4_4_0 | in_arb_reqs_4_5_0); // @[package.scala:81:59]
wire _in_vc_sel_T_13 = in_arb_sel[0] & in_arb_reqs_0_0_0 | in_arb_sel[1] & in_arb_reqs_1_0_0 | in_arb_sel[2] & in_arb_reqs_2_0_0 | in_arb_sel[3] & in_arb_reqs_3_0_0 | in_arb_sel[4] & in_arb_reqs_4_0_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_22 = in_arb_sel[0] & in_arb_reqs_0_0_1 | in_arb_sel[1] & in_arb_reqs_1_0_1 | in_arb_sel[2] & in_arb_reqs_2_0_1 | in_arb_sel[3] & in_arb_reqs_3_0_1 | in_arb_sel[4] & in_arb_reqs_4_0_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_31 = in_arb_sel[0] & in_arb_reqs_0_0_2 | in_arb_sel[1] & in_arb_reqs_1_0_2 | in_arb_sel[2] & in_arb_reqs_2_0_2 | in_arb_sel[3] & in_arb_reqs_3_0_2 | in_arb_sel[4] & in_arb_reqs_4_0_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_40 = in_arb_sel[0] & in_arb_reqs_0_1_0 | in_arb_sel[1] & in_arb_reqs_1_1_0 | in_arb_sel[2] & in_arb_reqs_2_1_0 | in_arb_sel[3] & in_arb_reqs_3_1_0 | in_arb_sel[4] & in_arb_reqs_4_1_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_49 = in_arb_sel[0] & in_arb_reqs_0_1_1 | in_arb_sel[1] & in_arb_reqs_1_1_1 | in_arb_sel[2] & in_arb_reqs_2_1_1 | in_arb_sel[3] & in_arb_reqs_3_1_1 | in_arb_sel[4] & in_arb_reqs_4_1_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_58 = in_arb_sel[0] & in_arb_reqs_0_1_2 | in_arb_sel[1] & in_arb_reqs_1_1_2 | in_arb_sel[2] & in_arb_reqs_2_1_2 | in_arb_sel[3] & in_arb_reqs_3_1_2 | in_arb_sel[4] & in_arb_reqs_4_1_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_67 = in_arb_sel[0] & in_arb_reqs_0_2_0 | in_arb_sel[1] & in_arb_reqs_1_2_0 | in_arb_sel[2] & in_arb_reqs_2_2_0 | in_arb_sel[3] & in_arb_reqs_3_2_0 | in_arb_sel[4] & in_arb_reqs_4_2_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_76 = in_arb_sel[0] & in_arb_reqs_0_2_1 | in_arb_sel[1] & in_arb_reqs_1_2_1 | in_arb_sel[2] & in_arb_reqs_2_2_1 | in_arb_sel[3] & in_arb_reqs_3_2_1 | in_arb_sel[4] & in_arb_reqs_4_2_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_85 = in_arb_sel[0] & in_arb_reqs_0_2_2 | in_arb_sel[1] & in_arb_reqs_1_2_2 | in_arb_sel[2] & in_arb_reqs_2_2_2 | in_arb_sel[3] & in_arb_reqs_3_2_2 | in_arb_sel[4] & in_arb_reqs_4_2_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_94 = in_arb_sel[0] & in_arb_reqs_0_3_0 | in_arb_sel[1] & in_arb_reqs_1_3_0 | in_arb_sel[2] & in_arb_reqs_2_3_0 | in_arb_sel[3] & in_arb_reqs_3_3_0 | in_arb_sel[4] & in_arb_reqs_4_3_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_103 = in_arb_sel[0] & in_arb_reqs_0_3_1 | in_arb_sel[1] & in_arb_reqs_1_3_1 | in_arb_sel[2] & in_arb_reqs_2_3_1 | in_arb_sel[3] & in_arb_reqs_3_3_1 | in_arb_sel[4] & in_arb_reqs_4_3_1; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_112 = in_arb_sel[0] & in_arb_reqs_0_3_2 | in_arb_sel[1] & in_arb_reqs_1_3_2 | in_arb_sel[2] & in_arb_reqs_2_3_2 | in_arb_sel[3] & in_arb_reqs_3_3_2 | in_arb_sel[4] & in_arb_reqs_4_3_2; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_121 = in_arb_sel[0] & in_arb_reqs_0_4_0 | in_arb_sel[1] & in_arb_reqs_1_4_0 | in_arb_sel[2] & in_arb_reqs_2_4_0 | in_arb_sel[3] & in_arb_reqs_3_4_0 | in_arb_sel[4] & in_arb_reqs_4_4_0; // @[Mux.scala:30:73, :32:36]
wire _in_vc_sel_T_130 = in_arb_sel[0] & in_arb_reqs_0_5_0 | in_arb_sel[1] & in_arb_reqs_1_5_0 | in_arb_sel[2] & in_arb_reqs_2_5_0 | in_arb_sel[3] & in_arb_reqs_3_5_0 | in_arb_sel[4] & in_arb_reqs_4_5_0; // @[Mux.scala:30:73, :32:36]
reg [13:0] mask_1; // @[ISLIP.scala:17:25]
wire [13:0] _full_T_1 = {_in_vc_sel_T_130, _in_vc_sel_T_121, _in_vc_sel_T_112, _in_vc_sel_T_103, _in_vc_sel_T_94, _in_vc_sel_T_85, _in_vc_sel_T_76, _in_vc_sel_T_67, _in_vc_sel_T_58, _in_vc_sel_T_49, _in_vc_sel_T_40, _in_vc_sel_T_31, _in_vc_sel_T_22, _in_vc_sel_T_13} & ~mask_1; // @[Mux.scala:30:73]
wire [27:0] oh = _full_T_1[0] ? 28'h1 : _full_T_1[1] ? 28'h2 : _full_T_1[2] ? 28'h4 : _full_T_1[3] ? 28'h8 : _full_T_1[4] ? 28'h10 : _full_T_1[5] ? 28'h20 : _full_T_1[6] ? 28'h40 : _full_T_1[7] ? 28'h80 : _full_T_1[8] ? 28'h100 : _full_T_1[9] ? 28'h200 : _full_T_1[10] ? 28'h400 : _full_T_1[11] ? 28'h800 : _full_T_1[12] ? 28'h1000 : _full_T_1[13] ? 28'h2000 : _in_vc_sel_T_13 ? 28'h4000 : _in_vc_sel_T_22 ? 28'h8000 : _in_vc_sel_T_31 ? 28'h10000 : _in_vc_sel_T_40 ? 28'h20000 : _in_vc_sel_T_49 ? 28'h40000 : _in_vc_sel_T_58 ? 28'h80000 : _in_vc_sel_T_67 ? 28'h100000 : _in_vc_sel_T_76 ? 28'h200000 : _in_vc_sel_T_85 ? 28'h400000 : _in_vc_sel_T_94 ? 28'h800000 : _in_vc_sel_T_103 ? 28'h1000000 : _in_vc_sel_T_112 ? 28'h2000000 : _in_vc_sel_T_121 ? 28'h4000000 : {_in_vc_sel_T_130, 27'h0}; // @[OneHot.scala:85:71]
wire [13:0] sel = oh[13:0] | oh[27:14]; // @[Mux.scala:50:70]
wire in_alloc_5_0 = _GEN & sel[13]; // @[package.scala:81:59]
wire in_alloc_4_0 = _GEN & sel[12]; // @[package.scala:81:59]
wire in_alloc_3_0 = _GEN & sel[9]; // @[package.scala:81:59]
wire in_alloc_3_1 = _GEN & sel[10]; // @[package.scala:81:59]
wire in_alloc_3_2 = _GEN & sel[11]; // @[package.scala:81:59]
wire in_alloc_2_0 = _GEN & sel[6]; // @[package.scala:81:59]
wire in_alloc_2_1 = _GEN & sel[7]; // @[package.scala:81:59]
wire in_alloc_2_2 = _GEN & sel[8]; // @[package.scala:81:59]
wire in_alloc_1_0 = _GEN & sel[3]; // @[package.scala:81:59]
wire in_alloc_1_1 = _GEN & sel[4]; // @[package.scala:81:59]
wire in_alloc_1_2 = _GEN & sel[5]; // @[package.scala:81:59]
wire in_alloc_0_0 = _GEN & sel[0]; // @[package.scala:81:59]
wire in_alloc_0_1 = _GEN & sel[1]; // @[package.scala:81:59]
wire in_alloc_0_2 = _GEN & sel[2]; // @[package.scala:81:59] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_129 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_129( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_54 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_86 = shr(io.in.a.bits.source, 4)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_152 = shr(io.in.a.bits.source, 4)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_199 = shr(io.in.a.bits.source, 4)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_240 = shr(io.in.a.bits.source, 4)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_283 = shr(io.in.a.bits.source, 4)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_321 = shr(io.in.a.bits.source, 4)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_359 = shr(io.in.a.bits.source, 4)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_108
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_109
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_54( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_30 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 4)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 4)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_64 = shr(io.in.a.bits.source, 4)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_77 = shr(io.in.a.bits.source, 4)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<4>(0h8))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<4>(0h9))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<4>(0ha))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<4>(0hb))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_164 = shr(io.in.a.bits.source, 4)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_170 = shr(io.in.a.bits.source, 4)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_177 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_178 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<18>(0h2f000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = and(_T_192, _T_197)
node _T_199 = or(UInt<1>(0h0), _T_198)
node _T_200 = and(_T_191, _T_199)
node _T_201 = asUInt(reset)
node _T_202 = eq(_T_201, UInt<1>(0h0))
when _T_202 :
node _T_203 = eq(_T_200, UInt<1>(0h0))
when _T_203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_200, UInt<1>(0h1), "") : assert_2
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<4>(0h8))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<4>(0h9))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<4>(0ha))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<4>(0hb))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h1))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_235 = shr(io.in.a.bits.source, 4)
node _T_236 = eq(_T_235, UInt<1>(0h0))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_242 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_243 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_244 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_204
connect _WIRE[1], _T_210
connect _WIRE[2], _T_216
connect _WIRE[3], _T_222
connect _WIRE[4], _T_228
connect _WIRE[5], _T_234
connect _WIRE[6], _T_240
connect _WIRE[7], _T_241
connect _WIRE[8], _T_242
connect _WIRE[9], _T_243
connect _WIRE[10], _T_244
node _T_245 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_246 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_249 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_253 = mux(_WIRE[7], _T_245, UInt<1>(0h0))
node _T_254 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_255 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_256 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_257 = or(_T_246, _T_247)
node _T_258 = or(_T_257, _T_248)
node _T_259 = or(_T_258, _T_249)
node _T_260 = or(_T_259, _T_250)
node _T_261 = or(_T_260, _T_251)
node _T_262 = or(_T_261, _T_252)
node _T_263 = or(_T_262, _T_253)
node _T_264 = or(_T_263, _T_254)
node _T_265 = or(_T_264, _T_255)
node _T_266 = or(_T_265, _T_256)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_266
node _T_267 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_268 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_269 = and(_T_267, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<18>(0h2f000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_WIRE_1, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_278, UInt<1>(0h1), "") : assert_3
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(source_ok, UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_285 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_286 = asUInt(reset)
node _T_287 = eq(_T_286, UInt<1>(0h0))
when _T_287 :
node _T_288 = eq(_T_285, UInt<1>(0h0))
when _T_288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_285, UInt<1>(0h1), "") : assert_5
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(is_aligned, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_292 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_292, UInt<1>(0h1), "") : assert_7
node _T_296 = not(io.in.a.bits.mask)
node _T_297 = eq(_T_296, UInt<1>(0h0))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_297, UInt<1>(0h1), "") : assert_8
node _T_301 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_301, UInt<1>(0h1), "") : assert_9
node _T_305 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_305 :
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_310 = shr(io.in.a.bits.source, 2)
node _T_311 = eq(_T_310, UInt<4>(0h8))
node _T_312 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_313 = and(_T_311, _T_312)
node _T_314 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_315 = and(_T_313, _T_314)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_316 = shr(io.in.a.bits.source, 2)
node _T_317 = eq(_T_316, UInt<4>(0h9))
node _T_318 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_319 = and(_T_317, _T_318)
node _T_320 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_321 = and(_T_319, _T_320)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_322 = shr(io.in.a.bits.source, 2)
node _T_323 = eq(_T_322, UInt<4>(0ha))
node _T_324 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_325 = and(_T_323, _T_324)
node _T_326 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_327 = and(_T_325, _T_326)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_328 = shr(io.in.a.bits.source, 2)
node _T_329 = eq(_T_328, UInt<4>(0hb))
node _T_330 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_331 = and(_T_329, _T_330)
node _T_332 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_333 = and(_T_331, _T_332)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_334 = shr(io.in.a.bits.source, 4)
node _T_335 = eq(_T_334, UInt<1>(0h1))
node _T_336 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_337 = and(_T_335, _T_336)
node _T_338 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_339 = and(_T_337, _T_338)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_340 = shr(io.in.a.bits.source, 4)
node _T_341 = eq(_T_340, UInt<1>(0h0))
node _T_342 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_343 = and(_T_341, _T_342)
node _T_344 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_348 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_349 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_350 = or(_T_309, _T_315)
node _T_351 = or(_T_350, _T_321)
node _T_352 = or(_T_351, _T_327)
node _T_353 = or(_T_352, _T_333)
node _T_354 = or(_T_353, _T_339)
node _T_355 = or(_T_354, _T_345)
node _T_356 = or(_T_355, _T_346)
node _T_357 = or(_T_356, _T_347)
node _T_358 = or(_T_357, _T_348)
node _T_359 = or(_T_358, _T_349)
node _T_360 = and(_T_308, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<18>(0h2f000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = and(_T_362, _T_367)
node _T_369 = or(UInt<1>(0h0), _T_368)
node _T_370 = and(_T_361, _T_369)
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_370, UInt<1>(0h1), "") : assert_10
node _T_374 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<4>(0h8))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<4>(0h9))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<4>(0ha))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<4>(0hb))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_399 = shr(io.in.a.bits.source, 4)
node _T_400 = eq(_T_399, UInt<1>(0h1))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_405 = shr(io.in.a.bits.source, 4)
node _T_406 = eq(_T_405, UInt<1>(0h0))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_412 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_413 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_414 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_374
connect _WIRE_2[1], _T_380
connect _WIRE_2[2], _T_386
connect _WIRE_2[3], _T_392
connect _WIRE_2[4], _T_398
connect _WIRE_2[5], _T_404
connect _WIRE_2[6], _T_410
connect _WIRE_2[7], _T_411
connect _WIRE_2[8], _T_412
connect _WIRE_2[9], _T_413
connect _WIRE_2[10], _T_414
node _T_415 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_416 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE_2[7], _T_415, UInt<1>(0h0))
node _T_424 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = or(_T_416, _T_417)
node _T_428 = or(_T_427, _T_418)
node _T_429 = or(_T_428, _T_419)
node _T_430 = or(_T_429, _T_420)
node _T_431 = or(_T_430, _T_421)
node _T_432 = or(_T_431, _T_422)
node _T_433 = or(_T_432, _T_423)
node _T_434 = or(_T_433, _T_424)
node _T_435 = or(_T_434, _T_425)
node _T_436 = or(_T_435, _T_426)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_436
node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_438 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_439 = and(_T_437, _T_438)
node _T_440 = or(UInt<1>(0h0), _T_439)
node _T_441 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_442 = cvt(_T_441)
node _T_443 = and(_T_442, asSInt(UInt<18>(0h2f000)))
node _T_444 = asSInt(_T_443)
node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0)))
node _T_446 = and(_T_440, _T_445)
node _T_447 = or(UInt<1>(0h0), _T_446)
node _T_448 = and(_WIRE_3, _T_447)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_448, UInt<1>(0h1), "") : assert_11
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(source_ok, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_455 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_T_455, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_455, UInt<1>(0h1), "") : assert_13
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(is_aligned, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_462 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_462, UInt<1>(0h1), "") : assert_15
node _T_466 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_466, UInt<1>(0h1), "") : assert_16
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_471, UInt<1>(0h1), "") : assert_17
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_475, UInt<1>(0h1), "") : assert_18
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<4>(0h8))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<4>(0h9))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<4>(0ha))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<4>(0hb))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_508 = shr(io.in.a.bits.source, 4)
node _T_509 = eq(_T_508, UInt<1>(0h1))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_514 = shr(io.in.a.bits.source, 4)
node _T_515 = eq(_T_514, UInt<1>(0h0))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_521 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_523 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_524 = or(_T_483, _T_489)
node _T_525 = or(_T_524, _T_495)
node _T_526 = or(_T_525, _T_501)
node _T_527 = or(_T_526, _T_507)
node _T_528 = or(_T_527, _T_513)
node _T_529 = or(_T_528, _T_519)
node _T_530 = or(_T_529, _T_520)
node _T_531 = or(_T_530, _T_521)
node _T_532 = or(_T_531, _T_522)
node _T_533 = or(_T_532, _T_523)
node _T_534 = and(_T_482, _T_533)
node _T_535 = or(UInt<1>(0h0), _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_535, UInt<1>(0h1), "") : assert_19
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<18>(0h2f000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = and(_T_542, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_549, UInt<1>(0h1), "") : assert_20
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(source_ok, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(is_aligned, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_559 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_559, UInt<1>(0h1), "") : assert_23
node _T_563 = eq(io.in.a.bits.mask, mask)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_563, UInt<1>(0h1), "") : assert_24
node _T_567 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_567, UInt<1>(0h1), "") : assert_25
node _T_571 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_571 :
node _T_572 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_573 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_574 = and(_T_572, _T_573)
node _T_575 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<4>(0h8))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<4>(0h9))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_588 = shr(io.in.a.bits.source, 2)
node _T_589 = eq(_T_588, UInt<4>(0ha))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<4>(0hb))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_600 = shr(io.in.a.bits.source, 4)
node _T_601 = eq(_T_600, UInt<1>(0h1))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_605 = and(_T_603, _T_604)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_606 = shr(io.in.a.bits.source, 4)
node _T_607 = eq(_T_606, UInt<1>(0h0))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_611 = and(_T_609, _T_610)
node _T_612 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_614 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_615 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_616 = or(_T_575, _T_581)
node _T_617 = or(_T_616, _T_587)
node _T_618 = or(_T_617, _T_593)
node _T_619 = or(_T_618, _T_599)
node _T_620 = or(_T_619, _T_605)
node _T_621 = or(_T_620, _T_611)
node _T_622 = or(_T_621, _T_612)
node _T_623 = or(_T_622, _T_613)
node _T_624 = or(_T_623, _T_614)
node _T_625 = or(_T_624, _T_615)
node _T_626 = and(_T_574, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_629 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_633 = cvt(_T_632)
node _T_634 = and(_T_633, asSInt(UInt<18>(0h2f000)))
node _T_635 = asSInt(_T_634)
node _T_636 = eq(_T_635, asSInt(UInt<1>(0h0)))
node _T_637 = and(_T_631, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = and(_T_627, _T_638)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_639, UInt<1>(0h1), "") : assert_26
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(source_ok, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(is_aligned, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_649 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_649, UInt<1>(0h1), "") : assert_29
node _T_653 = eq(io.in.a.bits.mask, mask)
node _T_654 = asUInt(reset)
node _T_655 = eq(_T_654, UInt<1>(0h0))
when _T_655 :
node _T_656 = eq(_T_653, UInt<1>(0h0))
when _T_656 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_653, UInt<1>(0h1), "") : assert_30
node _T_657 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_657 :
node _T_658 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_659 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_660 = and(_T_658, _T_659)
node _T_661 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_662 = shr(io.in.a.bits.source, 2)
node _T_663 = eq(_T_662, UInt<4>(0h8))
node _T_664 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_665 = and(_T_663, _T_664)
node _T_666 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_667 = and(_T_665, _T_666)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_668 = shr(io.in.a.bits.source, 2)
node _T_669 = eq(_T_668, UInt<4>(0h9))
node _T_670 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_671 = and(_T_669, _T_670)
node _T_672 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_673 = and(_T_671, _T_672)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_674 = shr(io.in.a.bits.source, 2)
node _T_675 = eq(_T_674, UInt<4>(0ha))
node _T_676 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_677 = and(_T_675, _T_676)
node _T_678 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_679 = and(_T_677, _T_678)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_680 = shr(io.in.a.bits.source, 2)
node _T_681 = eq(_T_680, UInt<4>(0hb))
node _T_682 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_683 = and(_T_681, _T_682)
node _T_684 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_685 = and(_T_683, _T_684)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_686 = shr(io.in.a.bits.source, 4)
node _T_687 = eq(_T_686, UInt<1>(0h1))
node _T_688 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_689 = and(_T_687, _T_688)
node _T_690 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_691 = and(_T_689, _T_690)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_692 = shr(io.in.a.bits.source, 4)
node _T_693 = eq(_T_692, UInt<1>(0h0))
node _T_694 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_695 = and(_T_693, _T_694)
node _T_696 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_697 = and(_T_695, _T_696)
node _T_698 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_699 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_700 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_701 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_702 = or(_T_661, _T_667)
node _T_703 = or(_T_702, _T_673)
node _T_704 = or(_T_703, _T_679)
node _T_705 = or(_T_704, _T_685)
node _T_706 = or(_T_705, _T_691)
node _T_707 = or(_T_706, _T_697)
node _T_708 = or(_T_707, _T_698)
node _T_709 = or(_T_708, _T_699)
node _T_710 = or(_T_709, _T_700)
node _T_711 = or(_T_710, _T_701)
node _T_712 = and(_T_660, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_715 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_716 = and(_T_714, _T_715)
node _T_717 = or(UInt<1>(0h0), _T_716)
node _T_718 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<18>(0h2f000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = and(_T_717, _T_722)
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = and(_T_713, _T_724)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_725, UInt<1>(0h1), "") : assert_31
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(source_ok, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(is_aligned, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_735 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_735, UInt<1>(0h1), "") : assert_34
node _T_739 = not(mask)
node _T_740 = and(io.in.a.bits.mask, _T_739)
node _T_741 = eq(_T_740, UInt<1>(0h0))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_741, UInt<1>(0h1), "") : assert_35
node _T_745 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_750 = shr(io.in.a.bits.source, 2)
node _T_751 = eq(_T_750, UInt<4>(0h8))
node _T_752 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_753 = and(_T_751, _T_752)
node _T_754 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_755 = and(_T_753, _T_754)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_756 = shr(io.in.a.bits.source, 2)
node _T_757 = eq(_T_756, UInt<4>(0h9))
node _T_758 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_759 = and(_T_757, _T_758)
node _T_760 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_761 = and(_T_759, _T_760)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<4>(0ha))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<4>(0hb))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_774 = shr(io.in.a.bits.source, 4)
node _T_775 = eq(_T_774, UInt<1>(0h1))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_780 = shr(io.in.a.bits.source, 4)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_785 = and(_T_783, _T_784)
node _T_786 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_787 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_788 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_789 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_790 = or(_T_749, _T_755)
node _T_791 = or(_T_790, _T_761)
node _T_792 = or(_T_791, _T_767)
node _T_793 = or(_T_792, _T_773)
node _T_794 = or(_T_793, _T_779)
node _T_795 = or(_T_794, _T_785)
node _T_796 = or(_T_795, _T_786)
node _T_797 = or(_T_796, _T_787)
node _T_798 = or(_T_797, _T_788)
node _T_799 = or(_T_798, _T_789)
node _T_800 = and(_T_748, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<18>(0h2f000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = or(UInt<1>(0h0), _T_808)
node _T_810 = and(_T_801, _T_809)
node _T_811 = asUInt(reset)
node _T_812 = eq(_T_811, UInt<1>(0h0))
when _T_812 :
node _T_813 = eq(_T_810, UInt<1>(0h0))
when _T_813 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_810, UInt<1>(0h1), "") : assert_36
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(source_ok, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(is_aligned, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_820 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_820, UInt<1>(0h1), "") : assert_39
node _T_824 = eq(io.in.a.bits.mask, mask)
node _T_825 = asUInt(reset)
node _T_826 = eq(_T_825, UInt<1>(0h0))
when _T_826 :
node _T_827 = eq(_T_824, UInt<1>(0h0))
when _T_827 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_824, UInt<1>(0h1), "") : assert_40
node _T_828 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_828 :
node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_831 = and(_T_829, _T_830)
node _T_832 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<4>(0h8))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<4>(0h9))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<4>(0ha))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<4>(0hb))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_857 = shr(io.in.a.bits.source, 4)
node _T_858 = eq(_T_857, UInt<1>(0h1))
node _T_859 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_860 = and(_T_858, _T_859)
node _T_861 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_862 = and(_T_860, _T_861)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_863 = shr(io.in.a.bits.source, 4)
node _T_864 = eq(_T_863, UInt<1>(0h0))
node _T_865 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_866 = and(_T_864, _T_865)
node _T_867 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_868 = and(_T_866, _T_867)
node _T_869 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_871 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_872 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_873 = or(_T_832, _T_838)
node _T_874 = or(_T_873, _T_844)
node _T_875 = or(_T_874, _T_850)
node _T_876 = or(_T_875, _T_856)
node _T_877 = or(_T_876, _T_862)
node _T_878 = or(_T_877, _T_868)
node _T_879 = or(_T_878, _T_869)
node _T_880 = or(_T_879, _T_870)
node _T_881 = or(_T_880, _T_871)
node _T_882 = or(_T_881, _T_872)
node _T_883 = and(_T_831, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_886 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<18>(0h2f000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = and(_T_885, _T_890)
node _T_892 = or(UInt<1>(0h0), _T_891)
node _T_893 = and(_T_884, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_893, UInt<1>(0h1), "") : assert_41
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_903 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_903, UInt<1>(0h1), "") : assert_44
node _T_907 = eq(io.in.a.bits.mask, mask)
node _T_908 = asUInt(reset)
node _T_909 = eq(_T_908, UInt<1>(0h0))
when _T_909 :
node _T_910 = eq(_T_907, UInt<1>(0h0))
when _T_910 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_907, UInt<1>(0h1), "") : assert_45
node _T_911 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_911 :
node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_913 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_916 = shr(io.in.a.bits.source, 2)
node _T_917 = eq(_T_916, UInt<4>(0h8))
node _T_918 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_919 = and(_T_917, _T_918)
node _T_920 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_921 = and(_T_919, _T_920)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_922 = shr(io.in.a.bits.source, 2)
node _T_923 = eq(_T_922, UInt<4>(0h9))
node _T_924 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_925 = and(_T_923, _T_924)
node _T_926 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_928 = shr(io.in.a.bits.source, 2)
node _T_929 = eq(_T_928, UInt<4>(0ha))
node _T_930 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_931 = and(_T_929, _T_930)
node _T_932 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_933 = and(_T_931, _T_932)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_934 = shr(io.in.a.bits.source, 2)
node _T_935 = eq(_T_934, UInt<4>(0hb))
node _T_936 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_937 = and(_T_935, _T_936)
node _T_938 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_939 = and(_T_937, _T_938)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_940 = shr(io.in.a.bits.source, 4)
node _T_941 = eq(_T_940, UInt<1>(0h1))
node _T_942 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_943 = and(_T_941, _T_942)
node _T_944 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_945 = and(_T_943, _T_944)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_946 = shr(io.in.a.bits.source, 4)
node _T_947 = eq(_T_946, UInt<1>(0h0))
node _T_948 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_949 = and(_T_947, _T_948)
node _T_950 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_953 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_954 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_955 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_956 = or(_T_915, _T_921)
node _T_957 = or(_T_956, _T_927)
node _T_958 = or(_T_957, _T_933)
node _T_959 = or(_T_958, _T_939)
node _T_960 = or(_T_959, _T_945)
node _T_961 = or(_T_960, _T_951)
node _T_962 = or(_T_961, _T_952)
node _T_963 = or(_T_962, _T_953)
node _T_964 = or(_T_963, _T_954)
node _T_965 = or(_T_964, _T_955)
node _T_966 = and(_T_914, _T_965)
node _T_967 = or(UInt<1>(0h0), _T_966)
node _T_968 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_969 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<18>(0h2f000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = and(_T_968, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = and(_T_967, _T_975)
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(_T_976, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_976, UInt<1>(0h1), "") : assert_46
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(is_aligned, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_986 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_986, UInt<1>(0h1), "") : assert_49
node _T_990 = eq(io.in.a.bits.mask, mask)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_990, UInt<1>(0h1), "") : assert_50
node _T_994 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_994, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_998 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_998, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<4>(0h8))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<4>(0h9))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<4>(0ha))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<4>(0hb))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 4)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 4)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1002 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1002 :
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(source_ok_1, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_54
node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_55
node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_56
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_57
node _T_1022 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1022 :
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(source_ok_1, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(sink_ok, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1029 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1030 = asUInt(reset)
node _T_1031 = eq(_T_1030, UInt<1>(0h0))
when _T_1031 :
node _T_1032 = eq(_T_1029, UInt<1>(0h0))
when _T_1032 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1029, UInt<1>(0h1), "") : assert_60
node _T_1033 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1034 = asUInt(reset)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
when _T_1035 :
node _T_1036 = eq(_T_1033, UInt<1>(0h0))
when _T_1036 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1033, UInt<1>(0h1), "") : assert_61
node _T_1037 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1038 = asUInt(reset)
node _T_1039 = eq(_T_1038, UInt<1>(0h0))
when _T_1039 :
node _T_1040 = eq(_T_1037, UInt<1>(0h0))
when _T_1040 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1037, UInt<1>(0h1), "") : assert_62
node _T_1041 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_63
node _T_1045 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1046 = or(UInt<1>(0h0), _T_1045)
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(_T_1046, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1046, UInt<1>(0h1), "") : assert_64
node _T_1050 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1050 :
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok_1, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(sink_ok, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1057 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_67
node _T_1061 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_68
node _T_1065 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_69
node _T_1069 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1070 = or(_T_1069, io.in.d.bits.corrupt)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_70
node _T_1074 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = asUInt(reset)
node _T_1077 = eq(_T_1076, UInt<1>(0h0))
when _T_1077 :
node _T_1078 = eq(_T_1075, UInt<1>(0h0))
when _T_1078 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1075, UInt<1>(0h1), "") : assert_71
node _T_1079 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = asUInt(reset)
node _T_1081 = eq(_T_1080, UInt<1>(0h0))
when _T_1081 :
node _T_1082 = eq(source_ok_1, UInt<1>(0h0))
when _T_1082 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1083 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1084 = asUInt(reset)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(_T_1083, UInt<1>(0h0))
when _T_1086 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1083, UInt<1>(0h1), "") : assert_73
node _T_1087 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(_T_1087, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1087, UInt<1>(0h1), "") : assert_74
node _T_1091 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1092 = or(UInt<1>(0h0), _T_1091)
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_75
node _T_1096 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1096 :
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(source_ok_1, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1100 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_77
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(_T_1104, io.in.d.bits.corrupt)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_78
node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1110 = or(UInt<1>(0h0), _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_79
node _T_1114 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1114 :
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(source_ok_1, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1118 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_81
node _T_1122 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_82
node _T_1126 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1127 = or(UInt<1>(0h0), _T_1126)
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1131 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1135 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(_T_1135, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1135, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1139 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1143 = eq(a_first, UInt<1>(0h0))
node _T_1144 = and(io.in.a.valid, _T_1143)
when _T_1144 :
node _T_1145 = eq(io.in.a.bits.opcode, opcode)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_87
node _T_1149 = eq(io.in.a.bits.param, param)
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_88
node _T_1153 = eq(io.in.a.bits.size, size)
node _T_1154 = asUInt(reset)
node _T_1155 = eq(_T_1154, UInt<1>(0h0))
when _T_1155 :
node _T_1156 = eq(_T_1153, UInt<1>(0h0))
when _T_1156 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1153, UInt<1>(0h1), "") : assert_89
node _T_1157 = eq(io.in.a.bits.source, source)
node _T_1158 = asUInt(reset)
node _T_1159 = eq(_T_1158, UInt<1>(0h0))
when _T_1159 :
node _T_1160 = eq(_T_1157, UInt<1>(0h0))
when _T_1160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1157, UInt<1>(0h1), "") : assert_90
node _T_1161 = eq(io.in.a.bits.address, address)
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(_T_1161, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1161, UInt<1>(0h1), "") : assert_91
node _T_1165 = and(io.in.a.ready, io.in.a.valid)
node _T_1166 = and(_T_1165, a_first)
when _T_1166 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1167 = eq(d_first, UInt<1>(0h0))
node _T_1168 = and(io.in.d.valid, _T_1167)
when _T_1168 :
node _T_1169 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_92
node _T_1173 = eq(io.in.d.bits.param, param_1)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_93
node _T_1177 = eq(io.in.d.bits.size, size_1)
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_94
node _T_1181 = eq(io.in.d.bits.source, source_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_95
node _T_1185 = eq(io.in.d.bits.sink, sink)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_96
node _T_1189 = eq(io.in.d.bits.denied, denied)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_97
node _T_1193 = and(io.in.d.ready, io.in.d.valid)
node _T_1194 = and(_T_1193, d_first)
when _T_1194 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1195 = and(io.in.a.valid, a_first_1)
node _T_1196 = and(_T_1195, UInt<1>(0h1))
when _T_1196 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1197 = and(io.in.a.ready, io.in.a.valid)
node _T_1198 = and(_T_1197, a_first_1)
node _T_1199 = and(_T_1198, UInt<1>(0h1))
when _T_1199 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1200 = dshr(inflight, io.in.a.bits.source)
node _T_1201 = bits(_T_1200, 0, 0)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1206 = and(io.in.d.valid, d_first_1)
node _T_1207 = and(_T_1206, UInt<1>(0h1))
node _T_1208 = eq(d_release_ack, UInt<1>(0h0))
node _T_1209 = and(_T_1207, _T_1208)
when _T_1209 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1210 = and(io.in.d.ready, io.in.d.valid)
node _T_1211 = and(_T_1210, d_first_1)
node _T_1212 = and(_T_1211, UInt<1>(0h1))
node _T_1213 = eq(d_release_ack, UInt<1>(0h0))
node _T_1214 = and(_T_1212, _T_1213)
when _T_1214 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1215 = and(io.in.d.valid, d_first_1)
node _T_1216 = and(_T_1215, UInt<1>(0h1))
node _T_1217 = eq(d_release_ack, UInt<1>(0h0))
node _T_1218 = and(_T_1216, _T_1217)
when _T_1218 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1219 = dshr(inflight, io.in.d.bits.source)
node _T_1220 = bits(_T_1219, 0, 0)
node _T_1221 = or(_T_1220, same_cycle_resp)
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1225 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1226 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1227 = or(_T_1225, _T_1226)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_100
node _T_1231 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_101
else :
node _T_1235 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1236 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1237 = or(_T_1235, _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_102
node _T_1241 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_103
node _T_1245 = and(io.in.d.valid, d_first_1)
node _T_1246 = and(_T_1245, a_first_1)
node _T_1247 = and(_T_1246, io.in.a.valid)
node _T_1248 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1249 = and(_T_1247, _T_1248)
node _T_1250 = eq(d_release_ack, UInt<1>(0h0))
node _T_1251 = and(_T_1249, _T_1250)
when _T_1251 :
node _T_1252 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1253 = or(_T_1252, io.in.a.ready)
node _T_1254 = asUInt(reset)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
when _T_1255 :
node _T_1256 = eq(_T_1253, UInt<1>(0h0))
when _T_1256 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1253, UInt<1>(0h1), "") : assert_104
node _T_1257 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1258 = orr(a_set_wo_ready)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
node _T_1260 = or(_T_1257, _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_60
node _T_1264 = orr(inflight)
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
node _T_1266 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1267 = or(_T_1265, _T_1266)
node _T_1268 = lt(watchdog, plusarg_reader.out)
node _T_1269 = or(_T_1267, _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1273 = and(io.in.a.ready, io.in.a.valid)
node _T_1274 = and(io.in.d.ready, io.in.d.valid)
node _T_1275 = or(_T_1273, _T_1274)
when _T_1275 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1276 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1277 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1278 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1279 = and(_T_1277, _T_1278)
node _T_1280 = and(_T_1276, _T_1279)
when _T_1280 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1281 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1282 = and(_T_1281, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1283 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1284 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1285 = and(_T_1283, _T_1284)
node _T_1286 = and(_T_1282, _T_1285)
when _T_1286 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1287 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1288 = bits(_T_1287, 0, 0)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1293 = and(io.in.d.valid, d_first_2)
node _T_1294 = and(_T_1293, UInt<1>(0h1))
node _T_1295 = and(_T_1294, d_release_ack_1)
when _T_1295 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1296 = and(io.in.d.ready, io.in.d.valid)
node _T_1297 = and(_T_1296, d_first_2)
node _T_1298 = and(_T_1297, UInt<1>(0h1))
node _T_1299 = and(_T_1298, d_release_ack_1)
when _T_1299 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1300 = and(io.in.d.valid, d_first_2)
node _T_1301 = and(_T_1300, UInt<1>(0h1))
node _T_1302 = and(_T_1301, d_release_ack_1)
when _T_1302 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1303 = dshr(inflight_1, io.in.d.bits.source)
node _T_1304 = bits(_T_1303, 0, 0)
node _T_1305 = or(_T_1304, same_cycle_resp_1)
node _T_1306 = asUInt(reset)
node _T_1307 = eq(_T_1306, UInt<1>(0h0))
when _T_1307 :
node _T_1308 = eq(_T_1305, UInt<1>(0h0))
when _T_1308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1305, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1309 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_109
else :
node _T_1313 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1314 = asUInt(reset)
node _T_1315 = eq(_T_1314, UInt<1>(0h0))
when _T_1315 :
node _T_1316 = eq(_T_1313, UInt<1>(0h0))
when _T_1316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1313, UInt<1>(0h1), "") : assert_110
node _T_1317 = and(io.in.d.valid, d_first_2)
node _T_1318 = and(_T_1317, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1319 = and(_T_1318, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1320 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = and(_T_1321, d_release_ack_1)
node _T_1323 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1324 = and(_T_1322, _T_1323)
when _T_1324 :
node _T_1325 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1326 = or(_T_1325, _WIRE_27.ready)
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_111
node _T_1330 = orr(c_set_wo_ready)
when _T_1330 :
node _T_1331 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_61
node _T_1335 = orr(inflight_1)
node _T_1336 = eq(_T_1335, UInt<1>(0h0))
node _T_1337 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1338 = or(_T_1336, _T_1337)
node _T_1339 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1340 = or(_T_1338, _T_1339)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:47:5)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1344 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1345 = and(io.in.d.ready, io.in.d.valid)
node _T_1346 = or(_T_1344, _T_1345)
when _T_1346 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_30( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1273 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1273; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1273; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1346 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1346; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1346; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1199 = _T_1273 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1214 = _T_1346 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1317 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1317 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1299 = _T_1346 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1299 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1299 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1299 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_52 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
when _T_8 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T_4, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_3)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_6
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T_4, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_3)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_6
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_9 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_10 = or(_T_9, prs1_rebusys_2)
node _T_11 = or(_T_10, prs1_rebusys_3)
node _T_12 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_13 = neq(_T_12, UInt<1>(0h0))
node _T_14 = or(_T_11, _T_13)
node _T_15 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_16 = and(_T_14, _T_15)
when _T_16 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_17 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_18 = or(_T_17, prs2_wakeups_2)
node _T_19 = or(_T_18, prs2_wakeups_3)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T_4, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_3)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_6
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T_4, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_3)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_6
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_20 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_21 = or(_T_20, prs2_rebusys_2)
node _T_22 = or(_T_21, prs2_rebusys_3)
node _T_23 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_24 = neq(_T_23, UInt<1>(0h0))
node _T_25 = or(_T_22, _T_24)
node _T_26 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_28 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_29 = or(_T_28, prs3_wakeups_2)
node _T_30 = or(_T_29, prs3_wakeups_3)
when _T_30 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T_4, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_3)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_6
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_31 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_32 = and(io.pred_wakeup_port.valid, _T_31)
when _T_32 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_33 = eq(io.squash_grant, UInt<1>(0h0))
node _T_34 = and(io.grant, _T_33)
when _T_34 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_35 = and(slot_valid, slot_uop.iw_issued)
when _T_35 :
connect next_valid, rebusied | module IssueSlot_52( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [1:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_38 :
output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}}
node rawA_exp = bits(io.a, 31, 23)
node _rawA_isZero_T = bits(rawA_exp, 8, 6)
node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0))
node _rawA_isSpecial_T = bits(rawA_exp, 8, 7)
node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3))
wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6)
node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T)
connect rawA.isNaN, _rawA_out_isNaN_T_1
node _rawA_out_isInf_T = bits(rawA_exp, 6, 6)
node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0))
node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1)
connect rawA.isInf, _rawA_out_isInf_T_2
connect rawA.isZero, rawA_isZero
node _rawA_out_sign_T = bits(io.a, 32, 32)
connect rawA.sign, _rawA_out_sign_T
node _rawA_out_sExp_T = cvt(rawA_exp)
connect rawA.sExp, _rawA_out_sExp_T
node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0))
node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T)
node _rawA_out_sig_T_2 = bits(io.a, 22, 0)
node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2)
connect rawA.sig, _rawA_out_sig_T_3
node rawB_exp = bits(io.b, 31, 23)
node _rawB_isZero_T = bits(rawB_exp, 8, 6)
node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0))
node _rawB_isSpecial_T = bits(rawB_exp, 8, 7)
node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3))
wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6)
node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T)
connect rawB.isNaN, _rawB_out_isNaN_T_1
node _rawB_out_isInf_T = bits(rawB_exp, 6, 6)
node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0))
node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1)
connect rawB.isInf, _rawB_out_isInf_T_2
connect rawB.isZero, rawB_isZero
node _rawB_out_sign_T = bits(io.b, 32, 32)
connect rawB.sign, _rawB_out_sign_T
node _rawB_out_sExp_T = cvt(rawB_exp)
connect rawB.sExp, _rawB_out_sExp_T
node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0))
node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T)
node _rawB_out_sig_T_2 = bits(io.b, 22, 0)
node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2)
connect rawB.sig, _rawB_out_sig_T_3
node rawC_exp = bits(io.c, 31, 23)
node _rawC_isZero_T = bits(rawC_exp, 8, 6)
node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0))
node _rawC_isSpecial_T = bits(rawC_exp, 8, 7)
node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3))
wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6)
node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T)
connect rawC.isNaN, _rawC_out_isNaN_T_1
node _rawC_out_isInf_T = bits(rawC_exp, 6, 6)
node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0))
node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1)
connect rawC.isInf, _rawC_out_isInf_T_2
connect rawC.isZero, rawC_isZero
node _rawC_out_sign_T = bits(io.c, 32, 32)
connect rawC.sign, _rawC_out_sign_T
node _rawC_out_sExp_T = cvt(rawC_exp)
connect rawC.sExp, _rawC_out_sExp_T
node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0))
node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T)
node _rawC_out_sig_T_2 = bits(io.c, 22, 0)
node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2)
connect rawC.sig, _rawC_out_sig_T_3
node _signProd_T = xor(rawA.sign, rawB.sign)
node _signProd_T_1 = bits(io.op, 1, 1)
node signProd = xor(_signProd_T, _signProd_T_1)
node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp)
node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b)))
node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1)
node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2)
node _doSubMags_T = xor(signProd, rawC.sign)
node _doSubMags_T_1 = bits(io.op, 0, 0)
node doSubMags = xor(_doSubMags_T, _doSubMags_T_1)
node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp)
node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1)
node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1)
node posNatCAlignDist = bits(sNatCAlignDist, 9, 0)
node _isMinCAlign_T = or(rawA.isZero, rawB.isZero)
node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0)))
node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1)
node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0))
node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18))
node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1)
node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2)
node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a))
node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0)
node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a))
node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2)
node _mainAlignedSigC_T = not(rawC.sig)
node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig)
node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0))
node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2)
node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3)
node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist)
node _reduced4CExtra_T = shl(rawC.sig, 2)
wire reduced4CExtra_reducedVec : UInt<1>[7]
node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0)
node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T)
connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1
node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4)
node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T)
connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1
node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8)
node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T)
connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1
node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12)
node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T)
connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1
node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16)
node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T)
connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1
node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20)
node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T)
connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1
node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24)
node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T)
connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1
node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1])
node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0])
node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3])
node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5])
node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo)
node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo)
node _reduced4CExtra_T_2 = shr(CAlignDist, 2)
node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2)
node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14)
node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0)
node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0)
node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0)
node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1)
node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7)
node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2)
node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0)
node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1)
node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11)
node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12)
node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4)
node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0)
node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1)
node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16)
node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17)
node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18)
node reduced4CExtra = orr(_reduced4CExtra_T_19)
node _alignedSigC_T = shr(mainAlignedSigC, 3)
node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_2 = andr(_alignedSigC_T_1)
node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0))
node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3)
node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0)
node _alignedSigC_T_6 = orr(_alignedSigC_T_5)
node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra)
node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7)
node alignedSigC_hi = asUInt(_alignedSigC_T)
node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8)
connect io.mulAddA, rawA.sig
connect io.mulAddB, rawB.sig
node _io_mulAddC_T = bits(alignedSigC, 48, 1)
connect io.mulAddC, _io_mulAddC_T
node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1)
node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4)
node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5)
node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22)
node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0))
node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8)
node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9)
connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10
node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN)
connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T
connect io.toPostMul.isInfA, rawA.isInf
connect io.toPostMul.isZeroA, rawA.isZero
connect io.toPostMul.isInfB, rawB.isInf
connect io.toPostMul.isZeroB, rawB.isZero
connect io.toPostMul.signProd, signProd
connect io.toPostMul.isNaNC, rawC.isNaN
connect io.toPostMul.isInfC, rawC.isInf
connect io.toPostMul.isZeroC, rawC.isZero
node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18)))
node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1)
node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1)
node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2)
connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3
connect io.toPostMul.doSubMags, doSubMags
connect io.toPostMul.CIsDominant, CIsDominant
node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0)
connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T
node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49)
connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T
node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0)
connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T | module MulAddRecFNToRaw_preMul_e8_s24_38( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:57:36, :61:35]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire _isMinCAlign_T = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire _signProd_T = rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + 11'h100; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_72 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[5], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<3>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_2 = eq(io.wakeup_ports[2].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_3 = eq(io.wakeup_ports[3].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_4 = eq(io.wakeup_ports[4].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs1_wakeups_2 = and(io.wakeup_ports[2].valid, prs1_matches_2)
node prs1_wakeups_3 = and(io.wakeup_ports[3].valid, prs1_matches_3)
node prs1_wakeups_4 = and(io.wakeup_ports[4].valid, prs1_matches_4)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs2_wakeups_2 = and(io.wakeup_ports[2].valid, prs2_matches_2)
node prs2_wakeups_3 = and(io.wakeup_ports[3].valid, prs2_matches_3)
node prs2_wakeups_4 = and(io.wakeup_ports[4].valid, prs2_matches_4)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs3_wakeups_2 = and(io.wakeup_ports[2].valid, prs3_matches_2)
node prs3_wakeups_3 = and(io.wakeup_ports[3].valid, prs3_matches_3)
node prs3_wakeups_4 = and(io.wakeup_ports[4].valid, prs3_matches_4)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs1_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs1_matches_2)
node prs1_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs1_matches_3)
node prs1_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs1_matches_4)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node prs2_rebusys_2 = and(io.wakeup_ports[2].bits.rebusy, prs2_matches_2)
node prs2_rebusys_3 = and(io.wakeup_ports[3].bits.rebusy, prs2_matches_3)
node prs2_rebusys_4 = and(io.wakeup_ports[4].bits.rebusy, prs2_matches_4)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
node _T_7 = or(_T_6, prs1_wakeups_2)
node _T_8 = or(_T_7, prs1_wakeups_3)
node _T_9 = or(_T_8, prs1_wakeups_4)
when _T_9 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_5 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
node _next_uop_iw_p1_speculative_child_T_6 = or(_next_uop_iw_p1_speculative_child_T_5, _next_uop_iw_p1_speculative_child_T_2)
node _next_uop_iw_p1_speculative_child_T_7 = or(_next_uop_iw_p1_speculative_child_T_6, _next_uop_iw_p1_speculative_child_T_3)
node _next_uop_iw_p1_speculative_child_T_8 = or(_next_uop_iw_p1_speculative_child_T_7, _next_uop_iw_p1_speculative_child_T_4)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_8
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = mux(prs1_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_3 = mux(prs1_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_4 = mux(prs1_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_5 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
node _next_uop_iw_p1_bypass_hint_T_6 = or(_next_uop_iw_p1_bypass_hint_T_5, _next_uop_iw_p1_bypass_hint_T_2)
node _next_uop_iw_p1_bypass_hint_T_7 = or(_next_uop_iw_p1_bypass_hint_T_6, _next_uop_iw_p1_bypass_hint_T_3)
node _next_uop_iw_p1_bypass_hint_T_8 = or(_next_uop_iw_p1_bypass_hint_T_7, _next_uop_iw_p1_bypass_hint_T_4)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_8
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_10 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_11 = or(_T_10, prs1_rebusys_2)
node _T_12 = or(_T_11, prs1_rebusys_3)
node _T_13 = or(_T_12, prs1_rebusys_4)
node _T_14 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_15 = neq(_T_14, UInt<1>(0h0))
node _T_16 = or(_T_13, _T_15)
node _T_17 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_18 = and(_T_16, _T_17)
when _T_18 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_19 = or(prs2_wakeups_0, prs2_wakeups_1)
node _T_20 = or(_T_19, prs2_wakeups_2)
node _T_21 = or(_T_20, prs2_wakeups_3)
node _T_22 = or(_T_21, prs2_wakeups_4)
when _T_22 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_5 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
node _next_uop_iw_p2_speculative_child_T_6 = or(_next_uop_iw_p2_speculative_child_T_5, _next_uop_iw_p2_speculative_child_T_2)
node _next_uop_iw_p2_speculative_child_T_7 = or(_next_uop_iw_p2_speculative_child_T_6, _next_uop_iw_p2_speculative_child_T_3)
node _next_uop_iw_p2_speculative_child_T_8 = or(_next_uop_iw_p2_speculative_child_T_7, _next_uop_iw_p2_speculative_child_T_4)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<3>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_8
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = mux(prs2_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_3 = mux(prs2_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_4 = mux(prs2_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_5 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
node _next_uop_iw_p2_bypass_hint_T_6 = or(_next_uop_iw_p2_bypass_hint_T_5, _next_uop_iw_p2_bypass_hint_T_2)
node _next_uop_iw_p2_bypass_hint_T_7 = or(_next_uop_iw_p2_bypass_hint_T_6, _next_uop_iw_p2_bypass_hint_T_3)
node _next_uop_iw_p2_bypass_hint_T_8 = or(_next_uop_iw_p2_bypass_hint_T_7, _next_uop_iw_p2_bypass_hint_T_4)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_8
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_23 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_24 = or(_T_23, prs2_rebusys_2)
node _T_25 = or(_T_24, prs2_rebusys_3)
node _T_26 = or(_T_25, prs2_rebusys_4)
node _T_27 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_28 = neq(_T_27, UInt<1>(0h0))
node _T_29 = or(_T_26, _T_28)
node _T_30 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_31 = and(_T_29, _T_30)
when _T_31 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_32 = or(prs3_wakeups_0, prs3_wakeups_1)
node _T_33 = or(_T_32, prs3_wakeups_2)
node _T_34 = or(_T_33, prs3_wakeups_3)
node _T_35 = or(_T_34, prs3_wakeups_4)
when _T_35 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = mux(prs3_wakeups_2, io.wakeup_ports[2].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_3 = mux(prs3_wakeups_3, io.wakeup_ports[3].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_4 = mux(prs3_wakeups_4, io.wakeup_ports[4].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_5 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
node _next_uop_iw_p3_bypass_hint_T_6 = or(_next_uop_iw_p3_bypass_hint_T_5, _next_uop_iw_p3_bypass_hint_T_2)
node _next_uop_iw_p3_bypass_hint_T_7 = or(_next_uop_iw_p3_bypass_hint_T_6, _next_uop_iw_p3_bypass_hint_T_3)
node _next_uop_iw_p3_bypass_hint_T_8 = or(_next_uop_iw_p3_bypass_hint_T_7, _next_uop_iw_p3_bypass_hint_T_4)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_8
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_36 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_37 = and(io.pred_wakeup_port.valid, _T_36)
when _T_37 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h0))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_38 = eq(io.squash_grant, UInt<1>(0h0))
node _T_39 = and(io.grant, _T_38)
when _T_39 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_40 = and(slot_valid, slot_uop.iw_issued)
when _T_40 :
connect next_valid, rebusied | module IssueSlot_72( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_clear = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_11 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<7>(0h7f))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 3)
node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 6, 0)
node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 13, 7)
node idx_history_hist_chunks_2 = bits(io.f1_req_ghist, 20, 14)
node idx_history_hist_chunks_3 = bits(io.f1_req_ghist, 27, 21)
node idx_history_hist_chunks_4 = bits(io.f1_req_ghist, 34, 28)
node idx_history_hist_chunks_5 = bits(io.f1_req_ghist, 41, 35)
node idx_history_hist_chunks_6 = bits(io.f1_req_ghist, 48, 42)
node idx_history_hist_chunks_7 = bits(io.f1_req_ghist, 55, 49)
node idx_history_hist_chunks_8 = bits(io.f1_req_ghist, 62, 56)
node idx_history_hist_chunks_9 = bits(io.f1_req_ghist, 63, 63)
node _idx_history_T = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1)
node _idx_history_T_1 = xor(_idx_history_T, idx_history_hist_chunks_2)
node _idx_history_T_2 = xor(_idx_history_T_1, idx_history_hist_chunks_3)
node _idx_history_T_3 = xor(_idx_history_T_2, idx_history_hist_chunks_4)
node _idx_history_T_4 = xor(_idx_history_T_3, idx_history_hist_chunks_5)
node _idx_history_T_5 = xor(_idx_history_T_4, idx_history_hist_chunks_6)
node _idx_history_T_6 = xor(_idx_history_T_5, idx_history_hist_chunks_7)
node _idx_history_T_7 = xor(_idx_history_T_6, idx_history_hist_chunks_8)
node idx_history = xor(_idx_history_T_7, idx_history_hist_chunks_9)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 6, 0)
node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 8, 0)
node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 17, 9)
node tag_history_hist_chunks_2 = bits(io.f1_req_ghist, 26, 18)
node tag_history_hist_chunks_3 = bits(io.f1_req_ghist, 35, 27)
node tag_history_hist_chunks_4 = bits(io.f1_req_ghist, 44, 36)
node tag_history_hist_chunks_5 = bits(io.f1_req_ghist, 53, 45)
node tag_history_hist_chunks_6 = bits(io.f1_req_ghist, 62, 54)
node tag_history_hist_chunks_7 = bits(io.f1_req_ghist, 63, 63)
node _tag_history_T = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1)
node _tag_history_T_1 = xor(_tag_history_T, tag_history_hist_chunks_2)
node _tag_history_T_2 = xor(_tag_history_T_1, tag_history_hist_chunks_3)
node _tag_history_T_3 = xor(_tag_history_T_2, tag_history_hist_chunks_4)
node _tag_history_T_4 = xor(_tag_history_T_3, tag_history_hist_chunks_5)
node _tag_history_T_5 = xor(_tag_history_T_4, tag_history_hist_chunks_6)
node tag_history = xor(_tag_history_T_5, tag_history_hist_chunks_7)
node _tag_T = shr(_T_1, 7)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 8, 0)
smem hi_us : UInt<1>[4] [128]
smem lo_us : UInt<1>[4] [128]
smem table : UInt<13>[4] [128]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<7>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<13>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 11, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 12, 12)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<13>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 11, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 12, 12)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<13>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 11, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 12, 12)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<13>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 11, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 12, 12)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<7>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<7>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 3)
node idx_history_hist_chunks_0_1 = bits(io.update_hist, 6, 0)
node idx_history_hist_chunks_1_1 = bits(io.update_hist, 13, 7)
node idx_history_hist_chunks_2_1 = bits(io.update_hist, 20, 14)
node idx_history_hist_chunks_3_1 = bits(io.update_hist, 27, 21)
node idx_history_hist_chunks_4_1 = bits(io.update_hist, 34, 28)
node idx_history_hist_chunks_5_1 = bits(io.update_hist, 41, 35)
node idx_history_hist_chunks_6_1 = bits(io.update_hist, 48, 42)
node idx_history_hist_chunks_7_1 = bits(io.update_hist, 55, 49)
node idx_history_hist_chunks_8_1 = bits(io.update_hist, 62, 56)
node idx_history_hist_chunks_9_1 = bits(io.update_hist, 63, 63)
node _idx_history_T_8 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1)
node _idx_history_T_9 = xor(_idx_history_T_8, idx_history_hist_chunks_2_1)
node _idx_history_T_10 = xor(_idx_history_T_9, idx_history_hist_chunks_3_1)
node _idx_history_T_11 = xor(_idx_history_T_10, idx_history_hist_chunks_4_1)
node _idx_history_T_12 = xor(_idx_history_T_11, idx_history_hist_chunks_5_1)
node _idx_history_T_13 = xor(_idx_history_T_12, idx_history_hist_chunks_6_1)
node _idx_history_T_14 = xor(_idx_history_T_13, idx_history_hist_chunks_7_1)
node _idx_history_T_15 = xor(_idx_history_T_14, idx_history_hist_chunks_8_1)
node idx_history_1 = xor(_idx_history_T_15, idx_history_hist_chunks_9_1)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 6, 0)
node tag_history_hist_chunks_0_1 = bits(io.update_hist, 8, 0)
node tag_history_hist_chunks_1_1 = bits(io.update_hist, 17, 9)
node tag_history_hist_chunks_2_1 = bits(io.update_hist, 26, 18)
node tag_history_hist_chunks_3_1 = bits(io.update_hist, 35, 27)
node tag_history_hist_chunks_4_1 = bits(io.update_hist, 44, 36)
node tag_history_hist_chunks_5_1 = bits(io.update_hist, 53, 45)
node tag_history_hist_chunks_6_1 = bits(io.update_hist, 62, 54)
node tag_history_hist_chunks_7_1 = bits(io.update_hist, 63, 63)
node _tag_history_T_6 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1)
node _tag_history_T_7 = xor(_tag_history_T_6, tag_history_hist_chunks_2_1)
node _tag_history_T_8 = xor(_tag_history_T_7, tag_history_hist_chunks_3_1)
node _tag_history_T_9 = xor(_tag_history_T_8, tag_history_hist_chunks_4_1)
node _tag_history_T_10 = xor(_tag_history_T_9, tag_history_hist_chunks_5_1)
node _tag_history_T_11 = xor(_tag_history_T_10, tag_history_hist_chunks_6_1)
node tag_history_1 = xor(_tag_history_T_11, tag_history_hist_chunks_7_1)
node _tag_T_2 = shr(_T_2, 7)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 8, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<9>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<13>[4]
connect _WIRE[0], UInt<13>(0h0)
connect _WIRE[1], UInt<13>(0h0)
connect _WIRE[2], UInt<13>(0h0)
connect _WIRE[3], UInt<13>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<13>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 6, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 6, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<9>[2], clock
reg wrbypass_idxs : UInt<7>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_11( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [12:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [12:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [51:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [6:0] reset_idx; // @[tage.scala:73:26]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26]
wire [6:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[6:0]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[13:7]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_2 = io_f1_req_ghist_0[20:14]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_3 = io_f1_req_ghist_0[27:21]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_4 = io_f1_req_ghist_0[34:28]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_5 = io_f1_req_ghist_0[41:35]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_6 = io_f1_req_ghist_0[48:42]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_7 = io_f1_req_ghist_0[55:49]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_8 = io_f1_req_ghist_0[62:56]; // @[tage.scala:24:7, :53:11]
wire idx_history_hist_chunks_9 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11]
wire tag_history_hist_chunks_7 = io_f1_req_ghist_0[63]; // @[tage.scala:24:7, :53:11]
wire [6:0] _idx_history_T = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_1 = _idx_history_T ^ idx_history_hist_chunks_2; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_2 = _idx_history_T_1 ^ idx_history_hist_chunks_3; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_3 = _idx_history_T_2 ^ idx_history_hist_chunks_4; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_4 = _idx_history_T_3 ^ idx_history_hist_chunks_5; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_5 = _idx_history_T_4 ^ idx_history_hist_chunks_6; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_6 = _idx_history_T_5 ^ idx_history_hist_chunks_7; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_7 = _idx_history_T_6 ^ idx_history_hist_chunks_8; // @[tage.scala:53:11, :55:25]
wire [6:0] idx_history = {_idx_history_T_7[6:1], _idx_history_T_7[0] ^ idx_history_hist_chunks_9}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35]
wire [36:0] _idx_T = {_tag_T, io_f1_req_pc_0[9:3] ^ idx_history}; // @[frontend.scala:162:35]
wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}]
wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [8:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[8:0]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[17:9]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_2 = io_f1_req_ghist_0[26:18]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_3 = io_f1_req_ghist_0[35:27]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_4 = io_f1_req_ghist_0[44:36]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_5 = io_f1_req_ghist_0[53:45]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_6 = io_f1_req_ghist_0[62:54]; // @[tage.scala:24:7, :53:11]
wire [8:0] _tag_history_T = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_1 = _tag_history_T ^ tag_history_hist_chunks_2; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_2 = _tag_history_T_1 ^ tag_history_hist_chunks_3; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_3 = _tag_history_T_2 ^ tag_history_hist_chunks_4; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_4 = _tag_history_T_3 ^ tag_history_hist_chunks_5; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_5 = _tag_history_T_4 ^ tag_history_hist_chunks_6; // @[tage.scala:53:11, :55:25]
wire [8:0] tag_history = {_tag_history_T_5[8:1], _tag_history_T_5[0] ^ tag_history_hist_chunks_7}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_1 = {_tag_T[29:9], _tag_T[8:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}]
wire [8:0] s1_tag = _tag_T_1[8:0]; // @[tage.scala:62:{50,64}]
wire [12:0] _s2_req_rtage_WIRE_2 = _table_R0_data[12:0]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_4 = _table_R0_data[25:13]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_6 = _table_R0_data[38:26]; // @[tage.scala:91:27, :97:87]
wire [12:0] _s2_req_rtage_WIRE_8 = _table_R0_data[51:39]; // @[tage.scala:91:27, :97:87]
reg [8:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [8:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [8:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[11:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[12]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [18:0] clear_u_ctr; // @[tage.scala:109:28]
wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85]
wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33]
wire [6:0] idx_history_hist_chunks_0_1 = io_update_hist_0[6:0]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_1_1 = io_update_hist_0[13:7]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_2_1 = io_update_hist_0[20:14]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_3_1 = io_update_hist_0[27:21]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_4_1 = io_update_hist_0[34:28]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_5_1 = io_update_hist_0[41:35]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_6_1 = io_update_hist_0[48:42]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_7_1 = io_update_hist_0[55:49]; // @[tage.scala:24:7, :53:11]
wire [6:0] idx_history_hist_chunks_8_1 = io_update_hist_0[62:56]; // @[tage.scala:24:7, :53:11]
wire idx_history_hist_chunks_9_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11]
wire tag_history_hist_chunks_7_1 = io_update_hist_0[63]; // @[tage.scala:24:7, :53:11]
wire [6:0] _idx_history_T_8 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_9 = _idx_history_T_8 ^ idx_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_10 = _idx_history_T_9 ^ idx_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_11 = _idx_history_T_10 ^ idx_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_12 = _idx_history_T_11 ^ idx_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_13 = _idx_history_T_12 ^ idx_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_14 = _idx_history_T_13 ^ idx_history_hist_chunks_7_1; // @[tage.scala:53:11, :55:25]
wire [6:0] _idx_history_T_15 = _idx_history_T_14 ^ idx_history_hist_chunks_8_1; // @[tage.scala:53:11, :55:25]
wire [6:0] idx_history_1 = {_idx_history_T_15[6:1], _idx_history_T_15[0] ^ idx_history_hist_chunks_9_1}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35]
wire [36:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[9:3] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}]
wire [8:0] tag_history_hist_chunks_0_1 = io_update_hist_0[8:0]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_1_1 = io_update_hist_0[17:9]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_2_1 = io_update_hist_0[26:18]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_3_1 = io_update_hist_0[35:27]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_4_1 = io_update_hist_0[44:36]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_5_1 = io_update_hist_0[53:45]; // @[tage.scala:24:7, :53:11]
wire [8:0] tag_history_hist_chunks_6_1 = io_update_hist_0[62:54]; // @[tage.scala:24:7, :53:11]
wire [8:0] _tag_history_T_6 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_7 = _tag_history_T_6 ^ tag_history_hist_chunks_2_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_8 = _tag_history_T_7 ^ tag_history_hist_chunks_3_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_9 = _tag_history_T_8 ^ tag_history_hist_chunks_4_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_10 = _tag_history_T_9 ^ tag_history_hist_chunks_5_1; // @[tage.scala:53:11, :55:25]
wire [8:0] _tag_history_T_11 = _tag_history_T_10 ^ tag_history_hist_chunks_6_1; // @[tage.scala:53:11, :55:25]
wire [8:0] tag_history_1 = {_tag_history_T_11[8:1], _tag_history_T_11[0] ^ tag_history_hist_chunks_7_1}; // @[tage.scala:53:11, :55:25]
wire [29:0] _tag_T_3 = {_tag_T_2[29:9], _tag_T_2[8:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}]
wire [8:0] update_tag = _tag_T_3[8:0]; // @[tage.scala:62:{50,64}]
wire [8:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [8:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [9:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [9:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 13'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 13'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 13'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 13'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [8:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [8:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 7'h0; // @[tage.scala:73:26]
clear_u_ctr <= 19'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_10 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_10 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_10 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s4k4z4u :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_45
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d128s4k4z4u
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d128s4k4z4u
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.mask, UInt<16>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_10.bits.sink, UInt<4>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_92 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_93 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLBuffer_a32d128s4k4z4u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_45 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s4k4z4u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s4k4z4u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_273 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_509
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_273( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_509 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCache :
input clock : Clock
input reset : Reset
output auto : { flip ctrls_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
inst ctrls of InclusiveCacheControl
connect ctrls.clock, clock
connect ctrls.reset, reset
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_40
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
connect ctrls.auto.ctrl_in, auto.ctrls_ctrl_in
inst inclusive_cache_bank_sched of InclusiveCacheBankScheduler
connect inclusive_cache_bank_sched.clock, clock
connect inclusive_cache_bank_sched.reset, reset
connect inclusive_cache_bank_sched.io.in, nodeIn
connect nodeOut.e.bits, inclusive_cache_bank_sched.io.out.e.bits
connect nodeOut.e.valid, inclusive_cache_bank_sched.io.out.e.valid
connect inclusive_cache_bank_sched.io.out.e.ready, nodeOut.e.ready
connect inclusive_cache_bank_sched.io.out.d, nodeOut.d
connect nodeOut.c.bits, inclusive_cache_bank_sched.io.out.c.bits
connect nodeOut.c.valid, inclusive_cache_bank_sched.io.out.c.valid
connect inclusive_cache_bank_sched.io.out.c.ready, nodeOut.c.ready
connect inclusive_cache_bank_sched.io.out.b, nodeOut.b
connect nodeOut.a.bits, inclusive_cache_bank_sched.io.out.a.bits
connect nodeOut.a.valid, inclusive_cache_bank_sched.io.out.a.valid
connect inclusive_cache_bank_sched.io.out.a.ready, nodeOut.a.ready
invalidate inclusive_cache_bank_sched.io.ways[0]
invalidate inclusive_cache_bank_sched.io.ways[1]
invalidate inclusive_cache_bank_sched.io.ways[2]
invalidate inclusive_cache_bank_sched.io.ways[3]
invalidate inclusive_cache_bank_sched.io.ways[4]
invalidate inclusive_cache_bank_sched.io.ways[5]
invalidate inclusive_cache_bank_sched.io.ways[6]
invalidate inclusive_cache_bank_sched.io.ways[7]
invalidate inclusive_cache_bank_sched.io.divs[0]
invalidate inclusive_cache_bank_sched.io.divs[1]
invalidate inclusive_cache_bank_sched.io.divs[2]
invalidate inclusive_cache_bank_sched.io.divs[3]
invalidate inclusive_cache_bank_sched.io.divs[4]
invalidate inclusive_cache_bank_sched.io.divs[5]
invalidate inclusive_cache_bank_sched.io.divs[6]
invalidate inclusive_cache_bank_sched.io.divs[7]
connect inclusive_cache_bank_sched.io.req.valid, UInt<1>(0h0)
connect inclusive_cache_bank_sched.io.req.bits.address, UInt<1>(0h0)
connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1)
node _nodeOut_a_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_address_mux_matches_T_1 = cvt(_nodeOut_a_bits_address_mux_matches_T)
node _nodeOut_a_bits_address_mux_matches_T_2 = and(_nodeOut_a_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_address_mux_matches_T_3 = asSInt(_nodeOut_a_bits_address_mux_matches_T_2)
node nodeOut_a_bits_address_mux_0_1 = eq(_nodeOut_a_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_address_T = or(inclusive_cache_bank_sched.io.out.a.bits.address, UInt<1>(0h0))
connect nodeOut.a.bits.address, _nodeOut_a_bits_address_T
node _nodeIn_b_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0))
node _nodeIn_b_bits_address_mux_matches_T_1 = cvt(_nodeIn_b_bits_address_mux_matches_T)
node _nodeIn_b_bits_address_mux_matches_T_2 = and(_nodeIn_b_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeIn_b_bits_address_mux_matches_T_3 = asSInt(_nodeIn_b_bits_address_mux_matches_T_2)
node nodeIn_b_bits_address_mux_0_1 = eq(_nodeIn_b_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeIn_b_bits_address_T = or(inclusive_cache_bank_sched.io.in.b.bits.address, UInt<1>(0h0))
connect nodeIn.b.bits.address, _nodeIn_b_bits_address_T
node _nodeOut_c_bits_address_mux_matches_T = xor(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0))
node _nodeOut_c_bits_address_mux_matches_T_1 = cvt(_nodeOut_c_bits_address_mux_matches_T)
node _nodeOut_c_bits_address_mux_matches_T_2 = and(_nodeOut_c_bits_address_mux_matches_T_1, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_address_mux_matches_T_3 = asSInt(_nodeOut_c_bits_address_mux_matches_T_2)
node nodeOut_c_bits_address_mux_0_1 = eq(_nodeOut_c_bits_address_mux_matches_T_3, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_address_T = or(inclusive_cache_bank_sched.io.out.c.bits.address, UInt<1>(0h0))
connect nodeOut.c.bits.address, _nodeOut_c_bits_address_T
connect ctrls.io.flush_req.ready, UInt<1>(0h0)
connect ctrls.io.flush_resp, UInt<1>(0h0)
connect ctrls.io.flush_match, UInt<1>(0h0)
node _contained_T = xor(ctrls.io.flush_req.bits, UInt<32>(0h80000000))
node _contained_T_1 = cvt(_contained_T)
node _contained_T_2 = and(_contained_T_1, asSInt(UInt<29>(0h10000000)))
node _contained_T_3 = asSInt(_contained_T_2)
node _contained_T_4 = eq(_contained_T_3, asSInt(UInt<1>(0h0)))
node _contained_T_5 = xor(ctrls.io.flush_req.bits, UInt<28>(0h8000000))
node _contained_T_6 = cvt(_contained_T_5)
node _contained_T_7 = and(_contained_T_6, asSInt(UInt<17>(0h10000)))
node _contained_T_8 = asSInt(_contained_T_7)
node _contained_T_9 = eq(_contained_T_8, asSInt(UInt<1>(0h0)))
node contained = or(_contained_T_4, _contained_T_9)
when contained :
connect ctrls.io.flush_match, UInt<1>(0h1)
node _inclusive_cache_bank_sched_io_req_valid_T = and(contained, ctrls.io.flush_req.valid)
connect inclusive_cache_bank_sched.io.req.valid, _inclusive_cache_bank_sched_io_req_valid_T
connect inclusive_cache_bank_sched.io.req.bits.address, ctrls.io.flush_req.bits
node _T = and(contained, inclusive_cache_bank_sched.io.req.ready)
when _T :
connect ctrls.io.flush_req.ready, UInt<1>(0h1)
when inclusive_cache_bank_sched.io.resp.valid :
connect ctrls.io.flush_resp, UInt<1>(0h1)
connect inclusive_cache_bank_sched.io.resp.ready, UInt<1>(0h1) | module InclusiveCache( // @[InclusiveCache.scala:108:9]
input clock, // @[InclusiveCache.scala:108:9]
input reset, // @[InclusiveCache.scala:108:9]
output auto_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire [31:0] _inclusive_cache_bank_sched_io_in_b_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_out_a_bits_address; // @[InclusiveCache.scala:137:29]
wire [31:0] _inclusive_cache_bank_sched_io_out_c_bits_address; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_req_ready; // @[InclusiveCache.scala:137:29]
wire _inclusive_cache_bank_sched_io_resp_valid; // @[InclusiveCache.scala:137:29]
wire _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43]
wire [63:0] _ctrls_io_flush_req_bits; // @[InclusiveCache.scala:103:43]
wire auto_ctrls_ctrl_in_a_valid_0 = auto_ctrls_ctrl_in_a_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_a_bits_opcode_0 = auto_ctrls_ctrl_in_a_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_a_bits_param_0 = auto_ctrls_ctrl_in_a_bits_param; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_ctrls_ctrl_in_a_bits_size_0 = auto_ctrls_ctrl_in_a_bits_size; // @[InclusiveCache.scala:108:9]
wire [10:0] auto_ctrls_ctrl_in_a_bits_source_0 = auto_ctrls_ctrl_in_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [25:0] auto_ctrls_ctrl_in_a_bits_address_0 = auto_ctrls_ctrl_in_a_bits_address; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_ctrls_ctrl_in_a_bits_mask_0 = auto_ctrls_ctrl_in_a_bits_mask; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_ctrls_ctrl_in_a_bits_data_0 = auto_ctrls_ctrl_in_a_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_a_bits_corrupt_0 = auto_ctrls_ctrl_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_d_ready_0 = auto_ctrls_ctrl_in_d_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_in_c_bits_corrupt_0 = auto_in_c_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[InclusiveCache.scala:108:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[InclusiveCache.scala:108:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[InclusiveCache.scala:108:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[InclusiveCache.scala:108:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[InclusiveCache.scala:108:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[InclusiveCache.scala:108:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[InclusiveCache.scala:108:9]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [7:0] auto_out_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [7:0] nodeOut_b_bits_mask = 8'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [31:0] auto_out_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [31:0] nodeOut_b_bits_address = 32'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] auto_out_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_opcode = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_size = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire [2:0] nodeOut_b_bits_source = 3'h0; // @[InclusiveCache.scala:108:9, :137:29]
wire auto_in_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_out_b_ready = 1'h1; // @[Nodes.scala:27:25]
wire auto_out_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeIn_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_b_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_e_ready = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_a_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire nodeIn_b_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire nodeOut_c_bits_address_mux_0_1 = 1'h1; // @[Nodes.scala:27:25]
wire [63:0] auto_in_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] auto_out_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] nodeIn_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [63:0] nodeOut_b_bits_data = 64'h0; // @[Nodes.scala:27:25]
wire [7:0] auto_in_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25]
wire [7:0] nodeIn_b_bits_mask = 8'hFF; // @[Nodes.scala:27:25]
wire [5:0] auto_in_b_bits_source = 6'h10; // @[Nodes.scala:27:25]
wire [5:0] nodeIn_b_bits_source = 6'h10; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] auto_in_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeIn_b_bits_opcode = 3'h6; // @[Nodes.scala:27:25]
wire [2:0] nodeIn_b_bits_size = 3'h6; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[Nodes.scala:27:25]
wire auto_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire auto_in_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire auto_out_b_valid = 1'h0; // @[Nodes.scala:27:25]
wire auto_out_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeIn_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire nodeOut_b_valid = 1'h0; // @[Nodes.scala:27:25]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Nodes.scala:27:25]
wire [1:0] auto_ctrls_ctrl_in_d_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire [1:0] auto_out_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire [1:0] nodeOut_b_bits_param = 2'h0; // @[InclusiveCache.scala:103:43, :108:9, :137:29]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_c_bits_corrupt = auto_in_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [5:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [10:0] auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_in_a_ready_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9]
wire auto_in_b_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_in_c_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [1:0] auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [5:0] auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_in_d_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [7:0] auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_out_a_valid_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9]
wire [31:0] auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9]
wire [63:0] auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9]
wire auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
wire auto_out_c_valid_0; // @[InclusiveCache.scala:108:9]
wire auto_out_d_ready_0; // @[InclusiveCache.scala:108:9]
wire [2:0] auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
wire auto_out_e_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[InclusiveCache.scala:108:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[InclusiveCache.scala:108:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[InclusiveCache.scala:108:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[InclusiveCache.scala:108:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[InclusiveCache.scala:108:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[InclusiveCache.scala:108:9]
wire [31:0] _nodeOut_a_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeOut_a_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_a_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeOut_a_bits_address = _nodeOut_a_bits_address_T; // @[Parameters.scala:248:14]
wire [31:0] _nodeIn_b_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeIn_b_bits_address_mux_matches_T_1 = {1'h0, _nodeIn_b_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeIn_b_bits_address = _nodeIn_b_bits_address_T; // @[Parameters.scala:248:14]
wire [31:0] _nodeOut_c_bits_address_mux_matches_T; // @[Parameters.scala:137:31]
wire [32:0] _nodeOut_c_bits_address_mux_matches_T_1 = {1'h0, _nodeOut_c_bits_address_mux_matches_T}; // @[Nodes.scala:27:25]
assign nodeOut_c_bits_address = _nodeOut_c_bits_address_T; // @[Parameters.scala:248:14]
wire [63:0] _contained_T = {_ctrls_io_flush_req_bits[63:32], _ctrls_io_flush_req_bits[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [64:0] _contained_T_1 = {1'h0, _contained_T}; // @[Nodes.scala:27:25]
wire [64:0] _contained_T_2 = _contained_T_1 & 65'h1FFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [64:0] _contained_T_3 = _contained_T_2; // @[Parameters.scala:137:46]
wire _contained_T_4 = _contained_T_3 == 65'h0; // @[Parameters.scala:137:{46,59}]
wire [63:0] _contained_T_5 = {_ctrls_io_flush_req_bits[63:28], _ctrls_io_flush_req_bits[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [64:0] _contained_T_6 = {1'h0, _contained_T_5}; // @[Nodes.scala:27:25]
wire [64:0] _contained_T_7 = _contained_T_6 & 65'h1FFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [64:0] _contained_T_8 = _contained_T_7; // @[Parameters.scala:137:46]
wire _contained_T_9 = _contained_T_8 == 65'h0; // @[Parameters.scala:137:{46,59}]
wire contained = _contained_T_4 | _contained_T_9; // @[Parameters.scala:137:59]
wire _inclusive_cache_bank_sched_io_req_valid_T = contained & _ctrls_io_flush_req_valid; // @[InclusiveCache.scala:103:43, :169:67, :172:41]
InclusiveCacheControl ctrls ( // @[InclusiveCache.scala:103:43]
.clock (clock),
.reset (reset),
.auto_ctrl_in_a_ready (auto_ctrls_ctrl_in_a_ready_0),
.auto_ctrl_in_a_valid (auto_ctrls_ctrl_in_a_valid_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_opcode (auto_ctrls_ctrl_in_a_bits_opcode_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_param (auto_ctrls_ctrl_in_a_bits_param_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_size (auto_ctrls_ctrl_in_a_bits_size_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_source (auto_ctrls_ctrl_in_a_bits_source_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_address (auto_ctrls_ctrl_in_a_bits_address_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_mask (auto_ctrls_ctrl_in_a_bits_mask_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_data (auto_ctrls_ctrl_in_a_bits_data_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_a_bits_corrupt (auto_ctrls_ctrl_in_a_bits_corrupt_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_d_ready (auto_ctrls_ctrl_in_d_ready_0), // @[InclusiveCache.scala:108:9]
.auto_ctrl_in_d_valid (auto_ctrls_ctrl_in_d_valid_0),
.auto_ctrl_in_d_bits_opcode (auto_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrl_in_d_bits_size (auto_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrl_in_d_bits_source (auto_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrl_in_d_bits_data (auto_ctrls_ctrl_in_d_bits_data_0),
.io_flush_match (contained), // @[InclusiveCache.scala:169:67]
.io_flush_req_ready (contained & _inclusive_cache_bank_sched_io_req_ready), // @[InclusiveCache.scala:137:29, :169:67, :174:25]
.io_flush_req_valid (_ctrls_io_flush_req_valid),
.io_flush_req_bits (_ctrls_io_flush_req_bits),
.io_flush_resp (_inclusive_cache_bank_sched_io_resp_valid) // @[InclusiveCache.scala:137:29]
); // @[InclusiveCache.scala:103:43]
TLMonitor_40 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
InclusiveCacheBankScheduler inclusive_cache_bank_sched ( // @[InclusiveCache.scala:137:29]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready),
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid),
.io_in_b_bits_param (nodeIn_b_bits_param),
.io_in_b_bits_address (_inclusive_cache_bank_sched_io_in_b_bits_address),
.io_in_c_ready (nodeIn_c_ready),
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_c_bits_corrupt (nodeIn_c_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid),
.io_in_d_bits_opcode (nodeIn_d_bits_opcode),
.io_in_d_bits_param (nodeIn_d_bits_param),
.io_in_d_bits_size (nodeIn_d_bits_size),
.io_in_d_bits_source (nodeIn_d_bits_source),
.io_in_d_bits_sink (nodeIn_d_bits_sink),
.io_in_d_bits_denied (nodeIn_d_bits_denied),
.io_in_d_bits_data (nodeIn_d_bits_data),
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt),
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_out_a_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_out_a_valid (nodeOut_a_valid),
.io_out_a_bits_opcode (nodeOut_a_bits_opcode),
.io_out_a_bits_param (nodeOut_a_bits_param),
.io_out_a_bits_size (nodeOut_a_bits_size),
.io_out_a_bits_source (nodeOut_a_bits_source),
.io_out_a_bits_address (_inclusive_cache_bank_sched_io_out_a_bits_address),
.io_out_a_bits_mask (nodeOut_a_bits_mask),
.io_out_a_bits_data (nodeOut_a_bits_data),
.io_out_a_bits_corrupt (nodeOut_a_bits_corrupt),
.io_out_c_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_out_c_valid (nodeOut_c_valid),
.io_out_c_bits_opcode (nodeOut_c_bits_opcode),
.io_out_c_bits_param (nodeOut_c_bits_param),
.io_out_c_bits_size (nodeOut_c_bits_size),
.io_out_c_bits_source (nodeOut_c_bits_source),
.io_out_c_bits_address (_inclusive_cache_bank_sched_io_out_c_bits_address),
.io_out_c_bits_data (nodeOut_c_bits_data),
.io_out_c_bits_corrupt (nodeOut_c_bits_corrupt),
.io_out_d_ready (nodeOut_d_ready),
.io_out_d_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_out_d_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_out_d_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_out_d_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_out_d_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_out_d_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_out_d_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_out_d_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_out_d_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_out_e_valid (nodeOut_e_valid),
.io_out_e_bits_sink (nodeOut_e_bits_sink),
.io_req_ready (_inclusive_cache_bank_sched_io_req_ready),
.io_req_valid (_inclusive_cache_bank_sched_io_req_valid_T), // @[InclusiveCache.scala:172:41]
.io_req_bits_address (_ctrls_io_flush_req_bits[31:0]), // @[Parameters.scala:137:31]
.io_resp_valid (_inclusive_cache_bank_sched_io_resp_valid)
); // @[InclusiveCache.scala:137:29]
assign _nodeOut_a_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:137:31]
assign _nodeOut_a_bits_address_T = _inclusive_cache_bank_sched_io_out_a_bits_address; // @[Parameters.scala:248:14]
assign _nodeIn_b_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:137:31]
assign _nodeIn_b_bits_address_T = _inclusive_cache_bank_sched_io_in_b_bits_address; // @[Parameters.scala:248:14]
assign _nodeOut_c_bits_address_mux_matches_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:137:31]
assign _nodeOut_c_bits_address_T = _inclusive_cache_bank_sched_io_out_c_bits_address; // @[Parameters.scala:248:14]
assign auto_ctrls_ctrl_in_a_ready = auto_ctrls_ctrl_in_a_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_valid = auto_ctrls_ctrl_in_d_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_opcode = auto_ctrls_ctrl_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_size = auto_ctrls_ctrl_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_source = auto_ctrls_ctrl_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_ctrls_ctrl_in_d_bits_data = auto_ctrls_ctrl_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_in_a_ready = auto_in_a_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[InclusiveCache.scala:108:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[InclusiveCache.scala:108:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[InclusiveCache.scala:108:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[InclusiveCache.scala:108:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[InclusiveCache.scala:108:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_50 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_306
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_50( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_306 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_18 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<7>(0h7f))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history = bits(io.f1_req_ghist, 1, 0)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 6, 0)
node tag_history = bits(io.f1_req_ghist, 1, 0)
node _tag_T = shr(_T_1, 7)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 6, 0)
smem hi_us : UInt<1>[4] [128]
smem lo_us : UInt<1>[4] [128]
smem table : UInt<11>[4] [128]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<7>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<11>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 9, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 10, 10)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<11>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 9, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 10, 10)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<11>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 9, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 10, 10)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<11>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 9, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 10, 10)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<7>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<7>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 18, 18)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 4)
node idx_history_1 = bits(io.update_hist, 1, 0)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 6, 0)
node tag_history_1 = bits(io.update_hist, 1, 0)
node _tag_T_2 = shr(_T_2, 7)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 6, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<11>[4]
connect _WIRE[0], UInt<11>(0h0)
connect _WIRE[1], UInt<11>(0h0)
connect _WIRE[2], UInt<11>(0h0)
connect _WIRE[3], UInt<11>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<11>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 6, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 6, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<7>[2], clock
reg wrbypass_idxs : UInt<7>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_18( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [43:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [6:0] reset_idx; // @[tage.scala:73:26]
wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26]
wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [35:0] _idx_T = {io_f1_req_pc_0[39:6], io_f1_req_pc_0[5:4] ^ idx_history}; // @[frontend.scala:162:35]
wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}]
wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:162:35]
wire [28:0] _tag_T_1 = {_tag_T[28:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}]
wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87]
wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87]
reg [6:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [18:0] clear_u_ctr; // @[tage.scala:109:28]
wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85]
wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33]
wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11]
wire [35:0] _idx_T_1 = {io_update_pc_0[39:6], io_update_pc_0[5:4] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}]
wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:162:35]
wire [28:0] _tag_T_3 = {_tag_T_2[28:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}]
wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 7'h0; // @[tage.scala:73:26]
clear_u_ctr <= 19'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_17 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_17 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_17 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_21 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_42
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_21
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _T_4 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _T_5 = or(_T, _T_1)
node _T_6 = or(_T_5, _T_2)
node _T_7 = or(_T_6, _T_3)
node _T_8 = or(_T_7, _T_4)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = and(io.in.valid, _T_9)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_11, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0h8)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h0)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<3>(0h4)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_4, UInt<2>(0h3), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_5, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_T_10, _route_buffer_io_enq_bits_flow_egress_node_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_T_11, _route_buffer_io_enq_bits_flow_egress_node_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_T_12, _route_buffer_io_enq_bits_flow_egress_node_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_13
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h1b), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h18), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1e), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h15), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, UInt<1>(0h0), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_5, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_11 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_10, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_11, _route_buffer_io_enq_bits_flow_egress_node_id_T_8)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_12, _route_buffer_io_enq_bits_flow_egress_node_id_T_9)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_13
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0h8))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_15 = and(io.in.ready, io.in.valid)
node _T_16 = and(_T_15, io.in.bits.head)
node _T_17 = and(_T_16, at_dest)
when _T_17 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_18 = eq(UInt<4>(0ha), io.in.bits.egress_id)
when _T_18 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_19 = eq(UInt<4>(0hb), io.in.bits.egress_id)
when _T_19 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_20 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_21 = and(route_q.io.enq.valid, _T_20)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = asUInt(reset)
node _T_24 = eq(_T_23, UInt<1>(0h0))
when _T_24 :
node _T_25 = eq(_T_22, UInt<1>(0h0))
when _T_25 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_22, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_43
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_21
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_26 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_27 = and(vcalloc_q.io.enq.valid, _T_26)
node _T_28 = eq(_T_27, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node _c_T_1 = cat(c_hi_1, _c_T)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_1)
node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _c_T_3 = cat(c_hi_3, _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_21( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 5'h1B; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 5'h18; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 5'h1E; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 5'h15; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_11 = {_route_buffer_io_enq_bits_flow_egress_node_id_T, {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire [2:0] _GEN_0 = _route_buffer_io_enq_bits_flow_egress_node_T_11[2:0] | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 3'h5 : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _GEN_1 = _GEN_0[1:0] | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_4}}; // @[Mux.scala:30:73]
wire [3:0] _GEN_2 = {_route_buffer_io_enq_bits_flow_egress_node_T_11[3], _GEN_0[2], _GEN_1}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_2 == 4'h8; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_2 != 4'h8; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module CtlPath :
input clock : Clock
input reset : Reset
output io : { flip dcpath : { halt : UInt<1>}, flip imem : { flip req : { valid : UInt<1>, bits : { pc : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<32>, inst : UInt<32>}}, debug : { if_pc : UInt<32>, if_inst : UInt<32>}, imiss : UInt<1>, flip exe_kill : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip dat : { br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, wb_hazard_stall : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, ctl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}}
invalidate io.ctl.exception_cause
invalidate io.ctl.exception
invalidate io.ctl.dmem_typ
invalidate io.ctl.dmem_fcn
invalidate io.ctl.dmem_val
invalidate io.ctl.csr_cmd
invalidate io.ctl.bypassable
invalidate io.ctl.rf_wen
invalidate io.ctl.wb_sel
invalidate io.ctl.alu_fun
invalidate io.ctl.op2_sel
invalidate io.ctl.op1_sel
invalidate io.ctl.brjmp_sel
invalidate io.ctl.pc_sel
invalidate io.ctl.exe_kill
invalidate io.dat.csr_interrupt
invalidate io.dat.csr_eret
invalidate io.dat.wb_hazard_stall
invalidate io.dat.data_misaligned
invalidate io.dat.inst_misaligned
invalidate io.dat.br_ltu
invalidate io.dat.br_lt
invalidate io.dat.br_eq
invalidate io.dmem.resp.bits.data
invalidate io.dmem.resp.valid
invalidate io.dmem.req.bits.typ
invalidate io.dmem.req.bits.fcn
invalidate io.dmem.req.bits.data
invalidate io.dmem.req.bits.addr
invalidate io.dmem.req.valid
invalidate io.dmem.req.ready
invalidate io.imem.exe_kill
invalidate io.imem.imiss
invalidate io.imem.debug.if_inst
invalidate io.imem.debug.if_pc
invalidate io.imem.resp.bits.inst
invalidate io.imem.resp.bits.pc
invalidate io.imem.resp.valid
invalidate io.imem.resp.ready
invalidate io.imem.req.bits.pc
invalidate io.imem.req.valid
invalidate io.dcpath.halt
node _csignals_T = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_1 = eq(UInt<14>(0h2003), _csignals_T)
node _csignals_T_2 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_3 = eq(UInt<2>(0h3), _csignals_T_2)
node _csignals_T_4 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_5 = eq(UInt<15>(0h4003), _csignals_T_4)
node _csignals_T_6 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_7 = eq(UInt<13>(0h1003), _csignals_T_6)
node _csignals_T_8 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_9 = eq(UInt<15>(0h5003), _csignals_T_8)
node _csignals_T_10 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_11 = eq(UInt<14>(0h2023), _csignals_T_10)
node _csignals_T_12 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_13 = eq(UInt<6>(0h23), _csignals_T_12)
node _csignals_T_14 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_15 = eq(UInt<13>(0h1023), _csignals_T_14)
node _csignals_T_16 = and(io.imem.resp.bits.inst, UInt<7>(0h7f))
node _csignals_T_17 = eq(UInt<5>(0h17), _csignals_T_16)
node _csignals_T_18 = and(io.imem.resp.bits.inst, UInt<7>(0h7f))
node _csignals_T_19 = eq(UInt<6>(0h37), _csignals_T_18)
node _csignals_T_20 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_21 = eq(UInt<5>(0h13), _csignals_T_20)
node _csignals_T_22 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_23 = eq(UInt<15>(0h7013), _csignals_T_22)
node _csignals_T_24 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_25 = eq(UInt<15>(0h6013), _csignals_T_24)
node _csignals_T_26 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_27 = eq(UInt<15>(0h4013), _csignals_T_26)
node _csignals_T_28 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_29 = eq(UInt<14>(0h2013), _csignals_T_28)
node _csignals_T_30 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_31 = eq(UInt<14>(0h3013), _csignals_T_30)
node _csignals_T_32 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_33 = eq(UInt<13>(0h1013), _csignals_T_32)
node _csignals_T_34 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_35 = eq(UInt<31>(0h40005013), _csignals_T_34)
node _csignals_T_36 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_37 = eq(UInt<15>(0h5013), _csignals_T_36)
node _csignals_T_38 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_39 = eq(UInt<13>(0h1033), _csignals_T_38)
node _csignals_T_40 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_41 = eq(UInt<6>(0h33), _csignals_T_40)
node _csignals_T_42 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_43 = eq(UInt<31>(0h40000033), _csignals_T_42)
node _csignals_T_44 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_45 = eq(UInt<14>(0h2033), _csignals_T_44)
node _csignals_T_46 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_47 = eq(UInt<14>(0h3033), _csignals_T_46)
node _csignals_T_48 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_49 = eq(UInt<15>(0h7033), _csignals_T_48)
node _csignals_T_50 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_51 = eq(UInt<15>(0h6033), _csignals_T_50)
node _csignals_T_52 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_53 = eq(UInt<15>(0h4033), _csignals_T_52)
node _csignals_T_54 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_55 = eq(UInt<31>(0h40005033), _csignals_T_54)
node _csignals_T_56 = and(io.imem.resp.bits.inst, UInt<32>(0hfe00707f))
node _csignals_T_57 = eq(UInt<15>(0h5033), _csignals_T_56)
node _csignals_T_58 = and(io.imem.resp.bits.inst, UInt<7>(0h7f))
node _csignals_T_59 = eq(UInt<7>(0h6f), _csignals_T_58)
node _csignals_T_60 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_61 = eq(UInt<7>(0h67), _csignals_T_60)
node _csignals_T_62 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_63 = eq(UInt<7>(0h63), _csignals_T_62)
node _csignals_T_64 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_65 = eq(UInt<13>(0h1063), _csignals_T_64)
node _csignals_T_66 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_67 = eq(UInt<15>(0h5063), _csignals_T_66)
node _csignals_T_68 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_69 = eq(UInt<15>(0h7063), _csignals_T_68)
node _csignals_T_70 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_71 = eq(UInt<15>(0h4063), _csignals_T_70)
node _csignals_T_72 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_73 = eq(UInt<15>(0h6063), _csignals_T_72)
node _csignals_T_74 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_75 = eq(UInt<15>(0h5073), _csignals_T_74)
node _csignals_T_76 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_77 = eq(UInt<15>(0h6073), _csignals_T_76)
node _csignals_T_78 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_79 = eq(UInt<13>(0h1073), _csignals_T_78)
node _csignals_T_80 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_81 = eq(UInt<14>(0h2073), _csignals_T_80)
node _csignals_T_82 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_83 = eq(UInt<14>(0h3073), _csignals_T_82)
node _csignals_T_84 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_85 = eq(UInt<15>(0h7073), _csignals_T_84)
node _csignals_T_86 = and(io.imem.resp.bits.inst, UInt<32>(0hffffffff))
node _csignals_T_87 = eq(UInt<7>(0h73), _csignals_T_86)
node _csignals_T_88 = and(io.imem.resp.bits.inst, UInt<32>(0hffffffff))
node _csignals_T_89 = eq(UInt<30>(0h30200073), _csignals_T_88)
node _csignals_T_90 = and(io.imem.resp.bits.inst, UInt<32>(0hffffffff))
node _csignals_T_91 = eq(UInt<31>(0h7b200073), _csignals_T_90)
node _csignals_T_92 = and(io.imem.resp.bits.inst, UInt<32>(0hffffffff))
node _csignals_T_93 = eq(UInt<21>(0h100073), _csignals_T_92)
node _csignals_T_94 = and(io.imem.resp.bits.inst, UInt<32>(0hffffffff))
node _csignals_T_95 = eq(UInt<29>(0h10500073), _csignals_T_94)
node _csignals_T_96 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_97 = eq(UInt<13>(0h100f), _csignals_T_96)
node _csignals_T_98 = and(io.imem.resp.bits.inst, UInt<15>(0h707f))
node _csignals_T_99 = eq(UInt<4>(0hf), _csignals_T_98)
node _csignals_T_100 = mux(_csignals_T_99, UInt<1>(0h1), UInt<1>(0h0))
node _csignals_T_101 = mux(_csignals_T_97, UInt<1>(0h1), _csignals_T_100)
node _csignals_T_102 = mux(_csignals_T_95, UInt<1>(0h1), _csignals_T_101)
node _csignals_T_103 = mux(_csignals_T_93, UInt<1>(0h1), _csignals_T_102)
node _csignals_T_104 = mux(_csignals_T_91, UInt<1>(0h1), _csignals_T_103)
node _csignals_T_105 = mux(_csignals_T_89, UInt<1>(0h1), _csignals_T_104)
node _csignals_T_106 = mux(_csignals_T_87, UInt<1>(0h1), _csignals_T_105)
node _csignals_T_107 = mux(_csignals_T_85, UInt<1>(0h1), _csignals_T_106)
node _csignals_T_108 = mux(_csignals_T_83, UInt<1>(0h1), _csignals_T_107)
node _csignals_T_109 = mux(_csignals_T_81, UInt<1>(0h1), _csignals_T_108)
node _csignals_T_110 = mux(_csignals_T_79, UInt<1>(0h1), _csignals_T_109)
node _csignals_T_111 = mux(_csignals_T_77, UInt<1>(0h1), _csignals_T_110)
node _csignals_T_112 = mux(_csignals_T_75, UInt<1>(0h1), _csignals_T_111)
node _csignals_T_113 = mux(_csignals_T_73, UInt<1>(0h1), _csignals_T_112)
node _csignals_T_114 = mux(_csignals_T_71, UInt<1>(0h1), _csignals_T_113)
node _csignals_T_115 = mux(_csignals_T_69, UInt<1>(0h1), _csignals_T_114)
node _csignals_T_116 = mux(_csignals_T_67, UInt<1>(0h1), _csignals_T_115)
node _csignals_T_117 = mux(_csignals_T_65, UInt<1>(0h1), _csignals_T_116)
node _csignals_T_118 = mux(_csignals_T_63, UInt<1>(0h1), _csignals_T_117)
node _csignals_T_119 = mux(_csignals_T_61, UInt<1>(0h1), _csignals_T_118)
node _csignals_T_120 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_119)
node _csignals_T_121 = mux(_csignals_T_57, UInt<1>(0h1), _csignals_T_120)
node _csignals_T_122 = mux(_csignals_T_55, UInt<1>(0h1), _csignals_T_121)
node _csignals_T_123 = mux(_csignals_T_53, UInt<1>(0h1), _csignals_T_122)
node _csignals_T_124 = mux(_csignals_T_51, UInt<1>(0h1), _csignals_T_123)
node _csignals_T_125 = mux(_csignals_T_49, UInt<1>(0h1), _csignals_T_124)
node _csignals_T_126 = mux(_csignals_T_47, UInt<1>(0h1), _csignals_T_125)
node _csignals_T_127 = mux(_csignals_T_45, UInt<1>(0h1), _csignals_T_126)
node _csignals_T_128 = mux(_csignals_T_43, UInt<1>(0h1), _csignals_T_127)
node _csignals_T_129 = mux(_csignals_T_41, UInt<1>(0h1), _csignals_T_128)
node _csignals_T_130 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_129)
node _csignals_T_131 = mux(_csignals_T_37, UInt<1>(0h1), _csignals_T_130)
node _csignals_T_132 = mux(_csignals_T_35, UInt<1>(0h1), _csignals_T_131)
node _csignals_T_133 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_132)
node _csignals_T_134 = mux(_csignals_T_31, UInt<1>(0h1), _csignals_T_133)
node _csignals_T_135 = mux(_csignals_T_29, UInt<1>(0h1), _csignals_T_134)
node _csignals_T_136 = mux(_csignals_T_27, UInt<1>(0h1), _csignals_T_135)
node _csignals_T_137 = mux(_csignals_T_25, UInt<1>(0h1), _csignals_T_136)
node _csignals_T_138 = mux(_csignals_T_23, UInt<1>(0h1), _csignals_T_137)
node _csignals_T_139 = mux(_csignals_T_21, UInt<1>(0h1), _csignals_T_138)
node _csignals_T_140 = mux(_csignals_T_19, UInt<1>(0h1), _csignals_T_139)
node _csignals_T_141 = mux(_csignals_T_17, UInt<1>(0h1), _csignals_T_140)
node _csignals_T_142 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_141)
node _csignals_T_143 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_142)
node _csignals_T_144 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_143)
node _csignals_T_145 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_144)
node _csignals_T_146 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_145)
node _csignals_T_147 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_146)
node _csignals_T_148 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_147)
node csignals_0 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_148)
node _csignals_T_149 = mux(_csignals_T_99, UInt<4>(0h0), UInt<4>(0h0))
node _csignals_T_150 = mux(_csignals_T_97, UInt<4>(0h0), _csignals_T_149)
node _csignals_T_151 = mux(_csignals_T_95, UInt<4>(0h0), _csignals_T_150)
node _csignals_T_152 = mux(_csignals_T_93, UInt<4>(0h0), _csignals_T_151)
node _csignals_T_153 = mux(_csignals_T_91, UInt<4>(0h0), _csignals_T_152)
node _csignals_T_154 = mux(_csignals_T_89, UInt<4>(0h0), _csignals_T_153)
node _csignals_T_155 = mux(_csignals_T_87, UInt<4>(0h0), _csignals_T_154)
node _csignals_T_156 = mux(_csignals_T_85, UInt<4>(0h0), _csignals_T_155)
node _csignals_T_157 = mux(_csignals_T_83, UInt<4>(0h0), _csignals_T_156)
node _csignals_T_158 = mux(_csignals_T_81, UInt<4>(0h0), _csignals_T_157)
node _csignals_T_159 = mux(_csignals_T_79, UInt<4>(0h0), _csignals_T_158)
node _csignals_T_160 = mux(_csignals_T_77, UInt<4>(0h0), _csignals_T_159)
node _csignals_T_161 = mux(_csignals_T_75, UInt<4>(0h0), _csignals_T_160)
node _csignals_T_162 = mux(_csignals_T_73, UInt<4>(0h6), _csignals_T_161)
node _csignals_T_163 = mux(_csignals_T_71, UInt<4>(0h5), _csignals_T_162)
node _csignals_T_164 = mux(_csignals_T_69, UInt<4>(0h4), _csignals_T_163)
node _csignals_T_165 = mux(_csignals_T_67, UInt<4>(0h3), _csignals_T_164)
node _csignals_T_166 = mux(_csignals_T_65, UInt<4>(0h1), _csignals_T_165)
node _csignals_T_167 = mux(_csignals_T_63, UInt<4>(0h2), _csignals_T_166)
node _csignals_T_168 = mux(_csignals_T_61, UInt<4>(0h8), _csignals_T_167)
node _csignals_T_169 = mux(_csignals_T_59, UInt<4>(0h7), _csignals_T_168)
node _csignals_T_170 = mux(_csignals_T_57, UInt<4>(0h0), _csignals_T_169)
node _csignals_T_171 = mux(_csignals_T_55, UInt<4>(0h0), _csignals_T_170)
node _csignals_T_172 = mux(_csignals_T_53, UInt<4>(0h0), _csignals_T_171)
node _csignals_T_173 = mux(_csignals_T_51, UInt<4>(0h0), _csignals_T_172)
node _csignals_T_174 = mux(_csignals_T_49, UInt<4>(0h0), _csignals_T_173)
node _csignals_T_175 = mux(_csignals_T_47, UInt<4>(0h0), _csignals_T_174)
node _csignals_T_176 = mux(_csignals_T_45, UInt<4>(0h0), _csignals_T_175)
node _csignals_T_177 = mux(_csignals_T_43, UInt<4>(0h0), _csignals_T_176)
node _csignals_T_178 = mux(_csignals_T_41, UInt<4>(0h0), _csignals_T_177)
node _csignals_T_179 = mux(_csignals_T_39, UInt<4>(0h0), _csignals_T_178)
node _csignals_T_180 = mux(_csignals_T_37, UInt<4>(0h0), _csignals_T_179)
node _csignals_T_181 = mux(_csignals_T_35, UInt<4>(0h0), _csignals_T_180)
node _csignals_T_182 = mux(_csignals_T_33, UInt<4>(0h0), _csignals_T_181)
node _csignals_T_183 = mux(_csignals_T_31, UInt<4>(0h0), _csignals_T_182)
node _csignals_T_184 = mux(_csignals_T_29, UInt<4>(0h0), _csignals_T_183)
node _csignals_T_185 = mux(_csignals_T_27, UInt<4>(0h0), _csignals_T_184)
node _csignals_T_186 = mux(_csignals_T_25, UInt<4>(0h0), _csignals_T_185)
node _csignals_T_187 = mux(_csignals_T_23, UInt<4>(0h0), _csignals_T_186)
node _csignals_T_188 = mux(_csignals_T_21, UInt<4>(0h0), _csignals_T_187)
node _csignals_T_189 = mux(_csignals_T_19, UInt<4>(0h0), _csignals_T_188)
node _csignals_T_190 = mux(_csignals_T_17, UInt<4>(0h0), _csignals_T_189)
node _csignals_T_191 = mux(_csignals_T_15, UInt<4>(0h0), _csignals_T_190)
node _csignals_T_192 = mux(_csignals_T_13, UInt<4>(0h0), _csignals_T_191)
node _csignals_T_193 = mux(_csignals_T_11, UInt<4>(0h0), _csignals_T_192)
node _csignals_T_194 = mux(_csignals_T_9, UInt<4>(0h0), _csignals_T_193)
node _csignals_T_195 = mux(_csignals_T_7, UInt<4>(0h0), _csignals_T_194)
node _csignals_T_196 = mux(_csignals_T_5, UInt<4>(0h0), _csignals_T_195)
node _csignals_T_197 = mux(_csignals_T_3, UInt<4>(0h0), _csignals_T_196)
node csignals_1 = mux(_csignals_T_1, UInt<4>(0h0), _csignals_T_197)
node _csignals_T_198 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_199 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_198)
node _csignals_T_200 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_199)
node _csignals_T_201 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_200)
node _csignals_T_202 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_201)
node _csignals_T_203 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_202)
node _csignals_T_204 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_203)
node _csignals_T_205 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_204)
node _csignals_T_206 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_205)
node _csignals_T_207 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_206)
node _csignals_T_208 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_207)
node _csignals_T_209 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_208)
node _csignals_T_210 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_209)
node _csignals_T_211 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_210)
node _csignals_T_212 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_211)
node _csignals_T_213 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_212)
node _csignals_T_214 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_213)
node _csignals_T_215 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_214)
node _csignals_T_216 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_215)
node _csignals_T_217 = mux(_csignals_T_61, UInt<1>(0h1), _csignals_T_216)
node _csignals_T_218 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_217)
node _csignals_T_219 = mux(_csignals_T_57, UInt<1>(0h0), _csignals_T_218)
node _csignals_T_220 = mux(_csignals_T_55, UInt<1>(0h0), _csignals_T_219)
node _csignals_T_221 = mux(_csignals_T_53, UInt<1>(0h0), _csignals_T_220)
node _csignals_T_222 = mux(_csignals_T_51, UInt<1>(0h0), _csignals_T_221)
node _csignals_T_223 = mux(_csignals_T_49, UInt<1>(0h0), _csignals_T_222)
node _csignals_T_224 = mux(_csignals_T_47, UInt<1>(0h0), _csignals_T_223)
node _csignals_T_225 = mux(_csignals_T_45, UInt<1>(0h0), _csignals_T_224)
node _csignals_T_226 = mux(_csignals_T_43, UInt<1>(0h0), _csignals_T_225)
node _csignals_T_227 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_226)
node _csignals_T_228 = mux(_csignals_T_39, UInt<1>(0h0), _csignals_T_227)
node _csignals_T_229 = mux(_csignals_T_37, UInt<1>(0h0), _csignals_T_228)
node _csignals_T_230 = mux(_csignals_T_35, UInt<1>(0h0), _csignals_T_229)
node _csignals_T_231 = mux(_csignals_T_33, UInt<1>(0h0), _csignals_T_230)
node _csignals_T_232 = mux(_csignals_T_31, UInt<1>(0h0), _csignals_T_231)
node _csignals_T_233 = mux(_csignals_T_29, UInt<1>(0h0), _csignals_T_232)
node _csignals_T_234 = mux(_csignals_T_27, UInt<1>(0h0), _csignals_T_233)
node _csignals_T_235 = mux(_csignals_T_25, UInt<1>(0h0), _csignals_T_234)
node _csignals_T_236 = mux(_csignals_T_23, UInt<1>(0h0), _csignals_T_235)
node _csignals_T_237 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_236)
node _csignals_T_238 = mux(_csignals_T_19, UInt<1>(0h0), _csignals_T_237)
node _csignals_T_239 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_238)
node _csignals_T_240 = mux(_csignals_T_15, UInt<1>(0h0), _csignals_T_239)
node _csignals_T_241 = mux(_csignals_T_13, UInt<1>(0h0), _csignals_T_240)
node _csignals_T_242 = mux(_csignals_T_11, UInt<1>(0h0), _csignals_T_241)
node _csignals_T_243 = mux(_csignals_T_9, UInt<1>(0h0), _csignals_T_242)
node _csignals_T_244 = mux(_csignals_T_7, UInt<1>(0h0), _csignals_T_243)
node _csignals_T_245 = mux(_csignals_T_5, UInt<1>(0h0), _csignals_T_244)
node _csignals_T_246 = mux(_csignals_T_3, UInt<1>(0h0), _csignals_T_245)
node csignals_2 = mux(_csignals_T_1, UInt<1>(0h0), _csignals_T_246)
node _csignals_T_247 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0))
node _csignals_T_248 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_247)
node _csignals_T_249 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_248)
node _csignals_T_250 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_249)
node _csignals_T_251 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_250)
node _csignals_T_252 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_251)
node _csignals_T_253 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_252)
node _csignals_T_254 = mux(_csignals_T_85, UInt<2>(0h2), _csignals_T_253)
node _csignals_T_255 = mux(_csignals_T_83, UInt<2>(0h0), _csignals_T_254)
node _csignals_T_256 = mux(_csignals_T_81, UInt<2>(0h0), _csignals_T_255)
node _csignals_T_257 = mux(_csignals_T_79, UInt<2>(0h0), _csignals_T_256)
node _csignals_T_258 = mux(_csignals_T_77, UInt<2>(0h2), _csignals_T_257)
node _csignals_T_259 = mux(_csignals_T_75, UInt<2>(0h2), _csignals_T_258)
node _csignals_T_260 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_259)
node _csignals_T_261 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_260)
node _csignals_T_262 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_261)
node _csignals_T_263 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_262)
node _csignals_T_264 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_263)
node _csignals_T_265 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_264)
node _csignals_T_266 = mux(_csignals_T_61, UInt<2>(0h0), _csignals_T_265)
node _csignals_T_267 = mux(_csignals_T_59, UInt<2>(0h0), _csignals_T_266)
node _csignals_T_268 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_267)
node _csignals_T_269 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_268)
node _csignals_T_270 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_269)
node _csignals_T_271 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_270)
node _csignals_T_272 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_271)
node _csignals_T_273 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_272)
node _csignals_T_274 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_273)
node _csignals_T_275 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_274)
node _csignals_T_276 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_275)
node _csignals_T_277 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_276)
node _csignals_T_278 = mux(_csignals_T_37, UInt<2>(0h0), _csignals_T_277)
node _csignals_T_279 = mux(_csignals_T_35, UInt<2>(0h0), _csignals_T_278)
node _csignals_T_280 = mux(_csignals_T_33, UInt<2>(0h0), _csignals_T_279)
node _csignals_T_281 = mux(_csignals_T_31, UInt<2>(0h0), _csignals_T_280)
node _csignals_T_282 = mux(_csignals_T_29, UInt<2>(0h0), _csignals_T_281)
node _csignals_T_283 = mux(_csignals_T_27, UInt<2>(0h0), _csignals_T_282)
node _csignals_T_284 = mux(_csignals_T_25, UInt<2>(0h0), _csignals_T_283)
node _csignals_T_285 = mux(_csignals_T_23, UInt<2>(0h0), _csignals_T_284)
node _csignals_T_286 = mux(_csignals_T_21, UInt<2>(0h0), _csignals_T_285)
node _csignals_T_287 = mux(_csignals_T_19, UInt<2>(0h1), _csignals_T_286)
node _csignals_T_288 = mux(_csignals_T_17, UInt<2>(0h1), _csignals_T_287)
node _csignals_T_289 = mux(_csignals_T_15, UInt<2>(0h0), _csignals_T_288)
node _csignals_T_290 = mux(_csignals_T_13, UInt<2>(0h0), _csignals_T_289)
node _csignals_T_291 = mux(_csignals_T_11, UInt<2>(0h0), _csignals_T_290)
node _csignals_T_292 = mux(_csignals_T_9, UInt<2>(0h0), _csignals_T_291)
node _csignals_T_293 = mux(_csignals_T_7, UInt<2>(0h0), _csignals_T_292)
node _csignals_T_294 = mux(_csignals_T_5, UInt<2>(0h0), _csignals_T_293)
node _csignals_T_295 = mux(_csignals_T_3, UInt<2>(0h0), _csignals_T_294)
node csignals_3 = mux(_csignals_T_1, UInt<2>(0h0), _csignals_T_295)
node _csignals_T_296 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0))
node _csignals_T_297 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_296)
node _csignals_T_298 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_297)
node _csignals_T_299 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_298)
node _csignals_T_300 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_299)
node _csignals_T_301 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_300)
node _csignals_T_302 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_301)
node _csignals_T_303 = mux(_csignals_T_85, UInt<2>(0h0), _csignals_T_302)
node _csignals_T_304 = mux(_csignals_T_83, UInt<2>(0h0), _csignals_T_303)
node _csignals_T_305 = mux(_csignals_T_81, UInt<2>(0h0), _csignals_T_304)
node _csignals_T_306 = mux(_csignals_T_79, UInt<2>(0h0), _csignals_T_305)
node _csignals_T_307 = mux(_csignals_T_77, UInt<2>(0h0), _csignals_T_306)
node _csignals_T_308 = mux(_csignals_T_75, UInt<2>(0h0), _csignals_T_307)
node _csignals_T_309 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_308)
node _csignals_T_310 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_309)
node _csignals_T_311 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_310)
node _csignals_T_312 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_311)
node _csignals_T_313 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_312)
node _csignals_T_314 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_313)
node _csignals_T_315 = mux(_csignals_T_61, UInt<2>(0h1), _csignals_T_314)
node _csignals_T_316 = mux(_csignals_T_59, UInt<2>(0h0), _csignals_T_315)
node _csignals_T_317 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_316)
node _csignals_T_318 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_317)
node _csignals_T_319 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_318)
node _csignals_T_320 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_319)
node _csignals_T_321 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_320)
node _csignals_T_322 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_321)
node _csignals_T_323 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_322)
node _csignals_T_324 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_323)
node _csignals_T_325 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_324)
node _csignals_T_326 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_325)
node _csignals_T_327 = mux(_csignals_T_37, UInt<2>(0h1), _csignals_T_326)
node _csignals_T_328 = mux(_csignals_T_35, UInt<2>(0h1), _csignals_T_327)
node _csignals_T_329 = mux(_csignals_T_33, UInt<2>(0h1), _csignals_T_328)
node _csignals_T_330 = mux(_csignals_T_31, UInt<2>(0h1), _csignals_T_329)
node _csignals_T_331 = mux(_csignals_T_29, UInt<2>(0h1), _csignals_T_330)
node _csignals_T_332 = mux(_csignals_T_27, UInt<2>(0h1), _csignals_T_331)
node _csignals_T_333 = mux(_csignals_T_25, UInt<2>(0h1), _csignals_T_332)
node _csignals_T_334 = mux(_csignals_T_23, UInt<2>(0h1), _csignals_T_333)
node _csignals_T_335 = mux(_csignals_T_21, UInt<2>(0h1), _csignals_T_334)
node _csignals_T_336 = mux(_csignals_T_19, UInt<2>(0h0), _csignals_T_335)
node _csignals_T_337 = mux(_csignals_T_17, UInt<2>(0h3), _csignals_T_336)
node _csignals_T_338 = mux(_csignals_T_15, UInt<2>(0h2), _csignals_T_337)
node _csignals_T_339 = mux(_csignals_T_13, UInt<2>(0h2), _csignals_T_338)
node _csignals_T_340 = mux(_csignals_T_11, UInt<2>(0h2), _csignals_T_339)
node _csignals_T_341 = mux(_csignals_T_9, UInt<2>(0h1), _csignals_T_340)
node _csignals_T_342 = mux(_csignals_T_7, UInt<2>(0h1), _csignals_T_341)
node _csignals_T_343 = mux(_csignals_T_5, UInt<2>(0h1), _csignals_T_342)
node _csignals_T_344 = mux(_csignals_T_3, UInt<2>(0h1), _csignals_T_343)
node csignals_4 = mux(_csignals_T_1, UInt<2>(0h1), _csignals_T_344)
node _csignals_T_345 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_346 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_345)
node _csignals_T_347 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_346)
node _csignals_T_348 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_347)
node _csignals_T_349 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_348)
node _csignals_T_350 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_349)
node _csignals_T_351 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_350)
node _csignals_T_352 = mux(_csignals_T_85, UInt<4>(0h8), _csignals_T_351)
node _csignals_T_353 = mux(_csignals_T_83, UInt<4>(0h8), _csignals_T_352)
node _csignals_T_354 = mux(_csignals_T_81, UInt<4>(0h8), _csignals_T_353)
node _csignals_T_355 = mux(_csignals_T_79, UInt<4>(0h8), _csignals_T_354)
node _csignals_T_356 = mux(_csignals_T_77, UInt<4>(0h8), _csignals_T_355)
node _csignals_T_357 = mux(_csignals_T_75, UInt<4>(0h8), _csignals_T_356)
node _csignals_T_358 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_357)
node _csignals_T_359 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_358)
node _csignals_T_360 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_359)
node _csignals_T_361 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_360)
node _csignals_T_362 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_361)
node _csignals_T_363 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_362)
node _csignals_T_364 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_363)
node _csignals_T_365 = mux(_csignals_T_59, UInt<1>(0h0), _csignals_T_364)
node _csignals_T_366 = mux(_csignals_T_57, UInt<3>(0h5), _csignals_T_365)
node _csignals_T_367 = mux(_csignals_T_55, UInt<4>(0hb), _csignals_T_366)
node _csignals_T_368 = mux(_csignals_T_53, UInt<3>(0h4), _csignals_T_367)
node _csignals_T_369 = mux(_csignals_T_51, UInt<3>(0h6), _csignals_T_368)
node _csignals_T_370 = mux(_csignals_T_49, UInt<3>(0h7), _csignals_T_369)
node _csignals_T_371 = mux(_csignals_T_47, UInt<4>(0he), _csignals_T_370)
node _csignals_T_372 = mux(_csignals_T_45, UInt<4>(0hc), _csignals_T_371)
node _csignals_T_373 = mux(_csignals_T_43, UInt<4>(0ha), _csignals_T_372)
node _csignals_T_374 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_373)
node _csignals_T_375 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_374)
node _csignals_T_376 = mux(_csignals_T_37, UInt<3>(0h5), _csignals_T_375)
node _csignals_T_377 = mux(_csignals_T_35, UInt<4>(0hb), _csignals_T_376)
node _csignals_T_378 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_377)
node _csignals_T_379 = mux(_csignals_T_31, UInt<4>(0he), _csignals_T_378)
node _csignals_T_380 = mux(_csignals_T_29, UInt<4>(0hc), _csignals_T_379)
node _csignals_T_381 = mux(_csignals_T_27, UInt<3>(0h4), _csignals_T_380)
node _csignals_T_382 = mux(_csignals_T_25, UInt<3>(0h6), _csignals_T_381)
node _csignals_T_383 = mux(_csignals_T_23, UInt<3>(0h7), _csignals_T_382)
node _csignals_T_384 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_383)
node _csignals_T_385 = mux(_csignals_T_19, UInt<4>(0h8), _csignals_T_384)
node _csignals_T_386 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_385)
node _csignals_T_387 = mux(_csignals_T_15, UInt<1>(0h0), _csignals_T_386)
node _csignals_T_388 = mux(_csignals_T_13, UInt<1>(0h0), _csignals_T_387)
node _csignals_T_389 = mux(_csignals_T_11, UInt<1>(0h0), _csignals_T_388)
node _csignals_T_390 = mux(_csignals_T_9, UInt<1>(0h0), _csignals_T_389)
node _csignals_T_391 = mux(_csignals_T_7, UInt<1>(0h0), _csignals_T_390)
node _csignals_T_392 = mux(_csignals_T_5, UInt<1>(0h0), _csignals_T_391)
node _csignals_T_393 = mux(_csignals_T_3, UInt<1>(0h0), _csignals_T_392)
node csignals_5 = mux(_csignals_T_1, UInt<1>(0h0), _csignals_T_393)
node _csignals_T_394 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0))
node _csignals_T_395 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_394)
node _csignals_T_396 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_395)
node _csignals_T_397 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_396)
node _csignals_T_398 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_397)
node _csignals_T_399 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_398)
node _csignals_T_400 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_399)
node _csignals_T_401 = mux(_csignals_T_85, UInt<2>(0h3), _csignals_T_400)
node _csignals_T_402 = mux(_csignals_T_83, UInt<2>(0h3), _csignals_T_401)
node _csignals_T_403 = mux(_csignals_T_81, UInt<2>(0h3), _csignals_T_402)
node _csignals_T_404 = mux(_csignals_T_79, UInt<2>(0h3), _csignals_T_403)
node _csignals_T_405 = mux(_csignals_T_77, UInt<2>(0h3), _csignals_T_404)
node _csignals_T_406 = mux(_csignals_T_75, UInt<2>(0h3), _csignals_T_405)
node _csignals_T_407 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_406)
node _csignals_T_408 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_407)
node _csignals_T_409 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_408)
node _csignals_T_410 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_409)
node _csignals_T_411 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_410)
node _csignals_T_412 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_411)
node _csignals_T_413 = mux(_csignals_T_61, UInt<2>(0h2), _csignals_T_412)
node _csignals_T_414 = mux(_csignals_T_59, UInt<2>(0h2), _csignals_T_413)
node _csignals_T_415 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_414)
node _csignals_T_416 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_415)
node _csignals_T_417 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_416)
node _csignals_T_418 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_417)
node _csignals_T_419 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_418)
node _csignals_T_420 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_419)
node _csignals_T_421 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_420)
node _csignals_T_422 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_421)
node _csignals_T_423 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_422)
node _csignals_T_424 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_423)
node _csignals_T_425 = mux(_csignals_T_37, UInt<2>(0h0), _csignals_T_424)
node _csignals_T_426 = mux(_csignals_T_35, UInt<2>(0h0), _csignals_T_425)
node _csignals_T_427 = mux(_csignals_T_33, UInt<2>(0h0), _csignals_T_426)
node _csignals_T_428 = mux(_csignals_T_31, UInt<2>(0h0), _csignals_T_427)
node _csignals_T_429 = mux(_csignals_T_29, UInt<2>(0h0), _csignals_T_428)
node _csignals_T_430 = mux(_csignals_T_27, UInt<2>(0h0), _csignals_T_429)
node _csignals_T_431 = mux(_csignals_T_25, UInt<2>(0h0), _csignals_T_430)
node _csignals_T_432 = mux(_csignals_T_23, UInt<2>(0h0), _csignals_T_431)
node _csignals_T_433 = mux(_csignals_T_21, UInt<2>(0h0), _csignals_T_432)
node _csignals_T_434 = mux(_csignals_T_19, UInt<2>(0h0), _csignals_T_433)
node _csignals_T_435 = mux(_csignals_T_17, UInt<2>(0h0), _csignals_T_434)
node _csignals_T_436 = mux(_csignals_T_15, UInt<2>(0h0), _csignals_T_435)
node _csignals_T_437 = mux(_csignals_T_13, UInt<2>(0h0), _csignals_T_436)
node _csignals_T_438 = mux(_csignals_T_11, UInt<2>(0h0), _csignals_T_437)
node _csignals_T_439 = mux(_csignals_T_9, UInt<2>(0h1), _csignals_T_438)
node _csignals_T_440 = mux(_csignals_T_7, UInt<2>(0h1), _csignals_T_439)
node _csignals_T_441 = mux(_csignals_T_5, UInt<2>(0h1), _csignals_T_440)
node _csignals_T_442 = mux(_csignals_T_3, UInt<2>(0h1), _csignals_T_441)
node csignals_6 = mux(_csignals_T_1, UInt<2>(0h1), _csignals_T_442)
node _csignals_T_443 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_444 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_443)
node _csignals_T_445 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_444)
node _csignals_T_446 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_445)
node _csignals_T_447 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_446)
node _csignals_T_448 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_447)
node _csignals_T_449 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_448)
node _csignals_T_450 = mux(_csignals_T_85, UInt<1>(0h1), _csignals_T_449)
node _csignals_T_451 = mux(_csignals_T_83, UInt<1>(0h1), _csignals_T_450)
node _csignals_T_452 = mux(_csignals_T_81, UInt<1>(0h1), _csignals_T_451)
node _csignals_T_453 = mux(_csignals_T_79, UInt<1>(0h1), _csignals_T_452)
node _csignals_T_454 = mux(_csignals_T_77, UInt<1>(0h1), _csignals_T_453)
node _csignals_T_455 = mux(_csignals_T_75, UInt<1>(0h1), _csignals_T_454)
node _csignals_T_456 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_455)
node _csignals_T_457 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_456)
node _csignals_T_458 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_457)
node _csignals_T_459 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_458)
node _csignals_T_460 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_459)
node _csignals_T_461 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_460)
node _csignals_T_462 = mux(_csignals_T_61, UInt<1>(0h1), _csignals_T_461)
node _csignals_T_463 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_462)
node _csignals_T_464 = mux(_csignals_T_57, UInt<1>(0h1), _csignals_T_463)
node _csignals_T_465 = mux(_csignals_T_55, UInt<1>(0h1), _csignals_T_464)
node _csignals_T_466 = mux(_csignals_T_53, UInt<1>(0h1), _csignals_T_465)
node _csignals_T_467 = mux(_csignals_T_51, UInt<1>(0h1), _csignals_T_466)
node _csignals_T_468 = mux(_csignals_T_49, UInt<1>(0h1), _csignals_T_467)
node _csignals_T_469 = mux(_csignals_T_47, UInt<1>(0h1), _csignals_T_468)
node _csignals_T_470 = mux(_csignals_T_45, UInt<1>(0h1), _csignals_T_469)
node _csignals_T_471 = mux(_csignals_T_43, UInt<1>(0h1), _csignals_T_470)
node _csignals_T_472 = mux(_csignals_T_41, UInt<1>(0h1), _csignals_T_471)
node _csignals_T_473 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_472)
node _csignals_T_474 = mux(_csignals_T_37, UInt<1>(0h1), _csignals_T_473)
node _csignals_T_475 = mux(_csignals_T_35, UInt<1>(0h1), _csignals_T_474)
node _csignals_T_476 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_475)
node _csignals_T_477 = mux(_csignals_T_31, UInt<1>(0h1), _csignals_T_476)
node _csignals_T_478 = mux(_csignals_T_29, UInt<1>(0h1), _csignals_T_477)
node _csignals_T_479 = mux(_csignals_T_27, UInt<1>(0h1), _csignals_T_478)
node _csignals_T_480 = mux(_csignals_T_25, UInt<1>(0h1), _csignals_T_479)
node _csignals_T_481 = mux(_csignals_T_23, UInt<1>(0h1), _csignals_T_480)
node _csignals_T_482 = mux(_csignals_T_21, UInt<1>(0h1), _csignals_T_481)
node _csignals_T_483 = mux(_csignals_T_19, UInt<1>(0h1), _csignals_T_482)
node _csignals_T_484 = mux(_csignals_T_17, UInt<1>(0h1), _csignals_T_483)
node _csignals_T_485 = mux(_csignals_T_15, UInt<1>(0h0), _csignals_T_484)
node _csignals_T_486 = mux(_csignals_T_13, UInt<1>(0h0), _csignals_T_485)
node _csignals_T_487 = mux(_csignals_T_11, UInt<1>(0h0), _csignals_T_486)
node _csignals_T_488 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_487)
node _csignals_T_489 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_488)
node _csignals_T_490 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_489)
node _csignals_T_491 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_490)
node csignals_7 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_491)
node _csignals_T_492 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_493 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_492)
node _csignals_T_494 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_493)
node _csignals_T_495 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_494)
node _csignals_T_496 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_495)
node _csignals_T_497 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_496)
node _csignals_T_498 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_497)
node _csignals_T_499 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_498)
node _csignals_T_500 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_499)
node _csignals_T_501 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_500)
node _csignals_T_502 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_501)
node _csignals_T_503 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_502)
node _csignals_T_504 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_503)
node _csignals_T_505 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_504)
node _csignals_T_506 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_505)
node _csignals_T_507 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_506)
node _csignals_T_508 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_507)
node _csignals_T_509 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_508)
node _csignals_T_510 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_509)
node _csignals_T_511 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_510)
node _csignals_T_512 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_511)
node _csignals_T_513 = mux(_csignals_T_57, UInt<1>(0h1), _csignals_T_512)
node _csignals_T_514 = mux(_csignals_T_55, UInt<1>(0h1), _csignals_T_513)
node _csignals_T_515 = mux(_csignals_T_53, UInt<1>(0h1), _csignals_T_514)
node _csignals_T_516 = mux(_csignals_T_51, UInt<1>(0h1), _csignals_T_515)
node _csignals_T_517 = mux(_csignals_T_49, UInt<1>(0h1), _csignals_T_516)
node _csignals_T_518 = mux(_csignals_T_47, UInt<1>(0h1), _csignals_T_517)
node _csignals_T_519 = mux(_csignals_T_45, UInt<1>(0h1), _csignals_T_518)
node _csignals_T_520 = mux(_csignals_T_43, UInt<1>(0h1), _csignals_T_519)
node _csignals_T_521 = mux(_csignals_T_41, UInt<1>(0h1), _csignals_T_520)
node _csignals_T_522 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_521)
node _csignals_T_523 = mux(_csignals_T_37, UInt<1>(0h1), _csignals_T_522)
node _csignals_T_524 = mux(_csignals_T_35, UInt<1>(0h1), _csignals_T_523)
node _csignals_T_525 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_524)
node _csignals_T_526 = mux(_csignals_T_31, UInt<1>(0h1), _csignals_T_525)
node _csignals_T_527 = mux(_csignals_T_29, UInt<1>(0h1), _csignals_T_526)
node _csignals_T_528 = mux(_csignals_T_27, UInt<1>(0h1), _csignals_T_527)
node _csignals_T_529 = mux(_csignals_T_25, UInt<1>(0h1), _csignals_T_528)
node _csignals_T_530 = mux(_csignals_T_23, UInt<1>(0h1), _csignals_T_529)
node _csignals_T_531 = mux(_csignals_T_21, UInt<1>(0h1), _csignals_T_530)
node _csignals_T_532 = mux(_csignals_T_19, UInt<1>(0h1), _csignals_T_531)
node _csignals_T_533 = mux(_csignals_T_17, UInt<1>(0h1), _csignals_T_532)
node _csignals_T_534 = mux(_csignals_T_15, UInt<1>(0h0), _csignals_T_533)
node _csignals_T_535 = mux(_csignals_T_13, UInt<1>(0h0), _csignals_T_534)
node _csignals_T_536 = mux(_csignals_T_11, UInt<1>(0h0), _csignals_T_535)
node _csignals_T_537 = mux(_csignals_T_9, UInt<1>(0h0), _csignals_T_536)
node _csignals_T_538 = mux(_csignals_T_7, UInt<1>(0h0), _csignals_T_537)
node _csignals_T_539 = mux(_csignals_T_5, UInt<1>(0h0), _csignals_T_538)
node _csignals_T_540 = mux(_csignals_T_3, UInt<1>(0h0), _csignals_T_539)
node csignals_8 = mux(_csignals_T_1, UInt<1>(0h0), _csignals_T_540)
node _csignals_T_541 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_542 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_541)
node _csignals_T_543 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_542)
node _csignals_T_544 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_543)
node _csignals_T_545 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_544)
node _csignals_T_546 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_545)
node _csignals_T_547 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_546)
node _csignals_T_548 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_547)
node _csignals_T_549 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_548)
node _csignals_T_550 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_549)
node _csignals_T_551 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_550)
node _csignals_T_552 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_551)
node _csignals_T_553 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_552)
node _csignals_T_554 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_553)
node _csignals_T_555 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_554)
node _csignals_T_556 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_555)
node _csignals_T_557 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_556)
node _csignals_T_558 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_557)
node _csignals_T_559 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_558)
node _csignals_T_560 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_559)
node _csignals_T_561 = mux(_csignals_T_59, UInt<1>(0h0), _csignals_T_560)
node _csignals_T_562 = mux(_csignals_T_57, UInt<1>(0h0), _csignals_T_561)
node _csignals_T_563 = mux(_csignals_T_55, UInt<1>(0h0), _csignals_T_562)
node _csignals_T_564 = mux(_csignals_T_53, UInt<1>(0h0), _csignals_T_563)
node _csignals_T_565 = mux(_csignals_T_51, UInt<1>(0h0), _csignals_T_564)
node _csignals_T_566 = mux(_csignals_T_49, UInt<1>(0h0), _csignals_T_565)
node _csignals_T_567 = mux(_csignals_T_47, UInt<1>(0h0), _csignals_T_566)
node _csignals_T_568 = mux(_csignals_T_45, UInt<1>(0h0), _csignals_T_567)
node _csignals_T_569 = mux(_csignals_T_43, UInt<1>(0h0), _csignals_T_568)
node _csignals_T_570 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_569)
node _csignals_T_571 = mux(_csignals_T_39, UInt<1>(0h0), _csignals_T_570)
node _csignals_T_572 = mux(_csignals_T_37, UInt<1>(0h0), _csignals_T_571)
node _csignals_T_573 = mux(_csignals_T_35, UInt<1>(0h0), _csignals_T_572)
node _csignals_T_574 = mux(_csignals_T_33, UInt<1>(0h0), _csignals_T_573)
node _csignals_T_575 = mux(_csignals_T_31, UInt<1>(0h0), _csignals_T_574)
node _csignals_T_576 = mux(_csignals_T_29, UInt<1>(0h0), _csignals_T_575)
node _csignals_T_577 = mux(_csignals_T_27, UInt<1>(0h0), _csignals_T_576)
node _csignals_T_578 = mux(_csignals_T_25, UInt<1>(0h0), _csignals_T_577)
node _csignals_T_579 = mux(_csignals_T_23, UInt<1>(0h0), _csignals_T_578)
node _csignals_T_580 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_579)
node _csignals_T_581 = mux(_csignals_T_19, UInt<1>(0h0), _csignals_T_580)
node _csignals_T_582 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_581)
node _csignals_T_583 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_582)
node _csignals_T_584 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_583)
node _csignals_T_585 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_584)
node _csignals_T_586 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_585)
node _csignals_T_587 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_586)
node _csignals_T_588 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_587)
node _csignals_T_589 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_588)
node csignals_9 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_589)
node _csignals_T_590 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0))
node _csignals_T_591 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_590)
node _csignals_T_592 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_591)
node _csignals_T_593 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_592)
node _csignals_T_594 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_593)
node _csignals_T_595 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_594)
node _csignals_T_596 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_595)
node _csignals_T_597 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_596)
node _csignals_T_598 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_597)
node _csignals_T_599 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_598)
node _csignals_T_600 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_599)
node _csignals_T_601 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_600)
node _csignals_T_602 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_601)
node _csignals_T_603 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_602)
node _csignals_T_604 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_603)
node _csignals_T_605 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_604)
node _csignals_T_606 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_605)
node _csignals_T_607 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_606)
node _csignals_T_608 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_607)
node _csignals_T_609 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_608)
node _csignals_T_610 = mux(_csignals_T_59, UInt<1>(0h0), _csignals_T_609)
node _csignals_T_611 = mux(_csignals_T_57, UInt<1>(0h0), _csignals_T_610)
node _csignals_T_612 = mux(_csignals_T_55, UInt<1>(0h0), _csignals_T_611)
node _csignals_T_613 = mux(_csignals_T_53, UInt<1>(0h0), _csignals_T_612)
node _csignals_T_614 = mux(_csignals_T_51, UInt<1>(0h0), _csignals_T_613)
node _csignals_T_615 = mux(_csignals_T_49, UInt<1>(0h0), _csignals_T_614)
node _csignals_T_616 = mux(_csignals_T_47, UInt<1>(0h0), _csignals_T_615)
node _csignals_T_617 = mux(_csignals_T_45, UInt<1>(0h0), _csignals_T_616)
node _csignals_T_618 = mux(_csignals_T_43, UInt<1>(0h0), _csignals_T_617)
node _csignals_T_619 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_618)
node _csignals_T_620 = mux(_csignals_T_39, UInt<1>(0h0), _csignals_T_619)
node _csignals_T_621 = mux(_csignals_T_37, UInt<1>(0h0), _csignals_T_620)
node _csignals_T_622 = mux(_csignals_T_35, UInt<1>(0h0), _csignals_T_621)
node _csignals_T_623 = mux(_csignals_T_33, UInt<1>(0h0), _csignals_T_622)
node _csignals_T_624 = mux(_csignals_T_31, UInt<1>(0h0), _csignals_T_623)
node _csignals_T_625 = mux(_csignals_T_29, UInt<1>(0h0), _csignals_T_624)
node _csignals_T_626 = mux(_csignals_T_27, UInt<1>(0h0), _csignals_T_625)
node _csignals_T_627 = mux(_csignals_T_25, UInt<1>(0h0), _csignals_T_626)
node _csignals_T_628 = mux(_csignals_T_23, UInt<1>(0h0), _csignals_T_627)
node _csignals_T_629 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_628)
node _csignals_T_630 = mux(_csignals_T_19, UInt<1>(0h0), _csignals_T_629)
node _csignals_T_631 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_630)
node _csignals_T_632 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_631)
node _csignals_T_633 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_632)
node _csignals_T_634 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_633)
node _csignals_T_635 = mux(_csignals_T_9, UInt<1>(0h0), _csignals_T_634)
node _csignals_T_636 = mux(_csignals_T_7, UInt<1>(0h0), _csignals_T_635)
node _csignals_T_637 = mux(_csignals_T_5, UInt<1>(0h0), _csignals_T_636)
node _csignals_T_638 = mux(_csignals_T_3, UInt<1>(0h0), _csignals_T_637)
node csignals_10 = mux(_csignals_T_1, UInt<1>(0h0), _csignals_T_638)
node _csignals_T_639 = mux(_csignals_T_99, UInt<3>(0h0), UInt<3>(0h0))
node _csignals_T_640 = mux(_csignals_T_97, UInt<3>(0h0), _csignals_T_639)
node _csignals_T_641 = mux(_csignals_T_95, UInt<3>(0h0), _csignals_T_640)
node _csignals_T_642 = mux(_csignals_T_93, UInt<3>(0h0), _csignals_T_641)
node _csignals_T_643 = mux(_csignals_T_91, UInt<3>(0h0), _csignals_T_642)
node _csignals_T_644 = mux(_csignals_T_89, UInt<3>(0h0), _csignals_T_643)
node _csignals_T_645 = mux(_csignals_T_87, UInt<3>(0h0), _csignals_T_644)
node _csignals_T_646 = mux(_csignals_T_85, UInt<3>(0h0), _csignals_T_645)
node _csignals_T_647 = mux(_csignals_T_83, UInt<3>(0h0), _csignals_T_646)
node _csignals_T_648 = mux(_csignals_T_81, UInt<3>(0h0), _csignals_T_647)
node _csignals_T_649 = mux(_csignals_T_79, UInt<3>(0h0), _csignals_T_648)
node _csignals_T_650 = mux(_csignals_T_77, UInt<3>(0h0), _csignals_T_649)
node _csignals_T_651 = mux(_csignals_T_75, UInt<3>(0h0), _csignals_T_650)
node _csignals_T_652 = mux(_csignals_T_73, UInt<3>(0h0), _csignals_T_651)
node _csignals_T_653 = mux(_csignals_T_71, UInt<3>(0h0), _csignals_T_652)
node _csignals_T_654 = mux(_csignals_T_69, UInt<3>(0h0), _csignals_T_653)
node _csignals_T_655 = mux(_csignals_T_67, UInt<3>(0h0), _csignals_T_654)
node _csignals_T_656 = mux(_csignals_T_65, UInt<3>(0h0), _csignals_T_655)
node _csignals_T_657 = mux(_csignals_T_63, UInt<3>(0h0), _csignals_T_656)
node _csignals_T_658 = mux(_csignals_T_61, UInt<3>(0h0), _csignals_T_657)
node _csignals_T_659 = mux(_csignals_T_59, UInt<3>(0h0), _csignals_T_658)
node _csignals_T_660 = mux(_csignals_T_57, UInt<3>(0h0), _csignals_T_659)
node _csignals_T_661 = mux(_csignals_T_55, UInt<3>(0h0), _csignals_T_660)
node _csignals_T_662 = mux(_csignals_T_53, UInt<3>(0h0), _csignals_T_661)
node _csignals_T_663 = mux(_csignals_T_51, UInt<3>(0h0), _csignals_T_662)
node _csignals_T_664 = mux(_csignals_T_49, UInt<3>(0h0), _csignals_T_663)
node _csignals_T_665 = mux(_csignals_T_47, UInt<3>(0h0), _csignals_T_664)
node _csignals_T_666 = mux(_csignals_T_45, UInt<3>(0h0), _csignals_T_665)
node _csignals_T_667 = mux(_csignals_T_43, UInt<3>(0h0), _csignals_T_666)
node _csignals_T_668 = mux(_csignals_T_41, UInt<3>(0h0), _csignals_T_667)
node _csignals_T_669 = mux(_csignals_T_39, UInt<3>(0h0), _csignals_T_668)
node _csignals_T_670 = mux(_csignals_T_37, UInt<3>(0h0), _csignals_T_669)
node _csignals_T_671 = mux(_csignals_T_35, UInt<3>(0h0), _csignals_T_670)
node _csignals_T_672 = mux(_csignals_T_33, UInt<3>(0h0), _csignals_T_671)
node _csignals_T_673 = mux(_csignals_T_31, UInt<3>(0h0), _csignals_T_672)
node _csignals_T_674 = mux(_csignals_T_29, UInt<3>(0h0), _csignals_T_673)
node _csignals_T_675 = mux(_csignals_T_27, UInt<3>(0h0), _csignals_T_674)
node _csignals_T_676 = mux(_csignals_T_25, UInt<3>(0h0), _csignals_T_675)
node _csignals_T_677 = mux(_csignals_T_23, UInt<3>(0h0), _csignals_T_676)
node _csignals_T_678 = mux(_csignals_T_21, UInt<3>(0h0), _csignals_T_677)
node _csignals_T_679 = mux(_csignals_T_19, UInt<3>(0h0), _csignals_T_678)
node _csignals_T_680 = mux(_csignals_T_17, UInt<3>(0h0), _csignals_T_679)
node _csignals_T_681 = mux(_csignals_T_15, UInt<3>(0h2), _csignals_T_680)
node _csignals_T_682 = mux(_csignals_T_13, UInt<3>(0h1), _csignals_T_681)
node _csignals_T_683 = mux(_csignals_T_11, UInt<3>(0h3), _csignals_T_682)
node _csignals_T_684 = mux(_csignals_T_9, UInt<3>(0h6), _csignals_T_683)
node _csignals_T_685 = mux(_csignals_T_7, UInt<3>(0h2), _csignals_T_684)
node _csignals_T_686 = mux(_csignals_T_5, UInt<3>(0h5), _csignals_T_685)
node _csignals_T_687 = mux(_csignals_T_3, UInt<3>(0h1), _csignals_T_686)
node csignals_11 = mux(_csignals_T_1, UInt<3>(0h3), _csignals_T_687)
node _csignals_T_688 = mux(_csignals_T_99, UInt<3>(0h0), UInt<3>(0h0))
node _csignals_T_689 = mux(_csignals_T_97, UInt<3>(0h0), _csignals_T_688)
node _csignals_T_690 = mux(_csignals_T_95, UInt<3>(0h4), _csignals_T_689)
node _csignals_T_691 = mux(_csignals_T_93, UInt<3>(0h4), _csignals_T_690)
node _csignals_T_692 = mux(_csignals_T_91, UInt<3>(0h4), _csignals_T_691)
node _csignals_T_693 = mux(_csignals_T_89, UInt<3>(0h4), _csignals_T_692)
node _csignals_T_694 = mux(_csignals_T_87, UInt<3>(0h4), _csignals_T_693)
node _csignals_T_695 = mux(_csignals_T_85, UInt<3>(0h7), _csignals_T_694)
node _csignals_T_696 = mux(_csignals_T_83, UInt<3>(0h7), _csignals_T_695)
node _csignals_T_697 = mux(_csignals_T_81, UInt<3>(0h6), _csignals_T_696)
node _csignals_T_698 = mux(_csignals_T_79, UInt<3>(0h5), _csignals_T_697)
node _csignals_T_699 = mux(_csignals_T_77, UInt<3>(0h6), _csignals_T_698)
node _csignals_T_700 = mux(_csignals_T_75, UInt<3>(0h5), _csignals_T_699)
node _csignals_T_701 = mux(_csignals_T_73, UInt<3>(0h0), _csignals_T_700)
node _csignals_T_702 = mux(_csignals_T_71, UInt<3>(0h0), _csignals_T_701)
node _csignals_T_703 = mux(_csignals_T_69, UInt<3>(0h0), _csignals_T_702)
node _csignals_T_704 = mux(_csignals_T_67, UInt<3>(0h0), _csignals_T_703)
node _csignals_T_705 = mux(_csignals_T_65, UInt<3>(0h0), _csignals_T_704)
node _csignals_T_706 = mux(_csignals_T_63, UInt<3>(0h0), _csignals_T_705)
node _csignals_T_707 = mux(_csignals_T_61, UInt<3>(0h0), _csignals_T_706)
node _csignals_T_708 = mux(_csignals_T_59, UInt<3>(0h0), _csignals_T_707)
node _csignals_T_709 = mux(_csignals_T_57, UInt<3>(0h0), _csignals_T_708)
node _csignals_T_710 = mux(_csignals_T_55, UInt<3>(0h0), _csignals_T_709)
node _csignals_T_711 = mux(_csignals_T_53, UInt<3>(0h0), _csignals_T_710)
node _csignals_T_712 = mux(_csignals_T_51, UInt<3>(0h0), _csignals_T_711)
node _csignals_T_713 = mux(_csignals_T_49, UInt<3>(0h0), _csignals_T_712)
node _csignals_T_714 = mux(_csignals_T_47, UInt<3>(0h0), _csignals_T_713)
node _csignals_T_715 = mux(_csignals_T_45, UInt<3>(0h0), _csignals_T_714)
node _csignals_T_716 = mux(_csignals_T_43, UInt<3>(0h0), _csignals_T_715)
node _csignals_T_717 = mux(_csignals_T_41, UInt<3>(0h0), _csignals_T_716)
node _csignals_T_718 = mux(_csignals_T_39, UInt<3>(0h0), _csignals_T_717)
node _csignals_T_719 = mux(_csignals_T_37, UInt<3>(0h0), _csignals_T_718)
node _csignals_T_720 = mux(_csignals_T_35, UInt<3>(0h0), _csignals_T_719)
node _csignals_T_721 = mux(_csignals_T_33, UInt<3>(0h0), _csignals_T_720)
node _csignals_T_722 = mux(_csignals_T_31, UInt<3>(0h0), _csignals_T_721)
node _csignals_T_723 = mux(_csignals_T_29, UInt<3>(0h0), _csignals_T_722)
node _csignals_T_724 = mux(_csignals_T_27, UInt<3>(0h0), _csignals_T_723)
node _csignals_T_725 = mux(_csignals_T_25, UInt<3>(0h0), _csignals_T_724)
node _csignals_T_726 = mux(_csignals_T_23, UInt<3>(0h0), _csignals_T_725)
node _csignals_T_727 = mux(_csignals_T_21, UInt<3>(0h0), _csignals_T_726)
node _csignals_T_728 = mux(_csignals_T_19, UInt<3>(0h0), _csignals_T_727)
node _csignals_T_729 = mux(_csignals_T_17, UInt<3>(0h0), _csignals_T_728)
node _csignals_T_730 = mux(_csignals_T_15, UInt<3>(0h0), _csignals_T_729)
node _csignals_T_731 = mux(_csignals_T_13, UInt<3>(0h0), _csignals_T_730)
node _csignals_T_732 = mux(_csignals_T_11, UInt<3>(0h0), _csignals_T_731)
node _csignals_T_733 = mux(_csignals_T_9, UInt<3>(0h0), _csignals_T_732)
node _csignals_T_734 = mux(_csignals_T_7, UInt<3>(0h0), _csignals_T_733)
node _csignals_T_735 = mux(_csignals_T_5, UInt<3>(0h0), _csignals_T_734)
node _csignals_T_736 = mux(_csignals_T_3, UInt<3>(0h0), _csignals_T_735)
node csignals_12 = mux(_csignals_T_1, UInt<3>(0h0), _csignals_T_736)
node _csignals_T_737 = mux(_csignals_T_99, UInt<3>(0h2), UInt<3>(0h0))
node _csignals_T_738 = mux(_csignals_T_97, UInt<3>(0h1), _csignals_T_737)
node _csignals_T_739 = mux(_csignals_T_95, UInt<3>(0h4), _csignals_T_738)
node _csignals_T_740 = mux(_csignals_T_93, UInt<3>(0h4), _csignals_T_739)
node _csignals_T_741 = mux(_csignals_T_91, UInt<3>(0h4), _csignals_T_740)
node _csignals_T_742 = mux(_csignals_T_89, UInt<3>(0h4), _csignals_T_741)
node _csignals_T_743 = mux(_csignals_T_87, UInt<3>(0h4), _csignals_T_742)
node _csignals_T_744 = mux(_csignals_T_85, UInt<3>(0h0), _csignals_T_743)
node _csignals_T_745 = mux(_csignals_T_83, UInt<3>(0h0), _csignals_T_744)
node _csignals_T_746 = mux(_csignals_T_81, UInt<3>(0h0), _csignals_T_745)
node _csignals_T_747 = mux(_csignals_T_79, UInt<3>(0h0), _csignals_T_746)
node _csignals_T_748 = mux(_csignals_T_77, UInt<3>(0h0), _csignals_T_747)
node _csignals_T_749 = mux(_csignals_T_75, UInt<3>(0h0), _csignals_T_748)
node _csignals_T_750 = mux(_csignals_T_73, UInt<3>(0h0), _csignals_T_749)
node _csignals_T_751 = mux(_csignals_T_71, UInt<3>(0h0), _csignals_T_750)
node _csignals_T_752 = mux(_csignals_T_69, UInt<3>(0h0), _csignals_T_751)
node _csignals_T_753 = mux(_csignals_T_67, UInt<3>(0h0), _csignals_T_752)
node _csignals_T_754 = mux(_csignals_T_65, UInt<3>(0h0), _csignals_T_753)
node _csignals_T_755 = mux(_csignals_T_63, UInt<3>(0h0), _csignals_T_754)
node _csignals_T_756 = mux(_csignals_T_61, UInt<3>(0h0), _csignals_T_755)
node _csignals_T_757 = mux(_csignals_T_59, UInt<3>(0h0), _csignals_T_756)
node _csignals_T_758 = mux(_csignals_T_57, UInt<3>(0h0), _csignals_T_757)
node _csignals_T_759 = mux(_csignals_T_55, UInt<3>(0h0), _csignals_T_758)
node _csignals_T_760 = mux(_csignals_T_53, UInt<3>(0h0), _csignals_T_759)
node _csignals_T_761 = mux(_csignals_T_51, UInt<3>(0h0), _csignals_T_760)
node _csignals_T_762 = mux(_csignals_T_49, UInt<3>(0h0), _csignals_T_761)
node _csignals_T_763 = mux(_csignals_T_47, UInt<3>(0h0), _csignals_T_762)
node _csignals_T_764 = mux(_csignals_T_45, UInt<3>(0h0), _csignals_T_763)
node _csignals_T_765 = mux(_csignals_T_43, UInt<3>(0h0), _csignals_T_764)
node _csignals_T_766 = mux(_csignals_T_41, UInt<3>(0h0), _csignals_T_765)
node _csignals_T_767 = mux(_csignals_T_39, UInt<3>(0h0), _csignals_T_766)
node _csignals_T_768 = mux(_csignals_T_37, UInt<3>(0h0), _csignals_T_767)
node _csignals_T_769 = mux(_csignals_T_35, UInt<3>(0h0), _csignals_T_768)
node _csignals_T_770 = mux(_csignals_T_33, UInt<3>(0h0), _csignals_T_769)
node _csignals_T_771 = mux(_csignals_T_31, UInt<3>(0h0), _csignals_T_770)
node _csignals_T_772 = mux(_csignals_T_29, UInt<3>(0h0), _csignals_T_771)
node _csignals_T_773 = mux(_csignals_T_27, UInt<3>(0h0), _csignals_T_772)
node _csignals_T_774 = mux(_csignals_T_25, UInt<3>(0h0), _csignals_T_773)
node _csignals_T_775 = mux(_csignals_T_23, UInt<3>(0h0), _csignals_T_774)
node _csignals_T_776 = mux(_csignals_T_21, UInt<3>(0h0), _csignals_T_775)
node _csignals_T_777 = mux(_csignals_T_19, UInt<3>(0h0), _csignals_T_776)
node _csignals_T_778 = mux(_csignals_T_17, UInt<3>(0h0), _csignals_T_777)
node _csignals_T_779 = mux(_csignals_T_15, UInt<3>(0h0), _csignals_T_778)
node _csignals_T_780 = mux(_csignals_T_13, UInt<3>(0h0), _csignals_T_779)
node _csignals_T_781 = mux(_csignals_T_11, UInt<3>(0h0), _csignals_T_780)
node _csignals_T_782 = mux(_csignals_T_9, UInt<3>(0h0), _csignals_T_781)
node _csignals_T_783 = mux(_csignals_T_7, UInt<3>(0h0), _csignals_T_782)
node _csignals_T_784 = mux(_csignals_T_5, UInt<3>(0h0), _csignals_T_783)
node _csignals_T_785 = mux(_csignals_T_3, UInt<3>(0h0), _csignals_T_784)
node csignals_13 = mux(_csignals_T_1, UInt<3>(0h0), _csignals_T_785)
wire take_evec : UInt<1>
node _ctrl_pc_sel_T = eq(csignals_1, UInt<4>(0h0))
node _ctrl_pc_sel_T_1 = eq(csignals_1, UInt<4>(0h1))
node _ctrl_pc_sel_T_2 = eq(io.dat.br_eq, UInt<1>(0h0))
node _ctrl_pc_sel_T_3 = mux(_ctrl_pc_sel_T_2, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_4 = eq(csignals_1, UInt<4>(0h2))
node _ctrl_pc_sel_T_5 = mux(io.dat.br_eq, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_6 = eq(csignals_1, UInt<4>(0h3))
node _ctrl_pc_sel_T_7 = eq(io.dat.br_lt, UInt<1>(0h0))
node _ctrl_pc_sel_T_8 = mux(_ctrl_pc_sel_T_7, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_9 = eq(csignals_1, UInt<4>(0h4))
node _ctrl_pc_sel_T_10 = eq(io.dat.br_ltu, UInt<1>(0h0))
node _ctrl_pc_sel_T_11 = mux(_ctrl_pc_sel_T_10, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_12 = eq(csignals_1, UInt<4>(0h5))
node _ctrl_pc_sel_T_13 = mux(io.dat.br_lt, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_14 = eq(csignals_1, UInt<4>(0h6))
node _ctrl_pc_sel_T_15 = mux(io.dat.br_ltu, UInt<3>(0h1), UInt<3>(0h0))
node _ctrl_pc_sel_T_16 = eq(csignals_1, UInt<4>(0h7))
node _ctrl_pc_sel_T_17 = eq(csignals_1, UInt<4>(0h8))
node _ctrl_pc_sel_T_18 = mux(_ctrl_pc_sel_T_17, UInt<3>(0h3), UInt<3>(0h0))
node _ctrl_pc_sel_T_19 = mux(_ctrl_pc_sel_T_16, UInt<3>(0h2), _ctrl_pc_sel_T_18)
node _ctrl_pc_sel_T_20 = mux(_ctrl_pc_sel_T_14, _ctrl_pc_sel_T_15, _ctrl_pc_sel_T_19)
node _ctrl_pc_sel_T_21 = mux(_ctrl_pc_sel_T_12, _ctrl_pc_sel_T_13, _ctrl_pc_sel_T_20)
node _ctrl_pc_sel_T_22 = mux(_ctrl_pc_sel_T_9, _ctrl_pc_sel_T_11, _ctrl_pc_sel_T_21)
node _ctrl_pc_sel_T_23 = mux(_ctrl_pc_sel_T_6, _ctrl_pc_sel_T_8, _ctrl_pc_sel_T_22)
node _ctrl_pc_sel_T_24 = mux(_ctrl_pc_sel_T_4, _ctrl_pc_sel_T_5, _ctrl_pc_sel_T_23)
node _ctrl_pc_sel_T_25 = mux(_ctrl_pc_sel_T_1, _ctrl_pc_sel_T_3, _ctrl_pc_sel_T_24)
node _ctrl_pc_sel_T_26 = mux(_ctrl_pc_sel_T, UInt<3>(0h0), _ctrl_pc_sel_T_25)
node ctrl_pc_sel = mux(take_evec, UInt<3>(0h4), _ctrl_pc_sel_T_26)
node _io_imem_req_valid_T = eq(ctrl_pc_sel, UInt<3>(0h0))
node _io_imem_req_valid_T_1 = eq(_io_imem_req_valid_T, UInt<1>(0h0))
node _io_imem_req_valid_T_2 = and(_io_imem_req_valid_T_1, io.imem.resp.valid)
node _io_imem_req_valid_T_3 = eq(io.dat.wb_hazard_stall, UInt<1>(0h0))
node _io_imem_req_valid_T_4 = and(_io_imem_req_valid_T_2, _io_imem_req_valid_T_3)
node _io_imem_req_valid_T_5 = eq(ctrl_pc_sel, UInt<3>(0h4))
node _io_imem_req_valid_T_6 = or(_io_imem_req_valid_T_4, _io_imem_req_valid_T_5)
connect io.imem.req.valid, _io_imem_req_valid_T_6
connect io.imem.exe_kill, take_evec
connect io.ctl.exe_kill, take_evec
connect io.ctl.pc_sel, ctrl_pc_sel
connect io.ctl.brjmp_sel, csignals_2
connect io.ctl.op1_sel, csignals_3
connect io.ctl.op2_sel, csignals_4
connect io.ctl.alu_fun, csignals_5
connect io.ctl.wb_sel, csignals_6
node _io_ctl_rf_wen_T = eq(io.imem.resp.valid, UInt<1>(0h0))
node _io_ctl_rf_wen_T_1 = mux(_io_ctl_rf_wen_T, UInt<1>(0h0), csignals_7)
connect io.ctl.rf_wen, _io_ctl_rf_wen_T_1
connect io.ctl.bypassable, csignals_8
node rs1_addr = bits(io.imem.resp.bits.inst, 19, 15)
node _csr_ren_T = eq(csignals_12, UInt<3>(0h6))
node _csr_ren_T_1 = eq(csignals_12, UInt<3>(0h7))
node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1)
node _csr_ren_T_3 = eq(rs1_addr, UInt<1>(0h0))
node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3)
node csr_cmd = mux(csr_ren, UInt<3>(0h2), csignals_12)
node _io_ctl_csr_cmd_T = eq(io.imem.resp.valid, UInt<1>(0h0))
node _io_ctl_csr_cmd_T_1 = mux(_io_ctl_csr_cmd_T, UInt<3>(0h0), csr_cmd)
connect io.ctl.csr_cmd, _io_ctl_csr_cmd_T_1
node _io_ctl_dmem_val_T = and(csignals_9, io.imem.resp.valid)
connect io.ctl.dmem_val, _io_ctl_dmem_val_T
connect io.ctl.dmem_fcn, csignals_10
connect io.ctl.dmem_typ, csignals_11
node _exe_illegal_T = eq(csignals_0, UInt<1>(0h0))
node exe_illegal = and(_exe_illegal_T, io.imem.resp.valid)
regreset wb_reg_illegal : UInt<1>, clock, reset, UInt<1>(0h0)
regreset wb_reg_data_misaligned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset wb_reg_inst_misaligned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset wb_reg_mem_fcn : UInt<1>, clock, reset, UInt<1>(0h0)
connect wb_reg_illegal, exe_illegal
connect wb_reg_data_misaligned, io.dat.data_misaligned
connect wb_reg_inst_misaligned, io.dat.inst_misaligned
connect wb_reg_mem_fcn, csignals_10
node _T = or(io.dat.wb_hazard_stall, io.ctl.exe_kill)
when _T :
connect wb_reg_illegal, UInt<1>(0h0)
connect wb_reg_data_misaligned, UInt<1>(0h0)
connect wb_reg_inst_misaligned, UInt<1>(0h0)
connect wb_reg_mem_fcn, UInt<1>(0h0)
node _take_evec_T = or(io.ctl.exception, io.dat.csr_eret)
node _take_evec_T_1 = or(_take_evec_T, io.dat.csr_interrupt)
connect take_evec, _take_evec_T_1
node _io_ctl_exception_T = or(wb_reg_illegal, wb_reg_inst_misaligned)
node _io_ctl_exception_T_1 = or(_io_ctl_exception_T, wb_reg_data_misaligned)
node _io_ctl_exception_T_2 = eq(io.dat.csr_eret, UInt<1>(0h0))
node _io_ctl_exception_T_3 = and(_io_ctl_exception_T_1, _io_ctl_exception_T_2)
connect io.ctl.exception, _io_ctl_exception_T_3
node _io_ctl_exception_cause_T = eq(wb_reg_mem_fcn, UInt<1>(0h1))
node _io_ctl_exception_cause_T_1 = mux(_io_ctl_exception_cause_T, UInt<3>(0h6), UInt<3>(0h4))
node _io_ctl_exception_cause_T_2 = mux(wb_reg_inst_misaligned, UInt<1>(0h0), _io_ctl_exception_cause_T_1)
node _io_ctl_exception_cause_T_3 = mux(wb_reg_illegal, UInt<2>(0h2), _io_ctl_exception_cause_T_2)
connect io.ctl.exception_cause, _io_ctl_exception_cause_T_3 | module CtlPath( // @[cpath.scala:52:7]
input clock, // @[cpath.scala:52:7]
input reset, // @[cpath.scala:52:7]
output io_imem_req_valid, // @[cpath.scala:54:15]
input io_imem_resp_valid, // @[cpath.scala:54:15]
input [31:0] io_imem_resp_bits_pc, // @[cpath.scala:54:15]
input [31:0] io_imem_resp_bits_inst, // @[cpath.scala:54:15]
input [31:0] io_imem_debug_if_pc, // @[cpath.scala:54:15]
input [31:0] io_imem_debug_if_inst, // @[cpath.scala:54:15]
output io_imem_exe_kill, // @[cpath.scala:54:15]
input io_dmem_req_ready, // @[cpath.scala:54:15]
input io_dmem_resp_valid, // @[cpath.scala:54:15]
input [31:0] io_dmem_resp_bits_data, // @[cpath.scala:54:15]
input io_dat_br_eq, // @[cpath.scala:54:15]
input io_dat_br_lt, // @[cpath.scala:54:15]
input io_dat_br_ltu, // @[cpath.scala:54:15]
input io_dat_inst_misaligned, // @[cpath.scala:54:15]
input io_dat_data_misaligned, // @[cpath.scala:54:15]
input io_dat_wb_hazard_stall, // @[cpath.scala:54:15]
input io_dat_csr_eret, // @[cpath.scala:54:15]
input io_dat_csr_interrupt, // @[cpath.scala:54:15]
output io_ctl_exe_kill, // @[cpath.scala:54:15]
output [2:0] io_ctl_pc_sel, // @[cpath.scala:54:15]
output io_ctl_brjmp_sel, // @[cpath.scala:54:15]
output [1:0] io_ctl_op1_sel, // @[cpath.scala:54:15]
output [1:0] io_ctl_op2_sel, // @[cpath.scala:54:15]
output [3:0] io_ctl_alu_fun, // @[cpath.scala:54:15]
output [1:0] io_ctl_wb_sel, // @[cpath.scala:54:15]
output io_ctl_rf_wen, // @[cpath.scala:54:15]
output io_ctl_bypassable, // @[cpath.scala:54:15]
output [2:0] io_ctl_csr_cmd, // @[cpath.scala:54:15]
output io_ctl_dmem_val, // @[cpath.scala:54:15]
output io_ctl_dmem_fcn, // @[cpath.scala:54:15]
output [2:0] io_ctl_dmem_typ, // @[cpath.scala:54:15]
output io_ctl_exception, // @[cpath.scala:54:15]
output [31:0] io_ctl_exception_cause // @[cpath.scala:54:15]
);
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[cpath.scala:52:7]
wire [31:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[cpath.scala:52:7]
wire [31:0] io_imem_resp_bits_inst_0 = io_imem_resp_bits_inst; // @[cpath.scala:52:7]
wire [31:0] io_imem_debug_if_pc_0 = io_imem_debug_if_pc; // @[cpath.scala:52:7]
wire [31:0] io_imem_debug_if_inst_0 = io_imem_debug_if_inst; // @[cpath.scala:52:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[cpath.scala:52:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[cpath.scala:52:7]
wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[cpath.scala:52:7]
wire io_dat_br_eq_0 = io_dat_br_eq; // @[cpath.scala:52:7]
wire io_dat_br_lt_0 = io_dat_br_lt; // @[cpath.scala:52:7]
wire io_dat_br_ltu_0 = io_dat_br_ltu; // @[cpath.scala:52:7]
wire io_dat_inst_misaligned_0 = io_dat_inst_misaligned; // @[cpath.scala:52:7]
wire io_dat_data_misaligned_0 = io_dat_data_misaligned; // @[cpath.scala:52:7]
wire io_dat_wb_hazard_stall_0 = io_dat_wb_hazard_stall; // @[cpath.scala:52:7]
wire io_dat_csr_eret_0 = io_dat_csr_eret; // @[cpath.scala:52:7]
wire io_dat_csr_interrupt_0 = io_dat_csr_interrupt; // @[cpath.scala:52:7]
wire [3:0] _csignals_T_149 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_150 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_151 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_152 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_153 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_154 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_155 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_156 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_157 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_158 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_159 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_160 = 4'h0; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_161 = 4'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_247 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_248 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_249 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_250 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_251 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_252 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_253 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_296 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_297 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_298 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_299 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_300 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_301 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_302 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_303 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_304 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_305 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_306 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_307 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_308 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_309 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_310 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_311 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_312 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_313 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_314 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_394 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_395 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_396 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_397 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_398 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_399 = 2'h0; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_400 = 2'h0; // @[Lookup.scala:34:39]
wire [2:0] io_dmem_req_bits_typ = 3'h0; // @[cpath.scala:52:7]
wire [2:0] _csignals_T_639 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_640 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_641 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_642 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_643 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_644 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_645 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_646 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_647 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_648 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_649 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_650 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_651 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_652 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_653 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_654 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_655 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_656 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_657 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_658 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_659 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_660 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_661 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_662 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_663 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_664 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_665 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_666 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_667 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_668 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_669 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_670 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_671 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_672 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_673 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_674 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_675 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_676 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_677 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_678 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_679 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_680 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_688 = 3'h0; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_689 = 3'h0; // @[Lookup.scala:34:39]
wire [31:0] io_imem_req_bits_pc = 32'h0; // @[cpath.scala:52:7]
wire [31:0] io_dmem_req_bits_addr = 32'h0; // @[cpath.scala:52:7]
wire [31:0] io_dmem_req_bits_data = 32'h0; // @[cpath.scala:52:7]
wire io_dcpath_halt = 1'h0; // @[cpath.scala:52:7]
wire io_imem_resp_ready = 1'h0; // @[cpath.scala:52:7]
wire io_imem_imiss = 1'h0; // @[cpath.scala:52:7]
wire io_dmem_req_valid = 1'h0; // @[cpath.scala:52:7]
wire io_dmem_req_bits_fcn = 1'h0; // @[cpath.scala:52:7]
wire _csignals_T_198 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_199 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_200 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_201 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_202 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_203 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_204 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_205 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_206 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_207 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_208 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_209 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_210 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_211 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_212 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_213 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_214 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_215 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_216 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_345 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_346 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_347 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_348 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_349 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_350 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_351 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_443 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_444 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_445 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_446 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_447 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_448 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_449 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_492 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_493 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_494 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_495 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_496 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_497 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_498 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_499 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_500 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_501 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_502 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_503 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_504 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_505 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_506 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_507 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_508 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_509 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_510 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_511 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_541 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_542 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_543 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_544 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_545 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_546 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_547 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_548 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_549 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_550 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_551 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_552 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_553 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_554 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_555 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_556 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_557 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_558 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_559 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_560 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_561 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_562 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_563 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_564 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_565 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_566 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_567 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_568 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_569 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_570 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_571 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_572 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_573 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_574 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_575 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_576 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_577 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_578 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_579 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_580 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_581 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_582 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_590 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_591 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_592 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_593 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_594 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_595 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_596 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_597 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_598 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_599 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_600 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_601 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_602 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_603 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_604 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_605 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_606 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_607 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_608 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_609 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_610 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_611 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_612 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_613 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_614 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_615 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_616 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_617 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_618 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_619 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_620 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_621 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_622 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_623 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_624 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_625 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_626 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_627 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_628 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_629 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_630 = 1'h0; // @[Lookup.scala:34:39]
wire _csignals_T_631 = 1'h0; // @[Lookup.scala:34:39]
wire _io_imem_req_valid_T_6; // @[cpath.scala:151:93]
wire [31:0] _csignals_T_86 = io_imem_resp_bits_inst_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_88 = io_imem_resp_bits_inst_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_90 = io_imem_resp_bits_inst_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_92 = io_imem_resp_bits_inst_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_94 = io_imem_resp_bits_inst_0; // @[Lookup.scala:31:38]
wire take_evec; // @[cpath.scala:135:24]
wire [2:0] ctrl_pc_sel; // @[cpath.scala:138:25]
wire csignals_2; // @[Lookup.scala:34:39]
wire [1:0] csignals_3; // @[Lookup.scala:34:39]
wire [1:0] csignals_4; // @[Lookup.scala:34:39]
wire [3:0] csignals_5; // @[Lookup.scala:34:39]
wire [1:0] csignals_6; // @[Lookup.scala:34:39]
wire _io_ctl_rf_wen_T_1; // @[cpath.scala:161:28]
wire csignals_8; // @[Lookup.scala:34:39]
wire [2:0] _io_ctl_csr_cmd_T_1; // @[cpath.scala:167:28]
wire _io_ctl_dmem_val_T; // @[cpath.scala:173:38]
wire csignals_10; // @[Lookup.scala:34:39]
wire [2:0] csignals_11; // @[Lookup.scala:34:39]
wire _io_ctl_exception_T_3; // @[cpath.scala:201:93]
wire io_imem_req_valid_0; // @[cpath.scala:52:7]
wire io_imem_exe_kill_0; // @[cpath.scala:52:7]
wire io_ctl_exe_kill_0; // @[cpath.scala:52:7]
wire [2:0] io_ctl_pc_sel_0; // @[cpath.scala:52:7]
wire io_ctl_brjmp_sel_0; // @[cpath.scala:52:7]
wire [1:0] io_ctl_op1_sel_0; // @[cpath.scala:52:7]
wire [1:0] io_ctl_op2_sel_0; // @[cpath.scala:52:7]
wire [3:0] io_ctl_alu_fun_0; // @[cpath.scala:52:7]
wire [1:0] io_ctl_wb_sel_0; // @[cpath.scala:52:7]
wire io_ctl_rf_wen_0; // @[cpath.scala:52:7]
wire io_ctl_bypassable_0; // @[cpath.scala:52:7]
wire [2:0] io_ctl_csr_cmd_0; // @[cpath.scala:52:7]
wire io_ctl_dmem_val_0; // @[cpath.scala:52:7]
wire io_ctl_dmem_fcn_0; // @[cpath.scala:52:7]
wire [2:0] io_ctl_dmem_typ_0; // @[cpath.scala:52:7]
wire io_ctl_exception_0; // @[cpath.scala:52:7]
wire [31:0] io_ctl_exception_cause_0; // @[cpath.scala:52:7]
wire [31:0] _GEN = {17'h0, io_imem_resp_bits_inst_0[14:0] & 15'h707F}; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T; // @[Lookup.scala:31:38]
assign _csignals_T = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_2; // @[Lookup.scala:31:38]
assign _csignals_T_2 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_4; // @[Lookup.scala:31:38]
assign _csignals_T_4 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_6; // @[Lookup.scala:31:38]
assign _csignals_T_6 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_8; // @[Lookup.scala:31:38]
assign _csignals_T_8 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_10; // @[Lookup.scala:31:38]
assign _csignals_T_10 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_12; // @[Lookup.scala:31:38]
assign _csignals_T_12 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_14; // @[Lookup.scala:31:38]
assign _csignals_T_14 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_20; // @[Lookup.scala:31:38]
assign _csignals_T_20 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_22; // @[Lookup.scala:31:38]
assign _csignals_T_22 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_24; // @[Lookup.scala:31:38]
assign _csignals_T_24 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_26; // @[Lookup.scala:31:38]
assign _csignals_T_26 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_28; // @[Lookup.scala:31:38]
assign _csignals_T_28 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_30; // @[Lookup.scala:31:38]
assign _csignals_T_30 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_60; // @[Lookup.scala:31:38]
assign _csignals_T_60 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_62; // @[Lookup.scala:31:38]
assign _csignals_T_62 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_64; // @[Lookup.scala:31:38]
assign _csignals_T_64 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_66; // @[Lookup.scala:31:38]
assign _csignals_T_66 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_68; // @[Lookup.scala:31:38]
assign _csignals_T_68 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_70; // @[Lookup.scala:31:38]
assign _csignals_T_70 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_72; // @[Lookup.scala:31:38]
assign _csignals_T_72 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_74; // @[Lookup.scala:31:38]
assign _csignals_T_74 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_76; // @[Lookup.scala:31:38]
assign _csignals_T_76 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_78; // @[Lookup.scala:31:38]
assign _csignals_T_78 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_80; // @[Lookup.scala:31:38]
assign _csignals_T_80 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_82; // @[Lookup.scala:31:38]
assign _csignals_T_82 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_84; // @[Lookup.scala:31:38]
assign _csignals_T_84 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_96; // @[Lookup.scala:31:38]
assign _csignals_T_96 = _GEN; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_98; // @[Lookup.scala:31:38]
assign _csignals_T_98 = _GEN; // @[Lookup.scala:31:38]
wire _csignals_T_1 = _csignals_T == 32'h2003; // @[Lookup.scala:31:38]
wire _csignals_T_3 = _csignals_T_2 == 32'h3; // @[Lookup.scala:31:38]
wire _csignals_T_5 = _csignals_T_4 == 32'h4003; // @[Lookup.scala:31:38]
wire _csignals_T_7 = _csignals_T_6 == 32'h1003; // @[Lookup.scala:31:38]
wire _csignals_T_9 = _csignals_T_8 == 32'h5003; // @[Lookup.scala:31:38]
wire _csignals_T_11 = _csignals_T_10 == 32'h2023; // @[Lookup.scala:31:38]
wire _csignals_T_13 = _csignals_T_12 == 32'h23; // @[Lookup.scala:31:38]
wire _csignals_T_15 = _csignals_T_14 == 32'h1023; // @[Lookup.scala:31:38]
wire _csignals_T_583 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_632 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39]
wire [31:0] _GEN_0 = {25'h0, io_imem_resp_bits_inst_0[6:0]}; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_16; // @[Lookup.scala:31:38]
assign _csignals_T_16 = _GEN_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_18; // @[Lookup.scala:31:38]
assign _csignals_T_18 = _GEN_0; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_58; // @[Lookup.scala:31:38]
assign _csignals_T_58 = _GEN_0; // @[Lookup.scala:31:38]
wire _csignals_T_17 = _csignals_T_16 == 32'h17; // @[Lookup.scala:31:38]
wire _csignals_T_19 = _csignals_T_18 == 32'h37; // @[Lookup.scala:31:38]
wire _csignals_T_21 = _csignals_T_20 == 32'h13; // @[Lookup.scala:31:38]
wire _csignals_T_23 = _csignals_T_22 == 32'h7013; // @[Lookup.scala:31:38]
wire _csignals_T_25 = _csignals_T_24 == 32'h6013; // @[Lookup.scala:31:38]
wire _csignals_T_27 = _csignals_T_26 == 32'h4013; // @[Lookup.scala:31:38]
wire _csignals_T_29 = _csignals_T_28 == 32'h2013; // @[Lookup.scala:31:38]
wire _csignals_T_31 = _csignals_T_30 == 32'h3013; // @[Lookup.scala:31:38]
wire [31:0] _GEN_1 = io_imem_resp_bits_inst_0 & 32'hFE00707F; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_32; // @[Lookup.scala:31:38]
assign _csignals_T_32 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_34; // @[Lookup.scala:31:38]
assign _csignals_T_34 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_36; // @[Lookup.scala:31:38]
assign _csignals_T_36 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_38; // @[Lookup.scala:31:38]
assign _csignals_T_38 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_40; // @[Lookup.scala:31:38]
assign _csignals_T_40 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_42; // @[Lookup.scala:31:38]
assign _csignals_T_42 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_44; // @[Lookup.scala:31:38]
assign _csignals_T_44 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_46; // @[Lookup.scala:31:38]
assign _csignals_T_46 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_48; // @[Lookup.scala:31:38]
assign _csignals_T_48 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_50; // @[Lookup.scala:31:38]
assign _csignals_T_50 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_52; // @[Lookup.scala:31:38]
assign _csignals_T_52 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_54; // @[Lookup.scala:31:38]
assign _csignals_T_54 = _GEN_1; // @[Lookup.scala:31:38]
wire [31:0] _csignals_T_56; // @[Lookup.scala:31:38]
assign _csignals_T_56 = _GEN_1; // @[Lookup.scala:31:38]
wire _csignals_T_33 = _csignals_T_32 == 32'h1013; // @[Lookup.scala:31:38]
wire _csignals_T_35 = _csignals_T_34 == 32'h40005013; // @[Lookup.scala:31:38]
wire _csignals_T_37 = _csignals_T_36 == 32'h5013; // @[Lookup.scala:31:38]
wire _csignals_T_39 = _csignals_T_38 == 32'h1033; // @[Lookup.scala:31:38]
wire _csignals_T_41 = _csignals_T_40 == 32'h33; // @[Lookup.scala:31:38]
wire _csignals_T_43 = _csignals_T_42 == 32'h40000033; // @[Lookup.scala:31:38]
wire _csignals_T_45 = _csignals_T_44 == 32'h2033; // @[Lookup.scala:31:38]
wire _csignals_T_47 = _csignals_T_46 == 32'h3033; // @[Lookup.scala:31:38]
wire _csignals_T_49 = _csignals_T_48 == 32'h7033; // @[Lookup.scala:31:38]
wire _csignals_T_51 = _csignals_T_50 == 32'h6033; // @[Lookup.scala:31:38]
wire _csignals_T_53 = _csignals_T_52 == 32'h4033; // @[Lookup.scala:31:38]
wire _csignals_T_55 = _csignals_T_54 == 32'h40005033; // @[Lookup.scala:31:38]
wire _csignals_T_57 = _csignals_T_56 == 32'h5033; // @[Lookup.scala:31:38]
wire _csignals_T_59 = _csignals_T_58 == 32'h6F; // @[Lookup.scala:31:38]
wire _csignals_T_512 = _csignals_T_59; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_61 = _csignals_T_60 == 32'h67; // @[Lookup.scala:31:38]
wire _csignals_T_217 = _csignals_T_61; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_63 = _csignals_T_62 == 32'h63; // @[Lookup.scala:31:38]
wire _csignals_T_65 = _csignals_T_64 == 32'h1063; // @[Lookup.scala:31:38]
wire _csignals_T_67 = _csignals_T_66 == 32'h5063; // @[Lookup.scala:31:38]
wire _csignals_T_69 = _csignals_T_68 == 32'h7063; // @[Lookup.scala:31:38]
wire _csignals_T_71 = _csignals_T_70 == 32'h4063; // @[Lookup.scala:31:38]
wire _csignals_T_73 = _csignals_T_72 == 32'h6063; // @[Lookup.scala:31:38]
wire _csignals_T_75 = _csignals_T_74 == 32'h5073; // @[Lookup.scala:31:38]
wire _csignals_T_77 = _csignals_T_76 == 32'h6073; // @[Lookup.scala:31:38]
wire _csignals_T_79 = _csignals_T_78 == 32'h1073; // @[Lookup.scala:31:38]
wire _csignals_T_81 = _csignals_T_80 == 32'h2073; // @[Lookup.scala:31:38]
wire _csignals_T_83 = _csignals_T_82 == 32'h3073; // @[Lookup.scala:31:38]
wire _csignals_T_85 = _csignals_T_84 == 32'h7073; // @[Lookup.scala:31:38]
wire _csignals_T_450 = _csignals_T_85; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_87 = _csignals_T_86 == 32'h73; // @[Lookup.scala:31:38]
wire _csignals_T_89 = _csignals_T_88 == 32'h30200073; // @[Lookup.scala:31:38]
wire _csignals_T_91 = _csignals_T_90 == 32'h7B200073; // @[Lookup.scala:31:38]
wire _csignals_T_93 = _csignals_T_92 == 32'h100073; // @[Lookup.scala:31:38]
wire _csignals_T_95 = _csignals_T_94 == 32'h10500073; // @[Lookup.scala:31:38]
wire _csignals_T_97 = _csignals_T_96 == 32'h100F; // @[Lookup.scala:31:38]
wire _csignals_T_99 = _csignals_T_98 == 32'hF; // @[Lookup.scala:31:38]
wire _csignals_T_100 = _csignals_T_99; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_101 = _csignals_T_97 | _csignals_T_100; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_102 = _csignals_T_95 | _csignals_T_101; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_103 = _csignals_T_93 | _csignals_T_102; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_104 = _csignals_T_91 | _csignals_T_103; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_105 = _csignals_T_89 | _csignals_T_104; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_106 = _csignals_T_87 | _csignals_T_105; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_107 = _csignals_T_85 | _csignals_T_106; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_108 = _csignals_T_83 | _csignals_T_107; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_109 = _csignals_T_81 | _csignals_T_108; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_110 = _csignals_T_79 | _csignals_T_109; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_111 = _csignals_T_77 | _csignals_T_110; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_112 = _csignals_T_75 | _csignals_T_111; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_113 = _csignals_T_73 | _csignals_T_112; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_114 = _csignals_T_71 | _csignals_T_113; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_115 = _csignals_T_69 | _csignals_T_114; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_116 = _csignals_T_67 | _csignals_T_115; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_117 = _csignals_T_65 | _csignals_T_116; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_118 = _csignals_T_63 | _csignals_T_117; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_119 = _csignals_T_61 | _csignals_T_118; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_120 = _csignals_T_59 | _csignals_T_119; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_121 = _csignals_T_57 | _csignals_T_120; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_122 = _csignals_T_55 | _csignals_T_121; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_123 = _csignals_T_53 | _csignals_T_122; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_124 = _csignals_T_51 | _csignals_T_123; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_125 = _csignals_T_49 | _csignals_T_124; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_126 = _csignals_T_47 | _csignals_T_125; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_127 = _csignals_T_45 | _csignals_T_126; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_128 = _csignals_T_43 | _csignals_T_127; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_129 = _csignals_T_41 | _csignals_T_128; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_130 = _csignals_T_39 | _csignals_T_129; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_131 = _csignals_T_37 | _csignals_T_130; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_132 = _csignals_T_35 | _csignals_T_131; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_133 = _csignals_T_33 | _csignals_T_132; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_134 = _csignals_T_31 | _csignals_T_133; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_135 = _csignals_T_29 | _csignals_T_134; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_136 = _csignals_T_27 | _csignals_T_135; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_137 = _csignals_T_25 | _csignals_T_136; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_138 = _csignals_T_23 | _csignals_T_137; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_139 = _csignals_T_21 | _csignals_T_138; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_140 = _csignals_T_19 | _csignals_T_139; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_141 = _csignals_T_17 | _csignals_T_140; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_142 = _csignals_T_15 | _csignals_T_141; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_143 = _csignals_T_13 | _csignals_T_142; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_144 = _csignals_T_11 | _csignals_T_143; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_145 = _csignals_T_9 | _csignals_T_144; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_146 = _csignals_T_7 | _csignals_T_145; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_147 = _csignals_T_5 | _csignals_T_146; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_148 = _csignals_T_3 | _csignals_T_147; // @[Lookup.scala:31:38, :34:39]
wire csignals_0 = _csignals_T_1 | _csignals_T_148; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_162 = _csignals_T_73 ? 4'h6 : 4'h0; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_163 = _csignals_T_71 ? 4'h5 : _csignals_T_162; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_164 = _csignals_T_69 ? 4'h4 : _csignals_T_163; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_165 = _csignals_T_67 ? 4'h3 : _csignals_T_164; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_166 = _csignals_T_65 ? 4'h1 : _csignals_T_165; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_167 = _csignals_T_63 ? 4'h2 : _csignals_T_166; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_168 = _csignals_T_61 ? 4'h8 : _csignals_T_167; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_169 = _csignals_T_59 ? 4'h7 : _csignals_T_168; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_170 = _csignals_T_57 ? 4'h0 : _csignals_T_169; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_171 = _csignals_T_55 ? 4'h0 : _csignals_T_170; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_172 = _csignals_T_53 ? 4'h0 : _csignals_T_171; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_173 = _csignals_T_51 ? 4'h0 : _csignals_T_172; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_174 = _csignals_T_49 ? 4'h0 : _csignals_T_173; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_175 = _csignals_T_47 ? 4'h0 : _csignals_T_174; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_176 = _csignals_T_45 ? 4'h0 : _csignals_T_175; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_177 = _csignals_T_43 ? 4'h0 : _csignals_T_176; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_178 = _csignals_T_41 ? 4'h0 : _csignals_T_177; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_179 = _csignals_T_39 ? 4'h0 : _csignals_T_178; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_180 = _csignals_T_37 ? 4'h0 : _csignals_T_179; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_181 = _csignals_T_35 ? 4'h0 : _csignals_T_180; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_182 = _csignals_T_33 ? 4'h0 : _csignals_T_181; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_183 = _csignals_T_31 ? 4'h0 : _csignals_T_182; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_184 = _csignals_T_29 ? 4'h0 : _csignals_T_183; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_185 = _csignals_T_27 ? 4'h0 : _csignals_T_184; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_186 = _csignals_T_25 ? 4'h0 : _csignals_T_185; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_187 = _csignals_T_23 ? 4'h0 : _csignals_T_186; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_188 = _csignals_T_21 ? 4'h0 : _csignals_T_187; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_189 = _csignals_T_19 ? 4'h0 : _csignals_T_188; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_190 = _csignals_T_17 ? 4'h0 : _csignals_T_189; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_191 = _csignals_T_15 ? 4'h0 : _csignals_T_190; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_192 = _csignals_T_13 ? 4'h0 : _csignals_T_191; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_193 = _csignals_T_11 ? 4'h0 : _csignals_T_192; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_194 = _csignals_T_9 ? 4'h0 : _csignals_T_193; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_195 = _csignals_T_7 ? 4'h0 : _csignals_T_194; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_196 = _csignals_T_5 ? 4'h0 : _csignals_T_195; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_197 = _csignals_T_3 ? 4'h0 : _csignals_T_196; // @[Lookup.scala:31:38, :34:39]
wire [3:0] csignals_1 = _csignals_T_1 ? 4'h0 : _csignals_T_197; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_218 = _csignals_T_59 | _csignals_T_217; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_219 = ~_csignals_T_57 & _csignals_T_218; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_220 = ~_csignals_T_55 & _csignals_T_219; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_221 = ~_csignals_T_53 & _csignals_T_220; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_222 = ~_csignals_T_51 & _csignals_T_221; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_223 = ~_csignals_T_49 & _csignals_T_222; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_224 = ~_csignals_T_47 & _csignals_T_223; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_225 = ~_csignals_T_45 & _csignals_T_224; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_226 = ~_csignals_T_43 & _csignals_T_225; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_227 = ~_csignals_T_41 & _csignals_T_226; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_228 = ~_csignals_T_39 & _csignals_T_227; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_229 = ~_csignals_T_37 & _csignals_T_228; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_230 = ~_csignals_T_35 & _csignals_T_229; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_231 = ~_csignals_T_33 & _csignals_T_230; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_232 = ~_csignals_T_31 & _csignals_T_231; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_233 = ~_csignals_T_29 & _csignals_T_232; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_234 = ~_csignals_T_27 & _csignals_T_233; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_235 = ~_csignals_T_25 & _csignals_T_234; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_236 = ~_csignals_T_23 & _csignals_T_235; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_237 = ~_csignals_T_21 & _csignals_T_236; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_238 = ~_csignals_T_19 & _csignals_T_237; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_239 = ~_csignals_T_17 & _csignals_T_238; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_240 = ~_csignals_T_15 & _csignals_T_239; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_241 = ~_csignals_T_13 & _csignals_T_240; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_242 = ~_csignals_T_11 & _csignals_T_241; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_243 = ~_csignals_T_9 & _csignals_T_242; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_244 = ~_csignals_T_7 & _csignals_T_243; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_245 = ~_csignals_T_5 & _csignals_T_244; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_246 = ~_csignals_T_3 & _csignals_T_245; // @[Lookup.scala:31:38, :34:39]
assign csignals_2 = ~_csignals_T_1 & _csignals_T_246; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_brjmp_sel_0 = csignals_2; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_254 = {_csignals_T_85, 1'h0}; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_255 = _csignals_T_83 ? 2'h0 : _csignals_T_254; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_256 = _csignals_T_81 ? 2'h0 : _csignals_T_255; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_257 = _csignals_T_79 ? 2'h0 : _csignals_T_256; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_258 = _csignals_T_77 ? 2'h2 : _csignals_T_257; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_259 = _csignals_T_75 ? 2'h2 : _csignals_T_258; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_260 = _csignals_T_73 ? 2'h0 : _csignals_T_259; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_261 = _csignals_T_71 ? 2'h0 : _csignals_T_260; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_262 = _csignals_T_69 ? 2'h0 : _csignals_T_261; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_263 = _csignals_T_67 ? 2'h0 : _csignals_T_262; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_264 = _csignals_T_65 ? 2'h0 : _csignals_T_263; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_265 = _csignals_T_63 ? 2'h0 : _csignals_T_264; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_266 = _csignals_T_61 ? 2'h0 : _csignals_T_265; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_267 = _csignals_T_59 ? 2'h0 : _csignals_T_266; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_268 = _csignals_T_57 ? 2'h0 : _csignals_T_267; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_269 = _csignals_T_55 ? 2'h0 : _csignals_T_268; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_270 = _csignals_T_53 ? 2'h0 : _csignals_T_269; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_271 = _csignals_T_51 ? 2'h0 : _csignals_T_270; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_272 = _csignals_T_49 ? 2'h0 : _csignals_T_271; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_273 = _csignals_T_47 ? 2'h0 : _csignals_T_272; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_274 = _csignals_T_45 ? 2'h0 : _csignals_T_273; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_275 = _csignals_T_43 ? 2'h0 : _csignals_T_274; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_276 = _csignals_T_41 ? 2'h0 : _csignals_T_275; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_277 = _csignals_T_39 ? 2'h0 : _csignals_T_276; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_278 = _csignals_T_37 ? 2'h0 : _csignals_T_277; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_279 = _csignals_T_35 ? 2'h0 : _csignals_T_278; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_280 = _csignals_T_33 ? 2'h0 : _csignals_T_279; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_281 = _csignals_T_31 ? 2'h0 : _csignals_T_280; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_282 = _csignals_T_29 ? 2'h0 : _csignals_T_281; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_283 = _csignals_T_27 ? 2'h0 : _csignals_T_282; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_284 = _csignals_T_25 ? 2'h0 : _csignals_T_283; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_285 = _csignals_T_23 ? 2'h0 : _csignals_T_284; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_286 = _csignals_T_21 ? 2'h0 : _csignals_T_285; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_287 = _csignals_T_19 ? 2'h1 : _csignals_T_286; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_288 = _csignals_T_17 ? 2'h1 : _csignals_T_287; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_289 = _csignals_T_15 ? 2'h0 : _csignals_T_288; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_290 = _csignals_T_13 ? 2'h0 : _csignals_T_289; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_291 = _csignals_T_11 ? 2'h0 : _csignals_T_290; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_292 = _csignals_T_9 ? 2'h0 : _csignals_T_291; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_293 = _csignals_T_7 ? 2'h0 : _csignals_T_292; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_294 = _csignals_T_5 ? 2'h0 : _csignals_T_293; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_295 = _csignals_T_3 ? 2'h0 : _csignals_T_294; // @[Lookup.scala:31:38, :34:39]
assign csignals_3 = _csignals_T_1 ? 2'h0 : _csignals_T_295; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_op1_sel_0 = csignals_3; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_315 = {1'h0, _csignals_T_61}; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_316 = _csignals_T_59 ? 2'h0 : _csignals_T_315; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_317 = _csignals_T_57 ? 2'h0 : _csignals_T_316; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_318 = _csignals_T_55 ? 2'h0 : _csignals_T_317; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_319 = _csignals_T_53 ? 2'h0 : _csignals_T_318; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_320 = _csignals_T_51 ? 2'h0 : _csignals_T_319; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_321 = _csignals_T_49 ? 2'h0 : _csignals_T_320; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_322 = _csignals_T_47 ? 2'h0 : _csignals_T_321; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_323 = _csignals_T_45 ? 2'h0 : _csignals_T_322; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_324 = _csignals_T_43 ? 2'h0 : _csignals_T_323; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_325 = _csignals_T_41 ? 2'h0 : _csignals_T_324; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_326 = _csignals_T_39 ? 2'h0 : _csignals_T_325; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_327 = _csignals_T_37 ? 2'h1 : _csignals_T_326; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_328 = _csignals_T_35 ? 2'h1 : _csignals_T_327; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_329 = _csignals_T_33 ? 2'h1 : _csignals_T_328; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_330 = _csignals_T_31 ? 2'h1 : _csignals_T_329; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_331 = _csignals_T_29 ? 2'h1 : _csignals_T_330; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_332 = _csignals_T_27 ? 2'h1 : _csignals_T_331; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_333 = _csignals_T_25 ? 2'h1 : _csignals_T_332; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_334 = _csignals_T_23 ? 2'h1 : _csignals_T_333; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_335 = _csignals_T_21 ? 2'h1 : _csignals_T_334; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_336 = _csignals_T_19 ? 2'h0 : _csignals_T_335; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_337 = _csignals_T_17 ? 2'h3 : _csignals_T_336; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_338 = _csignals_T_15 ? 2'h2 : _csignals_T_337; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_339 = _csignals_T_13 ? 2'h2 : _csignals_T_338; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_340 = _csignals_T_11 ? 2'h2 : _csignals_T_339; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_341 = _csignals_T_9 ? 2'h1 : _csignals_T_340; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_342 = _csignals_T_7 ? 2'h1 : _csignals_T_341; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_343 = _csignals_T_5 ? 2'h1 : _csignals_T_342; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_344 = _csignals_T_3 ? 2'h1 : _csignals_T_343; // @[Lookup.scala:31:38, :34:39]
assign csignals_4 = _csignals_T_1 ? 2'h1 : _csignals_T_344; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_op2_sel_0 = csignals_4; // @[Lookup.scala:34:39]
wire [3:0] _csignals_T_352 = {_csignals_T_85, 3'h0}; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_353 = _csignals_T_83 ? 4'h8 : _csignals_T_352; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_354 = _csignals_T_81 ? 4'h8 : _csignals_T_353; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_355 = _csignals_T_79 ? 4'h8 : _csignals_T_354; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_356 = _csignals_T_77 ? 4'h8 : _csignals_T_355; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_357 = _csignals_T_75 ? 4'h8 : _csignals_T_356; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_358 = _csignals_T_73 ? 4'h0 : _csignals_T_357; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_359 = _csignals_T_71 ? 4'h0 : _csignals_T_358; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_360 = _csignals_T_69 ? 4'h0 : _csignals_T_359; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_361 = _csignals_T_67 ? 4'h0 : _csignals_T_360; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_362 = _csignals_T_65 ? 4'h0 : _csignals_T_361; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_363 = _csignals_T_63 ? 4'h0 : _csignals_T_362; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_364 = _csignals_T_61 ? 4'h0 : _csignals_T_363; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_365 = _csignals_T_59 ? 4'h0 : _csignals_T_364; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_366 = _csignals_T_57 ? 4'h5 : _csignals_T_365; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_367 = _csignals_T_55 ? 4'hB : _csignals_T_366; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_368 = _csignals_T_53 ? 4'h4 : _csignals_T_367; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_369 = _csignals_T_51 ? 4'h6 : _csignals_T_368; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_370 = _csignals_T_49 ? 4'h7 : _csignals_T_369; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_371 = _csignals_T_47 ? 4'hE : _csignals_T_370; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_372 = _csignals_T_45 ? 4'hC : _csignals_T_371; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_373 = _csignals_T_43 ? 4'hA : _csignals_T_372; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_374 = _csignals_T_41 ? 4'h0 : _csignals_T_373; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_375 = _csignals_T_39 ? 4'h1 : _csignals_T_374; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_376 = _csignals_T_37 ? 4'h5 : _csignals_T_375; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_377 = _csignals_T_35 ? 4'hB : _csignals_T_376; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_378 = _csignals_T_33 ? 4'h1 : _csignals_T_377; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_379 = _csignals_T_31 ? 4'hE : _csignals_T_378; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_380 = _csignals_T_29 ? 4'hC : _csignals_T_379; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_381 = _csignals_T_27 ? 4'h4 : _csignals_T_380; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_382 = _csignals_T_25 ? 4'h6 : _csignals_T_381; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_383 = _csignals_T_23 ? 4'h7 : _csignals_T_382; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_384 = _csignals_T_21 ? 4'h0 : _csignals_T_383; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_385 = _csignals_T_19 ? 4'h8 : _csignals_T_384; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_386 = _csignals_T_17 ? 4'h0 : _csignals_T_385; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_387 = _csignals_T_15 ? 4'h0 : _csignals_T_386; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_388 = _csignals_T_13 ? 4'h0 : _csignals_T_387; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_389 = _csignals_T_11 ? 4'h0 : _csignals_T_388; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_390 = _csignals_T_9 ? 4'h0 : _csignals_T_389; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_391 = _csignals_T_7 ? 4'h0 : _csignals_T_390; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_392 = _csignals_T_5 ? 4'h0 : _csignals_T_391; // @[Lookup.scala:31:38, :34:39]
wire [3:0] _csignals_T_393 = _csignals_T_3 ? 4'h0 : _csignals_T_392; // @[Lookup.scala:31:38, :34:39]
assign csignals_5 = _csignals_T_1 ? 4'h0 : _csignals_T_393; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_alu_fun_0 = csignals_5; // @[Lookup.scala:34:39]
wire [1:0] _csignals_T_401 = {2{_csignals_T_85}}; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_402 = _csignals_T_83 ? 2'h3 : _csignals_T_401; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_403 = _csignals_T_81 ? 2'h3 : _csignals_T_402; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_404 = _csignals_T_79 ? 2'h3 : _csignals_T_403; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_405 = _csignals_T_77 ? 2'h3 : _csignals_T_404; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_406 = _csignals_T_75 ? 2'h3 : _csignals_T_405; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_407 = _csignals_T_73 ? 2'h0 : _csignals_T_406; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_408 = _csignals_T_71 ? 2'h0 : _csignals_T_407; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_409 = _csignals_T_69 ? 2'h0 : _csignals_T_408; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_410 = _csignals_T_67 ? 2'h0 : _csignals_T_409; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_411 = _csignals_T_65 ? 2'h0 : _csignals_T_410; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_412 = _csignals_T_63 ? 2'h0 : _csignals_T_411; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_413 = _csignals_T_61 ? 2'h2 : _csignals_T_412; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_414 = _csignals_T_59 ? 2'h2 : _csignals_T_413; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_415 = _csignals_T_57 ? 2'h0 : _csignals_T_414; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_416 = _csignals_T_55 ? 2'h0 : _csignals_T_415; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_417 = _csignals_T_53 ? 2'h0 : _csignals_T_416; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_418 = _csignals_T_51 ? 2'h0 : _csignals_T_417; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_419 = _csignals_T_49 ? 2'h0 : _csignals_T_418; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_420 = _csignals_T_47 ? 2'h0 : _csignals_T_419; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_421 = _csignals_T_45 ? 2'h0 : _csignals_T_420; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_422 = _csignals_T_43 ? 2'h0 : _csignals_T_421; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_423 = _csignals_T_41 ? 2'h0 : _csignals_T_422; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_424 = _csignals_T_39 ? 2'h0 : _csignals_T_423; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_425 = _csignals_T_37 ? 2'h0 : _csignals_T_424; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_426 = _csignals_T_35 ? 2'h0 : _csignals_T_425; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_427 = _csignals_T_33 ? 2'h0 : _csignals_T_426; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_428 = _csignals_T_31 ? 2'h0 : _csignals_T_427; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_429 = _csignals_T_29 ? 2'h0 : _csignals_T_428; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_430 = _csignals_T_27 ? 2'h0 : _csignals_T_429; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_431 = _csignals_T_25 ? 2'h0 : _csignals_T_430; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_432 = _csignals_T_23 ? 2'h0 : _csignals_T_431; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_433 = _csignals_T_21 ? 2'h0 : _csignals_T_432; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_434 = _csignals_T_19 ? 2'h0 : _csignals_T_433; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_435 = _csignals_T_17 ? 2'h0 : _csignals_T_434; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_436 = _csignals_T_15 ? 2'h0 : _csignals_T_435; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_437 = _csignals_T_13 ? 2'h0 : _csignals_T_436; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_438 = _csignals_T_11 ? 2'h0 : _csignals_T_437; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_439 = _csignals_T_9 ? 2'h1 : _csignals_T_438; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_440 = _csignals_T_7 ? 2'h1 : _csignals_T_439; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_441 = _csignals_T_5 ? 2'h1 : _csignals_T_440; // @[Lookup.scala:31:38, :34:39]
wire [1:0] _csignals_T_442 = _csignals_T_3 ? 2'h1 : _csignals_T_441; // @[Lookup.scala:31:38, :34:39]
assign csignals_6 = _csignals_T_1 ? 2'h1 : _csignals_T_442; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_wb_sel_0 = csignals_6; // @[Lookup.scala:34:39]
wire _csignals_T_451 = _csignals_T_83 | _csignals_T_450; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_452 = _csignals_T_81 | _csignals_T_451; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_453 = _csignals_T_79 | _csignals_T_452; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_454 = _csignals_T_77 | _csignals_T_453; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_455 = _csignals_T_75 | _csignals_T_454; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_456 = ~_csignals_T_73 & _csignals_T_455; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_457 = ~_csignals_T_71 & _csignals_T_456; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_458 = ~_csignals_T_69 & _csignals_T_457; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_459 = ~_csignals_T_67 & _csignals_T_458; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_460 = ~_csignals_T_65 & _csignals_T_459; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_461 = ~_csignals_T_63 & _csignals_T_460; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_462 = _csignals_T_61 | _csignals_T_461; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_463 = _csignals_T_59 | _csignals_T_462; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_464 = _csignals_T_57 | _csignals_T_463; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_465 = _csignals_T_55 | _csignals_T_464; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_466 = _csignals_T_53 | _csignals_T_465; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_467 = _csignals_T_51 | _csignals_T_466; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_468 = _csignals_T_49 | _csignals_T_467; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_469 = _csignals_T_47 | _csignals_T_468; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_470 = _csignals_T_45 | _csignals_T_469; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_471 = _csignals_T_43 | _csignals_T_470; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_472 = _csignals_T_41 | _csignals_T_471; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_473 = _csignals_T_39 | _csignals_T_472; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_474 = _csignals_T_37 | _csignals_T_473; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_475 = _csignals_T_35 | _csignals_T_474; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_476 = _csignals_T_33 | _csignals_T_475; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_477 = _csignals_T_31 | _csignals_T_476; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_478 = _csignals_T_29 | _csignals_T_477; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_479 = _csignals_T_27 | _csignals_T_478; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_480 = _csignals_T_25 | _csignals_T_479; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_481 = _csignals_T_23 | _csignals_T_480; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_482 = _csignals_T_21 | _csignals_T_481; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_483 = _csignals_T_19 | _csignals_T_482; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_484 = _csignals_T_17 | _csignals_T_483; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_485 = ~_csignals_T_15 & _csignals_T_484; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_486 = ~_csignals_T_13 & _csignals_T_485; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_487 = ~_csignals_T_11 & _csignals_T_486; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_488 = _csignals_T_9 | _csignals_T_487; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_489 = _csignals_T_7 | _csignals_T_488; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_490 = _csignals_T_5 | _csignals_T_489; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_491 = _csignals_T_3 | _csignals_T_490; // @[Lookup.scala:31:38, :34:39]
wire csignals_7 = _csignals_T_1 | _csignals_T_491; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_513 = _csignals_T_57 | _csignals_T_512; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_514 = _csignals_T_55 | _csignals_T_513; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_515 = _csignals_T_53 | _csignals_T_514; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_516 = _csignals_T_51 | _csignals_T_515; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_517 = _csignals_T_49 | _csignals_T_516; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_518 = _csignals_T_47 | _csignals_T_517; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_519 = _csignals_T_45 | _csignals_T_518; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_520 = _csignals_T_43 | _csignals_T_519; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_521 = _csignals_T_41 | _csignals_T_520; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_522 = _csignals_T_39 | _csignals_T_521; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_523 = _csignals_T_37 | _csignals_T_522; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_524 = _csignals_T_35 | _csignals_T_523; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_525 = _csignals_T_33 | _csignals_T_524; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_526 = _csignals_T_31 | _csignals_T_525; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_527 = _csignals_T_29 | _csignals_T_526; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_528 = _csignals_T_27 | _csignals_T_527; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_529 = _csignals_T_25 | _csignals_T_528; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_530 = _csignals_T_23 | _csignals_T_529; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_531 = _csignals_T_21 | _csignals_T_530; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_532 = _csignals_T_19 | _csignals_T_531; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_533 = _csignals_T_17 | _csignals_T_532; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_534 = ~_csignals_T_15 & _csignals_T_533; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_535 = ~_csignals_T_13 & _csignals_T_534; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_536 = ~_csignals_T_11 & _csignals_T_535; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_537 = ~_csignals_T_9 & _csignals_T_536; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_538 = ~_csignals_T_7 & _csignals_T_537; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_539 = ~_csignals_T_5 & _csignals_T_538; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_540 = ~_csignals_T_3 & _csignals_T_539; // @[Lookup.scala:31:38, :34:39]
assign csignals_8 = ~_csignals_T_1 & _csignals_T_540; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_bypassable_0 = csignals_8; // @[Lookup.scala:34:39]
wire _csignals_T_584 = _csignals_T_13 | _csignals_T_583; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_585 = _csignals_T_11 | _csignals_T_584; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_586 = _csignals_T_9 | _csignals_T_585; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_587 = _csignals_T_7 | _csignals_T_586; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_588 = _csignals_T_5 | _csignals_T_587; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_589 = _csignals_T_3 | _csignals_T_588; // @[Lookup.scala:31:38, :34:39]
wire csignals_9 = _csignals_T_1 | _csignals_T_589; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_633 = _csignals_T_13 | _csignals_T_632; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_634 = _csignals_T_11 | _csignals_T_633; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_635 = ~_csignals_T_9 & _csignals_T_634; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_636 = ~_csignals_T_7 & _csignals_T_635; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_637 = ~_csignals_T_5 & _csignals_T_636; // @[Lookup.scala:31:38, :34:39]
wire _csignals_T_638 = ~_csignals_T_3 & _csignals_T_637; // @[Lookup.scala:31:38, :34:39]
assign csignals_10 = ~_csignals_T_1 & _csignals_T_638; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_dmem_fcn_0 = csignals_10; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_681 = {1'h0, _csignals_T_15, 1'h0}; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_682 = _csignals_T_13 ? 3'h1 : _csignals_T_681; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_683 = _csignals_T_11 ? 3'h3 : _csignals_T_682; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_684 = _csignals_T_9 ? 3'h6 : _csignals_T_683; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_685 = _csignals_T_7 ? 3'h2 : _csignals_T_684; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_686 = _csignals_T_5 ? 3'h5 : _csignals_T_685; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_687 = _csignals_T_3 ? 3'h1 : _csignals_T_686; // @[Lookup.scala:31:38, :34:39]
assign csignals_11 = _csignals_T_1 ? 3'h3 : _csignals_T_687; // @[Lookup.scala:31:38, :34:39]
assign io_ctl_dmem_typ_0 = csignals_11; // @[Lookup.scala:34:39]
wire [2:0] _csignals_T_690 = {_csignals_T_95, 2'h0}; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_691 = _csignals_T_93 ? 3'h4 : _csignals_T_690; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_692 = _csignals_T_91 ? 3'h4 : _csignals_T_691; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_693 = _csignals_T_89 ? 3'h4 : _csignals_T_692; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_694 = _csignals_T_87 ? 3'h4 : _csignals_T_693; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_695 = _csignals_T_85 ? 3'h7 : _csignals_T_694; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_696 = _csignals_T_83 ? 3'h7 : _csignals_T_695; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_697 = _csignals_T_81 ? 3'h6 : _csignals_T_696; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_698 = _csignals_T_79 ? 3'h5 : _csignals_T_697; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_699 = _csignals_T_77 ? 3'h6 : _csignals_T_698; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_700 = _csignals_T_75 ? 3'h5 : _csignals_T_699; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_701 = _csignals_T_73 ? 3'h0 : _csignals_T_700; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_702 = _csignals_T_71 ? 3'h0 : _csignals_T_701; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_703 = _csignals_T_69 ? 3'h0 : _csignals_T_702; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_704 = _csignals_T_67 ? 3'h0 : _csignals_T_703; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_705 = _csignals_T_65 ? 3'h0 : _csignals_T_704; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_706 = _csignals_T_63 ? 3'h0 : _csignals_T_705; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_707 = _csignals_T_61 ? 3'h0 : _csignals_T_706; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_708 = _csignals_T_59 ? 3'h0 : _csignals_T_707; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_709 = _csignals_T_57 ? 3'h0 : _csignals_T_708; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_710 = _csignals_T_55 ? 3'h0 : _csignals_T_709; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_711 = _csignals_T_53 ? 3'h0 : _csignals_T_710; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_712 = _csignals_T_51 ? 3'h0 : _csignals_T_711; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_713 = _csignals_T_49 ? 3'h0 : _csignals_T_712; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_714 = _csignals_T_47 ? 3'h0 : _csignals_T_713; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_715 = _csignals_T_45 ? 3'h0 : _csignals_T_714; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_716 = _csignals_T_43 ? 3'h0 : _csignals_T_715; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_717 = _csignals_T_41 ? 3'h0 : _csignals_T_716; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_718 = _csignals_T_39 ? 3'h0 : _csignals_T_717; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_719 = _csignals_T_37 ? 3'h0 : _csignals_T_718; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_720 = _csignals_T_35 ? 3'h0 : _csignals_T_719; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_721 = _csignals_T_33 ? 3'h0 : _csignals_T_720; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_722 = _csignals_T_31 ? 3'h0 : _csignals_T_721; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_723 = _csignals_T_29 ? 3'h0 : _csignals_T_722; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_724 = _csignals_T_27 ? 3'h0 : _csignals_T_723; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_725 = _csignals_T_25 ? 3'h0 : _csignals_T_724; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_726 = _csignals_T_23 ? 3'h0 : _csignals_T_725; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_727 = _csignals_T_21 ? 3'h0 : _csignals_T_726; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_728 = _csignals_T_19 ? 3'h0 : _csignals_T_727; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_729 = _csignals_T_17 ? 3'h0 : _csignals_T_728; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_730 = _csignals_T_15 ? 3'h0 : _csignals_T_729; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_731 = _csignals_T_13 ? 3'h0 : _csignals_T_730; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_732 = _csignals_T_11 ? 3'h0 : _csignals_T_731; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_733 = _csignals_T_9 ? 3'h0 : _csignals_T_732; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_734 = _csignals_T_7 ? 3'h0 : _csignals_T_733; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_735 = _csignals_T_5 ? 3'h0 : _csignals_T_734; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_736 = _csignals_T_3 ? 3'h0 : _csignals_T_735; // @[Lookup.scala:31:38, :34:39]
wire [2:0] csignals_12 = _csignals_T_1 ? 3'h0 : _csignals_T_736; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_737 = {1'h0, _csignals_T_99, 1'h0}; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_738 = _csignals_T_97 ? 3'h1 : _csignals_T_737; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_739 = _csignals_T_95 ? 3'h4 : _csignals_T_738; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_740 = _csignals_T_93 ? 3'h4 : _csignals_T_739; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_741 = _csignals_T_91 ? 3'h4 : _csignals_T_740; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_742 = _csignals_T_89 ? 3'h4 : _csignals_T_741; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_743 = _csignals_T_87 ? 3'h4 : _csignals_T_742; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_744 = _csignals_T_85 ? 3'h0 : _csignals_T_743; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_745 = _csignals_T_83 ? 3'h0 : _csignals_T_744; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_746 = _csignals_T_81 ? 3'h0 : _csignals_T_745; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_747 = _csignals_T_79 ? 3'h0 : _csignals_T_746; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_748 = _csignals_T_77 ? 3'h0 : _csignals_T_747; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_749 = _csignals_T_75 ? 3'h0 : _csignals_T_748; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_750 = _csignals_T_73 ? 3'h0 : _csignals_T_749; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_751 = _csignals_T_71 ? 3'h0 : _csignals_T_750; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_752 = _csignals_T_69 ? 3'h0 : _csignals_T_751; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_753 = _csignals_T_67 ? 3'h0 : _csignals_T_752; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_754 = _csignals_T_65 ? 3'h0 : _csignals_T_753; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_755 = _csignals_T_63 ? 3'h0 : _csignals_T_754; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_756 = _csignals_T_61 ? 3'h0 : _csignals_T_755; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_757 = _csignals_T_59 ? 3'h0 : _csignals_T_756; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_758 = _csignals_T_57 ? 3'h0 : _csignals_T_757; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_759 = _csignals_T_55 ? 3'h0 : _csignals_T_758; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_760 = _csignals_T_53 ? 3'h0 : _csignals_T_759; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_761 = _csignals_T_51 ? 3'h0 : _csignals_T_760; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_762 = _csignals_T_49 ? 3'h0 : _csignals_T_761; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_763 = _csignals_T_47 ? 3'h0 : _csignals_T_762; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_764 = _csignals_T_45 ? 3'h0 : _csignals_T_763; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_765 = _csignals_T_43 ? 3'h0 : _csignals_T_764; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_766 = _csignals_T_41 ? 3'h0 : _csignals_T_765; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_767 = _csignals_T_39 ? 3'h0 : _csignals_T_766; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_768 = _csignals_T_37 ? 3'h0 : _csignals_T_767; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_769 = _csignals_T_35 ? 3'h0 : _csignals_T_768; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_770 = _csignals_T_33 ? 3'h0 : _csignals_T_769; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_771 = _csignals_T_31 ? 3'h0 : _csignals_T_770; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_772 = _csignals_T_29 ? 3'h0 : _csignals_T_771; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_773 = _csignals_T_27 ? 3'h0 : _csignals_T_772; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_774 = _csignals_T_25 ? 3'h0 : _csignals_T_773; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_775 = _csignals_T_23 ? 3'h0 : _csignals_T_774; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_776 = _csignals_T_21 ? 3'h0 : _csignals_T_775; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_777 = _csignals_T_19 ? 3'h0 : _csignals_T_776; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_778 = _csignals_T_17 ? 3'h0 : _csignals_T_777; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_779 = _csignals_T_15 ? 3'h0 : _csignals_T_778; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_780 = _csignals_T_13 ? 3'h0 : _csignals_T_779; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_781 = _csignals_T_11 ? 3'h0 : _csignals_T_780; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_782 = _csignals_T_9 ? 3'h0 : _csignals_T_781; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_783 = _csignals_T_7 ? 3'h0 : _csignals_T_782; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_784 = _csignals_T_5 ? 3'h0 : _csignals_T_783; // @[Lookup.scala:31:38, :34:39]
wire [2:0] _csignals_T_785 = _csignals_T_3 ? 3'h0 : _csignals_T_784; // @[Lookup.scala:31:38, :34:39]
wire [2:0] csignals_13 = _csignals_T_1 ? 3'h0 : _csignals_T_785; // @[Lookup.scala:31:38, :34:39]
wire _take_evec_T_1; // @[cpath.scala:199:60]
assign io_imem_exe_kill_0 = take_evec; // @[cpath.scala:52:7, :135:24]
assign io_ctl_exe_kill_0 = take_evec; // @[cpath.scala:52:7, :135:24]
wire _ctrl_pc_sel_T = csignals_1 == 4'h0; // @[Lookup.scala:34:39]
wire _ctrl_pc_sel_T_1 = csignals_1 == 4'h1; // @[Lookup.scala:34:39]
wire _ctrl_pc_sel_T_2 = ~io_dat_br_eq_0; // @[cpath.scala:52:7, :140:54]
wire [2:0] _ctrl_pc_sel_T_3 = {2'h0, _ctrl_pc_sel_T_2}; // @[cpath.scala:140:{53,54}]
wire _ctrl_pc_sel_T_4 = csignals_1 == 4'h2; // @[Lookup.scala:34:39]
wire [2:0] _ctrl_pc_sel_T_5 = {2'h0, io_dat_br_eq_0}; // @[cpath.scala:52:7, :141:53]
wire _ctrl_pc_sel_T_6 = csignals_1 == 4'h3; // @[Lookup.scala:34:39]
wire _ctrl_pc_sel_T_7 = ~io_dat_br_lt_0; // @[cpath.scala:52:7, :142:54]
wire [2:0] _ctrl_pc_sel_T_8 = {2'h0, _ctrl_pc_sel_T_7}; // @[cpath.scala:142:{53,54}]
wire _ctrl_pc_sel_T_9 = csignals_1 == 4'h4; // @[Lookup.scala:34:39]
wire _ctrl_pc_sel_T_10 = ~io_dat_br_ltu_0; // @[cpath.scala:52:7, :143:54]
wire [2:0] _ctrl_pc_sel_T_11 = {2'h0, _ctrl_pc_sel_T_10}; // @[cpath.scala:143:{53,54}]
wire _ctrl_pc_sel_T_12 = csignals_1 == 4'h5; // @[Lookup.scala:34:39]
wire [2:0] _ctrl_pc_sel_T_13 = {2'h0, io_dat_br_lt_0}; // @[cpath.scala:52:7, :144:53]
wire _ctrl_pc_sel_T_14 = csignals_1 == 4'h6; // @[Lookup.scala:34:39]
wire [2:0] _ctrl_pc_sel_T_15 = {2'h0, io_dat_br_ltu_0}; // @[cpath.scala:52:7, :145:53]
wire _ctrl_pc_sel_T_16 = csignals_1 == 4'h7; // @[Lookup.scala:34:39]
wire _ctrl_pc_sel_T_17 = csignals_1 == 4'h8; // @[Lookup.scala:34:39]
wire [2:0] _ctrl_pc_sel_T_18 = _ctrl_pc_sel_T_17 ? 3'h3 : 3'h0; // @[cpath.scala:147:{25,37}]
wire [2:0] _ctrl_pc_sel_T_19 = _ctrl_pc_sel_T_16 ? 3'h2 : _ctrl_pc_sel_T_18; // @[cpath.scala:146:{25,37}, :147:25]
wire [2:0] _ctrl_pc_sel_T_20 = _ctrl_pc_sel_T_14 ? _ctrl_pc_sel_T_15 : _ctrl_pc_sel_T_19; // @[cpath.scala:145:{25,37,53}, :146:25]
wire [2:0] _ctrl_pc_sel_T_21 = _ctrl_pc_sel_T_12 ? _ctrl_pc_sel_T_13 : _ctrl_pc_sel_T_20; // @[cpath.scala:144:{25,37,53}, :145:25]
wire [2:0] _ctrl_pc_sel_T_22 = _ctrl_pc_sel_T_9 ? _ctrl_pc_sel_T_11 : _ctrl_pc_sel_T_21; // @[cpath.scala:143:{25,37,53}, :144:25]
wire [2:0] _ctrl_pc_sel_T_23 = _ctrl_pc_sel_T_6 ? _ctrl_pc_sel_T_8 : _ctrl_pc_sel_T_22; // @[cpath.scala:142:{25,37,53}, :143:25]
wire [2:0] _ctrl_pc_sel_T_24 = _ctrl_pc_sel_T_4 ? _ctrl_pc_sel_T_5 : _ctrl_pc_sel_T_23; // @[cpath.scala:141:{25,37,53}, :142:25]
wire [2:0] _ctrl_pc_sel_T_25 = _ctrl_pc_sel_T_1 ? _ctrl_pc_sel_T_3 : _ctrl_pc_sel_T_24; // @[cpath.scala:140:{25,37,53}, :141:25]
wire [2:0] _ctrl_pc_sel_T_26 = _ctrl_pc_sel_T ? 3'h0 : _ctrl_pc_sel_T_25; // @[cpath.scala:139:{25,37}, :140:25]
assign ctrl_pc_sel = take_evec ? 3'h4 : _ctrl_pc_sel_T_26; // @[cpath.scala:135:24, :138:25, :139:25]
assign io_ctl_pc_sel_0 = ctrl_pc_sel; // @[cpath.scala:52:7, :138:25]
wire _io_imem_req_valid_T = ctrl_pc_sel == 3'h0; // @[cpath.scala:138:25, :151:41]
wire _io_imem_req_valid_T_1 = ~_io_imem_req_valid_T; // @[cpath.scala:151:{27,41}]
wire _io_imem_req_valid_T_2 = _io_imem_req_valid_T_1 & io_imem_resp_valid_0; // @[cpath.scala:52:7, :151:{27,51}]
wire _io_imem_req_valid_T_3 = ~io_dat_wb_hazard_stall_0; // @[cpath.scala:52:7, :151:68]
wire _io_imem_req_valid_T_4 = _io_imem_req_valid_T_2 & _io_imem_req_valid_T_3; // @[cpath.scala:151:{51,65,68}]
wire _io_imem_req_valid_T_5 = ctrl_pc_sel == 3'h4; // @[cpath.scala:138:25, :151:108]
assign _io_imem_req_valid_T_6 = _io_imem_req_valid_T_4 | _io_imem_req_valid_T_5; // @[cpath.scala:151:{65,93,108}]
assign io_imem_req_valid_0 = _io_imem_req_valid_T_6; // @[cpath.scala:52:7, :151:93]
wire _io_ctl_rf_wen_T = ~io_imem_resp_valid_0; // @[cpath.scala:52:7, :161:29]
assign _io_ctl_rf_wen_T_1 = ~_io_ctl_rf_wen_T & csignals_7; // @[Lookup.scala:34:39]
assign io_ctl_rf_wen_0 = _io_ctl_rf_wen_T_1; // @[cpath.scala:52:7, :161:28]
wire [4:0] rs1_addr = io_imem_resp_bits_inst_0[19:15]; // @[cpath.scala:52:7, :164:41]
wire _csr_ren_T = csignals_12 == 3'h6; // @[Lookup.scala:34:39]
wire _csr_ren_T_1 = &csignals_12; // @[Lookup.scala:34:39]
wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[cpath.scala:165:{30,40,54}]
wire _csr_ren_T_3 = rs1_addr == 5'h0; // @[cpath.scala:164:41, :165:77]
wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[cpath.scala:165:{40,65,77}]
wire [2:0] csr_cmd = csr_ren ? 3'h2 : csignals_12; // @[Lookup.scala:34:39]
wire _io_ctl_csr_cmd_T = ~io_imem_resp_valid_0; // @[cpath.scala:52:7, :161:29, :167:29]
assign _io_ctl_csr_cmd_T_1 = _io_ctl_csr_cmd_T ? 3'h0 : csr_cmd; // @[cpath.scala:166:21, :167:{28,29}]
assign io_ctl_csr_cmd_0 = _io_ctl_csr_cmd_T_1; // @[cpath.scala:52:7, :167:28]
assign _io_ctl_dmem_val_T = csignals_9 & io_imem_resp_valid_0; // @[Lookup.scala:34:39]
assign io_ctl_dmem_val_0 = _io_ctl_dmem_val_T; // @[cpath.scala:52:7, :173:38]
wire _exe_illegal_T = ~csignals_0; // @[Lookup.scala:34:39]
wire exe_illegal = _exe_illegal_T & io_imem_resp_valid_0; // @[cpath.scala:52:7, :181:{22,35}]
reg wb_reg_illegal; // @[cpath.scala:184:32]
reg wb_reg_data_misaligned; // @[cpath.scala:185:40]
reg wb_reg_inst_misaligned; // @[cpath.scala:186:40]
reg wb_reg_mem_fcn; // @[cpath.scala:187:32]
wire _io_ctl_exception_cause_T = wb_reg_mem_fcn; // @[cpath.scala:187:32, :204:50]
wire _take_evec_T = io_ctl_exception_0 | io_dat_csr_eret_0; // @[cpath.scala:52:7, :199:41]
assign _take_evec_T_1 = _take_evec_T | io_dat_csr_interrupt_0; // @[cpath.scala:52:7, :199:{41,60}]
assign take_evec = _take_evec_T_1; // @[cpath.scala:135:24, :199:60]
wire _io_ctl_exception_T = wb_reg_illegal | wb_reg_inst_misaligned; // @[cpath.scala:184:32, :186:40, :201:40]
wire _io_ctl_exception_T_1 = _io_ctl_exception_T | wb_reg_data_misaligned; // @[cpath.scala:185:40, :201:{40,66}]
wire _io_ctl_exception_T_2 = ~io_dat_csr_eret_0; // @[cpath.scala:52:7, :201:96]
assign _io_ctl_exception_T_3 = _io_ctl_exception_T_1 & _io_ctl_exception_T_2; // @[cpath.scala:201:{66,93,96}]
assign io_ctl_exception_0 = _io_ctl_exception_T_3; // @[cpath.scala:52:7, :201:93]
wire [2:0] _io_ctl_exception_cause_T_1 = {1'h1, _io_ctl_exception_cause_T, 1'h0}; // @[cpath.scala:204:{34,50}]
wire [2:0] _io_ctl_exception_cause_T_2 = wb_reg_inst_misaligned ? 3'h0 : _io_ctl_exception_cause_T_1; // @[cpath.scala:186:40, :203:34, :204:34]
wire [2:0] _io_ctl_exception_cause_T_3 = wb_reg_illegal ? 3'h2 : _io_ctl_exception_cause_T_2; // @[cpath.scala:184:32, :202:34, :203:34]
assign io_ctl_exception_cause_0 = {29'h0, _io_ctl_exception_cause_T_3}; // @[cpath.scala:52:7, :202:{27,34}]
wire _T = io_dat_wb_hazard_stall_0 | io_ctl_exe_kill_0; // @[cpath.scala:52:7, :192:33]
always @(posedge clock) begin // @[cpath.scala:52:7]
if (reset) begin // @[cpath.scala:52:7]
wb_reg_illegal <= 1'h0; // @[cpath.scala:184:32]
wb_reg_data_misaligned <= 1'h0; // @[cpath.scala:185:40]
wb_reg_inst_misaligned <= 1'h0; // @[cpath.scala:186:40]
wb_reg_mem_fcn <= 1'h0; // @[cpath.scala:187:32]
end
else begin // @[cpath.scala:52:7]
wb_reg_illegal <= ~_T & exe_illegal; // @[cpath.scala:181:35, :184:32, :188:19, :192:{33,53}, :193:22]
wb_reg_data_misaligned <= ~_T & io_dat_data_misaligned_0; // @[cpath.scala:52:7, :185:40, :188:19, :189:27, :192:{33,53}, :193:22, :194:30]
wb_reg_inst_misaligned <= ~_T & io_dat_inst_misaligned_0; // @[cpath.scala:52:7, :186:40, :188:19, :190:27, :192:{33,53}, :193:22, :195:30]
wb_reg_mem_fcn <= ~_T & csignals_10; // @[Lookup.scala:34:39]
end
always @(posedge)
assign io_imem_req_valid = io_imem_req_valid_0; // @[cpath.scala:52:7]
assign io_imem_exe_kill = io_imem_exe_kill_0; // @[cpath.scala:52:7]
assign io_ctl_exe_kill = io_ctl_exe_kill_0; // @[cpath.scala:52:7]
assign io_ctl_pc_sel = io_ctl_pc_sel_0; // @[cpath.scala:52:7]
assign io_ctl_brjmp_sel = io_ctl_brjmp_sel_0; // @[cpath.scala:52:7]
assign io_ctl_op1_sel = io_ctl_op1_sel_0; // @[cpath.scala:52:7]
assign io_ctl_op2_sel = io_ctl_op2_sel_0; // @[cpath.scala:52:7]
assign io_ctl_alu_fun = io_ctl_alu_fun_0; // @[cpath.scala:52:7]
assign io_ctl_wb_sel = io_ctl_wb_sel_0; // @[cpath.scala:52:7]
assign io_ctl_rf_wen = io_ctl_rf_wen_0; // @[cpath.scala:52:7]
assign io_ctl_bypassable = io_ctl_bypassable_0; // @[cpath.scala:52:7]
assign io_ctl_csr_cmd = io_ctl_csr_cmd_0; // @[cpath.scala:52:7]
assign io_ctl_dmem_val = io_ctl_dmem_val_0; // @[cpath.scala:52:7]
assign io_ctl_dmem_fcn = io_ctl_dmem_fcn_0; // @[cpath.scala:52:7]
assign io_ctl_dmem_typ = io_ctl_dmem_typ_0; // @[cpath.scala:52:7]
assign io_ctl_exception = io_ctl_exception_0; // @[cpath.scala:52:7]
assign io_ctl_exception_cause = io_ctl_exception_cause_0; // @[cpath.scala:52:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_214 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_214( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a22d64s7k1z3u_1 :
input clock : Clock
input reset : Reset
output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset full : UInt<1>, clock, reset, UInt<1>(0h0)
reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<22>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
node _io_deq_valid_T = or(io.enq.valid, full)
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T)
connect io.enq.ready, _io_enq_ready_T_1
node _io_deq_bits_T = mux(full, saved, io.enq.bits)
connect io.deq.bits, _io_deq_bits_T
connect io.full, full
node _T = and(io.enq.ready, io.enq.valid)
node _T_1 = and(_T, io.repeat)
when _T_1 :
connect full, UInt<1>(0h1)
connect saved, io.enq.bits
node _T_2 = and(io.deq.ready, io.deq.valid)
node _T_3 = eq(io.repeat, UInt<1>(0h0))
node _T_4 = and(_T_2, _T_3)
when _T_4 :
connect full, UInt<1>(0h0) | module Repeater_TLBundleA_a22d64s7k1z3u_1( // @[Repeater.scala:10:7]
input clock, // @[Repeater.scala:10:7]
input reset, // @[Repeater.scala:10:7]
input io_repeat, // @[Repeater.scala:13:14]
output io_full, // @[Repeater.scala:13:14]
output io_enq_ready, // @[Repeater.scala:13:14]
input io_enq_valid, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14]
input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14]
input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14]
input [21:0] io_enq_bits_address, // @[Repeater.scala:13:14]
input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14]
input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14]
input io_enq_bits_corrupt, // @[Repeater.scala:13:14]
input io_deq_ready, // @[Repeater.scala:13:14]
output io_deq_valid, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14]
output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14]
output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14]
output [21:0] io_deq_bits_address, // @[Repeater.scala:13:14]
output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14]
output io_deq_bits_corrupt // @[Repeater.scala:13:14]
);
wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7]
wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7]
wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7]
wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7]
wire [21:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7]
wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7]
wire _io_enq_ready_T_1; // @[Repeater.scala:25:32]
wire _io_deq_valid_T; // @[Repeater.scala:24:32]
wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21]
wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21]
wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21]
wire [21:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21]
wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21]
wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21]
wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21]
wire io_enq_ready_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7]
wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7]
wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7]
wire [21:0] io_deq_bits_address_0; // @[Repeater.scala:10:7]
wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7]
wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7]
wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
wire io_deq_valid_0; // @[Repeater.scala:10:7]
wire io_full_0; // @[Repeater.scala:10:7]
reg full; // @[Repeater.scala:20:21]
assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21]
reg [2:0] saved_opcode; // @[Repeater.scala:21:18]
reg [2:0] saved_param; // @[Repeater.scala:21:18]
reg [2:0] saved_size; // @[Repeater.scala:21:18]
reg [6:0] saved_source; // @[Repeater.scala:21:18]
reg [21:0] saved_address; // @[Repeater.scala:21:18]
reg [7:0] saved_mask; // @[Repeater.scala:21:18]
reg [63:0] saved_data; // @[Repeater.scala:21:18]
reg saved_corrupt; // @[Repeater.scala:21:18]
assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32]
wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35]
assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}]
assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32]
assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21]
assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21]
assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21]
wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Repeater.scala:10:7]
if (reset) // @[Repeater.scala:10:7]
full <= 1'h0; // @[Repeater.scala:20:21]
else // @[Repeater.scala:10:7]
full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35]
if (_T_1) begin // @[Decoupled.scala:51:35]
saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18]
saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18]
saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18]
saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18]
saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18]
saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18]
saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18]
saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18]
end
always @(posedge)
assign io_full = io_full_0; // @[Repeater.scala:10:7]
assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7]
assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7]
assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7]
assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7]
assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7]
assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7]
assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_13 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<12>(0h800)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<16>(0h8000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<17>(0h10000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<27>(0h4000000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<13>(0h1000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = or(_T_100, _T_105)
node _T_147 = or(_T_146, _T_110)
node _T_148 = or(_T_147, _T_115)
node _T_149 = or(_T_148, _T_120)
node _T_150 = or(_T_149, _T_125)
node _T_151 = or(_T_150, _T_130)
node _T_152 = or(_T_151, _T_135)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_145)
node _T_155 = and(_T_95, _T_154)
node _T_156 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_157 = or(UInt<1>(0h0), _T_156)
node _T_158 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_159 = cvt(_T_158)
node _T_160 = and(_T_159, asSInt(UInt<17>(0h10000)))
node _T_161 = asSInt(_T_160)
node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<29>(0h10000000)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = or(_T_162, _T_167)
node _T_169 = and(_T_157, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_155)
node _T_171 = or(_T_170, _T_169)
node _T_172 = and(_T_94, _T_171)
node _T_173 = asUInt(reset)
node _T_174 = eq(_T_173, UInt<1>(0h0))
when _T_174 :
node _T_175 = eq(_T_172, UInt<1>(0h0))
when _T_175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_172, UInt<1>(0h1), "") : assert_2
node _T_176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_177 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_178 = and(_T_176, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_181 = cvt(_T_180)
node _T_182 = and(_T_181, asSInt(UInt<14>(0h2000)))
node _T_183 = asSInt(_T_182)
node _T_184 = eq(_T_183, asSInt(UInt<1>(0h0)))
node _T_185 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_186 = cvt(_T_185)
node _T_187 = and(_T_186, asSInt(UInt<13>(0h1000)))
node _T_188 = asSInt(_T_187)
node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0)))
node _T_190 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_191 = cvt(_T_190)
node _T_192 = and(_T_191, asSInt(UInt<17>(0h10000)))
node _T_193 = asSInt(_T_192)
node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0)))
node _T_195 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_196 = cvt(_T_195)
node _T_197 = and(_T_196, asSInt(UInt<18>(0h2f000)))
node _T_198 = asSInt(_T_197)
node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0)))
node _T_200 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_201 = cvt(_T_200)
node _T_202 = and(_T_201, asSInt(UInt<12>(0h800)))
node _T_203 = asSInt(_T_202)
node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_206 = cvt(_T_205)
node _T_207 = and(_T_206, asSInt(UInt<16>(0h8000)))
node _T_208 = asSInt(_T_207)
node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0)))
node _T_210 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<17>(0h10000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<27>(0h4000000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<13>(0h1000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<29>(0h10000000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = or(_T_184, _T_189)
node _T_241 = or(_T_240, _T_194)
node _T_242 = or(_T_241, _T_199)
node _T_243 = or(_T_242, _T_204)
node _T_244 = or(_T_243, _T_209)
node _T_245 = or(_T_244, _T_214)
node _T_246 = or(_T_245, _T_219)
node _T_247 = or(_T_246, _T_224)
node _T_248 = or(_T_247, _T_229)
node _T_249 = or(_T_248, _T_234)
node _T_250 = or(_T_249, _T_239)
node _T_251 = and(_T_179, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(UInt<1>(0h0), _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_253, UInt<1>(0h1), "") : assert_3
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(source_ok, UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_260 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_260, UInt<1>(0h1), "") : assert_5
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(is_aligned, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_267 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_267, UInt<1>(0h1), "") : assert_7
node _T_271 = not(io.in.a.bits.mask)
node _T_272 = eq(_T_271, UInt<1>(0h0))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_272, UInt<1>(0h1), "") : assert_8
node _T_276 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_277 = asUInt(reset)
node _T_278 = eq(_T_277, UInt<1>(0h0))
when _T_278 :
node _T_279 = eq(_T_276, UInt<1>(0h0))
when _T_279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_276, UInt<1>(0h1), "") : assert_9
node _T_280 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_280 :
node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_283 = and(_T_281, _T_282)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_290 = shr(io.in.a.bits.source, 2)
node _T_291 = eq(_T_290, UInt<1>(0h1))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_295 = and(_T_293, _T_294)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_296 = shr(io.in.a.bits.source, 2)
node _T_297 = eq(_T_296, UInt<2>(0h2))
node _T_298 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_299 = and(_T_297, _T_298)
node _T_300 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_301 = and(_T_299, _T_300)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<2>(0h3))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _T_308 = or(_T_289, _T_295)
node _T_309 = or(_T_308, _T_301)
node _T_310 = or(_T_309, _T_307)
node _T_311 = and(_T_283, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_314 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<14>(0h2000)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<18>(0h2f000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<12>(0h800)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<16>(0h8000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<17>(0h10000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<27>(0h4000000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<13>(0h1000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = or(_T_318, _T_323)
node _T_365 = or(_T_364, _T_328)
node _T_366 = or(_T_365, _T_333)
node _T_367 = or(_T_366, _T_338)
node _T_368 = or(_T_367, _T_343)
node _T_369 = or(_T_368, _T_348)
node _T_370 = or(_T_369, _T_353)
node _T_371 = or(_T_370, _T_358)
node _T_372 = or(_T_371, _T_363)
node _T_373 = and(_T_313, _T_372)
node _T_374 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_375 = or(UInt<1>(0h0), _T_374)
node _T_376 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_377 = cvt(_T_376)
node _T_378 = and(_T_377, asSInt(UInt<17>(0h10000)))
node _T_379 = asSInt(_T_378)
node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0)))
node _T_381 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_382 = cvt(_T_381)
node _T_383 = and(_T_382, asSInt(UInt<29>(0h10000000)))
node _T_384 = asSInt(_T_383)
node _T_385 = eq(_T_384, asSInt(UInt<1>(0h0)))
node _T_386 = or(_T_380, _T_385)
node _T_387 = and(_T_375, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_373)
node _T_389 = or(_T_388, _T_387)
node _T_390 = and(_T_312, _T_389)
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_390, UInt<1>(0h1), "") : assert_10
node _T_394 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_395 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_396 = and(_T_394, _T_395)
node _T_397 = or(UInt<1>(0h0), _T_396)
node _T_398 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_399 = cvt(_T_398)
node _T_400 = and(_T_399, asSInt(UInt<14>(0h2000)))
node _T_401 = asSInt(_T_400)
node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0)))
node _T_403 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_404 = cvt(_T_403)
node _T_405 = and(_T_404, asSInt(UInt<13>(0h1000)))
node _T_406 = asSInt(_T_405)
node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0)))
node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<12>(0h800)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<16>(0h8000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<13>(0h1000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<17>(0h10000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<27>(0h4000000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<13>(0h1000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_454 = cvt(_T_453)
node _T_455 = and(_T_454, asSInt(UInt<29>(0h10000000)))
node _T_456 = asSInt(_T_455)
node _T_457 = eq(_T_456, asSInt(UInt<1>(0h0)))
node _T_458 = or(_T_402, _T_407)
node _T_459 = or(_T_458, _T_412)
node _T_460 = or(_T_459, _T_417)
node _T_461 = or(_T_460, _T_422)
node _T_462 = or(_T_461, _T_427)
node _T_463 = or(_T_462, _T_432)
node _T_464 = or(_T_463, _T_437)
node _T_465 = or(_T_464, _T_442)
node _T_466 = or(_T_465, _T_447)
node _T_467 = or(_T_466, _T_452)
node _T_468 = or(_T_467, _T_457)
node _T_469 = and(_T_397, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = and(UInt<1>(0h0), _T_470)
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_471, UInt<1>(0h1), "") : assert_11
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(source_ok, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_478 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_478, UInt<1>(0h1), "") : assert_13
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(is_aligned, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_485 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_485, UInt<1>(0h1), "") : assert_15
node _T_489 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_489, UInt<1>(0h1), "") : assert_16
node _T_493 = not(io.in.a.bits.mask)
node _T_494 = eq(_T_493, UInt<1>(0h0))
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_494, UInt<1>(0h1), "") : assert_17
node _T_498 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_498, UInt<1>(0h1), "") : assert_18
node _T_502 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_502 :
node _T_503 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_504 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_505 = and(_T_503, _T_504)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_506 = shr(io.in.a.bits.source, 2)
node _T_507 = eq(_T_506, UInt<1>(0h0))
node _T_508 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_509 = and(_T_507, _T_508)
node _T_510 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_511 = and(_T_509, _T_510)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_512 = shr(io.in.a.bits.source, 2)
node _T_513 = eq(_T_512, UInt<1>(0h1))
node _T_514 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_515 = and(_T_513, _T_514)
node _T_516 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_517 = and(_T_515, _T_516)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_518 = shr(io.in.a.bits.source, 2)
node _T_519 = eq(_T_518, UInt<2>(0h2))
node _T_520 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_521 = and(_T_519, _T_520)
node _T_522 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_523 = and(_T_521, _T_522)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_524 = shr(io.in.a.bits.source, 2)
node _T_525 = eq(_T_524, UInt<2>(0h3))
node _T_526 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_527 = and(_T_525, _T_526)
node _T_528 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_529 = and(_T_527, _T_528)
node _T_530 = or(_T_511, _T_517)
node _T_531 = or(_T_530, _T_523)
node _T_532 = or(_T_531, _T_529)
node _T_533 = and(_T_505, _T_532)
node _T_534 = or(UInt<1>(0h0), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_534, UInt<1>(0h1), "") : assert_19
node _T_538 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_539 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_540 = and(_T_538, _T_539)
node _T_541 = or(UInt<1>(0h0), _T_540)
node _T_542 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_543 = cvt(_T_542)
node _T_544 = and(_T_543, asSInt(UInt<13>(0h1000)))
node _T_545 = asSInt(_T_544)
node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0)))
node _T_547 = and(_T_541, _T_546)
node _T_548 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_549 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_550 = and(_T_548, _T_549)
node _T_551 = or(UInt<1>(0h0), _T_550)
node _T_552 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_553 = cvt(_T_552)
node _T_554 = and(_T_553, asSInt(UInt<14>(0h2000)))
node _T_555 = asSInt(_T_554)
node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0)))
node _T_557 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_558 = cvt(_T_557)
node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000)))
node _T_560 = asSInt(_T_559)
node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0)))
node _T_562 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<18>(0h2f000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<12>(0h800)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<16>(0h8000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<13>(0h1000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<27>(0h4000000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<13>(0h1000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_603 = cvt(_T_602)
node _T_604 = and(_T_603, asSInt(UInt<29>(0h10000000)))
node _T_605 = asSInt(_T_604)
node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0)))
node _T_607 = or(_T_556, _T_561)
node _T_608 = or(_T_607, _T_566)
node _T_609 = or(_T_608, _T_571)
node _T_610 = or(_T_609, _T_576)
node _T_611 = or(_T_610, _T_581)
node _T_612 = or(_T_611, _T_586)
node _T_613 = or(_T_612, _T_591)
node _T_614 = or(_T_613, _T_596)
node _T_615 = or(_T_614, _T_601)
node _T_616 = or(_T_615, _T_606)
node _T_617 = and(_T_551, _T_616)
node _T_618 = or(UInt<1>(0h0), _T_547)
node _T_619 = or(_T_618, _T_617)
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(_T_619, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_619, UInt<1>(0h1), "") : assert_20
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(source_ok, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(is_aligned, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_629 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_630 = asUInt(reset)
node _T_631 = eq(_T_630, UInt<1>(0h0))
when _T_631 :
node _T_632 = eq(_T_629, UInt<1>(0h0))
when _T_632 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_629, UInt<1>(0h1), "") : assert_23
node _T_633 = eq(io.in.a.bits.mask, mask)
node _T_634 = asUInt(reset)
node _T_635 = eq(_T_634, UInt<1>(0h0))
when _T_635 :
node _T_636 = eq(_T_633, UInt<1>(0h0))
when _T_636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_633, UInt<1>(0h1), "") : assert_24
node _T_637 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_638 = asUInt(reset)
node _T_639 = eq(_T_638, UInt<1>(0h0))
when _T_639 :
node _T_640 = eq(_T_637, UInt<1>(0h0))
when _T_640 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_637, UInt<1>(0h1), "") : assert_25
node _T_641 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_641 :
node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_643 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_644 = and(_T_642, _T_643)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<1>(0h0))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<1>(0h1))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<2>(0h2))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_663 = shr(io.in.a.bits.source, 2)
node _T_664 = eq(_T_663, UInt<2>(0h3))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_668 = and(_T_666, _T_667)
node _T_669 = or(_T_650, _T_656)
node _T_670 = or(_T_669, _T_662)
node _T_671 = or(_T_670, _T_668)
node _T_672 = and(_T_644, _T_671)
node _T_673 = or(UInt<1>(0h0), _T_672)
node _T_674 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_675 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_676 = and(_T_674, _T_675)
node _T_677 = or(UInt<1>(0h0), _T_676)
node _T_678 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<13>(0h1000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = and(_T_677, _T_682)
node _T_684 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_685 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_686 = and(_T_684, _T_685)
node _T_687 = or(UInt<1>(0h0), _T_686)
node _T_688 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<14>(0h2000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<18>(0h2f000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_699 = cvt(_T_698)
node _T_700 = and(_T_699, asSInt(UInt<12>(0h800)))
node _T_701 = asSInt(_T_700)
node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0)))
node _T_703 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_704 = cvt(_T_703)
node _T_705 = and(_T_704, asSInt(UInt<16>(0h8000)))
node _T_706 = asSInt(_T_705)
node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0)))
node _T_708 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<17>(0h10000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_714 = cvt(_T_713)
node _T_715 = and(_T_714, asSInt(UInt<13>(0h1000)))
node _T_716 = asSInt(_T_715)
node _T_717 = eq(_T_716, asSInt(UInt<1>(0h0)))
node _T_718 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_719 = cvt(_T_718)
node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000)))
node _T_721 = asSInt(_T_720)
node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0)))
node _T_723 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_724 = cvt(_T_723)
node _T_725 = and(_T_724, asSInt(UInt<27>(0h4000000)))
node _T_726 = asSInt(_T_725)
node _T_727 = eq(_T_726, asSInt(UInt<1>(0h0)))
node _T_728 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_729 = cvt(_T_728)
node _T_730 = and(_T_729, asSInt(UInt<13>(0h1000)))
node _T_731 = asSInt(_T_730)
node _T_732 = eq(_T_731, asSInt(UInt<1>(0h0)))
node _T_733 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_734 = cvt(_T_733)
node _T_735 = and(_T_734, asSInt(UInt<29>(0h10000000)))
node _T_736 = asSInt(_T_735)
node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0)))
node _T_738 = or(_T_692, _T_697)
node _T_739 = or(_T_738, _T_702)
node _T_740 = or(_T_739, _T_707)
node _T_741 = or(_T_740, _T_712)
node _T_742 = or(_T_741, _T_717)
node _T_743 = or(_T_742, _T_722)
node _T_744 = or(_T_743, _T_727)
node _T_745 = or(_T_744, _T_732)
node _T_746 = or(_T_745, _T_737)
node _T_747 = and(_T_687, _T_746)
node _T_748 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_749 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = and(_T_748, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_683)
node _T_756 = or(_T_755, _T_747)
node _T_757 = or(_T_756, _T_754)
node _T_758 = and(_T_673, _T_757)
node _T_759 = asUInt(reset)
node _T_760 = eq(_T_759, UInt<1>(0h0))
when _T_760 :
node _T_761 = eq(_T_758, UInt<1>(0h0))
when _T_761 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_758, UInt<1>(0h1), "") : assert_26
node _T_762 = asUInt(reset)
node _T_763 = eq(_T_762, UInt<1>(0h0))
when _T_763 :
node _T_764 = eq(source_ok, UInt<1>(0h0))
when _T_764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(is_aligned, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_768 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_768, UInt<1>(0h1), "") : assert_29
node _T_772 = eq(io.in.a.bits.mask, mask)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_772, UInt<1>(0h1), "") : assert_30
node _T_776 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_776 :
node _T_777 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_778 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_780 = shr(io.in.a.bits.source, 2)
node _T_781 = eq(_T_780, UInt<1>(0h0))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_785 = and(_T_783, _T_784)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_786 = shr(io.in.a.bits.source, 2)
node _T_787 = eq(_T_786, UInt<1>(0h1))
node _T_788 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_789 = and(_T_787, _T_788)
node _T_790 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_791 = and(_T_789, _T_790)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_792 = shr(io.in.a.bits.source, 2)
node _T_793 = eq(_T_792, UInt<2>(0h2))
node _T_794 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_795 = and(_T_793, _T_794)
node _T_796 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_797 = and(_T_795, _T_796)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_798 = shr(io.in.a.bits.source, 2)
node _T_799 = eq(_T_798, UInt<2>(0h3))
node _T_800 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_801 = and(_T_799, _T_800)
node _T_802 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_803 = and(_T_801, _T_802)
node _T_804 = or(_T_785, _T_791)
node _T_805 = or(_T_804, _T_797)
node _T_806 = or(_T_805, _T_803)
node _T_807 = and(_T_779, _T_806)
node _T_808 = or(UInt<1>(0h0), _T_807)
node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_810 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_811 = and(_T_809, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<13>(0h1000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = and(_T_812, _T_817)
node _T_819 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_820 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_821 = and(_T_819, _T_820)
node _T_822 = or(UInt<1>(0h0), _T_821)
node _T_823 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<14>(0h2000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<18>(0h2f000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<12>(0h800)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<16>(0h8000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<13>(0h1000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<17>(0h10000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_859 = cvt(_T_858)
node _T_860 = and(_T_859, asSInt(UInt<27>(0h4000000)))
node _T_861 = asSInt(_T_860)
node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0)))
node _T_863 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_864 = cvt(_T_863)
node _T_865 = and(_T_864, asSInt(UInt<13>(0h1000)))
node _T_866 = asSInt(_T_865)
node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0)))
node _T_868 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_869 = cvt(_T_868)
node _T_870 = and(_T_869, asSInt(UInt<29>(0h10000000)))
node _T_871 = asSInt(_T_870)
node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0)))
node _T_873 = or(_T_827, _T_832)
node _T_874 = or(_T_873, _T_837)
node _T_875 = or(_T_874, _T_842)
node _T_876 = or(_T_875, _T_847)
node _T_877 = or(_T_876, _T_852)
node _T_878 = or(_T_877, _T_857)
node _T_879 = or(_T_878, _T_862)
node _T_880 = or(_T_879, _T_867)
node _T_881 = or(_T_880, _T_872)
node _T_882 = and(_T_822, _T_881)
node _T_883 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_884 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = and(_T_883, _T_888)
node _T_890 = or(UInt<1>(0h0), _T_818)
node _T_891 = or(_T_890, _T_882)
node _T_892 = or(_T_891, _T_889)
node _T_893 = and(_T_808, _T_892)
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_893, UInt<1>(0h1), "") : assert_31
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(source_ok, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(is_aligned, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_903 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_903, UInt<1>(0h1), "") : assert_34
node _T_907 = not(mask)
node _T_908 = and(io.in.a.bits.mask, _T_907)
node _T_909 = eq(_T_908, UInt<1>(0h0))
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(_T_909, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_909, UInt<1>(0h1), "") : assert_35
node _T_913 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_913 :
node _T_914 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_915 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_916 = and(_T_914, _T_915)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_917 = shr(io.in.a.bits.source, 2)
node _T_918 = eq(_T_917, UInt<1>(0h0))
node _T_919 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_920 = and(_T_918, _T_919)
node _T_921 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_922 = and(_T_920, _T_921)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_923 = shr(io.in.a.bits.source, 2)
node _T_924 = eq(_T_923, UInt<1>(0h1))
node _T_925 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_926 = and(_T_924, _T_925)
node _T_927 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_928 = and(_T_926, _T_927)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_929 = shr(io.in.a.bits.source, 2)
node _T_930 = eq(_T_929, UInt<2>(0h2))
node _T_931 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_932 = and(_T_930, _T_931)
node _T_933 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_934 = and(_T_932, _T_933)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_935 = shr(io.in.a.bits.source, 2)
node _T_936 = eq(_T_935, UInt<2>(0h3))
node _T_937 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_938 = and(_T_936, _T_937)
node _T_939 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_940 = and(_T_938, _T_939)
node _T_941 = or(_T_922, _T_928)
node _T_942 = or(_T_941, _T_934)
node _T_943 = or(_T_942, _T_940)
node _T_944 = and(_T_916, _T_943)
node _T_945 = or(UInt<1>(0h0), _T_944)
node _T_946 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_947 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_948 = and(_T_946, _T_947)
node _T_949 = or(UInt<1>(0h0), _T_948)
node _T_950 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<14>(0h2000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_956 = cvt(_T_955)
node _T_957 = and(_T_956, asSInt(UInt<13>(0h1000)))
node _T_958 = asSInt(_T_957)
node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0)))
node _T_960 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_961 = cvt(_T_960)
node _T_962 = and(_T_961, asSInt(UInt<18>(0h2f000)))
node _T_963 = asSInt(_T_962)
node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0)))
node _T_965 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_966 = cvt(_T_965)
node _T_967 = and(_T_966, asSInt(UInt<12>(0h800)))
node _T_968 = asSInt(_T_967)
node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0)))
node _T_970 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<16>(0h8000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_976 = cvt(_T_975)
node _T_977 = and(_T_976, asSInt(UInt<17>(0h10000)))
node _T_978 = asSInt(_T_977)
node _T_979 = eq(_T_978, asSInt(UInt<1>(0h0)))
node _T_980 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_981 = cvt(_T_980)
node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000)))
node _T_983 = asSInt(_T_982)
node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0)))
node _T_985 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_986 = cvt(_T_985)
node _T_987 = and(_T_986, asSInt(UInt<17>(0h10000)))
node _T_988 = asSInt(_T_987)
node _T_989 = eq(_T_988, asSInt(UInt<1>(0h0)))
node _T_990 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_991 = cvt(_T_990)
node _T_992 = and(_T_991, asSInt(UInt<27>(0h4000000)))
node _T_993 = asSInt(_T_992)
node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0)))
node _T_995 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_996 = cvt(_T_995)
node _T_997 = and(_T_996, asSInt(UInt<13>(0h1000)))
node _T_998 = asSInt(_T_997)
node _T_999 = eq(_T_998, asSInt(UInt<1>(0h0)))
node _T_1000 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1001 = cvt(_T_1000)
node _T_1002 = and(_T_1001, asSInt(UInt<29>(0h10000000)))
node _T_1003 = asSInt(_T_1002)
node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0)))
node _T_1005 = or(_T_954, _T_959)
node _T_1006 = or(_T_1005, _T_964)
node _T_1007 = or(_T_1006, _T_969)
node _T_1008 = or(_T_1007, _T_974)
node _T_1009 = or(_T_1008, _T_979)
node _T_1010 = or(_T_1009, _T_984)
node _T_1011 = or(_T_1010, _T_989)
node _T_1012 = or(_T_1011, _T_994)
node _T_1013 = or(_T_1012, _T_999)
node _T_1014 = or(_T_1013, _T_1004)
node _T_1015 = and(_T_949, _T_1014)
node _T_1016 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1017 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1018 = cvt(_T_1017)
node _T_1019 = and(_T_1018, asSInt(UInt<17>(0h10000)))
node _T_1020 = asSInt(_T_1019)
node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0)))
node _T_1022 = and(_T_1016, _T_1021)
node _T_1023 = or(UInt<1>(0h0), _T_1015)
node _T_1024 = or(_T_1023, _T_1022)
node _T_1025 = and(_T_945, _T_1024)
node _T_1026 = asUInt(reset)
node _T_1027 = eq(_T_1026, UInt<1>(0h0))
when _T_1027 :
node _T_1028 = eq(_T_1025, UInt<1>(0h0))
when _T_1028 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1025, UInt<1>(0h1), "") : assert_36
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(source_ok, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1032 = asUInt(reset)
node _T_1033 = eq(_T_1032, UInt<1>(0h0))
when _T_1033 :
node _T_1034 = eq(is_aligned, UInt<1>(0h0))
when _T_1034 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1035 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_39
node _T_1039 = eq(io.in.a.bits.mask, mask)
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_40
node _T_1043 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1043 :
node _T_1044 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1045 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1046 = and(_T_1044, _T_1045)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1047 = shr(io.in.a.bits.source, 2)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
node _T_1049 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1052 = and(_T_1050, _T_1051)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1053 = shr(io.in.a.bits.source, 2)
node _T_1054 = eq(_T_1053, UInt<1>(0h1))
node _T_1055 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1058 = and(_T_1056, _T_1057)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1059 = shr(io.in.a.bits.source, 2)
node _T_1060 = eq(_T_1059, UInt<2>(0h2))
node _T_1061 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1064 = and(_T_1062, _T_1063)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1065 = shr(io.in.a.bits.source, 2)
node _T_1066 = eq(_T_1065, UInt<2>(0h3))
node _T_1067 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1068 = and(_T_1066, _T_1067)
node _T_1069 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1070 = and(_T_1068, _T_1069)
node _T_1071 = or(_T_1052, _T_1058)
node _T_1072 = or(_T_1071, _T_1064)
node _T_1073 = or(_T_1072, _T_1070)
node _T_1074 = and(_T_1046, _T_1073)
node _T_1075 = or(UInt<1>(0h0), _T_1074)
node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1077 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = or(UInt<1>(0h0), _T_1078)
node _T_1080 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1081 = cvt(_T_1080)
node _T_1082 = and(_T_1081, asSInt(UInt<14>(0h2000)))
node _T_1083 = asSInt(_T_1082)
node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0)))
node _T_1085 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1086 = cvt(_T_1085)
node _T_1087 = and(_T_1086, asSInt(UInt<13>(0h1000)))
node _T_1088 = asSInt(_T_1087)
node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0)))
node _T_1090 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<18>(0h2f000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<12>(0h800)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<16>(0h8000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1106 = cvt(_T_1105)
node _T_1107 = and(_T_1106, asSInt(UInt<17>(0h10000)))
node _T_1108 = asSInt(_T_1107)
node _T_1109 = eq(_T_1108, asSInt(UInt<1>(0h0)))
node _T_1110 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1111 = cvt(_T_1110)
node _T_1112 = and(_T_1111, asSInt(UInt<13>(0h1000)))
node _T_1113 = asSInt(_T_1112)
node _T_1114 = eq(_T_1113, asSInt(UInt<1>(0h0)))
node _T_1115 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1116 = cvt(_T_1115)
node _T_1117 = and(_T_1116, asSInt(UInt<17>(0h10000)))
node _T_1118 = asSInt(_T_1117)
node _T_1119 = eq(_T_1118, asSInt(UInt<1>(0h0)))
node _T_1120 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1121 = cvt(_T_1120)
node _T_1122 = and(_T_1121, asSInt(UInt<27>(0h4000000)))
node _T_1123 = asSInt(_T_1122)
node _T_1124 = eq(_T_1123, asSInt(UInt<1>(0h0)))
node _T_1125 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1126 = cvt(_T_1125)
node _T_1127 = and(_T_1126, asSInt(UInt<13>(0h1000)))
node _T_1128 = asSInt(_T_1127)
node _T_1129 = eq(_T_1128, asSInt(UInt<1>(0h0)))
node _T_1130 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1131 = cvt(_T_1130)
node _T_1132 = and(_T_1131, asSInt(UInt<29>(0h10000000)))
node _T_1133 = asSInt(_T_1132)
node _T_1134 = eq(_T_1133, asSInt(UInt<1>(0h0)))
node _T_1135 = or(_T_1084, _T_1089)
node _T_1136 = or(_T_1135, _T_1094)
node _T_1137 = or(_T_1136, _T_1099)
node _T_1138 = or(_T_1137, _T_1104)
node _T_1139 = or(_T_1138, _T_1109)
node _T_1140 = or(_T_1139, _T_1114)
node _T_1141 = or(_T_1140, _T_1119)
node _T_1142 = or(_T_1141, _T_1124)
node _T_1143 = or(_T_1142, _T_1129)
node _T_1144 = or(_T_1143, _T_1134)
node _T_1145 = and(_T_1079, _T_1144)
node _T_1146 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1147 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1148 = cvt(_T_1147)
node _T_1149 = and(_T_1148, asSInt(UInt<17>(0h10000)))
node _T_1150 = asSInt(_T_1149)
node _T_1151 = eq(_T_1150, asSInt(UInt<1>(0h0)))
node _T_1152 = and(_T_1146, _T_1151)
node _T_1153 = or(UInt<1>(0h0), _T_1145)
node _T_1154 = or(_T_1153, _T_1152)
node _T_1155 = and(_T_1075, _T_1154)
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_41
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(is_aligned, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1165 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_44
node _T_1169 = eq(io.in.a.bits.mask, mask)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_45
node _T_1173 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1173 :
node _T_1174 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1175 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1176 = and(_T_1174, _T_1175)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1177 = shr(io.in.a.bits.source, 2)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
node _T_1179 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1180 = and(_T_1178, _T_1179)
node _T_1181 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1182 = and(_T_1180, _T_1181)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1183 = shr(io.in.a.bits.source, 2)
node _T_1184 = eq(_T_1183, UInt<1>(0h1))
node _T_1185 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1186 = and(_T_1184, _T_1185)
node _T_1187 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1188 = and(_T_1186, _T_1187)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1189 = shr(io.in.a.bits.source, 2)
node _T_1190 = eq(_T_1189, UInt<2>(0h2))
node _T_1191 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1192 = and(_T_1190, _T_1191)
node _T_1193 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1194 = and(_T_1192, _T_1193)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1195 = shr(io.in.a.bits.source, 2)
node _T_1196 = eq(_T_1195, UInt<2>(0h3))
node _T_1197 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1200 = and(_T_1198, _T_1199)
node _T_1201 = or(_T_1182, _T_1188)
node _T_1202 = or(_T_1201, _T_1194)
node _T_1203 = or(_T_1202, _T_1200)
node _T_1204 = and(_T_1176, _T_1203)
node _T_1205 = or(UInt<1>(0h0), _T_1204)
node _T_1206 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1207 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = or(UInt<1>(0h0), _T_1208)
node _T_1210 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1211 = cvt(_T_1210)
node _T_1212 = and(_T_1211, asSInt(UInt<13>(0h1000)))
node _T_1213 = asSInt(_T_1212)
node _T_1214 = eq(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = and(_T_1209, _T_1214)
node _T_1216 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1217 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1218 = cvt(_T_1217)
node _T_1219 = and(_T_1218, asSInt(UInt<14>(0h2000)))
node _T_1220 = asSInt(_T_1219)
node _T_1221 = eq(_T_1220, asSInt(UInt<1>(0h0)))
node _T_1222 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1223 = cvt(_T_1222)
node _T_1224 = and(_T_1223, asSInt(UInt<17>(0h10000)))
node _T_1225 = asSInt(_T_1224)
node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0)))
node _T_1227 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1228 = cvt(_T_1227)
node _T_1229 = and(_T_1228, asSInt(UInt<18>(0h2f000)))
node _T_1230 = asSInt(_T_1229)
node _T_1231 = eq(_T_1230, asSInt(UInt<1>(0h0)))
node _T_1232 = xor(io.in.a.bits.address, UInt<22>(0h200000))
node _T_1233 = cvt(_T_1232)
node _T_1234 = and(_T_1233, asSInt(UInt<12>(0h800)))
node _T_1235 = asSInt(_T_1234)
node _T_1236 = eq(_T_1235, asSInt(UInt<1>(0h0)))
node _T_1237 = xor(io.in.a.bits.address, UInt<22>(0h300000))
node _T_1238 = cvt(_T_1237)
node _T_1239 = and(_T_1238, asSInt(UInt<16>(0h8000)))
node _T_1240 = asSInt(_T_1239)
node _T_1241 = eq(_T_1240, asSInt(UInt<1>(0h0)))
node _T_1242 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1243 = cvt(_T_1242)
node _T_1244 = and(_T_1243, asSInt(UInt<17>(0h10000)))
node _T_1245 = asSInt(_T_1244)
node _T_1246 = eq(_T_1245, asSInt(UInt<1>(0h0)))
node _T_1247 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1248 = cvt(_T_1247)
node _T_1249 = and(_T_1248, asSInt(UInt<13>(0h1000)))
node _T_1250 = asSInt(_T_1249)
node _T_1251 = eq(_T_1250, asSInt(UInt<1>(0h0)))
node _T_1252 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1253 = cvt(_T_1252)
node _T_1254 = and(_T_1253, asSInt(UInt<27>(0h4000000)))
node _T_1255 = asSInt(_T_1254)
node _T_1256 = eq(_T_1255, asSInt(UInt<1>(0h0)))
node _T_1257 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1258 = cvt(_T_1257)
node _T_1259 = and(_T_1258, asSInt(UInt<13>(0h1000)))
node _T_1260 = asSInt(_T_1259)
node _T_1261 = eq(_T_1260, asSInt(UInt<1>(0h0)))
node _T_1262 = or(_T_1221, _T_1226)
node _T_1263 = or(_T_1262, _T_1231)
node _T_1264 = or(_T_1263, _T_1236)
node _T_1265 = or(_T_1264, _T_1241)
node _T_1266 = or(_T_1265, _T_1246)
node _T_1267 = or(_T_1266, _T_1251)
node _T_1268 = or(_T_1267, _T_1256)
node _T_1269 = or(_T_1268, _T_1261)
node _T_1270 = and(_T_1216, _T_1269)
node _T_1271 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1272 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1273 = and(_T_1271, _T_1272)
node _T_1274 = or(UInt<1>(0h0), _T_1273)
node _T_1275 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1276 = cvt(_T_1275)
node _T_1277 = and(_T_1276, asSInt(UInt<17>(0h10000)))
node _T_1278 = asSInt(_T_1277)
node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0)))
node _T_1280 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1281 = cvt(_T_1280)
node _T_1282 = and(_T_1281, asSInt(UInt<29>(0h10000000)))
node _T_1283 = asSInt(_T_1282)
node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0)))
node _T_1285 = or(_T_1279, _T_1284)
node _T_1286 = and(_T_1274, _T_1285)
node _T_1287 = or(UInt<1>(0h0), _T_1215)
node _T_1288 = or(_T_1287, _T_1270)
node _T_1289 = or(_T_1288, _T_1286)
node _T_1290 = and(_T_1205, _T_1289)
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_46
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(source_ok, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(is_aligned, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1300 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_49
node _T_1304 = eq(io.in.a.bits.mask, mask)
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_50
node _T_1308 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1312 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1316 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1316 :
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(source_ok_1, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1320 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(_T_1320, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1320, UInt<1>(0h1), "") : assert_54
node _T_1324 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_55
node _T_1328 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_56
node _T_1332 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_57
node _T_1336 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1336 :
node _T_1337 = asUInt(reset)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
when _T_1338 :
node _T_1339 = eq(source_ok_1, UInt<1>(0h0))
when _T_1339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(sink_ok, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1343 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_60
node _T_1347 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_61
node _T_1351 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_62
node _T_1355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_63
node _T_1359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1360 = or(UInt<1>(0h1), _T_1359)
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_64
node _T_1364 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1364 :
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(source_ok_1, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(sink_ok, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1371 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_67
node _T_1375 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_68
node _T_1379 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_69
node _T_1383 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1384 = or(_T_1383, io.in.d.bits.corrupt)
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(_T_1384, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1384, UInt<1>(0h1), "") : assert_70
node _T_1388 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1389 = or(UInt<1>(0h1), _T_1388)
node _T_1390 = asUInt(reset)
node _T_1391 = eq(_T_1390, UInt<1>(0h0))
when _T_1391 :
node _T_1392 = eq(_T_1389, UInt<1>(0h0))
when _T_1392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1389, UInt<1>(0h1), "") : assert_71
node _T_1393 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(source_ok_1, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1397 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_73
node _T_1401 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1402 = asUInt(reset)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
when _T_1403 :
node _T_1404 = eq(_T_1401, UInt<1>(0h0))
when _T_1404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1401, UInt<1>(0h1), "") : assert_74
node _T_1405 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1406 = or(UInt<1>(0h1), _T_1405)
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_75
node _T_1410 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1410 :
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(source_ok_1, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1414 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_77
node _T_1418 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1419 = or(_T_1418, io.in.d.bits.corrupt)
node _T_1420 = asUInt(reset)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(_T_1419, UInt<1>(0h0))
when _T_1422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1419, UInt<1>(0h1), "") : assert_78
node _T_1423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1424 = or(UInt<1>(0h1), _T_1423)
node _T_1425 = asUInt(reset)
node _T_1426 = eq(_T_1425, UInt<1>(0h0))
when _T_1426 :
node _T_1427 = eq(_T_1424, UInt<1>(0h0))
when _T_1427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1424, UInt<1>(0h1), "") : assert_79
node _T_1428 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1428 :
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(source_ok_1, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(_T_1432, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1432, UInt<1>(0h1), "") : assert_81
node _T_1436 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1437 = asUInt(reset)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
when _T_1438 :
node _T_1439 = eq(_T_1436, UInt<1>(0h0))
when _T_1439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1436, UInt<1>(0h1), "") : assert_82
node _T_1440 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1441 = or(UInt<1>(0h1), _T_1440)
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1445 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1449 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1450 = asUInt(reset)
node _T_1451 = eq(_T_1450, UInt<1>(0h0))
when _T_1451 :
node _T_1452 = eq(_T_1449, UInt<1>(0h0))
when _T_1452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1449, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1453 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1454 = asUInt(reset)
node _T_1455 = eq(_T_1454, UInt<1>(0h0))
when _T_1455 :
node _T_1456 = eq(_T_1453, UInt<1>(0h0))
when _T_1456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1453, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1457 = eq(a_first, UInt<1>(0h0))
node _T_1458 = and(io.in.a.valid, _T_1457)
when _T_1458 :
node _T_1459 = eq(io.in.a.bits.opcode, opcode)
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_87
node _T_1463 = eq(io.in.a.bits.param, param)
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_88
node _T_1467 = eq(io.in.a.bits.size, size)
node _T_1468 = asUInt(reset)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
when _T_1469 :
node _T_1470 = eq(_T_1467, UInt<1>(0h0))
when _T_1470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1467, UInt<1>(0h1), "") : assert_89
node _T_1471 = eq(io.in.a.bits.source, source)
node _T_1472 = asUInt(reset)
node _T_1473 = eq(_T_1472, UInt<1>(0h0))
when _T_1473 :
node _T_1474 = eq(_T_1471, UInt<1>(0h0))
when _T_1474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1471, UInt<1>(0h1), "") : assert_90
node _T_1475 = eq(io.in.a.bits.address, address)
node _T_1476 = asUInt(reset)
node _T_1477 = eq(_T_1476, UInt<1>(0h0))
when _T_1477 :
node _T_1478 = eq(_T_1475, UInt<1>(0h0))
when _T_1478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1475, UInt<1>(0h1), "") : assert_91
node _T_1479 = and(io.in.a.ready, io.in.a.valid)
node _T_1480 = and(_T_1479, a_first)
when _T_1480 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1481 = eq(d_first, UInt<1>(0h0))
node _T_1482 = and(io.in.d.valid, _T_1481)
when _T_1482 :
node _T_1483 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_92
node _T_1487 = eq(io.in.d.bits.param, param_1)
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_93
node _T_1491 = eq(io.in.d.bits.size, size_1)
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_94
node _T_1495 = eq(io.in.d.bits.source, source_1)
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_95
node _T_1499 = eq(io.in.d.bits.sink, sink)
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_96
node _T_1503 = eq(io.in.d.bits.denied, denied)
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_97
node _T_1507 = and(io.in.d.ready, io.in.d.valid)
node _T_1508 = and(_T_1507, d_first)
when _T_1508 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1509 = and(io.in.a.valid, a_first_1)
node _T_1510 = and(_T_1509, UInt<1>(0h1))
when _T_1510 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1511 = and(io.in.a.ready, io.in.a.valid)
node _T_1512 = and(_T_1511, a_first_1)
node _T_1513 = and(_T_1512, UInt<1>(0h1))
when _T_1513 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1514 = dshr(inflight, io.in.a.bits.source)
node _T_1515 = bits(_T_1514, 0, 0)
node _T_1516 = eq(_T_1515, UInt<1>(0h0))
node _T_1517 = asUInt(reset)
node _T_1518 = eq(_T_1517, UInt<1>(0h0))
when _T_1518 :
node _T_1519 = eq(_T_1516, UInt<1>(0h0))
when _T_1519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1516, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1520 = and(io.in.d.valid, d_first_1)
node _T_1521 = and(_T_1520, UInt<1>(0h1))
node _T_1522 = eq(d_release_ack, UInt<1>(0h0))
node _T_1523 = and(_T_1521, _T_1522)
when _T_1523 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1524 = and(io.in.d.ready, io.in.d.valid)
node _T_1525 = and(_T_1524, d_first_1)
node _T_1526 = and(_T_1525, UInt<1>(0h1))
node _T_1527 = eq(d_release_ack, UInt<1>(0h0))
node _T_1528 = and(_T_1526, _T_1527)
when _T_1528 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1529 = and(io.in.d.valid, d_first_1)
node _T_1530 = and(_T_1529, UInt<1>(0h1))
node _T_1531 = eq(d_release_ack, UInt<1>(0h0))
node _T_1532 = and(_T_1530, _T_1531)
when _T_1532 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1533 = dshr(inflight, io.in.d.bits.source)
node _T_1534 = bits(_T_1533, 0, 0)
node _T_1535 = or(_T_1534, same_cycle_resp)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1539 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1540 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1541 = or(_T_1539, _T_1540)
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_100
node _T_1545 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1546 = asUInt(reset)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
when _T_1547 :
node _T_1548 = eq(_T_1545, UInt<1>(0h0))
when _T_1548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1545, UInt<1>(0h1), "") : assert_101
else :
node _T_1549 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1550 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1551 = or(_T_1549, _T_1550)
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_102
node _T_1555 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1556 = asUInt(reset)
node _T_1557 = eq(_T_1556, UInt<1>(0h0))
when _T_1557 :
node _T_1558 = eq(_T_1555, UInt<1>(0h0))
when _T_1558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1555, UInt<1>(0h1), "") : assert_103
node _T_1559 = and(io.in.d.valid, d_first_1)
node _T_1560 = and(_T_1559, a_first_1)
node _T_1561 = and(_T_1560, io.in.a.valid)
node _T_1562 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1563 = and(_T_1561, _T_1562)
node _T_1564 = eq(d_release_ack, UInt<1>(0h0))
node _T_1565 = and(_T_1563, _T_1564)
when _T_1565 :
node _T_1566 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1567 = or(_T_1566, io.in.a.ready)
node _T_1568 = asUInt(reset)
node _T_1569 = eq(_T_1568, UInt<1>(0h0))
when _T_1569 :
node _T_1570 = eq(_T_1567, UInt<1>(0h0))
when _T_1570 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1567, UInt<1>(0h1), "") : assert_104
node _T_1571 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1572 = orr(a_set_wo_ready)
node _T_1573 = eq(_T_1572, UInt<1>(0h0))
node _T_1574 = or(_T_1571, _T_1573)
node _T_1575 = asUInt(reset)
node _T_1576 = eq(_T_1575, UInt<1>(0h0))
when _T_1576 :
node _T_1577 = eq(_T_1574, UInt<1>(0h0))
when _T_1577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1574, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_26
node _T_1578 = orr(inflight)
node _T_1579 = eq(_T_1578, UInt<1>(0h0))
node _T_1580 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1581 = or(_T_1579, _T_1580)
node _T_1582 = lt(watchdog, plusarg_reader.out)
node _T_1583 = or(_T_1581, _T_1582)
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(_T_1583, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1583, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1587 = and(io.in.a.ready, io.in.a.valid)
node _T_1588 = and(io.in.d.ready, io.in.d.valid)
node _T_1589 = or(_T_1587, _T_1588)
when _T_1589 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1590 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1591 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1592 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1593 = and(_T_1591, _T_1592)
node _T_1594 = and(_T_1590, _T_1593)
when _T_1594 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1595 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1596 = and(_T_1595, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1597 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1598 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1599 = and(_T_1597, _T_1598)
node _T_1600 = and(_T_1596, _T_1599)
when _T_1600 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1601 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1602 = bits(_T_1601, 0, 0)
node _T_1603 = eq(_T_1602, UInt<1>(0h0))
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1607 = and(io.in.d.valid, d_first_2)
node _T_1608 = and(_T_1607, UInt<1>(0h1))
node _T_1609 = and(_T_1608, d_release_ack_1)
when _T_1609 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1610 = and(io.in.d.ready, io.in.d.valid)
node _T_1611 = and(_T_1610, d_first_2)
node _T_1612 = and(_T_1611, UInt<1>(0h1))
node _T_1613 = and(_T_1612, d_release_ack_1)
when _T_1613 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1614 = and(io.in.d.valid, d_first_2)
node _T_1615 = and(_T_1614, UInt<1>(0h1))
node _T_1616 = and(_T_1615, d_release_ack_1)
when _T_1616 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1617 = dshr(inflight_1, io.in.d.bits.source)
node _T_1618 = bits(_T_1617, 0, 0)
node _T_1619 = or(_T_1618, same_cycle_resp_1)
node _T_1620 = asUInt(reset)
node _T_1621 = eq(_T_1620, UInt<1>(0h0))
when _T_1621 :
node _T_1622 = eq(_T_1619, UInt<1>(0h0))
when _T_1622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1619, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1623 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1624 = asUInt(reset)
node _T_1625 = eq(_T_1624, UInt<1>(0h0))
when _T_1625 :
node _T_1626 = eq(_T_1623, UInt<1>(0h0))
when _T_1626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1623, UInt<1>(0h1), "") : assert_109
else :
node _T_1627 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1628 = asUInt(reset)
node _T_1629 = eq(_T_1628, UInt<1>(0h0))
when _T_1629 :
node _T_1630 = eq(_T_1627, UInt<1>(0h0))
when _T_1630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1627, UInt<1>(0h1), "") : assert_110
node _T_1631 = and(io.in.d.valid, d_first_2)
node _T_1632 = and(_T_1631, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1633 = and(_T_1632, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1634 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1635 = and(_T_1633, _T_1634)
node _T_1636 = and(_T_1635, d_release_ack_1)
node _T_1637 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
node _T_1639 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1640 = or(_T_1639, _WIRE_23.ready)
node _T_1641 = asUInt(reset)
node _T_1642 = eq(_T_1641, UInt<1>(0h0))
when _T_1642 :
node _T_1643 = eq(_T_1640, UInt<1>(0h0))
when _T_1643 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1640, UInt<1>(0h1), "") : assert_111
node _T_1644 = orr(c_set_wo_ready)
when _T_1644 :
node _T_1645 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1646 = asUInt(reset)
node _T_1647 = eq(_T_1646, UInt<1>(0h0))
when _T_1647 :
node _T_1648 = eq(_T_1645, UInt<1>(0h0))
when _T_1648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1645, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_27
node _T_1649 = orr(inflight_1)
node _T_1650 = eq(_T_1649, UInt<1>(0h0))
node _T_1651 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1652 = or(_T_1650, _T_1651)
node _T_1653 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1654 = or(_T_1652, _T_1653)
node _T_1655 = asUInt(reset)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
when _T_1656 :
node _T_1657 = eq(_T_1654, UInt<1>(0h0))
when _T_1657 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1654, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1658 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1659 = and(io.in.d.ready, io.in.d.valid)
node _T_1660 = or(_T_1658, _T_1659)
when _T_1660 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_13( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1587 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1587; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1587; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1660 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1660; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1660; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1660; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1513 = _T_1587 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1513 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1513 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1513 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1513 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1513 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1559 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1559 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1528 = _T_1660 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1528 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1528 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1528 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1631 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1631 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1613 = _T_1660 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1613 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1613 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1613 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_32 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h1))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[2]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = and(_T_11, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
node _T_24 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_24 :
node _T_25 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_26 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_29 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_30 = or(_T_28, _T_29)
node _T_31 = and(_T_27, _T_30)
node _T_32 = or(UInt<1>(0h0), _T_31)
node _T_33 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_34 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_35 = cvt(_T_34)
node _T_36 = and(_T_35, asSInt(UInt<14>(0h2000)))
node _T_37 = asSInt(_T_36)
node _T_38 = eq(_T_37, asSInt(UInt<1>(0h0)))
node _T_39 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_40 = cvt(_T_39)
node _T_41 = and(_T_40, asSInt(UInt<13>(0h1000)))
node _T_42 = asSInt(_T_41)
node _T_43 = eq(_T_42, asSInt(UInt<1>(0h0)))
node _T_44 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_45 = cvt(_T_44)
node _T_46 = and(_T_45, asSInt(UInt<17>(0h10000)))
node _T_47 = asSInt(_T_46)
node _T_48 = eq(_T_47, asSInt(UInt<1>(0h0)))
node _T_49 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_50 = cvt(_T_49)
node _T_51 = and(_T_50, asSInt(UInt<18>(0h2f000)))
node _T_52 = asSInt(_T_51)
node _T_53 = eq(_T_52, asSInt(UInt<1>(0h0)))
node _T_54 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<27>(0h4000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_65 = cvt(_T_64)
node _T_66 = and(_T_65, asSInt(UInt<13>(0h1000)))
node _T_67 = asSInt(_T_66)
node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_70 = cvt(_T_69)
node _T_71 = and(_T_70, asSInt(UInt<19>(0h40000)))
node _T_72 = asSInt(_T_71)
node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = or(_T_38, _T_43)
node _T_75 = or(_T_74, _T_48)
node _T_76 = or(_T_75, _T_53)
node _T_77 = or(_T_76, _T_58)
node _T_78 = or(_T_77, _T_63)
node _T_79 = or(_T_78, _T_68)
node _T_80 = or(_T_79, _T_73)
node _T_81 = and(_T_33, _T_80)
node _T_82 = or(UInt<1>(0h0), _T_81)
node _T_83 = and(_T_32, _T_82)
node _T_84 = asUInt(reset)
node _T_85 = eq(_T_84, UInt<1>(0h0))
when _T_85 :
node _T_86 = eq(_T_83, UInt<1>(0h0))
when _T_86 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_83, UInt<1>(0h1), "") : assert_2
node _T_87 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_88 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(UInt<1>(0h0), _T_89)
node _T_91 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_92 = cvt(_T_91)
node _T_93 = and(_T_92, asSInt(UInt<14>(0h2000)))
node _T_94 = asSInt(_T_93)
node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0)))
node _T_96 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<13>(0h1000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<17>(0h10000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<18>(0h2f000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<17>(0h10000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<27>(0h4000000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<19>(0h40000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = or(_T_95, _T_100)
node _T_132 = or(_T_131, _T_105)
node _T_133 = or(_T_132, _T_110)
node _T_134 = or(_T_133, _T_115)
node _T_135 = or(_T_134, _T_120)
node _T_136 = or(_T_135, _T_125)
node _T_137 = or(_T_136, _T_130)
node _T_138 = and(_T_90, _T_137)
node _T_139 = or(UInt<1>(0h0), _T_138)
node _T_140 = and(UInt<1>(0h0), _T_139)
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_140, UInt<1>(0h1), "") : assert_3
node _T_144 = asUInt(reset)
node _T_145 = eq(_T_144, UInt<1>(0h0))
when _T_145 :
node _T_146 = eq(source_ok, UInt<1>(0h0))
when _T_146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_147 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_148 = asUInt(reset)
node _T_149 = eq(_T_148, UInt<1>(0h0))
when _T_149 :
node _T_150 = eq(_T_147, UInt<1>(0h0))
when _T_150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_147, UInt<1>(0h1), "") : assert_5
node _T_151 = asUInt(reset)
node _T_152 = eq(_T_151, UInt<1>(0h0))
when _T_152 :
node _T_153 = eq(is_aligned, UInt<1>(0h0))
when _T_153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_154 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_T_154, UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_154, UInt<1>(0h1), "") : assert_7
node _T_158 = not(io.in.a.bits.mask)
node _T_159 = eq(_T_158, UInt<1>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_159, UInt<1>(0h1), "") : assert_8
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_163, UInt<1>(0h1), "") : assert_9
node _T_167 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_167 :
node _T_168 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_169 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_170 = and(_T_168, _T_169)
node _T_171 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_172 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_173 = or(_T_171, _T_172)
node _T_174 = and(_T_170, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_177 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_178 = cvt(_T_177)
node _T_179 = and(_T_178, asSInt(UInt<14>(0h2000)))
node _T_180 = asSInt(_T_179)
node _T_181 = eq(_T_180, asSInt(UInt<1>(0h0)))
node _T_182 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<13>(0h1000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_188 = cvt(_T_187)
node _T_189 = and(_T_188, asSInt(UInt<17>(0h10000)))
node _T_190 = asSInt(_T_189)
node _T_191 = eq(_T_190, asSInt(UInt<1>(0h0)))
node _T_192 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_193 = cvt(_T_192)
node _T_194 = and(_T_193, asSInt(UInt<18>(0h2f000)))
node _T_195 = asSInt(_T_194)
node _T_196 = eq(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_198 = cvt(_T_197)
node _T_199 = and(_T_198, asSInt(UInt<17>(0h10000)))
node _T_200 = asSInt(_T_199)
node _T_201 = eq(_T_200, asSInt(UInt<1>(0h0)))
node _T_202 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_203 = cvt(_T_202)
node _T_204 = and(_T_203, asSInt(UInt<27>(0h4000000)))
node _T_205 = asSInt(_T_204)
node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0)))
node _T_207 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_208 = cvt(_T_207)
node _T_209 = and(_T_208, asSInt(UInt<13>(0h1000)))
node _T_210 = asSInt(_T_209)
node _T_211 = eq(_T_210, asSInt(UInt<1>(0h0)))
node _T_212 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_213 = cvt(_T_212)
node _T_214 = and(_T_213, asSInt(UInt<19>(0h40000)))
node _T_215 = asSInt(_T_214)
node _T_216 = eq(_T_215, asSInt(UInt<1>(0h0)))
node _T_217 = or(_T_181, _T_186)
node _T_218 = or(_T_217, _T_191)
node _T_219 = or(_T_218, _T_196)
node _T_220 = or(_T_219, _T_201)
node _T_221 = or(_T_220, _T_206)
node _T_222 = or(_T_221, _T_211)
node _T_223 = or(_T_222, _T_216)
node _T_224 = and(_T_176, _T_223)
node _T_225 = or(UInt<1>(0h0), _T_224)
node _T_226 = and(_T_175, _T_225)
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_226, UInt<1>(0h1), "") : assert_10
node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _T_233 = or(UInt<1>(0h0), _T_232)
node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_235 = cvt(_T_234)
node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000)))
node _T_237 = asSInt(_T_236)
node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0)))
node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_240 = cvt(_T_239)
node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000)))
node _T_242 = asSInt(_T_241)
node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0)))
node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_245 = cvt(_T_244)
node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000)))
node _T_247 = asSInt(_T_246)
node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0)))
node _T_249 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_250 = cvt(_T_249)
node _T_251 = and(_T_250, asSInt(UInt<18>(0h2f000)))
node _T_252 = asSInt(_T_251)
node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0)))
node _T_254 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_255 = cvt(_T_254)
node _T_256 = and(_T_255, asSInt(UInt<17>(0h10000)))
node _T_257 = asSInt(_T_256)
node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0)))
node _T_259 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<27>(0h4000000)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<13>(0h1000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<19>(0h40000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = or(_T_238, _T_243)
node _T_275 = or(_T_274, _T_248)
node _T_276 = or(_T_275, _T_253)
node _T_277 = or(_T_276, _T_258)
node _T_278 = or(_T_277, _T_263)
node _T_279 = or(_T_278, _T_268)
node _T_280 = or(_T_279, _T_273)
node _T_281 = and(_T_233, _T_280)
node _T_282 = or(UInt<1>(0h0), _T_281)
node _T_283 = and(UInt<1>(0h0), _T_282)
node _T_284 = asUInt(reset)
node _T_285 = eq(_T_284, UInt<1>(0h0))
when _T_285 :
node _T_286 = eq(_T_283, UInt<1>(0h0))
when _T_286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_283, UInt<1>(0h1), "") : assert_11
node _T_287 = asUInt(reset)
node _T_288 = eq(_T_287, UInt<1>(0h0))
when _T_288 :
node _T_289 = eq(source_ok, UInt<1>(0h0))
when _T_289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_290 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(_T_290, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_290, UInt<1>(0h1), "") : assert_13
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(is_aligned, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_297 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_298 = asUInt(reset)
node _T_299 = eq(_T_298, UInt<1>(0h0))
when _T_299 :
node _T_300 = eq(_T_297, UInt<1>(0h0))
when _T_300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_297, UInt<1>(0h1), "") : assert_15
node _T_301 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_301, UInt<1>(0h1), "") : assert_16
node _T_305 = not(io.in.a.bits.mask)
node _T_306 = eq(_T_305, UInt<1>(0h0))
node _T_307 = asUInt(reset)
node _T_308 = eq(_T_307, UInt<1>(0h0))
when _T_308 :
node _T_309 = eq(_T_306, UInt<1>(0h0))
when _T_309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_306, UInt<1>(0h1), "") : assert_17
node _T_310 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_310, UInt<1>(0h1), "") : assert_18
node _T_314 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_314 :
node _T_315 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_316 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = or(_T_318, _T_319)
node _T_321 = and(_T_317, _T_320)
node _T_322 = or(UInt<1>(0h0), _T_321)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_322, UInt<1>(0h1), "") : assert_19
node _T_326 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_327 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_328 = and(_T_326, _T_327)
node _T_329 = or(UInt<1>(0h0), _T_328)
node _T_330 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_337 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_338 = and(_T_336, _T_337)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<14>(0h2000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<17>(0h10000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_351 = cvt(_T_350)
node _T_352 = and(_T_351, asSInt(UInt<18>(0h2f000)))
node _T_353 = asSInt(_T_352)
node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0)))
node _T_355 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_356 = cvt(_T_355)
node _T_357 = and(_T_356, asSInt(UInt<17>(0h10000)))
node _T_358 = asSInt(_T_357)
node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0)))
node _T_360 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_361 = cvt(_T_360)
node _T_362 = and(_T_361, asSInt(UInt<27>(0h4000000)))
node _T_363 = asSInt(_T_362)
node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0)))
node _T_365 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_366 = cvt(_T_365)
node _T_367 = and(_T_366, asSInt(UInt<13>(0h1000)))
node _T_368 = asSInt(_T_367)
node _T_369 = eq(_T_368, asSInt(UInt<1>(0h0)))
node _T_370 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_371 = cvt(_T_370)
node _T_372 = and(_T_371, asSInt(UInt<19>(0h40000)))
node _T_373 = asSInt(_T_372)
node _T_374 = eq(_T_373, asSInt(UInt<1>(0h0)))
node _T_375 = or(_T_344, _T_349)
node _T_376 = or(_T_375, _T_354)
node _T_377 = or(_T_376, _T_359)
node _T_378 = or(_T_377, _T_364)
node _T_379 = or(_T_378, _T_369)
node _T_380 = or(_T_379, _T_374)
node _T_381 = and(_T_339, _T_380)
node _T_382 = or(UInt<1>(0h0), _T_335)
node _T_383 = or(_T_382, _T_381)
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_383, UInt<1>(0h1), "") : assert_20
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(source_ok, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_393 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_393, UInt<1>(0h1), "") : assert_23
node _T_397 = eq(io.in.a.bits.mask, mask)
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_397, UInt<1>(0h1), "") : assert_24
node _T_401 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_401, UInt<1>(0h1), "") : assert_25
node _T_405 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_405 :
node _T_406 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_407 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_410 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_411 = or(_T_409, _T_410)
node _T_412 = and(_T_408, _T_411)
node _T_413 = or(UInt<1>(0h0), _T_412)
node _T_414 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_415 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_416 = and(_T_414, _T_415)
node _T_417 = or(UInt<1>(0h0), _T_416)
node _T_418 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<13>(0h1000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = and(_T_417, _T_422)
node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_425 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_426 = and(_T_424, _T_425)
node _T_427 = or(UInt<1>(0h0), _T_426)
node _T_428 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<14>(0h2000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<18>(0h2f000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<17>(0h10000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<27>(0h4000000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_449 = cvt(_T_448)
node _T_450 = and(_T_449, asSInt(UInt<13>(0h1000)))
node _T_451 = asSInt(_T_450)
node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0)))
node _T_453 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_454 = cvt(_T_453)
node _T_455 = and(_T_454, asSInt(UInt<19>(0h40000)))
node _T_456 = asSInt(_T_455)
node _T_457 = eq(_T_456, asSInt(UInt<1>(0h0)))
node _T_458 = or(_T_432, _T_437)
node _T_459 = or(_T_458, _T_442)
node _T_460 = or(_T_459, _T_447)
node _T_461 = or(_T_460, _T_452)
node _T_462 = or(_T_461, _T_457)
node _T_463 = and(_T_427, _T_462)
node _T_464 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_465 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_466 = cvt(_T_465)
node _T_467 = and(_T_466, asSInt(UInt<17>(0h10000)))
node _T_468 = asSInt(_T_467)
node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0)))
node _T_470 = and(_T_464, _T_469)
node _T_471 = or(UInt<1>(0h0), _T_423)
node _T_472 = or(_T_471, _T_463)
node _T_473 = or(_T_472, _T_470)
node _T_474 = and(_T_413, _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_474, UInt<1>(0h1), "") : assert_26
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(source_ok, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(is_aligned, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_484 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(_T_484, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_484, UInt<1>(0h1), "") : assert_29
node _T_488 = eq(io.in.a.bits.mask, mask)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_488, UInt<1>(0h1), "") : assert_30
node _T_492 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_492 :
node _T_493 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_494 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_497 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_498 = or(_T_496, _T_497)
node _T_499 = and(_T_495, _T_498)
node _T_500 = or(UInt<1>(0h0), _T_499)
node _T_501 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_502 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_503 = and(_T_501, _T_502)
node _T_504 = or(UInt<1>(0h0), _T_503)
node _T_505 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<13>(0h1000)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = and(_T_504, _T_509)
node _T_511 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_512 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_513 = and(_T_511, _T_512)
node _T_514 = or(UInt<1>(0h0), _T_513)
node _T_515 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_516 = cvt(_T_515)
node _T_517 = and(_T_516, asSInt(UInt<14>(0h2000)))
node _T_518 = asSInt(_T_517)
node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0)))
node _T_520 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_521 = cvt(_T_520)
node _T_522 = and(_T_521, asSInt(UInt<18>(0h2f000)))
node _T_523 = asSInt(_T_522)
node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0)))
node _T_525 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_526 = cvt(_T_525)
node _T_527 = and(_T_526, asSInt(UInt<17>(0h10000)))
node _T_528 = asSInt(_T_527)
node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0)))
node _T_530 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_531 = cvt(_T_530)
node _T_532 = and(_T_531, asSInt(UInt<27>(0h4000000)))
node _T_533 = asSInt(_T_532)
node _T_534 = eq(_T_533, asSInt(UInt<1>(0h0)))
node _T_535 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_536 = cvt(_T_535)
node _T_537 = and(_T_536, asSInt(UInt<13>(0h1000)))
node _T_538 = asSInt(_T_537)
node _T_539 = eq(_T_538, asSInt(UInt<1>(0h0)))
node _T_540 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_541 = cvt(_T_540)
node _T_542 = and(_T_541, asSInt(UInt<19>(0h40000)))
node _T_543 = asSInt(_T_542)
node _T_544 = eq(_T_543, asSInt(UInt<1>(0h0)))
node _T_545 = or(_T_519, _T_524)
node _T_546 = or(_T_545, _T_529)
node _T_547 = or(_T_546, _T_534)
node _T_548 = or(_T_547, _T_539)
node _T_549 = or(_T_548, _T_544)
node _T_550 = and(_T_514, _T_549)
node _T_551 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_553 = cvt(_T_552)
node _T_554 = and(_T_553, asSInt(UInt<17>(0h10000)))
node _T_555 = asSInt(_T_554)
node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0)))
node _T_557 = and(_T_551, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_510)
node _T_559 = or(_T_558, _T_550)
node _T_560 = or(_T_559, _T_557)
node _T_561 = and(_T_500, _T_560)
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(_T_561, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_561, UInt<1>(0h1), "") : assert_31
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(source_ok, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(is_aligned, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_571 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_572 = asUInt(reset)
node _T_573 = eq(_T_572, UInt<1>(0h0))
when _T_573 :
node _T_574 = eq(_T_571, UInt<1>(0h0))
when _T_574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_571, UInt<1>(0h1), "") : assert_34
node _T_575 = not(mask)
node _T_576 = and(io.in.a.bits.mask, _T_575)
node _T_577 = eq(_T_576, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_577, UInt<1>(0h1), "") : assert_35
node _T_581 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_581 :
node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_584 = and(_T_582, _T_583)
node _T_585 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_586 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_587 = or(_T_585, _T_586)
node _T_588 = and(_T_584, _T_587)
node _T_589 = or(UInt<1>(0h0), _T_588)
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _T_593 = or(UInt<1>(0h0), _T_592)
node _T_594 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<14>(0h2000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<13>(0h1000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<18>(0h2f000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<17>(0h10000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<27>(0h4000000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<13>(0h1000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<19>(0h40000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = or(_T_598, _T_603)
node _T_630 = or(_T_629, _T_608)
node _T_631 = or(_T_630, _T_613)
node _T_632 = or(_T_631, _T_618)
node _T_633 = or(_T_632, _T_623)
node _T_634 = or(_T_633, _T_628)
node _T_635 = and(_T_593, _T_634)
node _T_636 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_637 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_638 = cvt(_T_637)
node _T_639 = and(_T_638, asSInt(UInt<17>(0h10000)))
node _T_640 = asSInt(_T_639)
node _T_641 = eq(_T_640, asSInt(UInt<1>(0h0)))
node _T_642 = and(_T_636, _T_641)
node _T_643 = or(UInt<1>(0h0), _T_635)
node _T_644 = or(_T_643, _T_642)
node _T_645 = and(_T_589, _T_644)
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_645, UInt<1>(0h1), "") : assert_36
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(source_ok, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(is_aligned, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_655 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_655, UInt<1>(0h1), "") : assert_39
node _T_659 = eq(io.in.a.bits.mask, mask)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_659, UInt<1>(0h1), "") : assert_40
node _T_663 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_663 :
node _T_664 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_665 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_666 = and(_T_664, _T_665)
node _T_667 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_668 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_669 = or(_T_667, _T_668)
node _T_670 = and(_T_666, _T_669)
node _T_671 = or(UInt<1>(0h0), _T_670)
node _T_672 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_673 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_674 = and(_T_672, _T_673)
node _T_675 = or(UInt<1>(0h0), _T_674)
node _T_676 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_677 = cvt(_T_676)
node _T_678 = and(_T_677, asSInt(UInt<14>(0h2000)))
node _T_679 = asSInt(_T_678)
node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0)))
node _T_681 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_682 = cvt(_T_681)
node _T_683 = and(_T_682, asSInt(UInt<13>(0h1000)))
node _T_684 = asSInt(_T_683)
node _T_685 = eq(_T_684, asSInt(UInt<1>(0h0)))
node _T_686 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_687 = cvt(_T_686)
node _T_688 = and(_T_687, asSInt(UInt<18>(0h2f000)))
node _T_689 = asSInt(_T_688)
node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0)))
node _T_691 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_692 = cvt(_T_691)
node _T_693 = and(_T_692, asSInt(UInt<17>(0h10000)))
node _T_694 = asSInt(_T_693)
node _T_695 = eq(_T_694, asSInt(UInt<1>(0h0)))
node _T_696 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<27>(0h4000000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_702 = cvt(_T_701)
node _T_703 = and(_T_702, asSInt(UInt<13>(0h1000)))
node _T_704 = asSInt(_T_703)
node _T_705 = eq(_T_704, asSInt(UInt<1>(0h0)))
node _T_706 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<19>(0h40000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = or(_T_680, _T_685)
node _T_712 = or(_T_711, _T_690)
node _T_713 = or(_T_712, _T_695)
node _T_714 = or(_T_713, _T_700)
node _T_715 = or(_T_714, _T_705)
node _T_716 = or(_T_715, _T_710)
node _T_717 = and(_T_675, _T_716)
node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = and(_T_718, _T_723)
node _T_725 = or(UInt<1>(0h0), _T_717)
node _T_726 = or(_T_725, _T_724)
node _T_727 = and(_T_671, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_727, UInt<1>(0h1), "") : assert_41
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(source_ok, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_734 = asUInt(reset)
node _T_735 = eq(_T_734, UInt<1>(0h0))
when _T_735 :
node _T_736 = eq(is_aligned, UInt<1>(0h0))
when _T_736 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_737 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_737, UInt<1>(0h1), "") : assert_44
node _T_741 = eq(io.in.a.bits.mask, mask)
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_741, UInt<1>(0h1), "") : assert_45
node _T_745 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_745 :
node _T_746 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_747 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_748 = and(_T_746, _T_747)
node _T_749 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_750 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_751 = or(_T_749, _T_750)
node _T_752 = and(_T_748, _T_751)
node _T_753 = or(UInt<1>(0h0), _T_752)
node _T_754 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_755 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_756 = and(_T_754, _T_755)
node _T_757 = or(UInt<1>(0h0), _T_756)
node _T_758 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_759 = cvt(_T_758)
node _T_760 = and(_T_759, asSInt(UInt<13>(0h1000)))
node _T_761 = asSInt(_T_760)
node _T_762 = eq(_T_761, asSInt(UInt<1>(0h0)))
node _T_763 = and(_T_757, _T_762)
node _T_764 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_765 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<14>(0h2000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_796 = cvt(_T_795)
node _T_797 = and(_T_796, asSInt(UInt<19>(0h40000)))
node _T_798 = asSInt(_T_797)
node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0)))
node _T_800 = or(_T_769, _T_774)
node _T_801 = or(_T_800, _T_779)
node _T_802 = or(_T_801, _T_784)
node _T_803 = or(_T_802, _T_789)
node _T_804 = or(_T_803, _T_794)
node _T_805 = or(_T_804, _T_799)
node _T_806 = and(_T_764, _T_805)
node _T_807 = or(UInt<1>(0h0), _T_763)
node _T_808 = or(_T_807, _T_806)
node _T_809 = and(_T_753, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_809, UInt<1>(0h1), "") : assert_46
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_819 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_819, UInt<1>(0h1), "") : assert_49
node _T_823 = eq(io.in.a.bits.mask, mask)
node _T_824 = asUInt(reset)
node _T_825 = eq(_T_824, UInt<1>(0h0))
when _T_825 :
node _T_826 = eq(_T_823, UInt<1>(0h0))
when _T_826 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_823, UInt<1>(0h1), "") : assert_50
node _T_827 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_828 = asUInt(reset)
node _T_829 = eq(_T_828, UInt<1>(0h0))
when _T_829 :
node _T_830 = eq(_T_827, UInt<1>(0h0))
when _T_830 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_827, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_831 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_831, UInt<1>(0h1), "") : assert_52
node _source_ok_T_2 = eq(io.in.d.bits.source, UInt<1>(0h1))
node _source_ok_T_3 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[2]
connect _source_ok_WIRE_1[0], _source_ok_T_2
connect _source_ok_WIRE_1[1], _source_ok_T_3
node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_835 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_835 :
node _T_836 = asUInt(reset)
node _T_837 = eq(_T_836, UInt<1>(0h0))
when _T_837 :
node _T_838 = eq(source_ok_1, UInt<1>(0h0))
when _T_838 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_839 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_840 = asUInt(reset)
node _T_841 = eq(_T_840, UInt<1>(0h0))
when _T_841 :
node _T_842 = eq(_T_839, UInt<1>(0h0))
when _T_842 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_839, UInt<1>(0h1), "") : assert_54
node _T_843 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_844 = asUInt(reset)
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(_T_843, UInt<1>(0h0))
when _T_846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_843, UInt<1>(0h1), "") : assert_55
node _T_847 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_848 = asUInt(reset)
node _T_849 = eq(_T_848, UInt<1>(0h0))
when _T_849 :
node _T_850 = eq(_T_847, UInt<1>(0h0))
when _T_850 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_847, UInt<1>(0h1), "") : assert_56
node _T_851 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_852 = asUInt(reset)
node _T_853 = eq(_T_852, UInt<1>(0h0))
when _T_853 :
node _T_854 = eq(_T_851, UInt<1>(0h0))
when _T_854 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_851, UInt<1>(0h1), "") : assert_57
node _T_855 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_855 :
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(source_ok_1, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(sink_ok, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_862 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_862, UInt<1>(0h1), "") : assert_60
node _T_866 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_867 = asUInt(reset)
node _T_868 = eq(_T_867, UInt<1>(0h0))
when _T_868 :
node _T_869 = eq(_T_866, UInt<1>(0h0))
when _T_869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_866, UInt<1>(0h1), "") : assert_61
node _T_870 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_870, UInt<1>(0h1), "") : assert_62
node _T_874 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_875 = asUInt(reset)
node _T_876 = eq(_T_875, UInt<1>(0h0))
when _T_876 :
node _T_877 = eq(_T_874, UInt<1>(0h0))
when _T_877 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_874, UInt<1>(0h1), "") : assert_63
node _T_878 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_879 = or(UInt<1>(0h1), _T_878)
node _T_880 = asUInt(reset)
node _T_881 = eq(_T_880, UInt<1>(0h0))
when _T_881 :
node _T_882 = eq(_T_879, UInt<1>(0h0))
when _T_882 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_879, UInt<1>(0h1), "") : assert_64
node _T_883 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_883 :
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(source_ok_1, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(sink_ok, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_890 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_890, UInt<1>(0h1), "") : assert_67
node _T_894 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_895 = asUInt(reset)
node _T_896 = eq(_T_895, UInt<1>(0h0))
when _T_896 :
node _T_897 = eq(_T_894, UInt<1>(0h0))
when _T_897 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_894, UInt<1>(0h1), "") : assert_68
node _T_898 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_899 = asUInt(reset)
node _T_900 = eq(_T_899, UInt<1>(0h0))
when _T_900 :
node _T_901 = eq(_T_898, UInt<1>(0h0))
when _T_901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_898, UInt<1>(0h1), "") : assert_69
node _T_902 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_903 = or(_T_902, io.in.d.bits.corrupt)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_903, UInt<1>(0h1), "") : assert_70
node _T_907 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_908 = or(UInt<1>(0h1), _T_907)
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(_T_908, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_908, UInt<1>(0h1), "") : assert_71
node _T_912 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_912 :
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(source_ok_1, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_916 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_916, UInt<1>(0h1), "") : assert_73
node _T_920 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_920, UInt<1>(0h1), "") : assert_74
node _T_924 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_925 = or(UInt<1>(0h1), _T_924)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_925, UInt<1>(0h1), "") : assert_75
node _T_929 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_929 :
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(source_ok_1, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_933 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(_T_933, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_933, UInt<1>(0h1), "") : assert_77
node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_938 = or(_T_937, io.in.d.bits.corrupt)
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(_T_938, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_938, UInt<1>(0h1), "") : assert_78
node _T_942 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_943 = or(UInt<1>(0h1), _T_942)
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_943, UInt<1>(0h1), "") : assert_79
node _T_947 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_947 :
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(source_ok_1, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_951 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_T_951, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_951, UInt<1>(0h1), "") : assert_81
node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_955, UInt<1>(0h1), "") : assert_82
node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_960 = or(UInt<1>(0h1), _T_959)
node _T_961 = asUInt(reset)
node _T_962 = eq(_T_961, UInt<1>(0h0))
when _T_962 :
node _T_963 = eq(_T_960, UInt<1>(0h0))
when _T_963 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_960, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_964 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_965 = asUInt(reset)
node _T_966 = eq(_T_965, UInt<1>(0h0))
when _T_966 :
node _T_967 = eq(_T_964, UInt<1>(0h0))
when _T_967 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_964, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_968 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_969 = asUInt(reset)
node _T_970 = eq(_T_969, UInt<1>(0h0))
when _T_970 :
node _T_971 = eq(_T_968, UInt<1>(0h0))
when _T_971 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_968, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_972 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_972, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_976 = eq(a_first, UInt<1>(0h0))
node _T_977 = and(io.in.a.valid, _T_976)
when _T_977 :
node _T_978 = eq(io.in.a.bits.opcode, opcode)
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_978, UInt<1>(0h1), "") : assert_87
node _T_982 = eq(io.in.a.bits.param, param)
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_982, UInt<1>(0h1), "") : assert_88
node _T_986 = eq(io.in.a.bits.size, size)
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_986, UInt<1>(0h1), "") : assert_89
node _T_990 = eq(io.in.a.bits.source, source)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_990, UInt<1>(0h1), "") : assert_90
node _T_994 = eq(io.in.a.bits.address, address)
node _T_995 = asUInt(reset)
node _T_996 = eq(_T_995, UInt<1>(0h0))
when _T_996 :
node _T_997 = eq(_T_994, UInt<1>(0h0))
when _T_997 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_994, UInt<1>(0h1), "") : assert_91
node _T_998 = and(io.in.a.ready, io.in.a.valid)
node _T_999 = and(_T_998, a_first)
when _T_999 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1000 = eq(d_first, UInt<1>(0h0))
node _T_1001 = and(io.in.d.valid, _T_1000)
when _T_1001 :
node _T_1002 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_92
node _T_1006 = eq(io.in.d.bits.param, param_1)
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_93
node _T_1010 = eq(io.in.d.bits.size, size_1)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_94
node _T_1014 = eq(io.in.d.bits.source, source_1)
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_95
node _T_1018 = eq(io.in.d.bits.sink, sink)
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_96
node _T_1022 = eq(io.in.d.bits.denied, denied)
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_97
node _T_1026 = and(io.in.d.ready, io.in.d.valid)
node _T_1027 = and(_T_1026, d_first)
when _T_1027 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes : UInt<16>, clock, reset, UInt<16>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2>
connect a_set, UInt<2>(0h0)
wire a_set_wo_ready : UInt<2>
connect a_set_wo_ready, UInt<2>(0h0)
wire a_opcodes_set : UInt<8>
connect a_opcodes_set, UInt<8>(0h0)
wire a_sizes_set : UInt<16>
connect a_sizes_set, UInt<16>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1028 = and(io.in.a.valid, a_first_1)
node _T_1029 = and(_T_1028, UInt<1>(0h1))
when _T_1029 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1030 = and(io.in.a.ready, io.in.a.valid)
node _T_1031 = and(_T_1030, a_first_1)
node _T_1032 = and(_T_1031, UInt<1>(0h1))
when _T_1032 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1033 = dshr(inflight, io.in.a.bits.source)
node _T_1034 = bits(_T_1033, 0, 0)
node _T_1035 = eq(_T_1034, UInt<1>(0h0))
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2>
connect d_clr, UInt<2>(0h0)
wire d_clr_wo_ready : UInt<2>
connect d_clr_wo_ready, UInt<2>(0h0)
wire d_opcodes_clr : UInt<8>
connect d_opcodes_clr, UInt<8>(0h0)
wire d_sizes_clr : UInt<16>
connect d_sizes_clr, UInt<16>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1039 = and(io.in.d.valid, d_first_1)
node _T_1040 = and(_T_1039, UInt<1>(0h1))
node _T_1041 = eq(d_release_ack, UInt<1>(0h0))
node _T_1042 = and(_T_1040, _T_1041)
when _T_1042 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1043 = and(io.in.d.ready, io.in.d.valid)
node _T_1044 = and(_T_1043, d_first_1)
node _T_1045 = and(_T_1044, UInt<1>(0h1))
node _T_1046 = eq(d_release_ack, UInt<1>(0h0))
node _T_1047 = and(_T_1045, _T_1046)
when _T_1047 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1048 = and(io.in.d.valid, d_first_1)
node _T_1049 = and(_T_1048, UInt<1>(0h1))
node _T_1050 = eq(d_release_ack, UInt<1>(0h0))
node _T_1051 = and(_T_1049, _T_1050)
when _T_1051 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1052 = dshr(inflight, io.in.d.bits.source)
node _T_1053 = bits(_T_1052, 0, 0)
node _T_1054 = or(_T_1053, same_cycle_resp)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1058 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1059 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1060 = or(_T_1058, _T_1059)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_100
node _T_1064 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_101
else :
node _T_1068 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1069 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1070 = or(_T_1068, _T_1069)
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(_T_1070, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1070, UInt<1>(0h1), "") : assert_102
node _T_1074 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_103
node _T_1078 = and(io.in.d.valid, d_first_1)
node _T_1079 = and(_T_1078, a_first_1)
node _T_1080 = and(_T_1079, io.in.a.valid)
node _T_1081 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = eq(d_release_ack, UInt<1>(0h0))
node _T_1084 = and(_T_1082, _T_1083)
when _T_1084 :
node _T_1085 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1086 = or(_T_1085, io.in.a.ready)
node _T_1087 = asUInt(reset)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
when _T_1088 :
node _T_1089 = eq(_T_1086, UInt<1>(0h0))
when _T_1089 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1086, UInt<1>(0h1), "") : assert_104
node _T_1090 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1091 = orr(a_set_wo_ready)
node _T_1092 = eq(_T_1091, UInt<1>(0h0))
node _T_1093 = or(_T_1090, _T_1092)
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_64
node _T_1097 = orr(inflight)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
node _T_1099 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1100 = or(_T_1098, _T_1099)
node _T_1101 = lt(watchdog, plusarg_reader.out)
node _T_1102 = or(_T_1100, _T_1101)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1106 = and(io.in.a.ready, io.in.a.valid)
node _T_1107 = and(io.in.d.ready, io.in.d.valid)
node _T_1108 = or(_T_1106, _T_1107)
when _T_1108 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
regreset inflight_sizes_1 : UInt<16>, clock, reset, UInt<16>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2>
connect c_set, UInt<2>(0h0)
wire c_set_wo_ready : UInt<2>
connect c_set_wo_ready, UInt<2>(0h0)
wire c_opcodes_set : UInt<8>
connect c_opcodes_set, UInt<8>(0h0)
wire c_sizes_set : UInt<16>
connect c_sizes_set, UInt<16>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1109 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1110 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1111 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1112 = and(_T_1110, _T_1111)
node _T_1113 = and(_T_1109, _T_1112)
when _T_1113 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1114 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1115 = and(_T_1114, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1116 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1117 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1118 = and(_T_1116, _T_1117)
node _T_1119 = and(_T_1115, _T_1118)
when _T_1119 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1120 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1121 = bits(_T_1120, 0, 0)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2>
connect d_clr_1, UInt<2>(0h0)
wire d_clr_wo_ready_1 : UInt<2>
connect d_clr_wo_ready_1, UInt<2>(0h0)
wire d_opcodes_clr_1 : UInt<8>
connect d_opcodes_clr_1, UInt<8>(0h0)
wire d_sizes_clr_1 : UInt<16>
connect d_sizes_clr_1, UInt<16>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1126 = and(io.in.d.valid, d_first_2)
node _T_1127 = and(_T_1126, UInt<1>(0h1))
node _T_1128 = and(_T_1127, d_release_ack_1)
when _T_1128 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1129 = and(io.in.d.ready, io.in.d.valid)
node _T_1130 = and(_T_1129, d_first_2)
node _T_1131 = and(_T_1130, UInt<1>(0h1))
node _T_1132 = and(_T_1131, d_release_ack_1)
when _T_1132 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1133 = and(io.in.d.valid, d_first_2)
node _T_1134 = and(_T_1133, UInt<1>(0h1))
node _T_1135 = and(_T_1134, d_release_ack_1)
when _T_1135 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1136 = dshr(inflight_1, io.in.d.bits.source)
node _T_1137 = bits(_T_1136, 0, 0)
node _T_1138 = or(_T_1137, same_cycle_resp_1)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1142 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_109
else :
node _T_1146 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_110
node _T_1150 = and(io.in.d.valid, d_first_2)
node _T_1151 = and(_T_1150, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1152 = and(_T_1151, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1153 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1154 = and(_T_1152, _T_1153)
node _T_1155 = and(_T_1154, d_release_ack_1)
node _T_1156 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1157 = and(_T_1155, _T_1156)
when _T_1157 :
node _T_1158 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1159 = or(_T_1158, _WIRE_23.ready)
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_111
node _T_1163 = orr(c_set_wo_ready)
when _T_1163 :
node _T_1164 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_65
node _T_1168 = orr(inflight_1)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
node _T_1170 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1171 = or(_T_1169, _T_1170)
node _T_1172 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1173 = or(_T_1171, _T_1172)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1177 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1178 = and(io.in.d.ready, io.in.d.valid)
node _T_1179 = or(_T_1177, _T_1178)
when _T_1179 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_32( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59]
wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14]
wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27]
wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25]
wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28]
wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [15:0] c_sizes_set = 16'h0; // @[Monitor.scala:741:34]
wire [7:0] c_opcodes_set = 8'h0; // @[Monitor.scala:740:34]
wire [1:0] c_set = 2'h0; // @[Monitor.scala:738:34]
wire [1:0] c_set_wo_ready = 2'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire _source_ok_T_1 = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49]
wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}]
wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_WIRE_1_0 = _source_ok_T_2; // @[Parameters.scala:1138:31]
wire _source_ok_T_3 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_3; // @[Parameters.scala:1138:31]
wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1106 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1106; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1106; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1179 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1179; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1179; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1179; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [7:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [15:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [9:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [1:0] a_set; // @[Monitor.scala:626:34]
wire [1:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [7:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [15:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {8'h0, _a_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_1032 = _T_1106 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1032 ? _a_set_T : 2'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1032 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1032 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1032 ? _a_opcodes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1032 ? _a_sizes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1:0] d_clr; // @[Monitor.scala:664:34]
wire [1:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [7:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [15:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1078 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1078 & ~d_release_ack ? _d_clr_wo_ready_T : 2'h0; // @[OneHot.scala:58:35]
wire _T_1047 = _T_1179 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1047 ? _d_clr_T : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1047 ? _d_opcodes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1047 ? _d_sizes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [7:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [7:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [15:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46]
wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [9:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28]
wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [7:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {8'h0, _c_opcode_lookup_T_1 & 8'hF}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & 16'hFF; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [7:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [15:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1150 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1150 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire _T_1132 = _T_1179 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1132 ? _d_clr_T_1 : 2'h0; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1132 ? _d_opcodes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1132 ? _d_sizes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [7:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [7:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_23 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_23( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_223 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_224 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0)
node _source_ok_T = shr(io.in.a.bits.source, 4)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits = bits(_uncommonBits_T, 3, 0)
node _T_4 = shr(io.in.a.bits.source, 4)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<4>(0h9))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0)
node _T_24 = shr(io.in.a.bits.source, 4)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<4>(0h9))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<29>(0h10000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = or(_T_37, _T_42)
node _T_44 = and(_T_32, _T_43)
node _T_45 = or(UInt<1>(0h0), _T_44)
node _T_46 = and(_T_31, _T_45)
node _T_47 = asUInt(reset)
node _T_48 = eq(_T_47, UInt<1>(0h0))
when _T_48 :
node _T_49 = eq(_T_46, UInt<1>(0h0))
when _T_49 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_46, UInt<1>(0h1), "") : assert_2
node _T_50 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_51 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_52 = and(_T_50, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_55 = cvt(_T_54)
node _T_56 = and(_T_55, asSInt(UInt<17>(0h10000)))
node _T_57 = asSInt(_T_56)
node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0)))
node _T_59 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_60 = cvt(_T_59)
node _T_61 = and(_T_60, asSInt(UInt<29>(0h10000000)))
node _T_62 = asSInt(_T_61)
node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0)))
node _T_64 = or(_T_58, _T_63)
node _T_65 = and(_T_53, _T_64)
node _T_66 = or(UInt<1>(0h0), _T_65)
node _T_67 = and(UInt<1>(0h0), _T_66)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_67, UInt<1>(0h1), "") : assert_3
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_74 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(is_aligned, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_81 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_81, UInt<1>(0h1), "") : assert_7
node _T_85 = not(io.in.a.bits.mask)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_86, UInt<1>(0h1), "") : assert_8
node _T_90 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_94 :
node _T_95 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_96 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_97 = and(_T_95, _T_96)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0)
node _T_98 = shr(io.in.a.bits.source, 4)
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_101 = and(_T_99, _T_100)
node _T_102 = leq(uncommonBits_2, UInt<4>(0h9))
node _T_103 = and(_T_101, _T_102)
node _T_104 = and(_T_97, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_118)
node _T_120 = and(_T_105, _T_119)
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_120, UInt<1>(0h1), "") : assert_10
node _T_124 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_125 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_126 = and(_T_124, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_129 = cvt(_T_128)
node _T_130 = and(_T_129, asSInt(UInt<17>(0h10000)))
node _T_131 = asSInt(_T_130)
node _T_132 = eq(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_134 = cvt(_T_133)
node _T_135 = and(_T_134, asSInt(UInt<29>(0h10000000)))
node _T_136 = asSInt(_T_135)
node _T_137 = eq(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = or(_T_132, _T_137)
node _T_139 = and(_T_127, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = and(UInt<1>(0h0), _T_140)
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_141, UInt<1>(0h1), "") : assert_11
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_148 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_148, UInt<1>(0h1), "") : assert_13
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_155, UInt<1>(0h1), "") : assert_15
node _T_159 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_159, UInt<1>(0h1), "") : assert_16
node _T_163 = not(io.in.a.bits.mask)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = asUInt(reset)
node _T_166 = eq(_T_165, UInt<1>(0h0))
when _T_166 :
node _T_167 = eq(_T_164, UInt<1>(0h0))
when _T_167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_164, UInt<1>(0h1), "") : assert_17
node _T_168 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_168, UInt<1>(0h1), "") : assert_18
node _T_172 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_172 :
node _T_173 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_174 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_175 = and(_T_173, _T_174)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0)
node _T_176 = shr(io.in.a.bits.source, 4)
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_179 = and(_T_177, _T_178)
node _T_180 = leq(uncommonBits_3, UInt<4>(0h9))
node _T_181 = and(_T_179, _T_180)
node _T_182 = and(_T_175, _T_181)
node _T_183 = or(UInt<1>(0h0), _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_183, UInt<1>(0h1), "") : assert_19
node _T_187 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_188 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_189 = and(_T_187, _T_188)
node _T_190 = or(UInt<1>(0h0), _T_189)
node _T_191 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<17>(0h10000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<29>(0h10000000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = or(_T_195, _T_200)
node _T_202 = and(_T_190, _T_201)
node _T_203 = or(UInt<1>(0h0), _T_202)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_203, UInt<1>(0h1), "") : assert_20
node _T_207 = asUInt(reset)
node _T_208 = eq(_T_207, UInt<1>(0h0))
when _T_208 :
node _T_209 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(is_aligned, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_213 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_214 = asUInt(reset)
node _T_215 = eq(_T_214, UInt<1>(0h0))
when _T_215 :
node _T_216 = eq(_T_213, UInt<1>(0h0))
when _T_216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_213, UInt<1>(0h1), "") : assert_23
node _T_217 = eq(io.in.a.bits.mask, mask)
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(_T_217, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_217, UInt<1>(0h1), "") : assert_24
node _T_221 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_221, UInt<1>(0h1), "") : assert_25
node _T_225 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_225 :
node _T_226 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_227 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_229 = shr(io.in.a.bits.source, 4)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_4, UInt<4>(0h9))
node _T_234 = and(_T_232, _T_233)
node _T_235 = and(_T_228, _T_234)
node _T_236 = or(UInt<1>(0h0), _T_235)
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_239 = and(_T_237, _T_238)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_236, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_254, UInt<1>(0h1), "") : assert_26
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_264 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_264, UInt<1>(0h1), "") : assert_29
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_268, UInt<1>(0h1), "") : assert_30
node _T_272 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_272 :
node _T_273 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_274 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_275 = and(_T_273, _T_274)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_276 = shr(io.in.a.bits.source, 4)
node _T_277 = eq(_T_276, UInt<1>(0h0))
node _T_278 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_279 = and(_T_277, _T_278)
node _T_280 = leq(uncommonBits_5, UInt<4>(0h9))
node _T_281 = and(_T_279, _T_280)
node _T_282 = and(_T_275, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_285 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_286 = and(_T_284, _T_285)
node _T_287 = or(UInt<1>(0h0), _T_286)
node _T_288 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<17>(0h10000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<29>(0h10000000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = or(_T_292, _T_297)
node _T_299 = and(_T_287, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = and(_T_283, _T_300)
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_301, UInt<1>(0h1), "") : assert_31
node _T_305 = asUInt(reset)
node _T_306 = eq(_T_305, UInt<1>(0h0))
when _T_306 :
node _T_307 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(is_aligned, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_311 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_T_311, UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_311, UInt<1>(0h1), "") : assert_34
node _T_315 = not(mask)
node _T_316 = and(io.in.a.bits.mask, _T_315)
node _T_317 = eq(_T_316, UInt<1>(0h0))
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_317, UInt<1>(0h1), "") : assert_35
node _T_321 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_321 :
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_324 = and(_T_322, _T_323)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0)
node _T_325 = shr(io.in.a.bits.source, 4)
node _T_326 = eq(_T_325, UInt<1>(0h0))
node _T_327 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_328 = and(_T_326, _T_327)
node _T_329 = leq(uncommonBits_6, UInt<4>(0h9))
node _T_330 = and(_T_328, _T_329)
node _T_331 = and(_T_324, _T_330)
node _T_332 = or(UInt<1>(0h0), _T_331)
node _T_333 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<17>(0h10000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<29>(0h10000000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = or(_T_338, _T_343)
node _T_345 = and(_T_333, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_T_332, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_347, UInt<1>(0h1), "") : assert_36
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_354 = asUInt(reset)
node _T_355 = eq(_T_354, UInt<1>(0h0))
when _T_355 :
node _T_356 = eq(is_aligned, UInt<1>(0h0))
when _T_356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_357 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(_T_357, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_357, UInt<1>(0h1), "") : assert_39
node _T_361 = eq(io.in.a.bits.mask, mask)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_361, UInt<1>(0h1), "") : assert_40
node _T_365 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_365 :
node _T_366 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_367 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0)
node _T_369 = shr(io.in.a.bits.source, 4)
node _T_370 = eq(_T_369, UInt<1>(0h0))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_7, UInt<4>(0h9))
node _T_374 = and(_T_372, _T_373)
node _T_375 = and(_T_368, _T_374)
node _T_376 = or(UInt<1>(0h0), _T_375)
node _T_377 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_378 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<17>(0h10000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<29>(0h10000000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = or(_T_382, _T_387)
node _T_389 = and(_T_377, _T_388)
node _T_390 = or(UInt<1>(0h0), _T_389)
node _T_391 = and(_T_376, _T_390)
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_391, UInt<1>(0h1), "") : assert_41
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(is_aligned, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_401 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_401, UInt<1>(0h1), "") : assert_44
node _T_405 = eq(io.in.a.bits.mask, mask)
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_405, UInt<1>(0h1), "") : assert_45
node _T_409 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_409 :
node _T_410 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_411 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_412 = and(_T_410, _T_411)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0)
node _T_413 = shr(io.in.a.bits.source, 4)
node _T_414 = eq(_T_413, UInt<1>(0h0))
node _T_415 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_416 = and(_T_414, _T_415)
node _T_417 = leq(uncommonBits_8, UInt<4>(0h9))
node _T_418 = and(_T_416, _T_417)
node _T_419 = and(_T_412, _T_418)
node _T_420 = or(UInt<1>(0h0), _T_419)
node _T_421 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_423 = cvt(_T_422)
node _T_424 = and(_T_423, asSInt(UInt<17>(0h10000)))
node _T_425 = asSInt(_T_424)
node _T_426 = eq(_T_425, asSInt(UInt<1>(0h0)))
node _T_427 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<29>(0h10000000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = or(_T_426, _T_431)
node _T_433 = and(_T_421, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_T_420, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_435, UInt<1>(0h1), "") : assert_46
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(is_aligned, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_445 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_445, UInt<1>(0h1), "") : assert_49
node _T_449 = eq(io.in.a.bits.mask, mask)
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_449, UInt<1>(0h1), "") : assert_50
node _T_453 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_453, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_457 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_457, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 4)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_461 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_461 :
node _T_462 = asUInt(reset)
node _T_463 = eq(_T_462, UInt<1>(0h0))
when _T_463 :
node _T_464 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_465 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_466 = asUInt(reset)
node _T_467 = eq(_T_466, UInt<1>(0h0))
when _T_467 :
node _T_468 = eq(_T_465, UInt<1>(0h0))
when _T_468 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_465, UInt<1>(0h1), "") : assert_54
node _T_469 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_469, UInt<1>(0h1), "") : assert_55
node _T_473 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_473, UInt<1>(0h1), "") : assert_56
node _T_477 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_477, UInt<1>(0h1), "") : assert_57
node _T_481 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_481 :
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_485 = asUInt(reset)
node _T_486 = eq(_T_485, UInt<1>(0h0))
when _T_486 :
node _T_487 = eq(sink_ok, UInt<1>(0h0))
when _T_487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_488 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_488, UInt<1>(0h1), "") : assert_60
node _T_492 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_493 = asUInt(reset)
node _T_494 = eq(_T_493, UInt<1>(0h0))
when _T_494 :
node _T_495 = eq(_T_492, UInt<1>(0h0))
when _T_495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_492, UInt<1>(0h1), "") : assert_61
node _T_496 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_496, UInt<1>(0h1), "") : assert_62
node _T_500 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(_T_500, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_500, UInt<1>(0h1), "") : assert_63
node _T_504 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_505 = or(UInt<1>(0h1), _T_504)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_505, UInt<1>(0h1), "") : assert_64
node _T_509 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_509 :
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(sink_ok, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_516 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_517 = asUInt(reset)
node _T_518 = eq(_T_517, UInt<1>(0h0))
when _T_518 :
node _T_519 = eq(_T_516, UInt<1>(0h0))
when _T_519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_516, UInt<1>(0h1), "") : assert_67
node _T_520 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_520, UInt<1>(0h1), "") : assert_68
node _T_524 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_524, UInt<1>(0h1), "") : assert_69
node _T_528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_529 = or(_T_528, io.in.d.bits.corrupt)
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(_T_529, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_529, UInt<1>(0h1), "") : assert_70
node _T_533 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_534 = or(UInt<1>(0h1), _T_533)
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_534, UInt<1>(0h1), "") : assert_71
node _T_538 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_538 :
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_542 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_542, UInt<1>(0h1), "") : assert_73
node _T_546 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_546, UInt<1>(0h1), "") : assert_74
node _T_550 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_551 = or(UInt<1>(0h1), _T_550)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_551, UInt<1>(0h1), "") : assert_75
node _T_555 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_555 :
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_559 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_559, UInt<1>(0h1), "") : assert_77
node _T_563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_564 = or(_T_563, io.in.d.bits.corrupt)
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(_T_564, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_564, UInt<1>(0h1), "") : assert_78
node _T_568 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_569 = or(UInt<1>(0h1), _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_569, UInt<1>(0h1), "") : assert_79
node _T_573 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_573 :
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_577 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_577, UInt<1>(0h1), "") : assert_81
node _T_581 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_581, UInt<1>(0h1), "") : assert_82
node _T_585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_586 = or(UInt<1>(0h1), _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_586, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_590 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(_T_590, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_590, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_594 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_594, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_598 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_599 = asUInt(reset)
node _T_600 = eq(_T_599, UInt<1>(0h0))
when _T_600 :
node _T_601 = eq(_T_598, UInt<1>(0h0))
when _T_601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_598, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_602 = eq(a_first, UInt<1>(0h0))
node _T_603 = and(io.in.a.valid, _T_602)
when _T_603 :
node _T_604 = eq(io.in.a.bits.opcode, opcode)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_604, UInt<1>(0h1), "") : assert_87
node _T_608 = eq(io.in.a.bits.param, param)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_608, UInt<1>(0h1), "") : assert_88
node _T_612 = eq(io.in.a.bits.size, size)
node _T_613 = asUInt(reset)
node _T_614 = eq(_T_613, UInt<1>(0h0))
when _T_614 :
node _T_615 = eq(_T_612, UInt<1>(0h0))
when _T_615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_612, UInt<1>(0h1), "") : assert_89
node _T_616 = eq(io.in.a.bits.source, source)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_616, UInt<1>(0h1), "") : assert_90
node _T_620 = eq(io.in.a.bits.address, address)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_620, UInt<1>(0h1), "") : assert_91
node _T_624 = and(io.in.a.ready, io.in.a.valid)
node _T_625 = and(_T_624, a_first)
when _T_625 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_626 = eq(d_first, UInt<1>(0h0))
node _T_627 = and(io.in.d.valid, _T_626)
when _T_627 :
node _T_628 = eq(io.in.d.bits.opcode, opcode_1)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_628, UInt<1>(0h1), "") : assert_92
node _T_632 = eq(io.in.d.bits.param, param_1)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_632, UInt<1>(0h1), "") : assert_93
node _T_636 = eq(io.in.d.bits.size, size_1)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_636, UInt<1>(0h1), "") : assert_94
node _T_640 = eq(io.in.d.bits.source, source_1)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_640, UInt<1>(0h1), "") : assert_95
node _T_644 = eq(io.in.d.bits.sink, sink)
node _T_645 = asUInt(reset)
node _T_646 = eq(_T_645, UInt<1>(0h0))
when _T_646 :
node _T_647 = eq(_T_644, UInt<1>(0h0))
when _T_647 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_644, UInt<1>(0h1), "") : assert_96
node _T_648 = eq(io.in.d.bits.denied, denied)
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_648, UInt<1>(0h1), "") : assert_97
node _T_652 = and(io.in.d.ready, io.in.d.valid)
node _T_653 = and(_T_652, d_first)
when _T_653 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<10>
connect a_set, UInt<10>(0h0)
wire a_set_wo_ready : UInt<10>
connect a_set_wo_ready, UInt<10>(0h0)
wire a_opcodes_set : UInt<40>
connect a_opcodes_set, UInt<40>(0h0)
wire a_sizes_set : UInt<40>
connect a_sizes_set, UInt<40>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_654 = and(io.in.a.valid, a_first_1)
node _T_655 = and(_T_654, UInt<1>(0h1))
when _T_655 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_656 = and(io.in.a.ready, io.in.a.valid)
node _T_657 = and(_T_656, a_first_1)
node _T_658 = and(_T_657, UInt<1>(0h1))
when _T_658 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_659 = dshr(inflight, io.in.a.bits.source)
node _T_660 = bits(_T_659, 0, 0)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_661, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<10>
connect d_clr, UInt<10>(0h0)
wire d_clr_wo_ready : UInt<10>
connect d_clr_wo_ready, UInt<10>(0h0)
wire d_opcodes_clr : UInt<40>
connect d_opcodes_clr, UInt<40>(0h0)
wire d_sizes_clr : UInt<40>
connect d_sizes_clr, UInt<40>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_665 = and(io.in.d.valid, d_first_1)
node _T_666 = and(_T_665, UInt<1>(0h1))
node _T_667 = eq(d_release_ack, UInt<1>(0h0))
node _T_668 = and(_T_666, _T_667)
when _T_668 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_669 = and(io.in.d.ready, io.in.d.valid)
node _T_670 = and(_T_669, d_first_1)
node _T_671 = and(_T_670, UInt<1>(0h1))
node _T_672 = eq(d_release_ack, UInt<1>(0h0))
node _T_673 = and(_T_671, _T_672)
when _T_673 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_674 = and(io.in.d.valid, d_first_1)
node _T_675 = and(_T_674, UInt<1>(0h1))
node _T_676 = eq(d_release_ack, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
when _T_677 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_678 = dshr(inflight, io.in.d.bits.source)
node _T_679 = bits(_T_678, 0, 0)
node _T_680 = or(_T_679, same_cycle_resp)
node _T_681 = asUInt(reset)
node _T_682 = eq(_T_681, UInt<1>(0h0))
when _T_682 :
node _T_683 = eq(_T_680, UInt<1>(0h0))
when _T_683 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_680, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_684 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_685 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_686 = or(_T_684, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_686, UInt<1>(0h1), "") : assert_100
node _T_690 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_691 = asUInt(reset)
node _T_692 = eq(_T_691, UInt<1>(0h0))
when _T_692 :
node _T_693 = eq(_T_690, UInt<1>(0h0))
when _T_693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_690, UInt<1>(0h1), "") : assert_101
else :
node _T_694 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_695 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_696 = or(_T_694, _T_695)
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_696, UInt<1>(0h1), "") : assert_102
node _T_700 = eq(io.in.d.bits.size, a_size_lookup)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_700, UInt<1>(0h1), "") : assert_103
node _T_704 = and(io.in.d.valid, d_first_1)
node _T_705 = and(_T_704, a_first_1)
node _T_706 = and(_T_705, io.in.a.valid)
node _T_707 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_708 = and(_T_706, _T_707)
node _T_709 = eq(d_release_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_712 = or(_T_711, io.in.a.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_712, UInt<1>(0h1), "") : assert_104
node _T_716 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_717 = orr(a_set_wo_ready)
node _T_718 = eq(_T_717, UInt<1>(0h0))
node _T_719 = or(_T_716, _T_718)
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_719, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_86
node _T_723 = orr(inflight)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_726 = or(_T_724, _T_725)
node _T_727 = lt(watchdog, plusarg_reader.out)
node _T_728 = or(_T_726, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_728, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_732 = and(io.in.a.ready, io.in.a.valid)
node _T_733 = and(io.in.d.ready, io.in.d.valid)
node _T_734 = or(_T_732, _T_733)
when _T_734 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0)
regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<10>
connect c_set, UInt<10>(0h0)
wire c_set_wo_ready : UInt<10>
connect c_set_wo_ready, UInt<10>(0h0)
wire c_opcodes_set : UInt<40>
connect c_opcodes_set, UInt<40>(0h0)
wire c_sizes_set : UInt<40>
connect c_sizes_set, UInt<40>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_735 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_736 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_737 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_738 = and(_T_736, _T_737)
node _T_739 = and(_T_735, _T_738)
when _T_739 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_740 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_741 = and(_T_740, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_742 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_743 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_744 = and(_T_742, _T_743)
node _T_745 = and(_T_741, _T_744)
when _T_745 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_746 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_747 = bits(_T_746, 0, 0)
node _T_748 = eq(_T_747, UInt<1>(0h0))
node _T_749 = asUInt(reset)
node _T_750 = eq(_T_749, UInt<1>(0h0))
when _T_750 :
node _T_751 = eq(_T_748, UInt<1>(0h0))
when _T_751 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_748, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<10>
connect d_clr_1, UInt<10>(0h0)
wire d_clr_wo_ready_1 : UInt<10>
connect d_clr_wo_ready_1, UInt<10>(0h0)
wire d_opcodes_clr_1 : UInt<40>
connect d_opcodes_clr_1, UInt<40>(0h0)
wire d_sizes_clr_1 : UInt<40>
connect d_sizes_clr_1, UInt<40>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_752 = and(io.in.d.valid, d_first_2)
node _T_753 = and(_T_752, UInt<1>(0h1))
node _T_754 = and(_T_753, d_release_ack_1)
when _T_754 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_755 = and(io.in.d.ready, io.in.d.valid)
node _T_756 = and(_T_755, d_first_2)
node _T_757 = and(_T_756, UInt<1>(0h1))
node _T_758 = and(_T_757, d_release_ack_1)
when _T_758 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_759 = and(io.in.d.valid, d_first_2)
node _T_760 = and(_T_759, UInt<1>(0h1))
node _T_761 = and(_T_760, d_release_ack_1)
when _T_761 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_762 = dshr(inflight_1, io.in.d.bits.source)
node _T_763 = bits(_T_762, 0, 0)
node _T_764 = or(_T_763, same_cycle_resp_1)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_764, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_768 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_769 = asUInt(reset)
node _T_770 = eq(_T_769, UInt<1>(0h0))
when _T_770 :
node _T_771 = eq(_T_768, UInt<1>(0h0))
when _T_771 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_768, UInt<1>(0h1), "") : assert_109
else :
node _T_772 = eq(io.in.d.bits.size, c_size_lookup)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_772, UInt<1>(0h1), "") : assert_110
node _T_776 = and(io.in.d.valid, d_first_2)
node _T_777 = and(_T_776, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_778 = and(_T_777, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_779 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_780 = and(_T_778, _T_779)
node _T_781 = and(_T_780, d_release_ack_1)
node _T_782 = eq(c_probe_ack, UInt<1>(0h0))
node _T_783 = and(_T_781, _T_782)
when _T_783 :
node _T_784 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_785 = or(_T_784, _WIRE_23.ready)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_785, UInt<1>(0h1), "") : assert_111
node _T_789 = orr(c_set_wo_ready)
when _T_789 :
node _T_790 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_791 = asUInt(reset)
node _T_792 = eq(_T_791, UInt<1>(0h0))
when _T_792 :
node _T_793 = eq(_T_790, UInt<1>(0h0))
when _T_793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_790, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_87
node _T_794 = orr(inflight_1)
node _T_795 = eq(_T_794, UInt<1>(0h0))
node _T_796 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_797 = or(_T_795, _T_796)
node _T_798 = lt(watchdog_1, plusarg_reader_1.out)
node _T_799 = or(_T_797, _T_798)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:50:30)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_799, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_803 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_804 = and(io.in.d.ready, io.in.d.valid)
node _T_805 = or(_T_803, _T_804)
when _T_805 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_43( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_158 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_414
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_158( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_414 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_56 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_312
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_56( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_312 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLNoC_1_router_10ClockSinkDomain :
output auto : { routers_debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, routers_source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, routers_source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, routers_source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip routers_dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst routers of Router_39
connect routers.clock, childClock
connect routers.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect routers.auto.dest_nodes_in_0, auto.routers_dest_nodes_in_0
connect routers.auto.dest_nodes_in_1, auto.routers_dest_nodes_in_1
connect routers.auto.dest_nodes_in_2, auto.routers_dest_nodes_in_2
connect routers.auto.source_nodes_out_0.vc_free, auto.routers_source_nodes_out_0.vc_free
connect routers.auto.source_nodes_out_0.credit_return, auto.routers_source_nodes_out_0.credit_return
connect auto.routers_source_nodes_out_0.flit, routers.auto.source_nodes_out_0.flit
connect routers.auto.source_nodes_out_1.vc_free, auto.routers_source_nodes_out_1.vc_free
connect routers.auto.source_nodes_out_1.credit_return, auto.routers_source_nodes_out_1.credit_return
connect auto.routers_source_nodes_out_1.flit, routers.auto.source_nodes_out_1.flit
connect routers.auto.source_nodes_out_2.vc_free, auto.routers_source_nodes_out_2.vc_free
connect routers.auto.source_nodes_out_2.credit_return, auto.routers_source_nodes_out_2.credit_return
connect auto.routers_source_nodes_out_2.flit, routers.auto.source_nodes_out_2.flit
connect auto.routers_debug_out, routers.auto.debug_out
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module TLNoC_1_router_10ClockSinkDomain( // @[ClockDomain.scala:14:9]
output [2:0] auto_routers_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_routers_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_routers_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_routers_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_routers_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_routers_dest_nodes_in_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
Router_39 routers ( // @[NoC.scala:67:22]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_debug_out_va_stall_0 (auto_routers_debug_out_va_stall_0),
.auto_debug_out_va_stall_1 (auto_routers_debug_out_va_stall_1),
.auto_debug_out_va_stall_2 (auto_routers_debug_out_va_stall_2),
.auto_debug_out_sa_stall_0 (auto_routers_debug_out_sa_stall_0),
.auto_debug_out_sa_stall_1 (auto_routers_debug_out_sa_stall_1),
.auto_debug_out_sa_stall_2 (auto_routers_debug_out_sa_stall_2),
.auto_source_nodes_out_2_flit_0_valid (auto_routers_source_nodes_out_2_flit_0_valid),
.auto_source_nodes_out_2_flit_0_bits_head (auto_routers_source_nodes_out_2_flit_0_bits_head),
.auto_source_nodes_out_2_flit_0_bits_tail (auto_routers_source_nodes_out_2_flit_0_bits_tail),
.auto_source_nodes_out_2_flit_0_bits_payload (auto_routers_source_nodes_out_2_flit_0_bits_payload),
.auto_source_nodes_out_2_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_2_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_2_credit_return (auto_routers_source_nodes_out_2_credit_return),
.auto_source_nodes_out_2_vc_free (auto_routers_source_nodes_out_2_vc_free),
.auto_source_nodes_out_1_flit_0_valid (auto_routers_source_nodes_out_1_flit_0_valid),
.auto_source_nodes_out_1_flit_0_bits_head (auto_routers_source_nodes_out_1_flit_0_bits_head),
.auto_source_nodes_out_1_flit_0_bits_tail (auto_routers_source_nodes_out_1_flit_0_bits_tail),
.auto_source_nodes_out_1_flit_0_bits_payload (auto_routers_source_nodes_out_1_flit_0_bits_payload),
.auto_source_nodes_out_1_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_1_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_1_credit_return (auto_routers_source_nodes_out_1_credit_return),
.auto_source_nodes_out_1_vc_free (auto_routers_source_nodes_out_1_vc_free),
.auto_source_nodes_out_0_flit_0_valid (auto_routers_source_nodes_out_0_flit_0_valid),
.auto_source_nodes_out_0_flit_0_bits_head (auto_routers_source_nodes_out_0_flit_0_bits_head),
.auto_source_nodes_out_0_flit_0_bits_tail (auto_routers_source_nodes_out_0_flit_0_bits_tail),
.auto_source_nodes_out_0_flit_0_bits_payload (auto_routers_source_nodes_out_0_flit_0_bits_payload),
.auto_source_nodes_out_0_flit_0_bits_flow_vnet_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node),
.auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id (auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id),
.auto_source_nodes_out_0_flit_0_bits_virt_channel_id (auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id),
.auto_source_nodes_out_0_credit_return (auto_routers_source_nodes_out_0_credit_return),
.auto_source_nodes_out_0_vc_free (auto_routers_source_nodes_out_0_vc_free),
.auto_dest_nodes_in_2_flit_0_valid (auto_routers_dest_nodes_in_2_flit_0_valid),
.auto_dest_nodes_in_2_flit_0_bits_head (auto_routers_dest_nodes_in_2_flit_0_bits_head),
.auto_dest_nodes_in_2_flit_0_bits_tail (auto_routers_dest_nodes_in_2_flit_0_bits_tail),
.auto_dest_nodes_in_2_flit_0_bits_payload (auto_routers_dest_nodes_in_2_flit_0_bits_payload),
.auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_2_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_2_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_2_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_2_credit_return (auto_routers_dest_nodes_in_2_credit_return),
.auto_dest_nodes_in_2_vc_free (auto_routers_dest_nodes_in_2_vc_free),
.auto_dest_nodes_in_1_flit_0_valid (auto_routers_dest_nodes_in_1_flit_0_valid),
.auto_dest_nodes_in_1_flit_0_bits_head (auto_routers_dest_nodes_in_1_flit_0_bits_head),
.auto_dest_nodes_in_1_flit_0_bits_tail (auto_routers_dest_nodes_in_1_flit_0_bits_tail),
.auto_dest_nodes_in_1_flit_0_bits_payload (auto_routers_dest_nodes_in_1_flit_0_bits_payload),
.auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_1_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_1_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_1_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_1_credit_return (auto_routers_dest_nodes_in_1_credit_return),
.auto_dest_nodes_in_1_vc_free (auto_routers_dest_nodes_in_1_vc_free),
.auto_dest_nodes_in_0_flit_0_valid (auto_routers_dest_nodes_in_0_flit_0_valid),
.auto_dest_nodes_in_0_flit_0_bits_head (auto_routers_dest_nodes_in_0_flit_0_bits_head),
.auto_dest_nodes_in_0_flit_0_bits_tail (auto_routers_dest_nodes_in_0_flit_0_bits_tail),
.auto_dest_nodes_in_0_flit_0_bits_payload (auto_routers_dest_nodes_in_0_flit_0_bits_payload),
.auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_vnet_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node),
.auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id (auto_routers_dest_nodes_in_0_flit_0_bits_flow_egress_node_id),
.auto_dest_nodes_in_0_flit_0_bits_virt_channel_id (auto_routers_dest_nodes_in_0_flit_0_bits_virt_channel_id),
.auto_dest_nodes_in_0_credit_return (auto_routers_dest_nodes_in_0_credit_return),
.auto_dest_nodes_in_0_vc_free (auto_routers_dest_nodes_in_0_vc_free)
); // @[NoC.scala:67:22]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e5_s11_5 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<7>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<4>, highAlignedSigC : UInt<13>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<23>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 22, 22)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 21, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 35, 12)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 12, 11)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 33, 13)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 11, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 12, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 23, 8)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 10, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 0)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[3]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 10, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec[0])
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<5>(0h10)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 2, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 0, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_5, 1, 1)
node _CDom_reduced4SigExtra_T_8 = cat(_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7)
node _CDom_reduced4SigExtra_T_9 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_8)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_9)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 25, 25)
node _notCDom_absSigSum_T = bits(sigSum, 24, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 24, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[13]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 24, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = mux(_notCDom_normDistReduced2_T_1, UInt<4>(0hb), UInt<4>(0hc))
node _notCDom_normDistReduced2_T_14 = mux(_notCDom_normDistReduced2_T_2, UInt<4>(0ha), _notCDom_normDistReduced2_T_13)
node _notCDom_normDistReduced2_T_15 = mux(_notCDom_normDistReduced2_T_3, UInt<4>(0h9), _notCDom_normDistReduced2_T_14)
node _notCDom_normDistReduced2_T_16 = mux(_notCDom_normDistReduced2_T_4, UInt<4>(0h8), _notCDom_normDistReduced2_T_15)
node _notCDom_normDistReduced2_T_17 = mux(_notCDom_normDistReduced2_T_5, UInt<3>(0h7), _notCDom_normDistReduced2_T_16)
node _notCDom_normDistReduced2_T_18 = mux(_notCDom_normDistReduced2_T_6, UInt<3>(0h6), _notCDom_normDistReduced2_T_17)
node _notCDom_normDistReduced2_T_19 = mux(_notCDom_normDistReduced2_T_7, UInt<3>(0h5), _notCDom_normDistReduced2_T_18)
node _notCDom_normDistReduced2_T_20 = mux(_notCDom_normDistReduced2_T_8, UInt<3>(0h4), _notCDom_normDistReduced2_T_19)
node _notCDom_normDistReduced2_T_21 = mux(_notCDom_normDistReduced2_T_9, UInt<2>(0h3), _notCDom_normDistReduced2_T_20)
node _notCDom_normDistReduced2_T_22 = mux(_notCDom_normDistReduced2_T_10, UInt<2>(0h2), _notCDom_normDistReduced2_T_21)
node _notCDom_normDistReduced2_T_23 = mux(_notCDom_normDistReduced2_T_11, UInt<1>(0h1), _notCDom_normDistReduced2_T_22)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_12, UInt<1>(0h0), _notCDom_normDistReduced2_T_23)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 25, 10)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 5, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 1)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[4]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 6, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_reducedVec[1], notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_reducedVec[3], notCDom_reduced4SigExtra_reducedVec[2])
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 3, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 1, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 0, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_6, 1, 1)
node _notCDom_reduced4SigExtra_T_9 = cat(_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8)
node _notCDom_reduced4SigExtra_T_10 = bits(_notCDom_reduced4SigExtra_T_5, 2, 2)
node _notCDom_reduced4SigExtra_T_11 = cat(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10)
node _notCDom_reduced4SigExtra_T_12 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_11)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_12)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 13, 12)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e5_s11_5( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [6:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [3:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [12:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [22:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [6:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [13:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [6:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [3:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [12:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [22:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[MulAddRecFN.scala:169:7]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [6:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [13:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [6:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [13:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[MulAddRecFN.scala:169:7, :186:45]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[22]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [13:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 14'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [12:0] _sigSum_T_2 = _sigSum_T_1[12:0]; // @[MulAddRecFN.scala:193:47]
wire [12:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [21:0] _sigSum_T_4 = io_mulAddResult_0[21:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [34:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [35:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [7:0] _GEN = {io_fromPreMul_sExpSum_0[6], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [7:0] _CDom_sExp_T_1 = _GEN - {{6{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [6:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:203:43]
wire [6:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [23:0] _CDom_absSigSum_T = sigSum[35:12]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [23:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[12:11]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [20:0] _CDom_absSigSum_T_4 = sigSum[33:13]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [23:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [23:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [10:0] _CDom_absSigSumExtra_T = sigSum[11:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [10:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [11:0] _CDom_absSigSumExtra_T_3 = sigSum[12:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [38:0] _CDom_mainSig_T = {15'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [15:0] CDom_mainSig = _CDom_mainSig_T[23:8]; // @[MulAddRecFN.scala:219:{24,56}]
wire [10:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[10:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [10:0] _CDom_reduced4SigExtra_T_1 = _CDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[10:8]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[3:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [1:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [4:0] CDom_reduced4SigExtra_shift = $signed(5'sh10 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [1:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[2:1]; // @[primitives.scala:76:56, :78:22]
wire _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[0]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_5[1]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_8 = {_CDom_reduced4SigExtra_T_6, _CDom_reduced4SigExtra_T_7}; // @[primitives.scala:77:20]
wire [2:0] _CDom_reduced4SigExtra_T_9 = {1'h0, _CDom_reduced4SigExtra_T_2[1:0] & _CDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_9; // @[MulAddRecFN.scala:222:72, :223:73]
wire [12:0] _CDom_sig_T = CDom_mainSig[15:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [13:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[25]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [24:0] _notCDom_absSigSum_T = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [24:0] _notCDom_absSigSum_T_2 = sigSum[24:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [24:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [25:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {25'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [24:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[24:0]; // @[MulAddRecFN.scala:236:41]
wire [24:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[24]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire [3:0] _notCDom_normDistReduced2_T_13 = _notCDom_normDistReduced2_T_1 ? 4'hB : 4'hC; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_14 = _notCDom_normDistReduced2_T_2 ? 4'hA : _notCDom_normDistReduced2_T_13; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_15 = _notCDom_normDistReduced2_T_3 ? 4'h9 : _notCDom_normDistReduced2_T_14; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_16 = _notCDom_normDistReduced2_T_4 ? 4'h8 : _notCDom_normDistReduced2_T_15; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_17 = _notCDom_normDistReduced2_T_5 ? 4'h7 : _notCDom_normDistReduced2_T_16; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_18 = _notCDom_normDistReduced2_T_6 ? 4'h6 : _notCDom_normDistReduced2_T_17; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_19 = _notCDom_normDistReduced2_T_7 ? 4'h5 : _notCDom_normDistReduced2_T_18; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_20 = _notCDom_normDistReduced2_T_8 ? 4'h4 : _notCDom_normDistReduced2_T_19; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_21 = _notCDom_normDistReduced2_T_9 ? 4'h3 : _notCDom_normDistReduced2_T_20; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_22 = _notCDom_normDistReduced2_T_10 ? 4'h2 : _notCDom_normDistReduced2_T_21; // @[Mux.scala:50:70]
wire [3:0] _notCDom_normDistReduced2_T_23 = _notCDom_normDistReduced2_T_11 ? 4'h1 : _notCDom_normDistReduced2_T_22; // @[Mux.scala:50:70]
wire [3:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_12 ? 4'h0 : _notCDom_normDistReduced2_T_23; // @[Mux.scala:50:70]
wire [4:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [5:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [7:0] _notCDom_sExp_T_1 = _GEN - {{2{_notCDom_sExp_T[5]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [6:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[6:0]; // @[MulAddRecFN.scala:241:46]
wire [6:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [55:0] _notCDom_mainSig_T = {31'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [15:0] notCDom_mainSig = _notCDom_mainSig_T[25:10]; // @[MulAddRecFN.scala:243:{27,50}]
wire [5:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[5:0]; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_1 = {_notCDom_reduced4SigExtra_T, 1'h0}; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[6]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = _notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_reducedVec_1, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_reducedVec_3, notCDom_reduced4SigExtra_reducedVec_2}; // @[primitives.scala:101:30, :107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [2:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[3:1]; // @[Mux.scala:50:70]
wire [2:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] notCDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [2:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[3:1]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[1:0]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_6[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_9 = {_notCDom_reduced4SigExtra_T_7, _notCDom_reduced4SigExtra_T_8}; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_10 = _notCDom_reduced4SigExtra_T_5[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _notCDom_reduced4SigExtra_T_11 = {_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_10}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_12 = {1'h0, _notCDom_reduced4SigExtra_T_2[2:0] & _notCDom_reduced4SigExtra_T_11}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_12; // @[MulAddRecFN.scala:247:78, :249:11]
wire [12:0] _notCDom_sig_T = notCDom_mainSig[15:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [13:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[13:12]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = notCDom_completeCancellation ? roundingMode_min : _notCDom_sign_T; // @[MulAddRecFN.scala:186:45, :255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_3 = ~roundingMode_min; // @[MulAddRecFN.scala:186:45, :287:29]
wire _io_rawOut_sign_T_4 = notNaN_addZeros & _io_rawOut_sign_T_3; // @[MulAddRecFN.scala:267:58, :287:{26,29}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_8 = notNaN_addZeros & roundingMode_min; // @[MulAddRecFN.scala:186:45, :267:58, :289:26]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_10 = _io_rawOut_sign_T_8 & _io_rawOut_sign_T_9; // @[MulAddRecFN.scala:289:{26,46}, :290:37]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7 | _io_rawOut_sign_T_10; // @[MulAddRecFN.scala:286:43, :288:48, :289:46]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<27>(0h4000000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<13>(0h1000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<30>(0h20000000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_137 = cvt(_T_136)
node _T_138 = and(_T_137, asSInt(UInt<15>(0h4000)))
node _T_139 = asSInt(_T_138)
node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = or(_T_100, _T_105)
node _T_142 = or(_T_141, _T_110)
node _T_143 = or(_T_142, _T_115)
node _T_144 = or(_T_143, _T_120)
node _T_145 = or(_T_144, _T_125)
node _T_146 = or(_T_145, _T_130)
node _T_147 = or(_T_146, _T_135)
node _T_148 = or(_T_147, _T_140)
node _T_149 = and(_T_95, _T_148)
node _T_150 = or(UInt<1>(0h0), _T_149)
node _T_151 = and(_T_94, _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_151, UInt<1>(0h1), "") : assert_2
node _T_155 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_156 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_157 = and(_T_155, _T_156)
node _T_158 = or(UInt<1>(0h0), _T_157)
node _T_159 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<14>(0h2000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<13>(0h1000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_170 = cvt(_T_169)
node _T_171 = and(_T_170, asSInt(UInt<17>(0h10000)))
node _T_172 = asSInt(_T_171)
node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0)))
node _T_174 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_175 = cvt(_T_174)
node _T_176 = and(_T_175, asSInt(UInt<18>(0h2f000)))
node _T_177 = asSInt(_T_176)
node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0)))
node _T_179 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<17>(0h10000)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<27>(0h4000000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<30>(0h20000000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<15>(0h4000)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = or(_T_163, _T_168)
node _T_205 = or(_T_204, _T_173)
node _T_206 = or(_T_205, _T_178)
node _T_207 = or(_T_206, _T_183)
node _T_208 = or(_T_207, _T_188)
node _T_209 = or(_T_208, _T_193)
node _T_210 = or(_T_209, _T_198)
node _T_211 = or(_T_210, _T_203)
node _T_212 = and(_T_158, _T_211)
node _T_213 = or(UInt<1>(0h0), _T_212)
node _T_214 = and(UInt<1>(0h0), _T_213)
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(_T_214, UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_214, UInt<1>(0h1), "") : assert_3
node _T_218 = asUInt(reset)
node _T_219 = eq(_T_218, UInt<1>(0h0))
when _T_219 :
node _T_220 = eq(source_ok, UInt<1>(0h0))
when _T_220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_221 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_221, UInt<1>(0h1), "") : assert_5
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_228 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_228, UInt<1>(0h1), "") : assert_7
node _T_232 = not(io.in.a.bits.mask)
node _T_233 = eq(_T_232, UInt<1>(0h0))
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_233, UInt<1>(0h1), "") : assert_8
node _T_237 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_238 = asUInt(reset)
node _T_239 = eq(_T_238, UInt<1>(0h0))
when _T_239 :
node _T_240 = eq(_T_237, UInt<1>(0h0))
when _T_240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_237, UInt<1>(0h1), "") : assert_9
node _T_241 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_241 :
node _T_242 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_243 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_244 = and(_T_242, _T_243)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_245 = shr(io.in.a.bits.source, 2)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_248 = and(_T_246, _T_247)
node _T_249 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_251 = shr(io.in.a.bits.source, 2)
node _T_252 = eq(_T_251, UInt<1>(0h1))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_257 = shr(io.in.a.bits.source, 2)
node _T_258 = eq(_T_257, UInt<2>(0h2))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_263 = shr(io.in.a.bits.source, 2)
node _T_264 = eq(_T_263, UInt<2>(0h3))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_268 = and(_T_266, _T_267)
node _T_269 = or(_T_250, _T_256)
node _T_270 = or(_T_269, _T_262)
node _T_271 = or(_T_270, _T_268)
node _T_272 = and(_T_244, _T_271)
node _T_273 = or(UInt<1>(0h0), _T_272)
node _T_274 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_275 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_276 = cvt(_T_275)
node _T_277 = and(_T_276, asSInt(UInt<14>(0h2000)))
node _T_278 = asSInt(_T_277)
node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0)))
node _T_280 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_281 = cvt(_T_280)
node _T_282 = and(_T_281, asSInt(UInt<13>(0h1000)))
node _T_283 = asSInt(_T_282)
node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_286 = cvt(_T_285)
node _T_287 = and(_T_286, asSInt(UInt<17>(0h10000)))
node _T_288 = asSInt(_T_287)
node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0)))
node _T_290 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<18>(0h2f000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<17>(0h10000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<27>(0h4000000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<13>(0h1000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<30>(0h20000000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<15>(0h4000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = or(_T_279, _T_284)
node _T_321 = or(_T_320, _T_289)
node _T_322 = or(_T_321, _T_294)
node _T_323 = or(_T_322, _T_299)
node _T_324 = or(_T_323, _T_304)
node _T_325 = or(_T_324, _T_309)
node _T_326 = or(_T_325, _T_314)
node _T_327 = or(_T_326, _T_319)
node _T_328 = and(_T_274, _T_327)
node _T_329 = or(UInt<1>(0h0), _T_328)
node _T_330 = and(_T_273, _T_329)
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_330, UInt<1>(0h1), "") : assert_10
node _T_334 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_335 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_336 = and(_T_334, _T_335)
node _T_337 = or(UInt<1>(0h0), _T_336)
node _T_338 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<14>(0h2000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<13>(0h1000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<17>(0h10000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<18>(0h2f000)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<17>(0h10000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<27>(0h4000000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_374 = cvt(_T_373)
node _T_375 = and(_T_374, asSInt(UInt<30>(0h20000000)))
node _T_376 = asSInt(_T_375)
node _T_377 = eq(_T_376, asSInt(UInt<1>(0h0)))
node _T_378 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<15>(0h4000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = or(_T_342, _T_347)
node _T_384 = or(_T_383, _T_352)
node _T_385 = or(_T_384, _T_357)
node _T_386 = or(_T_385, _T_362)
node _T_387 = or(_T_386, _T_367)
node _T_388 = or(_T_387, _T_372)
node _T_389 = or(_T_388, _T_377)
node _T_390 = or(_T_389, _T_382)
node _T_391 = and(_T_337, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = and(UInt<1>(0h0), _T_392)
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_393, UInt<1>(0h1), "") : assert_11
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(source_ok, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_400, UInt<1>(0h1), "") : assert_13
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(is_aligned, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_407, UInt<1>(0h1), "") : assert_15
node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_411, UInt<1>(0h1), "") : assert_16
node _T_415 = not(io.in.a.bits.mask)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_416, UInt<1>(0h1), "") : assert_17
node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_420, UInt<1>(0h1), "") : assert_18
node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_424 :
node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_427 = and(_T_425, _T_426)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_428 = shr(io.in.a.bits.source, 2)
node _T_429 = eq(_T_428, UInt<1>(0h0))
node _T_430 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_431 = and(_T_429, _T_430)
node _T_432 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_433 = and(_T_431, _T_432)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_434 = shr(io.in.a.bits.source, 2)
node _T_435 = eq(_T_434, UInt<1>(0h1))
node _T_436 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_437 = and(_T_435, _T_436)
node _T_438 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_439 = and(_T_437, _T_438)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_440 = shr(io.in.a.bits.source, 2)
node _T_441 = eq(_T_440, UInt<2>(0h2))
node _T_442 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_443 = and(_T_441, _T_442)
node _T_444 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_445 = and(_T_443, _T_444)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_446 = shr(io.in.a.bits.source, 2)
node _T_447 = eq(_T_446, UInt<2>(0h3))
node _T_448 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_449 = and(_T_447, _T_448)
node _T_450 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_451 = and(_T_449, _T_450)
node _T_452 = or(_T_433, _T_439)
node _T_453 = or(_T_452, _T_445)
node _T_454 = or(_T_453, _T_451)
node _T_455 = and(_T_427, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_456, UInt<1>(0h1), "") : assert_19
node _T_460 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_461 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_462 = and(_T_460, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_465 = cvt(_T_464)
node _T_466 = and(_T_465, asSInt(UInt<13>(0h1000)))
node _T_467 = asSInt(_T_466)
node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0)))
node _T_469 = and(_T_463, _T_468)
node _T_470 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_471 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_472 = and(_T_470, _T_471)
node _T_473 = or(UInt<1>(0h0), _T_472)
node _T_474 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_475 = cvt(_T_474)
node _T_476 = and(_T_475, asSInt(UInt<14>(0h2000)))
node _T_477 = asSInt(_T_476)
node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0)))
node _T_479 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_480 = cvt(_T_479)
node _T_481 = and(_T_480, asSInt(UInt<17>(0h10000)))
node _T_482 = asSInt(_T_481)
node _T_483 = eq(_T_482, asSInt(UInt<1>(0h0)))
node _T_484 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_485 = cvt(_T_484)
node _T_486 = and(_T_485, asSInt(UInt<18>(0h2f000)))
node _T_487 = asSInt(_T_486)
node _T_488 = eq(_T_487, asSInt(UInt<1>(0h0)))
node _T_489 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_490 = cvt(_T_489)
node _T_491 = and(_T_490, asSInt(UInt<17>(0h10000)))
node _T_492 = asSInt(_T_491)
node _T_493 = eq(_T_492, asSInt(UInt<1>(0h0)))
node _T_494 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<27>(0h4000000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_500 = cvt(_T_499)
node _T_501 = and(_T_500, asSInt(UInt<13>(0h1000)))
node _T_502 = asSInt(_T_501)
node _T_503 = eq(_T_502, asSInt(UInt<1>(0h0)))
node _T_504 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<30>(0h20000000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<15>(0h4000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = or(_T_478, _T_483)
node _T_515 = or(_T_514, _T_488)
node _T_516 = or(_T_515, _T_493)
node _T_517 = or(_T_516, _T_498)
node _T_518 = or(_T_517, _T_503)
node _T_519 = or(_T_518, _T_508)
node _T_520 = or(_T_519, _T_513)
node _T_521 = and(_T_473, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_469)
node _T_523 = or(_T_522, _T_521)
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_523, UInt<1>(0h1), "") : assert_20
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(source_ok, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_530 = asUInt(reset)
node _T_531 = eq(_T_530, UInt<1>(0h0))
when _T_531 :
node _T_532 = eq(is_aligned, UInt<1>(0h0))
when _T_532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_533 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_534 = asUInt(reset)
node _T_535 = eq(_T_534, UInt<1>(0h0))
when _T_535 :
node _T_536 = eq(_T_533, UInt<1>(0h0))
when _T_536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_533, UInt<1>(0h1), "") : assert_23
node _T_537 = eq(io.in.a.bits.mask, mask)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_537, UInt<1>(0h1), "") : assert_24
node _T_541 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(_T_541, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_541, UInt<1>(0h1), "") : assert_25
node _T_545 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_545 :
node _T_546 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_547 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_548 = and(_T_546, _T_547)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_549 = shr(io.in.a.bits.source, 2)
node _T_550 = eq(_T_549, UInt<1>(0h0))
node _T_551 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_552 = and(_T_550, _T_551)
node _T_553 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_554 = and(_T_552, _T_553)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_555 = shr(io.in.a.bits.source, 2)
node _T_556 = eq(_T_555, UInt<1>(0h1))
node _T_557 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_558 = and(_T_556, _T_557)
node _T_559 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_560 = and(_T_558, _T_559)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_561 = shr(io.in.a.bits.source, 2)
node _T_562 = eq(_T_561, UInt<2>(0h2))
node _T_563 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_564 = and(_T_562, _T_563)
node _T_565 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_566 = and(_T_564, _T_565)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_567 = shr(io.in.a.bits.source, 2)
node _T_568 = eq(_T_567, UInt<2>(0h3))
node _T_569 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_570 = and(_T_568, _T_569)
node _T_571 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(_T_554, _T_560)
node _T_574 = or(_T_573, _T_566)
node _T_575 = or(_T_574, _T_572)
node _T_576 = and(_T_548, _T_575)
node _T_577 = or(UInt<1>(0h0), _T_576)
node _T_578 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_579 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_580 = and(_T_578, _T_579)
node _T_581 = or(UInt<1>(0h0), _T_580)
node _T_582 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<13>(0h1000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = and(_T_581, _T_586)
node _T_588 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_589 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_590 = and(_T_588, _T_589)
node _T_591 = or(UInt<1>(0h0), _T_590)
node _T_592 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<14>(0h2000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<18>(0h2f000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_603 = cvt(_T_602)
node _T_604 = and(_T_603, asSInt(UInt<17>(0h10000)))
node _T_605 = asSInt(_T_604)
node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0)))
node _T_607 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_608 = cvt(_T_607)
node _T_609 = and(_T_608, asSInt(UInt<27>(0h4000000)))
node _T_610 = asSInt(_T_609)
node _T_611 = eq(_T_610, asSInt(UInt<1>(0h0)))
node _T_612 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_613 = cvt(_T_612)
node _T_614 = and(_T_613, asSInt(UInt<13>(0h1000)))
node _T_615 = asSInt(_T_614)
node _T_616 = eq(_T_615, asSInt(UInt<1>(0h0)))
node _T_617 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_618 = cvt(_T_617)
node _T_619 = and(_T_618, asSInt(UInt<15>(0h4000)))
node _T_620 = asSInt(_T_619)
node _T_621 = eq(_T_620, asSInt(UInt<1>(0h0)))
node _T_622 = or(_T_596, _T_601)
node _T_623 = or(_T_622, _T_606)
node _T_624 = or(_T_623, _T_611)
node _T_625 = or(_T_624, _T_616)
node _T_626 = or(_T_625, _T_621)
node _T_627 = and(_T_591, _T_626)
node _T_628 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_629 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<17>(0h10000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = and(_T_628, _T_633)
node _T_635 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_636 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_637 = and(_T_635, _T_636)
node _T_638 = or(UInt<1>(0h0), _T_637)
node _T_639 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_640 = cvt(_T_639)
node _T_641 = and(_T_640, asSInt(UInt<30>(0h20000000)))
node _T_642 = asSInt(_T_641)
node _T_643 = eq(_T_642, asSInt(UInt<1>(0h0)))
node _T_644 = and(_T_638, _T_643)
node _T_645 = or(UInt<1>(0h0), _T_587)
node _T_646 = or(_T_645, _T_627)
node _T_647 = or(_T_646, _T_634)
node _T_648 = or(_T_647, _T_644)
node _T_649 = and(_T_577, _T_648)
node _T_650 = asUInt(reset)
node _T_651 = eq(_T_650, UInt<1>(0h0))
when _T_651 :
node _T_652 = eq(_T_649, UInt<1>(0h0))
when _T_652 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_649, UInt<1>(0h1), "") : assert_26
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(source_ok, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(is_aligned, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_659 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_659, UInt<1>(0h1), "") : assert_29
node _T_663 = eq(io.in.a.bits.mask, mask)
node _T_664 = asUInt(reset)
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(_T_663, UInt<1>(0h0))
when _T_666 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_663, UInt<1>(0h1), "") : assert_30
node _T_667 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_667 :
node _T_668 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_669 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_670 = and(_T_668, _T_669)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_671 = shr(io.in.a.bits.source, 2)
node _T_672 = eq(_T_671, UInt<1>(0h0))
node _T_673 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_674 = and(_T_672, _T_673)
node _T_675 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_676 = and(_T_674, _T_675)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_677 = shr(io.in.a.bits.source, 2)
node _T_678 = eq(_T_677, UInt<1>(0h1))
node _T_679 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_680 = and(_T_678, _T_679)
node _T_681 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_682 = and(_T_680, _T_681)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_683 = shr(io.in.a.bits.source, 2)
node _T_684 = eq(_T_683, UInt<2>(0h2))
node _T_685 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_686 = and(_T_684, _T_685)
node _T_687 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_688 = and(_T_686, _T_687)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_689 = shr(io.in.a.bits.source, 2)
node _T_690 = eq(_T_689, UInt<2>(0h3))
node _T_691 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_692 = and(_T_690, _T_691)
node _T_693 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(_T_676, _T_682)
node _T_696 = or(_T_695, _T_688)
node _T_697 = or(_T_696, _T_694)
node _T_698 = and(_T_670, _T_697)
node _T_699 = or(UInt<1>(0h0), _T_698)
node _T_700 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_701 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_702 = and(_T_700, _T_701)
node _T_703 = or(UInt<1>(0h0), _T_702)
node _T_704 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_711 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_712 = and(_T_710, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_712)
node _T_714 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_715 = cvt(_T_714)
node _T_716 = and(_T_715, asSInt(UInt<14>(0h2000)))
node _T_717 = asSInt(_T_716)
node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0)))
node _T_719 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<18>(0h2f000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_725 = cvt(_T_724)
node _T_726 = and(_T_725, asSInt(UInt<17>(0h10000)))
node _T_727 = asSInt(_T_726)
node _T_728 = eq(_T_727, asSInt(UInt<1>(0h0)))
node _T_729 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_730 = cvt(_T_729)
node _T_731 = and(_T_730, asSInt(UInt<27>(0h4000000)))
node _T_732 = asSInt(_T_731)
node _T_733 = eq(_T_732, asSInt(UInt<1>(0h0)))
node _T_734 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_735 = cvt(_T_734)
node _T_736 = and(_T_735, asSInt(UInt<13>(0h1000)))
node _T_737 = asSInt(_T_736)
node _T_738 = eq(_T_737, asSInt(UInt<1>(0h0)))
node _T_739 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_740 = cvt(_T_739)
node _T_741 = and(_T_740, asSInt(UInt<15>(0h4000)))
node _T_742 = asSInt(_T_741)
node _T_743 = eq(_T_742, asSInt(UInt<1>(0h0)))
node _T_744 = or(_T_718, _T_723)
node _T_745 = or(_T_744, _T_728)
node _T_746 = or(_T_745, _T_733)
node _T_747 = or(_T_746, _T_738)
node _T_748 = or(_T_747, _T_743)
node _T_749 = and(_T_713, _T_748)
node _T_750 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_751 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<17>(0h10000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = and(_T_750, _T_755)
node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_758 = leq(io.in.a.bits.size, UInt<4>(0h8))
node _T_759 = and(_T_757, _T_758)
node _T_760 = or(UInt<1>(0h0), _T_759)
node _T_761 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<30>(0h20000000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = and(_T_760, _T_765)
node _T_767 = or(UInt<1>(0h0), _T_709)
node _T_768 = or(_T_767, _T_749)
node _T_769 = or(_T_768, _T_756)
node _T_770 = or(_T_769, _T_766)
node _T_771 = and(_T_699, _T_770)
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_771, UInt<1>(0h1), "") : assert_31
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(source_ok, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(is_aligned, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_781 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_781, UInt<1>(0h1), "") : assert_34
node _T_785 = not(mask)
node _T_786 = and(io.in.a.bits.mask, _T_785)
node _T_787 = eq(_T_786, UInt<1>(0h0))
node _T_788 = asUInt(reset)
node _T_789 = eq(_T_788, UInt<1>(0h0))
when _T_789 :
node _T_790 = eq(_T_787, UInt<1>(0h0))
when _T_790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_787, UInt<1>(0h1), "") : assert_35
node _T_791 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_791 :
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_794 = and(_T_792, _T_793)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_795 = shr(io.in.a.bits.source, 2)
node _T_796 = eq(_T_795, UInt<1>(0h0))
node _T_797 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_798 = and(_T_796, _T_797)
node _T_799 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_800 = and(_T_798, _T_799)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<1>(0h1))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_807 = shr(io.in.a.bits.source, 2)
node _T_808 = eq(_T_807, UInt<2>(0h2))
node _T_809 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_810 = and(_T_808, _T_809)
node _T_811 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_813 = shr(io.in.a.bits.source, 2)
node _T_814 = eq(_T_813, UInt<2>(0h3))
node _T_815 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_816 = and(_T_814, _T_815)
node _T_817 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_818 = and(_T_816, _T_817)
node _T_819 = or(_T_800, _T_806)
node _T_820 = or(_T_819, _T_812)
node _T_821 = or(_T_820, _T_818)
node _T_822 = and(_T_794, _T_821)
node _T_823 = or(UInt<1>(0h0), _T_822)
node _T_824 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_825 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _T_827 = or(UInt<1>(0h0), _T_826)
node _T_828 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_829 = cvt(_T_828)
node _T_830 = and(_T_829, asSInt(UInt<14>(0h2000)))
node _T_831 = asSInt(_T_830)
node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0)))
node _T_833 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_834 = cvt(_T_833)
node _T_835 = and(_T_834, asSInt(UInt<13>(0h1000)))
node _T_836 = asSInt(_T_835)
node _T_837 = eq(_T_836, asSInt(UInt<1>(0h0)))
node _T_838 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_839 = cvt(_T_838)
node _T_840 = and(_T_839, asSInt(UInt<18>(0h2f000)))
node _T_841 = asSInt(_T_840)
node _T_842 = eq(_T_841, asSInt(UInt<1>(0h0)))
node _T_843 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_844 = cvt(_T_843)
node _T_845 = and(_T_844, asSInt(UInt<17>(0h10000)))
node _T_846 = asSInt(_T_845)
node _T_847 = eq(_T_846, asSInt(UInt<1>(0h0)))
node _T_848 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_849 = cvt(_T_848)
node _T_850 = and(_T_849, asSInt(UInt<27>(0h4000000)))
node _T_851 = asSInt(_T_850)
node _T_852 = eq(_T_851, asSInt(UInt<1>(0h0)))
node _T_853 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_854 = cvt(_T_853)
node _T_855 = and(_T_854, asSInt(UInt<13>(0h1000)))
node _T_856 = asSInt(_T_855)
node _T_857 = eq(_T_856, asSInt(UInt<1>(0h0)))
node _T_858 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_859 = cvt(_T_858)
node _T_860 = and(_T_859, asSInt(UInt<15>(0h4000)))
node _T_861 = asSInt(_T_860)
node _T_862 = eq(_T_861, asSInt(UInt<1>(0h0)))
node _T_863 = or(_T_832, _T_837)
node _T_864 = or(_T_863, _T_842)
node _T_865 = or(_T_864, _T_847)
node _T_866 = or(_T_865, _T_852)
node _T_867 = or(_T_866, _T_857)
node _T_868 = or(_T_867, _T_862)
node _T_869 = and(_T_827, _T_868)
node _T_870 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_871 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<17>(0h10000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<30>(0h20000000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = or(_T_875, _T_880)
node _T_882 = and(_T_870, _T_881)
node _T_883 = or(UInt<1>(0h0), _T_869)
node _T_884 = or(_T_883, _T_882)
node _T_885 = and(_T_823, _T_884)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_885, UInt<1>(0h1), "") : assert_36
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(source_ok, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(is_aligned, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_895 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_895, UInt<1>(0h1), "") : assert_39
node _T_899 = eq(io.in.a.bits.mask, mask)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_899, UInt<1>(0h1), "") : assert_40
node _T_903 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_903 :
node _T_904 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_905 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_906 = and(_T_904, _T_905)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_907 = shr(io.in.a.bits.source, 2)
node _T_908 = eq(_T_907, UInt<1>(0h0))
node _T_909 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_910 = and(_T_908, _T_909)
node _T_911 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_912 = and(_T_910, _T_911)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_913 = shr(io.in.a.bits.source, 2)
node _T_914 = eq(_T_913, UInt<1>(0h1))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_918 = and(_T_916, _T_917)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_919 = shr(io.in.a.bits.source, 2)
node _T_920 = eq(_T_919, UInt<2>(0h2))
node _T_921 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_922 = and(_T_920, _T_921)
node _T_923 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_924 = and(_T_922, _T_923)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_925 = shr(io.in.a.bits.source, 2)
node _T_926 = eq(_T_925, UInt<2>(0h3))
node _T_927 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_928 = and(_T_926, _T_927)
node _T_929 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _T_931 = or(_T_912, _T_918)
node _T_932 = or(_T_931, _T_924)
node _T_933 = or(_T_932, _T_930)
node _T_934 = and(_T_906, _T_933)
node _T_935 = or(UInt<1>(0h0), _T_934)
node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_937 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_938 = and(_T_936, _T_937)
node _T_939 = or(UInt<1>(0h0), _T_938)
node _T_940 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_941 = cvt(_T_940)
node _T_942 = and(_T_941, asSInt(UInt<14>(0h2000)))
node _T_943 = asSInt(_T_942)
node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0)))
node _T_945 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<18>(0h2f000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_956 = cvt(_T_955)
node _T_957 = and(_T_956, asSInt(UInt<17>(0h10000)))
node _T_958 = asSInt(_T_957)
node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0)))
node _T_960 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_961 = cvt(_T_960)
node _T_962 = and(_T_961, asSInt(UInt<27>(0h4000000)))
node _T_963 = asSInt(_T_962)
node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0)))
node _T_965 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_966 = cvt(_T_965)
node _T_967 = and(_T_966, asSInt(UInt<13>(0h1000)))
node _T_968 = asSInt(_T_967)
node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0)))
node _T_970 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<15>(0h4000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = or(_T_944, _T_949)
node _T_976 = or(_T_975, _T_954)
node _T_977 = or(_T_976, _T_959)
node _T_978 = or(_T_977, _T_964)
node _T_979 = or(_T_978, _T_969)
node _T_980 = or(_T_979, _T_974)
node _T_981 = and(_T_939, _T_980)
node _T_982 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_983 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_984 = cvt(_T_983)
node _T_985 = and(_T_984, asSInt(UInt<17>(0h10000)))
node _T_986 = asSInt(_T_985)
node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0)))
node _T_988 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_989 = cvt(_T_988)
node _T_990 = and(_T_989, asSInt(UInt<30>(0h20000000)))
node _T_991 = asSInt(_T_990)
node _T_992 = eq(_T_991, asSInt(UInt<1>(0h0)))
node _T_993 = or(_T_987, _T_992)
node _T_994 = and(_T_982, _T_993)
node _T_995 = or(UInt<1>(0h0), _T_981)
node _T_996 = or(_T_995, _T_994)
node _T_997 = and(_T_935, _T_996)
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_997, UInt<1>(0h1), "") : assert_41
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(source_ok, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(is_aligned, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1007 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_44
node _T_1011 = eq(io.in.a.bits.mask, mask)
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_45
node _T_1015 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1015 :
node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1017 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1018 = and(_T_1016, _T_1017)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1019 = shr(io.in.a.bits.source, 2)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
node _T_1021 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1022 = and(_T_1020, _T_1021)
node _T_1023 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1024 = and(_T_1022, _T_1023)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<1>(0h1))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1031 = shr(io.in.a.bits.source, 2)
node _T_1032 = eq(_T_1031, UInt<2>(0h2))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<2>(0h3))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = or(_T_1024, _T_1030)
node _T_1044 = or(_T_1043, _T_1036)
node _T_1045 = or(_T_1044, _T_1042)
node _T_1046 = and(_T_1018, _T_1045)
node _T_1047 = or(UInt<1>(0h0), _T_1046)
node _T_1048 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1049 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = or(UInt<1>(0h0), _T_1050)
node _T_1052 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1053 = cvt(_T_1052)
node _T_1054 = and(_T_1053, asSInt(UInt<13>(0h1000)))
node _T_1055 = asSInt(_T_1054)
node _T_1056 = eq(_T_1055, asSInt(UInt<1>(0h0)))
node _T_1057 = and(_T_1051, _T_1056)
node _T_1058 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1059 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1060 = cvt(_T_1059)
node _T_1061 = and(_T_1060, asSInt(UInt<14>(0h2000)))
node _T_1062 = asSInt(_T_1061)
node _T_1063 = eq(_T_1062, asSInt(UInt<1>(0h0)))
node _T_1064 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1065 = cvt(_T_1064)
node _T_1066 = and(_T_1065, asSInt(UInt<17>(0h10000)))
node _T_1067 = asSInt(_T_1066)
node _T_1068 = eq(_T_1067, asSInt(UInt<1>(0h0)))
node _T_1069 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1070 = cvt(_T_1069)
node _T_1071 = and(_T_1070, asSInt(UInt<18>(0h2f000)))
node _T_1072 = asSInt(_T_1071)
node _T_1073 = eq(_T_1072, asSInt(UInt<1>(0h0)))
node _T_1074 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1075 = cvt(_T_1074)
node _T_1076 = and(_T_1075, asSInt(UInt<17>(0h10000)))
node _T_1077 = asSInt(_T_1076)
node _T_1078 = eq(_T_1077, asSInt(UInt<1>(0h0)))
node _T_1079 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1080 = cvt(_T_1079)
node _T_1081 = and(_T_1080, asSInt(UInt<27>(0h4000000)))
node _T_1082 = asSInt(_T_1081)
node _T_1083 = eq(_T_1082, asSInt(UInt<1>(0h0)))
node _T_1084 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1085 = cvt(_T_1084)
node _T_1086 = and(_T_1085, asSInt(UInt<13>(0h1000)))
node _T_1087 = asSInt(_T_1086)
node _T_1088 = eq(_T_1087, asSInt(UInt<1>(0h0)))
node _T_1089 = xor(io.in.a.bits.address, UInt<31>(0h60000000))
node _T_1090 = cvt(_T_1089)
node _T_1091 = and(_T_1090, asSInt(UInt<30>(0h20000000)))
node _T_1092 = asSInt(_T_1091)
node _T_1093 = eq(_T_1092, asSInt(UInt<1>(0h0)))
node _T_1094 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1095 = cvt(_T_1094)
node _T_1096 = and(_T_1095, asSInt(UInt<15>(0h4000)))
node _T_1097 = asSInt(_T_1096)
node _T_1098 = eq(_T_1097, asSInt(UInt<1>(0h0)))
node _T_1099 = or(_T_1063, _T_1068)
node _T_1100 = or(_T_1099, _T_1073)
node _T_1101 = or(_T_1100, _T_1078)
node _T_1102 = or(_T_1101, _T_1083)
node _T_1103 = or(_T_1102, _T_1088)
node _T_1104 = or(_T_1103, _T_1093)
node _T_1105 = or(_T_1104, _T_1098)
node _T_1106 = and(_T_1058, _T_1105)
node _T_1107 = or(UInt<1>(0h0), _T_1057)
node _T_1108 = or(_T_1107, _T_1106)
node _T_1109 = and(_T_1047, _T_1108)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_46
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(is_aligned, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1119 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_49
node _T_1123 = eq(io.in.a.bits.mask, mask)
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_50
node _T_1127 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1131 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1135 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1135 :
node _T_1136 = asUInt(reset)
node _T_1137 = eq(_T_1136, UInt<1>(0h0))
when _T_1137 :
node _T_1138 = eq(source_ok_1, UInt<1>(0h0))
when _T_1138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1139 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1140 = asUInt(reset)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = eq(_T_1139, UInt<1>(0h0))
when _T_1142 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1139, UInt<1>(0h1), "") : assert_54
node _T_1143 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1144 = asUInt(reset)
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(_T_1143, UInt<1>(0h0))
when _T_1146 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1143, UInt<1>(0h1), "") : assert_55
node _T_1147 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1148 = asUInt(reset)
node _T_1149 = eq(_T_1148, UInt<1>(0h0))
when _T_1149 :
node _T_1150 = eq(_T_1147, UInt<1>(0h0))
when _T_1150 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1147, UInt<1>(0h1), "") : assert_56
node _T_1151 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_57
node _T_1155 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1155 :
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(source_ok_1, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(sink_ok, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1162 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_60
node _T_1166 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_61
node _T_1170 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_62
node _T_1174 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_63
node _T_1178 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1179 = or(UInt<1>(0h1), _T_1178)
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_64
node _T_1183 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1183 :
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(source_ok_1, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(sink_ok, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1190 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_67
node _T_1194 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_68
node _T_1198 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_69
node _T_1202 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1203 = or(_T_1202, io.in.d.bits.corrupt)
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_70
node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1208 = or(UInt<1>(0h1), _T_1207)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_71
node _T_1212 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(source_ok_1, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1216 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_73
node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_74
node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1225 = or(UInt<1>(0h1), _T_1224)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_75
node _T_1229 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1229 :
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(source_ok_1, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1233 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_77
node _T_1237 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1238 = or(_T_1237, io.in.d.bits.corrupt)
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_78
node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1243 = or(UInt<1>(0h1), _T_1242)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_79
node _T_1247 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1247 :
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(source_ok_1, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1251 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_81
node _T_1255 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_82
node _T_1259 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1260 = or(UInt<1>(0h1), _T_1259)
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1264 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1268 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1269 = asUInt(reset)
node _T_1270 = eq(_T_1269, UInt<1>(0h0))
when _T_1270 :
node _T_1271 = eq(_T_1268, UInt<1>(0h0))
when _T_1271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1268, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1272 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1273 = asUInt(reset)
node _T_1274 = eq(_T_1273, UInt<1>(0h0))
when _T_1274 :
node _T_1275 = eq(_T_1272, UInt<1>(0h0))
when _T_1275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1272, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1276 = eq(a_first, UInt<1>(0h0))
node _T_1277 = and(io.in.a.valid, _T_1276)
when _T_1277 :
node _T_1278 = eq(io.in.a.bits.opcode, opcode)
node _T_1279 = asUInt(reset)
node _T_1280 = eq(_T_1279, UInt<1>(0h0))
when _T_1280 :
node _T_1281 = eq(_T_1278, UInt<1>(0h0))
when _T_1281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1278, UInt<1>(0h1), "") : assert_87
node _T_1282 = eq(io.in.a.bits.param, param)
node _T_1283 = asUInt(reset)
node _T_1284 = eq(_T_1283, UInt<1>(0h0))
when _T_1284 :
node _T_1285 = eq(_T_1282, UInt<1>(0h0))
when _T_1285 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1282, UInt<1>(0h1), "") : assert_88
node _T_1286 = eq(io.in.a.bits.size, size)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_89
node _T_1290 = eq(io.in.a.bits.source, source)
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_90
node _T_1294 = eq(io.in.a.bits.address, address)
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_91
node _T_1298 = and(io.in.a.ready, io.in.a.valid)
node _T_1299 = and(_T_1298, a_first)
when _T_1299 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1300 = eq(d_first, UInt<1>(0h0))
node _T_1301 = and(io.in.d.valid, _T_1300)
when _T_1301 :
node _T_1302 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(_T_1302, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1302, UInt<1>(0h1), "") : assert_92
node _T_1306 = eq(io.in.d.bits.param, param_1)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_93
node _T_1310 = eq(io.in.d.bits.size, size_1)
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_94
node _T_1314 = eq(io.in.d.bits.source, source_1)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_95
node _T_1318 = eq(io.in.d.bits.sink, sink)
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_96
node _T_1322 = eq(io.in.d.bits.denied, denied)
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_97
node _T_1326 = and(io.in.d.ready, io.in.d.valid)
node _T_1327 = and(_T_1326, d_first)
when _T_1327 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1328 = and(io.in.a.valid, a_first_1)
node _T_1329 = and(_T_1328, UInt<1>(0h1))
when _T_1329 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1330 = and(io.in.a.ready, io.in.a.valid)
node _T_1331 = and(_T_1330, a_first_1)
node _T_1332 = and(_T_1331, UInt<1>(0h1))
when _T_1332 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1333 = dshr(inflight, io.in.a.bits.source)
node _T_1334 = bits(_T_1333, 0, 0)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1339 = and(io.in.d.valid, d_first_1)
node _T_1340 = and(_T_1339, UInt<1>(0h1))
node _T_1341 = eq(d_release_ack, UInt<1>(0h0))
node _T_1342 = and(_T_1340, _T_1341)
when _T_1342 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1343 = and(io.in.d.ready, io.in.d.valid)
node _T_1344 = and(_T_1343, d_first_1)
node _T_1345 = and(_T_1344, UInt<1>(0h1))
node _T_1346 = eq(d_release_ack, UInt<1>(0h0))
node _T_1347 = and(_T_1345, _T_1346)
when _T_1347 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1348 = and(io.in.d.valid, d_first_1)
node _T_1349 = and(_T_1348, UInt<1>(0h1))
node _T_1350 = eq(d_release_ack, UInt<1>(0h0))
node _T_1351 = and(_T_1349, _T_1350)
when _T_1351 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1352 = dshr(inflight, io.in.d.bits.source)
node _T_1353 = bits(_T_1352, 0, 0)
node _T_1354 = or(_T_1353, same_cycle_resp)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1358 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1359 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1360 = or(_T_1358, _T_1359)
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_100
node _T_1364 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_101
else :
node _T_1368 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1369 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1370 = or(_T_1368, _T_1369)
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(_T_1370, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1370, UInt<1>(0h1), "") : assert_102
node _T_1374 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1375 = asUInt(reset)
node _T_1376 = eq(_T_1375, UInt<1>(0h0))
when _T_1376 :
node _T_1377 = eq(_T_1374, UInt<1>(0h0))
when _T_1377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1374, UInt<1>(0h1), "") : assert_103
node _T_1378 = and(io.in.d.valid, d_first_1)
node _T_1379 = and(_T_1378, a_first_1)
node _T_1380 = and(_T_1379, io.in.a.valid)
node _T_1381 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1382 = and(_T_1380, _T_1381)
node _T_1383 = eq(d_release_ack, UInt<1>(0h0))
node _T_1384 = and(_T_1382, _T_1383)
when _T_1384 :
node _T_1385 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1386 = or(_T_1385, io.in.a.ready)
node _T_1387 = asUInt(reset)
node _T_1388 = eq(_T_1387, UInt<1>(0h0))
when _T_1388 :
node _T_1389 = eq(_T_1386, UInt<1>(0h0))
when _T_1389 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1386, UInt<1>(0h1), "") : assert_104
node _T_1390 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1391 = orr(a_set_wo_ready)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
node _T_1393 = or(_T_1390, _T_1392)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_40
node _T_1397 = orr(inflight)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
node _T_1399 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1400 = or(_T_1398, _T_1399)
node _T_1401 = lt(watchdog, plusarg_reader.out)
node _T_1402 = or(_T_1400, _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1406 = and(io.in.a.ready, io.in.a.valid)
node _T_1407 = and(io.in.d.ready, io.in.d.valid)
node _T_1408 = or(_T_1406, _T_1407)
when _T_1408 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1409 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1410 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1411 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1412 = and(_T_1410, _T_1411)
node _T_1413 = and(_T_1409, _T_1412)
when _T_1413 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1414 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1415 = and(_T_1414, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1416 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1417 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1418 = and(_T_1416, _T_1417)
node _T_1419 = and(_T_1415, _T_1418)
when _T_1419 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1420 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1421 = bits(_T_1420, 0, 0)
node _T_1422 = eq(_T_1421, UInt<1>(0h0))
node _T_1423 = asUInt(reset)
node _T_1424 = eq(_T_1423, UInt<1>(0h0))
when _T_1424 :
node _T_1425 = eq(_T_1422, UInt<1>(0h0))
when _T_1425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1422, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1426 = and(io.in.d.valid, d_first_2)
node _T_1427 = and(_T_1426, UInt<1>(0h1))
node _T_1428 = and(_T_1427, d_release_ack_1)
when _T_1428 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1429 = and(io.in.d.ready, io.in.d.valid)
node _T_1430 = and(_T_1429, d_first_2)
node _T_1431 = and(_T_1430, UInt<1>(0h1))
node _T_1432 = and(_T_1431, d_release_ack_1)
when _T_1432 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1433 = and(io.in.d.valid, d_first_2)
node _T_1434 = and(_T_1433, UInt<1>(0h1))
node _T_1435 = and(_T_1434, d_release_ack_1)
when _T_1435 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1436 = dshr(inflight_1, io.in.d.bits.source)
node _T_1437 = bits(_T_1436, 0, 0)
node _T_1438 = or(_T_1437, same_cycle_resp_1)
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(_T_1438, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1438, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1442 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(_T_1442, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1442, UInt<1>(0h1), "") : assert_109
else :
node _T_1446 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1447 = asUInt(reset)
node _T_1448 = eq(_T_1447, UInt<1>(0h0))
when _T_1448 :
node _T_1449 = eq(_T_1446, UInt<1>(0h0))
when _T_1449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1446, UInt<1>(0h1), "") : assert_110
node _T_1450 = and(io.in.d.valid, d_first_2)
node _T_1451 = and(_T_1450, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1452 = and(_T_1451, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1453 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1454 = and(_T_1452, _T_1453)
node _T_1455 = and(_T_1454, d_release_ack_1)
node _T_1456 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1457 = and(_T_1455, _T_1456)
when _T_1457 :
node _T_1458 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1459 = or(_T_1458, _WIRE_23.ready)
node _T_1460 = asUInt(reset)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
when _T_1461 :
node _T_1462 = eq(_T_1459, UInt<1>(0h0))
when _T_1462 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1459, UInt<1>(0h1), "") : assert_111
node _T_1463 = orr(c_set_wo_ready)
when _T_1463 :
node _T_1464 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_41
node _T_1468 = orr(inflight_1)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
node _T_1470 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1471 = or(_T_1469, _T_1470)
node _T_1472 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1473 = or(_T_1471, _T_1472)
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(_T_1473, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1473, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1477 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1478 = and(io.in.d.ready, io.in.d.valid)
node _T_1479 = or(_T_1477, _T_1478)
when _T_1479 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_20( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1406 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1406; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1406; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1479 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1479; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1479; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1479; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1332 = _T_1406 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1332 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1332 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1332 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1332 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1332 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1378 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1378 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1347 = _T_1479 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1347 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1347 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1347 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1450 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1450 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1432 = _T_1479 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1432 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1432 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1432 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RVCExpander_8 :
input clock : Clock
input reset : Reset
output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>}
node _io_rvc_T = bits(io.in, 1, 0)
node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3))
connect io.rvc, _io_rvc_T_1
node _io_out_s_opc_T = bits(io.in, 12, 5)
node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T)
node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f))
node _io_out_s_T = bits(io.in, 10, 7)
node _io_out_s_T_1 = bits(io.in, 12, 11)
node _io_out_s_T_2 = bits(io.in, 5, 5)
node _io_out_s_T_3 = bits(io.in, 6, 6)
node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0))
node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1)
node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2)
node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo)
node _io_out_s_T_5 = bits(io.in, 4, 2)
node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5)
node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc)
node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2))
node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0))
node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1)
node _io_out_s_T_8 = bits(io.in, 4, 2)
node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8)
node _io_out_s_T_10 = bits(io.in, 4, 2)
node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10)
node _io_out_s_T_12 = bits(io.in, 31, 27)
wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_0.bits, _io_out_s_T_7
connect io_out_s_0.rd, _io_out_s_T_9
connect io_out_s_0.rs1, UInt<5>(0h2)
connect io_out_s_0.rs2, _io_out_s_T_11
connect io_out_s_0.rs3, _io_out_s_T_12
node _io_out_s_T_13 = bits(io.in, 6, 5)
node _io_out_s_T_14 = bits(io.in, 12, 10)
node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14)
node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0))
node _io_out_s_T_16 = bits(io.in, 9, 7)
node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16)
node _io_out_s_T_18 = bits(io.in, 4, 2)
node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18)
node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7))
node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17)
node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3))
node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2)
node _io_out_s_T_21 = bits(io.in, 4, 2)
node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21)
node _io_out_s_T_23 = bits(io.in, 9, 7)
node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23)
node _io_out_s_T_25 = bits(io.in, 4, 2)
node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25)
node _io_out_s_T_27 = bits(io.in, 31, 27)
wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_1.bits, _io_out_s_T_20
connect io_out_s_1.rd, _io_out_s_T_22
connect io_out_s_1.rs1, _io_out_s_T_24
connect io_out_s_1.rs2, _io_out_s_T_26
connect io_out_s_1.rs3, _io_out_s_T_27
node _io_out_s_T_28 = bits(io.in, 5, 5)
node _io_out_s_T_29 = bits(io.in, 12, 10)
node _io_out_s_T_30 = bits(io.in, 6, 6)
node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0))
node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29)
node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3)
node _io_out_s_T_32 = bits(io.in, 9, 7)
node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32)
node _io_out_s_T_34 = bits(io.in, 4, 2)
node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34)
node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3))
node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33)
node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2))
node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4)
node _io_out_s_T_37 = bits(io.in, 4, 2)
node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37)
node _io_out_s_T_39 = bits(io.in, 9, 7)
node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39)
node _io_out_s_T_41 = bits(io.in, 4, 2)
node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41)
node _io_out_s_T_43 = bits(io.in, 31, 27)
wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_2.bits, _io_out_s_T_36
connect io_out_s_2.rd, _io_out_s_T_38
connect io_out_s_2.rs1, _io_out_s_T_40
connect io_out_s_2.rs2, _io_out_s_T_42
connect io_out_s_2.rs3, _io_out_s_T_43
node _io_out_s_T_44 = bits(io.in, 6, 5)
node _io_out_s_T_45 = bits(io.in, 12, 10)
node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45)
node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0))
node _io_out_s_T_47 = bits(io.in, 9, 7)
node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47)
node _io_out_s_T_49 = bits(io.in, 4, 2)
node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49)
node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3))
node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48)
node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3))
node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5)
node _io_out_s_T_52 = bits(io.in, 4, 2)
node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52)
node _io_out_s_T_54 = bits(io.in, 9, 7)
node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54)
node _io_out_s_T_56 = bits(io.in, 4, 2)
node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56)
node _io_out_s_T_58 = bits(io.in, 31, 27)
wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_3.bits, _io_out_s_T_51
connect io_out_s_3.rd, _io_out_s_T_53
connect io_out_s_3.rs1, _io_out_s_T_55
connect io_out_s_3.rs2, _io_out_s_T_57
connect io_out_s_3.rs3, _io_out_s_T_58
node _io_out_s_T_59 = bits(io.in, 5, 5)
node _io_out_s_T_60 = bits(io.in, 12, 10)
node _io_out_s_T_61 = bits(io.in, 6, 6)
node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0))
node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60)
node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6)
node _io_out_s_T_63 = shr(_io_out_s_T_62, 5)
node _io_out_s_T_64 = bits(io.in, 4, 2)
node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64)
node _io_out_s_T_66 = bits(io.in, 9, 7)
node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66)
node _io_out_s_T_68 = bits(io.in, 5, 5)
node _io_out_s_T_69 = bits(io.in, 12, 10)
node _io_out_s_T_70 = bits(io.in, 6, 6)
node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0))
node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69)
node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7)
node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0)
node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72)
node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f))
node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65)
node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67)
node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8)
node _io_out_s_T_74 = bits(io.in, 4, 2)
node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74)
node _io_out_s_T_76 = bits(io.in, 9, 7)
node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76)
node _io_out_s_T_78 = bits(io.in, 4, 2)
node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78)
node _io_out_s_T_80 = bits(io.in, 31, 27)
wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_4.bits, _io_out_s_T_73
connect io_out_s_4.rd, _io_out_s_T_75
connect io_out_s_4.rs1, _io_out_s_T_77
connect io_out_s_4.rs2, _io_out_s_T_79
connect io_out_s_4.rs3, _io_out_s_T_80
node _io_out_s_T_81 = bits(io.in, 6, 5)
node _io_out_s_T_82 = bits(io.in, 12, 10)
node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82)
node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0))
node _io_out_s_T_84 = shr(_io_out_s_T_83, 5)
node _io_out_s_T_85 = bits(io.in, 4, 2)
node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85)
node _io_out_s_T_87 = bits(io.in, 9, 7)
node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87)
node _io_out_s_T_89 = bits(io.in, 6, 5)
node _io_out_s_T_90 = bits(io.in, 12, 10)
node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90)
node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0))
node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0)
node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92)
node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27))
node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86)
node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88)
node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9)
node _io_out_s_T_94 = bits(io.in, 4, 2)
node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94)
node _io_out_s_T_96 = bits(io.in, 9, 7)
node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96)
node _io_out_s_T_98 = bits(io.in, 4, 2)
node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98)
node _io_out_s_T_100 = bits(io.in, 31, 27)
wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_5.bits, _io_out_s_T_93
connect io_out_s_5.rd, _io_out_s_T_95
connect io_out_s_5.rs1, _io_out_s_T_97
connect io_out_s_5.rs2, _io_out_s_T_99
connect io_out_s_5.rs3, _io_out_s_T_100
node _io_out_s_T_101 = bits(io.in, 5, 5)
node _io_out_s_T_102 = bits(io.in, 12, 10)
node _io_out_s_T_103 = bits(io.in, 6, 6)
node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0))
node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102)
node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10)
node _io_out_s_T_105 = shr(_io_out_s_T_104, 5)
node _io_out_s_T_106 = bits(io.in, 4, 2)
node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106)
node _io_out_s_T_108 = bits(io.in, 9, 7)
node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108)
node _io_out_s_T_110 = bits(io.in, 5, 5)
node _io_out_s_T_111 = bits(io.in, 12, 10)
node _io_out_s_T_112 = bits(io.in, 6, 6)
node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0))
node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111)
node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11)
node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0)
node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114)
node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23))
node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107)
node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109)
node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12)
node _io_out_s_T_116 = bits(io.in, 4, 2)
node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116)
node _io_out_s_T_118 = bits(io.in, 9, 7)
node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118)
node _io_out_s_T_120 = bits(io.in, 4, 2)
node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120)
node _io_out_s_T_122 = bits(io.in, 31, 27)
wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_6.bits, _io_out_s_T_115
connect io_out_s_6.rd, _io_out_s_T_117
connect io_out_s_6.rs1, _io_out_s_T_119
connect io_out_s_6.rs2, _io_out_s_T_121
connect io_out_s_6.rs3, _io_out_s_T_122
node _io_out_s_T_123 = bits(io.in, 6, 5)
node _io_out_s_T_124 = bits(io.in, 12, 10)
node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124)
node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0))
node _io_out_s_T_126 = shr(_io_out_s_T_125, 5)
node _io_out_s_T_127 = bits(io.in, 4, 2)
node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127)
node _io_out_s_T_129 = bits(io.in, 9, 7)
node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129)
node _io_out_s_T_131 = bits(io.in, 6, 5)
node _io_out_s_T_132 = bits(io.in, 12, 10)
node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132)
node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0))
node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0)
node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134)
node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23))
node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128)
node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130)
node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13)
node _io_out_s_T_136 = bits(io.in, 4, 2)
node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136)
node _io_out_s_T_138 = bits(io.in, 9, 7)
node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138)
node _io_out_s_T_140 = bits(io.in, 4, 2)
node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140)
node _io_out_s_T_142 = bits(io.in, 31, 27)
wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_7.bits, _io_out_s_T_135
connect io_out_s_7.rd, _io_out_s_T_137
connect io_out_s_7.rs1, _io_out_s_T_139
connect io_out_s_7.rs2, _io_out_s_T_141
connect io_out_s_7.rs3, _io_out_s_T_142
node _io_out_s_T_143 = bits(io.in, 12, 12)
node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_145 = bits(io.in, 6, 2)
node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145)
node _io_out_s_T_147 = bits(io.in, 11, 7)
node _io_out_s_T_148 = bits(io.in, 11, 7)
node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13))
node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147)
node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0))
node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14)
node _io_out_s_T_150 = bits(io.in, 11, 7)
node _io_out_s_T_151 = bits(io.in, 11, 7)
node _io_out_s_T_152 = bits(io.in, 4, 2)
node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152)
node _io_out_s_T_154 = bits(io.in, 31, 27)
wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_8.bits, _io_out_s_T_149
connect io_out_s_8.rd, _io_out_s_T_150
connect io_out_s_8.rs1, _io_out_s_T_151
connect io_out_s_8.rs2, _io_out_s_T_153
connect io_out_s_8.rs3, _io_out_s_T_154
node _io_out_s_opc_T_2 = bits(io.in, 11, 7)
node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2)
node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f))
node _io_out_s_T_155 = bits(io.in, 12, 12)
node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_157 = bits(io.in, 6, 2)
node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157)
node _io_out_s_T_159 = bits(io.in, 11, 7)
node _io_out_s_T_160 = bits(io.in, 11, 7)
node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1)
node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159)
node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0))
node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15)
node _io_out_s_T_162 = bits(io.in, 11, 7)
node _io_out_s_T_163 = bits(io.in, 11, 7)
node _io_out_s_T_164 = bits(io.in, 4, 2)
node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164)
node _io_out_s_T_166 = bits(io.in, 31, 27)
wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_9.bits, _io_out_s_T_161
connect io_out_s_9.rd, _io_out_s_T_162
connect io_out_s_9.rs1, _io_out_s_T_163
connect io_out_s_9.rs2, _io_out_s_T_165
connect io_out_s_9.rs3, _io_out_s_T_166
node _io_out_s_T_167 = bits(io.in, 12, 12)
node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_169 = bits(io.in, 6, 2)
node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169)
node _io_out_s_T_171 = bits(io.in, 11, 7)
node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13))
node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0))
node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0))
node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16)
node _io_out_s_T_173 = bits(io.in, 11, 7)
node _io_out_s_T_174 = bits(io.in, 4, 2)
node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174)
node _io_out_s_T_176 = bits(io.in, 31, 27)
wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_10.bits, _io_out_s_T_172
connect io_out_s_10.rd, _io_out_s_T_173
connect io_out_s_10.rs1, UInt<5>(0h0)
connect io_out_s_10.rs2, _io_out_s_T_175
connect io_out_s_10.rs3, _io_out_s_T_176
node _io_out_s_opc_T_4 = bits(io.in, 12, 12)
node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_opc_T_6 = bits(io.in, 6, 2)
node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6)
node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7)
node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f))
node _io_out_s_me_T = bits(io.in, 12, 12)
node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0))
node _io_out_s_me_T_2 = bits(io.in, 6, 2)
node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2)
node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0))
node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12)
node _io_out_s_me_T_5 = bits(io.in, 11, 7)
node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5)
node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2)
node _io_out_s_me_T_7 = bits(io.in, 11, 7)
node _io_out_s_me_T_8 = bits(io.in, 11, 7)
node _io_out_s_me_T_9 = bits(io.in, 4, 2)
node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9)
node _io_out_s_me_T_11 = bits(io.in, 31, 27)
wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_me.bits, _io_out_s_me_T_6
connect io_out_s_me.rd, _io_out_s_me_T_7
connect io_out_s_me.rs1, _io_out_s_me_T_8
connect io_out_s_me.rs2, _io_out_s_me_T_10
connect io_out_s_me.rs3, _io_out_s_me_T_11
node _io_out_s_T_177 = bits(io.in, 11, 7)
node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0))
node _io_out_s_T_179 = bits(io.in, 11, 7)
node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2))
node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180)
node _io_out_s_opc_T_9 = bits(io.in, 12, 12)
node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_opc_T_11 = bits(io.in, 6, 2)
node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11)
node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12)
node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f))
node _io_out_s_T_182 = bits(io.in, 12, 12)
node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0))
node _io_out_s_T_184 = bits(io.in, 4, 3)
node _io_out_s_T_185 = bits(io.in, 5, 5)
node _io_out_s_T_186 = bits(io.in, 2, 2)
node _io_out_s_T_187 = bits(io.in, 6, 6)
node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187)
node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0))
node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184)
node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185)
node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17)
node _io_out_s_T_189 = bits(io.in, 11, 7)
node _io_out_s_T_190 = bits(io.in, 11, 7)
node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3)
node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189)
node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0))
node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18)
node _io_out_s_T_192 = bits(io.in, 11, 7)
node _io_out_s_T_193 = bits(io.in, 11, 7)
node _io_out_s_T_194 = bits(io.in, 4, 2)
node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194)
node _io_out_s_T_196 = bits(io.in, 31, 27)
wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_res.bits, _io_out_s_T_191
connect io_out_s_res.rd, _io_out_s_T_192
connect io_out_s_res.rs1, _io_out_s_T_193
connect io_out_s_res.rs2, _io_out_s_T_195
connect io_out_s_res.rs3, _io_out_s_T_196
node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me)
node _io_out_s_T_197 = bits(io.in, 12, 12)
node _io_out_s_T_198 = bits(io.in, 6, 2)
node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198)
node _io_out_s_T_200 = bits(io.in, 9, 7)
node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200)
node _io_out_s_T_202 = bits(io.in, 9, 7)
node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202)
node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13))
node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201)
node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5))
node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19)
node _io_out_s_T_205 = bits(io.in, 12, 12)
node _io_out_s_T_206 = bits(io.in, 6, 2)
node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206)
node _io_out_s_T_208 = bits(io.in, 9, 7)
node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208)
node _io_out_s_T_210 = bits(io.in, 9, 7)
node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210)
node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13))
node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209)
node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5))
node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20)
node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000))
node _io_out_s_T_214 = bits(io.in, 12, 12)
node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0))
node _io_out_s_T_216 = bits(io.in, 6, 2)
node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216)
node _io_out_s_T_218 = bits(io.in, 9, 7)
node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218)
node _io_out_s_T_220 = bits(io.in, 9, 7)
node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220)
node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13))
node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219)
node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7))
node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21)
node _io_out_s_funct_T = bits(io.in, 12, 12)
node _io_out_s_funct_T_1 = bits(io.in, 6, 5)
node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1)
node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1))
node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0))
node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2))
node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4)
node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3))
node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6)
node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4))
node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8)
node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5))
node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10)
node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6))
node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12)
node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7))
node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14)
node _io_out_s_sub_T = bits(io.in, 6, 5)
node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0))
node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0))
node _io_out_s_opc_T_14 = bits(io.in, 12, 12)
node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33))
node _io_out_s_T_223 = bits(io.in, 4, 2)
node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223)
node _io_out_s_T_225 = bits(io.in, 9, 7)
node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225)
node _io_out_s_T_227 = bits(io.in, 9, 7)
node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227)
node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4)
node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226)
node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct)
node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22)
node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub)
node _io_out_s_T_231 = bits(io.in, 11, 10)
node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1))
node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204)
node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2))
node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233)
node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3))
node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235)
node _io_out_s_T_238 = bits(io.in, 9, 7)
node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238)
node _io_out_s_T_240 = bits(io.in, 9, 7)
node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240)
node _io_out_s_T_242 = bits(io.in, 4, 2)
node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242)
node _io_out_s_T_244 = bits(io.in, 31, 27)
wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_12.bits, _io_out_s_T_237
connect io_out_s_12.rd, _io_out_s_T_239
connect io_out_s_12.rs1, _io_out_s_T_241
connect io_out_s_12.rs2, _io_out_s_T_243
connect io_out_s_12.rs3, _io_out_s_T_244
node _io_out_s_T_245 = bits(io.in, 12, 12)
node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_247 = bits(io.in, 8, 8)
node _io_out_s_T_248 = bits(io.in, 10, 9)
node _io_out_s_T_249 = bits(io.in, 6, 6)
node _io_out_s_T_250 = bits(io.in, 7, 7)
node _io_out_s_T_251 = bits(io.in, 2, 2)
node _io_out_s_T_252 = bits(io.in, 11, 11)
node _io_out_s_T_253 = bits(io.in, 5, 3)
node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0))
node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252)
node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo)
node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250)
node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247)
node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248)
node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo)
node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23)
node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20)
node _io_out_s_T_256 = bits(io.in, 12, 12)
node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_258 = bits(io.in, 8, 8)
node _io_out_s_T_259 = bits(io.in, 10, 9)
node _io_out_s_T_260 = bits(io.in, 6, 6)
node _io_out_s_T_261 = bits(io.in, 7, 7)
node _io_out_s_T_262 = bits(io.in, 2, 2)
node _io_out_s_T_263 = bits(io.in, 11, 11)
node _io_out_s_T_264 = bits(io.in, 5, 3)
node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0))
node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263)
node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1)
node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261)
node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258)
node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259)
node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1)
node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24)
node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1)
node _io_out_s_T_267 = bits(io.in, 12, 12)
node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_269 = bits(io.in, 8, 8)
node _io_out_s_T_270 = bits(io.in, 10, 9)
node _io_out_s_T_271 = bits(io.in, 6, 6)
node _io_out_s_T_272 = bits(io.in, 7, 7)
node _io_out_s_T_273 = bits(io.in, 2, 2)
node _io_out_s_T_274 = bits(io.in, 11, 11)
node _io_out_s_T_275 = bits(io.in, 5, 3)
node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0))
node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274)
node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2)
node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272)
node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269)
node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270)
node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2)
node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25)
node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11)
node _io_out_s_T_278 = bits(io.in, 12, 12)
node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0))
node _io_out_s_T_280 = bits(io.in, 8, 8)
node _io_out_s_T_281 = bits(io.in, 10, 9)
node _io_out_s_T_282 = bits(io.in, 6, 6)
node _io_out_s_T_283 = bits(io.in, 7, 7)
node _io_out_s_T_284 = bits(io.in, 2, 2)
node _io_out_s_T_285 = bits(io.in, 11, 11)
node _io_out_s_T_286 = bits(io.in, 5, 3)
node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0))
node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285)
node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3)
node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283)
node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280)
node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281)
node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3)
node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26)
node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12)
node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0))
node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f))
node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266)
node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277)
node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27)
node _io_out_s_T_290 = bits(io.in, 9, 7)
node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290)
node _io_out_s_T_292 = bits(io.in, 4, 2)
node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292)
node _io_out_s_T_294 = bits(io.in, 31, 27)
wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_13.bits, _io_out_s_T_289
connect io_out_s_13.rd, UInt<5>(0h0)
connect io_out_s_13.rs1, _io_out_s_T_291
connect io_out_s_13.rs2, _io_out_s_T_293
connect io_out_s_13.rs3, _io_out_s_T_294
node _io_out_s_T_295 = bits(io.in, 12, 12)
node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_297 = bits(io.in, 6, 5)
node _io_out_s_T_298 = bits(io.in, 2, 2)
node _io_out_s_T_299 = bits(io.in, 11, 10)
node _io_out_s_T_300 = bits(io.in, 4, 3)
node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300)
node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0))
node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297)
node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298)
node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28)
node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12)
node _io_out_s_T_303 = bits(io.in, 12, 12)
node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_305 = bits(io.in, 6, 5)
node _io_out_s_T_306 = bits(io.in, 2, 2)
node _io_out_s_T_307 = bits(io.in, 11, 10)
node _io_out_s_T_308 = bits(io.in, 4, 3)
node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308)
node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0))
node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305)
node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306)
node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29)
node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5)
node _io_out_s_T_311 = bits(io.in, 9, 7)
node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311)
node _io_out_s_T_313 = bits(io.in, 12, 12)
node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_315 = bits(io.in, 6, 5)
node _io_out_s_T_316 = bits(io.in, 2, 2)
node _io_out_s_T_317 = bits(io.in, 11, 10)
node _io_out_s_T_318 = bits(io.in, 4, 3)
node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318)
node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0))
node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315)
node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316)
node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30)
node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1)
node _io_out_s_T_321 = bits(io.in, 12, 12)
node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_323 = bits(io.in, 6, 5)
node _io_out_s_T_324 = bits(io.in, 2, 2)
node _io_out_s_T_325 = bits(io.in, 11, 10)
node _io_out_s_T_326 = bits(io.in, 4, 3)
node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326)
node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0))
node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323)
node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324)
node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31)
node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11)
node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63))
node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320)
node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4)
node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312)
node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310)
node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4)
node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32)
node _io_out_s_T_330 = bits(io.in, 9, 7)
node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330)
node _io_out_s_T_332 = bits(io.in, 9, 7)
node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332)
node _io_out_s_T_334 = bits(io.in, 31, 27)
wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_14.bits, _io_out_s_T_329
connect io_out_s_14.rd, _io_out_s_T_331
connect io_out_s_14.rs1, _io_out_s_T_333
connect io_out_s_14.rs2, UInt<5>(0h0)
connect io_out_s_14.rs3, _io_out_s_T_334
node _io_out_s_T_335 = bits(io.in, 12, 12)
node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_337 = bits(io.in, 6, 5)
node _io_out_s_T_338 = bits(io.in, 2, 2)
node _io_out_s_T_339 = bits(io.in, 11, 10)
node _io_out_s_T_340 = bits(io.in, 4, 3)
node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340)
node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0))
node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337)
node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338)
node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33)
node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12)
node _io_out_s_T_343 = bits(io.in, 12, 12)
node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_345 = bits(io.in, 6, 5)
node _io_out_s_T_346 = bits(io.in, 2, 2)
node _io_out_s_T_347 = bits(io.in, 11, 10)
node _io_out_s_T_348 = bits(io.in, 4, 3)
node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348)
node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0))
node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345)
node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346)
node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34)
node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5)
node _io_out_s_T_351 = bits(io.in, 9, 7)
node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351)
node _io_out_s_T_353 = bits(io.in, 12, 12)
node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_355 = bits(io.in, 6, 5)
node _io_out_s_T_356 = bits(io.in, 2, 2)
node _io_out_s_T_357 = bits(io.in, 11, 10)
node _io_out_s_T_358 = bits(io.in, 4, 3)
node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358)
node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0))
node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355)
node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356)
node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35)
node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1)
node _io_out_s_T_361 = bits(io.in, 12, 12)
node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0))
node _io_out_s_T_363 = bits(io.in, 6, 5)
node _io_out_s_T_364 = bits(io.in, 2, 2)
node _io_out_s_T_365 = bits(io.in, 11, 10)
node _io_out_s_T_366 = bits(io.in, 4, 3)
node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366)
node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0))
node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363)
node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364)
node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36)
node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11)
node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63))
node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360)
node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5)
node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352)
node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350)
node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5)
node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37)
node _io_out_s_T_370 = bits(io.in, 9, 7)
node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370)
node _io_out_s_T_372 = bits(io.in, 31, 27)
wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_15.bits, _io_out_s_T_369
connect io_out_s_15.rd, UInt<5>(0h0)
connect io_out_s_15.rs1, _io_out_s_T_371
connect io_out_s_15.rs2, UInt<5>(0h0)
connect io_out_s_15.rs3, _io_out_s_T_372
node _io_out_s_load_opc_T = bits(io.in, 11, 7)
node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T)
node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f))
node _io_out_s_T_373 = bits(io.in, 12, 12)
node _io_out_s_T_374 = bits(io.in, 6, 2)
node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374)
node _io_out_s_T_376 = bits(io.in, 11, 7)
node _io_out_s_T_377 = bits(io.in, 11, 7)
node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13))
node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376)
node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1))
node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38)
node _io_out_s_T_379 = bits(io.in, 11, 7)
node _io_out_s_T_380 = bits(io.in, 11, 7)
node _io_out_s_T_381 = bits(io.in, 6, 2)
node _io_out_s_T_382 = bits(io.in, 31, 27)
wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_16.bits, _io_out_s_T_378
connect io_out_s_16.rd, _io_out_s_T_379
connect io_out_s_16.rs1, _io_out_s_T_380
connect io_out_s_16.rs2, _io_out_s_T_381
connect io_out_s_16.rs3, _io_out_s_T_382
node _io_out_s_T_383 = bits(io.in, 4, 2)
node _io_out_s_T_384 = bits(io.in, 12, 12)
node _io_out_s_T_385 = bits(io.in, 6, 5)
node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0))
node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384)
node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39)
node _io_out_s_T_387 = bits(io.in, 11, 7)
node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7))
node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2))
node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3))
node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40)
node _io_out_s_T_389 = bits(io.in, 11, 7)
node _io_out_s_T_390 = bits(io.in, 6, 2)
node _io_out_s_T_391 = bits(io.in, 31, 27)
wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_17.bits, _io_out_s_T_388
connect io_out_s_17.rd, _io_out_s_T_389
connect io_out_s_17.rs1, UInt<5>(0h2)
connect io_out_s_17.rs2, _io_out_s_T_390
connect io_out_s_17.rs3, _io_out_s_T_391
node _io_out_s_T_392 = bits(io.in, 3, 2)
node _io_out_s_T_393 = bits(io.in, 12, 12)
node _io_out_s_T_394 = bits(io.in, 6, 4)
node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0))
node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393)
node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41)
node _io_out_s_T_396 = bits(io.in, 11, 7)
node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc)
node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2))
node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2))
node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42)
node _io_out_s_T_398 = bits(io.in, 11, 7)
node _io_out_s_T_399 = bits(io.in, 6, 2)
node _io_out_s_T_400 = bits(io.in, 31, 27)
wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_18.bits, _io_out_s_T_397
connect io_out_s_18.rd, _io_out_s_T_398
connect io_out_s_18.rs1, UInt<5>(0h2)
connect io_out_s_18.rs2, _io_out_s_T_399
connect io_out_s_18.rs3, _io_out_s_T_400
node _io_out_s_T_401 = bits(io.in, 4, 2)
node _io_out_s_T_402 = bits(io.in, 12, 12)
node _io_out_s_T_403 = bits(io.in, 6, 5)
node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0))
node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402)
node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43)
node _io_out_s_T_405 = bits(io.in, 11, 7)
node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc)
node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2))
node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3))
node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44)
node _io_out_s_T_407 = bits(io.in, 11, 7)
node _io_out_s_T_408 = bits(io.in, 6, 2)
node _io_out_s_T_409 = bits(io.in, 31, 27)
wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_19.bits, _io_out_s_T_406
connect io_out_s_19.rd, _io_out_s_T_407
connect io_out_s_19.rs1, UInt<5>(0h2)
connect io_out_s_19.rs2, _io_out_s_T_408
connect io_out_s_19.rs3, _io_out_s_T_409
node _io_out_s_mv_T = bits(io.in, 6, 2)
node _io_out_s_mv_T_1 = bits(io.in, 11, 7)
node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33))
node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0))
node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0))
node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo)
node _io_out_s_mv_T_3 = bits(io.in, 11, 7)
node _io_out_s_mv_T_4 = bits(io.in, 6, 2)
node _io_out_s_mv_T_5 = bits(io.in, 31, 27)
wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_mv.bits, _io_out_s_mv_T_2
connect io_out_s_mv.rd, _io_out_s_mv_T_3
connect io_out_s_mv.rs1, UInt<5>(0h0)
connect io_out_s_mv.rs2, _io_out_s_mv_T_4
connect io_out_s_mv.rs3, _io_out_s_mv_T_5
node _io_out_s_add_T = bits(io.in, 6, 2)
node _io_out_s_add_T_1 = bits(io.in, 11, 7)
node _io_out_s_add_T_2 = bits(io.in, 11, 7)
node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33))
node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1)
node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0))
node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo)
node _io_out_s_add_T_4 = bits(io.in, 11, 7)
node _io_out_s_add_T_5 = bits(io.in, 11, 7)
node _io_out_s_add_T_6 = bits(io.in, 6, 2)
node _io_out_s_add_T_7 = bits(io.in, 31, 27)
wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_add.bits, _io_out_s_add_T_3
connect io_out_s_add.rd, _io_out_s_add_T_4
connect io_out_s_add.rs1, _io_out_s_add_T_5
connect io_out_s_add.rs2, _io_out_s_add_T_6
connect io_out_s_add.rs3, _io_out_s_add_T_7
node _io_out_s_jr_T = bits(io.in, 6, 2)
node _io_out_s_jr_T_1 = bits(io.in, 11, 7)
node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67))
node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1)
node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0))
node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo)
node _io_out_s_reserved_T = shr(io_out_s_jr, 7)
node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f))
node _io_out_s_jr_reserved_T = bits(io.in, 11, 7)
node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T)
node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved)
node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7)
node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2)
node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27)
wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2
connect io_out_s_jr_reserved.rd, UInt<5>(0h0)
connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3
connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4
connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5
node _io_out_s_jr_mv_T = bits(io.in, 6, 2)
node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T)
node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved)
node _io_out_s_jalr_T = bits(io.in, 6, 2)
node _io_out_s_jalr_T_1 = bits(io.in, 11, 7)
node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67))
node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1)
node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0))
node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo)
node _io_out_s_ebreak_T = shr(io_out_s_jr, 7)
node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73))
node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000))
node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7)
node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T)
node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak)
node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7)
node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2)
node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27)
wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2
connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1)
connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3
connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4
connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5
node _io_out_s_jalr_add_T = bits(io.in, 6, 2)
node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T)
node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak)
node _io_out_s_T_410 = bits(io.in, 12, 12)
node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv)
node _io_out_s_T_411 = bits(io.in, 9, 7)
node _io_out_s_T_412 = bits(io.in, 12, 10)
node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412)
node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0))
node _io_out_s_T_414 = shr(_io_out_s_T_413, 5)
node _io_out_s_T_415 = bits(io.in, 6, 2)
node _io_out_s_T_416 = bits(io.in, 9, 7)
node _io_out_s_T_417 = bits(io.in, 12, 10)
node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417)
node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0))
node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0)
node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419)
node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27))
node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415)
node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2))
node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45)
node _io_out_s_T_421 = bits(io.in, 11, 7)
node _io_out_s_T_422 = bits(io.in, 6, 2)
node _io_out_s_T_423 = bits(io.in, 31, 27)
wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_21.bits, _io_out_s_T_420
connect io_out_s_21.rd, _io_out_s_T_421
connect io_out_s_21.rs1, UInt<5>(0h2)
connect io_out_s_21.rs2, _io_out_s_T_422
connect io_out_s_21.rs3, _io_out_s_T_423
node _io_out_s_T_424 = bits(io.in, 8, 7)
node _io_out_s_T_425 = bits(io.in, 12, 9)
node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425)
node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0))
node _io_out_s_T_427 = shr(_io_out_s_T_426, 5)
node _io_out_s_T_428 = bits(io.in, 6, 2)
node _io_out_s_T_429 = bits(io.in, 8, 7)
node _io_out_s_T_430 = bits(io.in, 12, 9)
node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430)
node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0))
node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0)
node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432)
node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23))
node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428)
node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2))
node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46)
node _io_out_s_T_434 = bits(io.in, 11, 7)
node _io_out_s_T_435 = bits(io.in, 6, 2)
node _io_out_s_T_436 = bits(io.in, 31, 27)
wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_22.bits, _io_out_s_T_433
connect io_out_s_22.rd, _io_out_s_T_434
connect io_out_s_22.rs1, UInt<5>(0h2)
connect io_out_s_22.rs2, _io_out_s_T_435
connect io_out_s_22.rs3, _io_out_s_T_436
node _io_out_s_T_437 = bits(io.in, 9, 7)
node _io_out_s_T_438 = bits(io.in, 12, 10)
node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438)
node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0))
node _io_out_s_T_440 = shr(_io_out_s_T_439, 5)
node _io_out_s_T_441 = bits(io.in, 6, 2)
node _io_out_s_T_442 = bits(io.in, 9, 7)
node _io_out_s_T_443 = bits(io.in, 12, 10)
node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443)
node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0))
node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0)
node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445)
node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23))
node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441)
node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2))
node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47)
node _io_out_s_T_447 = bits(io.in, 11, 7)
node _io_out_s_T_448 = bits(io.in, 6, 2)
node _io_out_s_T_449 = bits(io.in, 31, 27)
wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_23.bits, _io_out_s_T_446
connect io_out_s_23.rd, _io_out_s_T_447
connect io_out_s_23.rs1, UInt<5>(0h2)
connect io_out_s_23.rs2, _io_out_s_T_448
connect io_out_s_23.rs3, _io_out_s_T_449
node _io_out_s_T_450 = bits(io.in, 11, 7)
node _io_out_s_T_451 = bits(io.in, 19, 15)
node _io_out_s_T_452 = bits(io.in, 24, 20)
node _io_out_s_T_453 = bits(io.in, 31, 27)
wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_24.bits, io.in
connect io_out_s_24.rd, _io_out_s_T_450
connect io_out_s_24.rs1, _io_out_s_T_451
connect io_out_s_24.rs2, _io_out_s_T_452
connect io_out_s_24.rs3, _io_out_s_T_453
node _io_out_s_T_454 = bits(io.in, 11, 7)
node _io_out_s_T_455 = bits(io.in, 19, 15)
node _io_out_s_T_456 = bits(io.in, 24, 20)
node _io_out_s_T_457 = bits(io.in, 31, 27)
wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_25.bits, io.in
connect io_out_s_25.rd, _io_out_s_T_454
connect io_out_s_25.rs1, _io_out_s_T_455
connect io_out_s_25.rs2, _io_out_s_T_456
connect io_out_s_25.rs3, _io_out_s_T_457
node _io_out_s_T_458 = bits(io.in, 11, 7)
node _io_out_s_T_459 = bits(io.in, 19, 15)
node _io_out_s_T_460 = bits(io.in, 24, 20)
node _io_out_s_T_461 = bits(io.in, 31, 27)
wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_26.bits, io.in
connect io_out_s_26.rd, _io_out_s_T_458
connect io_out_s_26.rs1, _io_out_s_T_459
connect io_out_s_26.rs2, _io_out_s_T_460
connect io_out_s_26.rs3, _io_out_s_T_461
node _io_out_s_T_462 = bits(io.in, 11, 7)
node _io_out_s_T_463 = bits(io.in, 19, 15)
node _io_out_s_T_464 = bits(io.in, 24, 20)
node _io_out_s_T_465 = bits(io.in, 31, 27)
wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_27.bits, io.in
connect io_out_s_27.rd, _io_out_s_T_462
connect io_out_s_27.rs1, _io_out_s_T_463
connect io_out_s_27.rs2, _io_out_s_T_464
connect io_out_s_27.rs3, _io_out_s_T_465
node _io_out_s_T_466 = bits(io.in, 11, 7)
node _io_out_s_T_467 = bits(io.in, 19, 15)
node _io_out_s_T_468 = bits(io.in, 24, 20)
node _io_out_s_T_469 = bits(io.in, 31, 27)
wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_28.bits, io.in
connect io_out_s_28.rd, _io_out_s_T_466
connect io_out_s_28.rs1, _io_out_s_T_467
connect io_out_s_28.rs2, _io_out_s_T_468
connect io_out_s_28.rs3, _io_out_s_T_469
node _io_out_s_T_470 = bits(io.in, 11, 7)
node _io_out_s_T_471 = bits(io.in, 19, 15)
node _io_out_s_T_472 = bits(io.in, 24, 20)
node _io_out_s_T_473 = bits(io.in, 31, 27)
wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_29.bits, io.in
connect io_out_s_29.rd, _io_out_s_T_470
connect io_out_s_29.rs1, _io_out_s_T_471
connect io_out_s_29.rs2, _io_out_s_T_472
connect io_out_s_29.rs3, _io_out_s_T_473
node _io_out_s_T_474 = bits(io.in, 11, 7)
node _io_out_s_T_475 = bits(io.in, 19, 15)
node _io_out_s_T_476 = bits(io.in, 24, 20)
node _io_out_s_T_477 = bits(io.in, 31, 27)
wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_30.bits, io.in
connect io_out_s_30.rd, _io_out_s_T_474
connect io_out_s_30.rs1, _io_out_s_T_475
connect io_out_s_30.rs2, _io_out_s_T_476
connect io_out_s_30.rs3, _io_out_s_T_477
node _io_out_s_T_478 = bits(io.in, 11, 7)
node _io_out_s_T_479 = bits(io.in, 19, 15)
node _io_out_s_T_480 = bits(io.in, 24, 20)
node _io_out_s_T_481 = bits(io.in, 31, 27)
wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}
connect io_out_s_31.bits, io.in
connect io_out_s_31.rd, _io_out_s_T_478
connect io_out_s_31.rs1, _io_out_s_T_479
connect io_out_s_31.rs2, _io_out_s_T_480
connect io_out_s_31.rs3, _io_out_s_T_481
node _io_out_T = bits(io.in, 1, 0)
node _io_out_T_1 = bits(io.in, 15, 13)
node _io_out_T_2 = cat(_io_out_T, _io_out_T_1)
node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1))
node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0)
node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2))
node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4)
node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3))
node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6)
node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4))
node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8)
node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5))
node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10)
node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6))
node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12)
node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7))
node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14)
node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8))
node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16)
node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9))
node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18)
node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha))
node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20)
node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb))
node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22)
node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc))
node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24)
node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd))
node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26)
node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he))
node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28)
node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf))
node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30)
node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10))
node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32)
node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11))
node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34)
node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12))
node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36)
node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13))
node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38)
node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14))
node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40)
node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15))
node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42)
node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16))
node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44)
node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17))
node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46)
node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18))
node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48)
node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19))
node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50)
node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a))
node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52)
node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b))
node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54)
node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c))
node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56)
node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d))
node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58)
node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e))
node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60)
node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f))
node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62)
connect io.out, _io_out_T_64
node _io_ill_s_T = bits(io.in, 12, 2)
node _io_ill_s_T_1 = orr(_io_ill_s_T)
node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0))
node _io_ill_s_T_2 = bits(io.in, 11, 7)
node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0))
node _io_ill_s_T_3 = bits(io.in, 12, 12)
node _io_ill_s_T_4 = bits(io.in, 6, 2)
node _io_ill_s_T_5 = orr(_io_ill_s_T_4)
node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5)
node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0))
node _io_ill_s_T_7 = bits(io.in, 12, 10)
node _io_ill_s_T_8 = andr(_io_ill_s_T_7)
node _io_ill_s_T_9 = bits(io.in, 6, 6)
node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1))
node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10)
node _io_ill_s_T_11 = bits(io.in, 11, 7)
node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0))
node _io_ill_s_T_12 = bits(io.in, 11, 7)
node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0))
node _io_ill_s_T_13 = bits(io.in, 12, 2)
node _io_ill_s_T_14 = orr(_io_ill_s_T_13)
node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0))
node _io_ill_T = bits(io.in, 1, 0)
node _io_ill_T_1 = bits(io.in, 15, 13)
node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1)
node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1))
node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0)
node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2))
node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4)
node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3))
node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6)
node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4))
node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8)
node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5))
node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10)
node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6))
node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12)
node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7))
node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14)
node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8))
node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16)
node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9))
node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18)
node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha))
node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20)
node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb))
node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22)
node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc))
node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24)
node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd))
node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26)
node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he))
node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28)
node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf))
node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30)
node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10))
node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32)
node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11))
node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34)
node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12))
node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36)
node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13))
node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38)
node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14))
node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40)
node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15))
node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42)
node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16))
node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44)
node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17))
node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46)
node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18))
node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48)
node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19))
node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50)
node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a))
node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52)
node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b))
node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54)
node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c))
node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56)
node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d))
node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58)
node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e))
node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60)
node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f))
node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62)
connect io.ill, _io_ill_T_64 | module RVCExpander_8( // @[RVC.scala:190:7]
input clock, // @[RVC.scala:190:7]
input reset, // @[RVC.scala:190:7]
input [31:0] io_in, // @[RVC.scala:191:14]
output [31:0] io_out_bits, // @[RVC.scala:191:14]
output io_rvc // @[RVC.scala:191:14]
);
wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7]
wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19]
wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19]
wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19]
wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21]
wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86]
wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86]
wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86]
wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7]
wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76]
wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76]
wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76]
wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76]
wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76]
wire _io_rvc_T_1; // @[RVC.scala:199:26]
wire _io_ill_T_64; // @[package.scala:39:76]
wire [31:0] io_out_bits_0; // @[RVC.scala:190:7]
wire [4:0] io_out_rd; // @[RVC.scala:190:7]
wire [4:0] io_out_rs1; // @[RVC.scala:190:7]
wire [4:0] io_out_rs2; // @[RVC.scala:190:7]
wire [4:0] io_out_rs3; // @[RVC.scala:190:7]
wire io_rvc_0; // @[RVC.scala:190:7]
wire io_ill; // @[RVC.scala:190:7]
wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20]
wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20]
wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20]
assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}]
assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26]
wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7]
wire _io_out_s_opc_T_1 = |_io_out_s_opc_T; // @[RVC.scala:53:{22,29}]
wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}]
wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7]
wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7]
wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7]
wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7]
wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7]
wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7]
wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7]
wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7]
wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7]
wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7]
wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7]
wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7]
wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7]
wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7]
wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7]
wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7]
wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7]
wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7]
wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7]
wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7]
wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7]
wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}]
wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}]
wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}]
wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24]
wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7]
wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7]
wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7]
wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15]
wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86]
wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15]
wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15]
wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86]
wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86]
wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7]
wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19]
assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15]
wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7]
wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7]
wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7]
wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7]
wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7]
wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7]
wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7]
wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7]
wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7]
wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7]
wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7]
wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7]
wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7]
wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7]
wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7]
wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7]
wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7]
wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18]
wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7]
wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7]
wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7]
wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7]
wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7]
wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23]
wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23]
wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23]
wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23]
wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86]
wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86]
wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86]
wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19]
assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23]
wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}]
wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}]
wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18]
wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22]
wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22]
wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86]
wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22]
wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86]
wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86]
wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86]
wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19]
assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22]
wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18]
wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22]
wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22]
wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22]
wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22]
wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86]
wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86]
wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86]
wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19]
assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22]
wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}]
wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}]
wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18]
wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32]
wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86]
wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}]
wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}]
wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18]
wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65]
wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86]
wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25]
wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}]
wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25]
wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25]
wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86]
wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86]
wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86]
wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19]
assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25]
wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18]
wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30]
wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86]
wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18]
wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63]
wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}]
wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23]
wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}]
wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23]
wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23]
wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86]
wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86]
wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86]
wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19]
assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23]
wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}]
wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}]
wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18]
wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29]
wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86]
wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}]
wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}]
wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18]
wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62]
wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86]
wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22]
wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}]
wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22]
wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22]
wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86]
wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86]
wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86]
wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19]
assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22]
wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18]
wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29]
wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86]
wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}]
wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18]
wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62]
wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}]
wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22]
wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}]
wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22]
wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22]
wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86]
wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17]
wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86]
wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86]
wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19]
assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22]
wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7]
wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7]
wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7]
wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7]
wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7]
wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7]
wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7]
wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7]
wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7]
wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7]
wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7]
wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7]
wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7]
wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7]
wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7]
wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7]
wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7]
wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7]
wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}]
wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7]
wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7]
wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7]
wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7]
wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7]
wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7]
wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7]
wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}]
wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7]
wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7]
wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24]
wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24]
wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24]
wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24]
wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24]
wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13]
wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86]
wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19]
wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24]
wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}]
wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}]
wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}]
wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15]
wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15]
wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15]
wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15]
wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15]
wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13]
wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86]
wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19]
wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}]
wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}]
wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22]
wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22]
wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22]
wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22]
wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22]
wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13]
wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86]
wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19]
wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}]
wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}]
wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29]
wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}]
wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}]
wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}]
wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19]
wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31]
wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}]
wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24]
wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24]
wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13]
wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86]
wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19]
wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14]
wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86]
wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}]
wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}]
wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}]
wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29]
wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}]
wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}]
wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7]
wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7]
wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7]
wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7]
wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7]
wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7]
wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7]
wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7]
wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}]
wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24]
wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}]
wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}]
wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24]
wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15]
wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15]
wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15]
wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15]
wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15]
wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13]
wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86]
wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}]
wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}]
wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}]
wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}]
wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}]
wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}]
wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21]
wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21]
wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21]
wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21]
wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}]
wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21]
wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21]
wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21]
wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21]
wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23]
wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}]
wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}]
wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21]
wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21]
wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21]
wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21]
wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}]
wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86]
wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}]
wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86]
wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}]
wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}]
wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}]
wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}]
wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86]
wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12]
wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12]
wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76]
wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12]
wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}]
wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7]
wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7]
wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86]
wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}]
wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86]
wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}]
wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86]
wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}]
wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76]
wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86]
wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86]
wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86]
wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19]
wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}]
wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7]
wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7]
wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7]
wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7]
wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7]
wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7]
wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7]
wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7]
wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7]
wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7]
wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7]
wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7]
wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7]
wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7]
wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7]
wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7]
wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7]
wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7]
wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7]
wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7]
wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17]
wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}]
wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17]
wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17]
wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26]
wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}]
wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17]
wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}]
wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17]
wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36]
wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}]
wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17]
wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}]
wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17]
wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17]
wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48]
wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}]
wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17]
wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}]
wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17]
wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17]
wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58]
wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}]
wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21]
wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}]
wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}]
wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21]
wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21]
wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86]
wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86]
wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17]
wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19]
wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17]
wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29]
wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17]
wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39]
wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17]
wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71]
wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17]
wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82]
wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}]
wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}]
wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24]
wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24]
wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}]
wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24]
wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24]
wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24]
wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86]
wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17]
wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86]
wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17]
wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19]
wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17]
wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29]
wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17]
wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39]
wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86]
wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17]
wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71]
wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}]
wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}]
wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17]
wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82]
wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}]
wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86]
wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24]
wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24]
wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}]
wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24]
wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24]
wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24]
wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86]
wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17]
wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19]
wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27]
wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}]
wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}]
wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24]
wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24]
wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86]
wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24]
wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19]
assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24]
wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}]
wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}]
wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20]
wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25]
wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86]
wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25]
wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25]
wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19]
assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25]
wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7]
wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7]
wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}]
wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}]
wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20]
wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24]
wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86]
wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86]
wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24]
wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19]
assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24]
wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}]
wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}]
wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20]
wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24]
wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86]
wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24]
wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24]
wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19]
assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24]
wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22]
wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22]
wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22]
wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22]
wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19]
assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22]
wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25]
wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25]
wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25]
wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25]
wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19]
assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25]
wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19]
wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19]
wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19]
wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29]
wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27]
wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}]
wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37]
wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}]
wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19]
assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33]
wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27]
wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}]
wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}]
wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}]
wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}]
wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}]
wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21]
wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21]
wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21]
wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}]
wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000}; // @[RVC.scala:140:{23,46}]
wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37]
wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}]
wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19]
assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33]
wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30]
wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}]
wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86]
wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}]
wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}]
wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}]
wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}]
wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}]
wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}]
wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}]
wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}]
wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}]
wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20]
wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34]
wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}]
wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20]
wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66]
wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}]
wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25]
wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}]
wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86]
wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25]
wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19]
assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25]
wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7]
wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7]
wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7]
wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7]
wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}]
wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20]
wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33]
wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}]
wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20]
wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65]
wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86]
wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24]
wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}]
wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86]
wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24]
wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19]
assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24]
wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}]
wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20]
wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33]
wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}]
wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20]
wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65]
wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}]
wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24]
wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}]
wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86]
wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24]
wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13]
wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14]
wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19]
wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19]
assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24]
wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19]
wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7]
wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19]
wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7]
wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19]
wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19]
wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19]
wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19]
wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19]
wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7]
wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7]
wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}]
wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86]
wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86]
wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86]
wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86]
wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86]
wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86]
wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86]
wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86]
wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86]
wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86]
wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86]
wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86]
wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86]
wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86]
wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86]
wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86]
wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86]
wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86]
wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86]
wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86]
wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86]
wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86]
wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86]
wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86]
wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86]
wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86]
wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86]
wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86]
wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86]
wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86]
wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}]
wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}]
wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86]
assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}]
assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}]
assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}]
assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}]
assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}]
assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76]
assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76]
assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76]
assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76]
assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76]
wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7]
wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7]
wire _io_ill_s_T_1 = |_io_ill_s_T; // @[RVC.scala:158:{19,27}]
wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}]
wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47]
wire _io_ill_s_T_5 = |_io_ill_s_T_4; // @[RVC.scala:168:{27,34}]
wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}]
wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}]
wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}]
wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}]
wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}]
wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18]
wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18]
wire _io_ill_s_T_14 = |_io_ill_s_T_13; // @[RVC.scala:177:{21,29}]
wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}]
wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}]
wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86]
wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}]
wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86]
wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}]
wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86]
wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}]
wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86]
wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8; // @[package.scala:39:{76,86}]
wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86]
wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}]
wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86]
wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}]
wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86]
wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}]
wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86]
wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}]
wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86]
wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}]
wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86]
wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}]
wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86]
wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}]
wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86]
wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}]
wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86]
wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}]
wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86]
wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}]
wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86]
wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}]
wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86]
wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}]
wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86]
wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}]
wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86]
wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}]
wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86]
wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}]
wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86]
wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}]
wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86]
wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}]
wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86]
wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}]
wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86]
wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}]
wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86]
wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}]
wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86]
wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}]
wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86]
wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}]
wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86]
wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}]
wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86]
wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}]
wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86]
wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}]
wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86]
wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}]
wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86]
assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}]
assign io_ill = _io_ill_T_64; // @[package.scala:39:76]
assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7]
assign io_rvc = io_rvc_0; // @[RVC.scala:190:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<4>(0h8))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_7
node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_28 = cvt(_T_27)
node _T_29 = and(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = asSInt(_T_29)
node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0)))
node _T_32 = or(_T_26, _T_31)
node _T_33 = and(_T_11, _T_24)
node _T_34 = and(_T_33, _T_32)
node _T_35 = asUInt(reset)
node _T_36 = eq(_T_35, UInt<1>(0h0))
when _T_36 :
node _T_37 = eq(_T_34, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_34, UInt<1>(0h1), "") : assert_1
node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_38 :
node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_50 = or(_T_42, _T_48)
node _T_51 = or(_T_50, _T_49)
node _T_52 = and(_T_41, _T_51)
node _T_53 = or(UInt<1>(0h0), _T_52)
node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_59, _T_64)
node _T_96 = or(_T_95, _T_69)
node _T_97 = or(_T_96, _T_74)
node _T_98 = or(_T_97, _T_79)
node _T_99 = or(_T_98, _T_84)
node _T_100 = or(_T_99, _T_89)
node _T_101 = or(_T_100, _T_94)
node _T_102 = and(_T_54, _T_101)
node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_104 = or(UInt<1>(0h0), _T_103)
node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = or(_T_109, _T_114)
node _T_116 = and(_T_104, _T_115)
node _T_117 = or(UInt<1>(0h0), _T_102)
node _T_118 = or(_T_117, _T_116)
node _T_119 = and(_T_53, _T_118)
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_119, UInt<1>(0h1), "") : assert_2
node _T_123 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_124 = shr(io.in.a.bits.source, 2)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_127 = and(_T_125, _T_126)
node _T_128 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_129 = and(_T_127, _T_128)
node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_123
connect _WIRE[1], _T_129
connect _WIRE[2], _T_130
node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_132 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_133 = mux(_WIRE[1], _T_131, UInt<1>(0h0))
node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_135 = or(_T_132, _T_133)
node _T_136 = or(_T_135, _T_134)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_136
node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_139 = and(_T_137, _T_138)
node _T_140 = or(UInt<1>(0h0), _T_139)
node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_142 = cvt(_T_141)
node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000)))
node _T_144 = asSInt(_T_143)
node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0)))
node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_167 = cvt(_T_166)
node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000)))
node _T_169 = asSInt(_T_168)
node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0)))
node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_172 = cvt(_T_171)
node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000)))
node _T_174 = asSInt(_T_173)
node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_145, _T_150)
node _T_192 = or(_T_191, _T_155)
node _T_193 = or(_T_192, _T_160)
node _T_194 = or(_T_193, _T_165)
node _T_195 = or(_T_194, _T_170)
node _T_196 = or(_T_195, _T_175)
node _T_197 = or(_T_196, _T_180)
node _T_198 = or(_T_197, _T_185)
node _T_199 = or(_T_198, _T_190)
node _T_200 = and(_T_140, _T_199)
node _T_201 = or(UInt<1>(0h0), _T_200)
node _T_202 = and(_WIRE_1, _T_201)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_202, UInt<1>(0h1), "") : assert_3
node _T_206 = asUInt(reset)
node _T_207 = eq(_T_206, UInt<1>(0h0))
when _T_207 :
node _T_208 = eq(source_ok, UInt<1>(0h0))
when _T_208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_210 = asUInt(reset)
node _T_211 = eq(_T_210, UInt<1>(0h0))
when _T_211 :
node _T_212 = eq(_T_209, UInt<1>(0h0))
when _T_212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_209, UInt<1>(0h1), "") : assert_5
node _T_213 = asUInt(reset)
node _T_214 = eq(_T_213, UInt<1>(0h0))
when _T_214 :
node _T_215 = eq(is_aligned, UInt<1>(0h0))
when _T_215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_216, UInt<1>(0h1), "") : assert_7
node _T_220 = not(io.in.a.bits.mask)
node _T_221 = eq(_T_220, UInt<1>(0h0))
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_T_221, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_221, UInt<1>(0h1), "") : assert_8
node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_225, UInt<1>(0h1), "") : assert_9
node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_229 :
node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_234 = shr(io.in.a.bits.source, 2)
node _T_235 = eq(_T_234, UInt<1>(0h0))
node _T_236 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_237 = and(_T_235, _T_236)
node _T_238 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_241 = or(_T_233, _T_239)
node _T_242 = or(_T_241, _T_240)
node _T_243 = and(_T_232, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_252 = cvt(_T_251)
node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000)))
node _T_254 = asSInt(_T_253)
node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0)))
node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_257 = cvt(_T_256)
node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000)))
node _T_259 = asSInt(_T_258)
node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0)))
node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_262 = cvt(_T_261)
node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000)))
node _T_264 = asSInt(_T_263)
node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0)))
node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_267 = cvt(_T_266)
node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000)))
node _T_269 = asSInt(_T_268)
node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0)))
node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_277 = cvt(_T_276)
node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000)))
node _T_279 = asSInt(_T_278)
node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0)))
node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_282 = cvt(_T_281)
node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000)))
node _T_284 = asSInt(_T_283)
node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0)))
node _T_286 = or(_T_250, _T_255)
node _T_287 = or(_T_286, _T_260)
node _T_288 = or(_T_287, _T_265)
node _T_289 = or(_T_288, _T_270)
node _T_290 = or(_T_289, _T_275)
node _T_291 = or(_T_290, _T_280)
node _T_292 = or(_T_291, _T_285)
node _T_293 = and(_T_245, _T_292)
node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_297 = cvt(_T_296)
node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000)))
node _T_299 = asSInt(_T_298)
node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0)))
node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = or(_T_300, _T_305)
node _T_307 = and(_T_295, _T_306)
node _T_308 = or(UInt<1>(0h0), _T_293)
node _T_309 = or(_T_308, _T_307)
node _T_310 = and(_T_244, _T_309)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_310, UInt<1>(0h1), "") : assert_10
node _T_314 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<1>(0h0))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_314
connect _WIRE_2[1], _T_320
connect _WIRE_2[2], _T_321
node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_323 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_324 = mux(_WIRE_2[1], _T_322, UInt<1>(0h0))
node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_326 = or(_T_323, _T_324)
node _T_327 = or(_T_326, _T_325)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_327
node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_330 = and(_T_328, _T_329)
node _T_331 = or(UInt<1>(0h0), _T_330)
node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_343 = cvt(_T_342)
node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000)))
node _T_345 = asSInt(_T_344)
node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0)))
node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_348 = cvt(_T_347)
node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000)))
node _T_350 = asSInt(_T_349)
node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0)))
node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_353 = cvt(_T_352)
node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000)))
node _T_355 = asSInt(_T_354)
node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0)))
node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_358 = cvt(_T_357)
node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000)))
node _T_360 = asSInt(_T_359)
node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0)))
node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = or(_T_336, _T_341)
node _T_383 = or(_T_382, _T_346)
node _T_384 = or(_T_383, _T_351)
node _T_385 = or(_T_384, _T_356)
node _T_386 = or(_T_385, _T_361)
node _T_387 = or(_T_386, _T_366)
node _T_388 = or(_T_387, _T_371)
node _T_389 = or(_T_388, _T_376)
node _T_390 = or(_T_389, _T_381)
node _T_391 = and(_T_331, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = and(_WIRE_3, _T_392)
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_393, UInt<1>(0h1), "") : assert_11
node _T_397 = asUInt(reset)
node _T_398 = eq(_T_397, UInt<1>(0h0))
when _T_398 :
node _T_399 = eq(source_ok, UInt<1>(0h0))
when _T_399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_401 = asUInt(reset)
node _T_402 = eq(_T_401, UInt<1>(0h0))
when _T_402 :
node _T_403 = eq(_T_400, UInt<1>(0h0))
when _T_403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_400, UInt<1>(0h1), "") : assert_13
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(is_aligned, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_407, UInt<1>(0h1), "") : assert_15
node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_411, UInt<1>(0h1), "") : assert_16
node _T_415 = not(io.in.a.bits.mask)
node _T_416 = eq(_T_415, UInt<1>(0h0))
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_416, UInt<1>(0h1), "") : assert_17
node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_T_420, UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_420, UInt<1>(0h1), "") : assert_18
node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_424 :
node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_429 = shr(io.in.a.bits.source, 2)
node _T_430 = eq(_T_429, UInt<1>(0h0))
node _T_431 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_432 = and(_T_430, _T_431)
node _T_433 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_436 = or(_T_428, _T_434)
node _T_437 = or(_T_436, _T_435)
node _T_438 = and(_T_427, _T_437)
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_439, UInt<1>(0h1), "") : assert_19
node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_445 = and(_T_443, _T_444)
node _T_446 = or(UInt<1>(0h0), _T_445)
node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = and(_T_446, _T_451)
node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_455 = and(_T_453, _T_454)
node _T_456 = or(UInt<1>(0h0), _T_455)
node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = or(_T_461, _T_466)
node _T_503 = or(_T_502, _T_471)
node _T_504 = or(_T_503, _T_476)
node _T_505 = or(_T_504, _T_481)
node _T_506 = or(_T_505, _T_486)
node _T_507 = or(_T_506, _T_491)
node _T_508 = or(_T_507, _T_496)
node _T_509 = or(_T_508, _T_501)
node _T_510 = and(_T_456, _T_509)
node _T_511 = or(UInt<1>(0h0), _T_452)
node _T_512 = or(_T_511, _T_510)
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_512, UInt<1>(0h1), "") : assert_20
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(source_ok, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(is_aligned, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_522, UInt<1>(0h1), "") : assert_23
node _T_526 = eq(io.in.a.bits.mask, mask)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_526, UInt<1>(0h1), "") : assert_24
node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_530, UInt<1>(0h1), "") : assert_25
node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_534 :
node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_539 = shr(io.in.a.bits.source, 2)
node _T_540 = eq(_T_539, UInt<1>(0h0))
node _T_541 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_542 = and(_T_540, _T_541)
node _T_543 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_546 = or(_T_538, _T_544)
node _T_547 = or(_T_546, _T_545)
node _T_548 = and(_T_537, _T_547)
node _T_549 = or(UInt<1>(0h0), _T_548)
node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_552 = and(_T_550, _T_551)
node _T_553 = or(UInt<1>(0h0), _T_552)
node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_555 = cvt(_T_554)
node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000)))
node _T_557 = asSInt(_T_556)
node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0)))
node _T_559 = and(_T_553, _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_570 = cvt(_T_569)
node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000)))
node _T_572 = asSInt(_T_571)
node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0)))
node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = or(_T_568, _T_573)
node _T_605 = or(_T_604, _T_578)
node _T_606 = or(_T_605, _T_583)
node _T_607 = or(_T_606, _T_588)
node _T_608 = or(_T_607, _T_593)
node _T_609 = or(_T_608, _T_598)
node _T_610 = or(_T_609, _T_603)
node _T_611 = and(_T_563, _T_610)
node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = and(_T_612, _T_617)
node _T_619 = or(UInt<1>(0h0), _T_559)
node _T_620 = or(_T_619, _T_611)
node _T_621 = or(_T_620, _T_618)
node _T_622 = and(_T_549, _T_621)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_622, UInt<1>(0h1), "") : assert_26
node _T_626 = asUInt(reset)
node _T_627 = eq(_T_626, UInt<1>(0h0))
when _T_627 :
node _T_628 = eq(source_ok, UInt<1>(0h0))
when _T_628 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(is_aligned, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_632, UInt<1>(0h1), "") : assert_29
node _T_636 = eq(io.in.a.bits.mask, mask)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_636, UInt<1>(0h1), "") : assert_30
node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_640 :
node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_643 = and(_T_641, _T_642)
node _T_644 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_645 = shr(io.in.a.bits.source, 2)
node _T_646 = eq(_T_645, UInt<1>(0h0))
node _T_647 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_648 = and(_T_646, _T_647)
node _T_649 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_652 = or(_T_644, _T_650)
node _T_653 = or(_T_652, _T_651)
node _T_654 = and(_T_643, _T_653)
node _T_655 = or(UInt<1>(0h0), _T_654)
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = or(UInt<1>(0h0), _T_658)
node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_661 = cvt(_T_660)
node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000)))
node _T_663 = asSInt(_T_662)
node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0)))
node _T_665 = and(_T_659, _T_664)
node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_668 = and(_T_666, _T_667)
node _T_669 = or(UInt<1>(0h0), _T_668)
node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_671 = cvt(_T_670)
node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000)))
node _T_673 = asSInt(_T_672)
node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0)))
node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = or(_T_674, _T_679)
node _T_711 = or(_T_710, _T_684)
node _T_712 = or(_T_711, _T_689)
node _T_713 = or(_T_712, _T_694)
node _T_714 = or(_T_713, _T_699)
node _T_715 = or(_T_714, _T_704)
node _T_716 = or(_T_715, _T_709)
node _T_717 = and(_T_669, _T_716)
node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_720 = cvt(_T_719)
node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000)))
node _T_722 = asSInt(_T_721)
node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0)))
node _T_724 = and(_T_718, _T_723)
node _T_725 = or(UInt<1>(0h0), _T_665)
node _T_726 = or(_T_725, _T_717)
node _T_727 = or(_T_726, _T_724)
node _T_728 = and(_T_655, _T_727)
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_T_728, UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_728, UInt<1>(0h1), "") : assert_31
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(source_ok, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(is_aligned, UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_739 = asUInt(reset)
node _T_740 = eq(_T_739, UInt<1>(0h0))
when _T_740 :
node _T_741 = eq(_T_738, UInt<1>(0h0))
when _T_741 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_738, UInt<1>(0h1), "") : assert_34
node _T_742 = not(mask)
node _T_743 = and(io.in.a.bits.mask, _T_742)
node _T_744 = eq(_T_743, UInt<1>(0h0))
node _T_745 = asUInt(reset)
node _T_746 = eq(_T_745, UInt<1>(0h0))
when _T_746 :
node _T_747 = eq(_T_744, UInt<1>(0h0))
when _T_747 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_744, UInt<1>(0h1), "") : assert_35
node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_748 :
node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_751 = and(_T_749, _T_750)
node _T_752 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_753 = shr(io.in.a.bits.source, 2)
node _T_754 = eq(_T_753, UInt<1>(0h0))
node _T_755 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_756 = and(_T_754, _T_755)
node _T_757 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_760 = or(_T_752, _T_758)
node _T_761 = or(_T_760, _T_759)
node _T_762 = and(_T_751, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_762)
node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_766 = and(_T_764, _T_765)
node _T_767 = or(UInt<1>(0h0), _T_766)
node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_769 = cvt(_T_768)
node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000)))
node _T_771 = asSInt(_T_770)
node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0)))
node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_774 = cvt(_T_773)
node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000)))
node _T_776 = asSInt(_T_775)
node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0)))
node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_784 = cvt(_T_783)
node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000)))
node _T_786 = asSInt(_T_785)
node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0)))
node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_789 = cvt(_T_788)
node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000)))
node _T_791 = asSInt(_T_790)
node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0)))
node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_794 = cvt(_T_793)
node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000)))
node _T_796 = asSInt(_T_795)
node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0)))
node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_799 = cvt(_T_798)
node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000)))
node _T_801 = asSInt(_T_800)
node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0)))
node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_809 = cvt(_T_808)
node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000)))
node _T_811 = asSInt(_T_810)
node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0)))
node _T_813 = or(_T_772, _T_777)
node _T_814 = or(_T_813, _T_782)
node _T_815 = or(_T_814, _T_787)
node _T_816 = or(_T_815, _T_792)
node _T_817 = or(_T_816, _T_797)
node _T_818 = or(_T_817, _T_802)
node _T_819 = or(_T_818, _T_807)
node _T_820 = or(_T_819, _T_812)
node _T_821 = and(_T_767, _T_820)
node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_824 = cvt(_T_823)
node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000)))
node _T_826 = asSInt(_T_825)
node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0)))
node _T_828 = and(_T_822, _T_827)
node _T_829 = or(UInt<1>(0h0), _T_821)
node _T_830 = or(_T_829, _T_828)
node _T_831 = and(_T_763, _T_830)
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_T_831, UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_831, UInt<1>(0h1), "") : assert_36
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(source_ok, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_838 = asUInt(reset)
node _T_839 = eq(_T_838, UInt<1>(0h0))
when _T_839 :
node _T_840 = eq(is_aligned, UInt<1>(0h0))
when _T_840 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_841, UInt<1>(0h1), "") : assert_39
node _T_845 = eq(io.in.a.bits.mask, mask)
node _T_846 = asUInt(reset)
node _T_847 = eq(_T_846, UInt<1>(0h0))
when _T_847 :
node _T_848 = eq(_T_845, UInt<1>(0h0))
when _T_848 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_845, UInt<1>(0h1), "") : assert_40
node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_849 :
node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_852 = and(_T_850, _T_851)
node _T_853 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_854 = shr(io.in.a.bits.source, 2)
node _T_855 = eq(_T_854, UInt<1>(0h0))
node _T_856 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_857 = and(_T_855, _T_856)
node _T_858 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_859 = and(_T_857, _T_858)
node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_861 = or(_T_853, _T_859)
node _T_862 = or(_T_861, _T_860)
node _T_863 = and(_T_852, _T_862)
node _T_864 = or(UInt<1>(0h0), _T_863)
node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_867 = and(_T_865, _T_866)
node _T_868 = or(UInt<1>(0h0), _T_867)
node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_905 = cvt(_T_904)
node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000)))
node _T_907 = asSInt(_T_906)
node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0)))
node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = or(_T_873, _T_878)
node _T_915 = or(_T_914, _T_883)
node _T_916 = or(_T_915, _T_888)
node _T_917 = or(_T_916, _T_893)
node _T_918 = or(_T_917, _T_898)
node _T_919 = or(_T_918, _T_903)
node _T_920 = or(_T_919, _T_908)
node _T_921 = or(_T_920, _T_913)
node _T_922 = and(_T_868, _T_921)
node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = and(_T_923, _T_928)
node _T_930 = or(UInt<1>(0h0), _T_922)
node _T_931 = or(_T_930, _T_929)
node _T_932 = and(_T_864, _T_931)
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(_T_932, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_932, UInt<1>(0h1), "") : assert_41
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(source_ok, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_939 = asUInt(reset)
node _T_940 = eq(_T_939, UInt<1>(0h0))
when _T_940 :
node _T_941 = eq(is_aligned, UInt<1>(0h0))
when _T_941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_943 = asUInt(reset)
node _T_944 = eq(_T_943, UInt<1>(0h0))
when _T_944 :
node _T_945 = eq(_T_942, UInt<1>(0h0))
when _T_945 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_942, UInt<1>(0h1), "") : assert_44
node _T_946 = eq(io.in.a.bits.mask, mask)
node _T_947 = asUInt(reset)
node _T_948 = eq(_T_947, UInt<1>(0h0))
when _T_948 :
node _T_949 = eq(_T_946, UInt<1>(0h0))
when _T_949 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_946, UInt<1>(0h1), "") : assert_45
node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_950 :
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_953 = and(_T_951, _T_952)
node _T_954 = eq(io.in.a.bits.source, UInt<4>(0h8))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_955 = shr(io.in.a.bits.source, 2)
node _T_956 = eq(_T_955, UInt<1>(0h0))
node _T_957 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_958 = and(_T_956, _T_957)
node _T_959 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_960 = and(_T_958, _T_959)
node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4))
node _T_962 = or(_T_954, _T_960)
node _T_963 = or(_T_962, _T_961)
node _T_964 = and(_T_953, _T_963)
node _T_965 = or(UInt<1>(0h0), _T_964)
node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_968 = and(_T_966, _T_967)
node _T_969 = or(UInt<1>(0h0), _T_968)
node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_971 = cvt(_T_970)
node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000)))
node _T_973 = asSInt(_T_972)
node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0)))
node _T_975 = and(_T_969, _T_974)
node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_988 = cvt(_T_987)
node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000)))
node _T_990 = asSInt(_T_989)
node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0)))
node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = or(_T_981, _T_986)
node _T_1013 = or(_T_1012, _T_991)
node _T_1014 = or(_T_1013, _T_996)
node _T_1015 = or(_T_1014, _T_1001)
node _T_1016 = or(_T_1015, _T_1006)
node _T_1017 = or(_T_1016, _T_1011)
node _T_1018 = and(_T_976, _T_1017)
node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1024 = cvt(_T_1023)
node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000)))
node _T_1026 = asSInt(_T_1025)
node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0)))
node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1029 = cvt(_T_1028)
node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000)))
node _T_1031 = asSInt(_T_1030)
node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0)))
node _T_1033 = or(_T_1027, _T_1032)
node _T_1034 = and(_T_1022, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_975)
node _T_1036 = or(_T_1035, _T_1018)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_965, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49
node _T_1052 = eq(io.in.a.bits.mask, mask)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50
node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52
node _source_ok_T_9 = eq(io.in.d.bits.source, UInt<4>(0h8))
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_10 = shr(io.in.d.bits.source, 2)
node _source_ok_T_11 = eq(_source_ok_T_10, UInt<1>(0h0))
node _source_ok_T_12 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_13 = and(_source_ok_T_11, _source_ok_T_12)
node _source_ok_T_14 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_9
connect _source_ok_WIRE_1[1], _source_ok_T_15
connect _source_ok_WIRE_1[2], _source_ok_T_16
node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1064 :
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(source_ok_1, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54
node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55
node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56
node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57
node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1084 :
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(source_ok_1, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1088 = asUInt(reset)
node _T_1089 = eq(_T_1088, UInt<1>(0h0))
when _T_1089 :
node _T_1090 = eq(sink_ok, UInt<1>(0h0))
when _T_1090 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1092 = asUInt(reset)
node _T_1093 = eq(_T_1092, UInt<1>(0h0))
when _T_1093 :
node _T_1094 = eq(_T_1091, UInt<1>(0h0))
when _T_1094 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60
node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1096 = asUInt(reset)
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(_T_1095, UInt<1>(0h0))
when _T_1098 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61
node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1100 = asUInt(reset)
node _T_1101 = eq(_T_1100, UInt<1>(0h0))
when _T_1101 :
node _T_1102 = eq(_T_1099, UInt<1>(0h0))
when _T_1102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62
node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63
node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1108 = or(UInt<1>(0h1), _T_1107)
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(_T_1108, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64
node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1112 :
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok_1, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(sink_ok, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67
node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68
node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(_T_1127, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69
node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1132 = or(_T_1131, io.in.d.bits.corrupt)
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70
node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1137 = or(UInt<1>(0h1), _T_1136)
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71
node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1141 :
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(source_ok_1, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73
node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(_T_1149, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74
node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1154 = or(UInt<1>(0h1), _T_1153)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75
node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1158 :
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok_1, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77
node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1167 = or(_T_1166, io.in.d.bits.corrupt)
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78
node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1172 = or(UInt<1>(0h1), _T_1171)
node _T_1173 = asUInt(reset)
node _T_1174 = eq(_T_1173, UInt<1>(0h0))
when _T_1174 :
node _T_1175 = eq(_T_1172, UInt<1>(0h0))
when _T_1175 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79
node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1176 :
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(source_ok_1, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81
node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82
node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1189 = or(UInt<1>(0h1), _T_1188)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84
node _T_1197 = eq(io.in.b.bits.source, UInt<4>(0h8))
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
node _T_1199 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1200 = cvt(_T_1199)
node _T_1201 = and(_T_1200, asSInt(UInt<1>(0h0)))
node _T_1202 = asSInt(_T_1201)
node _T_1203 = eq(_T_1202, asSInt(UInt<1>(0h0)))
node _T_1204 = or(_T_1198, _T_1203)
node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_1205 = shr(io.in.b.bits.source, 2)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
node _T_1207 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_1210 = and(_T_1208, _T_1209)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1213 = cvt(_T_1212)
node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0)))
node _T_1215 = asSInt(_T_1214)
node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0)))
node _T_1217 = or(_T_1211, _T_1216)
node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4))
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1221 = cvt(_T_1220)
node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0)))
node _T_1223 = asSInt(_T_1222)
node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0)))
node _T_1225 = or(_T_1219, _T_1224)
node _T_1226 = and(_T_1204, _T_1217)
node _T_1227 = and(_T_1226, _T_1225)
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[12]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2])
node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3])
node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4])
node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5])
node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6])
node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7])
node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8])
node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9])
node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10])
node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<4>(0h8))
node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0))
node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0)
node _legal_source_T_1 = shr(io.in.b.bits.source, 2)
node _legal_source_T_2 = eq(_legal_source_T_1, UInt<1>(0h0))
node _legal_source_T_3 = leq(UInt<1>(0h0), legal_source_uncommonBits)
node _legal_source_T_4 = and(_legal_source_T_2, _legal_source_T_3)
node _legal_source_T_5 = leq(legal_source_uncommonBits, UInt<2>(0h3))
node _legal_source_T_6 = and(_legal_source_T_4, _legal_source_T_5)
node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_6
connect _legal_source_WIRE[2], _legal_source_T_7
node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<4>(0h8), UInt<1>(0h0))
node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0))
node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9)
node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10)
wire _legal_source_WIRE_1 : UInt<4>
connect _legal_source_WIRE_1, _legal_source_T_12
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1231 :
node _T_1232 = eq(io.in.b.bits.source, UInt<4>(0h8))
node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_1233 = shr(io.in.b.bits.source, 2)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
node _T_1235 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_1236 = and(_T_1234, _T_1235)
node _T_1237 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_1238 = and(_T_1236, _T_1237)
node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1232
connect _WIRE_4[1], _T_1238
connect _WIRE_4[2], _T_1239
node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1241 = mux(_WIRE_4[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_1242 = mux(_WIRE_4[1], _T_1240, UInt<1>(0h0))
node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1244 = or(_T_1241, _T_1242)
node _T_1245 = or(_T_1244, _T_1243)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1245
node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1248 = and(_T_1246, _T_1247)
node _T_1249 = or(UInt<1>(0h0), _T_1248)
node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1251 = cvt(_T_1250)
node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000)))
node _T_1253 = asSInt(_T_1252)
node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0)))
node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1256 = cvt(_T_1255)
node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000)))
node _T_1258 = asSInt(_T_1257)
node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0)))
node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1261 = cvt(_T_1260)
node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000)))
node _T_1263 = asSInt(_T_1262)
node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0)))
node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1266 = cvt(_T_1265)
node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000)))
node _T_1268 = asSInt(_T_1267)
node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0)))
node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1271 = cvt(_T_1270)
node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000)))
node _T_1273 = asSInt(_T_1272)
node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0)))
node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1276 = cvt(_T_1275)
node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000)))
node _T_1278 = asSInt(_T_1277)
node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0)))
node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1281 = cvt(_T_1280)
node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000)))
node _T_1283 = asSInt(_T_1282)
node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0)))
node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1286 = cvt(_T_1285)
node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000)))
node _T_1288 = asSInt(_T_1287)
node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0)))
node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1291 = cvt(_T_1290)
node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000)))
node _T_1293 = asSInt(_T_1292)
node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0)))
node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1296 = cvt(_T_1295)
node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000)))
node _T_1298 = asSInt(_T_1297)
node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0)))
node _T_1300 = or(_T_1254, _T_1259)
node _T_1301 = or(_T_1300, _T_1264)
node _T_1302 = or(_T_1301, _T_1269)
node _T_1303 = or(_T_1302, _T_1274)
node _T_1304 = or(_T_1303, _T_1279)
node _T_1305 = or(_T_1304, _T_1284)
node _T_1306 = or(_T_1305, _T_1289)
node _T_1307 = or(_T_1306, _T_1294)
node _T_1308 = or(_T_1307, _T_1299)
node _T_1309 = and(_T_1249, _T_1308)
node _T_1310 = or(UInt<1>(0h0), _T_1309)
node _T_1311 = and(_WIRE_5, _T_1310)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(address_ok, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1318 = asUInt(reset)
node _T_1319 = eq(_T_1318, UInt<1>(0h0))
when _T_1319 :
node _T_1320 = eq(legal_source, UInt<1>(0h0))
when _T_1320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90
node _T_1328 = eq(io.in.b.bits.mask, mask_1)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91
node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92
node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1336 :
node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1339 = and(_T_1337, _T_1338)
node _T_1340 = or(UInt<1>(0h0), _T_1339)
node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1342 = cvt(_T_1341)
node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000)))
node _T_1344 = asSInt(_T_1343)
node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0)))
node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1347 = cvt(_T_1346)
node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000)))
node _T_1349 = asSInt(_T_1348)
node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0)))
node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1352 = cvt(_T_1351)
node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000)))
node _T_1354 = asSInt(_T_1353)
node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0)))
node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1357 = cvt(_T_1356)
node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000)))
node _T_1359 = asSInt(_T_1358)
node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0)))
node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1362 = cvt(_T_1361)
node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000)))
node _T_1364 = asSInt(_T_1363)
node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0)))
node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1367 = cvt(_T_1366)
node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000)))
node _T_1369 = asSInt(_T_1368)
node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0)))
node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1372 = cvt(_T_1371)
node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000)))
node _T_1374 = asSInt(_T_1373)
node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0)))
node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1377 = cvt(_T_1376)
node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000)))
node _T_1379 = asSInt(_T_1378)
node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0)))
node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1382 = cvt(_T_1381)
node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000)))
node _T_1384 = asSInt(_T_1383)
node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0)))
node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = or(_T_1345, _T_1350)
node _T_1392 = or(_T_1391, _T_1355)
node _T_1393 = or(_T_1392, _T_1360)
node _T_1394 = or(_T_1393, _T_1365)
node _T_1395 = or(_T_1394, _T_1370)
node _T_1396 = or(_T_1395, _T_1375)
node _T_1397 = or(_T_1396, _T_1380)
node _T_1398 = or(_T_1397, _T_1385)
node _T_1399 = or(_T_1398, _T_1390)
node _T_1400 = and(_T_1340, _T_1399)
node _T_1401 = or(UInt<1>(0h0), _T_1400)
node _T_1402 = and(UInt<1>(0h0), _T_1401)
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(_T_1402, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93
node _T_1406 = asUInt(reset)
node _T_1407 = eq(_T_1406, UInt<1>(0h0))
when _T_1407 :
node _T_1408 = eq(address_ok, UInt<1>(0h0))
when _T_1408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(legal_source, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1412 = asUInt(reset)
node _T_1413 = eq(_T_1412, UInt<1>(0h0))
when _T_1413 :
node _T_1414 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1416 = asUInt(reset)
node _T_1417 = eq(_T_1416, UInt<1>(0h0))
when _T_1417 :
node _T_1418 = eq(_T_1415, UInt<1>(0h0))
when _T_1418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97
node _T_1419 = eq(io.in.b.bits.mask, mask_1)
node _T_1420 = asUInt(reset)
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(_T_1419, UInt<1>(0h0))
when _T_1422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98
node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99
node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1430 = and(_T_1428, _T_1429)
node _T_1431 = or(UInt<1>(0h0), _T_1430)
node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1433 = cvt(_T_1432)
node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000)))
node _T_1435 = asSInt(_T_1434)
node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0)))
node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1438 = cvt(_T_1437)
node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000)))
node _T_1440 = asSInt(_T_1439)
node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0)))
node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1443 = cvt(_T_1442)
node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000)))
node _T_1445 = asSInt(_T_1444)
node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0)))
node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1448 = cvt(_T_1447)
node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000)))
node _T_1450 = asSInt(_T_1449)
node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0)))
node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1453 = cvt(_T_1452)
node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000)))
node _T_1455 = asSInt(_T_1454)
node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0)))
node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1458 = cvt(_T_1457)
node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000)))
node _T_1460 = asSInt(_T_1459)
node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0)))
node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1463 = cvt(_T_1462)
node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000)))
node _T_1465 = asSInt(_T_1464)
node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0)))
node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1468 = cvt(_T_1467)
node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000)))
node _T_1470 = asSInt(_T_1469)
node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0)))
node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1473 = cvt(_T_1472)
node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000)))
node _T_1475 = asSInt(_T_1474)
node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0)))
node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1478 = cvt(_T_1477)
node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000)))
node _T_1480 = asSInt(_T_1479)
node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0)))
node _T_1482 = or(_T_1436, _T_1441)
node _T_1483 = or(_T_1482, _T_1446)
node _T_1484 = or(_T_1483, _T_1451)
node _T_1485 = or(_T_1484, _T_1456)
node _T_1486 = or(_T_1485, _T_1461)
node _T_1487 = or(_T_1486, _T_1466)
node _T_1488 = or(_T_1487, _T_1471)
node _T_1489 = or(_T_1488, _T_1476)
node _T_1490 = or(_T_1489, _T_1481)
node _T_1491 = and(_T_1431, _T_1490)
node _T_1492 = or(UInt<1>(0h0), _T_1491)
node _T_1493 = and(UInt<1>(0h0), _T_1492)
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100
node _T_1497 = asUInt(reset)
node _T_1498 = eq(_T_1497, UInt<1>(0h0))
when _T_1498 :
node _T_1499 = eq(address_ok, UInt<1>(0h0))
when _T_1499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(legal_source, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104
node _T_1510 = eq(io.in.b.bits.mask, mask_1)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105
node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1514 :
node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1517 = and(_T_1515, _T_1516)
node _T_1518 = or(UInt<1>(0h0), _T_1517)
node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1520 = cvt(_T_1519)
node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000)))
node _T_1522 = asSInt(_T_1521)
node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0)))
node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1525 = cvt(_T_1524)
node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000)))
node _T_1527 = asSInt(_T_1526)
node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0)))
node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1530 = cvt(_T_1529)
node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000)))
node _T_1532 = asSInt(_T_1531)
node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0)))
node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1535 = cvt(_T_1534)
node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000)))
node _T_1537 = asSInt(_T_1536)
node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0)))
node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1540 = cvt(_T_1539)
node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000)))
node _T_1542 = asSInt(_T_1541)
node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0)))
node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1545 = cvt(_T_1544)
node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000)))
node _T_1547 = asSInt(_T_1546)
node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0)))
node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1550 = cvt(_T_1549)
node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000)))
node _T_1552 = asSInt(_T_1551)
node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0)))
node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1555 = cvt(_T_1554)
node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000)))
node _T_1557 = asSInt(_T_1556)
node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0)))
node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1560 = cvt(_T_1559)
node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000)))
node _T_1562 = asSInt(_T_1561)
node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0)))
node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1565 = cvt(_T_1564)
node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000)))
node _T_1567 = asSInt(_T_1566)
node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0)))
node _T_1569 = or(_T_1523, _T_1528)
node _T_1570 = or(_T_1569, _T_1533)
node _T_1571 = or(_T_1570, _T_1538)
node _T_1572 = or(_T_1571, _T_1543)
node _T_1573 = or(_T_1572, _T_1548)
node _T_1574 = or(_T_1573, _T_1553)
node _T_1575 = or(_T_1574, _T_1558)
node _T_1576 = or(_T_1575, _T_1563)
node _T_1577 = or(_T_1576, _T_1568)
node _T_1578 = and(_T_1518, _T_1577)
node _T_1579 = or(UInt<1>(0h0), _T_1578)
node _T_1580 = and(UInt<1>(0h0), _T_1579)
node _T_1581 = asUInt(reset)
node _T_1582 = eq(_T_1581, UInt<1>(0h0))
when _T_1582 :
node _T_1583 = eq(_T_1580, UInt<1>(0h0))
when _T_1583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106
node _T_1584 = asUInt(reset)
node _T_1585 = eq(_T_1584, UInt<1>(0h0))
when _T_1585 :
node _T_1586 = eq(address_ok, UInt<1>(0h0))
when _T_1586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1587 = asUInt(reset)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
when _T_1588 :
node _T_1589 = eq(legal_source, UInt<1>(0h0))
when _T_1589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110
node _T_1597 = not(mask_1)
node _T_1598 = and(io.in.b.bits.mask, _T_1597)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111
node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1603 :
node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1606 = and(_T_1604, _T_1605)
node _T_1607 = or(UInt<1>(0h0), _T_1606)
node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1609 = cvt(_T_1608)
node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000)))
node _T_1611 = asSInt(_T_1610)
node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0)))
node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1614 = cvt(_T_1613)
node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000)))
node _T_1616 = asSInt(_T_1615)
node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0)))
node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1619 = cvt(_T_1618)
node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000)))
node _T_1621 = asSInt(_T_1620)
node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0)))
node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1624 = cvt(_T_1623)
node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000)))
node _T_1626 = asSInt(_T_1625)
node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0)))
node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1629 = cvt(_T_1628)
node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000)))
node _T_1631 = asSInt(_T_1630)
node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0)))
node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1634 = cvt(_T_1633)
node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000)))
node _T_1636 = asSInt(_T_1635)
node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0)))
node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1639 = cvt(_T_1638)
node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000)))
node _T_1641 = asSInt(_T_1640)
node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0)))
node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1644 = cvt(_T_1643)
node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000)))
node _T_1646 = asSInt(_T_1645)
node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0)))
node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1649 = cvt(_T_1648)
node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000)))
node _T_1651 = asSInt(_T_1650)
node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0)))
node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1654 = cvt(_T_1653)
node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000)))
node _T_1656 = asSInt(_T_1655)
node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0)))
node _T_1658 = or(_T_1612, _T_1617)
node _T_1659 = or(_T_1658, _T_1622)
node _T_1660 = or(_T_1659, _T_1627)
node _T_1661 = or(_T_1660, _T_1632)
node _T_1662 = or(_T_1661, _T_1637)
node _T_1663 = or(_T_1662, _T_1642)
node _T_1664 = or(_T_1663, _T_1647)
node _T_1665 = or(_T_1664, _T_1652)
node _T_1666 = or(_T_1665, _T_1657)
node _T_1667 = and(_T_1607, _T_1666)
node _T_1668 = or(UInt<1>(0h0), _T_1667)
node _T_1669 = and(UInt<1>(0h0), _T_1668)
node _T_1670 = asUInt(reset)
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(_T_1669, UInt<1>(0h0))
when _T_1672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112
node _T_1673 = asUInt(reset)
node _T_1674 = eq(_T_1673, UInt<1>(0h0))
when _T_1674 :
node _T_1675 = eq(address_ok, UInt<1>(0h0))
when _T_1675 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(legal_source, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1679 = asUInt(reset)
node _T_1680 = eq(_T_1679, UInt<1>(0h0))
when _T_1680 :
node _T_1681 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1683 = asUInt(reset)
node _T_1684 = eq(_T_1683, UInt<1>(0h0))
when _T_1684 :
node _T_1685 = eq(_T_1682, UInt<1>(0h0))
when _T_1685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116
node _T_1686 = eq(io.in.b.bits.mask, mask_1)
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(_T_1686, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117
node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1690 :
node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1693 = and(_T_1691, _T_1692)
node _T_1694 = or(UInt<1>(0h0), _T_1693)
node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1696 = cvt(_T_1695)
node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000)))
node _T_1698 = asSInt(_T_1697)
node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0)))
node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1701 = cvt(_T_1700)
node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000)))
node _T_1703 = asSInt(_T_1702)
node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0)))
node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1706 = cvt(_T_1705)
node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000)))
node _T_1708 = asSInt(_T_1707)
node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0)))
node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1711 = cvt(_T_1710)
node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000)))
node _T_1713 = asSInt(_T_1712)
node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0)))
node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1716 = cvt(_T_1715)
node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000)))
node _T_1718 = asSInt(_T_1717)
node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0)))
node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1721 = cvt(_T_1720)
node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000)))
node _T_1723 = asSInt(_T_1722)
node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0)))
node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1726 = cvt(_T_1725)
node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000)))
node _T_1728 = asSInt(_T_1727)
node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0)))
node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1731 = cvt(_T_1730)
node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000)))
node _T_1733 = asSInt(_T_1732)
node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0)))
node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1736 = cvt(_T_1735)
node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000)))
node _T_1738 = asSInt(_T_1737)
node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0)))
node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1741 = cvt(_T_1740)
node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000)))
node _T_1743 = asSInt(_T_1742)
node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0)))
node _T_1745 = or(_T_1699, _T_1704)
node _T_1746 = or(_T_1745, _T_1709)
node _T_1747 = or(_T_1746, _T_1714)
node _T_1748 = or(_T_1747, _T_1719)
node _T_1749 = or(_T_1748, _T_1724)
node _T_1750 = or(_T_1749, _T_1729)
node _T_1751 = or(_T_1750, _T_1734)
node _T_1752 = or(_T_1751, _T_1739)
node _T_1753 = or(_T_1752, _T_1744)
node _T_1754 = and(_T_1694, _T_1753)
node _T_1755 = or(UInt<1>(0h0), _T_1754)
node _T_1756 = and(UInt<1>(0h0), _T_1755)
node _T_1757 = asUInt(reset)
node _T_1758 = eq(_T_1757, UInt<1>(0h0))
when _T_1758 :
node _T_1759 = eq(_T_1756, UInt<1>(0h0))
when _T_1759 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(address_ok, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1763 = asUInt(reset)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
when _T_1764 :
node _T_1765 = eq(legal_source, UInt<1>(0h0))
when _T_1765 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1766 = asUInt(reset)
node _T_1767 = eq(_T_1766, UInt<1>(0h0))
when _T_1767 :
node _T_1768 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1768 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122
node _T_1773 = eq(io.in.b.bits.mask, mask_1)
node _T_1774 = asUInt(reset)
node _T_1775 = eq(_T_1774, UInt<1>(0h0))
when _T_1775 :
node _T_1776 = eq(_T_1773, UInt<1>(0h0))
when _T_1776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123
node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1777 :
node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1780 = and(_T_1778, _T_1779)
node _T_1781 = or(UInt<1>(0h0), _T_1780)
node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1783 = cvt(_T_1782)
node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000)))
node _T_1785 = asSInt(_T_1784)
node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0)))
node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1788 = cvt(_T_1787)
node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000)))
node _T_1790 = asSInt(_T_1789)
node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0)))
node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1793 = cvt(_T_1792)
node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000)))
node _T_1795 = asSInt(_T_1794)
node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0)))
node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1798 = cvt(_T_1797)
node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000)))
node _T_1800 = asSInt(_T_1799)
node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0)))
node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1803 = cvt(_T_1802)
node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000)))
node _T_1805 = asSInt(_T_1804)
node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0)))
node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1808 = cvt(_T_1807)
node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000)))
node _T_1810 = asSInt(_T_1809)
node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0)))
node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1813 = cvt(_T_1812)
node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000)))
node _T_1815 = asSInt(_T_1814)
node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0)))
node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1818 = cvt(_T_1817)
node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000)))
node _T_1820 = asSInt(_T_1819)
node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0)))
node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1823 = cvt(_T_1822)
node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000)))
node _T_1825 = asSInt(_T_1824)
node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0)))
node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1828 = cvt(_T_1827)
node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000)))
node _T_1830 = asSInt(_T_1829)
node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0)))
node _T_1832 = or(_T_1786, _T_1791)
node _T_1833 = or(_T_1832, _T_1796)
node _T_1834 = or(_T_1833, _T_1801)
node _T_1835 = or(_T_1834, _T_1806)
node _T_1836 = or(_T_1835, _T_1811)
node _T_1837 = or(_T_1836, _T_1816)
node _T_1838 = or(_T_1837, _T_1821)
node _T_1839 = or(_T_1838, _T_1826)
node _T_1840 = or(_T_1839, _T_1831)
node _T_1841 = and(_T_1781, _T_1840)
node _T_1842 = or(UInt<1>(0h0), _T_1841)
node _T_1843 = and(UInt<1>(0h0), _T_1842)
node _T_1844 = asUInt(reset)
node _T_1845 = eq(_T_1844, UInt<1>(0h0))
when _T_1845 :
node _T_1846 = eq(_T_1843, UInt<1>(0h0))
when _T_1846 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124
node _T_1847 = asUInt(reset)
node _T_1848 = eq(_T_1847, UInt<1>(0h0))
when _T_1848 :
node _T_1849 = eq(address_ok, UInt<1>(0h0))
when _T_1849 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1850 = asUInt(reset)
node _T_1851 = eq(_T_1850, UInt<1>(0h0))
when _T_1851 :
node _T_1852 = eq(legal_source, UInt<1>(0h0))
when _T_1852 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1853 = asUInt(reset)
node _T_1854 = eq(_T_1853, UInt<1>(0h0))
when _T_1854 :
node _T_1855 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1855 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1856 = eq(io.in.b.bits.mask, mask_1)
node _T_1857 = asUInt(reset)
node _T_1858 = eq(_T_1857, UInt<1>(0h0))
when _T_1858 :
node _T_1859 = eq(_T_1856, UInt<1>(0h0))
when _T_1859 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128
node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1861 = asUInt(reset)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
node _T_1863 = eq(_T_1860, UInt<1>(0h0))
when _T_1863 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_1865 = asUInt(reset)
node _T_1866 = eq(_T_1865, UInt<1>(0h0))
when _T_1866 :
node _T_1867 = eq(_T_1864, UInt<1>(0h0))
when _T_1867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130
node _source_ok_T_18 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_19 = shr(io.in.c.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<1>(0h0))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_18
connect _source_ok_WIRE_2[1], _source_ok_T_24
connect _source_ok_WIRE_2[2], _source_ok_T_25
node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_86 = cvt(_address_ok_T_85)
node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000)))
node _address_ok_T_88 = asSInt(_address_ok_T_87)
node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0)))
node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_91 = cvt(_address_ok_T_90)
node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000)))
node _address_ok_T_93 = asSInt(_address_ok_T_92)
node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0)))
node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_96 = cvt(_address_ok_T_95)
node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000)))
node _address_ok_T_98 = asSInt(_address_ok_T_97)
node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0)))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[12]
connect _address_ok_WIRE_1[0], _address_ok_T_74
connect _address_ok_WIRE_1[1], _address_ok_T_79
connect _address_ok_WIRE_1[2], _address_ok_T_84
connect _address_ok_WIRE_1[3], _address_ok_T_89
connect _address_ok_WIRE_1[4], _address_ok_T_94
connect _address_ok_WIRE_1[5], _address_ok_T_99
connect _address_ok_WIRE_1[6], _address_ok_T_104
connect _address_ok_WIRE_1[7], _address_ok_T_109
connect _address_ok_WIRE_1[8], _address_ok_T_114
connect _address_ok_WIRE_1[9], _address_ok_T_119
connect _address_ok_WIRE_1[10], _address_ok_T_124
connect _address_ok_WIRE_1[11], _address_ok_T_129
node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2])
node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3])
node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4])
node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5])
node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6])
node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7])
node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8])
node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9])
node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10])
node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11])
node _T_1868 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _T_1869 = eq(_T_1868, UInt<1>(0h0))
node _T_1870 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1871 = cvt(_T_1870)
node _T_1872 = and(_T_1871, asSInt(UInt<1>(0h0)))
node _T_1873 = asSInt(_T_1872)
node _T_1874 = eq(_T_1873, asSInt(UInt<1>(0h0)))
node _T_1875 = or(_T_1869, _T_1874)
node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_1876 = shr(io.in.c.bits.source, 2)
node _T_1877 = eq(_T_1876, UInt<1>(0h0))
node _T_1878 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_1879 = and(_T_1877, _T_1878)
node _T_1880 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_1881 = and(_T_1879, _T_1880)
node _T_1882 = eq(_T_1881, UInt<1>(0h0))
node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1884 = cvt(_T_1883)
node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0)))
node _T_1886 = asSInt(_T_1885)
node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0)))
node _T_1888 = or(_T_1882, _T_1887)
node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1890 = eq(_T_1889, UInt<1>(0h0))
node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1892 = cvt(_T_1891)
node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0)))
node _T_1894 = asSInt(_T_1893)
node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0)))
node _T_1896 = or(_T_1890, _T_1895)
node _T_1897 = and(_T_1875, _T_1888)
node _T_1898 = and(_T_1897, _T_1896)
node _T_1899 = asUInt(reset)
node _T_1900 = eq(_T_1899, UInt<1>(0h0))
when _T_1900 :
node _T_1901 = eq(_T_1898, UInt<1>(0h0))
when _T_1901 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131
node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_1902 :
node _T_1903 = asUInt(reset)
node _T_1904 = eq(_T_1903, UInt<1>(0h0))
when _T_1904 :
node _T_1905 = eq(address_ok_1, UInt<1>(0h0))
when _T_1905 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_1906 = asUInt(reset)
node _T_1907 = eq(_T_1906, UInt<1>(0h0))
when _T_1907 :
node _T_1908 = eq(source_ok_2, UInt<1>(0h0))
when _T_1908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1910 = asUInt(reset)
node _T_1911 = eq(_T_1910, UInt<1>(0h0))
when _T_1911 :
node _T_1912 = eq(_T_1909, UInt<1>(0h0))
when _T_1912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134
node _T_1913 = asUInt(reset)
node _T_1914 = eq(_T_1913, UInt<1>(0h0))
when _T_1914 :
node _T_1915 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1917 = asUInt(reset)
node _T_1918 = eq(_T_1917, UInt<1>(0h0))
when _T_1918 :
node _T_1919 = eq(_T_1916, UInt<1>(0h0))
when _T_1919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136
node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_1921 = asUInt(reset)
node _T_1922 = eq(_T_1921, UInt<1>(0h0))
when _T_1922 :
node _T_1923 = eq(_T_1920, UInt<1>(0h0))
when _T_1923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137
node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_1924 :
node _T_1925 = asUInt(reset)
node _T_1926 = eq(_T_1925, UInt<1>(0h0))
when _T_1926 :
node _T_1927 = eq(address_ok_1, UInt<1>(0h0))
when _T_1927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_1928 = asUInt(reset)
node _T_1929 = eq(_T_1928, UInt<1>(0h0))
when _T_1929 :
node _T_1930 = eq(source_ok_2, UInt<1>(0h0))
when _T_1930 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_1932 = asUInt(reset)
node _T_1933 = eq(_T_1932, UInt<1>(0h0))
when _T_1933 :
node _T_1934 = eq(_T_1931, UInt<1>(0h0))
when _T_1934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140
node _T_1935 = asUInt(reset)
node _T_1936 = eq(_T_1935, UInt<1>(0h0))
when _T_1936 :
node _T_1937 = eq(is_aligned_2, UInt<1>(0h0))
when _T_1937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_1939 = asUInt(reset)
node _T_1940 = eq(_T_1939, UInt<1>(0h0))
when _T_1940 :
node _T_1941 = eq(_T_1938, UInt<1>(0h0))
when _T_1941 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142
node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_1942 :
node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_1945 = and(_T_1943, _T_1944)
node _T_1946 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_1947 = shr(io.in.c.bits.source, 2)
node _T_1948 = eq(_T_1947, UInt<1>(0h0))
node _T_1949 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_1950 = and(_T_1948, _T_1949)
node _T_1951 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_1952 = and(_T_1950, _T_1951)
node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_1954 = or(_T_1946, _T_1952)
node _T_1955 = or(_T_1954, _T_1953)
node _T_1956 = and(_T_1945, _T_1955)
node _T_1957 = or(UInt<1>(0h0), _T_1956)
node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_1960 = cvt(_T_1959)
node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000)))
node _T_1962 = asSInt(_T_1961)
node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0)))
node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_1965 = cvt(_T_1964)
node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000)))
node _T_1967 = asSInt(_T_1966)
node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0)))
node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_1970 = cvt(_T_1969)
node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000)))
node _T_1972 = asSInt(_T_1971)
node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0)))
node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_1975 = cvt(_T_1974)
node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000)))
node _T_1977 = asSInt(_T_1976)
node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0)))
node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_1980 = cvt(_T_1979)
node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000)))
node _T_1982 = asSInt(_T_1981)
node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0)))
node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_1985 = cvt(_T_1984)
node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000)))
node _T_1987 = asSInt(_T_1986)
node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0)))
node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_1990 = cvt(_T_1989)
node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000)))
node _T_1992 = asSInt(_T_1991)
node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0)))
node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_1995 = cvt(_T_1994)
node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000)))
node _T_1997 = asSInt(_T_1996)
node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0)))
node _T_1999 = or(_T_1963, _T_1968)
node _T_2000 = or(_T_1999, _T_1973)
node _T_2001 = or(_T_2000, _T_1978)
node _T_2002 = or(_T_2001, _T_1983)
node _T_2003 = or(_T_2002, _T_1988)
node _T_2004 = or(_T_2003, _T_1993)
node _T_2005 = or(_T_2004, _T_1998)
node _T_2006 = and(_T_1958, _T_2005)
node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2008 = or(UInt<1>(0h0), _T_2007)
node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2010 = cvt(_T_2009)
node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000)))
node _T_2012 = asSInt(_T_2011)
node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0)))
node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2015 = cvt(_T_2014)
node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000)))
node _T_2017 = asSInt(_T_2016)
node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0)))
node _T_2019 = or(_T_2013, _T_2018)
node _T_2020 = and(_T_2008, _T_2019)
node _T_2021 = or(UInt<1>(0h0), _T_2006)
node _T_2022 = or(_T_2021, _T_2020)
node _T_2023 = and(_T_1957, _T_2022)
node _T_2024 = asUInt(reset)
node _T_2025 = eq(_T_2024, UInt<1>(0h0))
when _T_2025 :
node _T_2026 = eq(_T_2023, UInt<1>(0h0))
when _T_2026 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143
node _T_2027 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_2028 = shr(io.in.c.bits.source, 2)
node _T_2029 = eq(_T_2028, UInt<1>(0h0))
node _T_2030 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_2031 = and(_T_2029, _T_2030)
node _T_2032 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_2033 = and(_T_2031, _T_2032)
node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_2027
connect _WIRE_6[1], _T_2033
connect _WIRE_6[2], _T_2034
node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2036 = mux(_WIRE_6[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2037 = mux(_WIRE_6[1], _T_2035, UInt<1>(0h0))
node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2039 = or(_T_2036, _T_2037)
node _T_2040 = or(_T_2039, _T_2038)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2040
node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2043 = and(_T_2041, _T_2042)
node _T_2044 = or(UInt<1>(0h0), _T_2043)
node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2046 = cvt(_T_2045)
node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000)))
node _T_2048 = asSInt(_T_2047)
node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0)))
node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2051 = cvt(_T_2050)
node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000)))
node _T_2053 = asSInt(_T_2052)
node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0)))
node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2056 = cvt(_T_2055)
node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000)))
node _T_2058 = asSInt(_T_2057)
node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0)))
node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2061 = cvt(_T_2060)
node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000)))
node _T_2063 = asSInt(_T_2062)
node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0)))
node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2066 = cvt(_T_2065)
node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000)))
node _T_2068 = asSInt(_T_2067)
node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0)))
node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2071 = cvt(_T_2070)
node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000)))
node _T_2073 = asSInt(_T_2072)
node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0)))
node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2076 = cvt(_T_2075)
node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000)))
node _T_2078 = asSInt(_T_2077)
node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0)))
node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2081 = cvt(_T_2080)
node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000)))
node _T_2083 = asSInt(_T_2082)
node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0)))
node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2086 = cvt(_T_2085)
node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000)))
node _T_2088 = asSInt(_T_2087)
node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0)))
node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2091 = cvt(_T_2090)
node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000)))
node _T_2093 = asSInt(_T_2092)
node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0)))
node _T_2095 = or(_T_2049, _T_2054)
node _T_2096 = or(_T_2095, _T_2059)
node _T_2097 = or(_T_2096, _T_2064)
node _T_2098 = or(_T_2097, _T_2069)
node _T_2099 = or(_T_2098, _T_2074)
node _T_2100 = or(_T_2099, _T_2079)
node _T_2101 = or(_T_2100, _T_2084)
node _T_2102 = or(_T_2101, _T_2089)
node _T_2103 = or(_T_2102, _T_2094)
node _T_2104 = and(_T_2044, _T_2103)
node _T_2105 = or(UInt<1>(0h0), _T_2104)
node _T_2106 = and(_WIRE_7, _T_2105)
node _T_2107 = asUInt(reset)
node _T_2108 = eq(_T_2107, UInt<1>(0h0))
when _T_2108 :
node _T_2109 = eq(_T_2106, UInt<1>(0h0))
when _T_2109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144
node _T_2110 = asUInt(reset)
node _T_2111 = eq(_T_2110, UInt<1>(0h0))
when _T_2111 :
node _T_2112 = eq(source_ok_2, UInt<1>(0h0))
when _T_2112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2114 = asUInt(reset)
node _T_2115 = eq(_T_2114, UInt<1>(0h0))
when _T_2115 :
node _T_2116 = eq(_T_2113, UInt<1>(0h0))
when _T_2116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146
node _T_2117 = asUInt(reset)
node _T_2118 = eq(_T_2117, UInt<1>(0h0))
when _T_2118 :
node _T_2119 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2121 = asUInt(reset)
node _T_2122 = eq(_T_2121, UInt<1>(0h0))
when _T_2122 :
node _T_2123 = eq(_T_2120, UInt<1>(0h0))
when _T_2123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148
node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2125 = asUInt(reset)
node _T_2126 = eq(_T_2125, UInt<1>(0h0))
when _T_2126 :
node _T_2127 = eq(_T_2124, UInt<1>(0h0))
when _T_2127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149
node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2128 :
node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2131 = and(_T_2129, _T_2130)
node _T_2132 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_2133 = shr(io.in.c.bits.source, 2)
node _T_2134 = eq(_T_2133, UInt<1>(0h0))
node _T_2135 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_2136 = and(_T_2134, _T_2135)
node _T_2137 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_2138 = and(_T_2136, _T_2137)
node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4))
node _T_2140 = or(_T_2132, _T_2138)
node _T_2141 = or(_T_2140, _T_2139)
node _T_2142 = and(_T_2131, _T_2141)
node _T_2143 = or(UInt<1>(0h0), _T_2142)
node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2146 = cvt(_T_2145)
node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000)))
node _T_2148 = asSInt(_T_2147)
node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0)))
node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2156 = cvt(_T_2155)
node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000)))
node _T_2158 = asSInt(_T_2157)
node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0)))
node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2161 = cvt(_T_2160)
node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000)))
node _T_2163 = asSInt(_T_2162)
node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0)))
node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2166 = cvt(_T_2165)
node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000)))
node _T_2168 = asSInt(_T_2167)
node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0)))
node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2171 = cvt(_T_2170)
node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000)))
node _T_2173 = asSInt(_T_2172)
node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0)))
node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2176 = cvt(_T_2175)
node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000)))
node _T_2178 = asSInt(_T_2177)
node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0)))
node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2181 = cvt(_T_2180)
node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000)))
node _T_2183 = asSInt(_T_2182)
node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0)))
node _T_2185 = or(_T_2149, _T_2154)
node _T_2186 = or(_T_2185, _T_2159)
node _T_2187 = or(_T_2186, _T_2164)
node _T_2188 = or(_T_2187, _T_2169)
node _T_2189 = or(_T_2188, _T_2174)
node _T_2190 = or(_T_2189, _T_2179)
node _T_2191 = or(_T_2190, _T_2184)
node _T_2192 = and(_T_2144, _T_2191)
node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2194 = or(UInt<1>(0h0), _T_2193)
node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2196 = cvt(_T_2195)
node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000)))
node _T_2198 = asSInt(_T_2197)
node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0)))
node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2201 = cvt(_T_2200)
node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000)))
node _T_2203 = asSInt(_T_2202)
node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0)))
node _T_2205 = or(_T_2199, _T_2204)
node _T_2206 = and(_T_2194, _T_2205)
node _T_2207 = or(UInt<1>(0h0), _T_2192)
node _T_2208 = or(_T_2207, _T_2206)
node _T_2209 = and(_T_2143, _T_2208)
node _T_2210 = asUInt(reset)
node _T_2211 = eq(_T_2210, UInt<1>(0h0))
when _T_2211 :
node _T_2212 = eq(_T_2209, UInt<1>(0h0))
when _T_2212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150
node _T_2213 = eq(io.in.c.bits.source, UInt<4>(0h8))
node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_2214 = shr(io.in.c.bits.source, 2)
node _T_2215 = eq(_T_2214, UInt<1>(0h0))
node _T_2216 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_2217 = and(_T_2215, _T_2216)
node _T_2218 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_2219 = and(_T_2217, _T_2218)
node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2213
connect _WIRE_8[1], _T_2219
connect _WIRE_8[2], _T_2220
node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2222 = mux(_WIRE_8[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_2223 = mux(_WIRE_8[1], _T_2221, UInt<1>(0h0))
node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2225 = or(_T_2222, _T_2223)
node _T_2226 = or(_T_2225, _T_2224)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2226
node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2229 = and(_T_2227, _T_2228)
node _T_2230 = or(UInt<1>(0h0), _T_2229)
node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2232 = cvt(_T_2231)
node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000)))
node _T_2234 = asSInt(_T_2233)
node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0)))
node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2237 = cvt(_T_2236)
node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000)))
node _T_2239 = asSInt(_T_2238)
node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0)))
node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2242 = cvt(_T_2241)
node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000)))
node _T_2244 = asSInt(_T_2243)
node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0)))
node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2247 = cvt(_T_2246)
node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000)))
node _T_2249 = asSInt(_T_2248)
node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0)))
node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2252 = cvt(_T_2251)
node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000)))
node _T_2254 = asSInt(_T_2253)
node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0)))
node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2257 = cvt(_T_2256)
node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000)))
node _T_2259 = asSInt(_T_2258)
node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0)))
node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2262 = cvt(_T_2261)
node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000)))
node _T_2264 = asSInt(_T_2263)
node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0)))
node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2267 = cvt(_T_2266)
node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000)))
node _T_2269 = asSInt(_T_2268)
node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0)))
node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2272 = cvt(_T_2271)
node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000)))
node _T_2274 = asSInt(_T_2273)
node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0)))
node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2277 = cvt(_T_2276)
node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000)))
node _T_2279 = asSInt(_T_2278)
node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0)))
node _T_2281 = or(_T_2235, _T_2240)
node _T_2282 = or(_T_2281, _T_2245)
node _T_2283 = or(_T_2282, _T_2250)
node _T_2284 = or(_T_2283, _T_2255)
node _T_2285 = or(_T_2284, _T_2260)
node _T_2286 = or(_T_2285, _T_2265)
node _T_2287 = or(_T_2286, _T_2270)
node _T_2288 = or(_T_2287, _T_2275)
node _T_2289 = or(_T_2288, _T_2280)
node _T_2290 = and(_T_2230, _T_2289)
node _T_2291 = or(UInt<1>(0h0), _T_2290)
node _T_2292 = and(_WIRE_9, _T_2291)
node _T_2293 = asUInt(reset)
node _T_2294 = eq(_T_2293, UInt<1>(0h0))
when _T_2294 :
node _T_2295 = eq(_T_2292, UInt<1>(0h0))
when _T_2295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151
node _T_2296 = asUInt(reset)
node _T_2297 = eq(_T_2296, UInt<1>(0h0))
when _T_2297 :
node _T_2298 = eq(source_ok_2, UInt<1>(0h0))
when _T_2298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2300 = asUInt(reset)
node _T_2301 = eq(_T_2300, UInt<1>(0h0))
when _T_2301 :
node _T_2302 = eq(_T_2299, UInt<1>(0h0))
when _T_2302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153
node _T_2303 = asUInt(reset)
node _T_2304 = eq(_T_2303, UInt<1>(0h0))
when _T_2304 :
node _T_2305 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2307 = asUInt(reset)
node _T_2308 = eq(_T_2307, UInt<1>(0h0))
when _T_2308 :
node _T_2309 = eq(_T_2306, UInt<1>(0h0))
when _T_2309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155
node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2310 :
node _T_2311 = asUInt(reset)
node _T_2312 = eq(_T_2311, UInt<1>(0h0))
when _T_2312 :
node _T_2313 = eq(address_ok_1, UInt<1>(0h0))
when _T_2313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2314 = asUInt(reset)
node _T_2315 = eq(_T_2314, UInt<1>(0h0))
when _T_2315 :
node _T_2316 = eq(source_ok_2, UInt<1>(0h0))
when _T_2316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2317 = asUInt(reset)
node _T_2318 = eq(_T_2317, UInt<1>(0h0))
when _T_2318 :
node _T_2319 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2321 = asUInt(reset)
node _T_2322 = eq(_T_2321, UInt<1>(0h0))
when _T_2322 :
node _T_2323 = eq(_T_2320, UInt<1>(0h0))
when _T_2323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159
node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2325 = asUInt(reset)
node _T_2326 = eq(_T_2325, UInt<1>(0h0))
when _T_2326 :
node _T_2327 = eq(_T_2324, UInt<1>(0h0))
when _T_2327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160
node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2328 :
node _T_2329 = asUInt(reset)
node _T_2330 = eq(_T_2329, UInt<1>(0h0))
when _T_2330 :
node _T_2331 = eq(address_ok_1, UInt<1>(0h0))
when _T_2331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2332 = asUInt(reset)
node _T_2333 = eq(_T_2332, UInt<1>(0h0))
when _T_2333 :
node _T_2334 = eq(source_ok_2, UInt<1>(0h0))
when _T_2334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2335 = asUInt(reset)
node _T_2336 = eq(_T_2335, UInt<1>(0h0))
when _T_2336 :
node _T_2337 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2339 = asUInt(reset)
node _T_2340 = eq(_T_2339, UInt<1>(0h0))
when _T_2340 :
node _T_2341 = eq(_T_2338, UInt<1>(0h0))
when _T_2341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164
node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2342 :
node _T_2343 = asUInt(reset)
node _T_2344 = eq(_T_2343, UInt<1>(0h0))
when _T_2344 :
node _T_2345 = eq(address_ok_1, UInt<1>(0h0))
when _T_2345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2346 = asUInt(reset)
node _T_2347 = eq(_T_2346, UInt<1>(0h0))
when _T_2347 :
node _T_2348 = eq(source_ok_2, UInt<1>(0h0))
when _T_2348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2349 = asUInt(reset)
node _T_2350 = eq(_T_2349, UInt<1>(0h0))
when _T_2350 :
node _T_2351 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2353 = asUInt(reset)
node _T_2354 = eq(_T_2353, UInt<1>(0h0))
when _T_2354 :
node _T_2355 = eq(_T_2352, UInt<1>(0h0))
when _T_2355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168
node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2357 = asUInt(reset)
node _T_2358 = eq(_T_2357, UInt<1>(0h0))
when _T_2358 :
node _T_2359 = eq(_T_2356, UInt<1>(0h0))
when _T_2359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2360 = asUInt(reset)
node _T_2361 = eq(_T_2360, UInt<1>(0h0))
when _T_2361 :
node _T_2362 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2363 = eq(a_first, UInt<1>(0h0))
node _T_2364 = and(io.in.a.valid, _T_2363)
when _T_2364 :
node _T_2365 = eq(io.in.a.bits.opcode, opcode)
node _T_2366 = asUInt(reset)
node _T_2367 = eq(_T_2366, UInt<1>(0h0))
when _T_2367 :
node _T_2368 = eq(_T_2365, UInt<1>(0h0))
when _T_2368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171
node _T_2369 = eq(io.in.a.bits.param, param)
node _T_2370 = asUInt(reset)
node _T_2371 = eq(_T_2370, UInt<1>(0h0))
when _T_2371 :
node _T_2372 = eq(_T_2369, UInt<1>(0h0))
when _T_2372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172
node _T_2373 = eq(io.in.a.bits.size, size)
node _T_2374 = asUInt(reset)
node _T_2375 = eq(_T_2374, UInt<1>(0h0))
when _T_2375 :
node _T_2376 = eq(_T_2373, UInt<1>(0h0))
when _T_2376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173
node _T_2377 = eq(io.in.a.bits.source, source)
node _T_2378 = asUInt(reset)
node _T_2379 = eq(_T_2378, UInt<1>(0h0))
when _T_2379 :
node _T_2380 = eq(_T_2377, UInt<1>(0h0))
when _T_2380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174
node _T_2381 = eq(io.in.a.bits.address, address)
node _T_2382 = asUInt(reset)
node _T_2383 = eq(_T_2382, UInt<1>(0h0))
when _T_2383 :
node _T_2384 = eq(_T_2381, UInt<1>(0h0))
when _T_2384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175
node _T_2385 = and(io.in.a.ready, io.in.a.valid)
node _T_2386 = and(_T_2385, a_first)
when _T_2386 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2387 = eq(d_first, UInt<1>(0h0))
node _T_2388 = and(io.in.d.valid, _T_2387)
when _T_2388 :
node _T_2389 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2390 = asUInt(reset)
node _T_2391 = eq(_T_2390, UInt<1>(0h0))
when _T_2391 :
node _T_2392 = eq(_T_2389, UInt<1>(0h0))
when _T_2392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176
node _T_2393 = eq(io.in.d.bits.param, param_1)
node _T_2394 = asUInt(reset)
node _T_2395 = eq(_T_2394, UInt<1>(0h0))
when _T_2395 :
node _T_2396 = eq(_T_2393, UInt<1>(0h0))
when _T_2396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177
node _T_2397 = eq(io.in.d.bits.size, size_1)
node _T_2398 = asUInt(reset)
node _T_2399 = eq(_T_2398, UInt<1>(0h0))
when _T_2399 :
node _T_2400 = eq(_T_2397, UInt<1>(0h0))
when _T_2400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178
node _T_2401 = eq(io.in.d.bits.source, source_1)
node _T_2402 = asUInt(reset)
node _T_2403 = eq(_T_2402, UInt<1>(0h0))
when _T_2403 :
node _T_2404 = eq(_T_2401, UInt<1>(0h0))
when _T_2404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179
node _T_2405 = eq(io.in.d.bits.sink, sink)
node _T_2406 = asUInt(reset)
node _T_2407 = eq(_T_2406, UInt<1>(0h0))
when _T_2407 :
node _T_2408 = eq(_T_2405, UInt<1>(0h0))
when _T_2408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180
node _T_2409 = eq(io.in.d.bits.denied, denied)
node _T_2410 = asUInt(reset)
node _T_2411 = eq(_T_2410, UInt<1>(0h0))
when _T_2411 :
node _T_2412 = eq(_T_2409, UInt<1>(0h0))
when _T_2412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181
node _T_2413 = and(io.in.d.ready, io.in.d.valid)
node _T_2414 = and(_T_2413, d_first)
when _T_2414 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2415 = eq(b_first, UInt<1>(0h0))
node _T_2416 = and(io.in.b.valid, _T_2415)
when _T_2416 :
node _T_2417 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2418 = asUInt(reset)
node _T_2419 = eq(_T_2418, UInt<1>(0h0))
when _T_2419 :
node _T_2420 = eq(_T_2417, UInt<1>(0h0))
when _T_2420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182
node _T_2421 = eq(io.in.b.bits.param, param_2)
node _T_2422 = asUInt(reset)
node _T_2423 = eq(_T_2422, UInt<1>(0h0))
when _T_2423 :
node _T_2424 = eq(_T_2421, UInt<1>(0h0))
when _T_2424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183
node _T_2425 = eq(io.in.b.bits.size, size_2)
node _T_2426 = asUInt(reset)
node _T_2427 = eq(_T_2426, UInt<1>(0h0))
when _T_2427 :
node _T_2428 = eq(_T_2425, UInt<1>(0h0))
when _T_2428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184
node _T_2429 = eq(io.in.b.bits.source, source_2)
node _T_2430 = asUInt(reset)
node _T_2431 = eq(_T_2430, UInt<1>(0h0))
when _T_2431 :
node _T_2432 = eq(_T_2429, UInt<1>(0h0))
when _T_2432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185
node _T_2433 = eq(io.in.b.bits.address, address_1)
node _T_2434 = asUInt(reset)
node _T_2435 = eq(_T_2434, UInt<1>(0h0))
when _T_2435 :
node _T_2436 = eq(_T_2433, UInt<1>(0h0))
when _T_2436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186
node _T_2437 = and(io.in.b.ready, io.in.b.valid)
node _T_2438 = and(_T_2437, b_first)
when _T_2438 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2439 = eq(c_first, UInt<1>(0h0))
node _T_2440 = and(io.in.c.valid, _T_2439)
when _T_2440 :
node _T_2441 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2442 = asUInt(reset)
node _T_2443 = eq(_T_2442, UInt<1>(0h0))
when _T_2443 :
node _T_2444 = eq(_T_2441, UInt<1>(0h0))
when _T_2444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187
node _T_2445 = eq(io.in.c.bits.param, param_3)
node _T_2446 = asUInt(reset)
node _T_2447 = eq(_T_2446, UInt<1>(0h0))
when _T_2447 :
node _T_2448 = eq(_T_2445, UInt<1>(0h0))
when _T_2448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188
node _T_2449 = eq(io.in.c.bits.size, size_3)
node _T_2450 = asUInt(reset)
node _T_2451 = eq(_T_2450, UInt<1>(0h0))
when _T_2451 :
node _T_2452 = eq(_T_2449, UInt<1>(0h0))
when _T_2452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189
node _T_2453 = eq(io.in.c.bits.source, source_3)
node _T_2454 = asUInt(reset)
node _T_2455 = eq(_T_2454, UInt<1>(0h0))
when _T_2455 :
node _T_2456 = eq(_T_2453, UInt<1>(0h0))
when _T_2456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190
node _T_2457 = eq(io.in.c.bits.address, address_2)
node _T_2458 = asUInt(reset)
node _T_2459 = eq(_T_2458, UInt<1>(0h0))
when _T_2459 :
node _T_2460 = eq(_T_2457, UInt<1>(0h0))
when _T_2460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191
node _T_2461 = and(io.in.c.ready, io.in.c.valid)
node _T_2462 = and(_T_2461, c_first)
when _T_2462 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0)
regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0)
regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<9>
connect a_set, UInt<9>(0h0)
wire a_set_wo_ready : UInt<9>
connect a_set_wo_ready, UInt<9>(0h0)
wire a_opcodes_set : UInt<36>
connect a_opcodes_set, UInt<36>(0h0)
wire a_sizes_set : UInt<72>
connect a_sizes_set, UInt<72>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2463 = and(io.in.a.valid, a_first_1)
node _T_2464 = and(_T_2463, UInt<1>(0h1))
when _T_2464 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2465 = and(io.in.a.ready, io.in.a.valid)
node _T_2466 = and(_T_2465, a_first_1)
node _T_2467 = and(_T_2466, UInt<1>(0h1))
when _T_2467 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2468 = dshr(inflight, io.in.a.bits.source)
node _T_2469 = bits(_T_2468, 0, 0)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
node _T_2471 = asUInt(reset)
node _T_2472 = eq(_T_2471, UInt<1>(0h0))
when _T_2472 :
node _T_2473 = eq(_T_2470, UInt<1>(0h0))
when _T_2473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<9>
connect d_clr, UInt<9>(0h0)
wire d_clr_wo_ready : UInt<9>
connect d_clr_wo_ready, UInt<9>(0h0)
wire d_opcodes_clr : UInt<36>
connect d_opcodes_clr, UInt<36>(0h0)
wire d_sizes_clr : UInt<72>
connect d_sizes_clr, UInt<72>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2474 = and(io.in.d.valid, d_first_1)
node _T_2475 = and(_T_2474, UInt<1>(0h1))
node _T_2476 = eq(d_release_ack, UInt<1>(0h0))
node _T_2477 = and(_T_2475, _T_2476)
when _T_2477 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2478 = and(io.in.d.ready, io.in.d.valid)
node _T_2479 = and(_T_2478, d_first_1)
node _T_2480 = and(_T_2479, UInt<1>(0h1))
node _T_2481 = eq(d_release_ack, UInt<1>(0h0))
node _T_2482 = and(_T_2480, _T_2481)
when _T_2482 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2483 = and(io.in.d.valid, d_first_1)
node _T_2484 = and(_T_2483, UInt<1>(0h1))
node _T_2485 = eq(d_release_ack, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2487 = dshr(inflight, io.in.d.bits.source)
node _T_2488 = bits(_T_2487, 0, 0)
node _T_2489 = or(_T_2488, same_cycle_resp)
node _T_2490 = asUInt(reset)
node _T_2491 = eq(_T_2490, UInt<1>(0h0))
when _T_2491 :
node _T_2492 = eq(_T_2489, UInt<1>(0h0))
when _T_2492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2495 = or(_T_2493, _T_2494)
node _T_2496 = asUInt(reset)
node _T_2497 = eq(_T_2496, UInt<1>(0h0))
when _T_2497 :
node _T_2498 = eq(_T_2495, UInt<1>(0h0))
when _T_2498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194
node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2500 = asUInt(reset)
node _T_2501 = eq(_T_2500, UInt<1>(0h0))
when _T_2501 :
node _T_2502 = eq(_T_2499, UInt<1>(0h0))
when _T_2502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195
else :
node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2505 = or(_T_2503, _T_2504)
node _T_2506 = asUInt(reset)
node _T_2507 = eq(_T_2506, UInt<1>(0h0))
when _T_2507 :
node _T_2508 = eq(_T_2505, UInt<1>(0h0))
when _T_2508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196
node _T_2509 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2510 = asUInt(reset)
node _T_2511 = eq(_T_2510, UInt<1>(0h0))
when _T_2511 :
node _T_2512 = eq(_T_2509, UInt<1>(0h0))
when _T_2512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197
node _T_2513 = and(io.in.d.valid, d_first_1)
node _T_2514 = and(_T_2513, a_first_1)
node _T_2515 = and(_T_2514, io.in.a.valid)
node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2517 = and(_T_2515, _T_2516)
node _T_2518 = eq(d_release_ack, UInt<1>(0h0))
node _T_2519 = and(_T_2517, _T_2518)
when _T_2519 :
node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2521 = or(_T_2520, io.in.a.ready)
node _T_2522 = asUInt(reset)
node _T_2523 = eq(_T_2522, UInt<1>(0h0))
when _T_2523 :
node _T_2524 = eq(_T_2521, UInt<1>(0h0))
when _T_2524 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198
node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2526 = orr(a_set_wo_ready)
node _T_2527 = eq(_T_2526, UInt<1>(0h0))
node _T_2528 = or(_T_2525, _T_2527)
node _T_2529 = asUInt(reset)
node _T_2530 = eq(_T_2529, UInt<1>(0h0))
when _T_2530 :
node _T_2531 = eq(_T_2528, UInt<1>(0h0))
when _T_2531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_84
node _T_2532 = orr(inflight)
node _T_2533 = eq(_T_2532, UInt<1>(0h0))
node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2535 = or(_T_2533, _T_2534)
node _T_2536 = lt(watchdog, plusarg_reader.out)
node _T_2537 = or(_T_2535, _T_2536)
node _T_2538 = asUInt(reset)
node _T_2539 = eq(_T_2538, UInt<1>(0h0))
when _T_2539 :
node _T_2540 = eq(_T_2537, UInt<1>(0h0))
when _T_2540 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2541 = and(io.in.a.ready, io.in.a.valid)
node _T_2542 = and(io.in.d.ready, io.in.d.valid)
node _T_2543 = or(_T_2541, _T_2542)
when _T_2543 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0)
regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0)
regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<9>
connect c_set, UInt<9>(0h0)
wire c_set_wo_ready : UInt<9>
connect c_set_wo_ready, UInt<9>(0h0)
wire c_opcodes_set : UInt<36>
connect c_opcodes_set, UInt<36>(0h0)
wire c_sizes_set : UInt<72>
connect c_sizes_set, UInt<72>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2544 = and(io.in.c.valid, c_first_1)
node _T_2545 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2546 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2547 = and(_T_2545, _T_2546)
node _T_2548 = and(_T_2544, _T_2547)
when _T_2548 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2549 = and(io.in.c.ready, io.in.c.valid)
node _T_2550 = and(_T_2549, c_first_1)
node _T_2551 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2552 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2553 = and(_T_2551, _T_2552)
node _T_2554 = and(_T_2550, _T_2553)
when _T_2554 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2555 = dshr(inflight_1, io.in.c.bits.source)
node _T_2556 = bits(_T_2555, 0, 0)
node _T_2557 = eq(_T_2556, UInt<1>(0h0))
node _T_2558 = asUInt(reset)
node _T_2559 = eq(_T_2558, UInt<1>(0h0))
when _T_2559 :
node _T_2560 = eq(_T_2557, UInt<1>(0h0))
when _T_2560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<9>
connect d_clr_1, UInt<9>(0h0)
wire d_clr_wo_ready_1 : UInt<9>
connect d_clr_wo_ready_1, UInt<9>(0h0)
wire d_opcodes_clr_1 : UInt<36>
connect d_opcodes_clr_1, UInt<36>(0h0)
wire d_sizes_clr_1 : UInt<72>
connect d_sizes_clr_1, UInt<72>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2561 = and(io.in.d.valid, d_first_2)
node _T_2562 = and(_T_2561, UInt<1>(0h1))
node _T_2563 = and(_T_2562, d_release_ack_1)
when _T_2563 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2564 = and(io.in.d.ready, io.in.d.valid)
node _T_2565 = and(_T_2564, d_first_2)
node _T_2566 = and(_T_2565, UInt<1>(0h1))
node _T_2567 = and(_T_2566, d_release_ack_1)
when _T_2567 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2568 = and(io.in.d.valid, d_first_2)
node _T_2569 = and(_T_2568, UInt<1>(0h1))
node _T_2570 = and(_T_2569, d_release_ack_1)
when _T_2570 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2571 = dshr(inflight_1, io.in.d.bits.source)
node _T_2572 = bits(_T_2571, 0, 0)
node _T_2573 = or(_T_2572, same_cycle_resp_1)
node _T_2574 = asUInt(reset)
node _T_2575 = eq(_T_2574, UInt<1>(0h0))
when _T_2575 :
node _T_2576 = eq(_T_2573, UInt<1>(0h0))
when _T_2576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2578 = asUInt(reset)
node _T_2579 = eq(_T_2578, UInt<1>(0h0))
when _T_2579 :
node _T_2580 = eq(_T_2577, UInt<1>(0h0))
when _T_2580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203
else :
node _T_2581 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2582 = asUInt(reset)
node _T_2583 = eq(_T_2582, UInt<1>(0h0))
when _T_2583 :
node _T_2584 = eq(_T_2581, UInt<1>(0h0))
when _T_2584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204
node _T_2585 = and(io.in.d.valid, d_first_2)
node _T_2586 = and(_T_2585, c_first_1)
node _T_2587 = and(_T_2586, io.in.c.valid)
node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2589 = and(_T_2587, _T_2588)
node _T_2590 = and(_T_2589, d_release_ack_1)
node _T_2591 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2592 = and(_T_2590, _T_2591)
when _T_2592 :
node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2594 = or(_T_2593, io.in.c.ready)
node _T_2595 = asUInt(reset)
node _T_2596 = eq(_T_2595, UInt<1>(0h0))
when _T_2596 :
node _T_2597 = eq(_T_2594, UInt<1>(0h0))
when _T_2597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205
node _T_2598 = orr(c_set_wo_ready)
when _T_2598 :
node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2600 = asUInt(reset)
node _T_2601 = eq(_T_2600, UInt<1>(0h0))
when _T_2601 :
node _T_2602 = eq(_T_2599, UInt<1>(0h0))
when _T_2602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_85
node _T_2603 = orr(inflight_1)
node _T_2604 = eq(_T_2603, UInt<1>(0h0))
node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2606 = or(_T_2604, _T_2605)
node _T_2607 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2608 = or(_T_2606, _T_2607)
node _T_2609 = asUInt(reset)
node _T_2610 = eq(_T_2609, UInt<1>(0h0))
when _T_2610 :
node _T_2611 = eq(_T_2608, UInt<1>(0h0))
when _T_2611 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2612 = and(io.in.c.ready, io.in.c.valid)
node _T_2613 = and(io.in.d.ready, io.in.d.valid)
node _T_2614 = or(_T_2612, _T_2613)
when _T_2614 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2615 = and(io.in.d.ready, io.in.d.valid)
node _T_2616 = and(_T_2615, d_first_3)
node _T_2617 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2618 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2619 = eq(_T_2618, UInt<1>(0h0))
node _T_2620 = and(_T_2617, _T_2619)
node _T_2621 = and(_T_2616, _T_2620)
when _T_2621 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2622 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2623 = bits(_T_2622, 0, 0)
node _T_2624 = eq(_T_2623, UInt<1>(0h0))
node _T_2625 = asUInt(reset)
node _T_2626 = eq(_T_2625, UInt<1>(0h0))
when _T_2626 :
node _T_2627 = eq(_T_2624, UInt<1>(0h0))
when _T_2627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2628 = and(io.in.e.ready, io.in.e.valid)
node _T_2629 = and(_T_2628, UInt<1>(0h1))
node _T_2630 = and(_T_2629, UInt<1>(0h1))
when _T_2630 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2631 = or(d_set, inflight_2)
node _T_2632 = dshr(_T_2631, io.in.e.bits.sink)
node _T_2633 = bits(_T_2632, 0, 0)
node _T_2634 = asUInt(reset)
node _T_2635 = eq(_T_2634, UInt<1>(0h0))
when _T_2635 :
node _T_2636 = eq(_T_2633, UInt<1>(0h0))
when _T_2636 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_42( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7]
wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7]
wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7]
wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_12 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31]
wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire b_first_last = 1'h1; // @[Edges.scala:232:33]
wire _legal_source_T_9 = 1'h0; // @[Mux.scala:30:73]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_1 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31]
wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_9 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_9; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_10 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_11 = _source_ok_T_10 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_13 = _source_ok_T_11; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31]
wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31]
wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _legal_source_T = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _legal_source_T_1 = io_in_b_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h4; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46]
wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46]
wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40]
wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46]
wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40]
wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46]
wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40]
wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46]
wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46]
wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40]
wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46]
wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40]
wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46]
wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40]
wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46]
wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40]
wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46]
wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40]
wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46]
wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46]
wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40]
wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64]
wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71]
assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71]
wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71]
assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46]
wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10]
wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10]
wire _legal_source_WIRE_0 = _legal_source_T; // @[Parameters.scala:1138:31]
wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire _legal_source_T_2 = _legal_source_T_1 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _legal_source_T_4 = _legal_source_T_2; // @[Parameters.scala:54:{32,67}]
wire _legal_source_T_6 = _legal_source_T_4; // @[Parameters.scala:54:67, :56:48]
wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31]
wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31]
wire [3:0] _legal_source_T_8 = {_legal_source_WIRE_0, 3'h0}; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_11 = _legal_source_T_8; // @[Mux.scala:30:73]
wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73]
wire [3:0] _legal_source_T_12 = {_legal_source_T_11[3], _legal_source_T_11[2:0] | _legal_source_T_10}; // @[Mux.scala:30:73]
wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73]
wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_18 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_0 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_19 = io_in_c_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_20 = _source_ok_T_19 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h4; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71]
assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71]
assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71]
wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46]
wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}]
wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46]
wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46]
wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40]
wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46]
wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40]
wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46]
wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40]
wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46]
wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46]
wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40]
wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46]
wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40]
wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46]
wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40]
wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46]
wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40]
wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46]
wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40]
wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7]
wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46]
wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40]
wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7]
wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46]
wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40]
wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64]
wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64]
wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35]
wire _d_first_T_3; // @[Decoupled.scala:51:35]
assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35]
wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35]
wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [3:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35]
wire _c_first_T; // @[Decoupled.scala:51:35]
assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35]
wire _c_first_T_1; // @[Decoupled.scala:51:35]
assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35]
wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [3:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [8:0] inflight; // @[Monitor.scala:614:27]
reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [71:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [8:0] a_set; // @[Monitor.scala:626:34]
wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [71:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101]
wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99]
wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_21 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_2467 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [8:0] d_clr; // @[Monitor.scala:664:34]
wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46]
wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_23 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_2482 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [8:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [8:0] inflight_1; // @[Monitor.scala:726:35]
reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [8:0] c_set; // @[Monitor.scala:738:34]
wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34]
wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34]
wire [71:0] c_sizes_set; // @[Monitor.scala:741:34]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40]
wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40]
wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44]
wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7]
wire [15:0] _GEN_24 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T; // @[OneHot.scala:58:35]
assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35]
assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35]
assign c_set = _T_2554 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53]
wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}]
assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}]
wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51]
wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}]
assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}]
wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79]
wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}]
assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}]
wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77]
wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}]
assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}]
wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47]
wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95]
wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}]
wire [8:0] d_clr_1; // @[Monitor.scala:774:34]
wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_2567 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}]
wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}]
wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}]
wire [8:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35]
wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43]
wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41]
wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26]
wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [7:0] d_set; // @[Monitor.scala:833:25]
wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35]
assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] e_clr; // @[Monitor.scala:839:25]
wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35]
wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35]
assign e_clr = _T_2630 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module PlusArgTimeout_3 :
input clock : Clock
input reset : Reset
output io : { flip count : UInt<32>}
inst plusarg_reader of plusarg_reader_111
node _T = gt(plusarg_reader.out, UInt<1>(0h0))
when _T :
node _T_1 = lt(io.count, plusarg_reader.out)
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert | module PlusArgTimeout_3( // @[PlusArg.scala:58:7]
input clock, // @[PlusArg.scala:58:7]
input reset, // @[PlusArg.scala:58:7]
input [31:0] io_count // @[PlusArg.scala:59:14]
);
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:62:19]
wire [31:0] io_count_0 = io_count; // @[PlusArg.scala:58:7] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_11 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_11( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_43 :
output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 0, 0)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1))
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i1_e8_s24_43(); // @[INToRecFN.scala:43:7]
wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31]
wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44]
wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22]
wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33]
wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72]
wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20]
wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_in = 1'h1; // @[Mux.scala:50:70]
wire io_detectTininess = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70]
wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70]
wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70]
wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29]
wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23]
wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36]
RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_43 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_138 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_148
connect io_out_sink_extend.clock, clock
connect io_out_sink_extend.reset, reset
connect io_out_sink_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_138( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_148 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_154 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_154( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_483 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_483( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Router_44 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_98
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn_1.vc_free
invalidate destNodesIn_1.credit_return
invalidate destNodesIn_1.flit[0].bits.virt_channel_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node
invalidate destNodesIn_1.flit[0].bits.flow.vnet_id
invalidate destNodesIn_1.flit[0].bits.payload
invalidate destNodesIn_1.flit[0].bits.tail
invalidate destNodesIn_1.flit[0].bits.head
invalidate destNodesIn_1.flit[0].valid
inst monitor_1 of NoCMonitor_99
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free
connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return
connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node
connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id
connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node
connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id
connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload
connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail
connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head
connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid
wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn_2.vc_free
invalidate destNodesIn_2.credit_return
invalidate destNodesIn_2.flit[0].bits.virt_channel_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node
invalidate destNodesIn_2.flit[0].bits.flow.vnet_id
invalidate destNodesIn_2.flit[0].bits.payload
invalidate destNodesIn_2.flit[0].bits.tail
invalidate destNodesIn_2.flit[0].bits.head
invalidate destNodesIn_2.flit[0].valid
inst monitor_2 of NoCMonitor_100
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free
connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return
connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node
connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id
connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node
connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id
connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload
connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail
connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head
connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut_1.vc_free
invalidate sourceNodesOut_1.credit_return
invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_1.flit[0].bits.payload
invalidate sourceNodesOut_1.flit[0].bits.tail
invalidate sourceNodesOut_1.flit[0].bits.head
invalidate sourceNodesOut_1.flit[0].valid
wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut_2.vc_free
invalidate sourceNodesOut_2.credit_return
invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_2.flit[0].bits.payload
invalidate sourceNodesOut_2.flit[0].bits.tail
invalidate sourceNodesOut_2.flit[0].bits.head
invalidate sourceNodesOut_2.flit[0].valid
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in_0
connect destNodesIn_1, auto.dest_nodes_in_1
connect destNodesIn_2, auto.dest_nodes_in_2
connect auto.source_nodes_out_0, sourceNodesOut
connect auto.source_nodes_out_1, sourceNodesOut_1
connect auto.source_nodes_out_2, sourceNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_6 of InputUnit_98
connect input_unit_0_from_6.clock, clock
connect input_unit_0_from_6.reset, reset
inst input_unit_1_from_14 of InputUnit_99
connect input_unit_1_from_14.clock, clock
connect input_unit_1_from_14.reset, reset
inst input_unit_2_from_16 of InputUnit_100
connect input_unit_2_from_16.clock, clock
connect input_unit_2_from_16.reset, reset
inst output_unit_0_to_6 of OutputUnit_98
connect output_unit_0_to_6.clock, clock
connect output_unit_0_to_6.reset, reset
inst output_unit_1_to_14 of OutputUnit_99
connect output_unit_1_to_14.clock, clock
connect output_unit_1_to_14.reset, reset
inst output_unit_2_to_16 of OutputUnit_100
connect output_unit_2_to_16.clock, clock
connect output_unit_2_to_16.reset, reset
inst switch of Switch_44
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_44
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_44
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_44
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_6.io.in, destNodesIn
connect input_unit_1_from_14.io.in, destNodesIn_1
connect input_unit_2_from_16.io.in, destNodesIn_2
connect output_unit_0_to_6.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_6.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_6.io.out.flit
connect output_unit_1_to_14.io.out.vc_free, sourceNodesOut_1.vc_free
connect output_unit_1_to_14.io.out.credit_return, sourceNodesOut_1.credit_return
connect sourceNodesOut_1.flit, output_unit_1_to_14.io.out.flit
connect output_unit_2_to_16.io.out.vc_free, sourceNodesOut_2.vc_free
connect output_unit_2_to_16.io.out.credit_return, sourceNodesOut_2.credit_return
connect sourceNodesOut_2.flit, output_unit_2_to_16.io.out.flit
connect route_computer.io.req.`0`, input_unit_0_from_6.io.router_req
connect route_computer.io.req.`1`, input_unit_1_from_14.io.router_req
connect route_computer.io.req.`2`, input_unit_2_from_16.io.router_req
connect input_unit_0_from_6.io.router_resp, route_computer.io.resp.`0`
connect input_unit_1_from_14.io.router_resp, route_computer.io.resp.`1`
connect input_unit_2_from_16.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_6.io.vcalloc_req
connect vc_allocator.io.req.`1`, input_unit_1_from_14.io.vcalloc_req
connect vc_allocator.io.req.`2`, input_unit_2_from_16.io.vcalloc_req
connect input_unit_0_from_6.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect input_unit_1_from_14.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect input_unit_2_from_16.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_6.io.allocs, vc_allocator.io.out_allocs.`0`
connect output_unit_1_to_14.io.allocs, vc_allocator.io.out_allocs.`1`
connect output_unit_2_to_16.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_6.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_6.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_6.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_6.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_6.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_6.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_6.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_6.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_6.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_6.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_6.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_6.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_6.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_6.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_6.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_6.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_6.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_6.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_6.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_6.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_6.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_6.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_6.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_6.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_6.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_6.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_14.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_14.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_14.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_14.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_14.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_14.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_14.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_14.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_14.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_14.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_14.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_14.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_14.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_14.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_14.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_14.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_14.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_14.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_14.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_14.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_14.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_14.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_14.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_14.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_14.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_14.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_16.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_16.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_16.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_16.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_16.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_16.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_16.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_16.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_16.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_16.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_16.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_16.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_16.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_16.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_16.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_16.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_16.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_16.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_16.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_16.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_16.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_16.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_16.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_16.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_16.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_16.io.channel_status[4].occupied
connect input_unit_0_from_6.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect input_unit_0_from_6.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect input_unit_0_from_6.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect input_unit_0_from_6.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect input_unit_0_from_6.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1]
connect input_unit_0_from_6.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2]
connect input_unit_0_from_6.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3]
connect input_unit_0_from_6.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4]
connect input_unit_0_from_6.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0]
connect input_unit_0_from_6.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1]
connect input_unit_0_from_6.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2]
connect input_unit_0_from_6.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3]
connect input_unit_0_from_6.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4]
connect input_unit_1_from_14.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect input_unit_1_from_14.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect input_unit_1_from_14.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect input_unit_1_from_14.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect input_unit_1_from_14.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect input_unit_1_from_14.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0]
connect input_unit_1_from_14.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1]
connect input_unit_1_from_14.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2]
connect input_unit_1_from_14.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3]
connect input_unit_1_from_14.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4]
connect input_unit_1_from_14.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0]
connect input_unit_1_from_14.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1]
connect input_unit_1_from_14.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2]
connect input_unit_1_from_14.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3]
connect input_unit_1_from_14.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4]
connect input_unit_2_from_16.io.out_credit_available.`0`[0], output_unit_0_to_6.io.credit_available[0]
connect input_unit_2_from_16.io.out_credit_available.`0`[1], output_unit_0_to_6.io.credit_available[1]
connect input_unit_2_from_16.io.out_credit_available.`0`[2], output_unit_0_to_6.io.credit_available[2]
connect input_unit_2_from_16.io.out_credit_available.`0`[3], output_unit_0_to_6.io.credit_available[3]
connect input_unit_2_from_16.io.out_credit_available.`0`[4], output_unit_0_to_6.io.credit_available[4]
connect input_unit_2_from_16.io.out_credit_available.`1`[0], output_unit_1_to_14.io.credit_available[0]
connect input_unit_2_from_16.io.out_credit_available.`1`[1], output_unit_1_to_14.io.credit_available[1]
connect input_unit_2_from_16.io.out_credit_available.`1`[2], output_unit_1_to_14.io.credit_available[2]
connect input_unit_2_from_16.io.out_credit_available.`1`[3], output_unit_1_to_14.io.credit_available[3]
connect input_unit_2_from_16.io.out_credit_available.`1`[4], output_unit_1_to_14.io.credit_available[4]
connect input_unit_2_from_16.io.out_credit_available.`2`[0], output_unit_2_to_16.io.credit_available[0]
connect input_unit_2_from_16.io.out_credit_available.`2`[1], output_unit_2_to_16.io.credit_available[1]
connect input_unit_2_from_16.io.out_credit_available.`2`[2], output_unit_2_to_16.io.credit_available[2]
connect input_unit_2_from_16.io.out_credit_available.`2`[3], output_unit_2_to_16.io.credit_available[3]
connect input_unit_2_from_16.io.out_credit_available.`2`[4], output_unit_2_to_16.io.credit_available[4]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_6.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], input_unit_1_from_14.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], input_unit_2_from_16.io.salloc_req[0]
connect output_unit_0_to_6.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_6.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_6.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_6.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_6.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_6.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_6.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_6.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_6.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_6.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_1_to_14.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect output_unit_1_to_14.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect output_unit_1_to_14.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail
connect output_unit_1_to_14.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc
connect output_unit_1_to_14.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail
connect output_unit_1_to_14.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc
connect output_unit_1_to_14.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail
connect output_unit_1_to_14.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc
connect output_unit_1_to_14.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail
connect output_unit_1_to_14.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc
connect output_unit_2_to_16.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect output_unit_2_to_16.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect output_unit_2_to_16.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail
connect output_unit_2_to_16.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc
connect output_unit_2_to_16.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail
connect output_unit_2_to_16.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc
connect output_unit_2_to_16.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail
connect output_unit_2_to_16.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc
connect output_unit_2_to_16.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail
connect output_unit_2_to_16.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc
connect switch.io.in.`0`[0], input_unit_0_from_6.io.out[0]
connect switch.io.in.`1`[0], input_unit_1_from_14.io.out[0]
connect switch.io.in.`2`[0], input_unit_2_from_16.io.out[0]
connect output_unit_0_to_6.io.in, switch.io.out.`0`
connect output_unit_1_to_14.io.in, switch.io.out.`1`
connect output_unit_2_to_16.io.in, switch.io.out.`2`
reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect input_unit_0_from_6.io.block, UInt<1>(0h0)
connect input_unit_1_from_14.io.block, UInt<1>(0h0)
connect input_unit_2_from_16.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_6.io.debug.va_stall
connect debugNodeOut.va_stall[1], input_unit_1_from_14.io.debug.va_stall
connect debugNodeOut.va_stall[2], input_unit_2_from_16.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_6.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], input_unit_1_from_14.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], input_unit_2_from_16.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_92
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 6 15 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid)
connect fired_1, _fired_T_1
node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = eq(debug_sample, _T_13)
node _T_15 = and(_T_11, _T_14)
node _T_16 = and(_T_15, fired_1)
when _T_16 :
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "nocsample %d 14 15 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, destNodesIn_1.flit[0].valid
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid)
connect fired_2, _fired_T_2
node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = eq(debug_sample, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = and(_T_23, fired_2)
when _T_24 :
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "nocsample %d 16 15 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, destNodesIn_2.flit[0].valid | module Router_44( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_2_to_16_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_2_to_16_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_14_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_14_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_6_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire [2:0] _input_unit_2_from_16_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_16_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_16_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_16_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_16_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_16_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_16_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_2_from_16_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_16_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_16_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_14_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_14_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_14_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_14_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_14_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_14_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_14_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_14_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_14_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_14_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_6_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_6_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_6_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_6_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_6_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_14_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_16_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module ForwardingAgeLogic :
input clock : Clock
input reset : Reset
output io : { flip addr_matches : UInt<8>, flip youngest_st_idx : UInt<3>, forwarding_val : UInt<1>, forwarding_idx : UInt<3>}
wire age_mask : UInt<1>[8]
connect age_mask[0], UInt<1>(0h1)
node _T = geq(UInt<1>(0h0), io.youngest_st_idx)
when _T :
connect age_mask[0], UInt<1>(0h0)
connect age_mask[1], UInt<1>(0h1)
node _T_1 = geq(UInt<1>(0h1), io.youngest_st_idx)
when _T_1 :
connect age_mask[1], UInt<1>(0h0)
connect age_mask[2], UInt<1>(0h1)
node _T_2 = geq(UInt<2>(0h2), io.youngest_st_idx)
when _T_2 :
connect age_mask[2], UInt<1>(0h0)
connect age_mask[3], UInt<1>(0h1)
node _T_3 = geq(UInt<2>(0h3), io.youngest_st_idx)
when _T_3 :
connect age_mask[3], UInt<1>(0h0)
connect age_mask[4], UInt<1>(0h1)
node _T_4 = geq(UInt<3>(0h4), io.youngest_st_idx)
when _T_4 :
connect age_mask[4], UInt<1>(0h0)
connect age_mask[5], UInt<1>(0h1)
node _T_5 = geq(UInt<3>(0h5), io.youngest_st_idx)
when _T_5 :
connect age_mask[5], UInt<1>(0h0)
connect age_mask[6], UInt<1>(0h1)
node _T_6 = geq(UInt<3>(0h6), io.youngest_st_idx)
when _T_6 :
connect age_mask[6], UInt<1>(0h0)
connect age_mask[7], UInt<1>(0h1)
node _T_7 = geq(UInt<3>(0h7), io.youngest_st_idx)
when _T_7 :
connect age_mask[7], UInt<1>(0h0)
wire matches : UInt<16>
node matches_lo_lo = cat(age_mask[1], age_mask[0])
node matches_lo_hi = cat(age_mask[3], age_mask[2])
node matches_lo = cat(matches_lo_hi, matches_lo_lo)
node matches_hi_lo = cat(age_mask[5], age_mask[4])
node matches_hi_hi = cat(age_mask[7], age_mask[6])
node matches_hi = cat(matches_hi_hi, matches_hi_lo)
node _matches_T = cat(matches_hi, matches_lo)
node _matches_T_1 = and(io.addr_matches, _matches_T)
node _matches_T_2 = cat(_matches_T_1, io.addr_matches)
connect matches, _matches_T_2
wire found_match : UInt<1>
connect found_match, UInt<1>(0h0)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_8 = bits(matches, 0, 0)
when _T_8 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_9 = bits(matches, 1, 1)
when _T_9 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h1)
node _T_10 = bits(matches, 2, 2)
when _T_10 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h2)
node _T_11 = bits(matches, 3, 3)
when _T_11 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h3)
node _T_12 = bits(matches, 4, 4)
when _T_12 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h4)
node _T_13 = bits(matches, 5, 5)
when _T_13 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h5)
node _T_14 = bits(matches, 6, 6)
when _T_14 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h6)
node _T_15 = bits(matches, 7, 7)
when _T_15 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h7)
node _T_16 = bits(matches, 8, 8)
when _T_16 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h0)
node _T_17 = bits(matches, 9, 9)
when _T_17 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<1>(0h1)
node _T_18 = bits(matches, 10, 10)
when _T_18 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h2)
node _T_19 = bits(matches, 11, 11)
when _T_19 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<2>(0h3)
node _T_20 = bits(matches, 12, 12)
when _T_20 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h4)
node _T_21 = bits(matches, 13, 13)
when _T_21 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h5)
node _T_22 = bits(matches, 14, 14)
when _T_22 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h6)
node _T_23 = bits(matches, 15, 15)
when _T_23 :
connect found_match, UInt<1>(0h1)
connect io.forwarding_idx, UInt<3>(0h7)
connect io.forwarding_val, found_match | module ForwardingAgeLogic( // @[lsu.scala:1678:7]
input clock, // @[lsu.scala:1678:7]
input reset, // @[lsu.scala:1678:7]
input [7:0] io_addr_matches, // @[lsu.scala:1680:15]
input [2:0] io_youngest_st_idx, // @[lsu.scala:1680:15]
output [2:0] io_forwarding_idx // @[lsu.scala:1680:15]
);
wire [7:0] io_addr_matches_0 = io_addr_matches; // @[lsu.scala:1678:7]
wire [2:0] io_youngest_st_idx_0 = io_youngest_st_idx; // @[lsu.scala:1678:7]
wire age_mask_7 = 1'h0; // @[lsu.scala:1691:23]
wire found_match; // @[lsu.scala:1706:26]
wire io_forwarding_val; // @[lsu.scala:1678:7]
wire [2:0] io_forwarding_idx_0; // @[lsu.scala:1678:7]
wire age_mask_0; // @[lsu.scala:1691:23]
wire age_mask_1; // @[lsu.scala:1691:23]
wire age_mask_2; // @[lsu.scala:1691:23]
wire age_mask_3; // @[lsu.scala:1691:23]
wire age_mask_4; // @[lsu.scala:1691:23]
wire age_mask_5; // @[lsu.scala:1691:23]
wire age_mask_6; // @[lsu.scala:1691:23]
assign age_mask_0 = |io_youngest_st_idx_0; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_1 = |(io_youngest_st_idx_0[2:1]); // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_2 = io_youngest_st_idx_0 > 3'h2; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_3 = io_youngest_st_idx_0[2]; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_4 = io_youngest_st_idx_0 > 3'h4; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_5 = io_youngest_st_idx_0 > 3'h5; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
assign age_mask_6 = &io_youngest_st_idx_0; // @[lsu.scala:1678:7, :1691:23, :1694:19, :1695:17, :1696:7, :1697:22]
wire [15:0] _matches_T_2; // @[lsu.scala:1703:18]
wire [15:0] matches_0; // @[lsu.scala:1702:22]
wire [1:0] matches_lo_lo = {age_mask_1, age_mask_0}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_lo_hi = {age_mask_3, age_mask_2}; // @[lsu.scala:1691:23, :1703:46]
wire [3:0] matches_lo = {matches_lo_hi, matches_lo_lo}; // @[lsu.scala:1703:46]
wire [1:0] matches_hi_lo = {age_mask_5, age_mask_4}; // @[lsu.scala:1691:23, :1703:46]
wire [1:0] matches_hi_hi = {1'h0, age_mask_6}; // @[lsu.scala:1691:23, :1703:46]
wire [3:0] matches_hi = {matches_hi_hi, matches_hi_lo}; // @[lsu.scala:1703:46]
wire [7:0] _matches_T = {matches_hi, matches_lo}; // @[lsu.scala:1703:46]
wire [7:0] _matches_T_1 = io_addr_matches_0 & _matches_T; // @[lsu.scala:1678:7, :1703:{35,46}]
assign _matches_T_2 = {_matches_T_1, io_addr_matches_0}; // @[lsu.scala:1678:7, :1703:{18,35}]
assign matches_0 = _matches_T_2; // @[lsu.scala:1702:22, :1703:18]
assign io_forwarding_val = found_match; // @[lsu.scala:1678:7, :1706:26]
assign found_match = |matches_0; // @[lsu.scala:1702:22, :1706:26, :1714:7, :1715:22]
assign io_forwarding_idx_0 = matches_0[15] ? 3'h7 : matches_0[14] ? 3'h6 : matches_0[13] ? 3'h5 : matches_0[12] ? 3'h4 : matches_0[11] ? 3'h3 : matches_0[10] ? 3'h2 : matches_0[9] ? 3'h1 : matches_0[8] ? 3'h0 : matches_0[7] ? 3'h7 : matches_0[6] ? 3'h6 : matches_0[5] ? 3'h5 : matches_0[4] ? 3'h4 : matches_0[3] ? 3'h3 : matches_0[2] ? 3'h2 : {2'h0, matches_0[1]}; // @[lsu.scala:1678:7, :1694:19, :1695:17, :1696:7, :1697:22, :1702:22, :1713:20, :1714:7, :1716:28]
assign io_forwarding_idx = io_forwarding_idx_0; // @[lsu.scala:1678:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AXI4Fragmenter_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}, out : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}}
wire nodeIn : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { }}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { }, last : UInt<1>}}}
invalidate nodeIn.r.bits.last
invalidate nodeIn.r.bits.resp
invalidate nodeIn.r.bits.data
invalidate nodeIn.r.bits.id
invalidate nodeIn.r.valid
invalidate nodeIn.r.ready
invalidate nodeIn.ar.bits.qos
invalidate nodeIn.ar.bits.prot
invalidate nodeIn.ar.bits.cache
invalidate nodeIn.ar.bits.lock
invalidate nodeIn.ar.bits.burst
invalidate nodeIn.ar.bits.size
invalidate nodeIn.ar.bits.len
invalidate nodeIn.ar.bits.addr
invalidate nodeIn.ar.bits.id
invalidate nodeIn.ar.valid
invalidate nodeIn.ar.ready
invalidate nodeIn.b.bits.resp
invalidate nodeIn.b.bits.id
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.w.bits.last
invalidate nodeIn.w.bits.strb
invalidate nodeIn.w.bits.data
invalidate nodeIn.w.valid
invalidate nodeIn.w.ready
invalidate nodeIn.aw.bits.qos
invalidate nodeIn.aw.bits.prot
invalidate nodeIn.aw.bits.cache
invalidate nodeIn.aw.bits.lock
invalidate nodeIn.aw.bits.burst
invalidate nodeIn.aw.bits.size
invalidate nodeIn.aw.bits.len
invalidate nodeIn.aw.bits.addr
invalidate nodeIn.aw.bits.id
invalidate nodeIn.aw.valid
invalidate nodeIn.aw.ready
wire nodeOut : { aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}}}, ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { real_last : UInt<1>}}}, flip r : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, data : UInt<64>, resp : UInt<2>, user : { }, echo : { real_last : UInt<1>}, last : UInt<1>}}}
invalidate nodeOut.r.bits.last
invalidate nodeOut.r.bits.echo.real_last
invalidate nodeOut.r.bits.resp
invalidate nodeOut.r.bits.data
invalidate nodeOut.r.bits.id
invalidate nodeOut.r.valid
invalidate nodeOut.r.ready
invalidate nodeOut.ar.bits.echo.real_last
invalidate nodeOut.ar.bits.qos
invalidate nodeOut.ar.bits.prot
invalidate nodeOut.ar.bits.cache
invalidate nodeOut.ar.bits.lock
invalidate nodeOut.ar.bits.burst
invalidate nodeOut.ar.bits.size
invalidate nodeOut.ar.bits.len
invalidate nodeOut.ar.bits.addr
invalidate nodeOut.ar.bits.id
invalidate nodeOut.ar.valid
invalidate nodeOut.ar.ready
invalidate nodeOut.b.bits.echo.real_last
invalidate nodeOut.b.bits.resp
invalidate nodeOut.b.bits.id
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.w.bits.last
invalidate nodeOut.w.bits.strb
invalidate nodeOut.w.bits.data
invalidate nodeOut.w.valid
invalidate nodeOut.w.ready
invalidate nodeOut.aw.bits.echo.real_last
invalidate nodeOut.aw.bits.qos
invalidate nodeOut.aw.bits.prot
invalidate nodeOut.aw.bits.cache
invalidate nodeOut.aw.bits.lock
invalidate nodeOut.aw.bits.burst
invalidate nodeOut.aw.bits.size
invalidate nodeOut.aw.bits.len
invalidate nodeOut.aw.bits.addr
invalidate nodeOut.aw.bits.id
invalidate nodeOut.aw.valid
invalidate nodeOut.aw.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst deq_q of Queue1_AXI4BundleAR_1
connect deq_q.clock, clock
connect deq_q.reset, reset
connect deq_q.io.enq.valid, nodeIn.ar.valid
connect deq_q.io.enq.bits.qos, nodeIn.ar.bits.qos
connect deq_q.io.enq.bits.prot, nodeIn.ar.bits.prot
connect deq_q.io.enq.bits.cache, nodeIn.ar.bits.cache
connect deq_q.io.enq.bits.lock, nodeIn.ar.bits.lock
connect deq_q.io.enq.bits.burst, nodeIn.ar.bits.burst
connect deq_q.io.enq.bits.size, nodeIn.ar.bits.size
connect deq_q.io.enq.bits.len, nodeIn.ar.bits.len
connect deq_q.io.enq.bits.addr, nodeIn.ar.bits.addr
connect deq_q.io.enq.bits.id, nodeIn.ar.bits.id
connect nodeIn.ar.ready, deq_q.io.enq.ready
wire irr : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
connect irr.bits, deq_q.io.deq.bits
connect irr.valid, deq_q.io.deq.valid
connect deq_q.io.deq.ready, irr.ready
wire in_ar : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_addr : UInt<29>, clock
reg r_len : UInt<8>, clock
node len = mux(busy, r_len, irr.bits.len)
node addr = mux(busy, r_addr, irr.bits.addr)
node lo = bits(addr, 2, 0)
node alignment = bits(addr, 10, 3)
node _support1_T = xor(addr, UInt<1>(0h0))
node _support1_T_1 = cvt(_support1_T)
node _support1_T_2 = and(_support1_T_1, asSInt(UInt<1>(0h0)))
node _support1_T_3 = asSInt(_support1_T_2)
node _support1_T_4 = eq(_support1_T_3, asSInt(UInt<1>(0h0)))
node _fillLow_T = shr(len, 1)
node _fillLow_T_1 = or(len, _fillLow_T)
node _fillLow_T_2 = shr(_fillLow_T_1, 2)
node _fillLow_T_3 = or(_fillLow_T_1, _fillLow_T_2)
node _fillLow_T_4 = shr(_fillLow_T_3, 4)
node _fillLow_T_5 = or(_fillLow_T_3, _fillLow_T_4)
node _fillLow_T_6 = bits(_fillLow_T_5, 7, 0)
node fillLow = shr(_fillLow_T_6, 1)
node _wipeHigh_T = not(len)
node _wipeHigh_T_1 = shl(_wipeHigh_T, 1)
node _wipeHigh_T_2 = bits(_wipeHigh_T_1, 7, 0)
node _wipeHigh_T_3 = or(_wipeHigh_T, _wipeHigh_T_2)
node _wipeHigh_T_4 = shl(_wipeHigh_T_3, 2)
node _wipeHigh_T_5 = bits(_wipeHigh_T_4, 7, 0)
node _wipeHigh_T_6 = or(_wipeHigh_T_3, _wipeHigh_T_5)
node _wipeHigh_T_7 = shl(_wipeHigh_T_6, 4)
node _wipeHigh_T_8 = bits(_wipeHigh_T_7, 7, 0)
node _wipeHigh_T_9 = or(_wipeHigh_T_6, _wipeHigh_T_8)
node _wipeHigh_T_10 = bits(_wipeHigh_T_9, 7, 0)
node wipeHigh = not(_wipeHigh_T_10)
node remain1 = or(fillLow, wipeHigh)
node _align1_T = shl(alignment, 1)
node _align1_T_1 = bits(_align1_T, 7, 0)
node _align1_T_2 = or(alignment, _align1_T_1)
node _align1_T_3 = shl(_align1_T_2, 2)
node _align1_T_4 = bits(_align1_T_3, 7, 0)
node _align1_T_5 = or(_align1_T_2, _align1_T_4)
node _align1_T_6 = shl(_align1_T_5, 4)
node _align1_T_7 = bits(_align1_T_6, 7, 0)
node _align1_T_8 = or(_align1_T_5, _align1_T_7)
node _align1_T_9 = bits(_align1_T_8, 7, 0)
node align1 = not(_align1_T_9)
node _maxSupported1_T = and(remain1, align1)
node maxSupported1 = and(_maxSupported1_T, UInt<1>(0h0))
node fixed = eq(irr.bits.burst, UInt<2>(0h0))
node narrow = neq(irr.bits.size, UInt<2>(0h3))
node bad = or(fixed, narrow)
node beats1 = mux(bad, UInt<1>(0h0), maxSupported1)
node _beats_T = shl(beats1, 1)
node _beats_T_1 = or(_beats_T, UInt<1>(0h1))
node _beats_T_2 = cat(UInt<1>(0h0), beats1)
node _beats_T_3 = not(_beats_T_2)
node beats = and(_beats_T_1, _beats_T_3)
node _inc_addr_T = dshl(beats, irr.bits.size)
node _inc_addr_T_1 = add(addr, _inc_addr_T)
node inc_addr = tail(_inc_addr_T_1, 1)
node _wrapMask_T = cat(irr.bits.len, UInt<8>(0hff))
node _wrapMask_T_1 = dshl(_wrapMask_T, irr.bits.size)
node wrapMask = shr(_wrapMask_T_1, 8)
wire mux_addr : UInt
connect mux_addr, inc_addr
node _T = eq(irr.bits.burst, UInt<2>(0h2))
when _T :
node _mux_addr_T = and(inc_addr, wrapMask)
node _mux_addr_T_1 = not(irr.bits.addr)
node _mux_addr_T_2 = or(_mux_addr_T_1, wrapMask)
node _mux_addr_T_3 = not(_mux_addr_T_2)
node _mux_addr_T_4 = or(_mux_addr_T, _mux_addr_T_3)
connect mux_addr, _mux_addr_T_4
node _T_1 = eq(irr.bits.burst, UInt<2>(0h0))
when _T_1 :
connect mux_addr, irr.bits.addr
node ar_last = eq(beats1, len)
node _irr_ready_T = and(in_ar.ready, ar_last)
connect irr.ready, _irr_ready_T
connect in_ar.valid, irr.valid
connect in_ar.bits.qos, irr.bits.qos
connect in_ar.bits.prot, irr.bits.prot
connect in_ar.bits.cache, irr.bits.cache
connect in_ar.bits.lock, irr.bits.lock
connect in_ar.bits.burst, irr.bits.burst
connect in_ar.bits.size, irr.bits.size
connect in_ar.bits.len, irr.bits.len
connect in_ar.bits.addr, irr.bits.addr
connect in_ar.bits.id, irr.bits.id
connect in_ar.bits.len, beats1
node _out_bits_addr_T = not(addr)
node _out_bits_addr_T_1 = dshl(UInt<3>(0h7), irr.bits.size)
node _out_bits_addr_T_2 = bits(_out_bits_addr_T_1, 2, 0)
node _out_bits_addr_T_3 = not(_out_bits_addr_T_2)
node _out_bits_addr_T_4 = or(_out_bits_addr_T, _out_bits_addr_T_3)
node _out_bits_addr_T_5 = not(_out_bits_addr_T_4)
connect in_ar.bits.addr, _out_bits_addr_T_5
node _T_2 = and(in_ar.ready, in_ar.valid)
when _T_2 :
node _busy_T = eq(ar_last, UInt<1>(0h0))
connect busy, _busy_T
connect r_addr, mux_addr
node _r_len_T = sub(len, beats)
node _r_len_T_1 = tail(_r_len_T, 1)
connect r_len, _r_len_T_1
inst deq_q_1 of Queue1_AXI4BundleAW_1
connect deq_q_1.clock, clock
connect deq_q_1.reset, reset
connect deq_q_1.io.enq.valid, nodeIn.aw.valid
connect deq_q_1.io.enq.bits.qos, nodeIn.aw.bits.qos
connect deq_q_1.io.enq.bits.prot, nodeIn.aw.bits.prot
connect deq_q_1.io.enq.bits.cache, nodeIn.aw.bits.cache
connect deq_q_1.io.enq.bits.lock, nodeIn.aw.bits.lock
connect deq_q_1.io.enq.bits.burst, nodeIn.aw.bits.burst
connect deq_q_1.io.enq.bits.size, nodeIn.aw.bits.size
connect deq_q_1.io.enq.bits.len, nodeIn.aw.bits.len
connect deq_q_1.io.enq.bits.addr, nodeIn.aw.bits.addr
connect deq_q_1.io.enq.bits.id, nodeIn.aw.bits.id
connect nodeIn.aw.ready, deq_q_1.io.enq.ready
wire irr_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
connect irr_1.bits, deq_q_1.io.deq.bits
connect irr_1.valid, deq_q_1.io.deq.valid
connect deq_q_1.io.deq.ready, irr_1.ready
wire in_aw : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<4>, addr : UInt<29>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, user : { }, echo : { }}}
regreset busy_1 : UInt<1>, clock, reset, UInt<1>(0h0)
reg r_addr_1 : UInt<29>, clock
reg r_len_1 : UInt<8>, clock
node len_1 = mux(busy_1, r_len_1, irr_1.bits.len)
node addr_1 = mux(busy_1, r_addr_1, irr_1.bits.addr)
node lo_1 = bits(addr_1, 2, 0)
node alignment_1 = bits(addr_1, 10, 3)
node _support1_T_5 = xor(addr_1, UInt<1>(0h0))
node _support1_T_6 = cvt(_support1_T_5)
node _support1_T_7 = and(_support1_T_6, asSInt(UInt<1>(0h0)))
node _support1_T_8 = asSInt(_support1_T_7)
node _support1_T_9 = eq(_support1_T_8, asSInt(UInt<1>(0h0)))
node _fillLow_T_7 = shr(len_1, 1)
node _fillLow_T_8 = or(len_1, _fillLow_T_7)
node _fillLow_T_9 = shr(_fillLow_T_8, 2)
node _fillLow_T_10 = or(_fillLow_T_8, _fillLow_T_9)
node _fillLow_T_11 = shr(_fillLow_T_10, 4)
node _fillLow_T_12 = or(_fillLow_T_10, _fillLow_T_11)
node _fillLow_T_13 = bits(_fillLow_T_12, 7, 0)
node fillLow_1 = shr(_fillLow_T_13, 1)
node _wipeHigh_T_11 = not(len_1)
node _wipeHigh_T_12 = shl(_wipeHigh_T_11, 1)
node _wipeHigh_T_13 = bits(_wipeHigh_T_12, 7, 0)
node _wipeHigh_T_14 = or(_wipeHigh_T_11, _wipeHigh_T_13)
node _wipeHigh_T_15 = shl(_wipeHigh_T_14, 2)
node _wipeHigh_T_16 = bits(_wipeHigh_T_15, 7, 0)
node _wipeHigh_T_17 = or(_wipeHigh_T_14, _wipeHigh_T_16)
node _wipeHigh_T_18 = shl(_wipeHigh_T_17, 4)
node _wipeHigh_T_19 = bits(_wipeHigh_T_18, 7, 0)
node _wipeHigh_T_20 = or(_wipeHigh_T_17, _wipeHigh_T_19)
node _wipeHigh_T_21 = bits(_wipeHigh_T_20, 7, 0)
node wipeHigh_1 = not(_wipeHigh_T_21)
node remain1_1 = or(fillLow_1, wipeHigh_1)
node _align1_T_10 = shl(alignment_1, 1)
node _align1_T_11 = bits(_align1_T_10, 7, 0)
node _align1_T_12 = or(alignment_1, _align1_T_11)
node _align1_T_13 = shl(_align1_T_12, 2)
node _align1_T_14 = bits(_align1_T_13, 7, 0)
node _align1_T_15 = or(_align1_T_12, _align1_T_14)
node _align1_T_16 = shl(_align1_T_15, 4)
node _align1_T_17 = bits(_align1_T_16, 7, 0)
node _align1_T_18 = or(_align1_T_15, _align1_T_17)
node _align1_T_19 = bits(_align1_T_18, 7, 0)
node align1_1 = not(_align1_T_19)
node _maxSupported1_T_1 = and(remain1_1, align1_1)
node maxSupported1_1 = and(_maxSupported1_T_1, UInt<1>(0h0))
node fixed_1 = eq(irr_1.bits.burst, UInt<2>(0h0))
node narrow_1 = neq(irr_1.bits.size, UInt<2>(0h3))
node bad_1 = or(fixed_1, narrow_1)
node beats1_1 = mux(bad_1, UInt<1>(0h0), maxSupported1_1)
node _beats_T_4 = shl(beats1_1, 1)
node _beats_T_5 = or(_beats_T_4, UInt<1>(0h1))
node _beats_T_6 = cat(UInt<1>(0h0), beats1_1)
node _beats_T_7 = not(_beats_T_6)
node w_beats = and(_beats_T_5, _beats_T_7)
node _inc_addr_T_2 = dshl(w_beats, irr_1.bits.size)
node _inc_addr_T_3 = add(addr_1, _inc_addr_T_2)
node inc_addr_1 = tail(_inc_addr_T_3, 1)
node _wrapMask_T_2 = cat(irr_1.bits.len, UInt<8>(0hff))
node _wrapMask_T_3 = dshl(_wrapMask_T_2, irr_1.bits.size)
node wrapMask_1 = shr(_wrapMask_T_3, 8)
wire mux_addr_1 : UInt
connect mux_addr_1, inc_addr_1
node _T_3 = eq(irr_1.bits.burst, UInt<2>(0h2))
when _T_3 :
node _mux_addr_T_5 = and(inc_addr_1, wrapMask_1)
node _mux_addr_T_6 = not(irr_1.bits.addr)
node _mux_addr_T_7 = or(_mux_addr_T_6, wrapMask_1)
node _mux_addr_T_8 = not(_mux_addr_T_7)
node _mux_addr_T_9 = or(_mux_addr_T_5, _mux_addr_T_8)
connect mux_addr_1, _mux_addr_T_9
node _T_4 = eq(irr_1.bits.burst, UInt<2>(0h0))
when _T_4 :
connect mux_addr_1, irr_1.bits.addr
node aw_last = eq(beats1_1, len_1)
node _irr_ready_T_1 = and(in_aw.ready, aw_last)
connect irr_1.ready, _irr_ready_T_1
connect in_aw.valid, irr_1.valid
connect in_aw.bits.qos, irr_1.bits.qos
connect in_aw.bits.prot, irr_1.bits.prot
connect in_aw.bits.cache, irr_1.bits.cache
connect in_aw.bits.lock, irr_1.bits.lock
connect in_aw.bits.burst, irr_1.bits.burst
connect in_aw.bits.size, irr_1.bits.size
connect in_aw.bits.len, irr_1.bits.len
connect in_aw.bits.addr, irr_1.bits.addr
connect in_aw.bits.id, irr_1.bits.id
connect in_aw.bits.len, beats1_1
node _out_bits_addr_T_6 = not(addr_1)
node _out_bits_addr_T_7 = dshl(UInt<3>(0h7), irr_1.bits.size)
node _out_bits_addr_T_8 = bits(_out_bits_addr_T_7, 2, 0)
node _out_bits_addr_T_9 = not(_out_bits_addr_T_8)
node _out_bits_addr_T_10 = or(_out_bits_addr_T_6, _out_bits_addr_T_9)
node _out_bits_addr_T_11 = not(_out_bits_addr_T_10)
connect in_aw.bits.addr, _out_bits_addr_T_11
node _T_5 = and(in_aw.ready, in_aw.valid)
when _T_5 :
node _busy_T_1 = eq(aw_last, UInt<1>(0h0))
connect busy_1, _busy_T_1
connect r_addr_1, mux_addr_1
node _r_len_T_2 = sub(len_1, w_beats)
node _r_len_T_3 = tail(_r_len_T_2, 1)
connect r_len_1, _r_len_T_3
inst in_w_deq_q of Queue1_AXI4BundleW_2
connect in_w_deq_q.clock, clock
connect in_w_deq_q.reset, reset
connect in_w_deq_q.io.enq.valid, nodeIn.w.valid
connect in_w_deq_q.io.enq.bits.last, nodeIn.w.bits.last
connect in_w_deq_q.io.enq.bits.strb, nodeIn.w.bits.strb
connect in_w_deq_q.io.enq.bits.data, nodeIn.w.bits.data
connect nodeIn.w.ready, in_w_deq_q.io.enq.ready
wire in_w : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<64>, strb : UInt<8>, last : UInt<1>, user : { }}}
connect in_w.bits, in_w_deq_q.io.deq.bits
connect in_w.valid, in_w_deq_q.io.deq.valid
connect in_w_deq_q.io.deq.ready, in_w.ready
connect nodeOut.ar.bits.qos, in_ar.bits.qos
connect nodeOut.ar.bits.prot, in_ar.bits.prot
connect nodeOut.ar.bits.cache, in_ar.bits.cache
connect nodeOut.ar.bits.lock, in_ar.bits.lock
connect nodeOut.ar.bits.burst, in_ar.bits.burst
connect nodeOut.ar.bits.size, in_ar.bits.size
connect nodeOut.ar.bits.len, in_ar.bits.len
connect nodeOut.ar.bits.addr, in_ar.bits.addr
connect nodeOut.ar.bits.id, in_ar.bits.id
connect nodeOut.ar.valid, in_ar.valid
connect in_ar.ready, nodeOut.ar.ready
connect nodeOut.ar.bits.echo.real_last, ar_last
regreset wbeats_latched : UInt<1>, clock, reset, UInt<1>(0h0)
wire wbeats_ready : UInt<1>
wire wbeats_valid : UInt<1>
node _T_6 = and(wbeats_valid, wbeats_ready)
when _T_6 :
connect wbeats_latched, UInt<1>(0h1)
node _T_7 = and(nodeOut.aw.ready, nodeOut.aw.valid)
when _T_7 :
connect wbeats_latched, UInt<1>(0h0)
node _nodeOut_aw_valid_T = or(wbeats_ready, wbeats_latched)
node _nodeOut_aw_valid_T_1 = and(in_aw.valid, _nodeOut_aw_valid_T)
connect nodeOut.aw.valid, _nodeOut_aw_valid_T_1
node _in_aw_ready_T = or(wbeats_ready, wbeats_latched)
node _in_aw_ready_T_1 = and(nodeOut.aw.ready, _in_aw_ready_T)
connect in_aw.ready, _in_aw_ready_T_1
node _wbeats_valid_T = eq(wbeats_latched, UInt<1>(0h0))
node _wbeats_valid_T_1 = and(in_aw.valid, _wbeats_valid_T)
connect wbeats_valid, _wbeats_valid_T_1
connect nodeOut.aw.bits.qos, in_aw.bits.qos
connect nodeOut.aw.bits.prot, in_aw.bits.prot
connect nodeOut.aw.bits.cache, in_aw.bits.cache
connect nodeOut.aw.bits.lock, in_aw.bits.lock
connect nodeOut.aw.bits.burst, in_aw.bits.burst
connect nodeOut.aw.bits.size, in_aw.bits.size
connect nodeOut.aw.bits.len, in_aw.bits.len
connect nodeOut.aw.bits.addr, in_aw.bits.addr
connect nodeOut.aw.bits.id, in_aw.bits.id
connect nodeOut.aw.bits.echo.real_last, aw_last
regreset w_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node w_idle = eq(w_counter, UInt<1>(0h0))
node _w_todo_T = mux(wbeats_valid, w_beats, UInt<1>(0h0))
node w_todo = mux(w_idle, _w_todo_T, w_counter)
node w_last = eq(w_todo, UInt<1>(0h1))
node _w_counter_T = and(nodeOut.w.ready, nodeOut.w.valid)
node _w_counter_T_1 = sub(w_todo, _w_counter_T)
node _w_counter_T_2 = tail(_w_counter_T_1, 1)
connect w_counter, _w_counter_T_2
node _T_8 = and(nodeOut.w.ready, nodeOut.w.valid)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = neq(w_todo, UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:181 assert (!out.w.fire || w_todo =/= 0.U) // underflow impossible\n") : printf
assert(clock, _T_11, UInt<1>(0h1), "") : assert
connect wbeats_ready, w_idle
node _nodeOut_w_valid_T = eq(wbeats_ready, UInt<1>(0h0))
node _nodeOut_w_valid_T_1 = or(_nodeOut_w_valid_T, wbeats_valid)
node _nodeOut_w_valid_T_2 = and(in_w.valid, _nodeOut_w_valid_T_1)
connect nodeOut.w.valid, _nodeOut_w_valid_T_2
node _in_w_ready_T = eq(wbeats_ready, UInt<1>(0h0))
node _in_w_ready_T_1 = or(_in_w_ready_T, wbeats_valid)
node _in_w_ready_T_2 = and(nodeOut.w.ready, _in_w_ready_T_1)
connect in_w.ready, _in_w_ready_T_2
connect nodeOut.w.bits.last, in_w.bits.last
connect nodeOut.w.bits.strb, in_w.bits.strb
connect nodeOut.w.bits.data, in_w.bits.data
connect nodeOut.w.bits.last, w_last
node _T_15 = eq(nodeOut.w.valid, UInt<1>(0h0))
node _T_16 = eq(in_w.bits.last, UInt<1>(0h0))
node _T_17 = or(_T_15, _T_16)
node _T_18 = or(_T_17, w_last)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:190 assert (!out.w.valid || !in_w.bits.last || w_last)\n") : printf_1
assert(clock, _T_18, UInt<1>(0h1), "") : assert_1
connect nodeIn.r.bits.last, nodeOut.r.bits.last
connect nodeIn.r.bits.resp, nodeOut.r.bits.resp
connect nodeIn.r.bits.data, nodeOut.r.bits.data
connect nodeIn.r.bits.id, nodeOut.r.bits.id
connect nodeIn.r.valid, nodeOut.r.valid
connect nodeOut.r.ready, nodeIn.r.ready
node _nodeIn_r_bits_last_T = and(nodeOut.r.bits.last, nodeOut.r.bits.echo.real_last)
connect nodeIn.r.bits.last, _nodeIn_r_bits_last_T
connect nodeIn.b.bits.resp, nodeOut.b.bits.resp
connect nodeIn.b.bits.id, nodeOut.b.bits.id
connect nodeIn.b.valid, nodeOut.b.valid
connect nodeOut.b.ready, nodeIn.b.ready
node _nodeIn_b_valid_T = and(nodeOut.b.valid, nodeOut.b.bits.echo.real_last)
connect nodeIn.b.valid, _nodeIn_b_valid_T
node _nodeOut_b_ready_T = eq(nodeOut.b.bits.echo.real_last, UInt<1>(0h0))
node _nodeOut_b_ready_T_1 = or(nodeIn.b.ready, _nodeOut_b_ready_T)
connect nodeOut.b.ready, _nodeOut_b_ready_T_1
wire _error_WIRE : UInt<2>[16]
connect _error_WIRE[0], UInt<2>(0h0)
connect _error_WIRE[1], UInt<2>(0h0)
connect _error_WIRE[2], UInt<2>(0h0)
connect _error_WIRE[3], UInt<2>(0h0)
connect _error_WIRE[4], UInt<2>(0h0)
connect _error_WIRE[5], UInt<2>(0h0)
connect _error_WIRE[6], UInt<2>(0h0)
connect _error_WIRE[7], UInt<2>(0h0)
connect _error_WIRE[8], UInt<2>(0h0)
connect _error_WIRE[9], UInt<2>(0h0)
connect _error_WIRE[10], UInt<2>(0h0)
connect _error_WIRE[11], UInt<2>(0h0)
connect _error_WIRE[12], UInt<2>(0h0)
connect _error_WIRE[13], UInt<2>(0h0)
connect _error_WIRE[14], UInt<2>(0h0)
connect _error_WIRE[15], UInt<2>(0h0)
regreset error : UInt<2>[16], clock, reset, _error_WIRE
node _nodeIn_b_bits_resp_T = or(nodeOut.b.bits.resp, error[nodeOut.b.bits.id])
connect nodeIn.b.bits.resp, _nodeIn_b_bits_resp_T
node shiftAmount = bits(nodeOut.b.bits.id, 3, 0)
node _T_22 = dshl(UInt<1>(0h1), shiftAmount)
node _T_23 = bits(_T_22, 15, 0)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_23, 4, 4)
node _T_29 = bits(_T_23, 5, 5)
node _T_30 = bits(_T_23, 6, 6)
node _T_31 = bits(_T_23, 7, 7)
node _T_32 = bits(_T_23, 8, 8)
node _T_33 = bits(_T_23, 9, 9)
node _T_34 = bits(_T_23, 10, 10)
node _T_35 = bits(_T_23, 11, 11)
node _T_36 = bits(_T_23, 12, 12)
node _T_37 = bits(_T_23, 13, 13)
node _T_38 = bits(_T_23, 14, 14)
node _T_39 = bits(_T_23, 15, 15)
node _T_40 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_41 = and(_T_24, _T_40)
when _T_41 :
node _error_0_T = or(error[0], nodeOut.b.bits.resp)
node _error_0_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_0_T)
connect error[0], _error_0_T_1
node _T_42 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_43 = and(_T_25, _T_42)
when _T_43 :
node _error_1_T = or(error[1], nodeOut.b.bits.resp)
node _error_1_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_1_T)
connect error[1], _error_1_T_1
node _T_44 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_45 = and(_T_26, _T_44)
when _T_45 :
node _error_2_T = or(error[2], nodeOut.b.bits.resp)
node _error_2_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_2_T)
connect error[2], _error_2_T_1
node _T_46 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_47 = and(_T_27, _T_46)
when _T_47 :
node _error_3_T = or(error[3], nodeOut.b.bits.resp)
node _error_3_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_3_T)
connect error[3], _error_3_T_1
node _T_48 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_49 = and(_T_28, _T_48)
when _T_49 :
node _error_4_T = or(error[4], nodeOut.b.bits.resp)
node _error_4_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_4_T)
connect error[4], _error_4_T_1
node _T_50 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_51 = and(_T_29, _T_50)
when _T_51 :
node _error_5_T = or(error[5], nodeOut.b.bits.resp)
node _error_5_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_5_T)
connect error[5], _error_5_T_1
node _T_52 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_53 = and(_T_30, _T_52)
when _T_53 :
node _error_6_T = or(error[6], nodeOut.b.bits.resp)
node _error_6_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_6_T)
connect error[6], _error_6_T_1
node _T_54 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_55 = and(_T_31, _T_54)
when _T_55 :
node _error_7_T = or(error[7], nodeOut.b.bits.resp)
node _error_7_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_7_T)
connect error[7], _error_7_T_1
node _T_56 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_57 = and(_T_32, _T_56)
when _T_57 :
node _error_8_T = or(error[8], nodeOut.b.bits.resp)
node _error_8_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_8_T)
connect error[8], _error_8_T_1
node _T_58 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_59 = and(_T_33, _T_58)
when _T_59 :
node _error_9_T = or(error[9], nodeOut.b.bits.resp)
node _error_9_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_9_T)
connect error[9], _error_9_T_1
node _T_60 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_61 = and(_T_34, _T_60)
when _T_61 :
node _error_10_T = or(error[10], nodeOut.b.bits.resp)
node _error_10_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_10_T)
connect error[10], _error_10_T_1
node _T_62 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_63 = and(_T_35, _T_62)
when _T_63 :
node _error_11_T = or(error[11], nodeOut.b.bits.resp)
node _error_11_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_11_T)
connect error[11], _error_11_T_1
node _T_64 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_65 = and(_T_36, _T_64)
when _T_65 :
node _error_12_T = or(error[12], nodeOut.b.bits.resp)
node _error_12_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_12_T)
connect error[12], _error_12_T_1
node _T_66 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_67 = and(_T_37, _T_66)
when _T_67 :
node _error_13_T = or(error[13], nodeOut.b.bits.resp)
node _error_13_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_13_T)
connect error[13], _error_13_T_1
node _T_68 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_69 = and(_T_38, _T_68)
when _T_69 :
node _error_14_T = or(error[14], nodeOut.b.bits.resp)
node _error_14_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_14_T)
connect error[14], _error_14_T_1
node _T_70 = and(nodeOut.b.ready, nodeOut.b.valid)
node _T_71 = and(_T_39, _T_70)
when _T_71 :
node _error_15_T = or(error[15], nodeOut.b.bits.resp)
node _error_15_T_1 = mux(nodeOut.b.bits.echo.real_last, UInt<1>(0h0), _error_15_T)
connect error[15], _error_15_T_1 | module AXI4Fragmenter_1( // @[Fragmenter.scala:37:9]
input clock, // @[Fragmenter.scala:37:9]
input reset, // @[Fragmenter.scala:37:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_echo_real_last, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
wire irr_1_valid; // @[Decoupled.scala:401:19]
wire [2:0] irr_1_bits_prot; // @[Decoupled.scala:401:19]
wire [3:0] irr_1_bits_cache; // @[Decoupled.scala:401:19]
wire irr_1_bits_lock; // @[Decoupled.scala:401:19]
wire [1:0] irr_1_bits_burst; // @[Decoupled.scala:401:19]
wire [2:0] irr_1_bits_size; // @[Decoupled.scala:401:19]
wire [3:0] irr_1_bits_id; // @[Decoupled.scala:401:19]
wire irr_valid; // @[Decoupled.scala:401:19]
wire [2:0] irr_bits_prot; // @[Decoupled.scala:401:19]
wire [3:0] irr_bits_cache; // @[Decoupled.scala:401:19]
wire irr_bits_lock; // @[Decoupled.scala:401:19]
wire [1:0] irr_bits_burst; // @[Decoupled.scala:401:19]
wire [2:0] irr_bits_size; // @[Decoupled.scala:401:19]
wire [3:0] irr_bits_id; // @[Decoupled.scala:401:19]
wire auto_in_aw_valid_0 = auto_in_aw_valid; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_aw_bits_id_0 = auto_in_aw_bits_id; // @[Fragmenter.scala:37:9]
wire [28:0] auto_in_aw_bits_addr_0 = auto_in_aw_bits_addr; // @[Fragmenter.scala:37:9]
wire [7:0] auto_in_aw_bits_len_0 = auto_in_aw_bits_len; // @[Fragmenter.scala:37:9]
wire [2:0] auto_in_aw_bits_size_0 = auto_in_aw_bits_size; // @[Fragmenter.scala:37:9]
wire [1:0] auto_in_aw_bits_burst_0 = auto_in_aw_bits_burst; // @[Fragmenter.scala:37:9]
wire auto_in_aw_bits_lock_0 = auto_in_aw_bits_lock; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_aw_bits_cache_0 = auto_in_aw_bits_cache; // @[Fragmenter.scala:37:9]
wire [2:0] auto_in_aw_bits_prot_0 = auto_in_aw_bits_prot; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_aw_bits_qos_0 = auto_in_aw_bits_qos; // @[Fragmenter.scala:37:9]
wire auto_in_w_valid_0 = auto_in_w_valid; // @[Fragmenter.scala:37:9]
wire [63:0] auto_in_w_bits_data_0 = auto_in_w_bits_data; // @[Fragmenter.scala:37:9]
wire [7:0] auto_in_w_bits_strb_0 = auto_in_w_bits_strb; // @[Fragmenter.scala:37:9]
wire auto_in_w_bits_last_0 = auto_in_w_bits_last; // @[Fragmenter.scala:37:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Fragmenter.scala:37:9]
wire auto_in_ar_valid_0 = auto_in_ar_valid; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_ar_bits_id_0 = auto_in_ar_bits_id; // @[Fragmenter.scala:37:9]
wire [28:0] auto_in_ar_bits_addr_0 = auto_in_ar_bits_addr; // @[Fragmenter.scala:37:9]
wire [7:0] auto_in_ar_bits_len_0 = auto_in_ar_bits_len; // @[Fragmenter.scala:37:9]
wire [2:0] auto_in_ar_bits_size_0 = auto_in_ar_bits_size; // @[Fragmenter.scala:37:9]
wire [1:0] auto_in_ar_bits_burst_0 = auto_in_ar_bits_burst; // @[Fragmenter.scala:37:9]
wire auto_in_ar_bits_lock_0 = auto_in_ar_bits_lock; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_ar_bits_cache_0 = auto_in_ar_bits_cache; // @[Fragmenter.scala:37:9]
wire [2:0] auto_in_ar_bits_prot_0 = auto_in_ar_bits_prot; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_ar_bits_qos_0 = auto_in_ar_bits_qos; // @[Fragmenter.scala:37:9]
wire auto_in_r_ready_0 = auto_in_r_ready; // @[Fragmenter.scala:37:9]
wire auto_out_aw_ready_0 = auto_out_aw_ready; // @[Fragmenter.scala:37:9]
wire auto_out_w_ready_0 = auto_out_w_ready; // @[Fragmenter.scala:37:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_b_bits_id_0 = auto_out_b_bits_id; // @[Fragmenter.scala:37:9]
wire [1:0] auto_out_b_bits_resp_0 = auto_out_b_bits_resp; // @[Fragmenter.scala:37:9]
wire auto_out_b_bits_echo_real_last_0 = auto_out_b_bits_echo_real_last; // @[Fragmenter.scala:37:9]
wire auto_out_ar_ready_0 = auto_out_ar_ready; // @[Fragmenter.scala:37:9]
wire auto_out_r_valid_0 = auto_out_r_valid; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_r_bits_id_0 = auto_out_r_bits_id; // @[Fragmenter.scala:37:9]
wire [63:0] auto_out_r_bits_data_0 = auto_out_r_bits_data; // @[Fragmenter.scala:37:9]
wire [1:0] auto_out_r_bits_resp_0 = auto_out_r_bits_resp; // @[Fragmenter.scala:37:9]
wire auto_out_r_bits_echo_real_last_0 = auto_out_r_bits_echo_real_last; // @[Fragmenter.scala:37:9]
wire auto_out_r_bits_last_0 = auto_out_r_bits_last; // @[Fragmenter.scala:37:9]
wire [7:0] auto_out_aw_bits_len = 8'h0; // @[Fragmenter.scala:37:9]
wire [7:0] auto_out_ar_bits_len = 8'h0; // @[Fragmenter.scala:37:9]
wire [7:0] nodeOut_aw_bits_len = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_ar_bits_len = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] in_ar_bits_len = 8'h0; // @[Fragmenter.scala:66:23]
wire [7:0] maxSupported1 = 8'h0; // @[Fragmenter.scala:97:46]
wire [7:0] beats1 = 8'h0; // @[Fragmenter.scala:105:25]
wire [7:0] in_aw_bits_len = 8'h0; // @[Fragmenter.scala:66:23]
wire [7:0] maxSupported1_1 = 8'h0; // @[Fragmenter.scala:97:46]
wire [7:0] beats1_1 = 8'h0; // @[Fragmenter.scala:105:25]
wire [1:0] _error_WIRE_0 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_1 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_2 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_3 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_4 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_5 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_6 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_7 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_8 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_9 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_10 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_11 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_12 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_13 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_14 = 2'h0; // @[Fragmenter.scala:211:60]
wire [1:0] _error_WIRE_15 = 2'h0; // @[Fragmenter.scala:211:60]
wire [8:0] _beats_T_1 = 9'h1; // @[package.scala:241:40]
wire [8:0] beats = 9'h1; // @[package.scala:241:47]
wire [8:0] _beats_T_5 = 9'h1; // @[package.scala:241:40]
wire [8:0] w_beats = 9'h1; // @[package.scala:241:47]
wire [8:0] _beats_T_3 = 9'h1FF; // @[package.scala:241:49]
wire [8:0] _beats_T_7 = 9'h1FF; // @[package.scala:241:49]
wire [8:0] _beats_T = 9'h0; // @[package.scala:241:35]
wire [8:0] _beats_T_2 = 9'h0; // @[package.scala:241:53]
wire [8:0] _beats_T_4 = 9'h0; // @[package.scala:241:35]
wire [8:0] _beats_T_6 = 9'h0; // @[package.scala:241:53]
wire _support1_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _support1_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire [29:0] _support1_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _support1_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _support1_T_7 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _support1_T_8 = 30'h0; // @[Parameters.scala:137:46]
wire nodeIn_aw_ready; // @[MixedNode.scala:551:17]
wire nodeIn_aw_valid = auto_in_aw_valid_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_aw_bits_id = auto_in_aw_bits_id_0; // @[Fragmenter.scala:37:9]
wire [28:0] nodeIn_aw_bits_addr = auto_in_aw_bits_addr_0; // @[Fragmenter.scala:37:9]
wire [7:0] nodeIn_aw_bits_len = auto_in_aw_bits_len_0; // @[Fragmenter.scala:37:9]
wire [2:0] nodeIn_aw_bits_size = auto_in_aw_bits_size_0; // @[Fragmenter.scala:37:9]
wire [1:0] nodeIn_aw_bits_burst = auto_in_aw_bits_burst_0; // @[Fragmenter.scala:37:9]
wire nodeIn_aw_bits_lock = auto_in_aw_bits_lock_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_aw_bits_cache = auto_in_aw_bits_cache_0; // @[Fragmenter.scala:37:9]
wire [2:0] nodeIn_aw_bits_prot = auto_in_aw_bits_prot_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_aw_bits_qos = auto_in_aw_bits_qos_0; // @[Fragmenter.scala:37:9]
wire nodeIn_w_ready; // @[MixedNode.scala:551:17]
wire nodeIn_w_valid = auto_in_w_valid_0; // @[Fragmenter.scala:37:9]
wire [63:0] nodeIn_w_bits_data = auto_in_w_bits_data_0; // @[Fragmenter.scala:37:9]
wire [7:0] nodeIn_w_bits_strb = auto_in_w_bits_strb_0; // @[Fragmenter.scala:37:9]
wire nodeIn_w_bits_last = auto_in_w_bits_last_0; // @[Fragmenter.scala:37:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Fragmenter.scala:37:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_id; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_ar_ready; // @[MixedNode.scala:551:17]
wire nodeIn_ar_valid = auto_in_ar_valid_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_ar_bits_id = auto_in_ar_bits_id_0; // @[Fragmenter.scala:37:9]
wire [28:0] nodeIn_ar_bits_addr = auto_in_ar_bits_addr_0; // @[Fragmenter.scala:37:9]
wire [7:0] nodeIn_ar_bits_len = auto_in_ar_bits_len_0; // @[Fragmenter.scala:37:9]
wire [2:0] nodeIn_ar_bits_size = auto_in_ar_bits_size_0; // @[Fragmenter.scala:37:9]
wire [1:0] nodeIn_ar_bits_burst = auto_in_ar_bits_burst_0; // @[Fragmenter.scala:37:9]
wire nodeIn_ar_bits_lock = auto_in_ar_bits_lock_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_ar_bits_cache = auto_in_ar_bits_cache_0; // @[Fragmenter.scala:37:9]
wire [2:0] nodeIn_ar_bits_prot = auto_in_ar_bits_prot_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeIn_ar_bits_qos = auto_in_ar_bits_qos_0; // @[Fragmenter.scala:37:9]
wire nodeIn_r_ready = auto_in_r_ready_0; // @[Fragmenter.scala:37:9]
wire nodeIn_r_valid; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_r_bits_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_r_bits_data; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_r_bits_resp; // @[MixedNode.scala:551:17]
wire nodeIn_r_bits_last; // @[MixedNode.scala:551:17]
wire nodeOut_aw_ready = auto_out_aw_ready_0; // @[Fragmenter.scala:37:9]
wire nodeOut_aw_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_id; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_aw_bits_addr; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_aw_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_aw_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_aw_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_aw_bits_echo_real_last; // @[MixedNode.scala:542:17]
wire nodeOut_w_ready = auto_out_w_ready_0; // @[Fragmenter.scala:37:9]
wire nodeOut_w_valid; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_w_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_w_bits_strb; // @[MixedNode.scala:542:17]
wire nodeOut_w_bits_last; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeOut_b_bits_id = auto_out_b_bits_id_0; // @[Fragmenter.scala:37:9]
wire [1:0] nodeOut_b_bits_resp = auto_out_b_bits_resp_0; // @[Fragmenter.scala:37:9]
wire nodeOut_b_bits_echo_real_last = auto_out_b_bits_echo_real_last_0; // @[Fragmenter.scala:37:9]
wire nodeOut_ar_ready = auto_out_ar_ready_0; // @[Fragmenter.scala:37:9]
wire nodeOut_ar_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_id; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_ar_bits_addr; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_ar_bits_burst; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_lock; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_cache; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_ar_bits_prot; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_ar_bits_qos; // @[MixedNode.scala:542:17]
wire nodeOut_ar_bits_echo_real_last; // @[MixedNode.scala:542:17]
wire nodeOut_r_ready; // @[MixedNode.scala:542:17]
wire nodeOut_r_valid = auto_out_r_valid_0; // @[Fragmenter.scala:37:9]
wire [3:0] nodeOut_r_bits_id = auto_out_r_bits_id_0; // @[Fragmenter.scala:37:9]
wire [63:0] nodeOut_r_bits_data = auto_out_r_bits_data_0; // @[Fragmenter.scala:37:9]
wire [1:0] nodeOut_r_bits_resp = auto_out_r_bits_resp_0; // @[Fragmenter.scala:37:9]
wire nodeOut_r_bits_echo_real_last = auto_out_r_bits_echo_real_last_0; // @[Fragmenter.scala:37:9]
wire nodeOut_r_bits_last = auto_out_r_bits_last_0; // @[Fragmenter.scala:37:9]
wire auto_in_aw_ready_0; // @[Fragmenter.scala:37:9]
wire auto_in_w_ready_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_b_bits_id_0; // @[Fragmenter.scala:37:9]
wire [1:0] auto_in_b_bits_resp_0; // @[Fragmenter.scala:37:9]
wire auto_in_b_valid_0; // @[Fragmenter.scala:37:9]
wire auto_in_ar_ready_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_in_r_bits_id_0; // @[Fragmenter.scala:37:9]
wire [63:0] auto_in_r_bits_data_0; // @[Fragmenter.scala:37:9]
wire [1:0] auto_in_r_bits_resp_0; // @[Fragmenter.scala:37:9]
wire auto_in_r_bits_last_0; // @[Fragmenter.scala:37:9]
wire auto_in_r_valid_0; // @[Fragmenter.scala:37:9]
wire auto_out_aw_bits_echo_real_last_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_aw_bits_id_0; // @[Fragmenter.scala:37:9]
wire [28:0] auto_out_aw_bits_addr_0; // @[Fragmenter.scala:37:9]
wire [2:0] auto_out_aw_bits_size_0; // @[Fragmenter.scala:37:9]
wire [1:0] auto_out_aw_bits_burst_0; // @[Fragmenter.scala:37:9]
wire auto_out_aw_bits_lock_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_aw_bits_cache_0; // @[Fragmenter.scala:37:9]
wire [2:0] auto_out_aw_bits_prot_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_aw_bits_qos_0; // @[Fragmenter.scala:37:9]
wire auto_out_aw_valid_0; // @[Fragmenter.scala:37:9]
wire [63:0] auto_out_w_bits_data_0; // @[Fragmenter.scala:37:9]
wire [7:0] auto_out_w_bits_strb_0; // @[Fragmenter.scala:37:9]
wire auto_out_w_bits_last_0; // @[Fragmenter.scala:37:9]
wire auto_out_w_valid_0; // @[Fragmenter.scala:37:9]
wire auto_out_b_ready_0; // @[Fragmenter.scala:37:9]
wire auto_out_ar_bits_echo_real_last_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_ar_bits_id_0; // @[Fragmenter.scala:37:9]
wire [28:0] auto_out_ar_bits_addr_0; // @[Fragmenter.scala:37:9]
wire [2:0] auto_out_ar_bits_size_0; // @[Fragmenter.scala:37:9]
wire [1:0] auto_out_ar_bits_burst_0; // @[Fragmenter.scala:37:9]
wire auto_out_ar_bits_lock_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_ar_bits_cache_0; // @[Fragmenter.scala:37:9]
wire [2:0] auto_out_ar_bits_prot_0; // @[Fragmenter.scala:37:9]
wire [3:0] auto_out_ar_bits_qos_0; // @[Fragmenter.scala:37:9]
wire auto_out_ar_valid_0; // @[Fragmenter.scala:37:9]
wire auto_out_r_ready_0; // @[Fragmenter.scala:37:9]
assign auto_in_aw_ready_0 = nodeIn_aw_ready; // @[Fragmenter.scala:37:9]
assign auto_in_w_ready_0 = nodeIn_w_ready; // @[Fragmenter.scala:37:9]
wire _nodeIn_b_valid_T; // @[Fragmenter.scala:207:33]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Fragmenter.scala:37:9]
assign auto_in_b_bits_id_0 = nodeIn_b_bits_id; // @[Fragmenter.scala:37:9]
wire [1:0] _nodeIn_b_bits_resp_T; // @[Fragmenter.scala:212:41]
assign auto_in_b_bits_resp_0 = nodeIn_b_bits_resp; // @[Fragmenter.scala:37:9]
assign auto_in_ar_ready_0 = nodeIn_ar_ready; // @[Fragmenter.scala:37:9]
assign nodeOut_r_ready = nodeIn_r_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_r_valid_0 = nodeIn_r_valid; // @[Fragmenter.scala:37:9]
assign auto_in_r_bits_id_0 = nodeIn_r_bits_id; // @[Fragmenter.scala:37:9]
assign auto_in_r_bits_data_0 = nodeIn_r_bits_data; // @[Fragmenter.scala:37:9]
assign auto_in_r_bits_resp_0 = nodeIn_r_bits_resp; // @[Fragmenter.scala:37:9]
wire _nodeIn_r_bits_last_T; // @[Fragmenter.scala:198:41]
assign auto_in_r_bits_last_0 = nodeIn_r_bits_last; // @[Fragmenter.scala:37:9]
wire _nodeOut_aw_valid_T_1; // @[Fragmenter.scala:167:35]
assign auto_out_aw_valid_0 = nodeOut_aw_valid; // @[Fragmenter.scala:37:9]
wire [3:0] in_aw_bits_id; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_id_0 = nodeOut_aw_bits_id; // @[Fragmenter.scala:37:9]
wire [28:0] in_aw_bits_addr; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_addr_0 = nodeOut_aw_bits_addr; // @[Fragmenter.scala:37:9]
wire [2:0] in_aw_bits_size; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_size_0 = nodeOut_aw_bits_size; // @[Fragmenter.scala:37:9]
wire [1:0] in_aw_bits_burst; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_burst_0 = nodeOut_aw_bits_burst; // @[Fragmenter.scala:37:9]
wire in_aw_bits_lock; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_lock_0 = nodeOut_aw_bits_lock; // @[Fragmenter.scala:37:9]
wire [3:0] in_aw_bits_cache; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_cache_0 = nodeOut_aw_bits_cache; // @[Fragmenter.scala:37:9]
wire [2:0] in_aw_bits_prot; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_prot_0 = nodeOut_aw_bits_prot; // @[Fragmenter.scala:37:9]
wire [3:0] in_aw_bits_qos; // @[Fragmenter.scala:66:23]
assign auto_out_aw_bits_qos_0 = nodeOut_aw_bits_qos; // @[Fragmenter.scala:37:9]
wire aw_last; // @[Fragmenter.scala:118:27]
assign auto_out_aw_bits_echo_real_last_0 = nodeOut_aw_bits_echo_real_last; // @[Fragmenter.scala:37:9]
wire _nodeOut_w_valid_T_2; // @[Fragmenter.scala:185:33]
assign auto_out_w_valid_0 = nodeOut_w_valid; // @[Fragmenter.scala:37:9]
wire [63:0] in_w_bits_data; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_data_0 = nodeOut_w_bits_data; // @[Fragmenter.scala:37:9]
wire [7:0] in_w_bits_strb; // @[Decoupled.scala:401:19]
assign auto_out_w_bits_strb_0 = nodeOut_w_bits_strb; // @[Fragmenter.scala:37:9]
wire w_last; // @[Fragmenter.scala:179:27]
assign auto_out_w_bits_last_0 = nodeOut_w_bits_last; // @[Fragmenter.scala:37:9]
wire _nodeOut_b_ready_T_1; // @[Fragmenter.scala:208:33]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Fragmenter.scala:37:9]
assign nodeIn_b_bits_id = nodeOut_b_bits_id; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] shiftAmount = nodeOut_b_bits_id; // @[OneHot.scala:64:49]
wire in_ar_ready = nodeOut_ar_ready; // @[Fragmenter.scala:66:23]
wire in_ar_valid; // @[Fragmenter.scala:66:23]
assign auto_out_ar_valid_0 = nodeOut_ar_valid; // @[Fragmenter.scala:37:9]
wire [3:0] in_ar_bits_id; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_id_0 = nodeOut_ar_bits_id; // @[Fragmenter.scala:37:9]
wire [28:0] in_ar_bits_addr; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_addr_0 = nodeOut_ar_bits_addr; // @[Fragmenter.scala:37:9]
wire [2:0] in_ar_bits_size; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_size_0 = nodeOut_ar_bits_size; // @[Fragmenter.scala:37:9]
wire [1:0] in_ar_bits_burst; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_burst_0 = nodeOut_ar_bits_burst; // @[Fragmenter.scala:37:9]
wire in_ar_bits_lock; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_lock_0 = nodeOut_ar_bits_lock; // @[Fragmenter.scala:37:9]
wire [3:0] in_ar_bits_cache; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_cache_0 = nodeOut_ar_bits_cache; // @[Fragmenter.scala:37:9]
wire [2:0] in_ar_bits_prot; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_prot_0 = nodeOut_ar_bits_prot; // @[Fragmenter.scala:37:9]
wire [3:0] in_ar_bits_qos; // @[Fragmenter.scala:66:23]
assign auto_out_ar_bits_qos_0 = nodeOut_ar_bits_qos; // @[Fragmenter.scala:37:9]
wire ar_last; // @[Fragmenter.scala:118:27]
assign auto_out_ar_bits_echo_real_last_0 = nodeOut_ar_bits_echo_real_last; // @[Fragmenter.scala:37:9]
assign auto_out_r_ready_0 = nodeOut_r_ready; // @[Fragmenter.scala:37:9]
assign nodeIn_r_valid = nodeOut_r_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_id = nodeOut_r_bits_id; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_data = nodeOut_r_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_r_bits_resp = nodeOut_r_bits_resp; // @[MixedNode.scala:542:17, :551:17]
wire _irr_ready_T; // @[Fragmenter.scala:119:30]
assign in_ar_valid = irr_valid; // @[Decoupled.scala:401:19]
assign in_ar_bits_id = irr_bits_id; // @[Decoupled.scala:401:19]
assign in_ar_bits_size = irr_bits_size; // @[Decoupled.scala:401:19]
assign in_ar_bits_burst = irr_bits_burst; // @[Decoupled.scala:401:19]
assign in_ar_bits_lock = irr_bits_lock; // @[Decoupled.scala:401:19]
assign in_ar_bits_cache = irr_bits_cache; // @[Decoupled.scala:401:19]
assign in_ar_bits_prot = irr_bits_prot; // @[Decoupled.scala:401:19]
wire [28:0] irr_bits_addr; // @[Decoupled.scala:401:19]
wire [7:0] irr_bits_len; // @[Decoupled.scala:401:19]
wire [3:0] irr_bits_qos; // @[Decoupled.scala:401:19]
assign in_ar_bits_qos = irr_bits_qos; // @[Decoupled.scala:401:19]
wire irr_ready; // @[Decoupled.scala:401:19]
assign nodeOut_ar_valid = in_ar_valid; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_id = in_ar_bits_id; // @[Fragmenter.scala:66:23]
wire [28:0] _out_bits_addr_T_5; // @[Fragmenter.scala:130:26]
assign nodeOut_ar_bits_addr = in_ar_bits_addr; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_size = in_ar_bits_size; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_burst = in_ar_bits_burst; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_lock = in_ar_bits_lock; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_cache = in_ar_bits_cache; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_prot = in_ar_bits_prot; // @[Fragmenter.scala:66:23]
assign nodeOut_ar_bits_qos = in_ar_bits_qos; // @[Fragmenter.scala:66:23]
reg busy; // @[Fragmenter.scala:68:29]
reg [28:0] r_addr; // @[Fragmenter.scala:69:25]
reg [7:0] r_len; // @[Fragmenter.scala:70:25]
wire [7:0] len = busy ? r_len : irr_bits_len; // @[Decoupled.scala:401:19]
wire [28:0] addr = busy ? r_addr : irr_bits_addr; // @[Decoupled.scala:401:19]
wire [28:0] _support1_T = addr; // @[Parameters.scala:137:31]
wire [2:0] lo = addr[2:0]; // @[Fragmenter.scala:73:23, :75:49]
wire [7:0] alignment = addr[10:3]; // @[Fragmenter.scala:73:23, :77:29]
wire [29:0] _support1_T_1 = {1'h0, _support1_T}; // @[Parameters.scala:137:{31,41}]
wire [6:0] _fillLow_T = len[7:1]; // @[package.scala:262:48]
wire [7:0] _fillLow_T_1 = {len[7], len[6:0] | _fillLow_T}; // @[package.scala:262:{43,48}]
wire [5:0] _fillLow_T_2 = _fillLow_T_1[7:2]; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_3 = {_fillLow_T_1[7:6], _fillLow_T_1[5:0] | _fillLow_T_2}; // @[package.scala:262:{43,48}]
wire [3:0] _fillLow_T_4 = _fillLow_T_3[7:4]; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_5 = {_fillLow_T_4, _fillLow_T_3[3:0] | _fillLow_T_4}; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_6 = _fillLow_T_5; // @[package.scala:262:43, :263:17]
wire [6:0] fillLow = _fillLow_T_6[7:1]; // @[package.scala:263:17]
wire [7:0] _wipeHigh_T = ~len; // @[Fragmenter.scala:72:23, :94:33]
wire [8:0] _wipeHigh_T_1 = {_wipeHigh_T, 1'h0}; // @[package.scala:253:48]
wire [7:0] _wipeHigh_T_2 = _wipeHigh_T_1[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_3 = _wipeHigh_T | _wipeHigh_T_2; // @[package.scala:253:{43,53}]
wire [9:0] _wipeHigh_T_4 = {_wipeHigh_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _wipeHigh_T_5 = _wipeHigh_T_4[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_6 = _wipeHigh_T_3 | _wipeHigh_T_5; // @[package.scala:253:{43,53}]
wire [11:0] _wipeHigh_T_7 = {_wipeHigh_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _wipeHigh_T_8 = _wipeHigh_T_7[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_9 = _wipeHigh_T_6 | _wipeHigh_T_8; // @[package.scala:253:{43,53}]
wire [7:0] _wipeHigh_T_10 = _wipeHigh_T_9; // @[package.scala:253:43, :254:17]
wire [7:0] wipeHigh = ~_wipeHigh_T_10; // @[package.scala:254:17]
wire [7:0] remain1 = {1'h0, fillLow} | wipeHigh; // @[Fragmenter.scala:93:37, :94:24, :95:32]
wire [8:0] _align1_T = {alignment, 1'h0}; // @[package.scala:253:48]
wire [7:0] _align1_T_1 = _align1_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_2 = alignment | _align1_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _align1_T_3 = {_align1_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _align1_T_4 = _align1_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_5 = _align1_T_2 | _align1_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _align1_T_6 = {_align1_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _align1_T_7 = _align1_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_8 = _align1_T_5 | _align1_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _align1_T_9 = _align1_T_8; // @[package.scala:253:43, :254:17]
wire [7:0] align1 = ~_align1_T_9; // @[package.scala:254:17]
wire [7:0] _maxSupported1_T = remain1 & align1; // @[Fragmenter.scala:95:32, :96:24, :97:37]
wire fixed = irr_bits_burst == 2'h0; // @[Decoupled.scala:401:19]
wire narrow = irr_bits_size != 3'h3; // @[Decoupled.scala:401:19]
wire bad = fixed | narrow; // @[Fragmenter.scala:100:34, :101:34, :102:25]
wire [15:0] _inc_addr_T = 16'h1 << irr_bits_size; // @[Decoupled.scala:401:19]
wire [29:0] _inc_addr_T_1 = {1'h0, addr} + {14'h0, _inc_addr_T}; // @[Fragmenter.scala:73:23, :108:{29,38}]
wire [28:0] inc_addr = _inc_addr_T_1[28:0]; // @[Fragmenter.scala:108:29]
wire [15:0] _wrapMask_T = {irr_bits_len, 8'hFF}; // @[Decoupled.scala:401:19]
wire [22:0] _wrapMask_T_1 = {7'h0, _wrapMask_T} << irr_bits_size; // @[Decoupled.scala:401:19]
wire [14:0] wrapMask = _wrapMask_T_1[22:8]; // @[Bundles.scala:33:{21,30}]
wire [28:0] mux_addr; // @[Fragmenter.scala:110:35]
wire [28:0] _mux_addr_T = {14'h0, inc_addr[14:0] & wrapMask}; // @[Fragmenter.scala:108:29, :112:33]
wire [28:0] _mux_addr_T_1 = ~irr_bits_addr; // @[Decoupled.scala:401:19]
wire [28:0] _mux_addr_T_2 = {_mux_addr_T_1[28:15], _mux_addr_T_1[14:0] | wrapMask}; // @[Fragmenter.scala:112:{49,62}]
wire [28:0] _mux_addr_T_3 = ~_mux_addr_T_2; // @[Fragmenter.scala:112:{47,62}]
wire [28:0] _mux_addr_T_4 = _mux_addr_T | _mux_addr_T_3; // @[Fragmenter.scala:112:{33,45,47}]
assign mux_addr = fixed ? irr_bits_addr : irr_bits_burst == 2'h2 ? _mux_addr_T_4 : inc_addr; // @[Decoupled.scala:401:19]
assign ar_last = len == 8'h0; // @[Fragmenter.scala:72:23, :118:27]
assign nodeOut_ar_bits_echo_real_last = ar_last; // @[Fragmenter.scala:118:27]
assign _irr_ready_T = in_ar_ready & ar_last; // @[Fragmenter.scala:66:23, :118:27, :119:30]
assign irr_ready = _irr_ready_T; // @[Decoupled.scala:401:19]
wire [28:0] _out_bits_addr_T = ~addr; // @[Fragmenter.scala:73:23, :130:28]
wire [9:0] _out_bits_addr_T_1 = 10'h7 << irr_bits_size; // @[Decoupled.scala:401:19]
wire [2:0] _out_bits_addr_T_2 = _out_bits_addr_T_1[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _out_bits_addr_T_3 = ~_out_bits_addr_T_2; // @[package.scala:243:{46,76}]
wire [28:0] _out_bits_addr_T_4 = {_out_bits_addr_T[28:3], _out_bits_addr_T[2:0] | _out_bits_addr_T_3}; // @[package.scala:243:46]
assign _out_bits_addr_T_5 = ~_out_bits_addr_T_4; // @[Fragmenter.scala:130:{26,34}]
assign in_ar_bits_addr = _out_bits_addr_T_5; // @[Fragmenter.scala:66:23, :130:26]
wire _busy_T = ~ar_last; // @[Fragmenter.scala:118:27, :133:19]
wire [9:0] _r_len_T = {2'h0, len} - 10'h1; // @[Fragmenter.scala:72:23, :135:25]
wire [8:0] _r_len_T_1 = _r_len_T[8:0]; // @[Fragmenter.scala:135:25]
wire _irr_ready_T_1; // @[Fragmenter.scala:119:30]
wire in_aw_valid = irr_1_valid; // @[Decoupled.scala:401:19]
assign in_aw_bits_id = irr_1_bits_id; // @[Decoupled.scala:401:19]
assign in_aw_bits_size = irr_1_bits_size; // @[Decoupled.scala:401:19]
assign in_aw_bits_burst = irr_1_bits_burst; // @[Decoupled.scala:401:19]
assign in_aw_bits_lock = irr_1_bits_lock; // @[Decoupled.scala:401:19]
assign in_aw_bits_cache = irr_1_bits_cache; // @[Decoupled.scala:401:19]
assign in_aw_bits_prot = irr_1_bits_prot; // @[Decoupled.scala:401:19]
wire [28:0] irr_1_bits_addr; // @[Decoupled.scala:401:19]
wire [7:0] irr_1_bits_len; // @[Decoupled.scala:401:19]
wire [3:0] irr_1_bits_qos; // @[Decoupled.scala:401:19]
assign in_aw_bits_qos = irr_1_bits_qos; // @[Decoupled.scala:401:19]
wire irr_1_ready; // @[Decoupled.scala:401:19]
wire _in_aw_ready_T_1; // @[Fragmenter.scala:168:35]
assign nodeOut_aw_bits_id = in_aw_bits_id; // @[Fragmenter.scala:66:23]
wire [28:0] _out_bits_addr_T_11; // @[Fragmenter.scala:130:26]
assign nodeOut_aw_bits_addr = in_aw_bits_addr; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_size = in_aw_bits_size; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_burst = in_aw_bits_burst; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_lock = in_aw_bits_lock; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_cache = in_aw_bits_cache; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_prot = in_aw_bits_prot; // @[Fragmenter.scala:66:23]
assign nodeOut_aw_bits_qos = in_aw_bits_qos; // @[Fragmenter.scala:66:23]
wire in_aw_ready; // @[Fragmenter.scala:66:23]
reg busy_1; // @[Fragmenter.scala:68:29]
reg [28:0] r_addr_1; // @[Fragmenter.scala:69:25]
reg [7:0] r_len_1; // @[Fragmenter.scala:70:25]
wire [7:0] len_1 = busy_1 ? r_len_1 : irr_1_bits_len; // @[Decoupled.scala:401:19]
wire [28:0] addr_1 = busy_1 ? r_addr_1 : irr_1_bits_addr; // @[Decoupled.scala:401:19]
wire [28:0] _support1_T_5 = addr_1; // @[Parameters.scala:137:31]
wire [2:0] lo_1 = addr_1[2:0]; // @[Fragmenter.scala:73:23, :75:49]
wire [7:0] alignment_1 = addr_1[10:3]; // @[Fragmenter.scala:73:23, :77:29]
wire [29:0] _support1_T_6 = {1'h0, _support1_T_5}; // @[Parameters.scala:137:{31,41}]
wire [6:0] _fillLow_T_7 = len_1[7:1]; // @[package.scala:262:48]
wire [7:0] _fillLow_T_8 = {len_1[7], len_1[6:0] | _fillLow_T_7}; // @[package.scala:262:{43,48}]
wire [5:0] _fillLow_T_9 = _fillLow_T_8[7:2]; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_10 = {_fillLow_T_8[7:6], _fillLow_T_8[5:0] | _fillLow_T_9}; // @[package.scala:262:{43,48}]
wire [3:0] _fillLow_T_11 = _fillLow_T_10[7:4]; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_12 = {_fillLow_T_11, _fillLow_T_10[3:0] | _fillLow_T_11}; // @[package.scala:262:{43,48}]
wire [7:0] _fillLow_T_13 = _fillLow_T_12; // @[package.scala:262:43, :263:17]
wire [6:0] fillLow_1 = _fillLow_T_13[7:1]; // @[package.scala:263:17]
wire [7:0] _wipeHigh_T_11 = ~len_1; // @[Fragmenter.scala:72:23, :94:33]
wire [8:0] _wipeHigh_T_12 = {_wipeHigh_T_11, 1'h0}; // @[package.scala:253:48]
wire [7:0] _wipeHigh_T_13 = _wipeHigh_T_12[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_14 = _wipeHigh_T_11 | _wipeHigh_T_13; // @[package.scala:253:{43,53}]
wire [9:0] _wipeHigh_T_15 = {_wipeHigh_T_14, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _wipeHigh_T_16 = _wipeHigh_T_15[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_17 = _wipeHigh_T_14 | _wipeHigh_T_16; // @[package.scala:253:{43,53}]
wire [11:0] _wipeHigh_T_18 = {_wipeHigh_T_17, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _wipeHigh_T_19 = _wipeHigh_T_18[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _wipeHigh_T_20 = _wipeHigh_T_17 | _wipeHigh_T_19; // @[package.scala:253:{43,53}]
wire [7:0] _wipeHigh_T_21 = _wipeHigh_T_20; // @[package.scala:253:43, :254:17]
wire [7:0] wipeHigh_1 = ~_wipeHigh_T_21; // @[package.scala:254:17]
wire [7:0] remain1_1 = {1'h0, fillLow_1} | wipeHigh_1; // @[Fragmenter.scala:93:37, :94:24, :95:32]
wire [8:0] _align1_T_10 = {alignment_1, 1'h0}; // @[package.scala:253:48]
wire [7:0] _align1_T_11 = _align1_T_10[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_12 = alignment_1 | _align1_T_11; // @[package.scala:253:{43,53}]
wire [9:0] _align1_T_13 = {_align1_T_12, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _align1_T_14 = _align1_T_13[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_15 = _align1_T_12 | _align1_T_14; // @[package.scala:253:{43,53}]
wire [11:0] _align1_T_16 = {_align1_T_15, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _align1_T_17 = _align1_T_16[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _align1_T_18 = _align1_T_15 | _align1_T_17; // @[package.scala:253:{43,53}]
wire [7:0] _align1_T_19 = _align1_T_18; // @[package.scala:253:43, :254:17]
wire [7:0] align1_1 = ~_align1_T_19; // @[package.scala:254:17]
wire [7:0] _maxSupported1_T_1 = remain1_1 & align1_1; // @[Fragmenter.scala:95:32, :96:24, :97:37]
wire fixed_1 = irr_1_bits_burst == 2'h0; // @[Decoupled.scala:401:19]
wire narrow_1 = irr_1_bits_size != 3'h3; // @[Decoupled.scala:401:19]
wire bad_1 = fixed_1 | narrow_1; // @[Fragmenter.scala:100:34, :101:34, :102:25]
wire [15:0] _inc_addr_T_2 = 16'h1 << irr_1_bits_size; // @[Decoupled.scala:401:19]
wire [29:0] _inc_addr_T_3 = {1'h0, addr_1} + {14'h0, _inc_addr_T_2}; // @[Fragmenter.scala:73:23, :108:{29,38}]
wire [28:0] inc_addr_1 = _inc_addr_T_3[28:0]; // @[Fragmenter.scala:108:29]
wire [15:0] _wrapMask_T_2 = {irr_1_bits_len, 8'hFF}; // @[Decoupled.scala:401:19]
wire [22:0] _wrapMask_T_3 = {7'h0, _wrapMask_T_2} << irr_1_bits_size; // @[Decoupled.scala:401:19]
wire [14:0] wrapMask_1 = _wrapMask_T_3[22:8]; // @[Bundles.scala:33:{21,30}]
wire [28:0] mux_addr_1; // @[Fragmenter.scala:110:35]
wire [28:0] _mux_addr_T_5 = {14'h0, inc_addr_1[14:0] & wrapMask_1}; // @[Fragmenter.scala:108:29, :112:33]
wire [28:0] _mux_addr_T_6 = ~irr_1_bits_addr; // @[Decoupled.scala:401:19]
wire [28:0] _mux_addr_T_7 = {_mux_addr_T_6[28:15], _mux_addr_T_6[14:0] | wrapMask_1}; // @[Fragmenter.scala:112:{49,62}]
wire [28:0] _mux_addr_T_8 = ~_mux_addr_T_7; // @[Fragmenter.scala:112:{47,62}]
wire [28:0] _mux_addr_T_9 = _mux_addr_T_5 | _mux_addr_T_8; // @[Fragmenter.scala:112:{33,45,47}]
assign mux_addr_1 = fixed_1 ? irr_1_bits_addr : irr_1_bits_burst == 2'h2 ? _mux_addr_T_9 : inc_addr_1; // @[Decoupled.scala:401:19]
assign aw_last = len_1 == 8'h0; // @[Fragmenter.scala:72:23, :118:27]
assign nodeOut_aw_bits_echo_real_last = aw_last; // @[Fragmenter.scala:118:27]
assign _irr_ready_T_1 = in_aw_ready & aw_last; // @[Fragmenter.scala:66:23, :118:27, :119:30]
assign irr_1_ready = _irr_ready_T_1; // @[Decoupled.scala:401:19]
wire [28:0] _out_bits_addr_T_6 = ~addr_1; // @[Fragmenter.scala:73:23, :130:28]
wire [9:0] _out_bits_addr_T_7 = 10'h7 << irr_1_bits_size; // @[Decoupled.scala:401:19]
wire [2:0] _out_bits_addr_T_8 = _out_bits_addr_T_7[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _out_bits_addr_T_9 = ~_out_bits_addr_T_8; // @[package.scala:243:{46,76}]
wire [28:0] _out_bits_addr_T_10 = {_out_bits_addr_T_6[28:3], _out_bits_addr_T_6[2:0] | _out_bits_addr_T_9}; // @[package.scala:243:46]
assign _out_bits_addr_T_11 = ~_out_bits_addr_T_10; // @[Fragmenter.scala:130:{26,34}]
assign in_aw_bits_addr = _out_bits_addr_T_11; // @[Fragmenter.scala:66:23, :130:26]
wire _busy_T_1 = ~aw_last; // @[Fragmenter.scala:118:27, :133:19]
wire [9:0] _r_len_T_2 = {2'h0, len_1} - 10'h1; // @[Fragmenter.scala:72:23, :135:25]
wire [8:0] _r_len_T_3 = _r_len_T_2[8:0]; // @[Fragmenter.scala:135:25]
wire _in_w_ready_T_2; // @[Fragmenter.scala:186:33]
assign nodeOut_w_bits_data = in_w_bits_data; // @[Decoupled.scala:401:19]
assign nodeOut_w_bits_strb = in_w_bits_strb; // @[Decoupled.scala:401:19]
wire in_w_bits_last; // @[Decoupled.scala:401:19]
wire in_w_ready; // @[Decoupled.scala:401:19]
wire in_w_valid; // @[Decoupled.scala:401:19]
reg wbeats_latched; // @[Fragmenter.scala:160:35]
wire w_idle; // @[Fragmenter.scala:177:30]
wire wbeats_ready; // @[Fragmenter.scala:161:30]
wire _wbeats_valid_T_1; // @[Fragmenter.scala:169:35]
wire wbeats_valid; // @[Fragmenter.scala:162:30]
wire _GEN = wbeats_ready | wbeats_latched; // @[Fragmenter.scala:160:35, :161:30, :167:52]
wire _nodeOut_aw_valid_T; // @[Fragmenter.scala:167:52]
assign _nodeOut_aw_valid_T = _GEN; // @[Fragmenter.scala:167:52]
wire _in_aw_ready_T; // @[Fragmenter.scala:168:52]
assign _in_aw_ready_T = _GEN; // @[Fragmenter.scala:167:52, :168:52]
assign _nodeOut_aw_valid_T_1 = in_aw_valid & _nodeOut_aw_valid_T; // @[Fragmenter.scala:66:23, :167:{35,52}]
assign nodeOut_aw_valid = _nodeOut_aw_valid_T_1; // @[Fragmenter.scala:167:35]
assign _in_aw_ready_T_1 = nodeOut_aw_ready & _in_aw_ready_T; // @[Fragmenter.scala:168:{35,52}]
assign in_aw_ready = _in_aw_ready_T_1; // @[Fragmenter.scala:66:23, :168:35]
wire _wbeats_valid_T = ~wbeats_latched; // @[Fragmenter.scala:160:35, :169:38]
assign _wbeats_valid_T_1 = in_aw_valid & _wbeats_valid_T; // @[Fragmenter.scala:66:23, :169:{35,38}]
assign wbeats_valid = _wbeats_valid_T_1; // @[Fragmenter.scala:162:30, :169:35]
reg [8:0] w_counter; // @[Fragmenter.scala:176:30]
assign w_idle = w_counter == 9'h0; // @[Fragmenter.scala:176:30, :177:30]
assign wbeats_ready = w_idle; // @[Fragmenter.scala:161:30, :177:30]
wire [8:0] _w_todo_T = {8'h0, wbeats_valid}; // @[Fragmenter.scala:162:30, :178:35]
wire [8:0] w_todo = w_idle ? _w_todo_T : w_counter; // @[Fragmenter.scala:176:30, :177:30, :178:{23,35}]
assign w_last = w_todo == 9'h1; // @[Fragmenter.scala:178:23, :179:27]
assign nodeOut_w_bits_last = w_last; // @[Fragmenter.scala:179:27]
wire _w_counter_T = nodeOut_w_ready & nodeOut_w_valid; // @[Decoupled.scala:51:35]
wire [9:0] _w_counter_T_1 = {1'h0, w_todo} - {9'h0, _w_counter_T}; // @[Decoupled.scala:51:35]
wire [8:0] _w_counter_T_2 = _w_counter_T_1[8:0]; // @[Fragmenter.scala:180:27]
wire _nodeOut_w_valid_T = ~wbeats_ready; // @[Fragmenter.scala:161:30, :185:37]
wire _nodeOut_w_valid_T_1 = _nodeOut_w_valid_T | wbeats_valid; // @[Fragmenter.scala:162:30, :185:{37,51}]
assign _nodeOut_w_valid_T_2 = in_w_valid & _nodeOut_w_valid_T_1; // @[Decoupled.scala:401:19]
assign nodeOut_w_valid = _nodeOut_w_valid_T_2; // @[Fragmenter.scala:185:33]
wire _in_w_ready_T = ~wbeats_ready; // @[Fragmenter.scala:161:30, :185:37, :186:37]
wire _in_w_ready_T_1 = _in_w_ready_T | wbeats_valid; // @[Fragmenter.scala:162:30, :186:{37,51}]
assign _in_w_ready_T_2 = nodeOut_w_ready & _in_w_ready_T_1; // @[Fragmenter.scala:186:{33,51}]
assign in_w_ready = _in_w_ready_T_2; // @[Decoupled.scala:401:19] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_24 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit_24
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0he), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_13 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0hf), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_14 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h10), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h11), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = or(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_17 = or(_q_io_enq_bits_ingress_id_T_16, _q_io_enq_bits_ingress_id_T_14)
node _q_io_enq_bits_ingress_id_T_18 = or(_q_io_enq_bits_ingress_id_T_17, _q_io_enq_bits_ingress_id_T_15)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_18
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_24( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_47 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_47( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_59 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_99 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<5>, vc_free : UInt<5>}}
wire _in_flight_WIRE : UInt<1>[5]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
regreset in_flight : UInt<1>[5], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = or(_T_10, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_16 = or(_T_15, UInt<1>(0h0))
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_21 = or(_T_20, UInt<1>(0h0))
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_21, UInt<1>(0h1), "") : assert_4
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_42 = and(_T_40, _T_41)
node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(_T_32, _T_39)
node _T_48 = or(_T_47, _T_46)
node _T_49 = or(_T_25, _T_48)
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5 | module NoCMonitor_99( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 3'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 3'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 3'h3; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_3 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<8>(0hff))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0)
node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8)
node idx_history = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 7, 0)
node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0)
node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8)
node tag_history = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1)
node _tag_T = shr(_T_1, 8)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 7, 0)
smem tage_u_16 : UInt<1>[8] [256]
smem tage_table_16 : UInt<12>[4] [256]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
wire s2_req_rus : UInt<1>[8]
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
connect io.f2_resp[0].valid, s2_req_rhits[0]
node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0])
connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T
connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr
connect io.f2_resp[1].valid, s2_req_rhits[1]
node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2])
connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T
connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr
connect io.f2_resp[2].valid, s2_req_rhits[2]
node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4])
connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T
connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr
connect io.f2_resp[3].valid, s2_req_rhits[3]
node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6])
connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T
connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr
regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _clear_u_hi_T = bits(clear_u_ctr, 19, 19)
node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1))
node _clear_u_lo_T = bits(clear_u_ctr, 19, 19)
node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0))
node clear_u_idx = shr(clear_u_ctr, 11)
wire _clear_u_mask_WIRE : UInt<1>[8]
connect _clear_u_mask_WIRE[0], clear_u_lo
connect _clear_u_mask_WIRE[1], clear_u_hi
connect _clear_u_mask_WIRE[2], clear_u_lo
connect _clear_u_mask_WIRE[3], clear_u_hi
connect _clear_u_mask_WIRE[4], clear_u_lo
connect _clear_u_mask_WIRE[5], clear_u_hi
connect _clear_u_mask_WIRE[6], clear_u_lo
connect _clear_u_mask_WIRE[7], clear_u_hi
node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0])
node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2])
node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo)
node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4])
node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6])
node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo)
node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo)
node _T_2 = shr(io.update_pc, 4)
node idx_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0)
node idx_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8)
node idx_history_1 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 7, 0)
node tag_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0)
node tag_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8)
node tag_history_1 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1)
node _tag_T_2 = shr(_T_2, 8)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 7, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
node _wen_T = or(io.update_mask[0], io.update_mask[1])
node _wen_T_1 = or(_wen_T, io.update_mask[2])
node _wen_T_2 = or(_wen_T_1, io.update_mask[3])
node _wen_T_3 = or(doing_reset, _wen_T_2)
wire wen : UInt<1>
connect wen, _wen_T_3
wire _rdata_WIRE : UInt<8>
invalidate _rdata_WIRE
when io.f1_req_valid :
connect _rdata_WIRE, s1_hashed_idx
read mport rdata = tage_table_16[_rdata_WIRE], clock
reg REG : UInt<1>, clock
connect REG, wen
node _T_3 = and(REG, UInt<1>(0h0))
when _T_3 :
wire _WIRE : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect _WIRE[0].ctr, UInt<3>(0h0)
connect _WIRE[0].tag, UInt<8>(0h0)
connect _WIRE[0].valid, UInt<1>(0h0)
connect _WIRE[1].ctr, UInt<3>(0h0)
connect _WIRE[1].tag, UInt<8>(0h0)
connect _WIRE[1].valid, UInt<1>(0h0)
connect _WIRE[2].ctr, UInt<3>(0h0)
connect _WIRE[2].tag, UInt<8>(0h0)
connect _WIRE[2].valid, UInt<1>(0h0)
connect _WIRE[3].ctr, UInt<3>(0h0)
connect _WIRE[3].tag, UInt<8>(0h0)
connect _WIRE[3].valid, UInt<1>(0h0)
connect s2_req_rtage, _WIRE
else :
wire _WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_2 : UInt<12>
connect _WIRE_2, rdata[0]
node _T_4 = bits(_WIRE_2, 2, 0)
connect _WIRE_1.ctr, _T_4
node _T_5 = bits(_WIRE_2, 10, 3)
connect _WIRE_1.tag, _T_5
node _T_6 = bits(_WIRE_2, 11, 11)
connect _WIRE_1.valid, _T_6
wire _WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_4 : UInt<12>
connect _WIRE_4, rdata[1]
node _T_7 = bits(_WIRE_4, 2, 0)
connect _WIRE_3.ctr, _T_7
node _T_8 = bits(_WIRE_4, 10, 3)
connect _WIRE_3.tag, _T_8
node _T_9 = bits(_WIRE_4, 11, 11)
connect _WIRE_3.valid, _T_9
wire _WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_6 : UInt<12>
connect _WIRE_6, rdata[2]
node _T_10 = bits(_WIRE_6, 2, 0)
connect _WIRE_5.ctr, _T_10
node _T_11 = bits(_WIRE_6, 10, 3)
connect _WIRE_5.tag, _T_11
node _T_12 = bits(_WIRE_6, 11, 11)
connect _WIRE_5.valid, _T_12
wire _WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _WIRE_8 : UInt<12>
connect _WIRE_8, rdata[3]
node _T_13 = bits(_WIRE_8, 2, 0)
connect _WIRE_7.ctr, _T_13
node _T_14 = bits(_WIRE_8, 10, 3)
connect _WIRE_7.tag, _T_14
node _T_15 = bits(_WIRE_8, 11, 11)
connect _WIRE_7.valid, _T_15
wire _WIRE_9 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect _WIRE_9[0].ctr, _WIRE_1.ctr
connect _WIRE_9[0].tag, _WIRE_1.tag
connect _WIRE_9[0].valid, _WIRE_1.valid
connect _WIRE_9[1].ctr, _WIRE_3.ctr
connect _WIRE_9[1].tag, _WIRE_3.tag
connect _WIRE_9[1].valid, _WIRE_3.valid
connect _WIRE_9[2].ctr, _WIRE_5.ctr
connect _WIRE_9[2].tag, _WIRE_5.tag
connect _WIRE_9[2].valid, _WIRE_5.valid
connect _WIRE_9[3].ctr, _WIRE_7.ctr
connect _WIRE_9[3].tag, _WIRE_7.tag
connect _WIRE_9[3].valid, _WIRE_7.valid
connect s2_req_rtage, _WIRE_9
when wen :
node widx = mux(doing_reset, reset_idx, update_idx)
wire _wdata_WIRE : UInt<12>[4]
connect _wdata_WIRE[0], UInt<12>(0h0)
connect _wdata_WIRE[1], UInt<12>(0h0)
connect _wdata_WIRE[2], UInt<12>(0h0)
connect _wdata_WIRE[3], UInt<12>(0h0)
node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _wdata_T = cat(wdata_hi, update_wdata[0].ctr)
node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr)
node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr)
node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr)
wire _wdata_WIRE_1 : UInt<12>[4]
connect _wdata_WIRE_1[0], _wdata_T
connect _wdata_WIRE_1[1], _wdata_T_1
connect _wdata_WIRE_1[2], _wdata_T_2
connect _wdata_WIRE_1[3], _wdata_T_3
node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1)
node _wmask_T = not(UInt<4>(0h0))
node wmask_lo = cat(io.update_mask[1], io.update_mask[0])
node wmask_hi = cat(io.update_mask[3], io.update_mask[2])
node _wmask_T_1 = cat(wmask_hi, wmask_lo)
node wmask = mux(doing_reset, _wmask_T, _wmask_T_1)
node _T_16 = bits(wmask, 0, 0)
node _T_17 = bits(wmask, 1, 1)
node _T_18 = bits(wmask, 2, 2)
node _T_19 = bits(wmask, 3, 3)
write mport MPORT = tage_table_16[widx], clock
when _T_16 :
connect MPORT[0], wdata[0]
when _T_17 :
connect MPORT[1], wdata[1]
when _T_18 :
connect MPORT[2], wdata[2]
when _T_19 :
connect MPORT[3], wdata[3]
wire update_u_mask : UInt<1>[8]
connect update_u_mask[0], io.update_u_mask[0]
connect update_u_mask[1], io.update_u_mask[0]
connect update_u_mask[2], io.update_u_mask[1]
connect update_u_mask[3], io.update_u_mask[1]
connect update_u_mask[4], io.update_u_mask[2]
connect update_u_mask[5], io.update_u_mask[2]
connect update_u_mask[6], io.update_u_mask[3]
connect update_u_mask[7], io.update_u_mask[3]
node _update_u_wen_T = or(doing_reset, doing_clear_u)
node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1])
node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2])
node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3])
node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4])
node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5])
node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6])
node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7])
node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7)
wire update_u_wen : UInt<1>
connect update_u_wen, _update_u_wen_T_8
wire _u_rdata_WIRE : UInt<8>
invalidate _u_rdata_WIRE
when io.f1_req_valid :
connect _u_rdata_WIRE, s1_hashed_idx
read mport u_rdata = tage_u_16[_u_rdata_WIRE], clock
connect s2_req_rus, u_rdata
when update_u_wen :
node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx)
node widx_1 = mux(doing_reset, reset_idx, _widx_T)
node _wdata_T_4 = or(doing_reset, doing_clear_u)
wire _wdata_WIRE_2 : UInt<1>[8]
connect _wdata_WIRE_2[0], UInt<1>(0h0)
connect _wdata_WIRE_2[1], UInt<1>(0h0)
connect _wdata_WIRE_2[2], UInt<1>(0h0)
connect _wdata_WIRE_2[3], UInt<1>(0h0)
connect _wdata_WIRE_2[4], UInt<1>(0h0)
connect _wdata_WIRE_2[5], UInt<1>(0h0)
connect _wdata_WIRE_2[6], UInt<1>(0h0)
connect _wdata_WIRE_2[7], UInt<1>(0h0)
node wdata_lo = cat(io.update_u[1], io.update_u[0])
node wdata_hi_4 = cat(io.update_u[3], io.update_u[2])
node _wdata_T_5 = cat(wdata_hi_4, wdata_lo)
node _wdata_T_6 = bits(_wdata_T_5, 0, 0)
node _wdata_T_7 = bits(_wdata_T_5, 1, 1)
node _wdata_T_8 = bits(_wdata_T_5, 2, 2)
node _wdata_T_9 = bits(_wdata_T_5, 3, 3)
node _wdata_T_10 = bits(_wdata_T_5, 4, 4)
node _wdata_T_11 = bits(_wdata_T_5, 5, 5)
node _wdata_T_12 = bits(_wdata_T_5, 6, 6)
node _wdata_T_13 = bits(_wdata_T_5, 7, 7)
wire _wdata_WIRE_3 : UInt<1>[8]
connect _wdata_WIRE_3[0], _wdata_T_6
connect _wdata_WIRE_3[1], _wdata_T_7
connect _wdata_WIRE_3[2], _wdata_T_8
connect _wdata_WIRE_3[3], _wdata_T_9
connect _wdata_WIRE_3[4], _wdata_T_10
connect _wdata_WIRE_3[5], _wdata_T_11
connect _wdata_WIRE_3[6], _wdata_T_12
connect _wdata_WIRE_3[7], _wdata_T_13
node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3)
node _wmask_T_2 = not(UInt<8>(0h0))
node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0])
node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2])
node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo)
node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4])
node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6])
node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo)
node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1)
node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3)
node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4)
node _T_20 = bits(wmask_1, 0, 0)
node _T_21 = bits(wmask_1, 1, 1)
node _T_22 = bits(wmask_1, 2, 2)
node _T_23 = bits(wmask_1, 3, 3)
node _T_24 = bits(wmask_1, 4, 4)
node _T_25 = bits(wmask_1, 5, 5)
node _T_26 = bits(wmask_1, 6, 6)
node _T_27 = bits(wmask_1, 7, 7)
node _T_28 = bits(widx_1, 7, 0)
write mport MPORT_1 = tage_u_16[_T_28], clock
when _T_20 :
connect MPORT_1[0], wdata_1[0]
when _T_21 :
connect MPORT_1[1], wdata_1[1]
when _T_22 :
connect MPORT_1[2], wdata_1[2]
when _T_23 :
connect MPORT_1[3], wdata_1[3]
when _T_24 :
connect MPORT_1[4], wdata_1[4]
when _T_25 :
connect MPORT_1[5], wdata_1[5]
when _T_26 :
connect MPORT_1[6], wdata_1[6]
when _T_27 :
connect MPORT_1[7], wdata_1[7]
reg wrbypass_tags : UInt<8>[2], clock
reg wrbypass_idxs : UInt<8>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _T_29 = or(io.update_mask[0], io.update_mask[1])
node _T_30 = or(_T_29, io.update_mask[2])
node _T_31 = or(_T_30, io.update_mask[3])
when _T_31 :
node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_32 :
wire _WIRE_10 : UInt<3>[4]
connect _WIRE_10[0], update_wdata[0].ctr
connect _WIRE_10[1], update_wdata[1].ctr
connect _WIRE_10[2], update_wdata[2].ctr
connect _WIRE_10[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_10
else :
wire _WIRE_11 : UInt<3>[4]
connect _WIRE_11[0], update_wdata[0].ctr
connect _WIRE_11[1], update_wdata[1].ctr
connect _WIRE_11[2], update_wdata[2].ctr
connect _WIRE_11[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_11
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_3( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f2_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14]
output io_f2_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14]
output io_f2_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14]
output io_f2_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire [47:0] _tage_table_16_R0_data; // @[tage.scala:90:27]
wire [7:0] _tage_u_16_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26]
wire [11:0] _wdata_WIRE_0 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_1 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_2 = 12'h0; // @[tage.scala:130:41]
wire [11:0] _wdata_WIRE_3 = 12'h0; // @[tage.scala:130:41]
wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34]
wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58]
wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58]
wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34]
wire s2_req_rhits_0; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_1; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_2; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34]
wire s2_req_rhits_3; // @[tage.scala:100:29]
wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26]
wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34]
wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30]
wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f2_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [7:0] reset_idx; // @[tage.scala:73:26]
wire [8:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26]
wire [8:0] _reset_idx_T = _GEN + {8'h0, doing_reset}; // @[tage.scala:72:28, :74:26]
wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26]
wire [7:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:149:35]
wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:149:35]
wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99]
wire [7:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12]
wire [7:0] tag_history = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}]
wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}]
wire wdata_1_0; // @[tage.scala:145:20]
wire wdata_1_1; // @[tage.scala:145:20]
wire wdata_1_2; // @[tage.scala:145:20]
wire wdata_1_3; // @[tage.scala:145:20]
wire wdata_1_4; // @[tage.scala:145:20]
wire wdata_1_5; // @[tage.scala:145:20]
wire wdata_1_6; // @[tage.scala:145:20]
wire wdata_1_7; // @[tage.scala:145:20]
wire s2_req_rus_0 = _tage_u_16_R0_data[0]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_1 = _tage_u_16_R0_data[1]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_2 = _tage_u_16_R0_data[2]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_3 = _tage_u_16_R0_data[3]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_4 = _tage_u_16_R0_data[4]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_5 = _tage_u_16_R0_data[5]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_6 = _tage_u_16_R0_data[6]; // @[tage.scala:89:27, :99:24]
wire s2_req_rus_7 = _tage_u_16_R0_data[7]; // @[tage.scala:89:27, :99:24]
wire [11:0] wdata_0; // @[tage.scala:130:20]
wire [11:0] wdata_1; // @[tage.scala:130:20]
wire [11:0] wdata_2; // @[tage.scala:130:20]
wire [11:0] wdata_3; // @[tage.scala:130:20]
reg [7:0] s2_tag; // @[tage.scala:96:29]
assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26]
assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26]
wire s2_req_rtage_0_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_0_tag; // @[tage.scala:98:26]
wire s2_req_rtage_1_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_1_tag; // @[tage.scala:98:26]
wire s2_req_rtage_2_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_2_tag; // @[tage.scala:98:26]
wire s2_req_rtage_3_valid; // @[tage.scala:98:26]
wire [7:0] s2_req_rtage_3_tag; // @[tage.scala:98:26]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29]
assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29]
assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34]
assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34]
assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34]
reg [19:0] clear_u_ctr; // @[tage.scala:109:28]
wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85]
wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31]
wire _clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:31, :114:31]
wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}]
wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29]
wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}]
wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29]
wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33]
wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109]
wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}]
wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}]
wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109]
wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109]
wire [7:0] idx_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_1 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:149:35]
wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:149:35]
wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] tag_history_1 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}]
wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}]
wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26]
wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60]
wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}]
wire wen = _wen_T_3; // @[tage.scala:121:{21,34}]
reg REG; // @[tage.scala:123:16]
assign s2_req_rtage_0_ctr = _tage_table_16_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_tag = _tage_table_16_R0_data[10:3]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_0_valid = _tage_table_16_R0_data[11]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_ctr = _tage_table_16_R0_data[14:12]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_tag = _tage_table_16_R0_data[22:15]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_1_valid = _tage_table_16_R0_data[23]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_ctr = _tage_table_16_R0_data[26:24]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_tag = _tage_table_16_R0_data[34:27]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_2_valid = _tage_table_16_R0_data[35]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_ctr = _tage_table_16_R0_data[38:36]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_tag = _tage_table_16_R0_data[46:39]; // @[tage.scala:90:27, :98:26, :126:49]
assign s2_req_rtage_3_valid = _tage_table_16_R0_data[47]; // @[tage.scala:90:27, :98:26, :126:49]
wire [7:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19]
wire [8:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}]
wire [8:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114]
wire [11:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}]
assign wdata_0 = doing_reset ? 12'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_1 = doing_reset ? 12'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_2 = doing_reset ? 12'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}]
assign wdata_3 = doing_reset ? 12'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}]
wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70]
wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70]
wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70]
wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}]
wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43]
wire _update_u_wen_T; // @[tage.scala:136:43]
assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43]
wire _wdata_T_4; // @[tage.scala:145:33]
assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33]
wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85]
wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}]
wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}]
wire [8:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47]
wire [8:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}]
wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110]
wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110]
wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110]
wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}]
wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}]
wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}]
wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}]
wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}]
wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}]
wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}]
wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}]
wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}]
assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}]
assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}]
assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}]
assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}]
assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}]
assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}]
assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}]
assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}]
wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106]
wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106]
wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106]
wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106]
wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}]
wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}]
reg [7:0] wrbypass_tags_0; // @[tage.scala:154:29]
reg [7:0] wrbypass_tags_1; // @[tage.scala:154:29]
reg [7:0] wrbypass_idxs_0; // @[tage.scala:155:29]
reg [7:0] wrbypass_idxs_1; // @[tage.scala:155:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:156:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:156:29]
reg wrbypass_enq_idx; // @[tage.scala:157:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}]
wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 8'h0; // @[tage.scala:73:26]
clear_u_ctr <= 20'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39]
end
else // @[tage.scala:157:33, :180:38, :181:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29]
REG <= wen; // @[tage.scala:121:21, :123:16]
if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39]
end
else // @[tage.scala:154:29, :180:38, :181:39, :185:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29]
if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29]
if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39]
end
else // @[tage.scala:155:29, :180:38, :181:39, :186:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29]
if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
end
else begin // @[tage.scala:156:29, :180:38, :181:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29]
end
always @(posedge)
tage_u_16 tage_u_16 ( // @[tage.scala:89:27]
.R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_u_16_R0_data),
.W0_addr (widx_1[7:0]), // @[tage.scala:144:19, :147:13]
.W0_en (update_u_wen), // @[tage.scala:136:30]
.W0_clk (clock),
.W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20]
.W0_mask (wmask_1) // @[tage.scala:146:20]
); // @[tage.scala:89:27]
tage_table_16 tage_table_16 ( // @[tage.scala:90:27]
.R0_addr (_rdata_WIRE), // @[tage.scala:122:99]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_tage_table_16_R0_data),
.W0_addr (widx), // @[tage.scala:129:19]
.W0_en (wen), // @[tage.scala:121:21]
.W0_clk (clock),
.W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20]
.W0_mask (wmask) // @[tage.scala:131:20]
); // @[tage.scala:90:27]
assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLFIFOFixer_3 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_21
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
node _a_notFIFO_T = xor(anonIn.a.bits.address, UInt<1>(0h0))
node _a_notFIFO_T_1 = cvt(_a_notFIFO_T)
node _a_notFIFO_T_2 = and(_a_notFIFO_T_1, asSInt(UInt<1>(0h0)))
node _a_notFIFO_T_3 = asSInt(_a_notFIFO_T_2)
node _a_notFIFO_T_4 = eq(_a_notFIFO_T_3, asSInt(UInt<1>(0h0)))
node _a_id_T = xor(anonIn.a.bits.address, UInt<1>(0h0))
node _a_id_T_1 = cvt(_a_id_T)
node _a_id_T_2 = and(_a_id_T_1, asSInt(UInt<33>(0h9a113000)))
node _a_id_T_3 = asSInt(_a_id_T_2)
node _a_id_T_4 = eq(_a_id_T_3, asSInt(UInt<1>(0h0)))
node _a_id_T_5 = xor(anonIn.a.bits.address, UInt<13>(0h1000))
node _a_id_T_6 = cvt(_a_id_T_5)
node _a_id_T_7 = and(_a_id_T_6, asSInt(UInt<33>(0h9a113000)))
node _a_id_T_8 = asSInt(_a_id_T_7)
node _a_id_T_9 = eq(_a_id_T_8, asSInt(UInt<1>(0h0)))
node _a_id_T_10 = xor(anonIn.a.bits.address, UInt<29>(0h10000000))
node _a_id_T_11 = cvt(_a_id_T_10)
node _a_id_T_12 = and(_a_id_T_11, asSInt(UInt<33>(0h9a113000)))
node _a_id_T_13 = asSInt(_a_id_T_12)
node _a_id_T_14 = eq(_a_id_T_13, asSInt(UInt<1>(0h0)))
node _a_id_T_15 = or(_a_id_T_9, _a_id_T_14)
node _a_id_T_16 = xor(anonIn.a.bits.address, UInt<14>(0h3000))
node _a_id_T_17 = cvt(_a_id_T_16)
node _a_id_T_18 = and(_a_id_T_17, asSInt(UInt<33>(0h9a113000)))
node _a_id_T_19 = asSInt(_a_id_T_18)
node _a_id_T_20 = eq(_a_id_T_19, asSInt(UInt<1>(0h0)))
node _a_id_T_21 = xor(anonIn.a.bits.address, UInt<17>(0h10000))
node _a_id_T_22 = cvt(_a_id_T_21)
node _a_id_T_23 = and(_a_id_T_22, asSInt(UInt<33>(0h9a110000)))
node _a_id_T_24 = asSInt(_a_id_T_23)
node _a_id_T_25 = eq(_a_id_T_24, asSInt(UInt<1>(0h0)))
node _a_id_T_26 = xor(anonIn.a.bits.address, UInt<21>(0h100000))
node _a_id_T_27 = cvt(_a_id_T_26)
node _a_id_T_28 = and(_a_id_T_27, asSInt(UInt<33>(0h9a103000)))
node _a_id_T_29 = asSInt(_a_id_T_28)
node _a_id_T_30 = eq(_a_id_T_29, asSInt(UInt<1>(0h0)))
node _a_id_T_31 = xor(anonIn.a.bits.address, UInt<26>(0h2000000))
node _a_id_T_32 = cvt(_a_id_T_31)
node _a_id_T_33 = and(_a_id_T_32, asSInt(UInt<33>(0h9a110000)))
node _a_id_T_34 = asSInt(_a_id_T_33)
node _a_id_T_35 = eq(_a_id_T_34, asSInt(UInt<1>(0h0)))
node _a_id_T_36 = xor(anonIn.a.bits.address, UInt<28>(0h8000000))
node _a_id_T_37 = cvt(_a_id_T_36)
node _a_id_T_38 = and(_a_id_T_37, asSInt(UInt<33>(0h98000000)))
node _a_id_T_39 = asSInt(_a_id_T_38)
node _a_id_T_40 = eq(_a_id_T_39, asSInt(UInt<1>(0h0)))
node _a_id_T_41 = xor(anonIn.a.bits.address, UInt<32>(0h80000000))
node _a_id_T_42 = cvt(_a_id_T_41)
node _a_id_T_43 = and(_a_id_T_42, asSInt(UInt<33>(0h9a110000)))
node _a_id_T_44 = asSInt(_a_id_T_43)
node _a_id_T_45 = eq(_a_id_T_44, asSInt(UInt<1>(0h0)))
node _a_id_T_46 = mux(_a_id_T_4, UInt<4>(0h8), UInt<1>(0h0))
node _a_id_T_47 = mux(_a_id_T_15, UInt<2>(0h3), UInt<1>(0h0))
node _a_id_T_48 = mux(_a_id_T_20, UInt<1>(0h1), UInt<1>(0h0))
node _a_id_T_49 = mux(_a_id_T_25, UInt<3>(0h4), UInt<1>(0h0))
node _a_id_T_50 = mux(_a_id_T_30, UInt<3>(0h6), UInt<1>(0h0))
node _a_id_T_51 = mux(_a_id_T_35, UInt<3>(0h5), UInt<1>(0h0))
node _a_id_T_52 = mux(_a_id_T_40, UInt<3>(0h7), UInt<1>(0h0))
node _a_id_T_53 = mux(_a_id_T_45, UInt<2>(0h2), UInt<1>(0h0))
node _a_id_T_54 = or(_a_id_T_46, _a_id_T_47)
node _a_id_T_55 = or(_a_id_T_54, _a_id_T_48)
node _a_id_T_56 = or(_a_id_T_55, _a_id_T_49)
node _a_id_T_57 = or(_a_id_T_56, _a_id_T_50)
node _a_id_T_58 = or(_a_id_T_57, _a_id_T_51)
node _a_id_T_59 = or(_a_id_T_58, _a_id_T_52)
node _a_id_T_60 = or(_a_id_T_59, _a_id_T_53)
wire a_id : UInt<4>
connect a_id, _a_id_T_60
node a_noDomain = eq(a_id, UInt<1>(0h0))
node _a_first_T = and(anonIn.a.ready, anonIn.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonIn.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(anonIn.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
node _d_first_T = and(anonOut.d.ready, anonOut.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), anonOut.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(anonOut.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node _d_first_T_1 = neq(anonOut.d.bits.opcode, UInt<3>(0h6))
node d_first = and(d_first_first, _d_first_T_1)
wire _flight_WIRE : UInt<1>[129]
connect _flight_WIRE[0], UInt<1>(0h0)
connect _flight_WIRE[1], UInt<1>(0h0)
connect _flight_WIRE[2], UInt<1>(0h0)
connect _flight_WIRE[3], UInt<1>(0h0)
connect _flight_WIRE[4], UInt<1>(0h0)
connect _flight_WIRE[5], UInt<1>(0h0)
connect _flight_WIRE[6], UInt<1>(0h0)
connect _flight_WIRE[7], UInt<1>(0h0)
connect _flight_WIRE[8], UInt<1>(0h0)
connect _flight_WIRE[9], UInt<1>(0h0)
connect _flight_WIRE[10], UInt<1>(0h0)
connect _flight_WIRE[11], UInt<1>(0h0)
connect _flight_WIRE[12], UInt<1>(0h0)
connect _flight_WIRE[13], UInt<1>(0h0)
connect _flight_WIRE[14], UInt<1>(0h0)
connect _flight_WIRE[15], UInt<1>(0h0)
connect _flight_WIRE[16], UInt<1>(0h0)
connect _flight_WIRE[17], UInt<1>(0h0)
connect _flight_WIRE[18], UInt<1>(0h0)
connect _flight_WIRE[19], UInt<1>(0h0)
connect _flight_WIRE[20], UInt<1>(0h0)
connect _flight_WIRE[21], UInt<1>(0h0)
connect _flight_WIRE[22], UInt<1>(0h0)
connect _flight_WIRE[23], UInt<1>(0h0)
connect _flight_WIRE[24], UInt<1>(0h0)
connect _flight_WIRE[25], UInt<1>(0h0)
connect _flight_WIRE[26], UInt<1>(0h0)
connect _flight_WIRE[27], UInt<1>(0h0)
connect _flight_WIRE[28], UInt<1>(0h0)
connect _flight_WIRE[29], UInt<1>(0h0)
connect _flight_WIRE[30], UInt<1>(0h0)
connect _flight_WIRE[31], UInt<1>(0h0)
connect _flight_WIRE[32], UInt<1>(0h0)
connect _flight_WIRE[33], UInt<1>(0h0)
connect _flight_WIRE[34], UInt<1>(0h0)
connect _flight_WIRE[35], UInt<1>(0h0)
connect _flight_WIRE[36], UInt<1>(0h0)
connect _flight_WIRE[37], UInt<1>(0h0)
connect _flight_WIRE[38], UInt<1>(0h0)
connect _flight_WIRE[39], UInt<1>(0h0)
connect _flight_WIRE[40], UInt<1>(0h0)
connect _flight_WIRE[41], UInt<1>(0h0)
connect _flight_WIRE[42], UInt<1>(0h0)
connect _flight_WIRE[43], UInt<1>(0h0)
connect _flight_WIRE[44], UInt<1>(0h0)
connect _flight_WIRE[45], UInt<1>(0h0)
connect _flight_WIRE[46], UInt<1>(0h0)
connect _flight_WIRE[47], UInt<1>(0h0)
connect _flight_WIRE[48], UInt<1>(0h0)
connect _flight_WIRE[49], UInt<1>(0h0)
connect _flight_WIRE[50], UInt<1>(0h0)
connect _flight_WIRE[51], UInt<1>(0h0)
connect _flight_WIRE[52], UInt<1>(0h0)
connect _flight_WIRE[53], UInt<1>(0h0)
connect _flight_WIRE[54], UInt<1>(0h0)
connect _flight_WIRE[55], UInt<1>(0h0)
connect _flight_WIRE[56], UInt<1>(0h0)
connect _flight_WIRE[57], UInt<1>(0h0)
connect _flight_WIRE[58], UInt<1>(0h0)
connect _flight_WIRE[59], UInt<1>(0h0)
connect _flight_WIRE[60], UInt<1>(0h0)
connect _flight_WIRE[61], UInt<1>(0h0)
connect _flight_WIRE[62], UInt<1>(0h0)
connect _flight_WIRE[63], UInt<1>(0h0)
connect _flight_WIRE[64], UInt<1>(0h0)
connect _flight_WIRE[65], UInt<1>(0h0)
connect _flight_WIRE[66], UInt<1>(0h0)
connect _flight_WIRE[67], UInt<1>(0h0)
connect _flight_WIRE[68], UInt<1>(0h0)
connect _flight_WIRE[69], UInt<1>(0h0)
connect _flight_WIRE[70], UInt<1>(0h0)
connect _flight_WIRE[71], UInt<1>(0h0)
connect _flight_WIRE[72], UInt<1>(0h0)
connect _flight_WIRE[73], UInt<1>(0h0)
connect _flight_WIRE[74], UInt<1>(0h0)
connect _flight_WIRE[75], UInt<1>(0h0)
connect _flight_WIRE[76], UInt<1>(0h0)
connect _flight_WIRE[77], UInt<1>(0h0)
connect _flight_WIRE[78], UInt<1>(0h0)
connect _flight_WIRE[79], UInt<1>(0h0)
connect _flight_WIRE[80], UInt<1>(0h0)
connect _flight_WIRE[81], UInt<1>(0h0)
connect _flight_WIRE[82], UInt<1>(0h0)
connect _flight_WIRE[83], UInt<1>(0h0)
connect _flight_WIRE[84], UInt<1>(0h0)
connect _flight_WIRE[85], UInt<1>(0h0)
connect _flight_WIRE[86], UInt<1>(0h0)
connect _flight_WIRE[87], UInt<1>(0h0)
connect _flight_WIRE[88], UInt<1>(0h0)
connect _flight_WIRE[89], UInt<1>(0h0)
connect _flight_WIRE[90], UInt<1>(0h0)
connect _flight_WIRE[91], UInt<1>(0h0)
connect _flight_WIRE[92], UInt<1>(0h0)
connect _flight_WIRE[93], UInt<1>(0h0)
connect _flight_WIRE[94], UInt<1>(0h0)
connect _flight_WIRE[95], UInt<1>(0h0)
connect _flight_WIRE[96], UInt<1>(0h0)
connect _flight_WIRE[97], UInt<1>(0h0)
connect _flight_WIRE[98], UInt<1>(0h0)
connect _flight_WIRE[99], UInt<1>(0h0)
connect _flight_WIRE[100], UInt<1>(0h0)
connect _flight_WIRE[101], UInt<1>(0h0)
connect _flight_WIRE[102], UInt<1>(0h0)
connect _flight_WIRE[103], UInt<1>(0h0)
connect _flight_WIRE[104], UInt<1>(0h0)
connect _flight_WIRE[105], UInt<1>(0h0)
connect _flight_WIRE[106], UInt<1>(0h0)
connect _flight_WIRE[107], UInt<1>(0h0)
connect _flight_WIRE[108], UInt<1>(0h0)
connect _flight_WIRE[109], UInt<1>(0h0)
connect _flight_WIRE[110], UInt<1>(0h0)
connect _flight_WIRE[111], UInt<1>(0h0)
connect _flight_WIRE[112], UInt<1>(0h0)
connect _flight_WIRE[113], UInt<1>(0h0)
connect _flight_WIRE[114], UInt<1>(0h0)
connect _flight_WIRE[115], UInt<1>(0h0)
connect _flight_WIRE[116], UInt<1>(0h0)
connect _flight_WIRE[117], UInt<1>(0h0)
connect _flight_WIRE[118], UInt<1>(0h0)
connect _flight_WIRE[119], UInt<1>(0h0)
connect _flight_WIRE[120], UInt<1>(0h0)
connect _flight_WIRE[121], UInt<1>(0h0)
connect _flight_WIRE[122], UInt<1>(0h0)
connect _flight_WIRE[123], UInt<1>(0h0)
connect _flight_WIRE[124], UInt<1>(0h0)
connect _flight_WIRE[125], UInt<1>(0h0)
connect _flight_WIRE[126], UInt<1>(0h0)
connect _flight_WIRE[127], UInt<1>(0h0)
connect _flight_WIRE[128], UInt<1>(0h0)
regreset flight : UInt<1>[129], clock, reset, _flight_WIRE
node _T = and(anonIn.a.ready, anonIn.a.valid)
node _T_1 = and(a_first, _T)
when _T_1 :
node _flight_T = eq(UInt<1>(0h0), UInt<1>(0h0))
connect flight[anonIn.a.bits.source], _flight_T
node _T_2 = and(anonIn.d.ready, anonIn.d.valid)
node _T_3 = and(d_first, _T_2)
when _T_3 :
connect flight[anonIn.d.bits.source], UInt<1>(0h0)
node _stalls_a_sel_uncommonBits_T = or(anonIn.a.bits.source, UInt<3>(0h0))
node stalls_a_sel_uncommonBits = bits(_stalls_a_sel_uncommonBits_T, 2, 0)
node _stalls_a_sel_T = shr(anonIn.a.bits.source, 3)
node _stalls_a_sel_T_1 = eq(_stalls_a_sel_T, UInt<2>(0h2))
node _stalls_a_sel_T_2 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits)
node _stalls_a_sel_T_3 = and(_stalls_a_sel_T_1, _stalls_a_sel_T_2)
node _stalls_a_sel_T_4 = leq(stalls_a_sel_uncommonBits, UInt<3>(0h7))
node stalls_a_sel = and(_stalls_a_sel_T_3, _stalls_a_sel_T_4)
node _stalls_id_T = and(anonIn.a.ready, anonIn.a.valid)
node _stalls_id_T_1 = and(_stalls_id_T, stalls_a_sel)
node _stalls_id_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _stalls_id_T_3 = and(_stalls_id_T_1, _stalls_id_T_2)
reg stalls_id : UInt<4>, clock
when _stalls_id_T_3 :
connect stalls_id, a_id
node _stalls_T = and(stalls_a_sel, a_first)
node _stalls_T_1 = or(flight[16], flight[17])
node _stalls_T_2 = or(_stalls_T_1, flight[18])
node _stalls_T_3 = or(_stalls_T_2, flight[19])
node _stalls_T_4 = or(_stalls_T_3, flight[20])
node _stalls_T_5 = or(_stalls_T_4, flight[21])
node _stalls_T_6 = or(_stalls_T_5, flight[22])
node _stalls_T_7 = or(_stalls_T_6, flight[23])
node _stalls_T_8 = and(_stalls_T, _stalls_T_7)
node _stalls_T_9 = neq(stalls_id, a_id)
node _stalls_T_10 = or(a_noDomain, _stalls_T_9)
node stalls_0 = and(_stalls_T_8, _stalls_T_10)
node _stalls_a_sel_uncommonBits_T_1 = or(anonIn.a.bits.source, UInt<3>(0h0))
node stalls_a_sel_uncommonBits_1 = bits(_stalls_a_sel_uncommonBits_T_1, 2, 0)
node _stalls_a_sel_T_5 = shr(anonIn.a.bits.source, 3)
node _stalls_a_sel_T_6 = eq(_stalls_a_sel_T_5, UInt<2>(0h3))
node _stalls_a_sel_T_7 = leq(UInt<1>(0h0), stalls_a_sel_uncommonBits_1)
node _stalls_a_sel_T_8 = and(_stalls_a_sel_T_6, _stalls_a_sel_T_7)
node _stalls_a_sel_T_9 = leq(stalls_a_sel_uncommonBits_1, UInt<3>(0h7))
node stalls_a_sel_1 = and(_stalls_a_sel_T_8, _stalls_a_sel_T_9)
node _stalls_id_T_4 = and(anonIn.a.ready, anonIn.a.valid)
node _stalls_id_T_5 = and(_stalls_id_T_4, stalls_a_sel_1)
node _stalls_id_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _stalls_id_T_7 = and(_stalls_id_T_5, _stalls_id_T_6)
reg stalls_id_1 : UInt<4>, clock
when _stalls_id_T_7 :
connect stalls_id_1, a_id
node _stalls_T_11 = and(stalls_a_sel_1, a_first)
node _stalls_T_12 = or(flight[24], flight[25])
node _stalls_T_13 = or(_stalls_T_12, flight[26])
node _stalls_T_14 = or(_stalls_T_13, flight[27])
node _stalls_T_15 = or(_stalls_T_14, flight[28])
node _stalls_T_16 = or(_stalls_T_15, flight[29])
node _stalls_T_17 = or(_stalls_T_16, flight[30])
node _stalls_T_18 = or(_stalls_T_17, flight[31])
node _stalls_T_19 = and(_stalls_T_11, _stalls_T_18)
node _stalls_T_20 = neq(stalls_id_1, a_id)
node _stalls_T_21 = or(a_noDomain, _stalls_T_20)
node stalls_1 = and(_stalls_T_19, _stalls_T_21)
node _stall_T = or(UInt<1>(0h0), stalls_0)
node stall = or(_stall_T, stalls_1)
connect anonOut.a, anonIn.a
connect anonIn.d, anonOut.d
node _anonOut_a_valid_T = eq(stall, UInt<1>(0h0))
node _anonOut_a_valid_T_1 = or(UInt<1>(0h0), _anonOut_a_valid_T)
node _anonOut_a_valid_T_2 = and(anonIn.a.valid, _anonOut_a_valid_T_1)
connect anonOut.a.valid, _anonOut_a_valid_T_2
node _anonIn_a_ready_T = eq(stall, UInt<1>(0h0))
node _anonIn_a_ready_T_1 = or(UInt<1>(0h0), _anonIn_a_ready_T)
node _anonIn_a_ready_T_2 = and(anonOut.a.ready, _anonIn_a_ready_T_1)
connect anonIn.a.ready, _anonIn_a_ready_T_2
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
node _T_4 = and(anonIn.a.valid, stall)
regreset SourceIdFIFOed : UInt<129>, clock, reset, UInt<129>(0h0)
wire SourceIdSet : UInt<129>
connect SourceIdSet, UInt<129>(0h0)
wire SourceIdClear : UInt<129>
connect SourceIdClear, UInt<129>(0h0)
node _T_5 = and(anonIn.a.ready, anonIn.a.valid)
node _T_6 = and(a_first, _T_5)
node _T_7 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _SourceIdSet_T = dshl(UInt<1>(0h1), anonIn.a.bits.source)
connect SourceIdSet, _SourceIdSet_T
node _T_9 = and(anonIn.d.ready, anonIn.d.valid)
node _T_10 = and(d_first, _T_9)
when _T_10 :
node _SourceIdClear_T = dshl(UInt<1>(0h1), anonIn.d.bits.source)
connect SourceIdClear, _SourceIdClear_T
node _SourceIdFIFOed_T = or(SourceIdFIFOed, SourceIdSet)
connect SourceIdFIFOed, _SourceIdFIFOed_T
node _allIDs_FIFOed_T = mux(UInt<1>(0h1), UInt<129>(0h1ffffffffffffffffffffffffffffffff), UInt<129>(0h0))
node allIDs_FIFOed = eq(SourceIdFIFOed, _allIDs_FIFOed_T)
node _T_11 = or(flight[0], flight[1])
node _T_12 = or(_T_11, flight[2])
node _T_13 = or(_T_12, flight[3])
node _T_14 = or(_T_13, flight[4])
node _T_15 = or(_T_14, flight[5])
node _T_16 = or(_T_15, flight[6])
node _T_17 = or(_T_16, flight[7])
node _T_18 = or(_T_17, flight[8])
node _T_19 = or(_T_18, flight[9])
node _T_20 = or(_T_19, flight[10])
node _T_21 = or(_T_20, flight[11])
node _T_22 = or(_T_21, flight[12])
node _T_23 = or(_T_22, flight[13])
node _T_24 = or(_T_23, flight[14])
node _T_25 = or(_T_24, flight[15])
node _T_26 = or(_T_25, flight[16])
node _T_27 = or(_T_26, flight[17])
node _T_28 = or(_T_27, flight[18])
node _T_29 = or(_T_28, flight[19])
node _T_30 = or(_T_29, flight[20])
node _T_31 = or(_T_30, flight[21])
node _T_32 = or(_T_31, flight[22])
node _T_33 = or(_T_32, flight[23])
node _T_34 = or(_T_33, flight[24])
node _T_35 = or(_T_34, flight[25])
node _T_36 = or(_T_35, flight[26])
node _T_37 = or(_T_36, flight[27])
node _T_38 = or(_T_37, flight[28])
node _T_39 = or(_T_38, flight[29])
node _T_40 = or(_T_39, flight[30])
node _T_41 = or(_T_40, flight[31])
node _T_42 = or(_T_41, flight[32])
node _T_43 = or(_T_42, flight[33])
node _T_44 = or(_T_43, flight[34])
node _T_45 = or(_T_44, flight[35])
node _T_46 = or(_T_45, flight[36])
node _T_47 = or(_T_46, flight[37])
node _T_48 = or(_T_47, flight[38])
node _T_49 = or(_T_48, flight[39])
node _T_50 = or(_T_49, flight[40])
node _T_51 = or(_T_50, flight[41])
node _T_52 = or(_T_51, flight[42])
node _T_53 = or(_T_52, flight[43])
node _T_54 = or(_T_53, flight[44])
node _T_55 = or(_T_54, flight[45])
node _T_56 = or(_T_55, flight[46])
node _T_57 = or(_T_56, flight[47])
node _T_58 = or(_T_57, flight[48])
node _T_59 = or(_T_58, flight[49])
node _T_60 = or(_T_59, flight[50])
node _T_61 = or(_T_60, flight[51])
node _T_62 = or(_T_61, flight[52])
node _T_63 = or(_T_62, flight[53])
node _T_64 = or(_T_63, flight[54])
node _T_65 = or(_T_64, flight[55])
node _T_66 = or(_T_65, flight[56])
node _T_67 = or(_T_66, flight[57])
node _T_68 = or(_T_67, flight[58])
node _T_69 = or(_T_68, flight[59])
node _T_70 = or(_T_69, flight[60])
node _T_71 = or(_T_70, flight[61])
node _T_72 = or(_T_71, flight[62])
node _T_73 = or(_T_72, flight[63])
node _T_74 = or(_T_73, flight[64])
node _T_75 = or(_T_74, flight[65])
node _T_76 = or(_T_75, flight[66])
node _T_77 = or(_T_76, flight[67])
node _T_78 = or(_T_77, flight[68])
node _T_79 = or(_T_78, flight[69])
node _T_80 = or(_T_79, flight[70])
node _T_81 = or(_T_80, flight[71])
node _T_82 = or(_T_81, flight[72])
node _T_83 = or(_T_82, flight[73])
node _T_84 = or(_T_83, flight[74])
node _T_85 = or(_T_84, flight[75])
node _T_86 = or(_T_85, flight[76])
node _T_87 = or(_T_86, flight[77])
node _T_88 = or(_T_87, flight[78])
node _T_89 = or(_T_88, flight[79])
node _T_90 = or(_T_89, flight[80])
node _T_91 = or(_T_90, flight[81])
node _T_92 = or(_T_91, flight[82])
node _T_93 = or(_T_92, flight[83])
node _T_94 = or(_T_93, flight[84])
node _T_95 = or(_T_94, flight[85])
node _T_96 = or(_T_95, flight[86])
node _T_97 = or(_T_96, flight[87])
node _T_98 = or(_T_97, flight[88])
node _T_99 = or(_T_98, flight[89])
node _T_100 = or(_T_99, flight[90])
node _T_101 = or(_T_100, flight[91])
node _T_102 = or(_T_101, flight[92])
node _T_103 = or(_T_102, flight[93])
node _T_104 = or(_T_103, flight[94])
node _T_105 = or(_T_104, flight[95])
node _T_106 = or(_T_105, flight[96])
node _T_107 = or(_T_106, flight[97])
node _T_108 = or(_T_107, flight[98])
node _T_109 = or(_T_108, flight[99])
node _T_110 = or(_T_109, flight[100])
node _T_111 = or(_T_110, flight[101])
node _T_112 = or(_T_111, flight[102])
node _T_113 = or(_T_112, flight[103])
node _T_114 = or(_T_113, flight[104])
node _T_115 = or(_T_114, flight[105])
node _T_116 = or(_T_115, flight[106])
node _T_117 = or(_T_116, flight[107])
node _T_118 = or(_T_117, flight[108])
node _T_119 = or(_T_118, flight[109])
node _T_120 = or(_T_119, flight[110])
node _T_121 = or(_T_120, flight[111])
node _T_122 = or(_T_121, flight[112])
node _T_123 = or(_T_122, flight[113])
node _T_124 = or(_T_123, flight[114])
node _T_125 = or(_T_124, flight[115])
node _T_126 = or(_T_125, flight[116])
node _T_127 = or(_T_126, flight[117])
node _T_128 = or(_T_127, flight[118])
node _T_129 = or(_T_128, flight[119])
node _T_130 = or(_T_129, flight[120])
node _T_131 = or(_T_130, flight[121])
node _T_132 = or(_T_131, flight[122])
node _T_133 = or(_T_132, flight[123])
node _T_134 = or(_T_133, flight[124])
node _T_135 = or(_T_134, flight[125])
node _T_136 = or(_T_135, flight[126])
node _T_137 = or(_T_136, flight[127])
node _T_138 = or(_T_137, flight[128])
node _T_139 = eq(_T_138, UInt<1>(0h0))
node _T_140 = gt(SourceIdSet, UInt<1>(0h0))
node _T_141 = gt(SourceIdClear, UInt<1>(0h0))
extmodule plusarg_reader_44 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_45 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLFIFOFixer_3( // @[FIFOFixer.scala:50:9]
input clock, // @[FIFOFixer.scala:50:9]
input reset, // @[FIFOFixer.scala:50:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [32:0] _a_notFIFO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _a_notFIFO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire _flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35]
wire _a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire _stalls_a_sel_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_2 = 1'h1; // @[FIFOFixer.scala:85:59]
wire _stalls_a_sel_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _stalls_a_sel_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _stalls_id_T_6 = 1'h1; // @[FIFOFixer.scala:85:59]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [128:0] _allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[FIFOFixer.scala:50:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[FIFOFixer.scala:50:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
wire auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
wire _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] _stalls_a_sel_uncommonBits_T = anonIn_a_bits_source; // @[Parameters.scala:52:29]
wire [7:0] _stalls_a_sel_uncommonBits_T_1 = anonIn_a_bits_source; // @[Parameters.scala:52:29]
assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] _a_notFIFO_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] _a_id_T = anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign anonOut_a_bits_mask = anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_data = anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_a_bits_corrupt = anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign anonOut_d_ready = anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign anonIn_d_valid = anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_data = anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_corrupt = anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire [32:0] _a_notFIFO_T_1 = {1'h0, _a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_1 = {1'h0, _a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_2 = _a_id_T_1 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_3 = _a_id_T_2; // @[Parameters.scala:137:46]
wire _a_id_T_4 = _a_id_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_5 = {anonIn_a_bits_address[31:13], anonIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_6 = {1'h0, _a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_7 = _a_id_T_6 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_8 = _a_id_T_7; // @[Parameters.scala:137:46]
wire _a_id_T_9 = _a_id_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_10 = {anonIn_a_bits_address[31:29], anonIn_a_bits_address[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_11 = {1'h0, _a_id_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_12 = _a_id_T_11 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_13 = _a_id_T_12; // @[Parameters.scala:137:46]
wire _a_id_T_14 = _a_id_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_id_T_15 = _a_id_T_9 | _a_id_T_14; // @[Parameters.scala:629:89]
wire [31:0] _a_id_T_16 = {anonIn_a_bits_address[31:14], anonIn_a_bits_address[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_17 = {1'h0, _a_id_T_16}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_18 = _a_id_T_17 & 33'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_19 = _a_id_T_18; // @[Parameters.scala:137:46]
wire _a_id_T_20 = _a_id_T_19 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _a_id_T_48 = _a_id_T_20; // @[Mux.scala:30:73]
wire [31:0] _a_id_T_21 = {anonIn_a_bits_address[31:17], anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_22 = {1'h0, _a_id_T_21}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_23 = _a_id_T_22 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_24 = _a_id_T_23; // @[Parameters.scala:137:46]
wire _a_id_T_25 = _a_id_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_26 = {anonIn_a_bits_address[31:21], anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_27 = {1'h0, _a_id_T_26}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_28 = _a_id_T_27 & 33'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_29 = _a_id_T_28; // @[Parameters.scala:137:46]
wire _a_id_T_30 = _a_id_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_31 = {anonIn_a_bits_address[31:26], anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_32 = {1'h0, _a_id_T_31}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_33 = _a_id_T_32 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_34 = _a_id_T_33; // @[Parameters.scala:137:46]
wire _a_id_T_35 = _a_id_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_36 = {anonIn_a_bits_address[31:28], anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_37 = {1'h0, _a_id_T_36}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_38 = _a_id_T_37 & 33'h98000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_39 = _a_id_T_38; // @[Parameters.scala:137:46]
wire _a_id_T_40 = _a_id_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _a_id_T_41 = anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] _a_id_T_42 = {1'h0, _a_id_T_41}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _a_id_T_43 = _a_id_T_42 & 33'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _a_id_T_44 = _a_id_T_43; // @[Parameters.scala:137:46]
wire _a_id_T_45 = _a_id_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [3:0] _a_id_T_46 = {_a_id_T_4, 3'h0}; // @[Mux.scala:30:73]
wire [1:0] _a_id_T_47 = {2{_a_id_T_15}}; // @[Mux.scala:30:73]
wire [2:0] _a_id_T_49 = {_a_id_T_25, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] _a_id_T_50 = _a_id_T_30 ? 3'h6 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _a_id_T_51 = _a_id_T_35 ? 3'h5 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _a_id_T_52 = {3{_a_id_T_40}}; // @[Mux.scala:30:73]
wire [1:0] _a_id_T_53 = {_a_id_T_45, 1'h0}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_54 = {_a_id_T_46[3:2], _a_id_T_46[1:0] | _a_id_T_47}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_55 = {_a_id_T_54[3:1], _a_id_T_54[0] | _a_id_T_48}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_56 = {_a_id_T_55[3], _a_id_T_55[2:0] | _a_id_T_49}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_57 = {_a_id_T_56[3], _a_id_T_56[2:0] | _a_id_T_50}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_58 = {_a_id_T_57[3], _a_id_T_57[2:0] | _a_id_T_51}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_59 = {_a_id_T_58[3], _a_id_T_58[2:0] | _a_id_T_52}; // @[Mux.scala:30:73]
wire [3:0] _a_id_T_60 = {_a_id_T_59[3:2], _a_id_T_59[1:0] | _a_id_T_53}; // @[Mux.scala:30:73]
wire [3:0] a_id = _a_id_T_60; // @[Mux.scala:30:73]
wire a_noDomain = a_id == 4'h0; // @[Mux.scala:30:73]
wire _T_5 = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T; // @[Decoupled.scala:51:35]
assign _stalls_id_T = _T_5; // @[Decoupled.scala:51:35]
wire _stalls_id_T_4; // @[Decoupled.scala:51:35]
assign _stalls_id_T_4 = _T_5; // @[Decoupled.scala:51:35]
wire [26:0] _a_first_beats1_decode_T = 27'hFFF << anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] _d_first_beats1_decode_T = 27'hFFF << anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _d_first_T_1 = anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire d_first = d_first_first & _d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg flight_0; // @[FIFOFixer.scala:79:27]
reg flight_1; // @[FIFOFixer.scala:79:27]
reg flight_2; // @[FIFOFixer.scala:79:27]
reg flight_3; // @[FIFOFixer.scala:79:27]
reg flight_4; // @[FIFOFixer.scala:79:27]
reg flight_5; // @[FIFOFixer.scala:79:27]
reg flight_6; // @[FIFOFixer.scala:79:27]
reg flight_7; // @[FIFOFixer.scala:79:27]
reg flight_8; // @[FIFOFixer.scala:79:27]
reg flight_9; // @[FIFOFixer.scala:79:27]
reg flight_10; // @[FIFOFixer.scala:79:27]
reg flight_11; // @[FIFOFixer.scala:79:27]
reg flight_12; // @[FIFOFixer.scala:79:27]
reg flight_13; // @[FIFOFixer.scala:79:27]
reg flight_14; // @[FIFOFixer.scala:79:27]
reg flight_15; // @[FIFOFixer.scala:79:27]
reg flight_16; // @[FIFOFixer.scala:79:27]
reg flight_17; // @[FIFOFixer.scala:79:27]
reg flight_18; // @[FIFOFixer.scala:79:27]
reg flight_19; // @[FIFOFixer.scala:79:27]
reg flight_20; // @[FIFOFixer.scala:79:27]
reg flight_21; // @[FIFOFixer.scala:79:27]
reg flight_22; // @[FIFOFixer.scala:79:27]
reg flight_23; // @[FIFOFixer.scala:79:27]
reg flight_24; // @[FIFOFixer.scala:79:27]
reg flight_25; // @[FIFOFixer.scala:79:27]
reg flight_26; // @[FIFOFixer.scala:79:27]
reg flight_27; // @[FIFOFixer.scala:79:27]
reg flight_28; // @[FIFOFixer.scala:79:27]
reg flight_29; // @[FIFOFixer.scala:79:27]
reg flight_30; // @[FIFOFixer.scala:79:27]
reg flight_31; // @[FIFOFixer.scala:79:27]
reg flight_32; // @[FIFOFixer.scala:79:27]
reg flight_33; // @[FIFOFixer.scala:79:27]
reg flight_34; // @[FIFOFixer.scala:79:27]
reg flight_35; // @[FIFOFixer.scala:79:27]
reg flight_36; // @[FIFOFixer.scala:79:27]
reg flight_37; // @[FIFOFixer.scala:79:27]
reg flight_38; // @[FIFOFixer.scala:79:27]
reg flight_39; // @[FIFOFixer.scala:79:27]
reg flight_40; // @[FIFOFixer.scala:79:27]
reg flight_41; // @[FIFOFixer.scala:79:27]
reg flight_42; // @[FIFOFixer.scala:79:27]
reg flight_43; // @[FIFOFixer.scala:79:27]
reg flight_44; // @[FIFOFixer.scala:79:27]
reg flight_45; // @[FIFOFixer.scala:79:27]
reg flight_46; // @[FIFOFixer.scala:79:27]
reg flight_47; // @[FIFOFixer.scala:79:27]
reg flight_48; // @[FIFOFixer.scala:79:27]
reg flight_49; // @[FIFOFixer.scala:79:27]
reg flight_50; // @[FIFOFixer.scala:79:27]
reg flight_51; // @[FIFOFixer.scala:79:27]
reg flight_52; // @[FIFOFixer.scala:79:27]
reg flight_53; // @[FIFOFixer.scala:79:27]
reg flight_54; // @[FIFOFixer.scala:79:27]
reg flight_55; // @[FIFOFixer.scala:79:27]
reg flight_56; // @[FIFOFixer.scala:79:27]
reg flight_57; // @[FIFOFixer.scala:79:27]
reg flight_58; // @[FIFOFixer.scala:79:27]
reg flight_59; // @[FIFOFixer.scala:79:27]
reg flight_60; // @[FIFOFixer.scala:79:27]
reg flight_61; // @[FIFOFixer.scala:79:27]
reg flight_62; // @[FIFOFixer.scala:79:27]
reg flight_63; // @[FIFOFixer.scala:79:27]
reg flight_64; // @[FIFOFixer.scala:79:27]
reg flight_65; // @[FIFOFixer.scala:79:27]
reg flight_66; // @[FIFOFixer.scala:79:27]
reg flight_67; // @[FIFOFixer.scala:79:27]
reg flight_68; // @[FIFOFixer.scala:79:27]
reg flight_69; // @[FIFOFixer.scala:79:27]
reg flight_70; // @[FIFOFixer.scala:79:27]
reg flight_71; // @[FIFOFixer.scala:79:27]
reg flight_72; // @[FIFOFixer.scala:79:27]
reg flight_73; // @[FIFOFixer.scala:79:27]
reg flight_74; // @[FIFOFixer.scala:79:27]
reg flight_75; // @[FIFOFixer.scala:79:27]
reg flight_76; // @[FIFOFixer.scala:79:27]
reg flight_77; // @[FIFOFixer.scala:79:27]
reg flight_78; // @[FIFOFixer.scala:79:27]
reg flight_79; // @[FIFOFixer.scala:79:27]
reg flight_80; // @[FIFOFixer.scala:79:27]
reg flight_81; // @[FIFOFixer.scala:79:27]
reg flight_82; // @[FIFOFixer.scala:79:27]
reg flight_83; // @[FIFOFixer.scala:79:27]
reg flight_84; // @[FIFOFixer.scala:79:27]
reg flight_85; // @[FIFOFixer.scala:79:27]
reg flight_86; // @[FIFOFixer.scala:79:27]
reg flight_87; // @[FIFOFixer.scala:79:27]
reg flight_88; // @[FIFOFixer.scala:79:27]
reg flight_89; // @[FIFOFixer.scala:79:27]
reg flight_90; // @[FIFOFixer.scala:79:27]
reg flight_91; // @[FIFOFixer.scala:79:27]
reg flight_92; // @[FIFOFixer.scala:79:27]
reg flight_93; // @[FIFOFixer.scala:79:27]
reg flight_94; // @[FIFOFixer.scala:79:27]
reg flight_95; // @[FIFOFixer.scala:79:27]
reg flight_96; // @[FIFOFixer.scala:79:27]
reg flight_97; // @[FIFOFixer.scala:79:27]
reg flight_98; // @[FIFOFixer.scala:79:27]
reg flight_99; // @[FIFOFixer.scala:79:27]
reg flight_100; // @[FIFOFixer.scala:79:27]
reg flight_101; // @[FIFOFixer.scala:79:27]
reg flight_102; // @[FIFOFixer.scala:79:27]
reg flight_103; // @[FIFOFixer.scala:79:27]
reg flight_104; // @[FIFOFixer.scala:79:27]
reg flight_105; // @[FIFOFixer.scala:79:27]
reg flight_106; // @[FIFOFixer.scala:79:27]
reg flight_107; // @[FIFOFixer.scala:79:27]
reg flight_108; // @[FIFOFixer.scala:79:27]
reg flight_109; // @[FIFOFixer.scala:79:27]
reg flight_110; // @[FIFOFixer.scala:79:27]
reg flight_111; // @[FIFOFixer.scala:79:27]
reg flight_112; // @[FIFOFixer.scala:79:27]
reg flight_113; // @[FIFOFixer.scala:79:27]
reg flight_114; // @[FIFOFixer.scala:79:27]
reg flight_115; // @[FIFOFixer.scala:79:27]
reg flight_116; // @[FIFOFixer.scala:79:27]
reg flight_117; // @[FIFOFixer.scala:79:27]
reg flight_118; // @[FIFOFixer.scala:79:27]
reg flight_119; // @[FIFOFixer.scala:79:27]
reg flight_120; // @[FIFOFixer.scala:79:27]
reg flight_121; // @[FIFOFixer.scala:79:27]
reg flight_122; // @[FIFOFixer.scala:79:27]
reg flight_123; // @[FIFOFixer.scala:79:27]
reg flight_124; // @[FIFOFixer.scala:79:27]
reg flight_125; // @[FIFOFixer.scala:79:27]
reg flight_126; // @[FIFOFixer.scala:79:27]
reg flight_127; // @[FIFOFixer.scala:79:27]
reg flight_128; // @[FIFOFixer.scala:79:27]
wire _T_9 = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] stalls_a_sel_uncommonBits = _stalls_a_sel_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _stalls_a_sel_T = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10]
wire [4:0] _stalls_a_sel_T_5 = anonIn_a_bits_source[7:3]; // @[Parameters.scala:54:10]
wire _stalls_a_sel_T_1 = _stalls_a_sel_T == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_3 = _stalls_a_sel_T_1; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel = _stalls_a_sel_T_3; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_1 = _stalls_id_T & stalls_a_sel; // @[Decoupled.scala:51:35]
wire _stalls_id_T_3 = _stalls_id_T_1; // @[FIFOFixer.scala:85:{47,56}]
reg [3:0] stalls_id; // @[FIFOFixer.scala:85:30]
wire _stalls_T = stalls_a_sel & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_1 = flight_16 | flight_17; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_2 = _stalls_T_1 | flight_18; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_3 = _stalls_T_2 | flight_19; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_4 = _stalls_T_3 | flight_20; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_5 = _stalls_T_4 | flight_21; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_6 = _stalls_T_5 | flight_22; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_7 = _stalls_T_6 | flight_23; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_8 = _stalls_T & _stalls_T_7; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_9 = stalls_id != a_id; // @[Mux.scala:30:73]
wire _stalls_T_10 = a_noDomain | _stalls_T_9; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_0 = _stalls_T_8 & _stalls_T_10; // @[FIFOFixer.scala:88:{26,50,65}]
wire _stall_T = stalls_0; // @[FIFOFixer.scala:88:50, :91:45]
wire [2:0] stalls_a_sel_uncommonBits_1 = _stalls_a_sel_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _stalls_a_sel_T_6 = _stalls_a_sel_T_5 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _stalls_a_sel_T_8 = _stalls_a_sel_T_6; // @[Parameters.scala:54:{32,67}]
wire stalls_a_sel_1 = _stalls_a_sel_T_8; // @[Parameters.scala:54:67, :56:48]
wire _stalls_id_T_5 = _stalls_id_T_4 & stalls_a_sel_1; // @[Decoupled.scala:51:35]
wire _stalls_id_T_7 = _stalls_id_T_5; // @[FIFOFixer.scala:85:{47,56}]
reg [3:0] stalls_id_1; // @[FIFOFixer.scala:85:30]
wire _stalls_T_11 = stalls_a_sel_1 & a_first; // @[FIFOFixer.scala:88:15]
wire _stalls_T_12 = flight_24 | flight_25; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_13 = _stalls_T_12 | flight_26; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_14 = _stalls_T_13 | flight_27; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_15 = _stalls_T_14 | flight_28; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_16 = _stalls_T_15 | flight_29; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_17 = _stalls_T_16 | flight_30; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_18 = _stalls_T_17 | flight_31; // @[FIFOFixer.scala:79:27, :88:44]
wire _stalls_T_19 = _stalls_T_11 & _stalls_T_18; // @[FIFOFixer.scala:88:{15,26,44}]
wire _stalls_T_20 = stalls_id_1 != a_id; // @[Mux.scala:30:73]
wire _stalls_T_21 = a_noDomain | _stalls_T_20; // @[FIFOFixer.scala:63:29, :88:{65,71}]
wire stalls_1 = _stalls_T_19 & _stalls_T_21; // @[FIFOFixer.scala:88:{26,50,65}]
wire stall = _stall_T | stalls_1; // @[FIFOFixer.scala:88:50, :91:45]
wire _anonOut_a_valid_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50]
wire _anonOut_a_valid_T_1 = _anonOut_a_valid_T; // @[FIFOFixer.scala:95:{47,50}]
assign _anonOut_a_valid_T_2 = anonIn_a_valid & _anonOut_a_valid_T_1; // @[FIFOFixer.scala:95:{33,47}]
assign anonOut_a_valid = _anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire _anonIn_a_ready_T = ~stall; // @[FIFOFixer.scala:91:45, :95:50, :96:50]
wire _anonIn_a_ready_T_1 = _anonIn_a_ready_T; // @[FIFOFixer.scala:96:{47,50}]
assign _anonIn_a_ready_T_2 = anonOut_a_ready & _anonIn_a_ready_T_1; // @[FIFOFixer.scala:96:{33,47}]
assign anonIn_a_ready = _anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [128:0] SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [128:0] SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [128:0] SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [255:0] _SourceIdSet_T = 256'h1 << anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign SourceIdSet = a_first & _T_5 ? _SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [255:0] _SourceIdClear_T = 256'h1 << anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign SourceIdClear = d_first & _T_9 ? _SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [128:0] _SourceIdFIFOed_T = SourceIdFIFOed | SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire allIDs_FIFOed = &SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire _T_1 = a_first & _T_5; // @[Decoupled.scala:51:35]
wire _T_3 = d_first & _T_9; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[FIFOFixer.scala:50:9]
if (reset) begin // @[FIFOFixer.scala:50:9]
a_first_counter <= 9'h0; // @[Edges.scala:229:27]
d_first_counter <= 9'h0; // @[Edges.scala:229:27]
flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27]
flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27]
SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[FIFOFixer.scala:50:9]
if (_a_first_T) // @[Decoupled.scala:51:35]
a_first_counter <= _a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (_d_first_T) // @[Decoupled.scala:51:35]
d_first_counter <= _d_first_counter_T; // @[Edges.scala:229:27, :236:21]
flight_0 <= ~(_T_3 & anonIn_d_bits_source == 8'h0) & (_T_1 & anonIn_a_bits_source == 8'h0 | flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_1 <= ~(_T_3 & anonIn_d_bits_source == 8'h1) & (_T_1 & anonIn_a_bits_source == 8'h1 | flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_2 <= ~(_T_3 & anonIn_d_bits_source == 8'h2) & (_T_1 & anonIn_a_bits_source == 8'h2 | flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_3 <= ~(_T_3 & anonIn_d_bits_source == 8'h3) & (_T_1 & anonIn_a_bits_source == 8'h3 | flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_4 <= ~(_T_3 & anonIn_d_bits_source == 8'h4) & (_T_1 & anonIn_a_bits_source == 8'h4 | flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_5 <= ~(_T_3 & anonIn_d_bits_source == 8'h5) & (_T_1 & anonIn_a_bits_source == 8'h5 | flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_6 <= ~(_T_3 & anonIn_d_bits_source == 8'h6) & (_T_1 & anonIn_a_bits_source == 8'h6 | flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_7 <= ~(_T_3 & anonIn_d_bits_source == 8'h7) & (_T_1 & anonIn_a_bits_source == 8'h7 | flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_8 <= ~(_T_3 & anonIn_d_bits_source == 8'h8) & (_T_1 & anonIn_a_bits_source == 8'h8 | flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_9 <= ~(_T_3 & anonIn_d_bits_source == 8'h9) & (_T_1 & anonIn_a_bits_source == 8'h9 | flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_10 <= ~(_T_3 & anonIn_d_bits_source == 8'hA) & (_T_1 & anonIn_a_bits_source == 8'hA | flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_11 <= ~(_T_3 & anonIn_d_bits_source == 8'hB) & (_T_1 & anonIn_a_bits_source == 8'hB | flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_12 <= ~(_T_3 & anonIn_d_bits_source == 8'hC) & (_T_1 & anonIn_a_bits_source == 8'hC | flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_13 <= ~(_T_3 & anonIn_d_bits_source == 8'hD) & (_T_1 & anonIn_a_bits_source == 8'hD | flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_14 <= ~(_T_3 & anonIn_d_bits_source == 8'hE) & (_T_1 & anonIn_a_bits_source == 8'hE | flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_15 <= ~(_T_3 & anonIn_d_bits_source == 8'hF) & (_T_1 & anonIn_a_bits_source == 8'hF | flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_16 <= ~(_T_3 & anonIn_d_bits_source == 8'h10) & (_T_1 & anonIn_a_bits_source == 8'h10 | flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_17 <= ~(_T_3 & anonIn_d_bits_source == 8'h11) & (_T_1 & anonIn_a_bits_source == 8'h11 | flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_18 <= ~(_T_3 & anonIn_d_bits_source == 8'h12) & (_T_1 & anonIn_a_bits_source == 8'h12 | flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_19 <= ~(_T_3 & anonIn_d_bits_source == 8'h13) & (_T_1 & anonIn_a_bits_source == 8'h13 | flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_20 <= ~(_T_3 & anonIn_d_bits_source == 8'h14) & (_T_1 & anonIn_a_bits_source == 8'h14 | flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_21 <= ~(_T_3 & anonIn_d_bits_source == 8'h15) & (_T_1 & anonIn_a_bits_source == 8'h15 | flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_22 <= ~(_T_3 & anonIn_d_bits_source == 8'h16) & (_T_1 & anonIn_a_bits_source == 8'h16 | flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_23 <= ~(_T_3 & anonIn_d_bits_source == 8'h17) & (_T_1 & anonIn_a_bits_source == 8'h17 | flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_24 <= ~(_T_3 & anonIn_d_bits_source == 8'h18) & (_T_1 & anonIn_a_bits_source == 8'h18 | flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_25 <= ~(_T_3 & anonIn_d_bits_source == 8'h19) & (_T_1 & anonIn_a_bits_source == 8'h19 | flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_26 <= ~(_T_3 & anonIn_d_bits_source == 8'h1A) & (_T_1 & anonIn_a_bits_source == 8'h1A | flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_27 <= ~(_T_3 & anonIn_d_bits_source == 8'h1B) & (_T_1 & anonIn_a_bits_source == 8'h1B | flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_28 <= ~(_T_3 & anonIn_d_bits_source == 8'h1C) & (_T_1 & anonIn_a_bits_source == 8'h1C | flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_29 <= ~(_T_3 & anonIn_d_bits_source == 8'h1D) & (_T_1 & anonIn_a_bits_source == 8'h1D | flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_30 <= ~(_T_3 & anonIn_d_bits_source == 8'h1E) & (_T_1 & anonIn_a_bits_source == 8'h1E | flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_31 <= ~(_T_3 & anonIn_d_bits_source == 8'h1F) & (_T_1 & anonIn_a_bits_source == 8'h1F | flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_32 <= ~(_T_3 & anonIn_d_bits_source == 8'h20) & (_T_1 & anonIn_a_bits_source == 8'h20 | flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_33 <= ~(_T_3 & anonIn_d_bits_source == 8'h21) & (_T_1 & anonIn_a_bits_source == 8'h21 | flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_34 <= ~(_T_3 & anonIn_d_bits_source == 8'h22) & (_T_1 & anonIn_a_bits_source == 8'h22 | flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_35 <= ~(_T_3 & anonIn_d_bits_source == 8'h23) & (_T_1 & anonIn_a_bits_source == 8'h23 | flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_36 <= ~(_T_3 & anonIn_d_bits_source == 8'h24) & (_T_1 & anonIn_a_bits_source == 8'h24 | flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_37 <= ~(_T_3 & anonIn_d_bits_source == 8'h25) & (_T_1 & anonIn_a_bits_source == 8'h25 | flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_38 <= ~(_T_3 & anonIn_d_bits_source == 8'h26) & (_T_1 & anonIn_a_bits_source == 8'h26 | flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_39 <= ~(_T_3 & anonIn_d_bits_source == 8'h27) & (_T_1 & anonIn_a_bits_source == 8'h27 | flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_40 <= ~(_T_3 & anonIn_d_bits_source == 8'h28) & (_T_1 & anonIn_a_bits_source == 8'h28 | flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_41 <= ~(_T_3 & anonIn_d_bits_source == 8'h29) & (_T_1 & anonIn_a_bits_source == 8'h29 | flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_42 <= ~(_T_3 & anonIn_d_bits_source == 8'h2A) & (_T_1 & anonIn_a_bits_source == 8'h2A | flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_43 <= ~(_T_3 & anonIn_d_bits_source == 8'h2B) & (_T_1 & anonIn_a_bits_source == 8'h2B | flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_44 <= ~(_T_3 & anonIn_d_bits_source == 8'h2C) & (_T_1 & anonIn_a_bits_source == 8'h2C | flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_45 <= ~(_T_3 & anonIn_d_bits_source == 8'h2D) & (_T_1 & anonIn_a_bits_source == 8'h2D | flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_46 <= ~(_T_3 & anonIn_d_bits_source == 8'h2E) & (_T_1 & anonIn_a_bits_source == 8'h2E | flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_47 <= ~(_T_3 & anonIn_d_bits_source == 8'h2F) & (_T_1 & anonIn_a_bits_source == 8'h2F | flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_48 <= ~(_T_3 & anonIn_d_bits_source == 8'h30) & (_T_1 & anonIn_a_bits_source == 8'h30 | flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_49 <= ~(_T_3 & anonIn_d_bits_source == 8'h31) & (_T_1 & anonIn_a_bits_source == 8'h31 | flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_50 <= ~(_T_3 & anonIn_d_bits_source == 8'h32) & (_T_1 & anonIn_a_bits_source == 8'h32 | flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_51 <= ~(_T_3 & anonIn_d_bits_source == 8'h33) & (_T_1 & anonIn_a_bits_source == 8'h33 | flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_52 <= ~(_T_3 & anonIn_d_bits_source == 8'h34) & (_T_1 & anonIn_a_bits_source == 8'h34 | flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_53 <= ~(_T_3 & anonIn_d_bits_source == 8'h35) & (_T_1 & anonIn_a_bits_source == 8'h35 | flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_54 <= ~(_T_3 & anonIn_d_bits_source == 8'h36) & (_T_1 & anonIn_a_bits_source == 8'h36 | flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_55 <= ~(_T_3 & anonIn_d_bits_source == 8'h37) & (_T_1 & anonIn_a_bits_source == 8'h37 | flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_56 <= ~(_T_3 & anonIn_d_bits_source == 8'h38) & (_T_1 & anonIn_a_bits_source == 8'h38 | flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_57 <= ~(_T_3 & anonIn_d_bits_source == 8'h39) & (_T_1 & anonIn_a_bits_source == 8'h39 | flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_58 <= ~(_T_3 & anonIn_d_bits_source == 8'h3A) & (_T_1 & anonIn_a_bits_source == 8'h3A | flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_59 <= ~(_T_3 & anonIn_d_bits_source == 8'h3B) & (_T_1 & anonIn_a_bits_source == 8'h3B | flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_60 <= ~(_T_3 & anonIn_d_bits_source == 8'h3C) & (_T_1 & anonIn_a_bits_source == 8'h3C | flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_61 <= ~(_T_3 & anonIn_d_bits_source == 8'h3D) & (_T_1 & anonIn_a_bits_source == 8'h3D | flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_62 <= ~(_T_3 & anonIn_d_bits_source == 8'h3E) & (_T_1 & anonIn_a_bits_source == 8'h3E | flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_63 <= ~(_T_3 & anonIn_d_bits_source == 8'h3F) & (_T_1 & anonIn_a_bits_source == 8'h3F | flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_64 <= ~(_T_3 & anonIn_d_bits_source == 8'h40) & (_T_1 & anonIn_a_bits_source == 8'h40 | flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_65 <= ~(_T_3 & anonIn_d_bits_source == 8'h41) & (_T_1 & anonIn_a_bits_source == 8'h41 | flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_66 <= ~(_T_3 & anonIn_d_bits_source == 8'h42) & (_T_1 & anonIn_a_bits_source == 8'h42 | flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_67 <= ~(_T_3 & anonIn_d_bits_source == 8'h43) & (_T_1 & anonIn_a_bits_source == 8'h43 | flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_68 <= ~(_T_3 & anonIn_d_bits_source == 8'h44) & (_T_1 & anonIn_a_bits_source == 8'h44 | flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_69 <= ~(_T_3 & anonIn_d_bits_source == 8'h45) & (_T_1 & anonIn_a_bits_source == 8'h45 | flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_70 <= ~(_T_3 & anonIn_d_bits_source == 8'h46) & (_T_1 & anonIn_a_bits_source == 8'h46 | flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_71 <= ~(_T_3 & anonIn_d_bits_source == 8'h47) & (_T_1 & anonIn_a_bits_source == 8'h47 | flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_72 <= ~(_T_3 & anonIn_d_bits_source == 8'h48) & (_T_1 & anonIn_a_bits_source == 8'h48 | flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_73 <= ~(_T_3 & anonIn_d_bits_source == 8'h49) & (_T_1 & anonIn_a_bits_source == 8'h49 | flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_74 <= ~(_T_3 & anonIn_d_bits_source == 8'h4A) & (_T_1 & anonIn_a_bits_source == 8'h4A | flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_75 <= ~(_T_3 & anonIn_d_bits_source == 8'h4B) & (_T_1 & anonIn_a_bits_source == 8'h4B | flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_76 <= ~(_T_3 & anonIn_d_bits_source == 8'h4C) & (_T_1 & anonIn_a_bits_source == 8'h4C | flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_77 <= ~(_T_3 & anonIn_d_bits_source == 8'h4D) & (_T_1 & anonIn_a_bits_source == 8'h4D | flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_78 <= ~(_T_3 & anonIn_d_bits_source == 8'h4E) & (_T_1 & anonIn_a_bits_source == 8'h4E | flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_79 <= ~(_T_3 & anonIn_d_bits_source == 8'h4F) & (_T_1 & anonIn_a_bits_source == 8'h4F | flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_80 <= ~(_T_3 & anonIn_d_bits_source == 8'h50) & (_T_1 & anonIn_a_bits_source == 8'h50 | flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_81 <= ~(_T_3 & anonIn_d_bits_source == 8'h51) & (_T_1 & anonIn_a_bits_source == 8'h51 | flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_82 <= ~(_T_3 & anonIn_d_bits_source == 8'h52) & (_T_1 & anonIn_a_bits_source == 8'h52 | flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_83 <= ~(_T_3 & anonIn_d_bits_source == 8'h53) & (_T_1 & anonIn_a_bits_source == 8'h53 | flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_84 <= ~(_T_3 & anonIn_d_bits_source == 8'h54) & (_T_1 & anonIn_a_bits_source == 8'h54 | flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_85 <= ~(_T_3 & anonIn_d_bits_source == 8'h55) & (_T_1 & anonIn_a_bits_source == 8'h55 | flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_86 <= ~(_T_3 & anonIn_d_bits_source == 8'h56) & (_T_1 & anonIn_a_bits_source == 8'h56 | flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_87 <= ~(_T_3 & anonIn_d_bits_source == 8'h57) & (_T_1 & anonIn_a_bits_source == 8'h57 | flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_88 <= ~(_T_3 & anonIn_d_bits_source == 8'h58) & (_T_1 & anonIn_a_bits_source == 8'h58 | flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_89 <= ~(_T_3 & anonIn_d_bits_source == 8'h59) & (_T_1 & anonIn_a_bits_source == 8'h59 | flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_90 <= ~(_T_3 & anonIn_d_bits_source == 8'h5A) & (_T_1 & anonIn_a_bits_source == 8'h5A | flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_91 <= ~(_T_3 & anonIn_d_bits_source == 8'h5B) & (_T_1 & anonIn_a_bits_source == 8'h5B | flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_92 <= ~(_T_3 & anonIn_d_bits_source == 8'h5C) & (_T_1 & anonIn_a_bits_source == 8'h5C | flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_93 <= ~(_T_3 & anonIn_d_bits_source == 8'h5D) & (_T_1 & anonIn_a_bits_source == 8'h5D | flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_94 <= ~(_T_3 & anonIn_d_bits_source == 8'h5E) & (_T_1 & anonIn_a_bits_source == 8'h5E | flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_95 <= ~(_T_3 & anonIn_d_bits_source == 8'h5F) & (_T_1 & anonIn_a_bits_source == 8'h5F | flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_96 <= ~(_T_3 & anonIn_d_bits_source == 8'h60) & (_T_1 & anonIn_a_bits_source == 8'h60 | flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_97 <= ~(_T_3 & anonIn_d_bits_source == 8'h61) & (_T_1 & anonIn_a_bits_source == 8'h61 | flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_98 <= ~(_T_3 & anonIn_d_bits_source == 8'h62) & (_T_1 & anonIn_a_bits_source == 8'h62 | flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_99 <= ~(_T_3 & anonIn_d_bits_source == 8'h63) & (_T_1 & anonIn_a_bits_source == 8'h63 | flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_100 <= ~(_T_3 & anonIn_d_bits_source == 8'h64) & (_T_1 & anonIn_a_bits_source == 8'h64 | flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_101 <= ~(_T_3 & anonIn_d_bits_source == 8'h65) & (_T_1 & anonIn_a_bits_source == 8'h65 | flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_102 <= ~(_T_3 & anonIn_d_bits_source == 8'h66) & (_T_1 & anonIn_a_bits_source == 8'h66 | flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_103 <= ~(_T_3 & anonIn_d_bits_source == 8'h67) & (_T_1 & anonIn_a_bits_source == 8'h67 | flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_104 <= ~(_T_3 & anonIn_d_bits_source == 8'h68) & (_T_1 & anonIn_a_bits_source == 8'h68 | flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_105 <= ~(_T_3 & anonIn_d_bits_source == 8'h69) & (_T_1 & anonIn_a_bits_source == 8'h69 | flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_106 <= ~(_T_3 & anonIn_d_bits_source == 8'h6A) & (_T_1 & anonIn_a_bits_source == 8'h6A | flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_107 <= ~(_T_3 & anonIn_d_bits_source == 8'h6B) & (_T_1 & anonIn_a_bits_source == 8'h6B | flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_108 <= ~(_T_3 & anonIn_d_bits_source == 8'h6C) & (_T_1 & anonIn_a_bits_source == 8'h6C | flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_109 <= ~(_T_3 & anonIn_d_bits_source == 8'h6D) & (_T_1 & anonIn_a_bits_source == 8'h6D | flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_110 <= ~(_T_3 & anonIn_d_bits_source == 8'h6E) & (_T_1 & anonIn_a_bits_source == 8'h6E | flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_111 <= ~(_T_3 & anonIn_d_bits_source == 8'h6F) & (_T_1 & anonIn_a_bits_source == 8'h6F | flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_112 <= ~(_T_3 & anonIn_d_bits_source == 8'h70) & (_T_1 & anonIn_a_bits_source == 8'h70 | flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_113 <= ~(_T_3 & anonIn_d_bits_source == 8'h71) & (_T_1 & anonIn_a_bits_source == 8'h71 | flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_114 <= ~(_T_3 & anonIn_d_bits_source == 8'h72) & (_T_1 & anonIn_a_bits_source == 8'h72 | flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_115 <= ~(_T_3 & anonIn_d_bits_source == 8'h73) & (_T_1 & anonIn_a_bits_source == 8'h73 | flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_116 <= ~(_T_3 & anonIn_d_bits_source == 8'h74) & (_T_1 & anonIn_a_bits_source == 8'h74 | flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_117 <= ~(_T_3 & anonIn_d_bits_source == 8'h75) & (_T_1 & anonIn_a_bits_source == 8'h75 | flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_118 <= ~(_T_3 & anonIn_d_bits_source == 8'h76) & (_T_1 & anonIn_a_bits_source == 8'h76 | flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_119 <= ~(_T_3 & anonIn_d_bits_source == 8'h77) & (_T_1 & anonIn_a_bits_source == 8'h77 | flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_120 <= ~(_T_3 & anonIn_d_bits_source == 8'h78) & (_T_1 & anonIn_a_bits_source == 8'h78 | flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_121 <= ~(_T_3 & anonIn_d_bits_source == 8'h79) & (_T_1 & anonIn_a_bits_source == 8'h79 | flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_122 <= ~(_T_3 & anonIn_d_bits_source == 8'h7A) & (_T_1 & anonIn_a_bits_source == 8'h7A | flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_123 <= ~(_T_3 & anonIn_d_bits_source == 8'h7B) & (_T_1 & anonIn_a_bits_source == 8'h7B | flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_124 <= ~(_T_3 & anonIn_d_bits_source == 8'h7C) & (_T_1 & anonIn_a_bits_source == 8'h7C | flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_125 <= ~(_T_3 & anonIn_d_bits_source == 8'h7D) & (_T_1 & anonIn_a_bits_source == 8'h7D | flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_126 <= ~(_T_3 & anonIn_d_bits_source == 8'h7E) & (_T_1 & anonIn_a_bits_source == 8'h7E | flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_127 <= ~(_T_3 & anonIn_d_bits_source == 8'h7F) & (_T_1 & anonIn_a_bits_source == 8'h7F | flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
flight_128 <= ~(_T_3 & anonIn_d_bits_source == 8'h80) & (_T_1 & anonIn_a_bits_source == 8'h80 | flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
SourceIdFIFOed <= _SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
end
if (_stalls_id_T_3) // @[FIFOFixer.scala:85:56]
stalls_id <= a_id; // @[Mux.scala:30:73]
if (_stalls_id_T_7) // @[FIFOFixer.scala:85:56]
stalls_id_1 <= a_id; // @[Mux.scala:30:73]
always @(posedge)
TLMonitor_21 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[FIFOFixer.scala:50:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[FIFOFixer.scala:50:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_sbus_i2_o1_a32d32s6k1z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_1
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<1>(0h0))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.mask, UInt<4>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<32>(0h0)
connect _WIRE_4.bits.mask, UInt<4>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<6>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.mask, UInt<4>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<6>(0h20))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.mask, UInt<4>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<32>(0h0)
connect _WIRE_26.bits.mask, UInt<4>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<1>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<32>(0h0)
connect _WIRE_28.bits.mask, UInt<4>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<6>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<32>(0h0)
connect _WIRE_30.bits.mask, UInt<4>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<1>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<32>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<6>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<32>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<1>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<32>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<6>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<32>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<1>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
connect anonIn_1.d.bits.source, UInt<1>(0h0)
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<32>(0h0)
connect _WIRE_48.bits.mask, UInt<4>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<6>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<32>(0h0)
connect _WIRE_50.bits.mask, UInt<4>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<6>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<32>(0h0)
connect _WIRE_52.bits.mask, UInt<4>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<6>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<32>(0h0)
connect _WIRE_54.bits.mask, UInt<4>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<6>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<32>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<6>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<32>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<6>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<32>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<6>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<32>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<6>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<32>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<6>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<6>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<6>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h0))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<6>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node requestBOI_0_1 = eq(_requestBOI_WIRE_3.bits.source, UInt<6>(0h20))
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h0))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node requestDOI_0_1 = eq(out[0].d.bits.source, UInt<6>(0h20))
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 2)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 2)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<6>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 2)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<6>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 2)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<6>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 2)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 2)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<6>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<6>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<6>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<32>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<4>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<6>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<32>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<6>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_74.bits.sink, UInt<1>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<32>(0h0)
connect _WIRE_76.bits.mask, UInt<4>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<6>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<32>(0h0)
connect _WIRE_78.bits.mask, UInt<4>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<6>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_sbus_i2_o1_a32d32s6k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire auto_anon_in_1_d_bits_source = 1'h0; // @[Xbar.scala:74:9]
wire anonIn_1_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire requestBOI_0_1 = 1'h0; // @[Parameters.scala:46:9]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _portsBIO_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_data = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsCOI_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_0_bits_data = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsCOI_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsCOI_filtered_1_0_bits_data = 32'h0; // @[Xbar.scala:352:24]
wire [5:0] _addressC_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _addressC_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _addressC_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _addressC_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _requestBOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _requestBOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _requestBOI_uncommonBits_T = 6'h0; // @[Parameters.scala:52:29]
wire [5:0] _requestBOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _requestBOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _beatsBO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _beatsBO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] _beatsCI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _beatsCI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _beatsCI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _beatsCI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _portsBIO_WIRE_bits_source = 6'h0; // @[Bundles.scala:264:74]
wire [5:0] _portsBIO_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:264:61]
wire [5:0] portsBIO_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] portsBIO_filtered_1_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] _portsCOI_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _portsCOI_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] portsCOI_filtered_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [5:0] _portsCOI_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _portsCOI_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] portsCOI_filtered_1_0_bits_source = 6'h0; // @[Xbar.scala:352:24]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_2_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _requestBOI_WIRE_3_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsBO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _portsBIO_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_0_bits_mask = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_mask = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [9:0] beatsBO_decode = 10'h0; // @[Edges.scala:220:59]
wire [9:0] beatsBO_0 = 10'h0; // @[Edges.scala:221:14]
wire [9:0] beatsCI_decode = 10'h0; // @[Edges.scala:220:59]
wire [9:0] beatsCI_0 = 10'h0; // @[Edges.scala:221:14]
wire [9:0] beatsCI_decode_1 = 10'h0; // @[Edges.scala:220:59]
wire [9:0] beatsCI_1 = 10'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [4:0] requestBOI_uncommonBits = 5'h0; // @[Parameters.scala:52:56]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [31:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [31:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [5:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [4:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [31:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [31:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [31:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [5:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [31:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [31:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [5:0] _in_1_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [31:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [31:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [5:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign in_0_a_bits_source = {1'h0, _in_0_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[4:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign _in_1_a_bits_source_T = {5'h10, anonIn_1_a_bits_source}; // @[Xbar.scala:166:55]
assign in_1_a_bits_source = _in_1_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [5:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [4:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[4:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[5]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = ~_requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire requestDOI_0_1 = out_0_d_bits_source == 6'h20; // @[Xbar.scala:216:19]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] beatsAI_decode = _beatsAI_decode_T_2[11:2]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [9:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [9:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:2]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [9:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [9:0] beatsDO_decode = _beatsDO_decode_T_2[11:2]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [9:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 10'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_192 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_209
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_192( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_209 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_67 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_86 = shr(io.in.a.bits.source, 5)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_152 = shr(io.in.a.bits.source, 5)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_199 = shr(io.in.a.bits.source, 5)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_240 = shr(io.in.a.bits.source, 5)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_283 = shr(io.in.a.bits.source, 5)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_321 = shr(io.in.a.bits.source, 5)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_359 = shr(io.in.a.bits.source, 5)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_136
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_137
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:119)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_67( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_2 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_2( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_35 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_35( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_39 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_89 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_89( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_3 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst mulFullRaw of MulFullRawFN_3
connect mulFullRaw.io.a.sig, io.a.sig
connect mulFullRaw.io.a.sExp, io.a.sExp
connect mulFullRaw.io.a.sign, io.a.sign
connect mulFullRaw.io.a.isZero, io.a.isZero
connect mulFullRaw.io.a.isInf, io.a.isInf
connect mulFullRaw.io.a.isNaN, io.a.isNaN
connect mulFullRaw.io.b.sig, io.b.sig
connect mulFullRaw.io.b.sExp, io.b.sExp
connect mulFullRaw.io.b.sign, io.b.sign
connect mulFullRaw.io.b.isZero, io.b.isZero
connect mulFullRaw.io.b.isInf, io.b.isInf
connect mulFullRaw.io.b.isNaN, io.b.isNaN
connect io.invalidExc, mulFullRaw.io.invalidExc
connect io.rawOut, mulFullRaw.io.rawOut
node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22)
node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0)
node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1)
node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2)
connect io.rawOut.sig, _io_rawOut_sig_T_3 | module MulRawFN_3( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_3 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_71 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_71( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_111 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_31 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_295
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_296
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_31( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_294 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_295 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_296 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_83 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_167
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_83( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_167 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
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